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ARMBaseInfo.h
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1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
19 
20 #include "ARMMCTargetDesc.h"
22 #include "Utils/ARMBaseInfo.h"
23 
24 namespace llvm {
25 
26 namespace ARM_PROC {
27  enum IMod {
28  IE = 2,
29  ID = 3
30  };
31 
32  enum IFlags {
33  F = 1,
34  I = 2,
35  A = 4
36  };
37 
38  inline static const char *IFlagsToString(unsigned val) {
39  switch (val) {
40  default: llvm_unreachable("Unknown iflags operand");
41  case F: return "f";
42  case I: return "i";
43  case A: return "a";
44  }
45  }
46 
47  inline static const char *IModToString(unsigned val) {
48  switch (val) {
49  default: llvm_unreachable("Unknown imod operand");
50  case IE: return "ie";
51  case ID: return "id";
52  }
53  }
54 }
55 
56 namespace ARM_MB {
57  // The Memory Barrier Option constants map directly to the 4-bit encoding of
58  // the option field for memory barrier operations.
59  enum MemBOpt {
61  OSHLD = 1,
62  OSHST = 2,
63  OSH = 3,
65  NSHLD = 5,
66  NSHST = 6,
67  NSH = 7,
69  ISHLD = 9,
70  ISHST = 10,
71  ISH = 11,
73  LD = 13,
74  ST = 14,
75  SY = 15
76  };
77 
78  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
79  switch (val) {
80  default: llvm_unreachable("Unknown memory operation");
81  case SY: return "sy";
82  case ST: return "st";
83  case LD: return HasV8 ? "ld" : "#0xd";
84  case RESERVED_12: return "#0xc";
85  case ISH: return "ish";
86  case ISHST: return "ishst";
87  case ISHLD: return HasV8 ? "ishld" : "#0x9";
88  case RESERVED_8: return "#0x8";
89  case NSH: return "nsh";
90  case NSHST: return "nshst";
91  case NSHLD: return HasV8 ? "nshld" : "#0x5";
92  case RESERVED_4: return "#0x4";
93  case OSH: return "osh";
94  case OSHST: return "oshst";
95  case OSHLD: return HasV8 ? "oshld" : "#0x1";
96  case RESERVED_0: return "#0x0";
97  }
98  }
99 } // namespace ARM_MB
100 
101 namespace ARM_ISB {
118  SY = 15
119  };
120 
121  inline static const char *InstSyncBOptToString(unsigned val) {
122  switch (val) {
123  default:
124  llvm_unreachable("Unknown memory operation");
125  case RESERVED_0: return "#0x0";
126  case RESERVED_1: return "#0x1";
127  case RESERVED_2: return "#0x2";
128  case RESERVED_3: return "#0x3";
129  case RESERVED_4: return "#0x4";
130  case RESERVED_5: return "#0x5";
131  case RESERVED_6: return "#0x6";
132  case RESERVED_7: return "#0x7";
133  case RESERVED_8: return "#0x8";
134  case RESERVED_9: return "#0x9";
135  case RESERVED_10: return "#0xa";
136  case RESERVED_11: return "#0xb";
137  case RESERVED_12: return "#0xc";
138  case RESERVED_13: return "#0xd";
139  case RESERVED_14: return "#0xe";
140  case SY: return "sy";
141  }
142  }
143 } // namespace ARM_ISB
144 
145 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
146 ///
147 static inline bool isARMLowRegister(unsigned Reg) {
148  using namespace ARM;
149  switch (Reg) {
150  case R0: case R1: case R2: case R3:
151  case R4: case R5: case R6: case R7:
152  return true;
153  default:
154  return false;
155  }
156 }
157 
158 /// ARMII - This namespace holds all of the target specific flags that
159 /// instruction info tracks.
160 ///
161 namespace ARMII {
162 
163  /// ARM Index Modes
164  enum IndexMode {
169  };
170 
171  /// ARM Addressing Modes
172  enum AddrMode {
183  AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
187  AddrModeT2_pc = 14, // +/- i12 for pc relative data
188  AddrModeT2_i8s4 = 15, // i8 * 4
190  };
191 
192  inline static const char *AddrModeToString(AddrMode addrmode) {
193  switch (addrmode) {
194  case AddrModeNone: return "AddrModeNone";
195  case AddrMode1: return "AddrMode1";
196  case AddrMode2: return "AddrMode2";
197  case AddrMode3: return "AddrMode3";
198  case AddrMode4: return "AddrMode4";
199  case AddrMode5: return "AddrMode5";
200  case AddrMode6: return "AddrMode6";
201  case AddrModeT1_1: return "AddrModeT1_1";
202  case AddrModeT1_2: return "AddrModeT1_2";
203  case AddrModeT1_4: return "AddrModeT1_4";
204  case AddrModeT1_s: return "AddrModeT1_s";
205  case AddrModeT2_i12: return "AddrModeT2_i12";
206  case AddrModeT2_i8: return "AddrModeT2_i8";
207  case AddrModeT2_so: return "AddrModeT2_so";
208  case AddrModeT2_pc: return "AddrModeT2_pc";
209  case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
210  case AddrMode_i12: return "AddrMode_i12";
211  }
212  }
213 
214  /// Target Operand Flag enum.
215  enum TOF {
216  //===------------------------------------------------------------------===//
217  // ARM Specific MachineOperand flags.
218 
220 
221  /// MO_LO16 - On a symbol operand, this represents a relocation containing
222  /// lower 16 bit of the address. Used only via movw instruction.
223  MO_LO16 = 0x1,
224 
225  /// MO_HI16 - On a symbol operand, this represents a relocation containing
226  /// higher 16 bit of the address. Used only via movt instruction.
227  MO_HI16 = 0x2,
228 
229  /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
230  /// just that part of the flag set.
232 
233  /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
234  MO_GOT = 0x8,
235 
236  /// MO_SBREL - On a symbol operand, this represents a static base relative
237  /// relocation. Used in movw and movt instructions.
238  MO_SBREL = 0x10,
239 
240  /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
241  /// to the symbol is for an import stub. This is used for DLL import
242  /// storage class indication on Windows.
243  MO_DLLIMPORT = 0x20,
244 
245  /// MO_SECREL - On a symbol operand this indicates that the immediate is
246  /// the offset from beginning of section.
247  ///
248  /// This is the TLS offset for the COFF/Windows TLS mechanism.
249  MO_SECREL = 0x40,
250 
251  /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
252  /// represents a symbol which, if indirect, will get special Darwin mangling
253  /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
254  /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
255  /// example).
256  MO_NONLAZY = 0x80,
257 
258  // It's undefined behaviour if an enum overflows the range between its
259  // smallest and largest values, but since these are |ed together, it can
260  // happen. Put a sentinel in (values of this enum are stored as "unsigned
261  // char").
263  };
264 
265  enum {
266  //===------------------------------------------------------------------===//
267  // Instruction Flags.
268 
269  //===------------------------------------------------------------------===//
270  // This four-bit field describes the addressing mode used.
271  AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
272 
273  // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
274  // and store ops only. Generic "updating" flag is used for ld/st multiple.
275  // The index mode enums are declared in ARMBaseInfo.h
278 
279  //===------------------------------------------------------------------===//
280  // Instruction encoding formats.
281  //
283  FormMask = 0x3f << FormShift,
284 
285  // Pseudo instructions
286  Pseudo = 0 << FormShift,
287 
288  // Multiply instructions
290 
291  // Branch instructions
292  BrFrm = 2 << FormShift,
294 
295  // Data Processing instructions
296  DPFrm = 4 << FormShift,
298 
299  // Load and Store
300  LdFrm = 6 << FormShift,
301  StFrm = 7 << FormShift,
305 
307 
308  // Miscellaneous arithmetic instructions
310  SatFrm = 13 << FormShift,
311 
312  // Extend instructions
313  ExtFrm = 14 << FormShift,
314 
315  // VFP formats
326 
327  // Thumb format
329 
330  // Miscelleaneous format
332 
333  // NEON formats
350 
351  //===------------------------------------------------------------------===//
352  // Misc flags.
353 
354  // UnaryDP - Indicates this is a unary data processing instruction, i.e.
355  // it doesn't have a Rn operand.
356  UnaryDP = 1 << 13,
357 
358  // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
359  // a 16-bit Thumb instruction if certain conditions are met.
360  Xform16Bit = 1 << 14,
361 
362  // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
363  // instruction. Used by the parser to determine whether to require the 'S'
364  // suffix on the mnemonic (when not in an IT block) or preclude it (when
365  // in an IT block).
367 
368  //===------------------------------------------------------------------===//
369  // Code domain.
376 
377  //===------------------------------------------------------------------===//
378  // Field shifts - such shifts are used to set field while generating
379  // machine instructions.
380  //
381  // FIXME: This list will need adjusting/fixing as the MC code emitter
382  // takes shape and the ARMCodeEmitter.cpp bits go away.
384 
405  };
406 
407 } // end namespace ARMII
408 
409 } // end namespace llvm;
410 
411 #endif
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:243
#define R4(n)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
TOF
Target Operand Flag enum.
Definition: ARMBaseInfo.h:215
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:164
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
Definition: ARMBaseInfo.h:234
#define R2(n)
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:238
Reg
All possible values of the reg field in the ModR/M byte.
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: ARMBaseInfo.h:249
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:121
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:223
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:47
#define R6(n)
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:78
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:172
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:38
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:147
MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects just that part of the flag set...
Definition: ARMBaseInfo.h:231
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:256
static const char * AddrModeToString(AddrMode addrmode)
Definition: ARMBaseInfo.h:192
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:227