LLVM  6.0.0svn
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/Value.h"
44 #include "llvm/MC/MCRegisterInfo.h"
46 #include <cassert>
47 #include <cstdint>
48 
49 using namespace llvm;
50 
51 #include "X86GenCallingConv.inc"
52 
54  : CallLowering(&TLI) {}
55 
56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57  SmallVectorImpl<ArgInfo> &SplitArgs,
58  const DataLayout &DL,
60  SplitArgTy PerformArgSplit) const {
61  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62  LLVMContext &Context = OrigArg.Ty->getContext();
63 
64  SmallVector<EVT, 4> SplitVTs;
66  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
67 
68  if (SplitVTs.size() != 1) {
69  // TODO: support struct/array split
70  return false;
71  }
72 
73  EVT VT = SplitVTs[0];
74  unsigned NumParts = TLI.getNumRegisters(Context, VT);
75 
76  if (NumParts == 1) {
77  // replace the original type ( pointer -> GPR ).
78  SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
79  OrigArg.Flags, OrigArg.IsFixed);
80  return true;
81  }
82 
83  SmallVector<unsigned, 8> SplitRegs;
84 
85  EVT PartVT = TLI.getRegisterType(Context, VT);
86  Type *PartTy = PartVT.getTypeForEVT(Context);
87 
88  for (unsigned i = 0; i < NumParts; ++i) {
89  ArgInfo Info =
91  PartTy, OrigArg.Flags};
92  SplitArgs.push_back(Info);
93  SplitRegs.push_back(Info.Reg);
94  }
95 
96  PerformArgSplit(SplitRegs);
97  return true;
98 }
99 
100 namespace {
101 
102 struct OutgoingValueHandler : public CallLowering::ValueHandler {
103  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
104  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
105  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
106  DL(MIRBuilder.getMF().getDataLayout()),
107  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
108 
109  unsigned getStackAddress(uint64_t Size, int64_t Offset,
110  MachinePointerInfo &MPO) override {
111  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
112  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
113  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
114  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
115 
116  unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
117  MIRBuilder.buildConstant(OffsetReg, Offset);
118 
119  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
120  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
121 
122  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
123  return AddrReg;
124  }
125 
126  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
127  CCValAssign &VA) override {
128  MIB.addUse(PhysReg, RegState::Implicit);
129  unsigned ExtReg = extendRegister(ValVReg, VA);
130  MIRBuilder.buildCopy(PhysReg, ExtReg);
131  }
132 
133  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
134  MachinePointerInfo &MPO, CCValAssign &VA) override {
135  unsigned ExtReg = extendRegister(ValVReg, VA);
136  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
138  /* Alignment */ 0);
139  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
140  }
141 
142  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
143  CCValAssign::LocInfo LocInfo,
144  const CallLowering::ArgInfo &Info, CCState &State) override {
145  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
146  StackSize = State.getNextStackOffset();
147 
148  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
149  X86::XMM3, X86::XMM4, X86::XMM5,
150  X86::XMM6, X86::XMM7};
151  if (!Info.IsFixed)
152  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
153 
154  return Res;
155  }
156 
157  uint64_t getStackSize() { return StackSize; }
158  uint64_t getNumXmmRegs() { return NumXMMRegs; }
159 
160 protected:
161  MachineInstrBuilder &MIB;
162  uint64_t StackSize = 0;
163  const DataLayout &DL;
164  const X86Subtarget &STI;
165  unsigned NumXMMRegs = 0;
166 };
167 
168 } // end anonymous namespace
169 
171  const Value *Val, unsigned VReg) const {
172  assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
173 
174  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
175 
176  if (VReg) {
177  MachineFunction &MF = MIRBuilder.getMF();
178  MachineRegisterInfo &MRI = MF.getRegInfo();
179  auto &DL = MF.getDataLayout();
180  const Function &F = *MF.getFunction();
181 
182  ArgInfo OrigArg{VReg, Val->getType()};
183  setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
184 
185  SmallVector<ArgInfo, 8> SplitArgs;
186  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
187  [&](ArrayRef<unsigned> Regs) {
188  MIRBuilder.buildUnmerge(Regs, VReg);
189  }))
190  return false;
191 
192  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
193  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
194  return false;
195  }
196 
197  MIRBuilder.insertInstr(MIB);
198  return true;
199 }
200 
201 namespace {
202 
203 struct IncomingValueHandler : public CallLowering::ValueHandler {
204  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
205  CCAssignFn *AssignFn)
206  : ValueHandler(MIRBuilder, MRI, AssignFn),
207  DL(MIRBuilder.getMF().getDataLayout()) {}
208 
209  unsigned getStackAddress(uint64_t Size, int64_t Offset,
210  MachinePointerInfo &MPO) override {
211  auto &MFI = MIRBuilder.getMF().getFrameInfo();
212  int FI = MFI.CreateFixedObject(Size, Offset, true);
213  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
214 
215  unsigned AddrReg = MRI.createGenericVirtualRegister(
217  MIRBuilder.buildFrameIndex(AddrReg, FI);
218  return AddrReg;
219  }
220 
221  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
222  MachinePointerInfo &MPO, CCValAssign &VA) override {
223  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
225  0);
226  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
227  }
228 
229  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
230  CCValAssign &VA) override {
231  markPhysRegUsed(PhysReg);
232  switch (VA.getLocInfo()) {
233  default:
234  MIRBuilder.buildCopy(ValVReg, PhysReg);
235  break;
236  case CCValAssign::LocInfo::SExt:
237  case CCValAssign::LocInfo::ZExt:
238  case CCValAssign::LocInfo::AExt: {
239  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
240  MIRBuilder.buildTrunc(ValVReg, Copy);
241  break;
242  }
243  }
244  }
245 
246  /// How the physical register gets marked varies between formal
247  /// parameters (it's a basic-block live-in), and a call instruction
248  /// (it's an implicit-def of the BL).
249  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
250 
251 protected:
252  const DataLayout &DL;
253 };
254 
255 struct FormalArgHandler : public IncomingValueHandler {
256  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
257  CCAssignFn *AssignFn)
258  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
259 
260  void markPhysRegUsed(unsigned PhysReg) override {
261  MIRBuilder.getMBB().addLiveIn(PhysReg);
262  }
263 };
264 
265 struct CallReturnHandler : public IncomingValueHandler {
266  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
267  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
268  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
269 
270  void markPhysRegUsed(unsigned PhysReg) override {
271  MIB.addDef(PhysReg, RegState::Implicit);
272  }
273 
274 protected:
275  MachineInstrBuilder &MIB;
276 };
277 
278 } // end anonymous namespace
279 
281  const Function &F,
282  ArrayRef<unsigned> VRegs) const {
283  if (F.arg_empty())
284  return true;
285 
286  // TODO: handle variadic function
287  if (F.isVarArg())
288  return false;
289 
290  MachineFunction &MF = MIRBuilder.getMF();
291  MachineRegisterInfo &MRI = MF.getRegInfo();
292  auto DL = MF.getDataLayout();
293 
294  SmallVector<ArgInfo, 8> SplitArgs;
295  unsigned Idx = 0;
296  for (auto &Arg : F.args()) {
297 
298  // TODO: handle not simple cases.
299  if (Arg.hasAttribute(Attribute::ByVal) ||
300  Arg.hasAttribute(Attribute::InReg) ||
301  Arg.hasAttribute(Attribute::StructRet) ||
302  Arg.hasAttribute(Attribute::SwiftSelf) ||
303  Arg.hasAttribute(Attribute::SwiftError) ||
304  Arg.hasAttribute(Attribute::Nest))
305  return false;
306 
307  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
308  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
309  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
310  [&](ArrayRef<unsigned> Regs) {
311  MIRBuilder.buildMerge(VRegs[Idx], Regs);
312  }))
313  return false;
314  Idx++;
315  }
316 
317  MachineBasicBlock &MBB = MIRBuilder.getMBB();
318  if (!MBB.empty())
319  MIRBuilder.setInstr(*MBB.begin());
320 
321  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
322  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
323  return false;
324 
325  // Move back to the end of the basic block.
326  MIRBuilder.setMBB(MBB);
327 
328  return true;
329 }
330 
332  CallingConv::ID CallConv,
333  const MachineOperand &Callee,
334  const ArgInfo &OrigRet,
335  ArrayRef<ArgInfo> OrigArgs) const {
336  MachineFunction &MF = MIRBuilder.getMF();
337  const Function &F = *MF.getFunction();
338  MachineRegisterInfo &MRI = MF.getRegInfo();
339  auto &DL = F.getParent()->getDataLayout();
340  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
341  const TargetInstrInfo &TII = *STI.getInstrInfo();
342  auto TRI = STI.getRegisterInfo();
343 
344  // Handle only Linux C, X86_64_SysV calling conventions for now.
345  if (!STI.isTargetLinux() ||
346  !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
347  return false;
348 
349  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
350  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
351 
352  // Create a temporarily-floating call instruction so we can add the implicit
353  // uses of arg registers.
354  bool Is64Bit = STI.is64Bit();
355  unsigned CallOpc = Callee.isReg()
356  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
357  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
358 
359  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
360  TRI->getCallPreservedMask(MF, CallConv));
361 
362  SmallVector<ArgInfo, 8> SplitArgs;
363  for (const auto &OrigArg : OrigArgs) {
364 
365  // TODO: handle not simple cases.
366  if (OrigArg.Flags.isByVal())
367  return false;
368 
369  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
370  [&](ArrayRef<unsigned> Regs) {
371  MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
372  }))
373  return false;
374  }
375  // Do the actual argument marshalling.
376  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
377  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
378  return false;
379 
380  bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
381  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
382  // From AMD64 ABI document:
383  // For calls that may call functions that use varargs or stdargs
384  // (prototype-less calls or calls to functions containing ellipsis (...) in
385  // the declaration) %al is used as hidden argument to specify the number
386  // of SSE registers used. The contents of %al do not need to match exactly
387  // the number of registers, but must be an ubound on the number of SSE
388  // registers used and is in the range 0 - 8 inclusive.
389 
390  MIRBuilder.buildInstr(X86::MOV8ri)
391  .addDef(X86::AL)
392  .addImm(Handler.getNumXmmRegs());
394  }
395 
396  // Now we can add the actual call instruction to the correct basic block.
397  MIRBuilder.insertInstr(MIB);
398 
399  // If Callee is a reg, since it is used by a target specific
400  // instruction, it must have a register class matching the
401  // constraint of that instruction.
402  if (Callee.isReg())
404  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
405  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(),
406  Callee.getReg(), 0));
407 
408  // Finally we can copy the returned value back into its virtual-register. In
409  // symmetry with the arguments, the physical register must be an
410  // implicit-define of the call instruction.
411 
412  if (OrigRet.Reg) {
413  SplitArgs.clear();
414  SmallVector<unsigned, 8> NewRegs;
415 
416  if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
417  [&](ArrayRef<unsigned> Regs) {
418  NewRegs.assign(Regs.begin(), Regs.end());
419  }))
420  return false;
421 
422  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
423  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
424  return false;
425 
426  if (!NewRegs.empty())
427  MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
428  }
429 
430  CallSeqStart.addImm(Handler.getStackSize())
431  .addImm(0 /* see getFrameTotalSize */)
432  .addImm(0 /* see getFrameAdjustment */);
433 
434  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
435  MIRBuilder.buildInstr(AdjStackUp)
436  .addImm(Handler.getStackSize())
437  .addImm(0 /* NumBytesForCalleeToPop */);
438 
439  return true;
440 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:158
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:425
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
LLVMContext & Context
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res<def> = G_GEP Op0, Op1.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:383
unsigned getReg() const
getReg - Returns the register number.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:935
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
static const MCPhysReg VRegs[32]
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:344
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res<def> = G_TRUNC Op.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
F(f)
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
const HexagonInstrInfo * TII
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:427
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool arg_empty() const
Definition: Function.h:631
const RegList & Regs
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
MachineFunction & getMF()
Getter for the function we currently build.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
amdgpu Simplify well known AMD library false Value * Callee
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:85
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, unsigned VReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Callback) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Extended Value Type.
Definition: ValueTypes.h:34
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:61
This class contains a discriminated union of information about pointers in memory operands...
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res<def> = G_FRAME_INDEX Idx.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:393
CCState - This class holds information needed while lowering arguments and return values...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res<def> = COPY Op.
CCValAssign - Represent assignment of one arg/retval to a location.
iterator end() const
Definition: ArrayRef.h:138
This file declares the MachineIRBuilder class.
This file describes how to lower LLVM calls to machine code calls.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Basic Alias true
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:656
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
The memory access always returns the same value (or traps).
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstrBuilder buildUnmerge(ArrayRef< unsigned > Res, unsigned Op)
Build and insert Res0<def>, ...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
bool isTargetLinux() const
Definition: X86Subtarget.h:571
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:622
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res<def> = G_LOAD Addr, MMO.
X86CallLowering(const X86TargetLowering &TLI)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res<def> = G_MERGE_VALUES Op0, ...
iterator_range< arg_iterator > args()
Definition: Function.h:621