LLVM  8.0.0svn
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/MC/MCRegisterInfo.h"
46 #include <cassert>
47 #include <cstdint>
48 
49 using namespace llvm;
50 
51 #include "X86GenCallingConv.inc"
52 
54  : CallLowering(&TLI) {}
55 
56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57  SmallVectorImpl<ArgInfo> &SplitArgs,
58  const DataLayout &DL,
60  SplitArgTy PerformArgSplit) const {
61  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62  LLVMContext &Context = OrigArg.Ty->getContext();
63 
64  SmallVector<EVT, 4> SplitVTs;
66  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
67 
68  if (OrigArg.Ty->isVoidTy())
69  return true;
70 
71  EVT VT = SplitVTs[0];
72  unsigned NumParts = TLI.getNumRegisters(Context, VT);
73 
74  if (NumParts == 1) {
75  // replace the original type ( pointer -> GPR ).
76  SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
77  OrigArg.Flags, OrigArg.IsFixed);
78  return true;
79  }
80 
81  SmallVector<unsigned, 8> SplitRegs;
82 
83  EVT PartVT = TLI.getRegisterType(Context, VT);
84  Type *PartTy = PartVT.getTypeForEVT(Context);
85 
86  for (unsigned i = 0; i < NumParts; ++i) {
87  ArgInfo Info =
89  PartTy, OrigArg.Flags};
90  SplitArgs.push_back(Info);
91  SplitRegs.push_back(Info.Reg);
92  }
93 
94  PerformArgSplit(SplitRegs);
95  return true;
96 }
97 
98 namespace {
99 
100 struct OutgoingValueHandler : public CallLowering::ValueHandler {
101  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
102  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
103  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
104  DL(MIRBuilder.getMF().getDataLayout()),
105  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
106 
107  unsigned getStackAddress(uint64_t Size, int64_t Offset,
108  MachinePointerInfo &MPO) override {
109  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
110  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
111  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
112  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
113 
114  unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
115  MIRBuilder.buildConstant(OffsetReg, Offset);
116 
117  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
118  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
119 
120  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
121  return AddrReg;
122  }
123 
124  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
125  CCValAssign &VA) override {
126  MIB.addUse(PhysReg, RegState::Implicit);
127 
128  unsigned ExtReg;
129  // If we are copying the value to a physical register with the
130  // size larger than the size of the value itself - build AnyExt
131  // to the size of the register first and only then do the copy.
132  // The example of that would be copying from s32 to xmm0, for which
133  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
134  // we expect normal extendRegister mechanism to work.
135  unsigned PhysRegSize =
136  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
137  unsigned ValSize = VA.getValVT().getSizeInBits();
138  unsigned LocSize = VA.getLocVT().getSizeInBits();
139  if (PhysRegSize > ValSize && LocSize == ValSize) {
140  assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
141  auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
142  ExtReg = MIB->getOperand(0).getReg();
143  } else
144  ExtReg = extendRegister(ValVReg, VA);
145 
146  MIRBuilder.buildCopy(PhysReg, ExtReg);
147  }
148 
149  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
150  MachinePointerInfo &MPO, CCValAssign &VA) override {
151  unsigned ExtReg = extendRegister(ValVReg, VA);
152  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
154  /* Alignment */ 0);
155  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
156  }
157 
158  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
159  CCValAssign::LocInfo LocInfo,
160  const CallLowering::ArgInfo &Info, CCState &State) override {
161  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
162  StackSize = State.getNextStackOffset();
163 
164  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
165  X86::XMM3, X86::XMM4, X86::XMM5,
166  X86::XMM6, X86::XMM7};
167  if (!Info.IsFixed)
168  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
169 
170  return Res;
171  }
172 
173  uint64_t getStackSize() { return StackSize; }
174  uint64_t getNumXmmRegs() { return NumXMMRegs; }
175 
176 protected:
177  MachineInstrBuilder &MIB;
178  uint64_t StackSize = 0;
179  const DataLayout &DL;
180  const X86Subtarget &STI;
181  unsigned NumXMMRegs = 0;
182 };
183 
184 } // end anonymous namespace
185 
187  MachineIRBuilder &MIRBuilder, const Value *Val,
188  ArrayRef<unsigned> VRegs) const {
189  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
190  "Return value without a vreg");
191  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
192 
193  if (!VRegs.empty()) {
194  MachineFunction &MF = MIRBuilder.getMF();
195  const Function &F = MF.getFunction();
196  MachineRegisterInfo &MRI = MF.getRegInfo();
197  auto &DL = MF.getDataLayout();
198  LLVMContext &Ctx = Val->getType()->getContext();
199  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
200 
201  SmallVector<EVT, 4> SplitEVTs;
202  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
203  assert(VRegs.size() == SplitEVTs.size() &&
204  "For each split Type there should be exactly one VReg.");
205 
206  SmallVector<ArgInfo, 8> SplitArgs;
207  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
208  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
209  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
210  if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
211  [&](ArrayRef<unsigned> Regs) {
212  MIRBuilder.buildUnmerge(Regs, VRegs[i]);
213  }))
214  return false;
215  }
216 
217  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
218  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
219  return false;
220  }
221 
222  MIRBuilder.insertInstr(MIB);
223  return true;
224 }
225 
226 namespace {
227 
228 struct IncomingValueHandler : public CallLowering::ValueHandler {
229  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
230  CCAssignFn *AssignFn)
231  : ValueHandler(MIRBuilder, MRI, AssignFn),
232  DL(MIRBuilder.getMF().getDataLayout()) {}
233 
234  unsigned getStackAddress(uint64_t Size, int64_t Offset,
235  MachinePointerInfo &MPO) override {
236  auto &MFI = MIRBuilder.getMF().getFrameInfo();
237  int FI = MFI.CreateFixedObject(Size, Offset, true);
238  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
239 
240  unsigned AddrReg = MRI.createGenericVirtualRegister(
242  MIRBuilder.buildFrameIndex(AddrReg, FI);
243  return AddrReg;
244  }
245 
246  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
247  MachinePointerInfo &MPO, CCValAssign &VA) override {
248  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
250  0);
251  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
252  }
253 
254  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
255  CCValAssign &VA) override {
256  markPhysRegUsed(PhysReg);
257 
258  switch (VA.getLocInfo()) {
259  default: {
260  // If we are copying the value from a physical register with the
261  // size larger than the size of the value itself - build the copy
262  // of the phys reg first and then build the truncation of that copy.
263  // The example of that would be copying from xmm0 to s32, for which
264  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
265  // we expect this to be handled in SExt/ZExt/AExt case.
266  unsigned PhysRegSize =
267  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
268  unsigned ValSize = VA.getValVT().getSizeInBits();
269  unsigned LocSize = VA.getLocVT().getSizeInBits();
270  if (PhysRegSize > ValSize && LocSize == ValSize) {
271  auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
272  MIRBuilder.buildTrunc(ValVReg, Copy);
273  return;
274  }
275 
276  MIRBuilder.buildCopy(ValVReg, PhysReg);
277  break;
278  }
279  case CCValAssign::LocInfo::SExt:
280  case CCValAssign::LocInfo::ZExt:
281  case CCValAssign::LocInfo::AExt: {
282  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
283  MIRBuilder.buildTrunc(ValVReg, Copy);
284  break;
285  }
286  }
287  }
288 
289  /// How the physical register gets marked varies between formal
290  /// parameters (it's a basic-block live-in), and a call instruction
291  /// (it's an implicit-def of the BL).
292  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
293 
294 protected:
295  const DataLayout &DL;
296 };
297 
298 struct FormalArgHandler : public IncomingValueHandler {
299  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
300  CCAssignFn *AssignFn)
301  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
302 
303  void markPhysRegUsed(unsigned PhysReg) override {
304  MIRBuilder.getMBB().addLiveIn(PhysReg);
305  }
306 };
307 
308 struct CallReturnHandler : public IncomingValueHandler {
309  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
310  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
311  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
312 
313  void markPhysRegUsed(unsigned PhysReg) override {
314  MIB.addDef(PhysReg, RegState::Implicit);
315  }
316 
317 protected:
318  MachineInstrBuilder &MIB;
319 };
320 
321 } // end anonymous namespace
322 
324  const Function &F,
325  ArrayRef<unsigned> VRegs) const {
326  if (F.arg_empty())
327  return true;
328 
329  // TODO: handle variadic function
330  if (F.isVarArg())
331  return false;
332 
333  MachineFunction &MF = MIRBuilder.getMF();
334  MachineRegisterInfo &MRI = MF.getRegInfo();
335  auto DL = MF.getDataLayout();
336 
337  SmallVector<ArgInfo, 8> SplitArgs;
338  unsigned Idx = 0;
339  for (auto &Arg : F.args()) {
340 
341  // TODO: handle not simple cases.
342  if (Arg.hasAttribute(Attribute::ByVal) ||
343  Arg.hasAttribute(Attribute::InReg) ||
344  Arg.hasAttribute(Attribute::StructRet) ||
345  Arg.hasAttribute(Attribute::SwiftSelf) ||
346  Arg.hasAttribute(Attribute::SwiftError) ||
347  Arg.hasAttribute(Attribute::Nest))
348  return false;
349 
350  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
351  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
352  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
353  [&](ArrayRef<unsigned> Regs) {
354  MIRBuilder.buildMerge(VRegs[Idx], Regs);
355  }))
356  return false;
357  Idx++;
358  }
359 
360  MachineBasicBlock &MBB = MIRBuilder.getMBB();
361  if (!MBB.empty())
362  MIRBuilder.setInstr(*MBB.begin());
363 
364  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
365  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
366  return false;
367 
368  // Move back to the end of the basic block.
369  MIRBuilder.setMBB(MBB);
370 
371  return true;
372 }
373 
375  CallingConv::ID CallConv,
376  const MachineOperand &Callee,
377  const ArgInfo &OrigRet,
378  ArrayRef<ArgInfo> OrigArgs) const {
379  MachineFunction &MF = MIRBuilder.getMF();
380  const Function &F = MF.getFunction();
381  MachineRegisterInfo &MRI = MF.getRegInfo();
382  auto &DL = F.getParent()->getDataLayout();
383  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
384  const TargetInstrInfo &TII = *STI.getInstrInfo();
385  auto TRI = STI.getRegisterInfo();
386 
387  // Handle only Linux C, X86_64_SysV calling conventions for now.
388  if (!STI.isTargetLinux() ||
389  !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
390  return false;
391 
392  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
393  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
394 
395  // Create a temporarily-floating call instruction so we can add the implicit
396  // uses of arg registers.
397  bool Is64Bit = STI.is64Bit();
398  unsigned CallOpc = Callee.isReg()
399  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
400  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
401 
402  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
403  TRI->getCallPreservedMask(MF, CallConv));
404 
405  SmallVector<ArgInfo, 8> SplitArgs;
406  for (const auto &OrigArg : OrigArgs) {
407 
408  // TODO: handle not simple cases.
409  if (OrigArg.Flags.isByVal())
410  return false;
411 
412  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
413  [&](ArrayRef<unsigned> Regs) {
414  MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
415  }))
416  return false;
417  }
418  // Do the actual argument marshalling.
419  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
420  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
421  return false;
422 
423  bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
424  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
425  // From AMD64 ABI document:
426  // For calls that may call functions that use varargs or stdargs
427  // (prototype-less calls or calls to functions containing ellipsis (...) in
428  // the declaration) %al is used as hidden argument to specify the number
429  // of SSE registers used. The contents of %al do not need to match exactly
430  // the number of registers, but must be an ubound on the number of SSE
431  // registers used and is in the range 0 - 8 inclusive.
432 
433  MIRBuilder.buildInstr(X86::MOV8ri)
434  .addDef(X86::AL)
435  .addImm(Handler.getNumXmmRegs());
437  }
438 
439  // Now we can add the actual call instruction to the correct basic block.
440  MIRBuilder.insertInstr(MIB);
441 
442  // If Callee is a reg, since it is used by a target specific
443  // instruction, it must have a register class matching the
444  // constraint of that instruction.
445  if (Callee.isReg())
447  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
448  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
449 
450  // Finally we can copy the returned value back into its virtual-register. In
451  // symmetry with the arguments, the physical register must be an
452  // implicit-define of the call instruction.
453 
454  if (OrigRet.Reg) {
455  SplitArgs.clear();
456  SmallVector<unsigned, 8> NewRegs;
457 
458  if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
459  [&](ArrayRef<unsigned> Regs) {
460  NewRegs.assign(Regs.begin(), Regs.end());
461  }))
462  return false;
463 
464  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
465  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
466  return false;
467 
468  if (!NewRegs.empty())
469  MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
470  }
471 
472  CallSeqStart.addImm(Handler.getStackSize())
473  .addImm(0 /* see getFrameTotalSize */)
474  .addImm(0 /* see getFrameAdjustment */);
475 
476  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
477  MIRBuilder.buildInstr(AdjStackUp)
478  .addImm(Handler.getStackSize())
479  .addImm(0 /* NumBytesForCalleeToPop */);
480 
481  return true;
482 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:177
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:516
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
iterator begin() const
Definition: ArrayRef.h:137
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:475
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildUnmerge(ArrayRef< unsigned > Res, unsigned Op)
Build and insert Res0, ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:954
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
static const MCPhysReg VRegs[32]
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op)
Build and insert Res = G_ANYEXT Op0.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
block Block Frequency true
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:364
const HexagonInstrInfo * TII
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
unsigned getSizeInBits() const
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:423
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
bool arg_empty() const
Definition: Function.h:699
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
amdgpu Simplify well known AMD library false Value * Callee
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Extended Value Type.
Definition: ValueTypes.h:34
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:61
This class contains a discriminated union of information about pointers in memory operands...
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:485
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
CCState - This class holds information needed while lowering arguments and return values...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
CCValAssign - Represent assignment of one arg/retval to a location.
iterator end() const
Definition: ArrayRef.h:138
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_TRUNC Op.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
void setReg(unsigned Reg)
Change the register this operand corresponds to.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
The memory access always returns the same value (or traps).
MachineFunction & getMF()
Getter for the function we currently build.
uint32_t Size
Definition: Profile.cpp:47
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
bool isTargetLinux() const
Definition: X86Subtarget.h:723
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:774
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
X86CallLowering(const X86TargetLowering &TLI)
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:47
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
iterator_range< arg_iterator > args()
Definition: Function.h:689
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144