LLVM  7.0.0svn
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/MC/MCRegisterInfo.h"
46 #include <cassert>
47 #include <cstdint>
48 
49 using namespace llvm;
50 
51 #include "X86GenCallingConv.inc"
52 
54  : CallLowering(&TLI) {}
55 
56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57  SmallVectorImpl<ArgInfo> &SplitArgs,
58  const DataLayout &DL,
60  SplitArgTy PerformArgSplit) const {
61  const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62  LLVMContext &Context = OrigArg.Ty->getContext();
63 
64  SmallVector<EVT, 4> SplitVTs;
66  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
67 
68  if (SplitVTs.size() != 1) {
69  // TODO: support struct/array split
70  return false;
71  }
72 
73  EVT VT = SplitVTs[0];
74  unsigned NumParts = TLI.getNumRegisters(Context, VT);
75 
76  if (NumParts == 1) {
77  // replace the original type ( pointer -> GPR ).
78  SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
79  OrigArg.Flags, OrigArg.IsFixed);
80  return true;
81  }
82 
83  SmallVector<unsigned, 8> SplitRegs;
84 
85  EVT PartVT = TLI.getRegisterType(Context, VT);
86  Type *PartTy = PartVT.getTypeForEVT(Context);
87 
88  for (unsigned i = 0; i < NumParts; ++i) {
89  ArgInfo Info =
91  PartTy, OrigArg.Flags};
92  SplitArgs.push_back(Info);
93  SplitRegs.push_back(Info.Reg);
94  }
95 
96  PerformArgSplit(SplitRegs);
97  return true;
98 }
99 
100 namespace {
101 
102 struct OutgoingValueHandler : public CallLowering::ValueHandler {
103  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
104  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
105  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
106  DL(MIRBuilder.getMF().getDataLayout()),
107  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
108 
109  unsigned getStackAddress(uint64_t Size, int64_t Offset,
110  MachinePointerInfo &MPO) override {
111  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
112  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
113  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
114  MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
115 
116  unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
117  MIRBuilder.buildConstant(OffsetReg, Offset);
118 
119  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
120  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
121 
122  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
123  return AddrReg;
124  }
125 
126  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
127  CCValAssign &VA) override {
128  MIB.addUse(PhysReg, RegState::Implicit);
129 
130  unsigned ExtReg;
131  // If we are copying the value to a physical register with the
132  // size larger than the size of the value itself - build AnyExt
133  // to the size of the register first and only then do the copy.
134  // The example of that would be copying from s32 to xmm0, for which
135  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
136  // we expect normal extendRegister mechanism to work.
137  unsigned PhysRegSize =
138  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
139  unsigned ValSize = VA.getValVT().getSizeInBits();
140  unsigned LocSize = VA.getLocVT().getSizeInBits();
141  if (PhysRegSize > ValSize && LocSize == ValSize) {
142  assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
143  auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
144  ExtReg = MIB->getOperand(0).getReg();
145  } else
146  ExtReg = extendRegister(ValVReg, VA);
147 
148  MIRBuilder.buildCopy(PhysReg, ExtReg);
149  }
150 
151  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
152  MachinePointerInfo &MPO, CCValAssign &VA) override {
153  unsigned ExtReg = extendRegister(ValVReg, VA);
154  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
156  /* Alignment */ 0);
157  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
158  }
159 
160  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
161  CCValAssign::LocInfo LocInfo,
162  const CallLowering::ArgInfo &Info, CCState &State) override {
163  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
164  StackSize = State.getNextStackOffset();
165 
166  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
167  X86::XMM3, X86::XMM4, X86::XMM5,
168  X86::XMM6, X86::XMM7};
169  if (!Info.IsFixed)
170  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
171 
172  return Res;
173  }
174 
175  uint64_t getStackSize() { return StackSize; }
176  uint64_t getNumXmmRegs() { return NumXMMRegs; }
177 
178 protected:
179  MachineInstrBuilder &MIB;
180  uint64_t StackSize = 0;
181  const DataLayout &DL;
182  const X86Subtarget &STI;
183  unsigned NumXMMRegs = 0;
184 };
185 
186 } // end anonymous namespace
187 
189  const Value *Val, unsigned VReg) const {
190  assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
191 
192  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
193 
194  if (VReg) {
195  MachineFunction &MF = MIRBuilder.getMF();
196  MachineRegisterInfo &MRI = MF.getRegInfo();
197  auto &DL = MF.getDataLayout();
198  const Function &F = MF.getFunction();
199 
200  ArgInfo OrigArg{VReg, Val->getType()};
201  setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
202 
203  SmallVector<ArgInfo, 8> SplitArgs;
204  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
205  [&](ArrayRef<unsigned> Regs) {
206  MIRBuilder.buildUnmerge(Regs, VReg);
207  }))
208  return false;
209 
210  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
211  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
212  return false;
213  }
214 
215  MIRBuilder.insertInstr(MIB);
216  return true;
217 }
218 
219 namespace {
220 
221 struct IncomingValueHandler : public CallLowering::ValueHandler {
222  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
223  CCAssignFn *AssignFn)
224  : ValueHandler(MIRBuilder, MRI, AssignFn),
225  DL(MIRBuilder.getMF().getDataLayout()) {}
226 
227  unsigned getStackAddress(uint64_t Size, int64_t Offset,
228  MachinePointerInfo &MPO) override {
229  auto &MFI = MIRBuilder.getMF().getFrameInfo();
230  int FI = MFI.CreateFixedObject(Size, Offset, true);
231  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
232 
233  unsigned AddrReg = MRI.createGenericVirtualRegister(
235  MIRBuilder.buildFrameIndex(AddrReg, FI);
236  return AddrReg;
237  }
238 
239  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
240  MachinePointerInfo &MPO, CCValAssign &VA) override {
241  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
243  0);
244  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
245  }
246 
247  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
248  CCValAssign &VA) override {
249  markPhysRegUsed(PhysReg);
250 
251  switch (VA.getLocInfo()) {
252  default: {
253  // If we are copying the value from a physical register with the
254  // size larger than the size of the value itself - build the copy
255  // of the phys reg first and then build the truncation of that copy.
256  // The example of that would be copying from xmm0 to s32, for which
257  // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
258  // we expect this to be handled in SExt/ZExt/AExt case.
259  unsigned PhysRegSize =
260  MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
261  unsigned ValSize = VA.getValVT().getSizeInBits();
262  unsigned LocSize = VA.getLocVT().getSizeInBits();
263  if (PhysRegSize > ValSize && LocSize == ValSize) {
264  auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
265  MIRBuilder.buildTrunc(ValVReg, Copy);
266  return;
267  }
268 
269  MIRBuilder.buildCopy(ValVReg, PhysReg);
270  break;
271  }
272  case CCValAssign::LocInfo::SExt:
273  case CCValAssign::LocInfo::ZExt:
274  case CCValAssign::LocInfo::AExt: {
275  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
276  MIRBuilder.buildTrunc(ValVReg, Copy);
277  break;
278  }
279  }
280  }
281 
282  /// How the physical register gets marked varies between formal
283  /// parameters (it's a basic-block live-in), and a call instruction
284  /// (it's an implicit-def of the BL).
285  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
286 
287 protected:
288  const DataLayout &DL;
289 };
290 
291 struct FormalArgHandler : public IncomingValueHandler {
292  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
293  CCAssignFn *AssignFn)
294  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
295 
296  void markPhysRegUsed(unsigned PhysReg) override {
297  MIRBuilder.getMBB().addLiveIn(PhysReg);
298  }
299 };
300 
301 struct CallReturnHandler : public IncomingValueHandler {
302  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
303  CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
304  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
305 
306  void markPhysRegUsed(unsigned PhysReg) override {
307  MIB.addDef(PhysReg, RegState::Implicit);
308  }
309 
310 protected:
311  MachineInstrBuilder &MIB;
312 };
313 
314 } // end anonymous namespace
315 
317  const Function &F,
318  ArrayRef<unsigned> VRegs) const {
319  if (F.arg_empty())
320  return true;
321 
322  // TODO: handle variadic function
323  if (F.isVarArg())
324  return false;
325 
326  MachineFunction &MF = MIRBuilder.getMF();
327  MachineRegisterInfo &MRI = MF.getRegInfo();
328  auto DL = MF.getDataLayout();
329 
330  SmallVector<ArgInfo, 8> SplitArgs;
331  unsigned Idx = 0;
332  for (auto &Arg : F.args()) {
333 
334  // TODO: handle not simple cases.
335  if (Arg.hasAttribute(Attribute::ByVal) ||
336  Arg.hasAttribute(Attribute::InReg) ||
337  Arg.hasAttribute(Attribute::StructRet) ||
338  Arg.hasAttribute(Attribute::SwiftSelf) ||
339  Arg.hasAttribute(Attribute::SwiftError) ||
340  Arg.hasAttribute(Attribute::Nest))
341  return false;
342 
343  ArgInfo OrigArg(VRegs[Idx], Arg.getType());
344  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
345  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
346  [&](ArrayRef<unsigned> Regs) {
347  MIRBuilder.buildMerge(VRegs[Idx], Regs);
348  }))
349  return false;
350  Idx++;
351  }
352 
353  MachineBasicBlock &MBB = MIRBuilder.getMBB();
354  if (!MBB.empty())
355  MIRBuilder.setInstr(*MBB.begin());
356 
357  FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
358  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
359  return false;
360 
361  // Move back to the end of the basic block.
362  MIRBuilder.setMBB(MBB);
363 
364  return true;
365 }
366 
368  CallingConv::ID CallConv,
369  const MachineOperand &Callee,
370  const ArgInfo &OrigRet,
371  ArrayRef<ArgInfo> OrigArgs) const {
372  MachineFunction &MF = MIRBuilder.getMF();
373  const Function &F = MF.getFunction();
374  MachineRegisterInfo &MRI = MF.getRegInfo();
375  auto &DL = F.getParent()->getDataLayout();
376  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
377  const TargetInstrInfo &TII = *STI.getInstrInfo();
378  auto TRI = STI.getRegisterInfo();
379 
380  // Handle only Linux C, X86_64_SysV calling conventions for now.
381  if (!STI.isTargetLinux() ||
382  !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
383  return false;
384 
385  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
386  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
387 
388  // Create a temporarily-floating call instruction so we can add the implicit
389  // uses of arg registers.
390  bool Is64Bit = STI.is64Bit();
391  unsigned CallOpc = Callee.isReg()
392  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
393  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
394 
395  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
396  TRI->getCallPreservedMask(MF, CallConv));
397 
398  SmallVector<ArgInfo, 8> SplitArgs;
399  for (const auto &OrigArg : OrigArgs) {
400 
401  // TODO: handle not simple cases.
402  if (OrigArg.Flags.isByVal())
403  return false;
404 
405  if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
406  [&](ArrayRef<unsigned> Regs) {
407  MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
408  }))
409  return false;
410  }
411  // Do the actual argument marshalling.
412  OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
413  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
414  return false;
415 
416  bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
417  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
418  // From AMD64 ABI document:
419  // For calls that may call functions that use varargs or stdargs
420  // (prototype-less calls or calls to functions containing ellipsis (...) in
421  // the declaration) %al is used as hidden argument to specify the number
422  // of SSE registers used. The contents of %al do not need to match exactly
423  // the number of registers, but must be an ubound on the number of SSE
424  // registers used and is in the range 0 - 8 inclusive.
425 
426  MIRBuilder.buildInstr(X86::MOV8ri)
427  .addDef(X86::AL)
428  .addImm(Handler.getNumXmmRegs());
430  }
431 
432  // Now we can add the actual call instruction to the correct basic block.
433  MIRBuilder.insertInstr(MIB);
434 
435  // If Callee is a reg, since it is used by a target specific
436  // instruction, it must have a register class matching the
437  // constraint of that instruction.
438  if (Callee.isReg())
440  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
441  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
442 
443  // Finally we can copy the returned value back into its virtual-register. In
444  // symmetry with the arguments, the physical register must be an
445  // implicit-define of the call instruction.
446 
447  if (OrigRet.Reg) {
448  SplitArgs.clear();
449  SmallVector<unsigned, 8> NewRegs;
450 
451  if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
452  [&](ArrayRef<unsigned> Regs) {
453  NewRegs.assign(Regs.begin(), Regs.end());
454  }))
455  return false;
456 
457  CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
458  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
459  return false;
460 
461  if (!NewRegs.empty())
462  MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
463  }
464 
465  CallSeqStart.addImm(Handler.getStackSize())
466  .addImm(0 /* see getFrameTotalSize */)
467  .addImm(0 /* see getFrameAdjustment */);
468 
469  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
470  MIRBuilder.buildInstr(AdjStackUp)
471  .addImm(Handler.getStackSize())
472  .addImm(0 /* NumBytesForCalleeToPop */);
473 
474  return true;
475 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:163
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:508
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
LLVMContext & Context
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:467
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildUnmerge(ArrayRef< unsigned > Res, unsigned Op)
Build and insert Res0, ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:928
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
static const MCPhysReg VRegs[32]
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:360
MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op)
Build and insert Res = G_ANYEXT Op0.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
const HexagonInstrInfo * TII
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
unsigned getSizeInBits() const
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:424
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
bool arg_empty() const
Definition: Function.h:685
const RegList & Regs
void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
amdgpu Simplify well known AMD library false Value * Callee
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
TargetInstrInfo - Interface to description of machine instruction set.
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, unsigned VReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Callback) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Extended Value Type.
Definition: ValueTypes.h:34
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:61
This class contains a discriminated union of information about pointers in memory operands...
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:477
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
CCState - This class holds information needed while lowering arguments and return values...
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
CCValAssign - Represent assignment of one arg/retval to a location.
iterator end() const
Definition: ArrayRef.h:138
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_TRUNC Op.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Basic Alias true
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:653
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:62
void setReg(unsigned Reg)
Change the register this operand corresponds to.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
The memory access always returns the same value (or traps).
MachineFunction & getMF()
Getter for the function we currently build.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
bool isTargetLinux() const
Definition: X86Subtarget.h:710
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:761
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:144
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
X86CallLowering(const X86TargetLowering &TLI)
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
iterator_range< arg_iterator > args()
Definition: Function.h:675