LLVM  8.0.0svn
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the MachineIRBuidler class.
11 //===----------------------------------------------------------------------===//
13 
21 #include "llvm/IR/DebugInfo.h"
22 
23 using namespace llvm;
24 
26  State.MF = &MF;
27  State.MBB = nullptr;
28  State.MRI = &MF.getRegInfo();
29  State.TII = MF.getSubtarget().getInstrInfo();
30  State.DL = DebugLoc();
32  State.InsertedInstr = nullptr;
33 }
34 
36  State.MBB = &MBB;
37  State.II = MBB.end();
38  assert(&getMF() == MBB.getParent() &&
39  "Basic block is in a different function");
40 }
41 
43  assert(MI.getParent() && "Instruction is not part of a basic block");
44  setMBB(*MI.getParent());
45  State.II = MI.getIterator();
46 }
47 
50  assert(MBB.getParent() == &getMF() &&
51  "Basic block is in a different function");
52  State.MBB = &MBB;
53  State.II = II;
54 }
55 
57  if (State.InsertedInstr)
58  State.InsertedInstr(InsertedInstr);
59 }
60 
62  std::function<void(MachineInstr *)> Inserted) {
63  State.InsertedInstr = std::move(Inserted);
64 }
65 
67  State.InsertedInstr = nullptr;
68 }
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
75  return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
79  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80  return MIB;
81 }
82 
84  getMBB().insert(getInsertPt(), MIB);
85  recordInsertion(MIB);
86  return MIB;
87 }
88 
91  const MDNode *Expr) {
92  assert(isa<DILocalVariable>(Variable) && "not a variable");
93  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94  assert(
95  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96  "Expected inlined-at fields to agree");
97  return insertInstr(BuildMI(getMF(), getDL(),
98  getTII().get(TargetOpcode::DBG_VALUE),
99  /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
103  unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
104  assert(isa<DILocalVariable>(Variable) && "not a variable");
105  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
106  assert(
107  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
108  "Expected inlined-at fields to agree");
109  return insertInstr(BuildMI(getMF(), getDL(),
110  getTII().get(TargetOpcode::DBG_VALUE),
111  /*IsIndirect*/ true, Reg, Variable, Expr));
112 }
113 
116  const MDNode *Expr) {
117  assert(isa<DILocalVariable>(Variable) && "not a variable");
118  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
119  assert(
120  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
121  "Expected inlined-at fields to agree");
122  return buildInstr(TargetOpcode::DBG_VALUE)
123  .addFrameIndex(FI)
124  .addImm(0)
125  .addMetadata(Variable)
126  .addMetadata(Expr);
127 }
128 
130  const Constant &C, const MDNode *Variable, const MDNode *Expr) {
131  assert(isa<DILocalVariable>(Variable) && "not a variable");
132  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
133  assert(
134  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
135  "Expected inlined-at fields to agree");
136  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
137  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
138  if (CI->getBitWidth() > 64)
139  MIB.addCImm(CI);
140  else
141  MIB.addImm(CI->getZExtValue());
142  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
143  MIB.addFPImm(CFP);
144  } else {
145  // Insert %noreg if we didn't find a usable constant and had to drop it.
146  MIB.addReg(0U);
147  }
148 
149  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
150 }
151 
153  assert(isa<DILabel>(Label) && "not a label");
154  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
155  "Expected inlined-at fields to agree");
156  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
157 
158  return MIB.addMetadata(Label);
159 }
160 
162  int Idx) {
163  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
164  return buildInstr(TargetOpcode::G_FRAME_INDEX)
165  .addDef(Res)
166  .addFrameIndex(Idx);
167 }
168 
171  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
172  assert(getMRI()->getType(Res).getAddressSpace() ==
173  GV->getType()->getAddressSpace() &&
174  "address space mismatch");
175 
176  return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
177  .addDef(Res)
178  .addGlobalAddress(GV);
179 }
180 
181 void MachineIRBuilderBase::validateBinaryOp(unsigned Res, unsigned Op0,
182  unsigned Op1) {
183  assert((getMRI()->getType(Res).isScalar() ||
184  getMRI()->getType(Res).isVector()) &&
185  "invalid operand type");
186  assert(getMRI()->getType(Res) == getMRI()->getType(Op0) &&
187  getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch");
188 }
189 
191  unsigned Op1) {
192  assert(getMRI()->getType(Res).isPointer() &&
193  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
194  assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
195 
196  return buildInstr(TargetOpcode::G_GEP)
197  .addDef(Res)
198  .addUse(Op0)
199  .addUse(Op1);
200 }
201 
203 MachineIRBuilderBase::materializeGEP(unsigned &Res, unsigned Op0,
204  const LLT &ValueTy, uint64_t Value) {
205  assert(Res == 0 && "Res is a result argument");
206  assert(ValueTy.isScalar() && "invalid offset type");
207 
208  if (Value == 0) {
209  Res = Op0;
210  return None;
211  }
212 
214  unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
215 
216  buildConstant(TmpReg, Value);
217  return buildGEP(Res, Op0, TmpReg);
218 }
219 
221  unsigned Op0,
222  uint32_t NumBits) {
223  assert(getMRI()->getType(Res).isPointer() &&
224  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
225 
226  return buildInstr(TargetOpcode::G_PTR_MASK)
227  .addDef(Res)
228  .addUse(Op0)
229  .addImm(NumBits);
230 }
231 
233  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
234 }
235 
237  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
238  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
239 }
240 
242  assert(getMRI()->getType(Res) == LLT() || getMRI()->getType(Op) == LLT() ||
243  getMRI()->getType(Res) == getMRI()->getType(Op));
244  return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
245 }
246 
249  LLT Ty = getMRI()->getType(Res);
250 
251  assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
252 
253  const ConstantInt *NewVal = &Val;
254  if (Ty.getSizeInBits() != Val.getBitWidth())
256  Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
257 
258  return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
259 }
260 
262  int64_t Val) {
263  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
264  getMRI()->getType(Res).getSizeInBits());
265  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
266  return buildConstant(Res, *CI);
267 }
268 
271  assert(getMRI()->getType(Res).isScalar() && "invalid operand type");
272 
273  return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
274 }
275 
277  double Val) {
278  LLT DstTy = getMRI()->getType(Res);
279  auto &Ctx = getMF().getFunction().getContext();
280  auto *CFP =
282  return buildFConstant(Res, *CFP);
283 }
284 
286  MachineBasicBlock &Dest) {
287  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
288 
289  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
290 }
291 
293  MachineMemOperand &MMO) {
294  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
295 }
296 
298 MachineIRBuilderBase::buildLoadInstr(unsigned Opcode, unsigned Res,
299  unsigned Addr, MachineMemOperand &MMO) {
300  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
301  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
302 
303  return buildInstr(Opcode)
304  .addDef(Res)
305  .addUse(Addr)
306  .addMemOperand(&MMO);
307 }
308 
310  unsigned Addr,
311  MachineMemOperand &MMO) {
312  assert(getMRI()->getType(Val).isValid() && "invalid operand type");
313  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
314 
315  return buildInstr(TargetOpcode::G_STORE)
316  .addUse(Val)
317  .addUse(Addr)
318  .addMemOperand(&MMO);
319 }
320 
322  unsigned CarryOut,
323  unsigned Op0, unsigned Op1,
324  unsigned CarryIn) {
325  assert(getMRI()->getType(Res).isScalar() && "invalid operand type");
326  assert(getMRI()->getType(Res) == getMRI()->getType(Op0) &&
327  getMRI()->getType(Res) == getMRI()->getType(Op1) && "type mismatch");
328  assert(getMRI()->getType(CarryOut).isScalar() && "invalid operand type");
329  assert(getMRI()->getType(CarryOut) == getMRI()->getType(CarryIn) &&
330  "type mismatch");
331 
332  return buildInstr(TargetOpcode::G_UADDE)
333  .addDef(Res)
334  .addDef(CarryOut)
335  .addUse(Op0)
336  .addUse(Op1)
337  .addUse(CarryIn);
338 }
339 
341  unsigned Op) {
342  validateTruncExt(Res, Op, true);
343  return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
344 }
345 
347  validateTruncExt(Res, Op, true);
348  return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
349 }
350 
352  validateTruncExt(Res, Op, true);
353  return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
354 }
355 
357  unsigned Res,
358  unsigned Op) {
359  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
360  TargetOpcode::G_SEXT == ExtOpc) &&
361  "Expecting Extending Opc");
362  assert(getMRI()->getType(Res).isScalar() ||
363  getMRI()->getType(Res).isVector());
364  assert(getMRI()->getType(Res).isScalar() == getMRI()->getType(Op).isScalar());
365 
366  unsigned Opcode = TargetOpcode::COPY;
367  if (getMRI()->getType(Res).getSizeInBits() >
368  getMRI()->getType(Op).getSizeInBits())
369  Opcode = ExtOpc;
370  else if (getMRI()->getType(Res).getSizeInBits() <
371  getMRI()->getType(Op).getSizeInBits())
372  Opcode = TargetOpcode::G_TRUNC;
373  else
374  assert(getMRI()->getType(Res) == getMRI()->getType(Op));
375 
376  return buildInstr(Opcode).addDef(Res).addUse(Op);
377 }
378 
380  unsigned Op) {
381  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
382 }
383 
385  unsigned Op) {
386  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
387 }
388 
390  unsigned Op) {
391  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
392 }
393 
395  unsigned Src) {
396  LLT SrcTy = getMRI()->getType(Src);
397  LLT DstTy = getMRI()->getType(Dst);
398  if (SrcTy == DstTy)
399  return buildCopy(Dst, Src);
400 
401  unsigned Opcode;
402  if (SrcTy.isPointer() && DstTy.isScalar())
403  Opcode = TargetOpcode::G_PTRTOINT;
404  else if (DstTy.isPointer() && SrcTy.isScalar())
405  Opcode = TargetOpcode::G_INTTOPTR;
406  else {
407  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
408  Opcode = TargetOpcode::G_BITCAST;
409  }
410 
411  return buildInstr(Opcode).addDef(Dst).addUse(Src);
412 }
413 
415 MachineIRBuilderBase::buildExtract(unsigned Res, unsigned Src, uint64_t Index) {
416 #ifndef NDEBUG
417  assert(getMRI()->getType(Src).isValid() && "invalid operand type");
418  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
419  assert(Index + getMRI()->getType(Res).getSizeInBits() <=
420  getMRI()->getType(Src).getSizeInBits() &&
421  "extracting off end of register");
422 #endif
423 
424  if (getMRI()->getType(Res).getSizeInBits() ==
425  getMRI()->getType(Src).getSizeInBits()) {
426  assert(Index == 0 && "insertion past the end of a register");
427  return buildCast(Res, Src);
428  }
429 
430  return buildInstr(TargetOpcode::G_EXTRACT)
431  .addDef(Res)
432  .addUse(Src)
433  .addImm(Index);
434 }
435 
437  ArrayRef<uint64_t> Indices) {
438 #ifndef NDEBUG
439  assert(Ops.size() == Indices.size() && "incompatible args");
440  assert(!Ops.empty() && "invalid trivial sequence");
441  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
442  "sequence offsets must be in ascending order");
443 
444  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
445  for (auto Op : Ops)
446  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
447 #endif
448 
449  LLT ResTy = getMRI()->getType(Res);
450  LLT OpTy = getMRI()->getType(Ops[0]);
451  unsigned OpSize = OpTy.getSizeInBits();
452  bool MaybeMerge = true;
453  for (unsigned i = 0; i < Ops.size(); ++i) {
454  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
455  MaybeMerge = false;
456  break;
457  }
458  }
459 
460  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
461  buildMerge(Res, Ops);
462  return;
463  }
464 
465  unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
466  buildUndef(ResIn);
467 
468  for (unsigned i = 0; i < Ops.size(); ++i) {
469  unsigned ResOut = i + 1 == Ops.size()
470  ? Res
472  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
473  ResIn = ResOut;
474  }
475 }
476 
478  return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res);
479 }
480 
482  ArrayRef<unsigned> Ops) {
483 
484 #ifndef NDEBUG
485  assert(!Ops.empty() && "invalid trivial sequence");
486  LLT Ty = getMRI()->getType(Ops[0]);
487  for (auto Reg : Ops)
488  assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
489  assert(Ops.size() * getMRI()->getType(Ops[0]).getSizeInBits() ==
490  getMRI()->getType(Res).getSizeInBits() &&
491  "input operands do not cover output register");
492 #endif
493 
494  if (Ops.size() == 1)
495  return buildCast(Res, Ops[0]);
496 
497  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
498  MIB.addDef(Res);
499  for (unsigned i = 0; i < Ops.size(); ++i)
500  MIB.addUse(Ops[i]);
501  return MIB;
502 }
503 
505  unsigned Op) {
506 
507 #ifndef NDEBUG
508  assert(!Res.empty() && "invalid trivial sequence");
509  LLT Ty = getMRI()->getType(Res[0]);
510  for (auto Reg : Res)
511  assert(getMRI()->getType(Reg) == Ty && "type mismatch in input list");
512  assert(Res.size() * getMRI()->getType(Res[0]).getSizeInBits() ==
513  getMRI()->getType(Op).getSizeInBits() &&
514  "input operands do not cover output register");
515 #endif
516 
517  MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
518  for (unsigned i = 0; i < Res.size(); ++i)
519  MIB.addDef(Res[i]);
520  MIB.addUse(Op);
521  return MIB;
522 }
523 
525  unsigned Src, unsigned Op,
526  unsigned Index) {
527  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
528  getMRI()->getType(Res).getSizeInBits() &&
529  "insertion past the end of a register");
530 
531  if (getMRI()->getType(Res).getSizeInBits() ==
532  getMRI()->getType(Op).getSizeInBits()) {
533  return buildCast(Res, Op);
534  }
535 
536  return buildInstr(TargetOpcode::G_INSERT)
537  .addDef(Res)
538  .addUse(Src)
539  .addUse(Op)
540  .addImm(Index);
541 }
542 
544  unsigned Res,
545  bool HasSideEffects) {
546  auto MIB =
547  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
548  : TargetOpcode::G_INTRINSIC);
549  if (Res)
550  MIB.addDef(Res);
551  MIB.addIntrinsicID(ID);
552  return MIB;
553 }
554 
556  unsigned Op) {
557  validateTruncExt(Res, Op, false);
558  return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
559 }
560 
562  unsigned Op) {
563  validateTruncExt(Res, Op, false);
564  return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
565 }
566 
568  unsigned Res, unsigned Op0,
569  unsigned Op1) {
570 #ifndef NDEBUG
571  assert(getMRI()->getType(Op0) == getMRI()->getType(Op0) && "type mismatch");
572  assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
573  if (getMRI()->getType(Op0).isScalar() || getMRI()->getType(Op0).isPointer())
574  assert(getMRI()->getType(Res).isScalar() && "type mismatch");
575  else
576  assert(getMRI()->getType(Res).isVector() &&
577  getMRI()->getType(Res).getNumElements() ==
578  getMRI()->getType(Op0).getNumElements() &&
579  "type mismatch");
580 #endif
581 
582  return buildInstr(TargetOpcode::G_ICMP)
583  .addDef(Res)
584  .addPredicate(Pred)
585  .addUse(Op0)
586  .addUse(Op1);
587 }
588 
590  unsigned Res, unsigned Op0,
591  unsigned Op1) {
592 #ifndef NDEBUG
593  assert((getMRI()->getType(Op0).isScalar() ||
594  getMRI()->getType(Op0).isVector()) &&
595  "invalid operand type");
596  assert(getMRI()->getType(Op0) == getMRI()->getType(Op1) && "type mismatch");
597  assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
598  if (getMRI()->getType(Op0).isScalar())
599  assert(getMRI()->getType(Res).isScalar() && "type mismatch");
600  else
601  assert(getMRI()->getType(Res).isVector() &&
602  getMRI()->getType(Res).getNumElements() ==
603  getMRI()->getType(Op0).getNumElements() &&
604  "type mismatch");
605 #endif
606 
607  return buildInstr(TargetOpcode::G_FCMP)
608  .addDef(Res)
609  .addPredicate(Pred)
610  .addUse(Op0)
611  .addUse(Op1);
612 }
613 
615  unsigned Tst,
616  unsigned Op0,
617  unsigned Op1) {
618 #ifndef NDEBUG
619  LLT ResTy = getMRI()->getType(Res);
620  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
621  "invalid operand type");
622  assert(ResTy == getMRI()->getType(Op0) && ResTy == getMRI()->getType(Op1) &&
623  "type mismatch");
624  if (ResTy.isScalar() || ResTy.isPointer())
625  assert(getMRI()->getType(Tst).isScalar() && "type mismatch");
626  else
627  assert((getMRI()->getType(Tst).isScalar() ||
628  (getMRI()->getType(Tst).isVector() &&
629  getMRI()->getType(Tst).getNumElements() ==
630  getMRI()->getType(Op0).getNumElements())) &&
631  "type mismatch");
632 #endif
633 
634  return buildInstr(TargetOpcode::G_SELECT)
635  .addDef(Res)
636  .addUse(Tst)
637  .addUse(Op0)
638  .addUse(Op1);
639 }
640 
643  unsigned Elt, unsigned Idx) {
644 #ifndef NDEBUG
645  LLT ResTy = getMRI()->getType(Res);
646  LLT ValTy = getMRI()->getType(Val);
647  LLT EltTy = getMRI()->getType(Elt);
648  LLT IdxTy = getMRI()->getType(Idx);
649  assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
650  assert(IdxTy.isScalar() && "invalid operand type");
651  assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
652  assert(ResTy.getElementType() == EltTy && "type mismatch");
653 #endif
654 
655  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
656  .addDef(Res)
657  .addUse(Val)
658  .addUse(Elt)
659  .addUse(Idx);
660 }
661 
664  unsigned Idx) {
665 #ifndef NDEBUG
666  LLT ResTy = getMRI()->getType(Res);
667  LLT ValTy = getMRI()->getType(Val);
668  LLT IdxTy = getMRI()->getType(Idx);
669  assert(ValTy.isVector() && "invalid operand type");
670  assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type");
671  assert(IdxTy.isScalar() && "invalid operand type");
672  assert(ValTy.getElementType() == ResTy && "type mismatch");
673 #endif
674 
675  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
676  .addDef(Res)
677  .addUse(Val)
678  .addUse(Idx);
679 }
680 
682  unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
683  unsigned NewVal, MachineMemOperand &MMO) {
684 #ifndef NDEBUG
685  LLT OldValResTy = getMRI()->getType(OldValRes);
686  LLT SuccessResTy = getMRI()->getType(SuccessRes);
687  LLT AddrTy = getMRI()->getType(Addr);
688  LLT CmpValTy = getMRI()->getType(CmpVal);
689  LLT NewValTy = getMRI()->getType(NewVal);
690  assert(OldValResTy.isScalar() && "invalid operand type");
691  assert(SuccessResTy.isScalar() && "invalid operand type");
692  assert(AddrTy.isPointer() && "invalid operand type");
693  assert(CmpValTy.isValid() && "invalid operand type");
694  assert(NewValTy.isValid() && "invalid operand type");
695  assert(OldValResTy == CmpValTy && "type mismatch");
696  assert(OldValResTy == NewValTy && "type mismatch");
697 #endif
698 
699  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
700  .addDef(OldValRes)
701  .addDef(SuccessRes)
702  .addUse(Addr)
703  .addUse(CmpVal)
704  .addUse(NewVal)
705  .addMemOperand(&MMO);
706 }
707 
709 MachineIRBuilderBase::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
710  unsigned CmpVal, unsigned NewVal,
711  MachineMemOperand &MMO) {
712 #ifndef NDEBUG
713  LLT OldValResTy = getMRI()->getType(OldValRes);
714  LLT AddrTy = getMRI()->getType(Addr);
715  LLT CmpValTy = getMRI()->getType(CmpVal);
716  LLT NewValTy = getMRI()->getType(NewVal);
717  assert(OldValResTy.isScalar() && "invalid operand type");
718  assert(AddrTy.isPointer() && "invalid operand type");
719  assert(CmpValTy.isValid() && "invalid operand type");
720  assert(NewValTy.isValid() && "invalid operand type");
721  assert(OldValResTy == CmpValTy && "type mismatch");
722  assert(OldValResTy == NewValTy && "type mismatch");
723 #endif
724 
725  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
726  .addDef(OldValRes)
727  .addUse(Addr)
728  .addUse(CmpVal)
729  .addUse(NewVal)
730  .addMemOperand(&MMO);
731 }
732 
734 MachineIRBuilderBase::buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
735  unsigned Addr, unsigned Val,
736  MachineMemOperand &MMO) {
737 #ifndef NDEBUG
738  LLT OldValResTy = getMRI()->getType(OldValRes);
739  LLT AddrTy = getMRI()->getType(Addr);
740  LLT ValTy = getMRI()->getType(Val);
741  assert(OldValResTy.isScalar() && "invalid operand type");
742  assert(AddrTy.isPointer() && "invalid operand type");
743  assert(ValTy.isValid() && "invalid operand type");
744  assert(OldValResTy == ValTy && "type mismatch");
745 #endif
746 
747  return buildInstr(Opcode)
748  .addDef(OldValRes)
749  .addUse(Addr)
750  .addUse(Val)
751  .addMemOperand(&MMO);
752 }
753 
755 MachineIRBuilderBase::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
756  unsigned Val, MachineMemOperand &MMO) {
757  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
758  MMO);
759 }
761 MachineIRBuilderBase::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
762  unsigned Val, MachineMemOperand &MMO) {
763  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
764  MMO);
765 }
767 MachineIRBuilderBase::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
768  unsigned Val, MachineMemOperand &MMO) {
769  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
770  MMO);
771 }
773 MachineIRBuilderBase::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
774  unsigned Val, MachineMemOperand &MMO) {
775  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
776  MMO);
777 }
779 MachineIRBuilderBase::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
780  unsigned Val, MachineMemOperand &MMO) {
781  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
782  MMO);
783 }
785 MachineIRBuilderBase::buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
786  unsigned Val, MachineMemOperand &MMO) {
787  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
788  MMO);
789 }
791 MachineIRBuilderBase::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
792  unsigned Val, MachineMemOperand &MMO) {
793  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
794  MMO);
795 }
797 MachineIRBuilderBase::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
798  unsigned Val, MachineMemOperand &MMO) {
799  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
800  MMO);
801 }
803 MachineIRBuilderBase::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
804  unsigned Val, MachineMemOperand &MMO) {
805  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
806  MMO);
807 }
809 MachineIRBuilderBase::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
810  unsigned Val, MachineMemOperand &MMO) {
811  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
812  MMO);
813 }
815 MachineIRBuilderBase::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
816  unsigned Val, MachineMemOperand &MMO) {
817  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
818  MMO);
819 }
820 
823 #ifndef NDEBUG
824  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
825 #endif
826 
827  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
828 }
829 
830 void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src,
831  bool IsExtend) {
832 #ifndef NDEBUG
833  LLT SrcTy = getMRI()->getType(Src);
834  LLT DstTy = getMRI()->getType(Dst);
835 
836  if (DstTy.isVector()) {
837  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
838  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
839  "different number of elements in a trunc/ext");
840  } else
841  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
842 
843  if (IsExtend)
844  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
845  "invalid narrowing extend");
846  else
847  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
848  "invalid widening trunc");
849 #endif
850 }
bool isFPPredicate() const
Definition: InstrTypes.h:976
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
iterator begin() const
Definition: ArrayRef.h:137
MachineInstrBuilder buildInsertVectorElement(unsigned Res, unsigned Val, unsigned Elt, unsigned Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
bool isScalar() const
MachineInstrBuilder buildFConstant(DstType &&Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildUndef(DstType &&Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildUnmerge(ArrayRef< unsigned > Res, unsigned Op)
Build and insert Res0, ...
MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
unsigned Reg
MachineInstrBuilder buildFPTrunc(DstType &&Res, SrcType &&Src)
Build and insert Res = G_FPTRUNC Op.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op)
Build and insert Res = G_ANYEXT Op0.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:862
MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:143
MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
bool isVector() const
The address of a basic block.
Definition: Constants.h:836
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
A description of a memory reference used in the backend.
std::function< void(MachineInstr *)> InsertedInstr
void setMF(MachineFunction &)
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineBasicBlock::iterator II
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:225
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAnyExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:891
MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:138
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_ZEXT Op.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:221
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildZExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
This is an important base class in LLVM.
Definition: Constant.h:42
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
MachineInstrBuilder buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0, unsigned Op1, unsigned CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:885
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:495
DebugLoc DL
Debug location to be set to any instruction we create.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val, unsigned Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
const DebugLoc & getDL()
Getter for DebugLoc.
self_iterator getIterator()
Definition: ilist_node.h:82
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
static wasm::ValType getType(const TargetRegisterClass *RC)
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:240
MachineInstrBuilder buildSExtOrTrunc(DstTy &&Dst, UseArgTy &&Use)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
iterator end() const
Definition: ArrayRef.h:138
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:684
MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst, unsigned Op0, unsigned Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_TRUNC Op.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
bool isIntPredicate() const
Definition: InstrTypes.h:977
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
void recordInsertions(std::function< void(MachineInstr *)> InsertedInstr)
MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
bool isPointer() const
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:248
MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildMerge(unsigned Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineFunction & getMF()
Getter for the function we currently build.
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
MachineInstrBuilder buildCast(DstType &&Res, ArgType &&Arg)
Build and insert an appropriate cast between two registers of equal size.
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
print Print MemDeps of function
IRTranslator LLVM IR MI
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, unsigned Res, unsigned Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.