LLVM  9.0.0svn
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
13 
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
37  State.MBB = &MBB;
38  State.II = MBB.end();
39  assert(&getMF() == MBB.getParent() &&
40  "Basic block is in a different function");
41 }
42 
44  assert(MI.getParent() && "Instruction is not part of a basic block");
45  setMBB(*MI.getParent());
46  State.II = MI.getIterator();
47 }
48 
50 
53  assert(MBB.getParent() == &getMF() &&
54  "Basic block is in a different function");
55  State.MBB = &MBB;
56  State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60  if (State.Observer)
61  State.Observer->createdInstr(*InsertedInstr);
62 }
63 
65  State.Observer = &Observer;
66 }
67 
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
75  return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
79  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80  return MIB;
81 }
82 
84  getMBB().insert(getInsertPt(), MIB);
85  recordInsertion(MIB);
86  return MIB;
87 }
88 
91  const MDNode *Expr) {
92  assert(isa<DILocalVariable>(Variable) && "not a variable");
93  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94  assert(
95  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96  "Expected inlined-at fields to agree");
97  return insertInstr(BuildMI(getMF(), getDL(),
98  getTII().get(TargetOpcode::DBG_VALUE),
99  /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
104  const MDNode *Expr) {
105  assert(isa<DILocalVariable>(Variable) && "not a variable");
106  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107  assert(
108  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109  "Expected inlined-at fields to agree");
110  return insertInstr(BuildMI(getMF(), getDL(),
111  getTII().get(TargetOpcode::DBG_VALUE),
112  /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
116  const MDNode *Variable,
117  const MDNode *Expr) {
118  assert(isa<DILocalVariable>(Variable) && "not a variable");
119  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120  assert(
121  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122  "Expected inlined-at fields to agree");
123  return buildInstr(TargetOpcode::DBG_VALUE)
124  .addFrameIndex(FI)
125  .addImm(0)
126  .addMetadata(Variable)
127  .addMetadata(Expr);
128 }
129 
131  const MDNode *Variable,
132  const MDNode *Expr) {
133  assert(isa<DILocalVariable>(Variable) && "not a variable");
134  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135  assert(
136  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137  "Expected inlined-at fields to agree");
138  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140  if (CI->getBitWidth() > 64)
141  MIB.addCImm(CI);
142  else
143  MIB.addImm(CI->getZExtValue());
144  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145  MIB.addFPImm(CFP);
146  } else {
147  // Insert %noreg if we didn't find a usable constant and had to drop it.
148  MIB.addReg(0U);
149  }
150 
151  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
155  assert(isa<DILabel>(Label) && "not a label");
156  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157  "Expected inlined-at fields to agree");
158  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160  return MIB.addMetadata(Label);
161 }
162 
164  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165  return buildInstr(TargetOpcode::G_FRAME_INDEX)
166  .addDef(Res)
167  .addFrameIndex(Idx);
168 }
169 
171  const GlobalValue *GV) {
172  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173  assert(getMRI()->getType(Res).getAddressSpace() ==
174  GV->getType()->getAddressSpace() &&
175  "address space mismatch");
176 
177  return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178  .addDef(Res)
179  .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183  const LLT &Op1) {
184  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185  assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
189  const LLT &Op1) {
190  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
191  assert((Res == Op0) && "type mismatch");
192 }
193 
195  unsigned Op1) {
196  assert(getMRI()->getType(Res).isPointer() &&
197  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
198  assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
199 
200  return buildInstr(TargetOpcode::G_GEP)
201  .addDef(Res)
202  .addUse(Op0)
203  .addUse(Op1);
204 }
205 
207 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
208  const LLT &ValueTy, uint64_t Value) {
209  assert(Res == 0 && "Res is a result argument");
210  assert(ValueTy.isScalar() && "invalid offset type");
211 
212  if (Value == 0) {
213  Res = Op0;
214  return None;
215  }
216 
218  auto Cst = buildConstant(ValueTy, Value);
219  return buildGEP(Res, Op0, Cst.getReg(0));
220 }
221 
223  uint32_t NumBits) {
224  assert(getMRI()->getType(Res).isPointer() &&
225  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
226 
227  return buildInstr(TargetOpcode::G_PTR_MASK)
228  .addDef(Res)
229  .addUse(Op0)
230  .addImm(NumBits);
231 }
232 
234  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
235 }
236 
238  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
239  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
240 }
241 
243  const SrcOp &Op) {
244  return buildInstr(TargetOpcode::COPY, Res, Op);
245 }
246 
248  const ConstantInt &Val) {
249  LLT Ty = Res.getLLTTy(*getMRI());
250  LLT EltTy = Ty.getScalarType();
251  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
252  "creating constant with the wrong size");
253 
254  if (Ty.isVector()) {
255  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
256  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
257  .addCImm(&Val);
258  return buildSplatVector(Res, Const);
259  }
260 
261  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
262  Res.addDefToMIB(*getMRI(), Const);
263  Const.addCImm(&Val);
264  return Const;
265 }
266 
268  int64_t Val) {
269  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
271  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
272  return buildConstant(Res, *CI);
273 }
274 
276  const ConstantFP &Val) {
277  LLT Ty = Res.getLLTTy(*getMRI());
278  LLT EltTy = Ty.getScalarType();
279 
281  == EltTy.getSizeInBits() &&
282  "creating fconstant with the wrong size");
283 
284  assert(!Ty.isPointer() && "invalid operand type");
285 
286  if (Ty.isVector()) {
287  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
288  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
289  .addFPImm(&Val);
290 
291  return buildSplatVector(Res, Const);
292  }
293 
294  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
295  Res.addDefToMIB(*getMRI(), Const);
296  Const.addFPImm(&Val);
297  return Const;
298 }
299 
301  const APInt &Val) {
302  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
303  return buildConstant(Res, *CI);
304 }
305 
307  double Val) {
308  LLT DstTy = Res.getLLTTy(*getMRI());
309  auto &Ctx = getMF().getFunction().getContext();
310  auto *CFP =
312  return buildFConstant(Res, *CFP);
313 }
314 
316  MachineBasicBlock &Dest) {
317  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
318 
319  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
320 }
321 
323  MachineMemOperand &MMO) {
324  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
325 }
326 
328  unsigned Res,
329  unsigned Addr,
330  MachineMemOperand &MMO) {
331  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
332  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
333 
334  return buildInstr(Opcode)
335  .addDef(Res)
336  .addUse(Addr)
337  .addMemOperand(&MMO);
338 }
339 
341  MachineMemOperand &MMO) {
342  assert(getMRI()->getType(Val).isValid() && "invalid operand type");
343  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
344 
345  return buildInstr(TargetOpcode::G_STORE)
346  .addUse(Val)
347  .addUse(Addr)
348  .addMemOperand(&MMO);
349 }
350 
352  const DstOp &CarryOut,
353  const SrcOp &Op0,
354  const SrcOp &Op1) {
355  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
356 }
357 
359  const DstOp &CarryOut,
360  const SrcOp &Op0,
361  const SrcOp &Op1,
362  const SrcOp &CarryIn) {
363  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
364  {Op0, Op1, CarryIn});
365 }
366 
368  const SrcOp &Op) {
369  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
370 }
371 
373  const SrcOp &Op) {
374  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
375 }
376 
378  const SrcOp &Op) {
379  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
380 }
381 
382 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
383  const auto *TLI = getMF().getSubtarget().getTargetLowering();
384  switch (TLI->getBooleanContents(IsVec, IsFP)) {
386  return TargetOpcode::G_SEXT;
388  return TargetOpcode::G_ZEXT;
389  default:
390  return TargetOpcode::G_ANYEXT;
391  }
392 }
393 
395  const SrcOp &Op,
396  bool IsFP) {
397  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
398  return buildInstr(ExtOp, Res, Op);
399 }
400 
402  const DstOp &Res,
403  const SrcOp &Op) {
404  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
405  TargetOpcode::G_SEXT == ExtOpc) &&
406  "Expecting Extending Opc");
407  assert(Res.getLLTTy(*getMRI()).isScalar() ||
408  Res.getLLTTy(*getMRI()).isVector());
409  assert(Res.getLLTTy(*getMRI()).isScalar() ==
410  Op.getLLTTy(*getMRI()).isScalar());
411 
412  unsigned Opcode = TargetOpcode::COPY;
413  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
414  Op.getLLTTy(*getMRI()).getSizeInBits())
415  Opcode = ExtOpc;
416  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
417  Op.getLLTTy(*getMRI()).getSizeInBits())
418  Opcode = TargetOpcode::G_TRUNC;
419  else
420  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
421 
422  return buildInstr(Opcode, Res, Op);
423 }
424 
426  const SrcOp &Op) {
427  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
428 }
429 
431  const SrcOp &Op) {
432  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
433 }
434 
436  const SrcOp &Op) {
437  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
438 }
439 
441  const SrcOp &Src) {
442  LLT SrcTy = Src.getLLTTy(*getMRI());
443  LLT DstTy = Dst.getLLTTy(*getMRI());
444  if (SrcTy == DstTy)
445  return buildCopy(Dst, Src);
446 
447  unsigned Opcode;
448  if (SrcTy.isPointer() && DstTy.isScalar())
449  Opcode = TargetOpcode::G_PTRTOINT;
450  else if (DstTy.isPointer() && SrcTy.isScalar())
451  Opcode = TargetOpcode::G_INTTOPTR;
452  else {
453  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
454  Opcode = TargetOpcode::G_BITCAST;
455  }
456 
457  return buildInstr(Opcode, Dst, Src);
458 }
459 
461  const SrcOp &Src,
462  uint64_t Index) {
463  LLT SrcTy = Src.getLLTTy(*getMRI());
464  LLT DstTy = Dst.getLLTTy(*getMRI());
465 
466 #ifndef NDEBUG
467  assert(SrcTy.isValid() && "invalid operand type");
468  assert(DstTy.isValid() && "invalid operand type");
469  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
470  "extracting off end of register");
471 #endif
472 
473  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
474  assert(Index == 0 && "insertion past the end of a register");
475  return buildCast(Dst, Src);
476  }
477 
478  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
479  Dst.addDefToMIB(*getMRI(), Extract);
480  Src.addSrcToMIB(Extract);
481  Extract.addImm(Index);
482  return Extract;
483 }
484 
486  ArrayRef<uint64_t> Indices) {
487 #ifndef NDEBUG
488  assert(Ops.size() == Indices.size() && "incompatible args");
489  assert(!Ops.empty() && "invalid trivial sequence");
490  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
491  "sequence offsets must be in ascending order");
492 
493  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
494  for (auto Op : Ops)
495  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
496 #endif
497 
498  LLT ResTy = getMRI()->getType(Res);
499  LLT OpTy = getMRI()->getType(Ops[0]);
500  unsigned OpSize = OpTy.getSizeInBits();
501  bool MaybeMerge = true;
502  for (unsigned i = 0; i < Ops.size(); ++i) {
503  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
504  MaybeMerge = false;
505  break;
506  }
507  }
508 
509  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
510  buildMerge(Res, Ops);
511  return;
512  }
513 
514  unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
515  buildUndef(ResIn);
516 
517  for (unsigned i = 0; i < Ops.size(); ++i) {
518  unsigned ResOut = i + 1 == Ops.size()
519  ? Res
521  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
522  ResIn = ResOut;
523  }
524 }
525 
527  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
528 }
529 
531  ArrayRef<unsigned> Ops) {
532  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
533  // we need some temporary storage for the DstOp objects. Here we use a
534  // sufficiently large SmallVector to not go through the heap.
535  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
536  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
537 }
538 
540  const SrcOp &Op) {
541  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
542  // we need some temporary storage for the DstOp objects. Here we use a
543  // sufficiently large SmallVector to not go through the heap.
544  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
545  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
546 }
547 
549  const SrcOp &Op) {
550  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
552  for (unsigned I = 0; I != NumReg; ++I)
553  TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
554  return buildUnmerge(TmpVec, Op);
555 }
556 
558  const SrcOp &Op) {
559  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
560  // we need some temporary storage for the DstOp objects. Here we use a
561  // sufficiently large SmallVector to not go through the heap.
562  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
563  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
564 }
565 
567  ArrayRef<unsigned> Ops) {
568  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
569  // we need some temporary storage for the DstOp objects. Here we use a
570  // sufficiently large SmallVector to not go through the heap.
571  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
572  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
573 }
574 
576  const SrcOp &Src) {
577  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
578  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
579 }
580 
583  ArrayRef<unsigned> Ops) {
584  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
585  // we need some temporary storage for the DstOp objects. Here we use a
586  // sufficiently large SmallVector to not go through the heap.
587  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
588  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
589 }
590 
593  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
594  // we need some temporary storage for the DstOp objects. Here we use a
595  // sufficiently large SmallVector to not go through the heap.
596  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
597  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
598 }
599 
601  unsigned Op, unsigned Index) {
602  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
603  getMRI()->getType(Res).getSizeInBits() &&
604  "insertion past the end of a register");
605 
606  if (getMRI()->getType(Res).getSizeInBits() ==
607  getMRI()->getType(Op).getSizeInBits()) {
608  return buildCast(Res, Op);
609  }
610 
611  return buildInstr(TargetOpcode::G_INSERT)
612  .addDef(Res)
613  .addUse(Src)
614  .addUse(Op)
615  .addImm(Index);
616 }
617 
619  ArrayRef<unsigned> ResultRegs,
620  bool HasSideEffects) {
621  auto MIB =
622  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
623  : TargetOpcode::G_INTRINSIC);
624  for (unsigned ResultReg : ResultRegs)
625  MIB.addDef(ResultReg);
626  MIB.addIntrinsicID(ID);
627  return MIB;
628 }
629 
631  const SrcOp &Op) {
632  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
633 }
634 
636  const SrcOp &Op) {
637  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
638 }
639 
641  const DstOp &Res,
642  const SrcOp &Op0,
643  const SrcOp &Op1) {
644  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
645 }
646 
648  const DstOp &Res,
649  const SrcOp &Op0,
650  const SrcOp &Op1) {
651 
652  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
653 }
654 
656  const SrcOp &Tst,
657  const SrcOp &Op0,
658  const SrcOp &Op1) {
659 
660  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
661 }
662 
665  const SrcOp &Elt, const SrcOp &Idx) {
666  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
667 }
668 
671  const SrcOp &Idx) {
672  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
673 }
674 
676  unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
677  unsigned NewVal, MachineMemOperand &MMO) {
678 #ifndef NDEBUG
679  LLT OldValResTy = getMRI()->getType(OldValRes);
680  LLT SuccessResTy = getMRI()->getType(SuccessRes);
681  LLT AddrTy = getMRI()->getType(Addr);
682  LLT CmpValTy = getMRI()->getType(CmpVal);
683  LLT NewValTy = getMRI()->getType(NewVal);
684  assert(OldValResTy.isScalar() && "invalid operand type");
685  assert(SuccessResTy.isScalar() && "invalid operand type");
686  assert(AddrTy.isPointer() && "invalid operand type");
687  assert(CmpValTy.isValid() && "invalid operand type");
688  assert(NewValTy.isValid() && "invalid operand type");
689  assert(OldValResTy == CmpValTy && "type mismatch");
690  assert(OldValResTy == NewValTy && "type mismatch");
691 #endif
692 
693  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
694  .addDef(OldValRes)
695  .addDef(SuccessRes)
696  .addUse(Addr)
697  .addUse(CmpVal)
698  .addUse(NewVal)
699  .addMemOperand(&MMO);
700 }
701 
703 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
704  unsigned CmpVal, unsigned NewVal,
705  MachineMemOperand &MMO) {
706 #ifndef NDEBUG
707  LLT OldValResTy = getMRI()->getType(OldValRes);
708  LLT AddrTy = getMRI()->getType(Addr);
709  LLT CmpValTy = getMRI()->getType(CmpVal);
710  LLT NewValTy = getMRI()->getType(NewVal);
711  assert(OldValResTy.isScalar() && "invalid operand type");
712  assert(AddrTy.isPointer() && "invalid operand type");
713  assert(CmpValTy.isValid() && "invalid operand type");
714  assert(NewValTy.isValid() && "invalid operand type");
715  assert(OldValResTy == CmpValTy && "type mismatch");
716  assert(OldValResTy == NewValTy && "type mismatch");
717 #endif
718 
719  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
720  .addDef(OldValRes)
721  .addUse(Addr)
722  .addUse(CmpVal)
723  .addUse(NewVal)
724  .addMemOperand(&MMO);
725 }
726 
728  unsigned OldValRes,
729  unsigned Addr,
730  unsigned Val,
731  MachineMemOperand &MMO) {
732 #ifndef NDEBUG
733  LLT OldValResTy = getMRI()->getType(OldValRes);
734  LLT AddrTy = getMRI()->getType(Addr);
735  LLT ValTy = getMRI()->getType(Val);
736  assert(OldValResTy.isScalar() && "invalid operand type");
737  assert(AddrTy.isPointer() && "invalid operand type");
738  assert(ValTy.isValid() && "invalid operand type");
739  assert(OldValResTy == ValTy && "type mismatch");
740 #endif
741 
742  return buildInstr(Opcode)
743  .addDef(OldValRes)
744  .addUse(Addr)
745  .addUse(Val)
746  .addMemOperand(&MMO);
747 }
748 
750 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
751  unsigned Val, MachineMemOperand &MMO) {
752  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
753  MMO);
754 }
756 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
757  unsigned Val, MachineMemOperand &MMO) {
758  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
759  MMO);
760 }
762 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
763  unsigned Val, MachineMemOperand &MMO) {
764  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
765  MMO);
766 }
768 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
769  unsigned Val, MachineMemOperand &MMO) {
770  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
771  MMO);
772 }
774 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
775  unsigned Val, MachineMemOperand &MMO) {
776  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
777  MMO);
778 }
780  unsigned Addr,
781  unsigned Val,
782  MachineMemOperand &MMO) {
783  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
784  MMO);
785 }
787 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
788  unsigned Val, MachineMemOperand &MMO) {
789  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
790  MMO);
791 }
793 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
794  unsigned Val, MachineMemOperand &MMO) {
795  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
796  MMO);
797 }
799 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
800  unsigned Val, MachineMemOperand &MMO) {
801  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
802  MMO);
803 }
805 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
806  unsigned Val, MachineMemOperand &MMO) {
807  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
808  MMO);
809 }
811 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
812  unsigned Val, MachineMemOperand &MMO) {
813  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
814  MMO);
815 }
816 
819 #ifndef NDEBUG
820  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
821 #endif
822 
823  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
824 }
825 
826 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
827  bool IsExtend) {
828 #ifndef NDEBUG
829  if (DstTy.isVector()) {
830  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
831  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
832  "different number of elements in a trunc/ext");
833  } else
834  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
835 
836  if (IsExtend)
837  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
838  "invalid narrowing extend");
839  else
840  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
841  "invalid widening trunc");
842 #endif
843 }
844 
845 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
846  const LLT &Op0Ty, const LLT &Op1Ty) {
847 #ifndef NDEBUG
848  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
849  "invalid operand type");
850  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
851  if (ResTy.isScalar() || ResTy.isPointer())
852  assert(TstTy.isScalar() && "type mismatch");
853  else
854  assert((TstTy.isScalar() ||
855  (TstTy.isVector() &&
856  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
857  "type mismatch");
858 #endif
859 }
860 
862  ArrayRef<DstOp> DstOps,
863  ArrayRef<SrcOp> SrcOps,
864  Optional<unsigned> Flags) {
865  switch (Opc) {
866  default:
867  break;
868  case TargetOpcode::G_SELECT: {
869  assert(DstOps.size() == 1 && "Invalid select");
870  assert(SrcOps.size() == 3 && "Invalid select");
872  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
873  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
874  break;
875  }
876  case TargetOpcode::G_ADD:
877  case TargetOpcode::G_AND:
878  case TargetOpcode::G_MUL:
879  case TargetOpcode::G_OR:
880  case TargetOpcode::G_SUB:
881  case TargetOpcode::G_XOR:
882  case TargetOpcode::G_UDIV:
883  case TargetOpcode::G_SDIV:
884  case TargetOpcode::G_UREM:
885  case TargetOpcode::G_SREM: {
886  // All these are binary ops.
887  assert(DstOps.size() == 1 && "Invalid Dst");
888  assert(SrcOps.size() == 2 && "Invalid Srcs");
889  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
890  SrcOps[0].getLLTTy(*getMRI()),
891  SrcOps[1].getLLTTy(*getMRI()));
892  break;
893  }
894  case TargetOpcode::G_SHL:
895  case TargetOpcode::G_ASHR:
896  case TargetOpcode::G_LSHR: {
897  assert(DstOps.size() == 1 && "Invalid Dst");
898  assert(SrcOps.size() == 2 && "Invalid Srcs");
899  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
900  SrcOps[0].getLLTTy(*getMRI()),
901  SrcOps[1].getLLTTy(*getMRI()));
902  break;
903  }
904  case TargetOpcode::G_SEXT:
905  case TargetOpcode::G_ZEXT:
906  case TargetOpcode::G_ANYEXT:
907  assert(DstOps.size() == 1 && "Invalid Dst");
908  assert(SrcOps.size() == 1 && "Invalid Srcs");
909  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
910  SrcOps[0].getLLTTy(*getMRI()), true);
911  break;
912  case TargetOpcode::G_TRUNC:
913  case TargetOpcode::G_FPTRUNC: {
914  assert(DstOps.size() == 1 && "Invalid Dst");
915  assert(SrcOps.size() == 1 && "Invalid Srcs");
916  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
917  SrcOps[0].getLLTTy(*getMRI()), false);
918  break;
919  }
920  case TargetOpcode::COPY:
921  assert(DstOps.size() == 1 && "Invalid Dst");
922  // If the caller wants to add a subreg source it has to be done separately
923  // so we may not have any SrcOps at this point yet.
924  break;
925  case TargetOpcode::G_FCMP:
926  case TargetOpcode::G_ICMP: {
927  assert(DstOps.size() == 1 && "Invalid Dst Operands");
928  assert(SrcOps.size() == 3 && "Invalid Src Operands");
929  // For F/ICMP, the first src operand is the predicate, followed by
930  // the two comparands.
931  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
932  "Expecting predicate");
933  assert([&]() -> bool {
934  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
935  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
936  : CmpInst::isFPPredicate(Pred);
937  }() && "Invalid predicate");
938  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
939  "Type mismatch");
940  assert([&]() -> bool {
941  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
942  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
943  if (Op0Ty.isScalar() || Op0Ty.isPointer())
944  return DstTy.isScalar();
945  else
946  return DstTy.isVector() &&
947  DstTy.getNumElements() == Op0Ty.getNumElements();
948  }() && "Type Mismatch");
949  break;
950  }
951  case TargetOpcode::G_UNMERGE_VALUES: {
952  assert(!DstOps.empty() && "Invalid trivial sequence");
953  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
954  assert(std::all_of(DstOps.begin(), DstOps.end(),
955  [&, this](const DstOp &Op) {
956  return Op.getLLTTy(*getMRI()) ==
957  DstOps[0].getLLTTy(*getMRI());
958  }) &&
959  "type mismatch in output list");
960  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
961  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
962  "input operands do not cover output register");
963  break;
964  }
965  case TargetOpcode::G_MERGE_VALUES: {
966  assert(!SrcOps.empty() && "invalid trivial sequence");
967  assert(DstOps.size() == 1 && "Invalid Dst");
968  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
969  [&, this](const SrcOp &Op) {
970  return Op.getLLTTy(*getMRI()) ==
971  SrcOps[0].getLLTTy(*getMRI());
972  }) &&
973  "type mismatch in input list");
974  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
975  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
976  "input operands do not cover output register");
977  if (SrcOps.size() == 1)
978  return buildCast(DstOps[0], SrcOps[0]);
979  if (DstOps[0].getLLTTy(*getMRI()).isVector())
980  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
981  break;
982  }
983  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
984  assert(DstOps.size() == 1 && "Invalid Dst size");
985  assert(SrcOps.size() == 2 && "Invalid Src size");
986  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
987  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
988  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
989  "Invalid operand type");
990  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
991  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
992  DstOps[0].getLLTTy(*getMRI()) &&
993  "Type mismatch");
994  break;
995  }
996  case TargetOpcode::G_INSERT_VECTOR_ELT: {
997  assert(DstOps.size() == 1 && "Invalid dst size");
998  assert(SrcOps.size() == 3 && "Invalid src size");
999  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1000  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1001  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1002  SrcOps[1].getLLTTy(*getMRI()) &&
1003  "Type mismatch");
1004  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1005  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1006  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1007  "Type mismatch");
1008  break;
1009  }
1010  case TargetOpcode::G_BUILD_VECTOR: {
1011  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1012  "Must have at least 2 operands");
1013  assert(DstOps.size() == 1 && "Invalid DstOps");
1014  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1015  "Res type must be a vector");
1016  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1017  [&, this](const SrcOp &Op) {
1018  return Op.getLLTTy(*getMRI()) ==
1019  SrcOps[0].getLLTTy(*getMRI());
1020  }) &&
1021  "type mismatch in input list");
1022  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1023  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1024  "input scalars do not exactly cover the output vector register");
1025  break;
1026  }
1027  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1028  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1029  "Must have at least 2 operands");
1030  assert(DstOps.size() == 1 && "Invalid DstOps");
1031  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1032  "Res type must be a vector");
1033  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1034  [&, this](const SrcOp &Op) {
1035  return Op.getLLTTy(*getMRI()) ==
1036  SrcOps[0].getLLTTy(*getMRI());
1037  }) &&
1038  "type mismatch in input list");
1039  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1040  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1041  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1042  break;
1043  }
1044  case TargetOpcode::G_CONCAT_VECTORS: {
1045  assert(DstOps.size() == 1 && "Invalid DstOps");
1046  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1047  "Must have at least 2 operands");
1048  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1049  [&, this](const SrcOp &Op) {
1050  return (Op.getLLTTy(*getMRI()).isVector() &&
1051  Op.getLLTTy(*getMRI()) ==
1052  SrcOps[0].getLLTTy(*getMRI()));
1053  }) &&
1054  "type mismatch in input list");
1055  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1056  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1057  "input vectors do not exactly cover the output vector register");
1058  break;
1059  }
1060  case TargetOpcode::G_UADDE: {
1061  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1062  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1063  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1064  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1065  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1066  "Invalid operand");
1067  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1068  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1069  "type mismatch");
1070  break;
1071  }
1072  }
1073 
1074  auto MIB = buildInstr(Opc);
1075  for (const DstOp &Op : DstOps)
1076  Op.addDefToMIB(*getMRI(), MIB);
1077  for (const SrcOp &Op : SrcOps)
1078  Op.addSrcToMIB(MIB);
1079  if (Flags)
1080  MIB->setFlags(*Flags);
1081  return MIB;
1082 }
bool isFPPredicate() const
Definition: InstrTypes.h:738
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
iterator begin() const
Definition: ArrayRef.h:136
unsigned getScalarSizeInBits() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< unsigned > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
bool isScalar() const
MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
GISelChangeObserver * Observer
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
unsigned Reg
virtual const TargetLowering * getTargetLowering() const
MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
LLT getScalarType() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:169
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
const fltSemantics & getSemantics() const
Definition: APFloat.h:1154
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
bool isVector() const
void setMF(MachineFunction &MF)
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
A description of a memory reference used in the backend.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend)
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineBasicBlock::iterator II
void recordInsertion(MachineInstr *MI) const
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:274
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:220
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void setChangeObserver(GISelChangeObserver &Observer)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_FPTRUNC Op.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
unsigned getReg() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
This is an important base class in LLVM.
Definition: Constant.h:41
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:646
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:526
DebugLoc DL
Debug location to be set to any instruction we create.
self_iterator getIterator()
Definition: ilist_node.h:81
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
static wasm::ValType getType(const TargetRegisterClass *RC)
MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
const APFloat & getValueAPF() const
Definition: Constants.h:302
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
iterator end() const
Definition: ArrayRef.h:137
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
const TargetInstrInfo & getTII()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:694
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
void setCSEInfo(GISelCSEInfo *Info)
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
bool isIntPredicate() const
Definition: InstrTypes.h:739
Class for arbitrary precision integers.
Definition: APInt.h:69
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
bool isPointer() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:72
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineFunction * MF
MachineFunction under construction.
MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
This file describes how to lower LLVM code to machine code.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.