LLVM  8.0.0svn
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the MachineIRBuidler class.
11 //===----------------------------------------------------------------------===//
14 
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
37  State.MBB = &MBB;
38  State.II = MBB.end();
39  assert(&getMF() == MBB.getParent() &&
40  "Basic block is in a different function");
41 }
42 
44  assert(MI.getParent() && "Instruction is not part of a basic block");
45  setMBB(*MI.getParent());
46  State.II = MI.getIterator();
47 }
48 
51  assert(MBB.getParent() == &getMF() &&
52  "Basic block is in a different function");
53  State.MBB = &MBB;
54  State.II = II;
55 }
56 
57 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
58  if (State.Observer)
59  State.Observer->createdInstr(*InsertedInstr);
60 }
61 
63  State.Observer = &Observer;
64 }
65 
67 
68 //------------------------------------------------------------------------------
69 // Build instruction variants.
70 //------------------------------------------------------------------------------
71 
73  return insertInstr(buildInstrNoInsert(Opcode));
74 }
75 
77  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
78  return MIB;
79 }
80 
82  getMBB().insert(getInsertPt(), MIB);
83  recordInsertion(MIB);
84  return MIB;
85 }
86 
89  const MDNode *Expr) {
90  assert(isa<DILocalVariable>(Variable) && "not a variable");
91  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
92  assert(
93  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
94  "Expected inlined-at fields to agree");
95  return insertInstr(BuildMI(getMF(), getDL(),
96  getTII().get(TargetOpcode::DBG_VALUE),
97  /*IsIndirect*/ false, Reg, Variable, Expr));
98 }
99 
102  const MDNode *Expr) {
103  assert(isa<DILocalVariable>(Variable) && "not a variable");
104  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
105  assert(
106  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
107  "Expected inlined-at fields to agree");
108  return insertInstr(BuildMI(getMF(), getDL(),
109  getTII().get(TargetOpcode::DBG_VALUE),
110  /*IsIndirect*/ true, Reg, Variable, Expr));
111 }
112 
114  const MDNode *Variable,
115  const MDNode *Expr) {
116  assert(isa<DILocalVariable>(Variable) && "not a variable");
117  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
118  assert(
119  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
120  "Expected inlined-at fields to agree");
121  return buildInstr(TargetOpcode::DBG_VALUE)
122  .addFrameIndex(FI)
123  .addImm(0)
124  .addMetadata(Variable)
125  .addMetadata(Expr);
126 }
127 
129  const MDNode *Variable,
130  const MDNode *Expr) {
131  assert(isa<DILocalVariable>(Variable) && "not a variable");
132  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
133  assert(
134  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
135  "Expected inlined-at fields to agree");
136  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
137  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
138  if (CI->getBitWidth() > 64)
139  MIB.addCImm(CI);
140  else
141  MIB.addImm(CI->getZExtValue());
142  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
143  MIB.addFPImm(CFP);
144  } else {
145  // Insert %noreg if we didn't find a usable constant and had to drop it.
146  MIB.addReg(0U);
147  }
148 
149  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
150 }
151 
153  assert(isa<DILabel>(Label) && "not a label");
154  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
155  "Expected inlined-at fields to agree");
156  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
157 
158  return MIB.addMetadata(Label);
159 }
160 
162  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
163  return buildInstr(TargetOpcode::G_FRAME_INDEX)
164  .addDef(Res)
165  .addFrameIndex(Idx);
166 }
167 
169  const GlobalValue *GV) {
170  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
171  assert(getMRI()->getType(Res).getAddressSpace() ==
172  GV->getType()->getAddressSpace() &&
173  "address space mismatch");
174 
175  return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
176  .addDef(Res)
177  .addGlobalAddress(GV);
178 }
179 
180 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
181  const LLT &Op1) {
182  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
183  assert((Res == Op0 && Res == Op1) && "type mismatch");
184 }
185 
187  unsigned Op1) {
188  assert(getMRI()->getType(Res).isPointer() &&
189  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
190  assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
191 
192  return buildInstr(TargetOpcode::G_GEP)
193  .addDef(Res)
194  .addUse(Op0)
195  .addUse(Op1);
196 }
197 
199 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
200  const LLT &ValueTy, uint64_t Value) {
201  assert(Res == 0 && "Res is a result argument");
202  assert(ValueTy.isScalar() && "invalid offset type");
203 
204  if (Value == 0) {
205  Res = Op0;
206  return None;
207  }
208 
210  unsigned TmpReg = getMRI()->createGenericVirtualRegister(ValueTy);
211 
212  buildConstant(TmpReg, Value);
213  return buildGEP(Res, Op0, TmpReg);
214 }
215 
217  uint32_t NumBits) {
218  assert(getMRI()->getType(Res).isPointer() &&
219  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
220 
221  return buildInstr(TargetOpcode::G_PTR_MASK)
222  .addDef(Res)
223  .addUse(Op0)
224  .addImm(NumBits);
225 }
226 
228  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
229 }
230 
232  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
233  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
234 }
235 
237  const SrcOp &Op) {
238  return buildInstr(TargetOpcode::COPY, Res, Op);
239 }
240 
242  const ConstantInt &Val) {
243  LLT Ty = Res.getLLTTy(*getMRI());
244 
245  assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
246 
247  const ConstantInt *NewVal = &Val;
248  if (Ty.getSizeInBits() != Val.getBitWidth())
250  Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
251 
252  auto MIB = buildInstr(TargetOpcode::G_CONSTANT);
253  Res.addDefToMIB(*getMRI(), MIB);
254  MIB.addCImm(NewVal);
255  return MIB;
256 }
257 
259  int64_t Val) {
260  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
261  Res.getLLTTy(*getMRI()).getSizeInBits());
262  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
263  return buildConstant(Res, *CI);
264 }
265 
267  const ConstantFP &Val) {
268  assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
269 
270  auto MIB = buildInstr(TargetOpcode::G_FCONSTANT);
271  Res.addDefToMIB(*getMRI(), MIB);
272  MIB.addFPImm(&Val);
273  return MIB;
274 }
275 
277  double Val) {
278  LLT DstTy = Res.getLLTTy(*getMRI());
279  auto &Ctx = getMF().getFunction().getContext();
280  auto *CFP =
282  return buildFConstant(Res, *CFP);
283 }
284 
286  MachineBasicBlock &Dest) {
287  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
288 
289  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
290 }
291 
293  MachineMemOperand &MMO) {
294  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
295 }
296 
298  unsigned Res,
299  unsigned Addr,
300  MachineMemOperand &MMO) {
301  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
302  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
303 
304  return buildInstr(Opcode)
305  .addDef(Res)
306  .addUse(Addr)
307  .addMemOperand(&MMO);
308 }
309 
311  MachineMemOperand &MMO) {
312  assert(getMRI()->getType(Val).isValid() && "invalid operand type");
313  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
314 
315  return buildInstr(TargetOpcode::G_STORE)
316  .addUse(Val)
317  .addUse(Addr)
318  .addMemOperand(&MMO);
319 }
320 
322  const DstOp &CarryOut,
323  const SrcOp &Op0,
324  const SrcOp &Op1,
325  const SrcOp &CarryIn) {
326  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
327  {Op0, Op1, CarryIn});
328 }
329 
331  const SrcOp &Op) {
332  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
333 }
334 
336  const SrcOp &Op) {
337  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
338 }
339 
341  const SrcOp &Op) {
342  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
343 }
344 
346  const DstOp &Res,
347  const SrcOp &Op) {
348  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
349  TargetOpcode::G_SEXT == ExtOpc) &&
350  "Expecting Extending Opc");
351  assert(Res.getLLTTy(*getMRI()).isScalar() ||
352  Res.getLLTTy(*getMRI()).isVector());
353  assert(Res.getLLTTy(*getMRI()).isScalar() ==
354  Op.getLLTTy(*getMRI()).isScalar());
355 
356  unsigned Opcode = TargetOpcode::COPY;
357  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
358  Op.getLLTTy(*getMRI()).getSizeInBits())
359  Opcode = ExtOpc;
360  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
361  Op.getLLTTy(*getMRI()).getSizeInBits())
362  Opcode = TargetOpcode::G_TRUNC;
363  else
364  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
365 
366  return buildInstr(Opcode, Res, Op);
367 }
368 
370  const SrcOp &Op) {
371  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
372 }
373 
375  const SrcOp &Op) {
376  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
377 }
378 
380  const SrcOp &Op) {
381  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
382 }
383 
385  const SrcOp &Src) {
386  LLT SrcTy = Src.getLLTTy(*getMRI());
387  LLT DstTy = Dst.getLLTTy(*getMRI());
388  if (SrcTy == DstTy)
389  return buildCopy(Dst, Src);
390 
391  unsigned Opcode;
392  if (SrcTy.isPointer() && DstTy.isScalar())
393  Opcode = TargetOpcode::G_PTRTOINT;
394  else if (DstTy.isPointer() && SrcTy.isScalar())
395  Opcode = TargetOpcode::G_INTTOPTR;
396  else {
397  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
398  Opcode = TargetOpcode::G_BITCAST;
399  }
400 
401  return buildInstr(Opcode, Dst, Src);
402 }
403 
405  uint64_t Index) {
406 #ifndef NDEBUG
407  assert(getMRI()->getType(Src).isValid() && "invalid operand type");
408  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
409  assert(Index + getMRI()->getType(Res).getSizeInBits() <=
410  getMRI()->getType(Src).getSizeInBits() &&
411  "extracting off end of register");
412 #endif
413 
414  if (getMRI()->getType(Res).getSizeInBits() ==
415  getMRI()->getType(Src).getSizeInBits()) {
416  assert(Index == 0 && "insertion past the end of a register");
417  return buildCast(Res, Src);
418  }
419 
420  return buildInstr(TargetOpcode::G_EXTRACT)
421  .addDef(Res)
422  .addUse(Src)
423  .addImm(Index);
424 }
425 
427  ArrayRef<uint64_t> Indices) {
428 #ifndef NDEBUG
429  assert(Ops.size() == Indices.size() && "incompatible args");
430  assert(!Ops.empty() && "invalid trivial sequence");
431  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
432  "sequence offsets must be in ascending order");
433 
434  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
435  for (auto Op : Ops)
436  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
437 #endif
438 
439  LLT ResTy = getMRI()->getType(Res);
440  LLT OpTy = getMRI()->getType(Ops[0]);
441  unsigned OpSize = OpTy.getSizeInBits();
442  bool MaybeMerge = true;
443  for (unsigned i = 0; i < Ops.size(); ++i) {
444  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
445  MaybeMerge = false;
446  break;
447  }
448  }
449 
450  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
451  buildMerge(Res, Ops);
452  return;
453  }
454 
455  unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
456  buildUndef(ResIn);
457 
458  for (unsigned i = 0; i < Ops.size(); ++i) {
459  unsigned ResOut = i + 1 == Ops.size()
460  ? Res
462  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
463  ResIn = ResOut;
464  }
465 }
466 
468  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
469 }
470 
472  ArrayRef<unsigned> Ops) {
473  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
474  // we need some temporary storage for the DstOp objects. Here we use a
475  // sufficiently large SmallVector to not go through the heap.
476  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
477  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
478 }
479 
481  const SrcOp &Op) {
482  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
483  // we need some temporary storage for the DstOp objects. Here we use a
484  // sufficiently large SmallVector to not go through the heap.
485  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
486  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
487 }
488 
490  const SrcOp &Op) {
491  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
492  // we need some temporary storage for the DstOp objects. Here we use a
493  // sufficiently large SmallVector to not go through the heap.
494  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
495  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
496 }
497 
499  ArrayRef<unsigned> Ops) {
500  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
501  // we need some temporary storage for the DstOp objects. Here we use a
502  // sufficiently large SmallVector to not go through the heap.
503  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
504  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
505 }
506 
509  ArrayRef<unsigned> Ops) {
510  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
511  // we need some temporary storage for the DstOp objects. Here we use a
512  // sufficiently large SmallVector to not go through the heap.
513  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
514  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
515 }
516 
519  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
520  // we need some temporary storage for the DstOp objects. Here we use a
521  // sufficiently large SmallVector to not go through the heap.
522  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
523  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
524 }
525 
527  unsigned Op, unsigned Index) {
528  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
529  getMRI()->getType(Res).getSizeInBits() &&
530  "insertion past the end of a register");
531 
532  if (getMRI()->getType(Res).getSizeInBits() ==
533  getMRI()->getType(Op).getSizeInBits()) {
534  return buildCast(Res, Op);
535  }
536 
537  return buildInstr(TargetOpcode::G_INSERT)
538  .addDef(Res)
539  .addUse(Src)
540  .addUse(Op)
541  .addImm(Index);
542 }
543 
545  unsigned Res,
546  bool HasSideEffects) {
547  auto MIB =
548  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
549  : TargetOpcode::G_INTRINSIC);
550  if (Res)
551  MIB.addDef(Res);
552  MIB.addIntrinsicID(ID);
553  return MIB;
554 }
555 
557  const SrcOp &Op) {
558  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
559 }
560 
562  const SrcOp &Op) {
563  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
564 }
565 
567  const DstOp &Res,
568  const SrcOp &Op0,
569  const SrcOp &Op1) {
570  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
571 }
572 
574  const DstOp &Res,
575  const SrcOp &Op0,
576  const SrcOp &Op1) {
577 
578  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
579 }
580 
582  const SrcOp &Tst,
583  const SrcOp &Op0,
584  const SrcOp &Op1) {
585 
586  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
587 }
588 
591  const SrcOp &Elt, const SrcOp &Idx) {
592  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
593 }
594 
597  const SrcOp &Idx) {
598  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
599 }
600 
602  unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
603  unsigned NewVal, MachineMemOperand &MMO) {
604 #ifndef NDEBUG
605  LLT OldValResTy = getMRI()->getType(OldValRes);
606  LLT SuccessResTy = getMRI()->getType(SuccessRes);
607  LLT AddrTy = getMRI()->getType(Addr);
608  LLT CmpValTy = getMRI()->getType(CmpVal);
609  LLT NewValTy = getMRI()->getType(NewVal);
610  assert(OldValResTy.isScalar() && "invalid operand type");
611  assert(SuccessResTy.isScalar() && "invalid operand type");
612  assert(AddrTy.isPointer() && "invalid operand type");
613  assert(CmpValTy.isValid() && "invalid operand type");
614  assert(NewValTy.isValid() && "invalid operand type");
615  assert(OldValResTy == CmpValTy && "type mismatch");
616  assert(OldValResTy == NewValTy && "type mismatch");
617 #endif
618 
619  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
620  .addDef(OldValRes)
621  .addDef(SuccessRes)
622  .addUse(Addr)
623  .addUse(CmpVal)
624  .addUse(NewVal)
625  .addMemOperand(&MMO);
626 }
627 
629 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
630  unsigned CmpVal, unsigned NewVal,
631  MachineMemOperand &MMO) {
632 #ifndef NDEBUG
633  LLT OldValResTy = getMRI()->getType(OldValRes);
634  LLT AddrTy = getMRI()->getType(Addr);
635  LLT CmpValTy = getMRI()->getType(CmpVal);
636  LLT NewValTy = getMRI()->getType(NewVal);
637  assert(OldValResTy.isScalar() && "invalid operand type");
638  assert(AddrTy.isPointer() && "invalid operand type");
639  assert(CmpValTy.isValid() && "invalid operand type");
640  assert(NewValTy.isValid() && "invalid operand type");
641  assert(OldValResTy == CmpValTy && "type mismatch");
642  assert(OldValResTy == NewValTy && "type mismatch");
643 #endif
644 
645  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
646  .addDef(OldValRes)
647  .addUse(Addr)
648  .addUse(CmpVal)
649  .addUse(NewVal)
650  .addMemOperand(&MMO);
651 }
652 
654  unsigned OldValRes,
655  unsigned Addr,
656  unsigned Val,
657  MachineMemOperand &MMO) {
658 #ifndef NDEBUG
659  LLT OldValResTy = getMRI()->getType(OldValRes);
660  LLT AddrTy = getMRI()->getType(Addr);
661  LLT ValTy = getMRI()->getType(Val);
662  assert(OldValResTy.isScalar() && "invalid operand type");
663  assert(AddrTy.isPointer() && "invalid operand type");
664  assert(ValTy.isValid() && "invalid operand type");
665  assert(OldValResTy == ValTy && "type mismatch");
666 #endif
667 
668  return buildInstr(Opcode)
669  .addDef(OldValRes)
670  .addUse(Addr)
671  .addUse(Val)
672  .addMemOperand(&MMO);
673 }
674 
676 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
677  unsigned Val, MachineMemOperand &MMO) {
678  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
679  MMO);
680 }
682 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
683  unsigned Val, MachineMemOperand &MMO) {
684  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
685  MMO);
686 }
688 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
689  unsigned Val, MachineMemOperand &MMO) {
690  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
691  MMO);
692 }
694 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
695  unsigned Val, MachineMemOperand &MMO) {
696  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
697  MMO);
698 }
700 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
701  unsigned Val, MachineMemOperand &MMO) {
702  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
703  MMO);
704 }
706  unsigned Addr,
707  unsigned Val,
708  MachineMemOperand &MMO) {
709  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
710  MMO);
711 }
713 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
714  unsigned Val, MachineMemOperand &MMO) {
715  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
716  MMO);
717 }
719 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
720  unsigned Val, MachineMemOperand &MMO) {
721  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
722  MMO);
723 }
725 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
726  unsigned Val, MachineMemOperand &MMO) {
727  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
728  MMO);
729 }
731 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
732  unsigned Val, MachineMemOperand &MMO) {
733  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
734  MMO);
735 }
737 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
738  unsigned Val, MachineMemOperand &MMO) {
739  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
740  MMO);
741 }
742 
745 #ifndef NDEBUG
746  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
747 #endif
748 
749  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
750 }
751 
752 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
753  bool IsExtend) {
754 #ifndef NDEBUG
755  if (DstTy.isVector()) {
756  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
757  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
758  "different number of elements in a trunc/ext");
759  } else
760  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
761 
762  if (IsExtend)
763  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
764  "invalid narrowing extend");
765  else
766  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
767  "invalid widening trunc");
768 #endif
769 }
770 
771 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
772  const LLT &Op0Ty, const LLT &Op1Ty) {
773 #ifndef NDEBUG
774  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
775  "invalid operand type");
776  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
777  if (ResTy.isScalar() || ResTy.isPointer())
778  assert(TstTy.isScalar() && "type mismatch");
779  else
780  assert((TstTy.isScalar() ||
781  (TstTy.isVector() &&
782  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
783  "type mismatch");
784 #endif
785 }
786 
788  ArrayRef<DstOp> DstOps,
789  ArrayRef<SrcOp> SrcOps,
790  Optional<unsigned> Flags) {
791  switch (Opc) {
792  default:
793  break;
794  case TargetOpcode::G_SELECT: {
795  assert(DstOps.size() == 1 && "Invalid select");
796  assert(SrcOps.size() == 3 && "Invalid select");
798  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
799  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
800  break;
801  }
802  case TargetOpcode::G_ADD:
803  case TargetOpcode::G_AND:
804  case TargetOpcode::G_ASHR:
805  case TargetOpcode::G_LSHR:
806  case TargetOpcode::G_MUL:
807  case TargetOpcode::G_OR:
808  case TargetOpcode::G_SHL:
809  case TargetOpcode::G_SUB:
810  case TargetOpcode::G_XOR:
811  case TargetOpcode::G_UDIV:
812  case TargetOpcode::G_SDIV:
813  case TargetOpcode::G_UREM:
814  case TargetOpcode::G_SREM: {
815  // All these are binary ops.
816  assert(DstOps.size() == 1 && "Invalid Dst");
817  assert(SrcOps.size() == 2 && "Invalid Srcs");
818  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
819  SrcOps[0].getLLTTy(*getMRI()),
820  SrcOps[1].getLLTTy(*getMRI()));
821  break;
822  case TargetOpcode::G_SEXT:
823  case TargetOpcode::G_ZEXT:
824  case TargetOpcode::G_ANYEXT:
825  assert(DstOps.size() == 1 && "Invalid Dst");
826  assert(SrcOps.size() == 1 && "Invalid Srcs");
827  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
828  SrcOps[0].getLLTTy(*getMRI()), true);
829  break;
830  case TargetOpcode::G_TRUNC:
831  case TargetOpcode::G_FPTRUNC:
832  assert(DstOps.size() == 1 && "Invalid Dst");
833  assert(SrcOps.size() == 1 && "Invalid Srcs");
834  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
835  SrcOps[0].getLLTTy(*getMRI()), false);
836  break;
837  }
838  case TargetOpcode::COPY:
839  assert(DstOps.size() == 1 && "Invalid Dst");
840  assert(SrcOps.size() == 1 && "Invalid Srcs");
841  assert(DstOps[0].getLLTTy(*getMRI()) == LLT() ||
842  SrcOps[0].getLLTTy(*getMRI()) == LLT() ||
843  DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI()));
844  break;
845  case TargetOpcode::G_FCMP:
846  case TargetOpcode::G_ICMP: {
847  assert(DstOps.size() == 1 && "Invalid Dst Operands");
848  assert(SrcOps.size() == 3 && "Invalid Src Operands");
849  // For F/ICMP, the first src operand is the predicate, followed by
850  // the two comparands.
851  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
852  "Expecting predicate");
853  assert([&]() -> bool {
854  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
855  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
856  : CmpInst::isFPPredicate(Pred);
857  }() && "Invalid predicate");
858  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
859  "Type mismatch");
860  assert([&]() -> bool {
861  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
862  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
863  if (Op0Ty.isScalar() || Op0Ty.isPointer())
864  return DstTy.isScalar();
865  else
866  return DstTy.isVector() &&
867  DstTy.getNumElements() == Op0Ty.getNumElements();
868  }() && "Type Mismatch");
869  break;
870  }
871  case TargetOpcode::G_UNMERGE_VALUES: {
872  assert(!DstOps.empty() && "Invalid trivial sequence");
873  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
874  assert(std::all_of(DstOps.begin(), DstOps.end(),
875  [&, this](const DstOp &Op) {
876  return Op.getLLTTy(*getMRI()) ==
877  DstOps[0].getLLTTy(*getMRI());
878  }) &&
879  "type mismatch in output list");
880  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
881  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
882  "input operands do not cover output register");
883  break;
884  }
885  case TargetOpcode::G_MERGE_VALUES: {
886  assert(!SrcOps.empty() && "invalid trivial sequence");
887  assert(DstOps.size() == 1 && "Invalid Dst");
888  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
889  [&, this](const SrcOp &Op) {
890  return Op.getLLTTy(*getMRI()) ==
891  SrcOps[0].getLLTTy(*getMRI());
892  }) &&
893  "type mismatch in input list");
894  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
895  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
896  "input operands do not cover output register");
897  if (SrcOps.size() == 1)
898  return buildCast(DstOps[0], SrcOps[0]);
899  if (DstOps[0].getLLTTy(*getMRI()).isVector())
900  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
901  break;
902  }
903  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
904  assert(DstOps.size() == 1 && "Invalid Dst size");
905  assert(SrcOps.size() == 2 && "Invalid Src size");
906  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
907  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
908  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
909  "Invalid operand type");
910  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
911  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
912  DstOps[0].getLLTTy(*getMRI()) &&
913  "Type mismatch");
914  break;
915  }
916  case TargetOpcode::G_INSERT_VECTOR_ELT: {
917  assert(DstOps.size() == 1 && "Invalid dst size");
918  assert(SrcOps.size() == 3 && "Invalid src size");
919  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
920  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
921  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
922  SrcOps[1].getLLTTy(*getMRI()) &&
923  "Type mismatch");
924  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
925  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
926  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
927  "Type mismatch");
928  break;
929  }
930  case TargetOpcode::G_BUILD_VECTOR: {
931  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
932  "Must have at least 2 operands");
933  assert(DstOps.size() == 1 && "Invalid DstOps");
934  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
935  "Res type must be a vector");
936  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
937  [&, this](const SrcOp &Op) {
938  return Op.getLLTTy(*getMRI()) ==
939  SrcOps[0].getLLTTy(*getMRI());
940  }) &&
941  "type mismatch in input list");
942  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
943  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
944  "input scalars do not exactly cover the outpur vector register");
945  break;
946  }
947  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
948  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
949  "Must have at least 2 operands");
950  assert(DstOps.size() == 1 && "Invalid DstOps");
951  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
952  "Res type must be a vector");
953  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
954  [&, this](const SrcOp &Op) {
955  return Op.getLLTTy(*getMRI()) ==
956  SrcOps[0].getLLTTy(*getMRI());
957  }) &&
958  "type mismatch in input list");
959  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
960  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
961  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
962  break;
963  }
964  case TargetOpcode::G_CONCAT_VECTORS: {
965  assert(DstOps.size() == 1 && "Invalid DstOps");
966  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
967  "Must have at least 2 operands");
968  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
969  [&, this](const SrcOp &Op) {
970  return (Op.getLLTTy(*getMRI()).isVector() &&
971  Op.getLLTTy(*getMRI()) ==
972  SrcOps[0].getLLTTy(*getMRI()));
973  }) &&
974  "type mismatch in input list");
975  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
976  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
977  "input vectors do not exactly cover the outpur vector register");
978  break;
979  }
980  case TargetOpcode::G_UADDE: {
981  assert(DstOps.size() == 2 && "Invalid no of dst operands");
982  assert(SrcOps.size() == 3 && "Invalid no of src operands");
983  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
984  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
985  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
986  "Invalid operand");
987  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
988  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
989  "type mismatch");
990  break;
991  }
992  }
993 
994  auto MIB = buildInstr(Opc);
995  for (const DstOp &Op : DstOps)
996  Op.addDefToMIB(*getMRI(), MIB);
997  for (const SrcOp &Op : SrcOps)
998  Op.addSrcToMIB(MIB);
999  if (Flags)
1000  MIB->setFlags(*Flags);
1001  return MIB;
1002 }
bool isFPPredicate() const
Definition: InstrTypes.h:734
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
iterator begin() const
Definition: ArrayRef.h:137
bool isScalar() const
MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
GISelChangeObserver * Observer
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
unsigned Reg
MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1180
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:864
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:143
MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
bool isVector() const
The address of a basic block.
Definition: Constants.h:840
MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
A description of a memory reference used in the backend.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend)
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineBasicBlock::iterator II
void recordInsertion(MachineInstr *MI) const
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:225
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:884
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:138
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:221
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
void setChangeObserver(GISelChangeObserver &Observer)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_FPTRUNC Op.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
This is an important base class in LLVM.
Definition: Constant.h:42
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, unsigned Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:642
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:495
DebugLoc DL
Debug location to be set to any instruction we create.
self_iterator getIterator()
Definition: ilist_node.h:82
void setMF(MachineFunction &)
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:194
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
static wasm::ValType getType(const TargetRegisterClass *RC)
MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:240
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
iterator end() const
Definition: ArrayRef.h:138
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
const TargetInstrInfo & getTII()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:622
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:685
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
bool isIntPredicate() const
Definition: InstrTypes.h:735
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
bool isPointer() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:73
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineFunction * MF
MachineFunction under construction.
MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
const DebugLoc & getDL()
Getter for DebugLoc.
virtual void createdInstr(const MachineInstr &MI)=0
An instruction was created and inserted into the function.
MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:274
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.