LLVM  10.0.0svn
Public Types | Public Member Functions | Protected Types | Protected Attributes | List of all members
llvm::X86Subtarget Class Referencefinal

#include "Target/X86/X86Subtarget.h"

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Public Types

enum  X86ProcFamilyEnum {
  Others, IntelAtom, IntelSLM, IntelGLM,
  IntelGLP, IntelTRM
}
 

Public Member Functions

 X86Subtarget (const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, MaybeAlign StackAlignOverride, unsigned PreferVectorWidthOverride, unsigned RequiredVectorWidth)
 This constructor initializes the data members to match that of the specified triple. More...
 
const X86TargetLoweringgetTargetLowering () const override
 
const X86InstrInfogetInstrInfo () const override
 
const X86FrameLoweringgetFrameLowering () const override
 
const X86SelectionDAGInfogetSelectionDAGInfo () const override
 
const X86RegisterInfogetRegisterInfo () const override
 
Align getStackAlignment () const
 Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...
 
unsigned getMaxInlineSizeThreshold () const
 Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...
 
void ParseSubtargetFeatures (StringRef CPU, StringRef FS)
 ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...
 
const CallLoweringgetCallLowering () const override
 Methods used by Global ISel. More...
 
InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
bool is64Bit () const
 Is this x86_64? (disregarding specific ABI / programming model) More...
 
bool is32Bit () const
 
bool is16Bit () const
 
bool isTarget64BitILP32 () const
 Is this x86_64 with the ILP32 programming model (x32 ABI)? More...
 
bool isTarget64BitLP64 () const
 Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? More...
 
PICStyles::Style getPICStyle () const
 
void setPICStyle (PICStyles::Style Style)
 
bool hasX87 () const
 
bool hasCmpxchg8b () const
 
bool hasNOPL () const
 
bool hasCMov () const
 
bool hasSSE1 () const
 
bool hasSSE2 () const
 
bool hasSSE3 () const
 
bool hasSSSE3 () const
 
bool hasSSE41 () const
 
bool hasSSE42 () const
 
bool hasAVX () const
 
bool hasAVX2 () const
 
bool hasAVX512 () const
 
bool hasInt256 () const
 
bool hasSSE4A () const
 
bool hasMMX () const
 
bool has3DNow () const
 
bool has3DNowA () const
 
bool hasPOPCNT () const
 
bool hasAES () const
 
bool hasVAES () const
 
bool hasFXSR () const
 
bool hasXSAVE () const
 
bool hasXSAVEOPT () const
 
bool hasXSAVEC () const
 
bool hasXSAVES () const
 
bool hasPCLMUL () const
 
bool hasVPCLMULQDQ () const
 
bool hasGFNI () const
 
bool hasFMA () const
 
bool hasFMA4 () const
 
bool hasAnyFMA () const
 
bool hasXOP () const
 
bool hasTBM () const
 
bool hasLWP () const
 
bool hasMOVBE () const
 
bool hasRDRAND () const
 
bool hasF16C () const
 
bool hasFSGSBase () const
 
bool hasLZCNT () const
 
bool hasBMI () const
 
bool hasBMI2 () const
 
bool hasVBMI () const
 
bool hasVBMI2 () const
 
bool hasIFMA () const
 
bool hasRTM () const
 
bool hasADX () const
 
bool hasSHA () const
 
bool hasPRFCHW () const
 
bool hasPREFETCHWT1 () const
 
bool hasSSEPrefetch () const
 
bool hasRDSEED () const
 
bool hasLAHFSAHF () const
 
bool hasMWAITX () const
 
bool hasCLZERO () const
 
bool hasCLDEMOTE () const
 
bool hasMOVDIRI () const
 
bool hasMOVDIR64B () const
 
bool hasPTWRITE () const
 
bool isSHLDSlow () const
 
bool isPMULLDSlow () const
 
bool isPMADDWDSlow () const
 
bool isUnalignedMem16Slow () const
 
bool isUnalignedMem32Slow () const
 
int getGatherOverhead () const
 
int getScatterOverhead () const
 
bool hasSSEUnalignedMem () const
 
bool hasCmpxchg16b () const
 
bool useLeaForSP () const
 
bool hasPOPCNTFalseDeps () const
 
bool hasLZCNTFalseDeps () const
 
bool hasFastVariableShuffle () const
 
bool hasFastPartialYMMorZMMWrite () const
 
bool hasFastGather () const
 
bool hasFastScalarFSQRT () const
 
bool hasFastVectorFSQRT () const
 
bool hasFastLZCNT () const
 
bool hasFastSHLDRotate () const
 
bool hasFastBEXTR () const
 
bool hasFastHorizontalOps () const
 
bool hasFastScalarShiftMasks () const
 
bool hasFastVectorShiftMasks () const
 
bool hasMacroFusion () const
 
bool hasBranchFusion () const
 
bool hasERMSB () const
 
bool hasSlowDivide32 () const
 
bool hasSlowDivide64 () const
 
bool padShortFunctions () const
 
bool slowTwoMemOps () const
 
bool LEAusesAG () const
 
bool slowLEA () const
 
bool slow3OpsLEA () const
 
bool slowIncDec () const
 
bool hasCDI () const
 
bool hasVPOPCNTDQ () const
 
bool hasPFI () const
 
bool hasERI () const
 
bool hasDQI () const
 
bool hasBWI () const
 
bool hasVLX () const
 
bool hasPKU () const
 
bool hasVNNI () const
 
bool hasBF16 () const
 
bool hasVP2INTERSECT () const
 
bool hasBITALG () const
 
bool hasSHSTK () const
 
bool hasCLFLUSHOPT () const
 
bool hasCLWB () const
 
bool hasWBNOINVD () const
 
bool hasRDPID () const
 
bool hasWAITPKG () const
 
bool hasPCONFIG () const
 
bool hasSGX () const
 
bool threewayBranchProfitable () const
 
bool hasINVPCID () const
 
bool hasENQCMD () const
 
bool useRetpolineIndirectCalls () const
 
bool useRetpolineIndirectBranches () const
 
bool useRetpolineExternalThunk () const
 
unsigned getPreferVectorWidth () const
 
unsigned getRequiredVectorWidth () const
 
bool canExtendTo512DQ () const
 
bool canExtendTo512BW () const
 
bool useAVX512Regs () const
 
bool useBWIRegs () const
 
bool isXRaySupported () const override
 
X86ProcFamilyEnum getProcFamily () const
 
bool isAtom () const
 TODO: to be removed later and replaced with suitable properties. More...
 
bool isSLM () const
 
bool isGLM () const
 
bool useSoftFloat () const
 
bool useAA () const override
 
bool hasMFence () const
 Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2). More...
 
const TriplegetTargetTriple () const
 
bool isTargetDarwin () const
 
bool isTargetFreeBSD () const
 
bool isTargetDragonFly () const
 
bool isTargetSolaris () const
 
bool isTargetPS4 () const
 
bool isTargetELF () const
 
bool isTargetCOFF () const
 
bool isTargetMachO () const
 
bool isTargetLinux () const
 
bool isTargetKFreeBSD () const
 
bool isTargetGlibc () const
 
bool isTargetAndroid () const
 
bool isTargetNaCl () const
 
bool isTargetNaCl32 () const
 
bool isTargetNaCl64 () const
 
bool isTargetMCU () const
 
bool isTargetFuchsia () const
 
bool isTargetWindowsMSVC () const
 
bool isTargetWindowsCoreCLR () const
 
bool isTargetWindowsCygwin () const
 
bool isTargetWindowsGNU () const
 
bool isTargetWindowsItanium () const
 
bool isTargetCygMing () const
 
bool isOSWindows () const
 
bool isTargetWin64 () const
 
bool isTargetWin32 () const
 
bool isPICStyleGOT () const
 
bool isPICStyleRIPRel () const
 
bool isPICStyleStubPIC () const
 
bool isPositionIndependent () const
 
bool isCallingConvWin64 (CallingConv::ID CC) const
 
unsigned char classifyLocalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalReference (const GlobalValue *GV, const Module &M) const
 
unsigned char classifyGlobalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV, const Module &M) const
 Classify a global function reference for the current subtarget. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV) const
 
unsigned char classifyBlockAddressReference () const
 Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
bool isLegalToCallImmediateAddr () const
 Return true if the subtarget allows calls to immediate address. More...
 
bool enableIndirectBrExpand () const override
 If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect jump. More...
 
bool enableMachineScheduler () const override
 Enable the MachineScheduler pass for all X86 subtargets. More...
 
bool enableEarlyIfConversion () const override
 
void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
 
AntiDepBreakMode getAntiDepBreakMode () const override
 
bool enableAdvancedRASplitCost () const override
 

Protected Types

enum  X86SSEEnum {
  NoSSE, SSE1, SSE2, SSE3,
  SSSE3, SSE41, SSE42, AVX,
  AVX2, AVX512F
}
 
enum  X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA }
 

Protected Attributes

X86ProcFamilyEnum X86ProcFamily = Others
 X86 processor family: Intel Atom, and others. More...
 
PICStyles::Style PICStyle
 Which PIC style to use. More...
 
const TargetMachineTM
 
X86SSEEnum X86SSELevel = NoSSE
 SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. More...
 
X863DNowEnum X863DNowLevel = NoThreeDNow
 MMX, 3DNow, 3DNow Athlon, or none supported. More...
 
bool HasX87 = false
 True if the processor supports X87 instructions. More...
 
bool HasCmpxchg8b = false
 True if the processor supports CMPXCHG8B. More...
 
bool HasNOPL = false
 True if this processor has NOPL instruction (generally pentium pro+). More...
 
bool HasCMov = false
 True if this processor has conditional move instructions (generally pentium pro+). More...
 
bool HasX86_64 = false
 True if the processor supports X86-64 instructions. More...
 
bool HasPOPCNT = false
 True if the processor supports POPCNT. More...
 
bool HasSSE4A = false
 True if the processor supports SSE4A instructions. More...
 
bool HasAES = false
 Target has AES instructions. More...
 
bool HasVAES = false
 
bool HasFXSR = false
 Target has FXSAVE/FXRESTOR instructions. More...
 
bool HasXSAVE = false
 Target has XSAVE instructions. More...
 
bool HasXSAVEOPT = false
 Target has XSAVEOPT instructions. More...
 
bool HasXSAVEC = false
 Target has XSAVEC instructions. More...
 
bool HasXSAVES = false
 Target has XSAVES instructions. More...
 
bool HasPCLMUL = false
 Target has carry-less multiplication. More...
 
bool HasVPCLMULQDQ = false
 
bool HasGFNI = false
 Target has Galois Field Arithmetic instructions. More...
 
bool HasFMA = false
 Target has 3-operand fused multiply-add. More...
 
bool HasFMA4 = false
 Target has 4-operand fused multiply-add. More...
 
bool HasXOP = false
 Target has XOP instructions. More...
 
bool HasTBM = false
 Target has TBM instructions. More...
 
bool HasLWP = false
 Target has LWP instructions. More...
 
bool HasMOVBE = false
 True if the processor has the MOVBE instruction. More...
 
bool HasRDRAND = false
 True if the processor has the RDRAND instruction. More...
 
bool HasF16C = false
 Processor has 16-bit floating point conversion instructions. More...
 
bool HasFSGSBase = false
 Processor has FS/GS base insturctions. More...
 
bool HasLZCNT = false
 Processor has LZCNT instruction. More...
 
bool HasBMI = false
 Processor has BMI1 instructions. More...
 
bool HasBMI2 = false
 Processor has BMI2 instructions. More...
 
bool HasVBMI = false
 Processor has VBMI instructions. More...
 
bool HasVBMI2 = false
 Processor has VBMI2 instructions. More...
 
bool HasIFMA = false
 Processor has Integer Fused Multiply Add. More...
 
bool HasRTM = false
 Processor has RTM instructions. More...
 
bool HasADX = false
 Processor has ADX instructions. More...
 
bool HasSHA = false
 Processor has SHA instructions. More...
 
bool HasPRFCHW = false
 Processor has PRFCHW instructions. More...
 
bool HasRDSEED = false
 Processor has RDSEED instructions. More...
 
bool HasLAHFSAHF = false
 Processor has LAHF/SAHF instructions. More...
 
bool HasMWAITX = false
 Processor has MONITORX/MWAITX instructions. More...
 
bool HasCLZERO = false
 Processor has Cache Line Zero instruction. More...
 
bool HasCLDEMOTE = false
 Processor has Cache Line Demote instruction. More...
 
bool HasMOVDIRI = false
 Processor has MOVDIRI instruction (direct store integer). More...
 
bool HasMOVDIR64B = false
 Processor has MOVDIR64B instruction (direct store 64 bytes). More...
 
bool HasPTWRITE = false
 Processor has ptwrite instruction. More...
 
bool HasPREFETCHWT1 = false
 Processor has Prefetch with intent to Write instruction. More...
 
bool IsSHLDSlow = false
 True if SHLD instructions are slow. More...
 
bool IsPMULLDSlow = false
 True if the PMULLD instruction is slow compared to PMULLW/PMULHW and. More...
 
bool IsPMADDWDSlow = false
 True if the PMADDWD instruction is slow compared to PMULLD. More...
 
bool IsUAMem16Slow = false
 True if unaligned memory accesses of 16-bytes are slow. More...
 
bool IsUAMem32Slow = false
 True if unaligned memory accesses of 32-bytes are slow. More...
 
bool HasSSEUnalignedMem = false
 True if SSE operations can have unaligned memory operands. More...
 
bool HasCmpxchg16b = false
 True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips. More...
 
bool UseLeaForSP = false
 True if the LEA instruction should be used for adjusting the stack pointer. More...
 
bool HasPOPCNTFalseDeps = false
 True if POPCNT instruction has a false dependency on the destination register. More...
 
bool HasLZCNTFalseDeps = false
 True if LZCNT/TZCNT instructions have a false dependency on the destination register. More...
 
bool HasFastVariableShuffle = false
 True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuffles. More...
 
bool HasFastPartialYMMorZMMWrite = false
 True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register without clearing the upper part. More...
 
bool HasFast11ByteNOP = false
 True if there is no performance penalty for writing NOPs with up to 11 bytes. More...
 
bool HasFast15ByteNOP = false
 True if there is no performance penalty for writing NOPs with up to 15 bytes. More...
 
bool HasFastGather = false
 True if gather is reasonably fast. More...
 
bool HasFastScalarFSQRT = false
 True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration. More...
 
bool HasFastVectorFSQRT = false
 True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. More...
 
bool HasSlowDivide32 = false
 True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible. More...
 
bool HasSlowDivide64 = false
 True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible. More...
 
bool HasFastLZCNT = false
 True if LZCNT instruction is fast. More...
 
bool HasFastSHLDRotate = false
 True if SHLD based rotate is fast. More...
 
bool HasMacroFusion = false
 True if the processor supports macrofusion. More...
 
bool HasBranchFusion = false
 True if the processor supports branch fusion. More...
 
bool HasERMSB = false
 True if the processor has enhanced REP MOVSB/STOSB. More...
 
bool PadShortFunctions = false
 True if the short functions should be padded to prevent a stall when returning too early. More...
 
bool SlowTwoMemOps = false
 True if two memory operand instructions should use a temporary register instead. More...
 
bool LEAUsesAG = false
 True if the LEA instruction inputs have to be ready at address generation (AG) time. More...
 
bool SlowLEA = false
 True if the LEA instruction with certain arguments is slow. More...
 
bool Slow3OpsLEA = false
 True if the LEA instruction has all three source operands: base, index, and offset or if the LEA instruction uses base and index registers where the base is EBP, RBP,or R13. More...
 
bool SlowIncDec = false
 True if INC and DEC instructions are slow when writing to flags. More...
 
bool HasPFI = false
 Processor has AVX-512 PreFetch Instructions. More...
 
bool HasERI = false
 Processor has AVX-512 Exponential and Reciprocal Instructions. More...
 
bool HasCDI = false
 Processor has AVX-512 Conflict Detection Instructions. More...
 
bool HasVPOPCNTDQ = false
 Processor has AVX-512 population count Instructions. More...
 
bool HasDQI = false
 Processor has AVX-512 Doubleword and Quadword instructions. More...
 
bool HasBWI = false
 Processor has AVX-512 Byte and Word instructions. More...
 
bool HasVLX = false
 Processor has AVX-512 Vector Length eXtenstions. More...
 
bool HasPKU = false
 Processor has PKU extenstions. More...
 
bool HasVNNI = false
 Processor has AVX-512 Vector Neural Network Instructions. More...
 
bool HasBF16 = false
 Processor has AVX-512 bfloat16 floating-point extensions. More...
 
bool HasENQCMD = false
 Processor supports ENQCMD instructions. More...
 
bool HasBITALG = false
 Processor has AVX-512 Bit Algorithms instructions. More...
 
bool HasVP2INTERSECT = false
 Processor has AVX-512 vp2intersect instructions. More...
 
bool DeprecatedHasMPX = false
 Deprecated flag for MPX instructions. More...
 
bool HasSHSTK = false
 Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack. More...
 
bool HasINVPCID = false
 Processor supports Invalidate Process-Context Identifier. More...
 
bool HasSGX = false
 Processor has Software Guard Extensions. More...
 
bool HasCLFLUSHOPT = false
 Processor supports Flush Cache Line instruction. More...
 
bool HasCLWB = false
 Processor supports Cache Line Write Back instruction. More...
 
bool HasWBNOINVD = false
 Processor supports Write Back No Invalidate instruction. More...
 
bool HasRDPID = false
 Processor support RDPID instruction. More...
 
bool HasWAITPKG = false
 Processor supports WaitPKG instructions. More...
 
bool HasPCONFIG = false
 Processor supports PCONFIG instruction. More...
 
bool HasFastBEXTR = false
 Processor has a single uop BEXTR implementation. More...
 
bool HasFastHorizontalOps = false
 Try harder to combine to horizontal vector ops if they are fast. More...
 
bool HasFastScalarShiftMasks = false
 Prefer a left/right scalar logical shifts pair over a shift+and pair. More...
 
bool HasFastVectorShiftMasks = false
 Prefer a left/right vector logical shifts pair over a shift+and pair. More...
 
bool UseRetpolineIndirectCalls = false
 Use a retpoline thunk rather than indirect calls to block speculative execution. More...
 
bool UseRetpolineIndirectBranches = false
 Use a retpoline thunk or remove any indirect branch to block speculative execution. More...
 
bool DeprecatedUseRetpoline = false
 Deprecated flag, query UseRetpolineIndirectCalls and UseRetpolineIndirectBranches instead. More...
 
bool UseRetpolineExternalThunk = false
 When using a retpoline thunk, call an externally provided thunk rather than emitting one inside the compiler. More...
 
bool UseSoftFloat = false
 Use software floating point for code generation. More...
 
bool UseAA = false
 Use alias analysis during code generation. More...
 
Align stackAlignment = Align(4)
 The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...
 
unsigned MaxInlineSizeThreshold = 128
 Max. More...
 
bool Prefer128Bit = false
 Indicates target prefers 128 bit instructions. More...
 
bool Prefer256Bit = false
 Indicates target prefers 256 bit instructions. More...
 
bool ThreewayBranchProfitable = false
 Threeway branch is profitable in this subtarget. More...
 
Triple TargetTriple
 What processor and OS we're targeting. More...
 
std::unique_ptr< CallLoweringCallLoweringInfo
 GlobalISel related APIs. More...
 
std::unique_ptr< LegalizerInfoLegalizer
 
std::unique_ptr< RegisterBankInfoRegBankInfo
 
std::unique_ptr< InstructionSelectorInstSelector
 

Detailed Description

Definition at line 52 of file X86Subtarget.h.

Member Enumeration Documentation

◆ X863DNowEnum

Enumerator
NoThreeDNow 
MMX 
ThreeDNow 
ThreeDNowA 

Definition at line 70 of file X86Subtarget.h.

◆ X86ProcFamilyEnum

Enumerator
Others 
IntelAtom 
IntelSLM 
IntelGLM 
IntelGLP 
IntelTRM 

Definition at line 56 of file X86Subtarget.h.

◆ X86SSEEnum

Enumerator
NoSSE 
SSE1 
SSE2 
SSE3 
SSSE3 
SSE41 
SSE42 
AVX 
AVX2 
AVX512F 

Definition at line 66 of file X86Subtarget.h.

Constructor & Destructor Documentation

◆ X86Subtarget()

X86Subtarget::X86Subtarget ( const Triple TT,
StringRef  CPU,
StringRef  FS,
const X86TargetMachine TM,
MaybeAlign  StackAlignOverride,
unsigned  PreferVectorWidthOverride,
unsigned  RequiredVectorWidth 
)

Member Function Documentation

◆ canExtendTo512BW()

bool llvm::X86Subtarget::canExtendTo512BW ( ) const
inline

◆ canExtendTo512DQ()

bool llvm::X86Subtarget::canExtendTo512DQ ( ) const
inline

◆ classifyBlockAddressReference()

unsigned char X86Subtarget::classifyBlockAddressReference ( ) const

Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 58 of file X86Subtarget.cpp.

References classifyLocalReference().

Referenced by getRetpolineSymbol(), and LowerEXTRACT_SUBVECTOR().

◆ classifyGlobalFunctionReference() [1/2]

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV,
const Module M 
) const

◆ classifyGlobalFunctionReference() [2/2]

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV) const

◆ classifyGlobalReference() [1/2]

unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV,
const Module M 
) const

◆ classifyGlobalReference() [2/2]

unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV) const

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 65 of file X86Subtarget.cpp.

References classifyGlobalReference(), and llvm::GlobalValue::getParent().

◆ classifyLocalReference()

unsigned char X86Subtarget::classifyLocalReference ( const GlobalValue GV) const

◆ enableAdvancedRASplitCost()

bool llvm::X86Subtarget::enableAdvancedRASplitCost ( ) const
inlineoverride

Definition at line 876 of file X86Subtarget.h.

◆ enableEarlyIfConversion()

bool X86Subtarget::enableEarlyIfConversion ( ) const
override

Definition at line 374 of file X86Subtarget.cpp.

References hasCMov(), and X86EarlyIfConv.

◆ enableIndirectBrExpand()

bool llvm::X86Subtarget::enableIndirectBrExpand ( ) const
inlineoverride

If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect jump.

Definition at line 860 of file X86Subtarget.h.

◆ enableMachineScheduler()

bool llvm::X86Subtarget::enableMachineScheduler ( ) const
inlineoverride

Enable the MachineScheduler pass for all X86 subtargets.

Definition at line 865 of file X86Subtarget.h.

◆ getAntiDepBreakMode()

AntiDepBreakMode llvm::X86Subtarget::getAntiDepBreakMode ( ) const
inlineoverride

Definition at line 872 of file X86Subtarget.h.

◆ getCallLowering()

const CallLowering * X86Subtarget::getCallLowering ( ) const
override

Methods used by Global ISel.

Definition at line 358 of file X86Subtarget.cpp.

References CallLoweringInfo.

◆ getFrameLowering()

const X86FrameLowering* llvm::X86Subtarget::getFrameLowering ( ) const
inlineoverride

◆ getGatherOverhead()

int llvm::X86Subtarget::getGatherOverhead ( ) const
inline

Definition at line 648 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::getUserCost().

◆ getInstrInfo()

const X86InstrInfo* llvm::X86Subtarget::getInstrInfo ( ) const
inlineoverride

◆ getInstructionSelector()

InstructionSelector * X86Subtarget::getInstructionSelector ( ) const
override

Definition at line 362 of file X86Subtarget.cpp.

References InstSelector.

◆ getLegalizerInfo()

const LegalizerInfo * X86Subtarget::getLegalizerInfo ( ) const
override

Definition at line 366 of file X86Subtarget.cpp.

◆ getMaxInlineSizeThreshold()

unsigned llvm::X86Subtarget::getMaxInlineSizeThreshold ( ) const
inline

Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 528 of file X86Subtarget.h.

Referenced by emitConstantSizeRepmov().

◆ getPICStyle()

PICStyles::Style llvm::X86Subtarget::getPICStyle ( ) const
inline

Definition at line 572 of file X86Subtarget.h.

◆ getPostRAMutations()

void X86Subtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
override

Definition at line 378 of file X86Subtarget.cpp.

References llvm::createX86MacroFusionDAGMutation().

◆ getPreferVectorWidth()

unsigned llvm::X86Subtarget::getPreferVectorWidth ( ) const
inline

◆ getProcFamily()

X86ProcFamilyEnum llvm::X86Subtarget::getProcFamily ( ) const
inline

Definition at line 736 of file X86Subtarget.h.

◆ getRegBankInfo()

const RegisterBankInfo * X86Subtarget::getRegBankInfo ( ) const
override

Definition at line 370 of file X86Subtarget.cpp.

References RegBankInfo.

◆ getRegisterInfo()

const X86RegisterInfo* llvm::X86Subtarget::getRegisterInfo ( ) const
inlineoverride

◆ getRequiredVectorWidth()

unsigned llvm::X86Subtarget::getRequiredVectorWidth ( ) const
inline

Definition at line 711 of file X86Subtarget.h.

◆ getScatterOverhead()

int llvm::X86Subtarget::getScatterOverhead ( ) const
inline

Definition at line 649 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::getUserCost().

◆ getSelectionDAGInfo()

const X86SelectionDAGInfo* llvm::X86Subtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 513 of file X86Subtarget.h.

◆ getStackAlignment()

Align llvm::X86Subtarget::getStackAlignment ( ) const
inline

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 524 of file X86Subtarget.h.

◆ getTargetLowering()

const X86TargetLowering* llvm::X86Subtarget::getTargetLowering ( ) const
inlineoverride

◆ getTargetTriple()

const Triple& llvm::X86Subtarget::getTargetTriple ( ) const
inline

◆ has3DNow()

bool llvm::X86Subtarget::has3DNow ( ) const
inline

Definition at line 593 of file X86Subtarget.h.

References llvm::X86II::ThreeDNow.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ has3DNowA()

bool llvm::X86Subtarget::has3DNowA ( ) const
inline

Definition at line 594 of file X86Subtarget.h.

◆ hasADX()

bool llvm::X86Subtarget::hasADX ( ) const
inline

Definition at line 625 of file X86Subtarget.h.

◆ hasAES()

bool llvm::X86Subtarget::hasAES ( ) const
inline

Definition at line 596 of file X86Subtarget.h.

◆ hasAnyFMA()

bool llvm::X86Subtarget::hasAnyFMA ( ) const
inline

◆ hasAVX()

bool llvm::X86Subtarget::hasAVX ( ) const
inline

Definition at line 587 of file X86Subtarget.h.

References llvm::AVX.

Referenced by callHasRegMask(), combineBasicSADPattern(), combineBitcastvxi1(), combineConcatVectorOps(), combineConcatVectors(), combineExtInVec(), combineExtractSubvector(), combineFaddFsub(), combineHorizontalPredicateResult(), combineLoopSADPattern(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), createVariablePermute(), EltsFromConsecutiveLoads(), EmitTest(), emitXBegin(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaxInterleaveFactor(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), InsertBitToMaskVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), llvm::X86TTIImpl::isLegalNTStore(), isSortedByValueNo(), llvm::X86LegalizerInfo::legalizeIntrinsic(), LowerANY_EXTEND(), lowerBuildVectorAsBroadcast(), LowerEXTEND_VECTOR_INREG(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), LowerToHorizontalOp(), lowerV2F64Shuffle(), lowerV4F32Shuffle(), LowerZERO_EXTEND(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86TargetLowering::reduceSelectOfFPConstantLoads(), useVectorCast(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasAVX2()

bool llvm::X86Subtarget::hasAVX2 ( ) const
inline

Definition at line 588 of file X86Subtarget.h.

References llvm::AVX2.

Referenced by combineConcatVectorOps(), combineExtractSubvector(), combineShuffleOfConcatUndef(), combineVectorTruncation(), combineX86ShuffleChain(), convertShiftLeftToScale(), createVariablePermute(), EltsFromConsecutiveLoads(), llvm::X86TTIImpl::enableMemCmpExpansion(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getShuffleCost(), InsertBitToMaskVector(), llvm::X86TargetLowering::isDesirableToCombineBuildVectorToShuffleTruncate(), llvm::X86TTIImpl::isLegalMaskedGather(), llvm::X86TTIImpl::isLegalNTLoad(), isLegalToCallImmediateAddr(), llvm::X86TargetLowering::isVectorClearMaskLegal(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), llvm::X86LegalizerInfo::legalizeIntrinsic(), lower256BitShuffle(), lowerBuildVectorAsBroadcast(), LowerMGATHER(), LowerRotate(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsTruncBroadcast(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerToHorizontalOp(), lowerV16I16Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV2X128Shuffle(), lowerV32I8Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV8F32Shuffle(), lowerV8I32Shuffle(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchUnaryPermuteShuffle(), llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), and SplitOpsAndApply().

◆ hasAVX512()

bool llvm::X86Subtarget::hasAVX512 ( ) const
inline

Definition at line 589 of file X86Subtarget.h.

Referenced by canonicalizeBitSelect(), combineBitcast(), combineBitcastvxi1(), combineCastedMaskArithmetic(), combineCompareEqual(), combineExtSetcc(), combineLoad(), combineMaskedLoad(), combineSetCC(), combineStore(), combineToExtendBoolVectorInReg(), combineTruncateWithSat(), combineVectorPack(), combineVectorSignBitsTruncation(), combineX86ShuffleChain(), llvm::X86TargetLowering::convertSelectOfConstantsToMath(), convertShiftLeftToScale(), CopyToFromAsymmetricReg(), createVariablePermute(), EmitAVX512Test(), llvm::X86TTIImpl::enableMemCmpExpansion(), llvm::X86TTIImpl::getArithmeticInstrCost(), getBroadcastOpcode(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getGatherScatterOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::X86RegisterInfo::getReservedRegs(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), llvm::X86TTIImpl::getUserCost(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TTIImpl::isLegalMaskedExpandLoad(), llvm::X86TTIImpl::isLegalMaskedGather(), llvm::X86TTIImpl::isLegalMaskedScatter(), isLegalToCallImmediateAddr(), llvm::X86TargetLowering::isLoadBitCastBeneficial(), isSortedByValueNo(), llvm::X86LegalizerInfo::legalizeIntrinsic(), lower1BitShuffle(), lower512BitShuffle(), LowerBITCAST(), LowerEXTEND_VECTOR_INREG(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleWithUndefHalf(), LowerStore(), LowerTruncateVecI1(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerV8F32Shuffle(), lowerV8I32Shuffle(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), useVectorCast(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasBF16()

bool llvm::X86Subtarget::hasBF16 ( ) const
inline

Definition at line 690 of file X86Subtarget.h.

◆ hasBITALG()

bool llvm::X86Subtarget::hasBITALG ( ) const
inline

Definition at line 692 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasBMI()

bool llvm::X86Subtarget::hasBMI ( ) const
inline

◆ hasBMI2()

bool llvm::X86Subtarget::hasBMI2 ( ) const
inline

Definition at line 620 of file X86Subtarget.h.

Referenced by hasBZHI().

◆ hasBranchFusion()

bool llvm::X86Subtarget::hasBranchFusion ( ) const
inline

Definition at line 671 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::canMacroFuseCmp(), and shouldScheduleAdjacent().

◆ hasBWI()

bool llvm::X86Subtarget::hasBWI ( ) const
inline

Definition at line 686 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), combineBitcastvxi1(), combineSetCC(), combineStore(), combineTruncateWithSat(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), createVariablePermute(), EmitAVX512Test(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getLoadStoreRegOpcode(), getMaskNode(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getv64i1Argument(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), llvm::X86LegalizerInfo::legalizeIntrinsic(), lower1BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerMLOAD(), LowerMSTORE(), LowerMULH(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), lowerV16I16Shuffle(), lowerV16I32Shuffle(), lowerV32I16Shuffle(), lowerV64I8Shuffle(), LowerVectorCTLZ(), LowerVectorCTPOP(), LowerZERO_EXTEND_Mask(), matchBinaryShuffle(), matchShuffleAsShift(), Passv64i1ArgInRegs(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasCDI()

bool llvm::X86Subtarget::hasCDI ( ) const
inline

◆ hasCLDEMOTE()

bool llvm::X86Subtarget::hasCLDEMOTE ( ) const
inline

Definition at line 639 of file X86Subtarget.h.

◆ hasCLFLUSHOPT()

bool llvm::X86Subtarget::hasCLFLUSHOPT ( ) const
inline

Definition at line 694 of file X86Subtarget.h.

◆ hasCLWB()

bool llvm::X86Subtarget::hasCLWB ( ) const
inline

Definition at line 695 of file X86Subtarget.h.

◆ hasCLZERO()

bool llvm::X86Subtarget::hasCLZERO ( ) const
inline

Definition at line 638 of file X86Subtarget.h.

◆ hasCMov()

bool llvm::X86Subtarget::hasCMov ( ) const
inline

◆ hasCmpxchg16b()

bool llvm::X86Subtarget::hasCmpxchg16b ( ) const
inline

◆ hasCmpxchg8b()

bool llvm::X86Subtarget::hasCmpxchg8b ( ) const
inline

Definition at line 576 of file X86Subtarget.h.

Referenced by LowerRotate(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasDQI()

bool llvm::X86Subtarget::hasDQI ( ) const
inline

◆ hasENQCMD()

bool llvm::X86Subtarget::hasENQCMD ( ) const
inline

Definition at line 703 of file X86Subtarget.h.

◆ hasERI()

bool llvm::X86Subtarget::hasERI ( ) const
inline

Definition at line 684 of file X86Subtarget.h.

◆ hasERMSB()

bool llvm::X86Subtarget::hasERMSB ( ) const
inline

Definition at line 672 of file X86Subtarget.h.

Referenced by emitConstantSizeRepmov().

◆ hasF16C()

bool llvm::X86Subtarget::hasF16C ( ) const
inline

Definition at line 616 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasFastBEXTR()

bool llvm::X86Subtarget::hasFastBEXTR ( ) const
inline

Definition at line 666 of file X86Subtarget.h.

Referenced by foldMaskedShiftToBEXTR().

◆ hasFastGather()

bool llvm::X86Subtarget::hasFastGather ( ) const
inline

◆ hasFastHorizontalOps()

bool llvm::X86Subtarget::hasFastHorizontalOps ( ) const
inline

Definition at line 667 of file X86Subtarget.h.

Referenced by combineReductionToHorizontal(), and shouldUseHorizontalOp().

◆ hasFastLZCNT()

bool llvm::X86Subtarget::hasFastLZCNT ( ) const
inline

Definition at line 664 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::isCtlzFast().

◆ hasFastPartialYMMorZMMWrite()

bool llvm::X86Subtarget::hasFastPartialYMMorZMMWrite ( ) const
inline

Definition at line 658 of file X86Subtarget.h.

Referenced by callHasRegMask().

◆ hasFastScalarFSQRT()

bool llvm::X86Subtarget::hasFastScalarFSQRT ( ) const
inline

Definition at line 662 of file X86Subtarget.h.

Referenced by EmitTest().

◆ hasFastScalarShiftMasks()

bool llvm::X86Subtarget::hasFastScalarShiftMasks ( ) const
inline

◆ hasFastSHLDRotate()

bool llvm::X86Subtarget::hasFastSHLDRotate ( ) const
inline

Definition at line 665 of file X86Subtarget.h.

◆ hasFastVariableShuffle()

bool llvm::X86Subtarget::hasFastVariableShuffle ( ) const
inline

Definition at line 655 of file X86Subtarget.h.

Referenced by combineX86ShuffleChain(), and lowerShuffleWithUndefHalf().

◆ hasFastVectorFSQRT()

bool llvm::X86Subtarget::hasFastVectorFSQRT ( ) const
inline

Definition at line 663 of file X86Subtarget.h.

Referenced by EmitTest().

◆ hasFastVectorShiftMasks()

bool llvm::X86Subtarget::hasFastVectorShiftMasks ( ) const
inline

◆ hasFMA()

bool llvm::X86Subtarget::hasFMA ( ) const
inline

Definition at line 608 of file X86Subtarget.h.

◆ hasFMA4()

bool llvm::X86Subtarget::hasFMA4 ( ) const
inline

Definition at line 609 of file X86Subtarget.h.

◆ hasFSGSBase()

bool llvm::X86Subtarget::hasFSGSBase ( ) const
inline

Definition at line 617 of file X86Subtarget.h.

◆ hasFXSR()

bool llvm::X86Subtarget::hasFXSR ( ) const
inline

Definition at line 598 of file X86Subtarget.h.

◆ hasGFNI()

bool llvm::X86Subtarget::hasGFNI ( ) const
inline

Definition at line 605 of file X86Subtarget.h.

◆ hasIFMA()

bool llvm::X86Subtarget::hasIFMA ( ) const
inline

Definition at line 623 of file X86Subtarget.h.

◆ hasInt256()

bool llvm::X86Subtarget::hasInt256 ( ) const
inline

◆ hasINVPCID()

bool llvm::X86Subtarget::hasINVPCID ( ) const
inline

Definition at line 702 of file X86Subtarget.h.

◆ hasLAHFSAHF()

bool llvm::X86Subtarget::hasLAHFSAHF ( ) const
inline

Definition at line 636 of file X86Subtarget.h.

Referenced by EmitTest().

◆ hasLWP()

bool llvm::X86Subtarget::hasLWP ( ) const
inline

Definition at line 613 of file X86Subtarget.h.

◆ hasLZCNT()

bool llvm::X86Subtarget::hasLZCNT ( ) const
inline

◆ hasLZCNTFalseDeps()

bool llvm::X86Subtarget::hasLZCNTFalseDeps ( ) const
inline

Definition at line 654 of file X86Subtarget.h.

Referenced by hasPartialRegUpdate().

◆ hasMacroFusion()

bool llvm::X86Subtarget::hasMacroFusion ( ) const
inline

Definition at line 670 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::canMacroFuseCmp(), and shouldScheduleAdjacent().

◆ hasMFence()

bool llvm::X86Subtarget::hasMFence ( ) const
inline

Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).

There isn't any reason to disable it if the target processor supports it.

Definition at line 752 of file X86Subtarget.h.

References is64Bit().

Referenced by LowerATOMIC_FENCE(), and LowerRotate().

◆ hasMMX()

bool llvm::X86Subtarget::hasMMX ( ) const
inline

◆ hasMOVBE()

bool llvm::X86Subtarget::hasMOVBE ( ) const
inline

Definition at line 614 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasMOVDIR64B()

bool llvm::X86Subtarget::hasMOVDIR64B ( ) const
inline

Definition at line 641 of file X86Subtarget.h.

◆ hasMOVDIRI()

bool llvm::X86Subtarget::hasMOVDIRI ( ) const
inline

Definition at line 640 of file X86Subtarget.h.

◆ hasMWAITX()

bool llvm::X86Subtarget::hasMWAITX ( ) const
inline

Definition at line 637 of file X86Subtarget.h.

◆ hasNOPL()

bool llvm::X86Subtarget::hasNOPL ( ) const
inline

Definition at line 577 of file X86Subtarget.h.

◆ hasPCLMUL()

bool llvm::X86Subtarget::hasPCLMUL ( ) const
inline

Definition at line 603 of file X86Subtarget.h.

◆ hasPCONFIG()

bool llvm::X86Subtarget::hasPCONFIG ( ) const
inline

Definition at line 699 of file X86Subtarget.h.

◆ hasPFI()

bool llvm::X86Subtarget::hasPFI ( ) const
inline

Definition at line 683 of file X86Subtarget.h.

◆ hasPKU()

bool llvm::X86Subtarget::hasPKU ( ) const
inline

Definition at line 688 of file X86Subtarget.h.

◆ hasPOPCNT()

bool llvm::X86Subtarget::hasPOPCNT ( ) const
inline

◆ hasPOPCNTFalseDeps()

bool llvm::X86Subtarget::hasPOPCNTFalseDeps ( ) const
inline

Definition at line 653 of file X86Subtarget.h.

Referenced by hasPartialRegUpdate().

◆ hasPREFETCHWT1()

bool llvm::X86Subtarget::hasPREFETCHWT1 ( ) const
inline

Definition at line 628 of file X86Subtarget.h.

◆ hasPRFCHW()

bool llvm::X86Subtarget::hasPRFCHW ( ) const
inline

Definition at line 627 of file X86Subtarget.h.

◆ hasPTWRITE()

bool llvm::X86Subtarget::hasPTWRITE ( ) const
inline

Definition at line 642 of file X86Subtarget.h.

◆ hasRDPID()

bool llvm::X86Subtarget::hasRDPID ( ) const
inline

Definition at line 697 of file X86Subtarget.h.

◆ hasRDRAND()

bool llvm::X86Subtarget::hasRDRAND ( ) const
inline

Definition at line 615 of file X86Subtarget.h.

◆ hasRDSEED()

bool llvm::X86Subtarget::hasRDSEED ( ) const
inline

Definition at line 635 of file X86Subtarget.h.

◆ hasRTM()

bool llvm::X86Subtarget::hasRTM ( ) const
inline

Definition at line 624 of file X86Subtarget.h.

◆ hasSGX()

bool llvm::X86Subtarget::hasSGX ( ) const
inline

Definition at line 700 of file X86Subtarget.h.

◆ hasSHA()

bool llvm::X86Subtarget::hasSHA ( ) const
inline

Definition at line 626 of file X86Subtarget.h.

◆ hasSHSTK()

bool llvm::X86Subtarget::hasSHSTK ( ) const
inline

Definition at line 693 of file X86Subtarget.h.

◆ hasSlowDivide32()

bool llvm::X86Subtarget::hasSlowDivide32 ( ) const
inline

Definition at line 673 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSlowDivide64()

bool llvm::X86Subtarget::hasSlowDivide64 ( ) const
inline

Definition at line 674 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSE1()

bool llvm::X86Subtarget::hasSSE1 ( ) const
inline

◆ hasSSE2()

bool llvm::X86Subtarget::hasSSE2 ( ) const
inline

Definition at line 582 of file X86Subtarget.h.

Referenced by combineAnd(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineCompareEqual(), combineExtractWithShuffle(), combineFAndFNotToFAndn(), combineFMinNumFMaxNum(), combineHorizontalPredicateResult(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMOVMSK(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePMULH(), combineSetCC(), combineStore(), combineSubToSubus(), combineToExtendBoolVectorInReg(), combineTruncateWithSat(), combineVectorSignBitsTruncation(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), combineX86ShuffleChain(), combineXor(), llvm::X86InstrInfo::commuteInstructionImpl(), convertIntLogicToFPLogic(), detectAVGPattern(), EmitTest(), llvm::X86TTIImpl::enableMemCmpExpansion(), llvm::X86InstrInfo::findCommutedOpIndices(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), getZeroVector(), llvm::X86TargetLowering::hasAndNot(), InsertBitToMaskVector(), isSortedByValueNo(), llvm::X86LegalizerInfo::legalizeIntrinsic(), LowerBITCAST(), LowerBuildVectorAsInsert(), LowerEXTEND_VECTOR_INREG(), LowerMUL(), LowerMULH(), lowerRegToMasks(), LowerRotate(), LowerShift(), LowerStore(), lowerV4F32Shuffle(), lowerX86FPLogicOp(), llvm::X86TargetLowering::LowerXConstraint(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchPMADDWD(), matchPMADDWD_2(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), materializeVectorConstant(), Passv64i1ArgInRegs(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), SplitOpsAndApply(), SupportedVectorShiftWithImm(), truncateVectorWithPACK(), useVectorCast(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSE3()

bool llvm::X86Subtarget::hasSSE3 ( ) const
inline

◆ hasSSE41()

bool llvm::X86Subtarget::hasSSE41 ( ) const
inline

Definition at line 585 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), combineExtractWithShuffle(), combineHorizontalMinMaxResult(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineReductionToHorizontal(), combineTruncateWithSat(), combineVectorSignBitsTruncation(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), llvm::X86InstrInfo::commuteInstructionImpl(), convertShiftLeftToScale(), createVariablePermute(), ExtractBitFromMaskVector(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getShuffleCost(), getTargetVShiftNode(), InsertBitToMaskVector(), llvm::X86LegalizerInfo::legalizeIntrinsic(), LowerABS(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerBuildVectorv8i16(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsSpecificZeroOrAnyExtend(), LowerTruncateVecI1(), lowerUINT_TO_FP_vXi32(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV4F32Shuffle(), lowerV4I32Shuffle(), lowerV8I16Shuffle(), LowerVectorAllZeroTest(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchUnaryShuffle(), matchVectorShuffleWithPACK(), matchVectorShuffleWithUNPCK(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), truncateVectorWithPACK(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSE42()

bool llvm::X86Subtarget::hasSSE42 ( ) const
inline

◆ hasSSE4A()

bool llvm::X86Subtarget::hasSSE4A ( ) const
inline

◆ hasSSEPrefetch()

bool llvm::X86Subtarget::hasSSEPrefetch ( ) const
inline

Definition at line 629 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSEUnalignedMem()

bool llvm::X86Subtarget::hasSSEUnalignedMem ( ) const
inline

Definition at line 650 of file X86Subtarget.h.

◆ hasSSSE3()

bool llvm::X86Subtarget::hasSSSE3 ( ) const
inline

◆ hasTBM()

bool llvm::X86Subtarget::hasTBM ( ) const
inline

Definition at line 612 of file X86Subtarget.h.

Referenced by foldMaskedShiftToBEXTR().

◆ hasVAES()

bool llvm::X86Subtarget::hasVAES ( ) const
inline

Definition at line 597 of file X86Subtarget.h.

◆ hasVBMI()

bool llvm::X86Subtarget::hasVBMI ( ) const
inline

◆ hasVBMI2()

bool llvm::X86Subtarget::hasVBMI2 ( ) const
inline

◆ hasVLX()

bool llvm::X86Subtarget::hasVLX ( ) const
inline

◆ hasVNNI()

bool llvm::X86Subtarget::hasVNNI ( ) const
inline

Definition at line 689 of file X86Subtarget.h.

◆ hasVP2INTERSECT()

bool llvm::X86Subtarget::hasVP2INTERSECT ( ) const
inline

Definition at line 691 of file X86Subtarget.h.

◆ hasVPCLMULQDQ()

bool llvm::X86Subtarget::hasVPCLMULQDQ ( ) const
inline

Definition at line 604 of file X86Subtarget.h.

◆ hasVPOPCNTDQ()

bool llvm::X86Subtarget::hasVPOPCNTDQ ( ) const
inline

Definition at line 682 of file X86Subtarget.h.

Referenced by LowerVectorCTPOP(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasWAITPKG()

bool llvm::X86Subtarget::hasWAITPKG ( ) const
inline

Definition at line 698 of file X86Subtarget.h.

◆ hasWBNOINVD()

bool llvm::X86Subtarget::hasWBNOINVD ( ) const
inline

Definition at line 696 of file X86Subtarget.h.

◆ hasX87()

bool llvm::X86Subtarget::hasX87 ( ) const
inline

◆ hasXOP()

bool llvm::X86Subtarget::hasXOP ( ) const
inline

◆ hasXSAVE()

bool llvm::X86Subtarget::hasXSAVE ( ) const
inline

Definition at line 599 of file X86Subtarget.h.

◆ hasXSAVEC()

bool llvm::X86Subtarget::hasXSAVEC ( ) const
inline

Definition at line 601 of file X86Subtarget.h.

◆ hasXSAVEOPT()

bool llvm::X86Subtarget::hasXSAVEOPT ( ) const
inline

Definition at line 600 of file X86Subtarget.h.

◆ hasXSAVES()

bool llvm::X86Subtarget::hasXSAVES ( ) const
inline

Definition at line 602 of file X86Subtarget.h.

◆ is16Bit()

bool llvm::X86Subtarget::is16Bit ( ) const
inline

◆ is32Bit()

bool llvm::X86Subtarget::is32Bit ( ) const
inline

◆ is64Bit()

bool llvm::X86Subtarget::is64Bit ( ) const
inline

Is this x86_64? (disregarding specific ABI / programming model)

Definition at line 548 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::X86TargetLowering::canMergeStoresTo(), classifyGlobalFunctionReference(), classifyGlobalReference(), llvm::X86InstrInfo::classifyLEAReg(), classifyLocalReference(), combineAnd(), combineCompareEqual(), combineSIntToFP(), combineStore(), computeBytesPoppedByCalleeForSRet(), convertTailJumpOpcode(), llvm::X86InstrInfo::convertToThreeAddress(), createPHIsForCMOVsInSinkBB(), emitLockedStackOp(), EmitNops(), llvm::X86TargetLowering::emitStackGuardXorFP(), EmitTest(), llvm::X86TTIImpl::enableMemCmpExpansion(), expandIntrinsicWChainHelper(), ExpandMOVImmSExti8(), llvm::X86TargetLowering::findRepresentativeClass(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getIRStackGuard(), getLoadStoreRegOpcode(), getMOVL(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), getOptimalRepmovsType(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), getRetOpcode(), getRetpolineSymbol(), llvm::X86TargetLowering::getSafeStackPointerLocation(), llvm::X86InstrInfo::getSerializableDirectMachineOperandTargetFlags(), llvm::X86TargetLowering::getStackProbeSymbolName(), hasBZHI(), llvm::X86FrameLowering::inlineStackProbe(), IsCallReturnTwice(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::X86TargetLowering::isIntDivCheap(), llvm::X86TargetLowering::isLegalAddressingMode(), isSortedByValueNo(), llvm::X86TargetLowering::isZExtFree(), llvm::X86LegalizerInfo::legalizeIntrinsic(), LowerADJUST_TRAMPOLINE(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerBITCAST(), llvm::X86CallLowering::lowerCall(), LowerCMP_SWAP(), LowerFSINCOS(), LowerI64IntToFP_AVX512DQ(), lowerRegToMasks(), LowerRotate(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), LowerStore(), LowerToTLSExecModel(), LowerTruncateVecI1(), lowerUINT_TO_FP_vec(), LowerVACOPY(), llvm::X86TargetLowering::markLibCallAttributes(), MatchingStackOffset(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), printAsmMRegister(), llvm::X86FrameLowering::processFunctionBeforeFrameFinalized(), recoverFramePointer(), removeRedundantBlockingStores(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair(), SimplifyShortMoveForm(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::X86TargetLowering::supportSwiftError(), llvm::X86TargetLowering::useLoadStackGuardNode(), vectorizeExtractedCast(), llvm::X86FrameLowering::X86FrameLowering(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isAtom()

bool llvm::X86Subtarget::isAtom ( ) const
inline

TODO: to be removed later and replaced with suitable properties.

Definition at line 739 of file X86Subtarget.h.

Referenced by EmitTest(), llvm::X86TTIImpl::enableInterleavedAccessVectorization(), llvm::X86TTIImpl::getMaxInterleaveFactor(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isCallingConvWin64()

bool llvm::X86Subtarget::isCallingConvWin64 ( CallingConv::ID  CC) const
inline

◆ isGLM()

bool llvm::X86Subtarget::isGLM ( ) const
inline

◆ isLegalToCallImmediateAddr()

bool X86Subtarget::isLegalToCallImmediateAddr ( ) const

◆ isOSWindows()

bool llvm::X86Subtarget::isOSWindows ( ) const
inline

◆ isPICStyleGOT()

bool llvm::X86Subtarget::isPICStyleGOT ( ) const
inline

◆ isPICStyleRIPRel()

bool llvm::X86Subtarget::isPICStyleRIPRel ( ) const
inline

◆ isPICStyleStubPIC()

bool llvm::X86Subtarget::isPICStyleStubPIC ( ) const
inline

◆ isPMADDWDSlow()

bool llvm::X86Subtarget::isPMADDWDSlow ( ) const
inline

Definition at line 645 of file X86Subtarget.h.

Referenced by combineMulToPMADDWD().

◆ isPMULLDSlow()

bool llvm::X86Subtarget::isPMULLDSlow ( ) const
inline

Definition at line 644 of file X86Subtarget.h.

Referenced by reduceVMULWidth().

◆ isPositionIndependent()

bool llvm::X86Subtarget::isPositionIndependent ( ) const
inline

◆ isSHLDSlow()

bool llvm::X86Subtarget::isSHLDSlow ( ) const
inline

Definition at line 643 of file X86Subtarget.h.

Referenced by combineOr(), and LowerFunnelShift().

◆ isSLM()

bool llvm::X86Subtarget::isSLM ( ) const
inline

◆ isTarget64BitILP32()

bool llvm::X86Subtarget::isTarget64BitILP32 ( ) const
inline

◆ isTarget64BitLP64()

bool llvm::X86Subtarget::isTarget64BitLP64 ( ) const
inline

◆ isTargetAndroid()

bool llvm::X86Subtarget::isTargetAndroid ( ) const
inline

◆ isTargetCOFF()

bool llvm::X86Subtarget::isTargetCOFF ( ) const
inline

◆ isTargetCygMing()

bool llvm::X86Subtarget::isTargetCygMing ( ) const
inline

◆ isTargetDarwin()

bool llvm::X86Subtarget::isTargetDarwin ( ) const
inline

◆ isTargetDragonFly()

bool llvm::X86Subtarget::isTargetDragonFly ( ) const
inline

◆ isTargetELF()

bool llvm::X86Subtarget::isTargetELF ( ) const
inline

◆ isTargetFreeBSD()

bool llvm::X86Subtarget::isTargetFreeBSD ( ) const
inline

◆ isTargetFuchsia()

bool llvm::X86Subtarget::isTargetFuchsia ( ) const
inline

◆ isTargetGlibc()

bool llvm::X86Subtarget::isTargetGlibc ( ) const
inline

Definition at line 768 of file X86Subtarget.h.

References llvm::Triple::isOSGlibc().

◆ isTargetKFreeBSD()

bool llvm::X86Subtarget::isTargetKFreeBSD ( ) const
inline

Definition at line 767 of file X86Subtarget.h.

References llvm::Triple::isOSKFreeBSD().

Referenced by isLegalToCallImmediateAddr().

◆ isTargetLinux()

bool llvm::X86Subtarget::isTargetLinux ( ) const
inline

◆ isTargetMachO()

bool llvm::X86Subtarget::isTargetMachO ( ) const
inline

◆ isTargetMCU()

bool llvm::X86Subtarget::isTargetMCU ( ) const
inline

◆ isTargetNaCl()

bool llvm::X86Subtarget::isTargetNaCl ( ) const
inline

Definition at line 770 of file X86Subtarget.h.

References llvm::Triple::isOSNaCl().

◆ isTargetNaCl32()

bool llvm::X86Subtarget::isTargetNaCl32 ( ) const
inline

Definition at line 771 of file X86Subtarget.h.

References is64Bit().

◆ isTargetNaCl64()

bool llvm::X86Subtarget::isTargetNaCl64 ( ) const
inline

◆ isTargetPS4()

bool llvm::X86Subtarget::isTargetPS4 ( ) const
inline

Definition at line 760 of file X86Subtarget.h.

References llvm::Triple::isPS4CPU().

◆ isTargetSolaris()

bool llvm::X86Subtarget::isTargetSolaris ( ) const
inline

Definition at line 759 of file X86Subtarget.h.

References llvm::Triple::isOSSolaris().

Referenced by isLegalToCallImmediateAddr().

◆ isTargetWin32()

bool llvm::X86Subtarget::isTargetWin32 ( ) const
inline

◆ isTargetWin64()

bool llvm::X86Subtarget::isTargetWin64 ( ) const
inline

◆ isTargetWindowsCoreCLR()

bool llvm::X86Subtarget::isTargetWindowsCoreCLR ( ) const
inline

◆ isTargetWindowsCygwin()

bool llvm::X86Subtarget::isTargetWindowsCygwin ( ) const
inline

Definition at line 784 of file X86Subtarget.h.

References llvm::Triple::isWindowsCygwinEnvironment().

◆ isTargetWindowsGNU()

bool llvm::X86Subtarget::isTargetWindowsGNU ( ) const
inline

◆ isTargetWindowsItanium()

bool llvm::X86Subtarget::isTargetWindowsItanium ( ) const
inline

◆ isTargetWindowsMSVC()

bool llvm::X86Subtarget::isTargetWindowsMSVC ( ) const
inline

◆ isUnalignedMem16Slow()

bool llvm::X86Subtarget::isUnalignedMem16Slow ( ) const
inline

◆ isUnalignedMem32Slow()

bool llvm::X86Subtarget::isUnalignedMem32Slow ( ) const
inline

◆ isXRaySupported()

bool llvm::X86Subtarget::isXRaySupported ( ) const
inlineoverride

Definition at line 734 of file X86Subtarget.h.

References is64Bit().

◆ LEAusesAG()

bool llvm::X86Subtarget::LEAusesAG ( ) const
inline

Definition at line 677 of file X86Subtarget.h.

Referenced by isLEA().

◆ padShortFunctions()

bool llvm::X86Subtarget::padShortFunctions ( ) const
inline

Definition at line 675 of file X86Subtarget.h.

Referenced by llvm::createX86PadShortFunctions().

◆ ParseSubtargetFeatures()

void llvm::X86Subtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  FS 
)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

Referenced by isLegalToCallImmediateAddr().

◆ setPICStyle()

void llvm::X86Subtarget::setPICStyle ( PICStyles::Style  Style)
inline

Definition at line 573 of file X86Subtarget.h.

Referenced by X86Subtarget().

◆ slow3OpsLEA()

bool llvm::X86Subtarget::slow3OpsLEA ( ) const
inline

Definition at line 679 of file X86Subtarget.h.

Referenced by isLEA().

◆ slowIncDec()

bool llvm::X86Subtarget::slowIncDec ( ) const
inline

Definition at line 680 of file X86Subtarget.h.

Referenced by isLEA().

◆ slowLEA()

bool llvm::X86Subtarget::slowLEA ( ) const
inline

Definition at line 678 of file X86Subtarget.h.

Referenced by combineMul(), and isLEA().

◆ slowTwoMemOps()

bool llvm::X86Subtarget::slowTwoMemOps ( ) const
inline

Definition at line 676 of file X86Subtarget.h.

◆ threewayBranchProfitable()

bool llvm::X86Subtarget::threewayBranchProfitable ( ) const
inline

Definition at line 701 of file X86Subtarget.h.

Referenced by findUncondBrI().

◆ useAA()

bool llvm::X86Subtarget::useAA ( ) const
inlineoverride

Definition at line 747 of file X86Subtarget.h.

◆ useAVX512Regs()

bool llvm::X86Subtarget::useAVX512Regs ( ) const
inline

◆ useBWIRegs()

bool llvm::X86Subtarget::useBWIRegs ( ) const
inline

◆ useLeaForSP()

bool llvm::X86Subtarget::useLeaForSP ( ) const
inline

Definition at line 652 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::emitSPUpdate(), and isLEA().

◆ useRetpolineExternalThunk()

bool llvm::X86Subtarget::useRetpolineExternalThunk ( ) const
inline

Definition at line 708 of file X86Subtarget.h.

Referenced by getRetpolineSymbol().

◆ useRetpolineIndirectBranches()

bool llvm::X86Subtarget::useRetpolineIndirectBranches ( ) const
inline

Definition at line 705 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::areJTsAllowed().

◆ useRetpolineIndirectCalls()

bool llvm::X86Subtarget::useRetpolineIndirectCalls ( ) const
inline

◆ useSoftFloat()

bool llvm::X86Subtarget::useSoftFloat ( ) const
inline

Member Data Documentation

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::X86Subtarget::CallLoweringInfo
protected

GlobalISel related APIs.

Definition at line 455 of file X86Subtarget.h.

Referenced by getCallLowering(), and X86Subtarget().

◆ DeprecatedHasMPX

bool llvm::X86Subtarget::DeprecatedHasMPX = false
protected

Deprecated flag for MPX instructions.

Definition at line 369 of file X86Subtarget.h.

◆ DeprecatedUseRetpoline

bool llvm::X86Subtarget::DeprecatedUseRetpoline = false
protected

Deprecated flag, query UseRetpolineIndirectCalls and UseRetpolineIndirectBranches instead.

Definition at line 421 of file X86Subtarget.h.

◆ HasADX

bool llvm::X86Subtarget::HasADX = false
protected

Processor has ADX instructions.

Definition at line 186 of file X86Subtarget.h.

◆ HasAES

bool llvm::X86Subtarget::HasAES = false
protected

Target has AES instructions.

Definition at line 112 of file X86Subtarget.h.

◆ HasBF16

bool llvm::X86Subtarget::HasBF16 = false
protected

Processor has AVX-512 bfloat16 floating-point extensions.

Definition at line 357 of file X86Subtarget.h.

◆ HasBITALG

bool llvm::X86Subtarget::HasBITALG = false
protected

Processor has AVX-512 Bit Algorithms instructions.

Definition at line 363 of file X86Subtarget.h.

◆ HasBMI

bool llvm::X86Subtarget::HasBMI = false
protected

Processor has BMI1 instructions.

Definition at line 168 of file X86Subtarget.h.

◆ HasBMI2

bool llvm::X86Subtarget::HasBMI2 = false
protected

Processor has BMI2 instructions.

Definition at line 171 of file X86Subtarget.h.

◆ HasBranchFusion

bool llvm::X86Subtarget::HasBranchFusion = false
protected

True if the processor supports branch fusion.

Definition at line 301 of file X86Subtarget.h.

◆ HasBWI

bool llvm::X86Subtarget::HasBWI = false
protected

Processor has AVX-512 Byte and Word instructions.

Definition at line 345 of file X86Subtarget.h.

◆ HasCDI

bool llvm::X86Subtarget::HasCDI = false
protected

Processor has AVX-512 Conflict Detection Instructions.

Definition at line 336 of file X86Subtarget.h.

◆ HasCLDEMOTE

bool llvm::X86Subtarget::HasCLDEMOTE = false
protected

Processor has Cache Line Demote instruction.

Definition at line 207 of file X86Subtarget.h.

◆ HasCLFLUSHOPT

bool llvm::X86Subtarget::HasCLFLUSHOPT = false
protected

Processor supports Flush Cache Line instruction.

Definition at line 382 of file X86Subtarget.h.

◆ HasCLWB

bool llvm::X86Subtarget::HasCLWB = false
protected

Processor supports Cache Line Write Back instruction.

Definition at line 385 of file X86Subtarget.h.

◆ HasCLZERO

bool llvm::X86Subtarget::HasCLZERO = false
protected

Processor has Cache Line Zero instruction.

Definition at line 204 of file X86Subtarget.h.

◆ HasCMov

bool llvm::X86Subtarget::HasCMov = false
protected

True if this processor has conditional move instructions (generally pentium pro+).

Definition at line 100 of file X86Subtarget.h.

◆ HasCmpxchg16b

bool llvm::X86Subtarget::HasCmpxchg16b = false
protected

True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips.

Definition at line 243 of file X86Subtarget.h.

◆ HasCmpxchg8b

bool llvm::X86Subtarget::HasCmpxchg8b = false
protected

True if the processor supports CMPXCHG8B.

Definition at line 92 of file X86Subtarget.h.

◆ HasDQI

bool llvm::X86Subtarget::HasDQI = false
protected

Processor has AVX-512 Doubleword and Quadword instructions.

Definition at line 342 of file X86Subtarget.h.

◆ HasENQCMD

bool llvm::X86Subtarget::HasENQCMD = false
protected

Processor supports ENQCMD instructions.

Definition at line 360 of file X86Subtarget.h.

◆ HasERI

bool llvm::X86Subtarget::HasERI = false
protected

Processor has AVX-512 Exponential and Reciprocal Instructions.

Definition at line 333 of file X86Subtarget.h.

◆ HasERMSB

bool llvm::X86Subtarget::HasERMSB = false
protected

True if the processor has enhanced REP MOVSB/STOSB.

Definition at line 304 of file X86Subtarget.h.

◆ HasF16C

bool llvm::X86Subtarget::HasF16C = false
protected

Processor has 16-bit floating point conversion instructions.

Definition at line 159 of file X86Subtarget.h.

◆ HasFast11ByteNOP

bool llvm::X86Subtarget::HasFast11ByteNOP = false
protected

True if there is no performance penalty for writing NOPs with up to 11 bytes.

Definition at line 265 of file X86Subtarget.h.

◆ HasFast15ByteNOP

bool llvm::X86Subtarget::HasFast15ByteNOP = false
protected

True if there is no performance penalty for writing NOPs with up to 15 bytes.

Definition at line 269 of file X86Subtarget.h.

◆ HasFastBEXTR

bool llvm::X86Subtarget::HasFastBEXTR = false
protected

Processor has a single uop BEXTR implementation.

Definition at line 400 of file X86Subtarget.h.

◆ HasFastGather

bool llvm::X86Subtarget::HasFastGather = false
protected

True if gather is reasonably fast.

This is true for Skylake client and all AVX-512 CPUs.

Definition at line 273 of file X86Subtarget.h.

◆ HasFastHorizontalOps

bool llvm::X86Subtarget::HasFastHorizontalOps = false
protected

Try harder to combine to horizontal vector ops if they are fast.

Definition at line 403 of file X86Subtarget.h.

◆ HasFastLZCNT

bool llvm::X86Subtarget::HasFastLZCNT = false
protected

True if LZCNT instruction is fast.

Definition at line 292 of file X86Subtarget.h.

◆ HasFastPartialYMMorZMMWrite

bool llvm::X86Subtarget::HasFastPartialYMMorZMMWrite = false
protected

True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register without clearing the upper part.

Definition at line 261 of file X86Subtarget.h.

◆ HasFastScalarFSQRT

bool llvm::X86Subtarget::HasFastScalarFSQRT = false
protected

True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration.

Definition at line 277 of file X86Subtarget.h.

◆ HasFastScalarShiftMasks

bool llvm::X86Subtarget::HasFastScalarShiftMasks = false
protected

Prefer a left/right scalar logical shifts pair over a shift+and pair.

Definition at line 406 of file X86Subtarget.h.

◆ HasFastSHLDRotate

bool llvm::X86Subtarget::HasFastSHLDRotate = false
protected

True if SHLD based rotate is fast.

Definition at line 295 of file X86Subtarget.h.

◆ HasFastVariableShuffle

bool llvm::X86Subtarget::HasFastVariableShuffle = false
protected

True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuffles.

Definition at line 257 of file X86Subtarget.h.

◆ HasFastVectorFSQRT

bool llvm::X86Subtarget::HasFastVectorFSQRT = false
protected

True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.

Definition at line 281 of file X86Subtarget.h.

◆ HasFastVectorShiftMasks

bool llvm::X86Subtarget::HasFastVectorShiftMasks = false
protected

Prefer a left/right vector logical shifts pair over a shift+and pair.

Definition at line 409 of file X86Subtarget.h.

◆ HasFMA

bool llvm::X86Subtarget::HasFMA = false
protected

Target has 3-operand fused multiply-add.

Definition at line 138 of file X86Subtarget.h.

◆ HasFMA4

bool llvm::X86Subtarget::HasFMA4 = false
protected

Target has 4-operand fused multiply-add.

Definition at line 141 of file X86Subtarget.h.

◆ HasFSGSBase

bool llvm::X86Subtarget::HasFSGSBase = false
protected

Processor has FS/GS base insturctions.

Definition at line 162 of file X86Subtarget.h.

◆ HasFXSR

bool llvm::X86Subtarget::HasFXSR = false
protected

Target has FXSAVE/FXRESTOR instructions.

Definition at line 116 of file X86Subtarget.h.

◆ HasGFNI

bool llvm::X86Subtarget::HasGFNI = false
protected

Target has Galois Field Arithmetic instructions.

Definition at line 135 of file X86Subtarget.h.

◆ HasIFMA

bool llvm::X86Subtarget::HasIFMA = false
protected

Processor has Integer Fused Multiply Add.

Definition at line 180 of file X86Subtarget.h.

◆ HasINVPCID

bool llvm::X86Subtarget::HasINVPCID = false
protected

Processor supports Invalidate Process-Context Identifier.

Definition at line 376 of file X86Subtarget.h.

◆ HasLAHFSAHF

bool llvm::X86Subtarget::HasLAHFSAHF = false
protected

Processor has LAHF/SAHF instructions.

Definition at line 198 of file X86Subtarget.h.

◆ HasLWP

bool llvm::X86Subtarget::HasLWP = false
protected

Target has LWP instructions.

Definition at line 150 of file X86Subtarget.h.

◆ HasLZCNT

bool llvm::X86Subtarget::HasLZCNT = false
protected

Processor has LZCNT instruction.

Definition at line 165 of file X86Subtarget.h.

◆ HasLZCNTFalseDeps

bool llvm::X86Subtarget::HasLZCNTFalseDeps = false
protected

True if LZCNT/TZCNT instructions have a false dependency on the destination register.

Definition at line 253 of file X86Subtarget.h.

◆ HasMacroFusion

bool llvm::X86Subtarget::HasMacroFusion = false
protected

True if the processor supports macrofusion.

Definition at line 298 of file X86Subtarget.h.

◆ HasMOVBE

bool llvm::X86Subtarget::HasMOVBE = false
protected

True if the processor has the MOVBE instruction.

Definition at line 153 of file X86Subtarget.h.

◆ HasMOVDIR64B

bool llvm::X86Subtarget::HasMOVDIR64B = false
protected

Processor has MOVDIR64B instruction (direct store 64 bytes).

Definition at line 213 of file X86Subtarget.h.

◆ HasMOVDIRI

bool llvm::X86Subtarget::HasMOVDIRI = false
protected

Processor has MOVDIRI instruction (direct store integer).

Definition at line 210 of file X86Subtarget.h.

◆ HasMWAITX

bool llvm::X86Subtarget::HasMWAITX = false
protected

Processor has MONITORX/MWAITX instructions.

Definition at line 201 of file X86Subtarget.h.

◆ HasNOPL

bool llvm::X86Subtarget::HasNOPL = false
protected

True if this processor has NOPL instruction (generally pentium pro+).

Definition at line 96 of file X86Subtarget.h.

◆ HasPCLMUL

bool llvm::X86Subtarget::HasPCLMUL = false
protected

Target has carry-less multiplication.

Definition at line 131 of file X86Subtarget.h.

◆ HasPCONFIG

bool llvm::X86Subtarget::HasPCONFIG = false
protected

Processor supports PCONFIG instruction.

Definition at line 397 of file X86Subtarget.h.

◆ HasPFI

bool llvm::X86Subtarget::HasPFI = false
protected

Processor has AVX-512 PreFetch Instructions.

Definition at line 330 of file X86Subtarget.h.

◆ HasPKU

bool llvm::X86Subtarget::HasPKU = false
protected

Processor has PKU extenstions.

Definition at line 351 of file X86Subtarget.h.

◆ HasPOPCNT

bool llvm::X86Subtarget::HasPOPCNT = false
protected

True if the processor supports POPCNT.

Definition at line 106 of file X86Subtarget.h.

◆ HasPOPCNTFalseDeps

bool llvm::X86Subtarget::HasPOPCNTFalseDeps = false
protected

True if POPCNT instruction has a false dependency on the destination register.

Definition at line 250 of file X86Subtarget.h.

◆ HasPREFETCHWT1

bool llvm::X86Subtarget::HasPREFETCHWT1 = false
protected

Processor has Prefetch with intent to Write instruction.

Definition at line 219 of file X86Subtarget.h.

◆ HasPRFCHW

bool llvm::X86Subtarget::HasPRFCHW = false
protected

Processor has PRFCHW instructions.

Definition at line 192 of file X86Subtarget.h.

◆ HasPTWRITE

bool llvm::X86Subtarget::HasPTWRITE = false
protected

Processor has ptwrite instruction.

Definition at line 216 of file X86Subtarget.h.

◆ HasRDPID

bool llvm::X86Subtarget::HasRDPID = false
protected

Processor support RDPID instruction.

Definition at line 391 of file X86Subtarget.h.

◆ HasRDRAND

bool llvm::X86Subtarget::HasRDRAND = false
protected

True if the processor has the RDRAND instruction.

Definition at line 156 of file X86Subtarget.h.

◆ HasRDSEED

bool llvm::X86Subtarget::HasRDSEED = false
protected

Processor has RDSEED instructions.

Definition at line 195 of file X86Subtarget.h.

◆ HasRTM

bool llvm::X86Subtarget::HasRTM = false
protected

Processor has RTM instructions.

Definition at line 183 of file X86Subtarget.h.

◆ HasSGX

bool llvm::X86Subtarget::HasSGX = false
protected

Processor has Software Guard Extensions.

Definition at line 379 of file X86Subtarget.h.

◆ HasSHA

bool llvm::X86Subtarget::HasSHA = false
protected

Processor has SHA instructions.

Definition at line 189 of file X86Subtarget.h.

◆ HasSHSTK

bool llvm::X86Subtarget::HasSHSTK = false
protected

Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack.

Definition at line 373 of file X86Subtarget.h.

◆ HasSlowDivide32

bool llvm::X86Subtarget::HasSlowDivide32 = false
protected

True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible.

Definition at line 285 of file X86Subtarget.h.

◆ HasSlowDivide64

bool llvm::X86Subtarget::HasSlowDivide64 = false
protected

True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible.

Definition at line 289 of file X86Subtarget.h.

◆ HasSSE4A

bool llvm::X86Subtarget::HasSSE4A = false
protected

True if the processor supports SSE4A instructions.

Definition at line 109 of file X86Subtarget.h.

◆ HasSSEUnalignedMem

bool llvm::X86Subtarget::HasSSEUnalignedMem = false
protected

True if SSE operations can have unaligned memory operands.

This may require setting a configuration bit in the processor.

Definition at line 239 of file X86Subtarget.h.

◆ HasTBM

bool llvm::X86Subtarget::HasTBM = false
protected

Target has TBM instructions.

Definition at line 147 of file X86Subtarget.h.

◆ HasVAES

bool llvm::X86Subtarget::HasVAES = false
protected

Definition at line 113 of file X86Subtarget.h.

◆ HasVBMI

bool llvm::X86Subtarget::HasVBMI = false
protected

Processor has VBMI instructions.

Definition at line 174 of file X86Subtarget.h.

◆ HasVBMI2

bool llvm::X86Subtarget::HasVBMI2 = false
protected

Processor has VBMI2 instructions.

Definition at line 177 of file X86Subtarget.h.

◆ HasVLX

bool llvm::X86Subtarget::HasVLX = false
protected

Processor has AVX-512 Vector Length eXtenstions.

Definition at line 348 of file X86Subtarget.h.

◆ HasVNNI

bool llvm::X86Subtarget::HasVNNI = false
protected

Processor has AVX-512 Vector Neural Network Instructions.

Definition at line 354 of file X86Subtarget.h.

◆ HasVP2INTERSECT

bool llvm::X86Subtarget::HasVP2INTERSECT = false
protected

Processor has AVX-512 vp2intersect instructions.

Definition at line 366 of file X86Subtarget.h.

◆ HasVPCLMULQDQ

bool llvm::X86Subtarget::HasVPCLMULQDQ = false
protected

Definition at line 132 of file X86Subtarget.h.

◆ HasVPOPCNTDQ

bool llvm::X86Subtarget::HasVPOPCNTDQ = false
protected

Processor has AVX-512 population count Instructions.

Definition at line 339 of file X86Subtarget.h.

◆ HasWAITPKG

bool llvm::X86Subtarget::HasWAITPKG = false
protected

Processor supports WaitPKG instructions.

Definition at line 394 of file X86Subtarget.h.

◆ HasWBNOINVD

bool llvm::X86Subtarget::HasWBNOINVD = false
protected

Processor supports Write Back No Invalidate instruction.

Definition at line 388 of file X86Subtarget.h.

◆ HasX86_64

bool llvm::X86Subtarget::HasX86_64 = false
protected

True if the processor supports X86-64 instructions.

Definition at line 103 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasX87

bool llvm::X86Subtarget::HasX87 = false
protected

True if the processor supports X87 instructions.

Definition at line 89 of file X86Subtarget.h.

◆ HasXOP

bool llvm::X86Subtarget::HasXOP = false
protected

Target has XOP instructions.

Definition at line 144 of file X86Subtarget.h.

◆ HasXSAVE

bool llvm::X86Subtarget::HasXSAVE = false
protected

Target has XSAVE instructions.

Definition at line 119 of file X86Subtarget.h.

◆ HasXSAVEC

bool llvm::X86Subtarget::HasXSAVEC = false
protected

Target has XSAVEC instructions.

Definition at line 125 of file X86Subtarget.h.

◆ HasXSAVEOPT

bool llvm::X86Subtarget::HasXSAVEOPT = false
protected

Target has XSAVEOPT instructions.

Definition at line 122 of file X86Subtarget.h.

◆ HasXSAVES

bool llvm::X86Subtarget::HasXSAVES = false
protected

Target has XSAVES instructions.

Definition at line 128 of file X86Subtarget.h.

◆ InstSelector

std::unique_ptr<InstructionSelector> llvm::X86Subtarget::InstSelector
protected

Definition at line 458 of file X86Subtarget.h.

Referenced by getInstructionSelector(), and X86Subtarget().

◆ IsPMADDWDSlow

bool llvm::X86Subtarget::IsPMADDWDSlow = false
protected

True if the PMADDWD instruction is slow compared to PMULLD.

Definition at line 229 of file X86Subtarget.h.

◆ IsPMULLDSlow

bool llvm::X86Subtarget::IsPMULLDSlow = false
protected

True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.

Definition at line 226 of file X86Subtarget.h.

◆ IsSHLDSlow

bool llvm::X86Subtarget::IsSHLDSlow = false
protected

True if SHLD instructions are slow.

Definition at line 222 of file X86Subtarget.h.

◆ IsUAMem16Slow

bool llvm::X86Subtarget::IsUAMem16Slow = false
protected

True if unaligned memory accesses of 16-bytes are slow.

Definition at line 232 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ IsUAMem32Slow

bool llvm::X86Subtarget::IsUAMem32Slow = false
protected

True if unaligned memory accesses of 32-bytes are slow.

Definition at line 235 of file X86Subtarget.h.

◆ LEAUsesAG

bool llvm::X86Subtarget::LEAUsesAG = false
protected

True if the LEA instruction inputs have to be ready at address generation (AG) time.

Definition at line 316 of file X86Subtarget.h.

◆ Legalizer

std::unique_ptr<LegalizerInfo> llvm::X86Subtarget::Legalizer
protected

Definition at line 456 of file X86Subtarget.h.

◆ MaxInlineSizeThreshold

unsigned llvm::X86Subtarget::MaxInlineSizeThreshold = 128
protected

Max.

memset / memcpy size that is turned into rep/movs, rep/stos ops.

Definition at line 440 of file X86Subtarget.h.

◆ PadShortFunctions

bool llvm::X86Subtarget::PadShortFunctions = false
protected

True if the short functions should be padded to prevent a stall when returning too early.

Definition at line 308 of file X86Subtarget.h.

◆ PICStyle

PICStyles::Style llvm::X86Subtarget::PICStyle
protected

Which PIC style to use.

Definition at line 78 of file X86Subtarget.h.

◆ Prefer128Bit

bool llvm::X86Subtarget::Prefer128Bit = false
protected

Indicates target prefers 128 bit instructions.

Definition at line 443 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ Prefer256Bit

bool llvm::X86Subtarget::Prefer256Bit = false
protected

Indicates target prefers 256 bit instructions.

Definition at line 446 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::X86Subtarget::RegBankInfo
protected

Definition at line 457 of file X86Subtarget.h.

Referenced by getRegBankInfo(), and X86Subtarget().

◆ Slow3OpsLEA

bool llvm::X86Subtarget::Slow3OpsLEA = false
protected

True if the LEA instruction has all three source operands: base, index, and offset or if the LEA instruction uses base and index registers where the base is EBP, RBP,or R13.

Definition at line 324 of file X86Subtarget.h.

◆ SlowIncDec

bool llvm::X86Subtarget::SlowIncDec = false
protected

True if INC and DEC instructions are slow when writing to flags.

Definition at line 327 of file X86Subtarget.h.

◆ SlowLEA

bool llvm::X86Subtarget::SlowLEA = false
protected

True if the LEA instruction with certain arguments is slow.

Definition at line 319 of file X86Subtarget.h.

◆ SlowTwoMemOps

bool llvm::X86Subtarget::SlowTwoMemOps = false
protected

True if two memory operand instructions should use a temporary register instead.

Definition at line 312 of file X86Subtarget.h.

◆ stackAlignment

Align llvm::X86Subtarget::stackAlignment = Align(4)
protected

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 435 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ TargetTriple

Triple llvm::X86Subtarget::TargetTriple
protected

What processor and OS we're targeting.

Definition at line 452 of file X86Subtarget.h.

◆ ThreewayBranchProfitable

bool llvm::X86Subtarget::ThreewayBranchProfitable = false
protected

Threeway branch is profitable in this subtarget.

Definition at line 449 of file X86Subtarget.h.

◆ TM

const TargetMachine& llvm::X86Subtarget::TM
protected

◆ UseAA

bool llvm::X86Subtarget::UseAA = false
protected

Use alias analysis during code generation.

Definition at line 431 of file X86Subtarget.h.

◆ UseLeaForSP

bool llvm::X86Subtarget::UseLeaForSP = false
protected

True if the LEA instruction should be used for adjusting the stack pointer.

This is an optimization for Intel Atom processors.

Definition at line 247 of file X86Subtarget.h.

◆ UseRetpolineExternalThunk

bool llvm::X86Subtarget::UseRetpolineExternalThunk = false
protected

When using a retpoline thunk, call an externally provided thunk rather than emitting one inside the compiler.

Definition at line 425 of file X86Subtarget.h.

◆ UseRetpolineIndirectBranches

bool llvm::X86Subtarget::UseRetpolineIndirectBranches = false
protected

Use a retpoline thunk or remove any indirect branch to block speculative execution.

Definition at line 417 of file X86Subtarget.h.

◆ UseRetpolineIndirectCalls

bool llvm::X86Subtarget::UseRetpolineIndirectCalls = false
protected

Use a retpoline thunk rather than indirect calls to block speculative execution.

Definition at line 413 of file X86Subtarget.h.

◆ UseSoftFloat

bool llvm::X86Subtarget::UseSoftFloat = false
protected

Use software floating point for code generation.

Definition at line 428 of file X86Subtarget.h.

◆ X863DNowLevel

X863DNowEnum llvm::X86Subtarget::X863DNowLevel = NoThreeDNow
protected

MMX, 3DNow, 3DNow Athlon, or none supported.

Definition at line 86 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ X86ProcFamily

X86ProcFamilyEnum llvm::X86Subtarget::X86ProcFamily = Others
protected

X86 processor family: Intel Atom, and others.

Definition at line 75 of file X86Subtarget.h.

◆ X86SSELevel

X86SSEEnum llvm::X86Subtarget::X86SSELevel = NoSSE
protected

SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.

Definition at line 83 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().


The documentation for this class was generated from the following files: