LLVM  7.0.0svn
Public Types | Public Member Functions | Protected Types | Protected Attributes | List of all members
llvm::X86Subtarget Class Referencefinal

#include "Target/X86/X86Subtarget.h"

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Public Types

enum  X86ProcFamilyEnum {
  Others, IntelAtom, IntelSLM, IntelGLM,
  IntelGLP, IntelTRM, IntelHaswell, IntelBroadwell,
  IntelSkylake, IntelKNL, IntelSKX, IntelCannonlake,
  IntelIcelakeClient, IntelIcelakeServer
}
 

Public Member Functions

 X86Subtarget (const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride, unsigned PreferVectorWidthOverride, unsigned RequiredVectorWidth)
 This constructor initializes the data members to match that of the specified triple. More...
 
const X86TargetLoweringgetTargetLowering () const override
 
const X86InstrInfogetInstrInfo () const override
 
const X86FrameLoweringgetFrameLowering () const override
 
const X86SelectionDAGInfogetSelectionDAGInfo () const override
 
const X86RegisterInfogetRegisterInfo () const override
 
unsigned getStackAlignment () const
 Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...
 
unsigned getMaxInlineSizeThreshold () const
 Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...
 
void ParseSubtargetFeatures (StringRef CPU, StringRef FS)
 ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...
 
const CallLoweringgetCallLowering () const override
 Methods used by Global ISel. More...
 
const InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
bool is64Bit () const
 Is this x86_64? (disregarding specific ABI / programming model) More...
 
bool is32Bit () const
 
bool is16Bit () const
 
bool isTarget64BitILP32 () const
 Is this x86_64 with the ILP32 programming model (x32 ABI)? More...
 
bool isTarget64BitLP64 () const
 Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? More...
 
PICStyles::Style getPICStyle () const
 
void setPICStyle (PICStyles::Style Style)
 
bool hasX87 () const
 
bool hasNOPL () const
 
bool hasCMov () const
 
bool hasSSE1 () const
 
bool hasSSE2 () const
 
bool hasSSE3 () const
 
bool hasSSSE3 () const
 
bool hasSSE41 () const
 
bool hasSSE42 () const
 
bool hasAVX () const
 
bool hasAVX2 () const
 
bool hasAVX512 () const
 
bool hasInt256 () const
 
bool hasSSE4A () const
 
bool hasMMX () const
 
bool has3DNow () const
 
bool has3DNowA () const
 
bool hasPOPCNT () const
 
bool hasAES () const
 
bool hasVAES () const
 
bool hasFXSR () const
 
bool hasXSAVE () const
 
bool hasXSAVEOPT () const
 
bool hasXSAVEC () const
 
bool hasXSAVES () const
 
bool hasPCLMUL () const
 
bool hasVPCLMULQDQ () const
 
bool hasGFNI () const
 
bool hasFMA () const
 
bool hasFMA4 () const
 
bool hasAnyFMA () const
 
bool hasXOP () const
 
bool hasTBM () const
 
bool hasLWP () const
 
bool hasMOVBE () const
 
bool hasRDRAND () const
 
bool hasF16C () const
 
bool hasFSGSBase () const
 
bool hasLZCNT () const
 
bool hasBMI () const
 
bool hasBMI2 () const
 
bool hasVBMI () const
 
bool hasVBMI2 () const
 
bool hasIFMA () const
 
bool hasRTM () const
 
bool hasADX () const
 
bool hasSHA () const
 
bool hasPRFCHW () const
 
bool hasPREFETCHWT1 () const
 
bool hasSSEPrefetch () const
 
bool hasRDSEED () const
 
bool hasLAHFSAHF () const
 
bool hasMWAITX () const
 
bool hasCLZERO () const
 
bool hasCLDEMOTE () const
 
bool hasMOVDIRI () const
 
bool hasMOVDIR64B () const
 
bool hasPTWRITE () const
 
bool isSHLDSlow () const
 
bool isPMULLDSlow () const
 
bool isUnalignedMem16Slow () const
 
bool isUnalignedMem32Slow () const
 
int getGatherOverhead () const
 
int getScatterOverhead () const
 
bool hasSSEUnalignedMem () const
 
bool hasCmpxchg16b () const
 
bool useLeaForSP () const
 
bool hasPOPCNTFalseDeps () const
 
bool hasLZCNTFalseDeps () const
 
bool hasFastVariableShuffle () const
 
bool hasFastPartialYMMorZMMWrite () const
 
bool hasFastGather () const
 
bool hasFastScalarFSQRT () const
 
bool hasFastVectorFSQRT () const
 
bool hasFastLZCNT () const
 
bool hasFastSHLDRotate () const
 
bool hasMacroFusion () const
 
bool hasERMSB () const
 
bool hasSlowDivide32 () const
 
bool hasSlowDivide64 () const
 
bool padShortFunctions () const
 
bool slowTwoMemOps () const
 
bool LEAusesAG () const
 
bool slowLEA () const
 
bool slow3OpsLEA () const
 
bool slowIncDec () const
 
bool hasCDI () const
 
bool hasVPOPCNTDQ () const
 
bool hasPFI () const
 
bool hasERI () const
 
bool hasDQI () const
 
bool hasBWI () const
 
bool hasVLX () const
 
bool hasPKU () const
 
bool hasVNNI () const
 
bool hasBITALG () const
 
bool hasMPX () const
 
bool hasSHSTK () const
 
bool hasCLFLUSHOPT () const
 
bool hasCLWB () const
 
bool hasWBNOINVD () const
 
bool hasRDPID () const
 
bool hasWAITPKG () const
 
bool hasPCONFIG () const
 
bool hasSGX () const
 
bool hasINVPCID () const
 
bool useRetpoline () const
 
bool useRetpolineExternalThunk () const
 
unsigned getPreferVectorWidth () const
 
unsigned getRequiredVectorWidth () const
 
bool canExtendTo512DQ () const
 
bool canExtendTo512BW () const
 
bool useAVX512Regs () const
 
bool useBWIRegs () const
 
bool isXRaySupported () const override
 
X86ProcFamilyEnum getProcFamily () const
 
bool isAtom () const
 TODO: to be removed later and replaced with suitable properties. More...
 
bool isSLM () const
 
bool isGLM () const
 
bool useSoftFloat () const
 
bool hasMFence () const
 Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2). More...
 
const TriplegetTargetTriple () const
 
bool isTargetDarwin () const
 
bool isTargetFreeBSD () const
 
bool isTargetDragonFly () const
 
bool isTargetSolaris () const
 
bool isTargetPS4 () const
 
bool isTargetELF () const
 
bool isTargetCOFF () const
 
bool isTargetMachO () const
 
bool isTargetLinux () const
 
bool isTargetKFreeBSD () const
 
bool isTargetGlibc () const
 
bool isTargetAndroid () const
 
bool isTargetNaCl () const
 
bool isTargetNaCl32 () const
 
bool isTargetNaCl64 () const
 
bool isTargetMCU () const
 
bool isTargetFuchsia () const
 
bool isTargetWindowsMSVC () const
 
bool isTargetKnownWindowsMSVC () const
 
bool isTargetWindowsCoreCLR () const
 
bool isTargetWindowsCygwin () const
 
bool isTargetWindowsGNU () const
 
bool isTargetWindowsItanium () const
 
bool isTargetCygMing () const
 
bool isOSWindows () const
 
bool isTargetWin64 () const
 
bool isTargetWin32 () const
 
bool isPICStyleGOT () const
 
bool isPICStyleRIPRel () const
 
bool isPICStyleStubPIC () const
 
bool isPositionIndependent () const
 
bool isCallingConvWin64 (CallingConv::ID CC) const
 
unsigned char classifyLocalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalReference (const GlobalValue *GV, const Module &M) const
 
unsigned char classifyGlobalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV, const Module &M) const
 Classify a global function reference for the current subtarget. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV) const
 
unsigned char classifyBlockAddressReference () const
 Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
bool isLegalToCallImmediateAddr () const
 Return true if the subtarget allows calls to immediate address. More...
 
bool enableIndirectBrExpand () const override
 If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect jump. More...
 
bool enableMachineScheduler () const override
 Enable the MachineScheduler pass for all X86 subtargets. More...
 
bool supportPrintSchedInfo () const override
 
bool enableEarlyIfConversion () const override
 
AntiDepBreakMode getAntiDepBreakMode () const override
 
bool enableAdvancedRASplitCost () const override
 

Protected Types

enum  X86SSEEnum {
  NoSSE, SSE1, SSE2, SSE3,
  SSSE3, SSE41, SSE42, AVX,
  AVX2, AVX512F
}
 
enum  X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA }
 

Protected Attributes

X86ProcFamilyEnum X86ProcFamily
 X86 processor family: Intel Atom, and others. More...
 
PICStyles::Style PICStyle
 Which PIC style to use. More...
 
const TargetMachineTM
 
X86SSEEnum X86SSELevel
 SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. More...
 
X863DNowEnum X863DNowLevel
 MMX, 3DNow, 3DNow Athlon, or none supported. More...
 
bool HasX87
 True if the processor supports X87 instructions. More...
 
bool HasNOPL
 True if this processor has NOPL instruction (generally pentium pro+). More...
 
bool HasCMov
 True if this processor has conditional move instructions (generally pentium pro+). More...
 
bool HasX86_64
 True if the processor supports X86-64 instructions. More...
 
bool HasPOPCNT
 True if the processor supports POPCNT. More...
 
bool HasSSE4A
 True if the processor supports SSE4A instructions. More...
 
bool HasAES
 Target has AES instructions. More...
 
bool HasVAES
 
bool HasFXSR
 Target has FXSAVE/FXRESTOR instructions. More...
 
bool HasXSAVE
 Target has XSAVE instructions. More...
 
bool HasXSAVEOPT
 Target has XSAVEOPT instructions. More...
 
bool HasXSAVEC
 Target has XSAVEC instructions. More...
 
bool HasXSAVES
 Target has XSAVES instructions. More...
 
bool HasPCLMUL
 Target has carry-less multiplication. More...
 
bool HasVPCLMULQDQ
 
bool HasGFNI
 Target has Galois Field Arithmetic instructions. More...
 
bool HasFMA
 Target has 3-operand fused multiply-add. More...
 
bool HasFMA4
 Target has 4-operand fused multiply-add. More...
 
bool HasXOP
 Target has XOP instructions. More...
 
bool HasTBM
 Target has TBM instructions. More...
 
bool HasLWP
 Target has LWP instructions. More...
 
bool HasMOVBE
 True if the processor has the MOVBE instruction. More...
 
bool HasRDRAND
 True if the processor has the RDRAND instruction. More...
 
bool HasF16C
 Processor has 16-bit floating point conversion instructions. More...
 
bool HasFSGSBase
 Processor has FS/GS base insturctions. More...
 
bool HasLZCNT
 Processor has LZCNT instruction. More...
 
bool HasBMI
 Processor has BMI1 instructions. More...
 
bool HasBMI2
 Processor has BMI2 instructions. More...
 
bool HasVBMI
 Processor has VBMI instructions. More...
 
bool HasVBMI2
 Processor has VBMI2 instructions. More...
 
bool HasIFMA
 Processor has Integer Fused Multiply Add. More...
 
bool HasRTM
 Processor has RTM instructions. More...
 
bool HasADX
 Processor has ADX instructions. More...
 
bool HasSHA
 Processor has SHA instructions. More...
 
bool HasPRFCHW
 Processor has PRFCHW instructions. More...
 
bool HasRDSEED
 Processor has RDSEED instructions. More...
 
bool HasLAHFSAHF
 Processor has LAHF/SAHF instructions. More...
 
bool HasMWAITX
 Processor has MONITORX/MWAITX instructions. More...
 
bool HasCLZERO
 Processor has Cache Line Zero instruction. More...
 
bool HasCLDEMOTE
 Processor has Cache Line Demote instruction. More...
 
bool HasMOVDIRI
 Processor has MOVDIRI instruction (direct store integer). More...
 
bool HasMOVDIR64B
 Processor has MOVDIR64B instruction (direct store 64 bytes). More...
 
bool HasPTWRITE
 Processor has ptwrite instruction. More...
 
bool HasPREFETCHWT1
 Processor has Prefetch with intent to Write instruction. More...
 
bool IsSHLDSlow
 True if SHLD instructions are slow. More...
 
bool IsPMULLDSlow
 True if the PMULLD instruction is slow compared to PMULLW/PMULHW and. More...
 
bool IsUAMem16Slow
 True if unaligned memory accesses of 16-bytes are slow. More...
 
bool IsUAMem32Slow
 True if unaligned memory accesses of 32-bytes are slow. More...
 
bool HasSSEUnalignedMem
 True if SSE operations can have unaligned memory operands. More...
 
bool HasCmpxchg16b
 True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips. More...
 
bool UseLeaForSP
 True if the LEA instruction should be used for adjusting the stack pointer. More...
 
bool HasPOPCNTFalseDeps
 True if POPCNT instruction has a false dependency on the destination register. More...
 
bool HasLZCNTFalseDeps
 True if LZCNT/TZCNT instructions have a false dependency on the destination register. More...
 
bool HasFastVariableShuffle
 True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuffles. More...
 
bool HasFastPartialYMMorZMMWrite
 True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register without clearing the upper part. More...
 
bool HasFast11ByteNOP
 True if there is no performance penalty for writing NOPs with up to 11 bytes. More...
 
bool HasFast15ByteNOP
 True if there is no performance penalty for writing NOPs with up to 15 bytes. More...
 
bool HasFastGather
 True if gather is reasonably fast. More...
 
bool HasFastScalarFSQRT
 True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration. More...
 
bool HasFastVectorFSQRT
 True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. More...
 
bool HasSlowDivide32
 True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible. More...
 
bool HasSlowDivide64
 True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible. More...
 
bool HasFastLZCNT
 True if LZCNT instruction is fast. More...
 
bool HasFastSHLDRotate
 True if SHLD based rotate is fast. More...
 
bool HasMacroFusion
 True if the processor supports macrofusion. More...
 
bool HasERMSB
 True if the processor has enhanced REP MOVSB/STOSB. More...
 
bool PadShortFunctions
 True if the short functions should be padded to prevent a stall when returning too early. More...
 
bool SlowTwoMemOps
 True if two memory operand instructions should use a temporary register instead. More...
 
bool LEAUsesAG
 True if the LEA instruction inputs have to be ready at address generation (AG) time. More...
 
bool SlowLEA
 True if the LEA instruction with certain arguments is slow. More...
 
bool Slow3OpsLEA
 True if the LEA instruction has all three source operands: base, index, and offset or if the LEA instruction uses base and index registers where the base is EBP, RBP,or R13. More...
 
bool SlowIncDec
 True if INC and DEC instructions are slow when writing to flags. More...
 
bool HasPFI
 Processor has AVX-512 PreFetch Instructions. More...
 
bool HasERI
 Processor has AVX-512 Exponential and Reciprocal Instructions. More...
 
bool HasCDI
 Processor has AVX-512 Conflict Detection Instructions. More...
 
bool HasVPOPCNTDQ
 Processor has AVX-512 population count Instructions. More...
 
bool HasDQI
 Processor has AVX-512 Doubleword and Quadword instructions. More...
 
bool HasBWI
 Processor has AVX-512 Byte and Word instructions. More...
 
bool HasVLX
 Processor has AVX-512 Vector Length eXtenstions. More...
 
bool HasPKU
 Processor has PKU extenstions. More...
 
bool HasVNNI
 Processor has AVX-512 Vector Neural Network Instructions. More...
 
bool HasBITALG
 Processor has AVX-512 Bit Algorithms instructions. More...
 
bool HasMPX
 Processor supports MPX - Memory Protection Extensions. More...
 
bool HasSHSTK
 Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack. More...
 
bool HasINVPCID
 Processor supports Invalidate Process-Context Identifier. More...
 
bool HasSGX
 Processor has Software Guard Extensions. More...
 
bool HasCLFLUSHOPT
 Processor supports Flush Cache Line instruction. More...
 
bool HasCLWB
 Processor supports Cache Line Write Back instruction. More...
 
bool HasWBNOINVD
 Processor supports Write Back No Invalidate instruction. More...
 
bool HasRDPID
 Processor support RDPID instruction. More...
 
bool HasWAITPKG
 Processor supports WaitPKG instructions. More...
 
bool HasPCONFIG
 Processor supports PCONFIG instruction. More...
 
bool UseRetpoline
 Use a retpoline thunk rather than indirect calls to block speculative execution. More...
 
bool UseRetpolineExternalThunk
 When using a retpoline thunk, call an externally provided thunk rather than emitting one inside the compiler. More...
 
bool UseSoftFloat
 Use software floating point for code generation. More...
 
unsigned stackAlignment
 The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...
 
unsigned MaxInlineSizeThreshold
 Max. More...
 
bool Prefer256Bit
 Indicates target prefers 256 bit instructions. More...
 
Triple TargetTriple
 What processor and OS we're targeting. More...
 
std::unique_ptr< CallLoweringCallLoweringInfo
 GlobalISel related APIs. More...
 
std::unique_ptr< LegalizerInfoLegalizer
 
std::unique_ptr< RegisterBankInfoRegBankInfo
 
std::unique_ptr< InstructionSelectorInstSelector
 

Detailed Description

Definition at line 52 of file X86Subtarget.h.

Member Enumeration Documentation

◆ X863DNowEnum

Enumerator
NoThreeDNow 
MMX 
ThreeDNow 
ThreeDNowA 

Definition at line 76 of file X86Subtarget.h.

◆ X86ProcFamilyEnum

Enumerator
Others 
IntelAtom 
IntelSLM 
IntelGLM 
IntelGLP 
IntelTRM 
IntelHaswell 
IntelBroadwell 
IntelSkylake 
IntelKNL 
IntelSKX 
IntelCannonlake 
IntelIcelakeClient 
IntelIcelakeServer 

Definition at line 54 of file X86Subtarget.h.

◆ X86SSEEnum

Enumerator
NoSSE 
SSE1 
SSE2 
SSE3 
SSSE3 
SSE41 
SSE42 
AVX 
AVX2 
AVX512F 

Definition at line 72 of file X86Subtarget.h.

Constructor & Destructor Documentation

◆ X86Subtarget()

X86Subtarget::X86Subtarget ( const Triple TT,
StringRef  CPU,
StringRef  FS,
const X86TargetMachine TM,
unsigned  StackAlignOverride,
unsigned  PreferVectorWidthOverride,
unsigned  RequiredVectorWidth 
)

Member Function Documentation

◆ canExtendTo512BW()

bool llvm::X86Subtarget::canExtendTo512BW ( ) const
inline

Definition at line 664 of file X86Subtarget.h.

Referenced by lower1BitVectorShuffle(), LowerMULH(), and LowerShift().

◆ canExtendTo512DQ()

bool llvm::X86Subtarget::canExtendTo512DQ ( ) const
inline

◆ classifyBlockAddressReference()

unsigned char X86Subtarget::classifyBlockAddressReference ( ) const

Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 58 of file X86Subtarget.cpp.

References classifyLocalReference().

Referenced by getRetpolineSymbol(), and LowerEXTRACT_SUBVECTOR().

◆ classifyGlobalFunctionReference() [1/2]

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV,
const Module M 
) const

◆ classifyGlobalFunctionReference() [2/2]

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV) const

◆ classifyGlobalReference() [1/2]

unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV,
const Module M 
) const

◆ classifyGlobalReference() [2/2]

unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV) const

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 65 of file X86Subtarget.cpp.

References classifyGlobalReference(), and llvm::GlobalValue::getParent().

◆ classifyLocalReference()

unsigned char X86Subtarget::classifyLocalReference ( const GlobalValue GV) const

◆ enableAdvancedRASplitCost()

bool llvm::X86Subtarget::enableAdvancedRASplitCost ( ) const
inlineoverride

Definition at line 820 of file X86Subtarget.h.

◆ enableEarlyIfConversion()

bool X86Subtarget::enableEarlyIfConversion ( ) const
override

Definition at line 434 of file X86Subtarget.cpp.

References hasCMov(), and X86EarlyIfConv.

◆ enableIndirectBrExpand()

bool llvm::X86Subtarget::enableIndirectBrExpand ( ) const
inlineoverride

If we are using retpolines, we need to expand indirectbr to avoid it lowering to an actual indirect jump.

Definition at line 806 of file X86Subtarget.h.

◆ enableMachineScheduler()

bool llvm::X86Subtarget::enableMachineScheduler ( ) const
inlineoverride

Enable the MachineScheduler pass for all X86 subtargets.

Definition at line 809 of file X86Subtarget.h.

◆ getAntiDepBreakMode()

AntiDepBreakMode llvm::X86Subtarget::getAntiDepBreakMode ( ) const
inlineoverride

Definition at line 816 of file X86Subtarget.h.

◆ getCallLowering()

const CallLowering * X86Subtarget::getCallLowering ( ) const
override

Methods used by Global ISel.

Definition at line 418 of file X86Subtarget.cpp.

References CallLoweringInfo.

◆ getFrameLowering()

const X86FrameLowering* llvm::X86Subtarget::getFrameLowering ( ) const
inlineoverride

◆ getGatherOverhead()

int llvm::X86Subtarget::getGatherOverhead ( ) const
inline

Definition at line 603 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::getUserCost().

◆ getInstrInfo()

const X86InstrInfo* llvm::X86Subtarget::getInstrInfo ( ) const
inlineoverride

◆ getInstructionSelector()

const InstructionSelector * X86Subtarget::getInstructionSelector ( ) const
override

Definition at line 422 of file X86Subtarget.cpp.

References InstSelector.

◆ getLegalizerInfo()

const LegalizerInfo * X86Subtarget::getLegalizerInfo ( ) const
override

Definition at line 426 of file X86Subtarget.cpp.

◆ getMaxInlineSizeThreshold()

unsigned llvm::X86Subtarget::getMaxInlineSizeThreshold ( ) const
inline

Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 486 of file X86Subtarget.h.

◆ getPICStyle()

PICStyles::Style llvm::X86Subtarget::getPICStyle ( ) const
inline

Definition at line 531 of file X86Subtarget.h.

◆ getPreferVectorWidth()

unsigned llvm::X86Subtarget::getPreferVectorWidth ( ) const
inline

Definition at line 654 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::getRegisterBitWidth().

◆ getProcFamily()

X86ProcFamilyEnum llvm::X86Subtarget::getProcFamily ( ) const
inline

Definition at line 680 of file X86Subtarget.h.

Referenced by combineMulToPMADDWD().

◆ getRegBankInfo()

const RegisterBankInfo * X86Subtarget::getRegBankInfo ( ) const
override

Definition at line 430 of file X86Subtarget.cpp.

References RegBankInfo.

◆ getRegisterInfo()

const X86RegisterInfo* llvm::X86Subtarget::getRegisterInfo ( ) const
inlineoverride

◆ getRequiredVectorWidth()

unsigned llvm::X86Subtarget::getRequiredVectorWidth ( ) const
inline

Definition at line 655 of file X86Subtarget.h.

◆ getScatterOverhead()

int llvm::X86Subtarget::getScatterOverhead ( ) const
inline

Definition at line 604 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::getUserCost().

◆ getSelectionDAGInfo()

const X86SelectionDAGInfo* llvm::X86Subtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 471 of file X86Subtarget.h.

◆ getStackAlignment()

unsigned llvm::X86Subtarget::getStackAlignment ( ) const
inline

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 482 of file X86Subtarget.h.

◆ getTargetLowering()

const X86TargetLowering* llvm::X86Subtarget::getTargetLowering ( ) const
inlineoverride

◆ getTargetTriple()

const Triple& llvm::X86Subtarget::getTargetTriple ( ) const
inline

◆ has3DNow()

bool llvm::X86Subtarget::has3DNow ( ) const
inline

Definition at line 549 of file X86Subtarget.h.

References llvm::X86II::ThreeDNow.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ has3DNowA()

bool llvm::X86Subtarget::has3DNowA ( ) const
inline

Definition at line 550 of file X86Subtarget.h.

◆ hasADX()

bool llvm::X86Subtarget::hasADX ( ) const
inline

Definition at line 581 of file X86Subtarget.h.

◆ hasAES()

bool llvm::X86Subtarget::hasAES ( ) const
inline

Definition at line 552 of file X86Subtarget.h.

◆ hasAnyFMA()

bool llvm::X86Subtarget::hasAnyFMA ( ) const
inline

◆ hasAVX()

bool llvm::X86Subtarget::hasAVX ( ) const
inline

Definition at line 543 of file X86Subtarget.h.

Referenced by callHasRegMask(), combineBasicSADPattern(), combineBitcastvxi1(), combineFaddFsub(), combineFMinNumFMaxNum(), combineHorizontalPredicateResult(), combineLoopMAddPattern(), combineLoopSADPattern(), combineSelect(), combineSubToSubus(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), createVariablePermute(), emitClzero(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaxInterleaveFactor(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), hasNonFlagsUse(), InsertBitToMaskVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), LowerANY_EXTEND(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerShift(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerV2F64VectorShuffle(), lowerV4F32VectorShuffle(), lowerVectorShuffleAsBroadcast(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), X86ChooseCmpOpcode(), llvm::X86LegalizerInfo::X86LegalizerInfo(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasAVX2()

bool llvm::X86Subtarget::hasAVX2 ( ) const
inline

Definition at line 544 of file X86Subtarget.h.

Referenced by combineHorizontalPredicateResult(), combineSelect(), combineShuffleOfConcatUndef(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), combineX86ShuffleChain(), createVariablePermute(), llvm::X86TTIImpl::enableMemCmpExpansion(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getShuffleCost(), InsertBitToMaskVector(), llvm::X86TargetLowering::isDesirableToCombineBuildVectorToShuffleTruncate(), llvm::X86TTIImpl::isLegalMaskedGather(), isLegalToCallImmediateAddr(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), lower256BitVectorShuffle(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerMGATHER(), LowerRotate(), lowerShuffleAsRepeatedMaskAndLanePermute(), LowerToHorizontalOp(), lowerV16I16VectorShuffle(), lowerV2X128VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8I32VectorShuffle(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithUndefHalf(), lowerVSELECTtoVectorShuffle(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), SplitOpsAndApply(), and llvm::X86LegalizerInfo::X86LegalizerInfo().

◆ hasAVX512()

bool llvm::X86Subtarget::hasAVX512 ( ) const
inline

Definition at line 545 of file X86Subtarget.h.

Referenced by combineBitcast(), combineBitcastvxi1(), combineCastedMaskArithmetic(), combineCompareEqual(), combineExtSetcc(), combineGatherScatter(), combineMaskedLoad(), combineSelect(), combineSetCC(), combineStore(), combineToExtendBoolVectorInReg(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), llvm::X86TargetLowering::convertSelectOfConstantsToMath(), CopyToFromAsymmetricReg(), createVariablePermute(), EmitKTEST(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getGatherScatterOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::X86RegisterInfo::getReservedRegs(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), llvm::X86TTIImpl::getUserCost(), llvm::X86TTIImpl::isLegalMaskedGather(), llvm::X86TTIImpl::isLegalMaskedScatter(), isLegalToCallImmediateAddr(), isSATValidOnAVX512Subtarget(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), lower1BitVectorShuffle(), lower512BitVectorShuffle(), LowerBITCAST(), LowerBUILD_VECTORAsVariablePermute(), LowerEXTEND_VECTOR_INREG(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL_LOHI(), LowerRotate(), LowerScalarImmediateShift(), LowerStore(), LowerTruncateVecI1(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerV8F32VectorShuffle(), lowerV8I32VectorShuffle(), LowerVSETCC(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), truncateVectorWithPACK(), X86ChooseCmpOpcode(), llvm::X86LegalizerInfo::X86LegalizerInfo(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasBITALG()

bool llvm::X86Subtarget::hasBITALG ( ) const
inline

Definition at line 640 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasBMI()

bool llvm::X86Subtarget::hasBMI ( ) const
inline

◆ hasBMI2()

bool llvm::X86Subtarget::hasBMI2 ( ) const
inline

Definition at line 576 of file X86Subtarget.h.

Referenced by hasBZHI().

◆ hasBWI()

bool llvm::X86Subtarget::hasBWI ( ) const
inline

Definition at line 636 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), combineSelect(), combineSetCC(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), createVariablePermute(), EmitKTEST(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getLoadStoreRegOpcode(), getMaskNode(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getv64i1Argument(), getZeroVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), isSATValidOnAVX512Subtarget(), isTruncWithZeroHighBitsInput(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), lower1BitVectorShuffle(), LowerBITCAST(), LowerLoad(), LowerMLOAD(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerShift(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV32I16VectorShuffle(), lowerV64I8VectorShuffle(), LowerVectorCTLZ(), LowerVectorCTPOP(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleWithPSHUFB(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchVectorShuffleAsShift(), Passv64i1ArgInRegs(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), llvm::X86LegalizerInfo::X86LegalizerInfo(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasCDI()

bool llvm::X86Subtarget::hasCDI ( ) const
inline

◆ hasCLDEMOTE()

bool llvm::X86Subtarget::hasCLDEMOTE ( ) const
inline

Definition at line 595 of file X86Subtarget.h.

◆ hasCLFLUSHOPT()

bool llvm::X86Subtarget::hasCLFLUSHOPT ( ) const
inline

Definition at line 643 of file X86Subtarget.h.

◆ hasCLWB()

bool llvm::X86Subtarget::hasCLWB ( ) const
inline

Definition at line 644 of file X86Subtarget.h.

◆ hasCLZERO()

bool llvm::X86Subtarget::hasCLZERO ( ) const
inline

Definition at line 594 of file X86Subtarget.h.

◆ hasCMov()

bool llvm::X86Subtarget::hasCMov ( ) const
inline

◆ hasCmpxchg16b()

bool llvm::X86Subtarget::hasCmpxchg16b ( ) const
inline

Definition at line 606 of file X86Subtarget.h.

Referenced by LowerXALUO(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasDQI()

bool llvm::X86Subtarget::hasDQI ( ) const
inline

◆ hasERI()

bool llvm::X86Subtarget::hasERI ( ) const
inline

Definition at line 634 of file X86Subtarget.h.

◆ hasERMSB()

bool llvm::X86Subtarget::hasERMSB ( ) const
inline

Definition at line 622 of file X86Subtarget.h.

◆ hasF16C()

bool llvm::X86Subtarget::hasF16C ( ) const
inline

Definition at line 572 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasFastGather()

bool llvm::X86Subtarget::hasFastGather ( ) const
inline

◆ hasFastLZCNT()

bool llvm::X86Subtarget::hasFastLZCNT ( ) const
inline

Definition at line 619 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::isCtlzFast().

◆ hasFastPartialYMMorZMMWrite()

bool llvm::X86Subtarget::hasFastPartialYMMorZMMWrite ( ) const
inline

Definition at line 613 of file X86Subtarget.h.

Referenced by callHasRegMask().

◆ hasFastScalarFSQRT()

bool llvm::X86Subtarget::hasFastScalarFSQRT ( ) const
inline

Definition at line 617 of file X86Subtarget.h.

Referenced by hasNonFlagsUse().

◆ hasFastSHLDRotate()

bool llvm::X86Subtarget::hasFastSHLDRotate ( ) const
inline

Definition at line 620 of file X86Subtarget.h.

◆ hasFastVariableShuffle()

bool llvm::X86Subtarget::hasFastVariableShuffle ( ) const
inline

Definition at line 610 of file X86Subtarget.h.

Referenced by combineX86ShuffleChain().

◆ hasFastVectorFSQRT()

bool llvm::X86Subtarget::hasFastVectorFSQRT ( ) const
inline

Definition at line 618 of file X86Subtarget.h.

Referenced by hasNonFlagsUse().

◆ hasFMA()

bool llvm::X86Subtarget::hasFMA ( ) const
inline

Definition at line 564 of file X86Subtarget.h.

◆ hasFMA4()

bool llvm::X86Subtarget::hasFMA4 ( ) const
inline

Definition at line 565 of file X86Subtarget.h.

◆ hasFSGSBase()

bool llvm::X86Subtarget::hasFSGSBase ( ) const
inline

Definition at line 573 of file X86Subtarget.h.

◆ hasFXSR()

bool llvm::X86Subtarget::hasFXSR ( ) const
inline

Definition at line 554 of file X86Subtarget.h.

◆ hasGFNI()

bool llvm::X86Subtarget::hasGFNI ( ) const
inline

Definition at line 561 of file X86Subtarget.h.

◆ hasIFMA()

bool llvm::X86Subtarget::hasIFMA ( ) const
inline

Definition at line 579 of file X86Subtarget.h.

◆ hasInt256()

bool llvm::X86Subtarget::hasInt256 ( ) const
inline

◆ hasINVPCID()

bool llvm::X86Subtarget::hasINVPCID ( ) const
inline

Definition at line 650 of file X86Subtarget.h.

◆ hasLAHFSAHF()

bool llvm::X86Subtarget::hasLAHFSAHF ( ) const
inline

Definition at line 592 of file X86Subtarget.h.

Referenced by hasNonFlagsUse().

◆ hasLWP()

bool llvm::X86Subtarget::hasLWP ( ) const
inline

Definition at line 569 of file X86Subtarget.h.

◆ hasLZCNT()

bool llvm::X86Subtarget::hasLZCNT ( ) const
inline

◆ hasLZCNTFalseDeps()

bool llvm::X86Subtarget::hasLZCNTFalseDeps ( ) const
inline

Definition at line 609 of file X86Subtarget.h.

Referenced by hasPartialRegUpdate().

◆ hasMacroFusion()

bool llvm::X86Subtarget::hasMacroFusion ( ) const
inline

Definition at line 621 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::canMacroFuseCmp(), and shouldScheduleAdjacent().

◆ hasMFence()

bool llvm::X86Subtarget::hasMFence ( ) const
inline

Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).

There isn't any reason to disable it if the target processor supports it.

Definition at line 695 of file X86Subtarget.h.

References is64Bit().

Referenced by LowerATOMIC_FENCE(), and LowerXALUO().

◆ hasMMX()

bool llvm::X86Subtarget::hasMMX ( ) const
inline

◆ hasMOVBE()

bool llvm::X86Subtarget::hasMOVBE ( ) const
inline

Definition at line 570 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasMOVDIR64B()

bool llvm::X86Subtarget::hasMOVDIR64B ( ) const
inline

Definition at line 597 of file X86Subtarget.h.

◆ hasMOVDIRI()

bool llvm::X86Subtarget::hasMOVDIRI ( ) const
inline

Definition at line 596 of file X86Subtarget.h.

◆ hasMPX()

bool llvm::X86Subtarget::hasMPX ( ) const
inline

Definition at line 641 of file X86Subtarget.h.

◆ hasMWAITX()

bool llvm::X86Subtarget::hasMWAITX ( ) const
inline

Definition at line 593 of file X86Subtarget.h.

◆ hasNOPL()

bool llvm::X86Subtarget::hasNOPL ( ) const
inline

Definition at line 535 of file X86Subtarget.h.

◆ hasPCLMUL()

bool llvm::X86Subtarget::hasPCLMUL ( ) const
inline

Definition at line 559 of file X86Subtarget.h.

◆ hasPCONFIG()

bool llvm::X86Subtarget::hasPCONFIG ( ) const
inline

Definition at line 648 of file X86Subtarget.h.

◆ hasPFI()

bool llvm::X86Subtarget::hasPFI ( ) const
inline

Definition at line 633 of file X86Subtarget.h.

◆ hasPKU()

bool llvm::X86Subtarget::hasPKU ( ) const
inline

Definition at line 638 of file X86Subtarget.h.

◆ hasPOPCNT()

bool llvm::X86Subtarget::hasPOPCNT ( ) const
inline

◆ hasPOPCNTFalseDeps()

bool llvm::X86Subtarget::hasPOPCNTFalseDeps ( ) const
inline

Definition at line 608 of file X86Subtarget.h.

Referenced by hasPartialRegUpdate().

◆ hasPREFETCHWT1()

bool llvm::X86Subtarget::hasPREFETCHWT1 ( ) const
inline

Definition at line 584 of file X86Subtarget.h.

◆ hasPRFCHW()

bool llvm::X86Subtarget::hasPRFCHW ( ) const
inline

Definition at line 583 of file X86Subtarget.h.

◆ hasPTWRITE()

bool llvm::X86Subtarget::hasPTWRITE ( ) const
inline

Definition at line 598 of file X86Subtarget.h.

◆ hasRDPID()

bool llvm::X86Subtarget::hasRDPID ( ) const
inline

Definition at line 646 of file X86Subtarget.h.

◆ hasRDRAND()

bool llvm::X86Subtarget::hasRDRAND ( ) const
inline

Definition at line 571 of file X86Subtarget.h.

◆ hasRDSEED()

bool llvm::X86Subtarget::hasRDSEED ( ) const
inline

Definition at line 591 of file X86Subtarget.h.

◆ hasRTM()

bool llvm::X86Subtarget::hasRTM ( ) const
inline

Definition at line 580 of file X86Subtarget.h.

◆ hasSGX()

bool llvm::X86Subtarget::hasSGX ( ) const
inline

Definition at line 649 of file X86Subtarget.h.

◆ hasSHA()

bool llvm::X86Subtarget::hasSHA ( ) const
inline

Definition at line 582 of file X86Subtarget.h.

◆ hasSHSTK()

bool llvm::X86Subtarget::hasSHSTK ( ) const
inline

Definition at line 642 of file X86Subtarget.h.

◆ hasSlowDivide32()

bool llvm::X86Subtarget::hasSlowDivide32 ( ) const
inline

Definition at line 623 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSlowDivide64()

bool llvm::X86Subtarget::hasSlowDivide64 ( ) const
inline

Definition at line 624 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSE1()

bool llvm::X86Subtarget::hasSSE1 ( ) const
inline

◆ hasSSE2()

bool llvm::X86Subtarget::hasSSE2 ( ) const
inline

Definition at line 538 of file X86Subtarget.h.

Referenced by combineAnd(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineCompareEqual(), combineExtractWithShuffle(), combineFAndFNotToFAndn(), combineFMinNumFMaxNum(), combineHorizontalPredicateResult(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combinePMULH(), combineSelect(), combineSetCC(), combineStore(), combineSubToSubus(), combineToExtendBoolVectorInReg(), combineToExtendVectorInReg(), combineVectorSignBitsTruncation(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), combineX86ShuffleChain(), combineXor(), llvm::X86InstrInfo::commuteInstructionImpl(), convertIntLogicToFPLogic(), detectAVGPattern(), llvm::X86TTIImpl::enableMemCmpExpansion(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getShuffleCost(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), getZeroVector(), llvm::X86TargetLowering::hasAndNot(), hasNonFlagsUse(), InsertBitToMaskVector(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), LowerBITCAST(), LowerBuildVectorAsInsert(), LowerEXTEND_VECTOR_INREG(), LowerLoad(), LowerMUL(), LowerMUL_LOHI(), LowerShift(), lowerV4F32VectorShuffle(), LowerVSETCC(), LowerVSETCCWithSUBUS(), lowerX86FPLogicOp(), llvm::X86TargetLowering::LowerXConstraint(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchPMADDWD(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), materializeVectorConstant(), Passv64i1ArgInRegs(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), SplitOpsAndApply(), SupportedVectorShiftWithImm(), truncateVectorWithPACK(), X86ChooseCmpOpcode(), llvm::X86LegalizerInfo::X86LegalizerInfo(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSE3()

bool llvm::X86Subtarget::hasSSE3 ( ) const
inline

◆ hasSSE41()

bool llvm::X86Subtarget::hasSSE41 ( ) const
inline

◆ hasSSE42()

bool llvm::X86Subtarget::hasSSE42 ( ) const
inline

◆ hasSSE4A()

bool llvm::X86Subtarget::hasSSE4A ( ) const
inline

◆ hasSSEPrefetch()

bool llvm::X86Subtarget::hasSSEPrefetch ( ) const
inline

Definition at line 585 of file X86Subtarget.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

◆ hasSSEUnalignedMem()

bool llvm::X86Subtarget::hasSSEUnalignedMem ( ) const
inline

Definition at line 605 of file X86Subtarget.h.

◆ hasSSSE3()

bool llvm::X86Subtarget::hasSSSE3 ( ) const
inline

◆ hasTBM()

bool llvm::X86Subtarget::hasTBM ( ) const
inline

Definition at line 568 of file X86Subtarget.h.

◆ hasVAES()

bool llvm::X86Subtarget::hasVAES ( ) const
inline

Definition at line 553 of file X86Subtarget.h.

◆ hasVBMI()

bool llvm::X86Subtarget::hasVBMI ( ) const
inline

◆ hasVBMI2()

bool llvm::X86Subtarget::hasVBMI2 ( ) const
inline

Definition at line 578 of file X86Subtarget.h.

◆ hasVLX()

bool llvm::X86Subtarget::hasVLX ( ) const
inline

◆ hasVNNI()

bool llvm::X86Subtarget::hasVNNI ( ) const
inline

Definition at line 639 of file X86Subtarget.h.

◆ hasVPCLMULQDQ()

bool llvm::X86Subtarget::hasVPCLMULQDQ ( ) const
inline

Definition at line 560 of file X86Subtarget.h.

◆ hasVPOPCNTDQ()

bool llvm::X86Subtarget::hasVPOPCNTDQ ( ) const
inline

Definition at line 632 of file X86Subtarget.h.

Referenced by LowerVectorCTPOP(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasWAITPKG()

bool llvm::X86Subtarget::hasWAITPKG ( ) const
inline

Definition at line 647 of file X86Subtarget.h.

◆ hasWBNOINVD()

bool llvm::X86Subtarget::hasWBNOINVD ( ) const
inline

Definition at line 645 of file X86Subtarget.h.

◆ hasX87()

bool llvm::X86Subtarget::hasX87 ( ) const
inline

Definition at line 534 of file X86Subtarget.h.

Referenced by lowerRegToMasks(), and llvm::X86TargetLowering::X86TargetLowering().

◆ hasXOP()

bool llvm::X86Subtarget::hasXOP ( ) const
inline

◆ hasXSAVE()

bool llvm::X86Subtarget::hasXSAVE ( ) const
inline

Definition at line 555 of file X86Subtarget.h.

◆ hasXSAVEC()

bool llvm::X86Subtarget::hasXSAVEC ( ) const
inline

Definition at line 557 of file X86Subtarget.h.

◆ hasXSAVEOPT()

bool llvm::X86Subtarget::hasXSAVEOPT ( ) const
inline

Definition at line 556 of file X86Subtarget.h.

◆ hasXSAVES()

bool llvm::X86Subtarget::hasXSAVES ( ) const
inline

Definition at line 558 of file X86Subtarget.h.

◆ is16Bit()

bool llvm::X86Subtarget::is16Bit ( ) const
inline

◆ is32Bit()

bool llvm::X86Subtarget::is32Bit ( ) const
inline

◆ is64Bit()

bool llvm::X86Subtarget::is64Bit ( ) const
inline

Is this x86_64? (disregarding specific ABI / programming model)

Definition at line 507 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::X86TargetLowering::canMergeStoresTo(), classifyGlobalFunctionReference(), classifyGlobalReference(), llvm::X86InstrInfo::classifyLEAReg(), classifyLocalReference(), combineAnd(), combineCompareEqual(), combineSIntToFP(), combineStore(), computeBytesPoppedByCalleeForSRet(), llvm::X86InstrInfo::convertToThreeAddress(), createPHIsForCMOVsInSinkBB(), llvm::createX86GlobalBaseRegPass(), llvm::createX86IndirectBranchTrackingPass(), emitClzero(), emitMonitor(), EmitNops(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::X86TTIImpl::enableMemCmpExpansion(), ExpandMOVImmSExti8(), llvm::X86TargetLowering::findRepresentativeClass(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), getExtendedControlRegister(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getIRStackGuard(), getLoadStoreRegOpcode(), getMOVL(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), getRetOpcode(), getRetpolineSymbol(), llvm::X86TargetLowering::getSafeStackPointerLocation(), llvm::X86InstrInfo::getSerializableDirectMachineOperandTargetFlags(), llvm::X86TargetLowering::getStackProbeSymbolName(), hasBZHI(), llvm::X86FrameLowering::inlineStackProbe(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::X86TargetLowering::isIntDivCheap(), llvm::X86TargetLowering::isLegalAddressingMode(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), isXor1OfSetCC(), llvm::X86TargetLowering::isZExtFree(), LowerADJUST_TRAMPOLINE(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerBITCAST(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), llvm::X86CallLowering::lowerCall(), LowerCMP_SWAP(), LowerEXTRACT_SUBVECTOR(), LowerFSINCOS(), LowerI64IntToFP_AVX512DQ(), lowerRegToMasks(), LowerToTLSExecModel(), lowerUINT_TO_FP_vec(), LowerVACOPY(), LowerXALUO(), llvm::X86TargetLowering::markLibCallAttributes(), MatchingStackOffset(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), printAsmMRegister(), llvm::X86FrameLowering::processFunctionBeforeFrameFinalized(), recoverFramePointer(), removeRedundantBlockingStores(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), shouldGuaranteeTCO(), SimplifyShortMoveForm(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::X86TargetLowering::supportSwiftError(), llvm::X86TargetLowering::useLoadStackGuardNode(), llvm::X86FrameLowering::X86FrameLowering(), llvm::X86LegalizerInfo::X86LegalizerInfo(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isAtom()

bool llvm::X86Subtarget::isAtom ( ) const
inline

TODO: to be removed later and replaced with suitable properties.

Definition at line 683 of file X86Subtarget.h.

Referenced by llvm::X86TTIImpl::enableInterleavedAccessVectorization(), llvm::X86TTIImpl::getMaxInterleaveFactor(), hasNonFlagsUse(), and llvm::X86TargetLowering::X86TargetLowering().

◆ isCallingConvWin64()

bool llvm::X86Subtarget::isCallingConvWin64 ( CallingConv::ID  CC) const
inline

◆ isGLM()

bool llvm::X86Subtarget::isGLM ( ) const
inline

◆ isLegalToCallImmediateAddr()

bool X86Subtarget::isLegalToCallImmediateAddr ( ) const

Return true if the subtarget allows calls to immediate address.

Definition at line 181 of file X86Subtarget.cpp.

References assert(), llvm::dbgs(), llvm::TargetMachine::getRelocationModel(), HasADX, HasAES, hasAVX2(), hasAVX512(), HasBITALG, HasBMI, HasBMI2, HasBWI, HasCDI, HasCLDEMOTE, HasCLFLUSHOPT, HasCLWB, HasCLZERO, HasCMov, HasCmpxchg16b, HasDQI, HasERI, HasERMSB, HasF16C, HasFast11ByteNOP, HasFast15ByteNOP, HasFastGather, hasFastGather(), HasFastLZCNT, HasFastPartialYMMorZMMWrite, HasFastScalarFSQRT, HasFastSHLDRotate, HasFastVariableShuffle, HasFastVectorFSQRT, HasFMA, HasFMA4, HasFSGSBase, HasFXSR, HasGFNI, HasIFMA, HasINVPCID, HasLAHFSAHF, HasLWP, HasLZCNT, HasLZCNTFalseDeps, HasMacroFusion, HasMOVBE, HasMOVDIR64B, HasMOVDIRI, HasMPX, HasMWAITX, HasNOPL, HasPCLMUL, HasPCONFIG, HasPFI, HasPKU, HasPOPCNT, HasPOPCNTFalseDeps, HasPREFETCHWT1, HasPRFCHW, HasPTWRITE, HasRDPID, HasRDRAND, HasRDSEED, HasRTM, HasSGX, HasSHA, HasSHSTK, HasSlowDivide32, HasSlowDivide64, hasSSE42(), HasSSE4A, hasSSE4A(), HasSSEUnalignedMem, HasTBM, HasVAES, HasVBMI, HasVBMI2, HasVLX, HasVNNI, HasVPCLMULQDQ, HasVPOPCNTDQ, HasWAITPKG, HasWBNOINVD, HasX86_64, HasX87, HasXOP, HasXSAVE, HasXSAVEC, HasXSAVEOPT, HasXSAVES, IsPMULLDSlow, IsSHLDSlow, isTargetDarwin(), isTargetELF(), isTargetKFreeBSD(), isTargetLinux(), isTargetSolaris(), isTargetWin32(), IsUAMem16Slow, IsUAMem32Slow, LEAUsesAG, LLVM_DEBUG, llvm_unreachable, MaxInlineSizeThreshold, NoSSE, NoThreeDNow, Others, PadShortFunctions, ParseSubtargetFeatures(), Prefer256Bit, Slow3OpsLEA, SlowIncDec, SlowLEA, SlowTwoMemOps, stackAlignment, llvm::Reloc::Static, TM, UseLeaForSP, UseRetpoline, UseRetpolineExternalThunk, UseSoftFloat, X863DNowLevel, X86ProcFamily, and X86SSELevel.

◆ isOSWindows()

bool llvm::X86Subtarget::isOSWindows ( ) const
inline

◆ isPICStyleGOT()

bool llvm::X86Subtarget::isPICStyleGOT ( ) const
inline

◆ isPICStyleRIPRel()

bool llvm::X86Subtarget::isPICStyleRIPRel ( ) const
inline

◆ isPICStyleStubPIC()

bool llvm::X86Subtarget::isPICStyleStubPIC ( ) const
inline

◆ isPMULLDSlow()

bool llvm::X86Subtarget::isPMULLDSlow ( ) const
inline

Definition at line 600 of file X86Subtarget.h.

Referenced by reduceVMULWidth().

◆ isPositionIndependent()

bool llvm::X86Subtarget::isPositionIndependent ( ) const
inline

◆ isSHLDSlow()

bool llvm::X86Subtarget::isSHLDSlow ( ) const
inline

Definition at line 599 of file X86Subtarget.h.

Referenced by combineOr().

◆ isSLM()

bool llvm::X86Subtarget::isSLM ( ) const
inline

◆ isTarget64BitILP32()

bool llvm::X86Subtarget::isTarget64BitILP32 ( ) const
inline

◆ isTarget64BitLP64()

bool llvm::X86Subtarget::isTarget64BitLP64 ( ) const
inline

◆ isTargetAndroid()

bool llvm::X86Subtarget::isTargetAndroid ( ) const
inline

◆ isTargetCOFF()

bool llvm::X86Subtarget::isTargetCOFF ( ) const
inline

◆ isTargetCygMing()

bool llvm::X86Subtarget::isTargetCygMing ( ) const
inline

◆ isTargetDarwin()

bool llvm::X86Subtarget::isTargetDarwin ( ) const
inline

◆ isTargetDragonFly()

bool llvm::X86Subtarget::isTargetDragonFly ( ) const
inline

◆ isTargetELF()

bool llvm::X86Subtarget::isTargetELF ( ) const
inline

◆ isTargetFreeBSD()

bool llvm::X86Subtarget::isTargetFreeBSD ( ) const
inline

◆ isTargetFuchsia()

bool llvm::X86Subtarget::isTargetFuchsia ( ) const
inline

◆ isTargetGlibc()

bool llvm::X86Subtarget::isTargetGlibc ( ) const
inline

Definition at line 711 of file X86Subtarget.h.

References llvm::Triple::isOSGlibc().

◆ isTargetKFreeBSD()

bool llvm::X86Subtarget::isTargetKFreeBSD ( ) const
inline

Definition at line 710 of file X86Subtarget.h.

References llvm::Triple::isOSKFreeBSD().

Referenced by isLegalToCallImmediateAddr().

◆ isTargetKnownWindowsMSVC()

bool llvm::X86Subtarget::isTargetKnownWindowsMSVC ( ) const
inline

◆ isTargetLinux()

bool llvm::X86Subtarget::isTargetLinux ( ) const
inline

◆ isTargetMachO()

bool llvm::X86Subtarget::isTargetMachO ( ) const
inline

◆ isTargetMCU()

bool llvm::X86Subtarget::isTargetMCU ( ) const
inline

◆ isTargetNaCl()

bool llvm::X86Subtarget::isTargetNaCl ( ) const
inline

Definition at line 713 of file X86Subtarget.h.

References llvm::Triple::isOSNaCl().

◆ isTargetNaCl32()

bool llvm::X86Subtarget::isTargetNaCl32 ( ) const
inline

Definition at line 714 of file X86Subtarget.h.

References is64Bit().

◆ isTargetNaCl64()

bool llvm::X86Subtarget::isTargetNaCl64 ( ) const
inline

◆ isTargetPS4()

bool llvm::X86Subtarget::isTargetPS4 ( ) const
inline

Definition at line 703 of file X86Subtarget.h.

References llvm::Triple::isPS4CPU().

◆ isTargetSolaris()

bool llvm::X86Subtarget::isTargetSolaris ( ) const
inline

Definition at line 702 of file X86Subtarget.h.

References llvm::Triple::isOSSolaris().

Referenced by isLegalToCallImmediateAddr().

◆ isTargetWin32()

bool llvm::X86Subtarget::isTargetWin32 ( ) const
inline

◆ isTargetWin64()

bool llvm::X86Subtarget::isTargetWin64 ( ) const
inline

◆ isTargetWindowsCoreCLR()

bool llvm::X86Subtarget::isTargetWindowsCoreCLR ( ) const
inline

◆ isTargetWindowsCygwin()

bool llvm::X86Subtarget::isTargetWindowsCygwin ( ) const
inline

Definition at line 731 of file X86Subtarget.h.

References llvm::Triple::isWindowsCygwinEnvironment().

◆ isTargetWindowsGNU()

bool llvm::X86Subtarget::isTargetWindowsGNU ( ) const
inline

◆ isTargetWindowsItanium()

bool llvm::X86Subtarget::isTargetWindowsItanium ( ) const
inline

◆ isTargetWindowsMSVC()

bool llvm::X86Subtarget::isTargetWindowsMSVC ( ) const
inline

◆ isUnalignedMem16Slow()

bool llvm::X86Subtarget::isUnalignedMem16Slow ( ) const
inline

◆ isUnalignedMem32Slow()

bool llvm::X86Subtarget::isUnalignedMem32Slow ( ) const
inline

◆ isXRaySupported()

bool llvm::X86Subtarget::isXRaySupported ( ) const
inlineoverride

Definition at line 678 of file X86Subtarget.h.

References is64Bit().

◆ LEAusesAG()

bool llvm::X86Subtarget::LEAusesAG ( ) const
inline

Definition at line 627 of file X86Subtarget.h.

Referenced by llvm::createX86FixupLEAs().

◆ padShortFunctions()

bool llvm::X86Subtarget::padShortFunctions ( ) const
inline

Definition at line 625 of file X86Subtarget.h.

Referenced by llvm::createX86PadShortFunctions().

◆ ParseSubtargetFeatures()

void llvm::X86Subtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  FS 
)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

Referenced by isLegalToCallImmediateAddr().

◆ setPICStyle()

void llvm::X86Subtarget::setPICStyle ( PICStyles::Style  Style)
inline

Definition at line 532 of file X86Subtarget.h.

Referenced by X86Subtarget().

◆ slow3OpsLEA()

bool llvm::X86Subtarget::slow3OpsLEA ( ) const
inline

Definition at line 629 of file X86Subtarget.h.

Referenced by llvm::createX86FixupLEAs(), and isLEASimpleIncOrDec().

◆ slowIncDec()

bool llvm::X86Subtarget::slowIncDec ( ) const
inline

◆ slowLEA()

bool llvm::X86Subtarget::slowLEA ( ) const
inline

Definition at line 628 of file X86Subtarget.h.

Referenced by combineMul(), and llvm::createX86FixupLEAs().

◆ slowTwoMemOps()

bool llvm::X86Subtarget::slowTwoMemOps ( ) const
inline

Definition at line 626 of file X86Subtarget.h.

◆ supportPrintSchedInfo()

bool llvm::X86Subtarget::supportPrintSchedInfo ( ) const
inlineoverride

Definition at line 812 of file X86Subtarget.h.

◆ useAVX512Regs()

bool llvm::X86Subtarget::useAVX512Regs ( ) const
inline

◆ useBWIRegs()

bool llvm::X86Subtarget::useBWIRegs ( ) const
inline

◆ useLeaForSP()

bool llvm::X86Subtarget::useLeaForSP ( ) const
inline

Definition at line 607 of file X86Subtarget.h.

Referenced by llvm::X86FrameLowering::emitSPUpdate().

◆ useRetpoline()

bool llvm::X86Subtarget::useRetpoline ( ) const
inline

◆ useRetpolineExternalThunk()

bool llvm::X86Subtarget::useRetpolineExternalThunk ( ) const
inline

Definition at line 652 of file X86Subtarget.h.

Referenced by getRetpolineSymbol().

◆ useSoftFloat()

bool llvm::X86Subtarget::useSoftFloat ( ) const
inline

Member Data Documentation

◆ CallLoweringInfo

std::unique_ptr<CallLowering> llvm::X86Subtarget::CallLoweringInfo
protected

GlobalISel related APIs.

Definition at line 413 of file X86Subtarget.h.

Referenced by getCallLowering(), and X86Subtarget().

◆ HasADX

bool llvm::X86Subtarget::HasADX
protected

Processor has ADX instructions.

Definition at line 189 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasAES

bool llvm::X86Subtarget::HasAES
protected

Target has AES instructions.

Definition at line 115 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasBITALG

bool llvm::X86Subtarget::HasBITALG
protected

Processor has AVX-512 Bit Algorithms instructions.

Definition at line 354 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasBMI

bool llvm::X86Subtarget::HasBMI
protected

Processor has BMI1 instructions.

Definition at line 171 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasBMI2

bool llvm::X86Subtarget::HasBMI2
protected

Processor has BMI2 instructions.

Definition at line 174 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasBWI

bool llvm::X86Subtarget::HasBWI
protected

Processor has AVX-512 Byte and Word instructions.

Definition at line 342 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCDI

bool llvm::X86Subtarget::HasCDI
protected

Processor has AVX-512 Conflict Detection Instructions.

Definition at line 333 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCLDEMOTE

bool llvm::X86Subtarget::HasCLDEMOTE
protected

Processor has Cache Line Demote instruction.

Definition at line 210 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCLFLUSHOPT

bool llvm::X86Subtarget::HasCLFLUSHOPT
protected

Processor supports Flush Cache Line instruction.

Definition at line 370 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCLWB

bool llvm::X86Subtarget::HasCLWB
protected

Processor supports Cache Line Write Back instruction.

Definition at line 373 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCLZERO

bool llvm::X86Subtarget::HasCLZERO
protected

Processor has Cache Line Zero instruction.

Definition at line 207 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCMov

bool llvm::X86Subtarget::HasCMov
protected

True if this processor has conditional move instructions (generally pentium pro+).

Definition at line 103 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasCmpxchg16b

bool llvm::X86Subtarget::HasCmpxchg16b
protected

True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips.

Definition at line 243 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasDQI

bool llvm::X86Subtarget::HasDQI
protected

Processor has AVX-512 Doubleword and Quadword instructions.

Definition at line 339 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasERI

bool llvm::X86Subtarget::HasERI
protected

Processor has AVX-512 Exponential and Reciprocal Instructions.

Definition at line 330 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasERMSB

bool llvm::X86Subtarget::HasERMSB
protected

True if the processor has enhanced REP MOVSB/STOSB.

Definition at line 301 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasF16C

bool llvm::X86Subtarget::HasF16C
protected

Processor has 16-bit floating point conversion instructions.

Definition at line 162 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFast11ByteNOP

bool llvm::X86Subtarget::HasFast11ByteNOP
protected

True if there is no performance penalty for writing NOPs with up to 11 bytes.

Definition at line 265 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFast15ByteNOP

bool llvm::X86Subtarget::HasFast15ByteNOP
protected

True if there is no performance penalty for writing NOPs with up to 15 bytes.

Definition at line 269 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastGather

bool llvm::X86Subtarget::HasFastGather
protected

True if gather is reasonably fast.

This is true for Skylake client and all AVX-512 CPUs.

Definition at line 273 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastLZCNT

bool llvm::X86Subtarget::HasFastLZCNT
protected

True if LZCNT instruction is fast.

Definition at line 292 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastPartialYMMorZMMWrite

bool llvm::X86Subtarget::HasFastPartialYMMorZMMWrite
protected

True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register without clearing the upper part.

Definition at line 261 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastScalarFSQRT

bool llvm::X86Subtarget::HasFastScalarFSQRT
protected

True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration.

Definition at line 277 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastSHLDRotate

bool llvm::X86Subtarget::HasFastSHLDRotate
protected

True if SHLD based rotate is fast.

Definition at line 295 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastVariableShuffle

bool llvm::X86Subtarget::HasFastVariableShuffle
protected

True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuffles.

Definition at line 257 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFastVectorFSQRT

bool llvm::X86Subtarget::HasFastVectorFSQRT
protected

True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.

Definition at line 281 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFMA

bool llvm::X86Subtarget::HasFMA
protected

Target has 3-operand fused multiply-add.

Definition at line 141 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFMA4

bool llvm::X86Subtarget::HasFMA4
protected

Target has 4-operand fused multiply-add.

Definition at line 144 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFSGSBase

bool llvm::X86Subtarget::HasFSGSBase
protected

Processor has FS/GS base insturctions.

Definition at line 165 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasFXSR

bool llvm::X86Subtarget::HasFXSR
protected

Target has FXSAVE/FXRESTOR instructions.

Definition at line 119 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasGFNI

bool llvm::X86Subtarget::HasGFNI
protected

Target has Galois Field Arithmetic instructions.

Definition at line 138 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasIFMA

bool llvm::X86Subtarget::HasIFMA
protected

Processor has Integer Fused Multiply Add.

Definition at line 183 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasINVPCID

bool llvm::X86Subtarget::HasINVPCID
protected

Processor supports Invalidate Process-Context Identifier.

Definition at line 364 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasLAHFSAHF

bool llvm::X86Subtarget::HasLAHFSAHF
protected

Processor has LAHF/SAHF instructions.

Definition at line 201 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasLWP

bool llvm::X86Subtarget::HasLWP
protected

Target has LWP instructions.

Definition at line 153 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasLZCNT

bool llvm::X86Subtarget::HasLZCNT
protected

Processor has LZCNT instruction.

Definition at line 168 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasLZCNTFalseDeps

bool llvm::X86Subtarget::HasLZCNTFalseDeps
protected

True if LZCNT/TZCNT instructions have a false dependency on the destination register.

Definition at line 253 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMacroFusion

bool llvm::X86Subtarget::HasMacroFusion
protected

True if the processor supports macrofusion.

Definition at line 298 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMOVBE

bool llvm::X86Subtarget::HasMOVBE
protected

True if the processor has the MOVBE instruction.

Definition at line 156 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMOVDIR64B

bool llvm::X86Subtarget::HasMOVDIR64B
protected

Processor has MOVDIR64B instruction (direct store 64 bytes).

Definition at line 216 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMOVDIRI

bool llvm::X86Subtarget::HasMOVDIRI
protected

Processor has MOVDIRI instruction (direct store integer).

Definition at line 213 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMPX

bool llvm::X86Subtarget::HasMPX
protected

Processor supports MPX - Memory Protection Extensions.

Definition at line 357 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasMWAITX

bool llvm::X86Subtarget::HasMWAITX
protected

Processor has MONITORX/MWAITX instructions.

Definition at line 204 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasNOPL

bool llvm::X86Subtarget::HasNOPL
protected

True if this processor has NOPL instruction (generally pentium pro+).

Definition at line 99 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPCLMUL

bool llvm::X86Subtarget::HasPCLMUL
protected

Target has carry-less multiplication.

Definition at line 134 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPCONFIG

bool llvm::X86Subtarget::HasPCONFIG
protected

Processor supports PCONFIG instruction.

Definition at line 385 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPFI

bool llvm::X86Subtarget::HasPFI
protected

Processor has AVX-512 PreFetch Instructions.

Definition at line 327 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPKU

bool llvm::X86Subtarget::HasPKU
protected

Processor has PKU extenstions.

Definition at line 348 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPOPCNT

bool llvm::X86Subtarget::HasPOPCNT
protected

True if the processor supports POPCNT.

Definition at line 109 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPOPCNTFalseDeps

bool llvm::X86Subtarget::HasPOPCNTFalseDeps
protected

True if POPCNT instruction has a false dependency on the destination register.

Definition at line 250 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPREFETCHWT1

bool llvm::X86Subtarget::HasPREFETCHWT1
protected

Processor has Prefetch with intent to Write instruction.

Definition at line 222 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPRFCHW

bool llvm::X86Subtarget::HasPRFCHW
protected

Processor has PRFCHW instructions.

Definition at line 195 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasPTWRITE

bool llvm::X86Subtarget::HasPTWRITE
protected

Processor has ptwrite instruction.

Definition at line 219 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasRDPID

bool llvm::X86Subtarget::HasRDPID
protected

Processor support RDPID instruction.

Definition at line 379 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasRDRAND

bool llvm::X86Subtarget::HasRDRAND
protected

True if the processor has the RDRAND instruction.

Definition at line 159 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasRDSEED

bool llvm::X86Subtarget::HasRDSEED
protected

Processor has RDSEED instructions.

Definition at line 198 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasRTM

bool llvm::X86Subtarget::HasRTM
protected

Processor has RTM instructions.

Definition at line 186 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSGX

bool llvm::X86Subtarget::HasSGX
protected

Processor has Software Guard Extensions.

Definition at line 367 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSHA

bool llvm::X86Subtarget::HasSHA
protected

Processor has SHA instructions.

Definition at line 192 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSHSTK

bool llvm::X86Subtarget::HasSHSTK
protected

Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack.

Definition at line 361 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSlowDivide32

bool llvm::X86Subtarget::HasSlowDivide32
protected

True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible.

Definition at line 285 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSlowDivide64

bool llvm::X86Subtarget::HasSlowDivide64
protected

True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible.

Definition at line 289 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSSE4A

bool llvm::X86Subtarget::HasSSE4A
protected

True if the processor supports SSE4A instructions.

Definition at line 112 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasSSEUnalignedMem

bool llvm::X86Subtarget::HasSSEUnalignedMem
protected

True if SSE operations can have unaligned memory operands.

This may require setting a configuration bit in the processor.

Definition at line 239 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasTBM

bool llvm::X86Subtarget::HasTBM
protected

Target has TBM instructions.

Definition at line 150 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVAES

bool llvm::X86Subtarget::HasVAES
protected

Definition at line 116 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVBMI

bool llvm::X86Subtarget::HasVBMI
protected

Processor has VBMI instructions.

Definition at line 177 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVBMI2

bool llvm::X86Subtarget::HasVBMI2
protected

Processor has VBMI2 instructions.

Definition at line 180 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVLX

bool llvm::X86Subtarget::HasVLX
protected

Processor has AVX-512 Vector Length eXtenstions.

Definition at line 345 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVNNI

bool llvm::X86Subtarget::HasVNNI
protected

Processor has AVX-512 Vector Neural Network Instructions.

Definition at line 351 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVPCLMULQDQ

bool llvm::X86Subtarget::HasVPCLMULQDQ
protected

Definition at line 135 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasVPOPCNTDQ

bool llvm::X86Subtarget::HasVPOPCNTDQ
protected

Processor has AVX-512 population count Instructions.

Definition at line 336 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasWAITPKG

bool llvm::X86Subtarget::HasWAITPKG
protected

Processor supports WaitPKG instructions.

Definition at line 382 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasWBNOINVD

bool llvm::X86Subtarget::HasWBNOINVD
protected

Processor supports Write Back No Invalidate instruction.

Definition at line 376 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasX86_64

bool llvm::X86Subtarget::HasX86_64
protected

True if the processor supports X86-64 instructions.

Definition at line 106 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasX87

bool llvm::X86Subtarget::HasX87
protected

True if the processor supports X87 instructions.

Definition at line 95 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasXOP

bool llvm::X86Subtarget::HasXOP
protected

Target has XOP instructions.

Definition at line 147 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasXSAVE

bool llvm::X86Subtarget::HasXSAVE
protected

Target has XSAVE instructions.

Definition at line 122 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasXSAVEC

bool llvm::X86Subtarget::HasXSAVEC
protected

Target has XSAVEC instructions.

Definition at line 128 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasXSAVEOPT

bool llvm::X86Subtarget::HasXSAVEOPT
protected

Target has XSAVEOPT instructions.

Definition at line 125 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ HasXSAVES

bool llvm::X86Subtarget::HasXSAVES
protected

Target has XSAVES instructions.

Definition at line 131 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ InstSelector

std::unique_ptr<InstructionSelector> llvm::X86Subtarget::InstSelector
protected

Definition at line 416 of file X86Subtarget.h.

Referenced by getInstructionSelector(), and X86Subtarget().

◆ IsPMULLDSlow

bool llvm::X86Subtarget::IsPMULLDSlow
protected

True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.

Definition at line 229 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ IsSHLDSlow

bool llvm::X86Subtarget::IsSHLDSlow
protected

True if SHLD instructions are slow.

Definition at line 225 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ IsUAMem16Slow

bool llvm::X86Subtarget::IsUAMem16Slow
protected

True if unaligned memory accesses of 16-bytes are slow.

Definition at line 232 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ IsUAMem32Slow

bool llvm::X86Subtarget::IsUAMem32Slow
protected

True if unaligned memory accesses of 32-bytes are slow.

Definition at line 235 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ LEAUsesAG

bool llvm::X86Subtarget::LEAUsesAG
protected

True if the LEA instruction inputs have to be ready at address generation (AG) time.

Definition at line 313 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ Legalizer

std::unique_ptr<LegalizerInfo> llvm::X86Subtarget::Legalizer
protected

Definition at line 414 of file X86Subtarget.h.

◆ MaxInlineSizeThreshold

unsigned llvm::X86Subtarget::MaxInlineSizeThreshold
protected

Max.

memset / memcpy size that is turned into rep/movs, rep/stos ops.

Definition at line 404 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ PadShortFunctions

bool llvm::X86Subtarget::PadShortFunctions
protected

True if the short functions should be padded to prevent a stall when returning too early.

Definition at line 305 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ PICStyle

PICStyles::Style llvm::X86Subtarget::PICStyle
protected

Which PIC style to use.

Definition at line 84 of file X86Subtarget.h.

◆ Prefer256Bit

bool llvm::X86Subtarget::Prefer256Bit
protected

Indicates target prefers 256 bit instructions.

Definition at line 407 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ RegBankInfo

std::unique_ptr<RegisterBankInfo> llvm::X86Subtarget::RegBankInfo
protected

Definition at line 415 of file X86Subtarget.h.

Referenced by getRegBankInfo(), and X86Subtarget().

◆ Slow3OpsLEA

bool llvm::X86Subtarget::Slow3OpsLEA
protected

True if the LEA instruction has all three source operands: base, index, and offset or if the LEA instruction uses base and index registers where the base is EBP, RBP,or R13.

Definition at line 321 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ SlowIncDec

bool llvm::X86Subtarget::SlowIncDec
protected

True if INC and DEC instructions are slow when writing to flags.

Definition at line 324 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ SlowLEA

bool llvm::X86Subtarget::SlowLEA
protected

True if the LEA instruction with certain arguments is slow.

Definition at line 316 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ SlowTwoMemOps

bool llvm::X86Subtarget::SlowTwoMemOps
protected

True if two memory operand instructions should use a temporary register instead.

Definition at line 309 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ stackAlignment

unsigned llvm::X86Subtarget::stackAlignment
protected

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 400 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ TargetTriple

Triple llvm::X86Subtarget::TargetTriple
protected

What processor and OS we're targeting.

Definition at line 410 of file X86Subtarget.h.

◆ TM

const TargetMachine& llvm::X86Subtarget::TM
protected

◆ UseLeaForSP

bool llvm::X86Subtarget::UseLeaForSP
protected

True if the LEA instruction should be used for adjusting the stack pointer.

This is an optimization for Intel Atom processors.

Definition at line 247 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ UseRetpoline

bool llvm::X86Subtarget::UseRetpoline
protected

Use a retpoline thunk rather than indirect calls to block speculative execution.

Definition at line 389 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ UseRetpolineExternalThunk

bool llvm::X86Subtarget::UseRetpolineExternalThunk
protected

When using a retpoline thunk, call an externally provided thunk rather than emitting one inside the compiler.

Definition at line 393 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ UseSoftFloat

bool llvm::X86Subtarget::UseSoftFloat
protected

Use software floating point for code generation.

Definition at line 396 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ X863DNowLevel

X863DNowEnum llvm::X86Subtarget::X863DNowLevel
protected

MMX, 3DNow, 3DNow Athlon, or none supported.

Definition at line 92 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ X86ProcFamily

X86ProcFamilyEnum llvm::X86Subtarget::X86ProcFamily
protected

X86 processor family: Intel Atom, and others.

Definition at line 81 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().

◆ X86SSELevel

X86SSEEnum llvm::X86Subtarget::X86SSELevel
protected

SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.

Definition at line 89 of file X86Subtarget.h.

Referenced by isLegalToCallImmediateAddr().


The documentation for this class was generated from the following files: