LLVM 19.0.0git
X86BaseInfo.h
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1//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the X86 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18
19#include "X86MCTargetDesc.h"
20#include "llvm/MC/MCInstrDesc.h"
23
24namespace llvm {
25namespace X86 {
26// Enums for memory operand decoding. Each memory operand is represented with
27// a 5 operand sequence in the form: [Base, Scale, Index, Disp, Segment]
28enum {
33 // The operand # of the segment in the memory operand.
35 // Total number of operands in a memory reference.
37};
38
39/// AVX512 static rounding constants. These need to match the values in
40/// avx512fintrin.h.
47 NO_EXC = 8
48};
49
50/// The constants to describe instr prefixes if there are
53 IP_HAS_OP_SIZE = 1U << 0,
54 IP_HAS_AD_SIZE = 1U << 1,
56 IP_HAS_REPEAT = 1U << 3,
57 IP_HAS_LOCK = 1U << 4,
58 IP_HAS_NOTRACK = 1U << 5,
59 IP_USE_VEX = 1U << 6,
60 IP_USE_VEX2 = 1U << 7,
61 IP_USE_VEX3 = 1U << 8,
62 IP_USE_EVEX = 1U << 9,
63 IP_USE_DISP8 = 1U << 10,
64 IP_USE_DISP32 = 1U << 11,
65};
66
67enum OperandType : unsigned {
68 // AVX512 embedded rounding control. This should only have values 0-3.
71};
72
73// X86 specific condition code. These correspond to X86_*_COND in
74// X86InstrInfo.td. They must be kept in synch.
76 COND_O = 0,
78 COND_B = 2,
80 COND_E = 4,
83 COND_A = 7,
84 COND_S = 8,
86 COND_P = 10,
87 COND_NP = 11,
88 COND_L = 12,
89 COND_GE = 13,
90 COND_LE = 14,
91 COND_G = 15,
93 // Artificial condition codes. These are used by analyzeBranch
94 // to indicate a block terminated with two conditional branches that together
95 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
96 // which can't be represented on x86 with a single condition. These
97 // are never used in MachineInstrs and are inverses of one another.
102
103// The classification for the first instruction in macro fusion.
104// FIXME: Zen 3 support branch fusion for OR/XOR.
106 Test, // TEST
107 Cmp, // CMP
108 And, // AND
109 AddSub, // ADD, SUB
110 IncDec, // INC, DEC
111 Invalid // Not valid as a first macro fusion instruction
112};
113
115 AB, // JA, JB and variants
116 ELG, // JE, JL, JG and variants
117 SPO, // JS, JP, JO and variants
118 Invalid, // Not a fusible jump.
119};
120
121/// \returns the type of the first instruction in macro-fusion.
122// FIXME: Zen 3 support branch fusion for OR/XOR.
125 switch (Opcode) {
126 default:
128 // TEST
129 case X86::TEST16i16:
130 case X86::TEST16mr:
131 case X86::TEST16ri:
132 case X86::TEST16rr:
133 case X86::TEST32i32:
134 case X86::TEST32mr:
135 case X86::TEST32ri:
136 case X86::TEST32rr:
137 case X86::TEST64i32:
138 case X86::TEST64mr:
139 case X86::TEST64ri32:
140 case X86::TEST64rr:
141 case X86::TEST8i8:
142 case X86::TEST8mr:
143 case X86::TEST8ri:
144 case X86::TEST8rr:
146 case X86::AND16i16:
147 case X86::AND16ri:
148 case X86::AND16ri8:
149 case X86::AND16rm:
150 case X86::AND16rr:
151 case X86::AND16rr_REV:
152 case X86::AND32i32:
153 case X86::AND32ri:
154 case X86::AND32ri8:
155 case X86::AND32rm:
156 case X86::AND32rr:
157 case X86::AND32rr_REV:
158 case X86::AND64i32:
159 case X86::AND64ri32:
160 case X86::AND64ri8:
161 case X86::AND64rm:
162 case X86::AND64rr:
163 case X86::AND64rr_REV:
164 case X86::AND8i8:
165 case X86::AND8ri:
166 case X86::AND8ri8:
167 case X86::AND8rm:
168 case X86::AND8rr:
169 case X86::AND8rr_REV:
171 // CMP
172 case X86::CMP16i16:
173 case X86::CMP16mr:
174 case X86::CMP16ri:
175 case X86::CMP16ri8:
176 case X86::CMP16rm:
177 case X86::CMP16rr:
178 case X86::CMP16rr_REV:
179 case X86::CMP32i32:
180 case X86::CMP32mr:
181 case X86::CMP32ri:
182 case X86::CMP32ri8:
183 case X86::CMP32rm:
184 case X86::CMP32rr:
185 case X86::CMP32rr_REV:
186 case X86::CMP64i32:
187 case X86::CMP64mr:
188 case X86::CMP64ri32:
189 case X86::CMP64ri8:
190 case X86::CMP64rm:
191 case X86::CMP64rr:
192 case X86::CMP64rr_REV:
193 case X86::CMP8i8:
194 case X86::CMP8mr:
195 case X86::CMP8ri:
196 case X86::CMP8ri8:
197 case X86::CMP8rm:
198 case X86::CMP8rr:
199 case X86::CMP8rr_REV:
201 // ADD
202 case X86::ADD16i16:
203 case X86::ADD16ri:
204 case X86::ADD16ri8:
205 case X86::ADD16rm:
206 case X86::ADD16rr:
207 case X86::ADD16rr_REV:
208 case X86::ADD32i32:
209 case X86::ADD32ri:
210 case X86::ADD32ri8:
211 case X86::ADD32rm:
212 case X86::ADD32rr:
213 case X86::ADD32rr_REV:
214 case X86::ADD64i32:
215 case X86::ADD64ri32:
216 case X86::ADD64ri8:
217 case X86::ADD64rm:
218 case X86::ADD64rr:
219 case X86::ADD64rr_REV:
220 case X86::ADD8i8:
221 case X86::ADD8ri:
222 case X86::ADD8ri8:
223 case X86::ADD8rm:
224 case X86::ADD8rr:
225 case X86::ADD8rr_REV:
226 // SUB
227 case X86::SUB16i16:
228 case X86::SUB16ri:
229 case X86::SUB16ri8:
230 case X86::SUB16rm:
231 case X86::SUB16rr:
232 case X86::SUB16rr_REV:
233 case X86::SUB32i32:
234 case X86::SUB32ri:
235 case X86::SUB32ri8:
236 case X86::SUB32rm:
237 case X86::SUB32rr:
238 case X86::SUB32rr_REV:
239 case X86::SUB64i32:
240 case X86::SUB64ri32:
241 case X86::SUB64ri8:
242 case X86::SUB64rm:
243 case X86::SUB64rr:
244 case X86::SUB64rr_REV:
245 case X86::SUB8i8:
246 case X86::SUB8ri:
247 case X86::SUB8ri8:
248 case X86::SUB8rm:
249 case X86::SUB8rr:
250 case X86::SUB8rr_REV:
252 // INC
253 case X86::INC16r:
254 case X86::INC16r_alt:
255 case X86::INC32r:
256 case X86::INC32r_alt:
257 case X86::INC64r:
258 case X86::INC8r:
259 // DEC
260 case X86::DEC16r:
261 case X86::DEC16r_alt:
262 case X86::DEC32r:
263 case X86::DEC32r_alt:
264 case X86::DEC64r:
265 case X86::DEC8r:
267 }
268}
269
270/// \returns the type of the second instruction in macro-fusion.
273 if (CC == X86::COND_INVALID)
275 switch (CC) {
276 default:
278 case X86::COND_E: // JE,JZ
279 case X86::COND_NE: // JNE,JNZ
280 case X86::COND_L: // JL,JNGE
281 case X86::COND_LE: // JLE,JNG
282 case X86::COND_G: // JG,JNLE
283 case X86::COND_GE: // JGE,JNL
285 case X86::COND_B: // JB,JC
286 case X86::COND_BE: // JNA,JBE
287 case X86::COND_A: // JA,JNBE
288 case X86::COND_AE: // JAE,JNC,JNB
290 case X86::COND_S: // JS
291 case X86::COND_NS: // JNS
292 case X86::COND_P: // JP,JPE
293 case X86::COND_NP: // JNP,JPO
294 case X86::COND_O: // JO
295 case X86::COND_NO: // JNO
297 }
298}
299
300/// \param FirstKind kind of the first instruction in macro fusion.
301/// \param SecondKind kind of the second instruction in macro fusion.
302///
303/// \returns true if the two instruction can be macro fused.
305 SecondMacroFusionInstKind SecondKind) {
306 switch (FirstKind) {
309 return true;
312 return SecondKind == X86::SecondMacroFusionInstKind::AB ||
315 return SecondKind == X86::SecondMacroFusionInstKind::ELG;
317 return false;
318 }
319 llvm_unreachable("unknown fusion type");
320}
321
322/// Defines the possible values of the branch boundary alignment mask.
326 AlignBranchJcc = 1U << 1,
327 AlignBranchJmp = 1U << 2,
329 AlignBranchRet = 1U << 4,
330 AlignBranchIndirect = 1U << 5
332
333/// Defines the encoding values for segment override prefix.
340 SS_Encoding = 0x36
342
343/// Given a segment register, return the encoding of the segment override
344/// prefix for it.
347 switch (Reg) {
348 default:
349 llvm_unreachable("Unknown segment register!");
350 case X86::CS:
351 return CS_Encoding;
352 case X86::DS:
353 return DS_Encoding;
354 case X86::ES:
355 return ES_Encoding;
356 case X86::FS:
357 return FS_Encoding;
358 case X86::GS:
359 return GS_Encoding;
360 case X86::SS:
361 return SS_Encoding;
362 }
363}
364
365} // namespace X86
366
367/// X86II - This namespace holds all of the target specific flags that
368/// instruction info tracks.
369///
370namespace X86II {
371/// Target Operand Flag enum.
372enum TOF {
373 //===------------------------------------------------------------------===//
374 // X86 Specific MachineOperand flags.
375 //
376 /// MO_NO_FLAG - No flag for the operand
378 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
379 /// relocation of:
380 /// SYMBOL_LABEL + [. - PICBASELABEL]
382 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
383 /// immediate should get the value of the symbol minus the PIC base label:
384 /// SYMBOL_LABEL - PICBASELABEL
386 /// MO_GOT - On a symbol operand this indicates that the immediate is the
387 /// offset to the GOT entry for the symbol name from the base of the GOT.
388 /// See the X86-64 ELF ABI supplement for more details.
389 /// SYMBOL_LABEL @GOT
391 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
392 /// the offset to the location of the symbol name from the base of the GOT.
393 /// See the X86-64 ELF ABI supplement for more details.
394 /// SYMBOL_LABEL @GOTOFF
396 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
397 /// offset to the GOT entry for the symbol name from the current code
398 /// location.
399 /// See the X86-64 ELF ABI supplement for more details.
400 /// SYMBOL_LABEL @GOTPCREL
402 /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
403 /// relocations are guaranteed to be emitted by the integrated assembler
404 /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
406 /// MO_PLT - On a symbol operand this indicates that the immediate is
407 /// offset to the PLT entry of symbol name from the current code location.
408 /// See the X86-64 ELF ABI supplement for more details.
409 /// SYMBOL_LABEL @PLT
411 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
412 /// the offset of the GOT entry with the TLS index structure that contains
413 /// the module number and variable offset for the symbol. Used in the
414 /// general dynamic TLS access model.
415 /// See 'ELF Handling for Thread-Local Storage' for more details.
416 /// SYMBOL_LABEL @TLSGD
418 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
419 /// the offset of the GOT entry with the TLS index for the module that
420 /// contains the symbol. When this index is passed to a call to
421 /// __tls_get_addr, the function will return the base address of the TLS
422 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
423 /// See 'ELF Handling for Thread-Local Storage' for more details.
424 /// SYMBOL_LABEL @TLSLD
426 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
427 /// the offset of the GOT entry with the TLS index for the module that
428 /// contains the symbol. When this index is passed to a call to
429 /// ___tls_get_addr, the function will return the base address of the TLS
430 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
431 /// See 'ELF Handling for Thread-Local Storage' for more details.
432 /// SYMBOL_LABEL @TLSLDM
434 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
435 /// the offset of the GOT entry with the thread-pointer offset for the
436 /// symbol. Used in the x86-64 initial exec TLS access model.
437 /// See 'ELF Handling for Thread-Local Storage' for more details.
438 /// SYMBOL_LABEL @GOTTPOFF
440 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
441 /// the absolute address of the GOT entry with the negative thread-pointer
442 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
443 /// model.
444 /// See 'ELF Handling for Thread-Local Storage' for more details.
445 /// SYMBOL_LABEL @INDNTPOFF
447 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
448 /// the thread-pointer offset for the symbol. Used in the x86-64 local
449 /// exec TLS access model.
450 /// See 'ELF Handling for Thread-Local Storage' for more details.
451 /// SYMBOL_LABEL @TPOFF
453 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
454 /// the offset of the GOT entry with the TLS offset of the symbol. Used
455 /// in the local dynamic TLS access model.
456 /// See 'ELF Handling for Thread-Local Storage' for more details.
457 /// SYMBOL_LABEL @DTPOFF
459 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
460 /// the negative thread-pointer offset for the symbol. Used in the IA32
461 /// local exec TLS access model.
462 /// See 'ELF Handling for Thread-Local Storage' for more details.
463 /// SYMBOL_LABEL @NTPOFF
465 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
466 /// the offset of the GOT entry with the negative thread-pointer offset for
467 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
468 /// See 'ELF Handling for Thread-Local Storage' for more details.
469 /// SYMBOL_LABEL @GOTNTPOFF
471 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
472 /// reference is actually to the "__imp_FOO" symbol. This is used for
473 /// dllimport linkage on windows.
475 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
476 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
477 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
479 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
480 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
481 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
483 /// MO_TLVP - On a symbol operand this indicates that the immediate is
484 /// some TLS offset.
485 /// This is the TLS offset for the Darwin TLS mechanism.
487 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
488 /// is some TLS offset from the picbase.
489 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
491 /// MO_SECREL - On a symbol operand this indicates that the immediate is
492 /// the offset from beginning of section.
493 /// This is the TLS offset for the COFF/Windows TLS mechanism.
495 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
496 /// to be an absolute symbol in range [0,128), so we can use the @ABS8
497 /// symbol modifier.
499 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
500 /// reference is actually to the ".refptr.FOO" symbol. This is used for
501 /// stub symbols on windows.
503};
504
505enum : uint64_t {
506 //===------------------------------------------------------------------===//
507 // Instruction encodings. These are the standard/most common forms for X86
508 // instructions.
509 //
510 /// PseudoFrm - This represents an instruction that is a pseudo instruction
511 /// or one that has not been implemented yet. It is illegal to code generate
512 /// it, but tolerated for intermediate implementation stages.
514 /// Raw - This form is for instructions that don't have any operands, so
515 /// they are just a fixed opcode value, like 'leave'.
517 /// AddRegFrm - This form is used for instructions like 'push r32' that have
518 /// their one register operand added to their opcode.
520 /// RawFrmMemOffs - This form is for instructions that store an absolute
521 /// memory offset as an immediate with a possible segment override.
523 /// RawFrmSrc - This form is for instructions that use the source index
524 /// register SI/ESI/RSI with a possible segment override.
526 /// RawFrmDst - This form is for instructions that use the destination index
527 /// register DI/EDI/RDI.
529 /// RawFrmDstSrc - This form is for instructions that use the source index
530 /// register SI/ESI/RSI with a possible segment override, and also the
531 /// destination index register DI/EDI/RDI.
533 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
534 /// immediates, the first of which is a 16-bit immediate (specified by
535 /// the imm encoding) and the second is a 8-bit fixed value.
537 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
538 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
539 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
540 /// manual, this operand is described as pntr16:32 and pntr16:16
542 /// AddCCFrm - This form is used for Jcc that encode the condition code
543 /// in the lower 4 bits of the opcode.
545 /// PrefixByte - This form is used for instructions that represent a prefix
546 /// byte like data16 or rep.
548 /// MRMDestRegCC - This form is used for the cfcmov instructions, which use
549 /// the Mod/RM byte to specify the operands reg(r/m) and reg(reg) and also
550 /// encodes a condition code.
552 /// MRMDestMemCC - This form is used for the cfcmov instructions, which use
553 /// the Mod/RM byte to specify the operands mem(r/m) and reg(reg) and also
554 /// encodes a condition code.
556 /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
557 /// byte to specify a destination which in this case is memory and operand 3
558 /// with VEX.VVVV, and also encodes a condition code.
560 /// Instructions operate on a register Reg/Opcode operand not the r/m field.
561 MRMr0 = 21,
562 /// MRMSrcMem - But force to use the SIB field.
564 /// MRMDestMem - But force to use the SIB field.
566 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
567 /// to specify a destination, which in this case is memory.
569 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
570 /// to specify a source, which in this case is memory.
572 /// MRMSrcMem4VOp3 - This form is used for instructions that encode
573 /// operand 3 with VEX.VVVV and load from memory.
575 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
576 /// byte to specify the fourth source, which in this case is memory.
578 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
579 /// byte to specify the operands and also encodes a condition code.
581 /// MRMXm - This form is used for instructions that use the Mod/RM byte
582 /// to specify a memory source, but doesn't use the middle field. And has
583 /// a condition code.
585 /// MRMXm - This form is used for instructions that use the Mod/RM byte
586 /// to specify a memory source, but doesn't use the middle field.
587 MRMXm = 31,
588 /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
589 /// reg field to hold extended opcode, which is represented as /0, /1, ...
590 MRM0m = 32, // Format /0
591 MRM1m = 33, // Format /1
592 MRM2m = 34, // Format /2
593 MRM3m = 35, // Format /3
594 MRM4m = 36, // Format /4
595 MRM5m = 37, // Format /5
596 MRM6m = 38, // Format /6
597 MRM7m = 39, // Format /7
598 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
599 /// to specify a destination, which in this case is a register.
601 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
602 /// to specify a source, which in this case is a register.
604 /// MRMSrcReg4VOp3 - This form is used for instructions that encode
605 /// operand 3 with VEX.VVVV and do not load from memory.
607 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
608 /// byte to specify the fourth source, which in this case is a register.
610 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
611 /// byte to specify the operands and also encodes a condition code
613 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
614 /// to specify a register source, but doesn't use the middle field. And has
615 /// a condition code.
617 /// MRMXr - This form is used for instructions that use the Mod/RM byte
618 /// to specify a register source, but doesn't use the middle field.
619 MRMXr = 47,
620 /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
621 /// reg field to hold extended opcode, which is represented as /0, /1, ...
622 MRM0r = 48, // Format /0
623 MRM1r = 49, // Format /1
624 MRM2r = 50, // Format /2
625 MRM3r = 51, // Format /3
626 MRM4r = 52, // Format /4
627 MRM5r = 53, // Format /5
628 MRM6r = 54, // Format /6
629 MRM7r = 55, // Format /7
630 /// MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but
631 /// ignore r/m.
632 MRM0X = 56, // Format /0
633 MRM1X = 57, // Format /1
634 MRM2X = 58, // Format /2
635 MRM3X = 59, // Format /3
636 MRM4X = 60, // Format /4
637 MRM5X = 61, // Format /5
638 MRM6X = 62, // Format /6
639 MRM7X = 63, // Format /7
640 /// MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
641 MRM_C0 = 64,
642 MRM_C1 = 65,
643 MRM_C2 = 66,
644 MRM_C3 = 67,
645 MRM_C4 = 68,
646 MRM_C5 = 69,
647 MRM_C6 = 70,
648 MRM_C7 = 71,
649 MRM_C8 = 72,
650 MRM_C9 = 73,
651 MRM_CA = 74,
652 MRM_CB = 75,
653 MRM_CC = 76,
654 MRM_CD = 77,
655 MRM_CE = 78,
656 MRM_CF = 79,
657 MRM_D0 = 80,
658 MRM_D1 = 81,
659 MRM_D2 = 82,
660 MRM_D3 = 83,
661 MRM_D4 = 84,
662 MRM_D5 = 85,
663 MRM_D6 = 86,
664 MRM_D7 = 87,
665 MRM_D8 = 88,
666 MRM_D9 = 89,
667 MRM_DA = 90,
668 MRM_DB = 91,
669 MRM_DC = 92,
670 MRM_DD = 93,
671 MRM_DE = 94,
672 MRM_DF = 95,
673 MRM_E0 = 96,
674 MRM_E1 = 97,
675 MRM_E2 = 98,
676 MRM_E3 = 99,
677 MRM_E4 = 100,
678 MRM_E5 = 101,
679 MRM_E6 = 102,
680 MRM_E7 = 103,
681 MRM_E8 = 104,
682 MRM_E9 = 105,
683 MRM_EA = 106,
684 MRM_EB = 107,
685 MRM_EC = 108,
686 MRM_ED = 109,
687 MRM_EE = 110,
688 MRM_EF = 111,
689 MRM_F0 = 112,
690 MRM_F1 = 113,
691 MRM_F2 = 114,
692 MRM_F3 = 115,
693 MRM_F4 = 116,
694 MRM_F5 = 117,
695 MRM_F6 = 118,
696 MRM_F7 = 119,
697 MRM_F8 = 120,
698 MRM_F9 = 121,
699 MRM_FA = 122,
700 MRM_FB = 123,
701 MRM_FC = 124,
702 MRM_FD = 125,
703 MRM_FE = 126,
704 MRM_FF = 127,
705 FormMask = 127,
706 //===------------------------------------------------------------------===//
707 // Actual flags...
708 /// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
709 /// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
710 /// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
711 /// prefix in 16-bit mode.
717 /// AsSize - AdSizeX implies this instruction determines its need of 0x67
718 /// prefix from a normal ModRM memory operand. The other types indicate that
719 /// an operand is encoded with a specific width and a prefix is needed if
720 /// it differs from the current mode.
727 //===------------------------------------------------------------------===//
728 /// OpPrefix - There are several prefix bytes that are used as opcode
729 /// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
730 /// no prefix.
733 /// PD - Prefix code for packed double precision vector floating point
734 /// operations performed in the SSE registers.
736 /// XS, XD - These prefix codes are for single and double precision scalar
737 /// floating point operations performed in the SSE registers.
740 //===------------------------------------------------------------------===//
741 /// OpMap - This field determines which opcode map this instruction
742 /// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
745 /// OB - OneByte - Set if this instruction has a one byte opcode.
747 /// TB - TwoByte - Set if this instruction has a two byte opcode, which
748 /// starts with a 0x0F byte before the real opcode.
750 /// T8, TA - Prefix after the 0x0F prefix.
753 /// XOP8 - Prefix to include use of imm byte.
755 /// XOP9 - Prefix to exclude use of imm byte.
757 /// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
759 /// ThreeDNow - This indicates that the instruction uses the
760 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
761 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
762 /// storing a classifier in the imm8 field. To simplify our implementation,
763 /// we handle this by storeing the classifier in the opcode field and using
764 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
766 /// MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
771 //===------------------------------------------------------------------===//
772 /// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
773 /// They are used to specify GPRs and SSE registers, 64-bit operand size,
774 /// etc. We only cares about REX.W and REX.R bits and only the former is
775 /// statically determined.
778 //===------------------------------------------------------------------===//
779 // This 4-bit field describes the size of an immediate operand. Zero is
780 // unused so that we can tell if we forgot to set a value.
792 //===------------------------------------------------------------------===//
793 /// FP Instruction Classification... Zero is non-fp instruction.
794 /// FPTypeMask - Mask for all of the FP types...
797 /// NotFP - The default, set for instructions that do not use FP registers.
799 /// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
801 /// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
803 /// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
804 /// result back to ST(0). For example, fcos, fsqrt, etc.
806 /// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
807 /// explicit argument, storing the result to either ST(0) or the implicit
808 /// argument. For example: fadd, fsub, fmul, etc...
810 /// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
811 /// explicit argument, but have no destination. Example: fucom, fucomi, ...
813 /// CondMovFP - "2 operand" floating point conditional move instructions.
815 /// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
817 /// Lock prefix
820 /// REP prefix
822 REP = 1 << REPShift,
823 /// Execution domain for SSE instructions.
824 /// 0 means normal, non-SSE instruction.
826 /// Encoding
829 /// LEGACY - encoding using REX/REX2 or w/o opcode prefix.
831 /// VEX - encoding using 0xC4/0xC5
833 /// XOP - Opcode prefix used by XOP instructions.
835 /// EVEX - Specifies that this instruction use EVEX form which provides
836 /// syntax support up to 32 512-bit register operands and up to 7 16-bit
837 /// mask operands as well as source operand data swizzling/memory operand
838 /// conversion, eviction hint, and rounding mode.
840 /// Opcode
842 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
843 /// address instructions in SSE are represented as 3 address ones in AVX
844 /// and the additional register is encoded in VEX_VVVV prefix.
847 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
848 /// instruction uses 256-bit wide registers. This is usually auto detected
849 /// if a VR256 register is used, but some AVX instructions also have this
850 /// field marked when using a f256 memory references.
852 VEX_L = 1ULL << VEX_LShift,
853 /// EVEX_K - Set if this instruction requires masking
856 /// EVEX_Z - Set if this instruction has EVEX.Z field set.
859 /// EVEX_L2 - Set if this instruction has EVEX.L' field set.
862 /// EVEX_B - Set if this instruction has EVEX.B field set.
865 /// The scaling factor for the AVX512's 8-bit compressed displacement.
868 /// Explicitly specified rounding control
871 /// NOTRACK prefix
874 /// Force REX2/VEX/EVEX encoding
876 /// For instructions that require REX2 prefix even if EGPR is not used.
878 /// For instructions that use VEX encoding only when {vex}, {vex2} or {vex3}
879 /// is present.
881 /// For instructions that are promoted to EVEX space for EGPR.
884 /// EVEX_NF - Set if this instruction has EVEX.NF field set.
887 // TwoConditionalOps - Set if this instruction has two conditional operands
891
892/// \returns true if the instruction with given opcode is a prefix.
893inline bool isPrefix(uint64_t TSFlags) {
894 return (TSFlags & X86II::FormMask) == PrefixByte;
895}
896
897/// \returns true if the instruction with given opcode is a pseudo.
898inline bool isPseudo(uint64_t TSFlags) {
899 return (TSFlags & X86II::FormMask) == Pseudo;
900}
901
902/// \returns the "base" X86 opcode for the specified machine
903/// instruction.
904inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
905 return TSFlags >> X86II::OpcodeShift;
906}
907
908inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; }
909
910/// Decode the "size of immediate" field from the TSFlags field of the
911/// specified instruction.
912inline unsigned getSizeOfImm(uint64_t TSFlags) {
913 switch (TSFlags & X86II::ImmMask) {
914 default:
915 llvm_unreachable("Unknown immediate size");
916 case X86II::Imm8:
917 case X86II::Imm8PCRel:
918 case X86II::Imm8Reg:
919 return 1;
920 case X86II::Imm16:
922 return 2;
923 case X86II::Imm32:
924 case X86II::Imm32S:
926 return 4;
927 case X86II::Imm64:
928 return 8;
929 }
930}
931
932/// \returns true if the immediate of the specified instruction's TSFlags
933/// indicates that it is pc relative.
934inline bool isImmPCRel(uint64_t TSFlags) {
935 switch (TSFlags & X86II::ImmMask) {
936 default:
937 llvm_unreachable("Unknown immediate size");
938 case X86II::Imm8PCRel:
941 return true;
942 case X86II::Imm8:
943 case X86II::Imm8Reg:
944 case X86II::Imm16:
945 case X86II::Imm32:
946 case X86II::Imm32S:
947 case X86II::Imm64:
948 return false;
949 }
950}
951
952/// \returns true if the immediate of the specified instruction's
953/// TSFlags indicates that it is signed.
954inline bool isImmSigned(uint64_t TSFlags) {
955 switch (TSFlags & X86II::ImmMask) {
956 default:
957 llvm_unreachable("Unknown immediate signedness");
958 case X86II::Imm32S:
959 return true;
960 case X86II::Imm8:
961 case X86II::Imm8PCRel:
962 case X86II::Imm8Reg:
963 case X86II::Imm16:
965 case X86II::Imm32:
967 case X86II::Imm64:
968 return false;
969 }
970}
971
972/// Compute whether all of the def operands are repeated in the uses and
973/// therefore should be skipped.
974/// This determines the start of the unique operand list. We need to determine
975/// if all of the defs have a corresponding tied operand in the uses.
976/// Unfortunately, the tied operand information is encoded in the uses not
977/// the defs so we have to use some heuristics to find which operands to
978/// query.
979inline unsigned getOperandBias(const MCInstrDesc &Desc) {
980 unsigned NumDefs = Desc.getNumDefs();
981 unsigned NumOps = Desc.getNumOperands();
982 switch (NumDefs) {
983 default:
984 llvm_unreachable("Unexpected number of defs");
985 case 0:
986 return 0;
987 case 1:
988 // Common two addr case.
989 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
990 return 1;
991 // Check for AVX-512 scatter which has a TIED_TO in the second to last
992 // operand.
993 if (NumOps == 8 && Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
994 return 1;
995 return 0;
996 case 2:
997 // XCHG/XADD have two destinations and two sources.
998 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
999 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
1000 return 2;
1001 // Check for gather. AVX-512 has the second tied operand early. AVX2
1002 // has it as the last op.
1003 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
1004 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
1005 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
1006 return 2;
1007 return 0;
1008 }
1009}
1010
1011/// \returns true if the instruction has a NDD (new data destination).
1012inline bool hasNewDataDest(uint64_t TSFlags) {
1013 return (TSFlags & X86II::OpMapMask) == X86II::T_MAP4 &&
1014 (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V);
1015}
1016
1017/// \returns operand # for the first field of the memory operand or -1 if no
1018/// memory operands.
1019/// NOTE: This ignores tied operands. If there is a tied register which is
1020/// duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted
1021/// as one operand.
1022inline int getMemoryOperandNo(uint64_t TSFlags) {
1023 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1024 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1025
1026 switch (TSFlags & X86II::FormMask) {
1027 default:
1028 llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1029 case X86II::Pseudo:
1030 case X86II::RawFrm:
1031 case X86II::AddRegFrm:
1032 case X86II::RawFrmImm8:
1033 case X86II::RawFrmImm16:
1035 case X86II::RawFrmSrc:
1036 case X86II::RawFrmDst:
1038 case X86II::AddCCFrm:
1039 case X86II::PrefixByte:
1040 return -1;
1041 case X86II::MRMDestMem:
1044 return hasNewDataDest(TSFlags);
1045 case X86II::MRMSrcMem:
1047 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1048 // mask register.
1049 return 1 + HasVEX_4V + HasEVEX_K;
1051 // Skip registers encoded in reg.
1052 return 1 + HasEVEX_K;
1054 // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1055 return 3;
1056 case X86II::MRMSrcMemCC:
1057 return 1 + hasNewDataDest(TSFlags);
1059 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1060 // mask register.
1061 return 1;
1062 case X86II::MRMDestReg:
1064 case X86II::MRMSrcReg:
1067 case X86II::MRMSrcRegCC:
1068 case X86II::MRMXrCC:
1069 case X86II::MRMr0:
1070 case X86II::MRMXr:
1071 case X86II::MRM0r:
1072 case X86II::MRM1r:
1073 case X86II::MRM2r:
1074 case X86II::MRM3r:
1075 case X86II::MRM4r:
1076 case X86II::MRM5r:
1077 case X86II::MRM6r:
1078 case X86II::MRM7r:
1079 return -1;
1080 case X86II::MRM0X:
1081 case X86II::MRM1X:
1082 case X86II::MRM2X:
1083 case X86II::MRM3X:
1084 case X86II::MRM4X:
1085 case X86II::MRM5X:
1086 case X86II::MRM6X:
1087 case X86II::MRM7X:
1088 return -1;
1089 case X86II::MRMXmCC:
1090 case X86II::MRMXm:
1091 case X86II::MRM0m:
1092 case X86II::MRM1m:
1093 case X86II::MRM2m:
1094 case X86II::MRM3m:
1095 case X86II::MRM4m:
1096 case X86II::MRM5m:
1097 case X86II::MRM6m:
1098 case X86II::MRM7m:
1099 // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1100 return 0 + HasVEX_4V + HasEVEX_K;
1101 case X86II::MRM_C0:
1102 case X86II::MRM_C1:
1103 case X86II::MRM_C2:
1104 case X86II::MRM_C3:
1105 case X86II::MRM_C4:
1106 case X86II::MRM_C5:
1107 case X86II::MRM_C6:
1108 case X86II::MRM_C7:
1109 case X86II::MRM_C8:
1110 case X86II::MRM_C9:
1111 case X86II::MRM_CA:
1112 case X86II::MRM_CB:
1113 case X86II::MRM_CC:
1114 case X86II::MRM_CD:
1115 case X86II::MRM_CE:
1116 case X86II::MRM_CF:
1117 case X86II::MRM_D0:
1118 case X86II::MRM_D1:
1119 case X86II::MRM_D2:
1120 case X86II::MRM_D3:
1121 case X86II::MRM_D4:
1122 case X86II::MRM_D5:
1123 case X86II::MRM_D6:
1124 case X86II::MRM_D7:
1125 case X86II::MRM_D8:
1126 case X86II::MRM_D9:
1127 case X86II::MRM_DA:
1128 case X86II::MRM_DB:
1129 case X86II::MRM_DC:
1130 case X86II::MRM_DD:
1131 case X86II::MRM_DE:
1132 case X86II::MRM_DF:
1133 case X86II::MRM_E0:
1134 case X86II::MRM_E1:
1135 case X86II::MRM_E2:
1136 case X86II::MRM_E3:
1137 case X86II::MRM_E4:
1138 case X86II::MRM_E5:
1139 case X86II::MRM_E6:
1140 case X86II::MRM_E7:
1141 case X86II::MRM_E8:
1142 case X86II::MRM_E9:
1143 case X86II::MRM_EA:
1144 case X86II::MRM_EB:
1145 case X86II::MRM_EC:
1146 case X86II::MRM_ED:
1147 case X86II::MRM_EE:
1148 case X86II::MRM_EF:
1149 case X86II::MRM_F0:
1150 case X86II::MRM_F1:
1151 case X86II::MRM_F2:
1152 case X86II::MRM_F3:
1153 case X86II::MRM_F4:
1154 case X86II::MRM_F5:
1155 case X86II::MRM_F6:
1156 case X86II::MRM_F7:
1157 case X86II::MRM_F8:
1158 case X86II::MRM_F9:
1159 case X86II::MRM_FA:
1160 case X86II::MRM_FB:
1161 case X86II::MRM_FC:
1162 case X86II::MRM_FD:
1163 case X86II::MRM_FE:
1164 case X86II::MRM_FF:
1165 return -1;
1166 }
1167}
1168
1169/// \returns true if the register is a XMM.
1170inline bool isXMMReg(unsigned RegNo) {
1171 assert(X86::XMM15 - X86::XMM0 == 15 &&
1172 "XMM0-15 registers are not continuous");
1173 assert(X86::XMM31 - X86::XMM16 == 15 &&
1174 "XMM16-31 registers are not continuous");
1175 return (RegNo >= X86::XMM0 && RegNo <= X86::XMM15) ||
1176 (RegNo >= X86::XMM16 && RegNo <= X86::XMM31);
1177}
1178
1179/// \returns true if the register is a YMM.
1180inline bool isYMMReg(unsigned RegNo) {
1181 assert(X86::YMM15 - X86::YMM0 == 15 &&
1182 "YMM0-15 registers are not continuous");
1183 assert(X86::YMM31 - X86::YMM16 == 15 &&
1184 "YMM16-31 registers are not continuous");
1185 return (RegNo >= X86::YMM0 && RegNo <= X86::YMM15) ||
1186 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31);
1187}
1188
1189/// \returns true if the register is a ZMM.
1190inline bool isZMMReg(unsigned RegNo) {
1191 assert(X86::ZMM31 - X86::ZMM0 == 31 && "ZMM registers are not continuous");
1192 return RegNo >= X86::ZMM0 && RegNo <= X86::ZMM31;
1193}
1194
1195/// \returns true if \p RegNo is an apx extended register.
1196inline bool isApxExtendedReg(unsigned RegNo) {
1197 assert(X86::R31WH - X86::R16 == 95 && "EGPRs are not continuous");
1198 return RegNo >= X86::R16 && RegNo <= X86::R31WH;
1199}
1200
1201/// \returns true if the MachineOperand is a x86-64 extended (r8 or
1202/// higher) register, e.g. r8, xmm8, xmm13, etc.
1203inline bool isX86_64ExtendedReg(unsigned RegNo) {
1204 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM15) ||
1205 (RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1206 (RegNo >= X86::YMM8 && RegNo <= X86::YMM15) ||
1207 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1208 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
1209 return true;
1210
1211 if (isApxExtendedReg(RegNo))
1212 return true;
1213
1214 switch (RegNo) {
1215 default:
1216 break;
1217 case X86::R8:
1218 case X86::R9:
1219 case X86::R10:
1220 case X86::R11:
1221 case X86::R12:
1222 case X86::R13:
1223 case X86::R14:
1224 case X86::R15:
1225 case X86::R8D:
1226 case X86::R9D:
1227 case X86::R10D:
1228 case X86::R11D:
1229 case X86::R12D:
1230 case X86::R13D:
1231 case X86::R14D:
1232 case X86::R15D:
1233 case X86::R8W:
1234 case X86::R9W:
1235 case X86::R10W:
1236 case X86::R11W:
1237 case X86::R12W:
1238 case X86::R13W:
1239 case X86::R14W:
1240 case X86::R15W:
1241 case X86::R8B:
1242 case X86::R9B:
1243 case X86::R10B:
1244 case X86::R11B:
1245 case X86::R12B:
1246 case X86::R13B:
1247 case X86::R14B:
1248 case X86::R15B:
1249 case X86::CR8:
1250 case X86::CR9:
1251 case X86::CR10:
1252 case X86::CR11:
1253 case X86::CR12:
1254 case X86::CR13:
1255 case X86::CR14:
1256 case X86::CR15:
1257 case X86::DR8:
1258 case X86::DR9:
1259 case X86::DR10:
1260 case X86::DR11:
1261 case X86::DR12:
1262 case X86::DR13:
1263 case X86::DR14:
1264 case X86::DR15:
1265 return true;
1266 }
1267 return false;
1268}
1269
1271 uint64_t TSFlags = Desc.TSFlags;
1272 uint64_t Encoding = TSFlags & EncodingMask;
1273 // EVEX can always use egpr.
1274 if (Encoding == X86II::EVEX)
1275 return true;
1276
1277 unsigned Opcode = Desc.Opcode;
1278 // MOV32r0 is always expanded to XOR32rr
1279 if (Opcode == X86::MOV32r0)
1280 return true;
1281 // To be conservative, egpr is not used for all pseudo instructions
1282 // because we are not sure what instruction it will become.
1283 // FIXME: Could we improve it in X86ExpandPseudo?
1284 if (isPseudo(TSFlags))
1285 return false;
1286
1287 // MAP OB/TB in legacy encoding space can always use egpr except
1288 // XSAVE*/XRSTOR*.
1289 switch (Opcode) {
1290 default:
1291 break;
1292 case X86::XSAVE:
1293 case X86::XSAVE64:
1294 case X86::XSAVEOPT:
1295 case X86::XSAVEOPT64:
1296 case X86::XSAVEC:
1297 case X86::XSAVEC64:
1298 case X86::XSAVES:
1299 case X86::XSAVES64:
1300 case X86::XRSTOR:
1301 case X86::XRSTOR64:
1302 case X86::XRSTORS:
1303 case X86::XRSTORS64:
1304 return false;
1305 }
1306 uint64_t OpMap = TSFlags & X86II::OpMapMask;
1307 return !Encoding && (OpMap == X86II::OB || OpMap == X86II::TB);
1308}
1309
1310/// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1311/// registers, e.g. zmm21, etc.
1312static inline bool is32ExtendedReg(unsigned RegNo) {
1313 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1314 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1315 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
1316}
1317
1318inline bool isX86_64NonExtLowByteReg(unsigned reg) {
1319 return (reg == X86::SPL || reg == X86::BPL || reg == X86::SIL ||
1320 reg == X86::DIL);
1321}
1322
1323/// \returns true if this is a masked instruction.
1324inline bool isKMasked(uint64_t TSFlags) {
1325 return (TSFlags & X86II::EVEX_K) != 0;
1326}
1327
1328/// \returns true if this is a merge masked instruction.
1329inline bool isKMergeMasked(uint64_t TSFlags) {
1330 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1331}
1332
1333/// \returns true if the intruction needs a SIB.
1334inline bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode) {
1335 // The SIB byte must be used if there is an index register.
1336 if (IndexReg)
1337 return true;
1338
1339 // The SIB byte must be used if the base is ESP/RSP/R12/R20/R28, all of
1340 // which encode to an R/M value of 4, which indicates that a SIB byte is
1341 // present.
1342 switch (BaseReg) {
1343 default:
1344 // If there is no base register and we're in 64-bit mode, we need a SIB
1345 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
1346 return In64BitMode && !BaseReg;
1347 case X86::ESP:
1348 case X86::RSP:
1349 case X86::R12:
1350 case X86::R12D:
1351 case X86::R20:
1352 case X86::R20D:
1353 case X86::R28:
1354 case X86::R28D:
1355 return true;
1356 }
1357}
1358
1359} // namespace X86II
1360} // namespace llvm
1361#endif
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
@ X86
Windows x64, Windows Itanium (IA-64)
bool isKMergeMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1329
bool isXMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1170
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1203
bool isPrefix(uint64_t TSFlags)
Definition: X86BaseInfo.h:893
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:908
bool hasNewDataDest(uint64_t TSFlags)
Definition: X86BaseInfo.h:1012
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:372
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:425
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:405
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:395
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:482
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition: X86BaseInfo.h:381
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:502
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:464
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:478
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:446
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:470
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:452
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:490
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:390
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:498
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:410
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:417
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
Definition: X86BaseInfo.h:377
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:486
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:474
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:439
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:494
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:458
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:385
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:433
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:401
@ ExplicitOpPrefixShift
Force REX2/VEX/EVEX encoding.
Definition: X86BaseInfo.h:875
@ MRM0X
MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but ignore r/m.
Definition: X86BaseInfo.h:632
@ EVEX_ZShift
EVEX_Z - Set if this instruction has EVEX.Z field set.
Definition: X86BaseInfo.h:857
@ RawFrm
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:516
@ VEX_LShift
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:851
@ SpecialFP
SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
Definition: X86BaseInfo.h:816
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:532
@ EVEX_KShift
EVEX_K - Set if this instruction requires masking.
Definition: X86BaseInfo.h:854
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
Definition: X86BaseInfo.h:839
@ OpcodeShift
Opcode.
Definition: X86BaseInfo.h:841
@ ExplicitREX2Prefix
For instructions that require REX2 prefix even if EGPR is not used.
Definition: X86BaseInfo.h:877
@ EVEX_BShift
EVEX_B - Set if this instruction has EVEX.B field set.
Definition: X86BaseInfo.h:863
@ MRMSrcMemCC
MRMSrcMemCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:580
@ NotFP
NotFP - The default, set for instructions that do not use FP registers.
Definition: X86BaseInfo.h:798
@ MRM_C0
MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:641
@ RawFrmDst
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI.
Definition: X86BaseInfo.h:528
@ OpPrefixShift
OpPrefix - There are several prefix bytes that are used as opcode extensions.
Definition: X86BaseInfo.h:731
@ MRMDestMem4VOp3CC
MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM byte to specify a destinat...
Definition: X86BaseInfo.h:559
@ OB
OB - OneByte - Set if this instruction has a one byte opcode.
Definition: X86BaseInfo.h:746
@ AddCCFrm
AddCCFrm - This form is used for Jcc that encode the condition code in the lower 4 bits of the opcode...
Definition: X86BaseInfo.h:544
@ T_MAP4
MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:767
@ PrefixByte
PrefixByte - This form is used for instructions that represent a prefix byte like data16 or rep.
Definition: X86BaseInfo.h:547
@ MRMr0
Instructions operate on a register Reg/Opcode operand not the r/m field.
Definition: X86BaseInfo.h:561
@ TwoConditionalOps_Shift
Definition: X86BaseInfo.h:888
@ MRMXm
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:587
@ OneArgFPRW
OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a result back to ST(0).
Definition: X86BaseInfo.h:805
@ MRM0r
MRM0r-MRM7r - Instructions that operate on a register r/m operand and use reg field to hold extended ...
Definition: X86BaseInfo.h:622
@ MRMDestMemFSIB
MRMDestMem - But force to use the SIB field.
Definition: X86BaseInfo.h:565
@ AddRegFrm
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:519
@ ExplicitEVEXPrefix
For instructions that are promoted to EVEX space for EGPR.
Definition: X86BaseInfo.h:882
@ VEX
VEX - encoding using 0xC4/0xC5.
Definition: X86BaseInfo.h:832
@ RawFrmImm8
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:536
@ OpSizeShift
OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
Definition: X86BaseInfo.h:712
@ TB
TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...
Definition: X86BaseInfo.h:749
@ XOP
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:834
@ MRMXr
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:619
@ LOCKShift
Lock prefix.
Definition: X86BaseInfo.h:818
@ MRMSrcMem4VOp3
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:574
@ EVEX_L2Shift
EVEX_L2 - Set if this instruction has EVEX.L' field set.
Definition: X86BaseInfo.h:860
@ XOP8
XOP8 - Prefix to include use of imm byte.
Definition: X86BaseInfo.h:754
@ ZeroArgFP
ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0.
Definition: X86BaseInfo.h:800
@ REXShift
REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
Definition: X86BaseInfo.h:776
@ MRMDestRegCC
MRMDestRegCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:551
@ AdSizeShift
AsSize - AdSizeX implies this instruction determines its need of 0x67 prefix from a normal ModRM memo...
Definition: X86BaseInfo.h:721
@ REPShift
REP prefix.
Definition: X86BaseInfo.h:821
@ PD
PD - Prefix code for packed double precision vector floating point operations performed in the SSE re...
Definition: X86BaseInfo.h:735
@ MRMDestMem
MRMDestMem - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:568
@ EncodingShift
Encoding.
Definition: X86BaseInfo.h:827
@ OneArgFP
OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst.
Definition: X86BaseInfo.h:802
@ MRMSrcMemFSIB
MRMSrcMem - But force to use the SIB field.
Definition: X86BaseInfo.h:563
@ CompareFP
CompareFP - 2 arg FP instructions which implicitly read ST(0) and an explicit argument,...
Definition: X86BaseInfo.h:812
@ NoTrackShift
NOTRACK prefix.
Definition: X86BaseInfo.h:872
@ ExplicitVEXPrefix
For instructions that use VEX encoding only when {vex}, {vex2} or {vex3} is present.
Definition: X86BaseInfo.h:880
@ EVEX_RCShift
Explicitly specified rounding control.
Definition: X86BaseInfo.h:869
@ MRMSrcRegOp4
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:609
@ MRMXrCC
MRMXCCr - This form is used for instructions that use the Mod/RM byte to specify a register source,...
Definition: X86BaseInfo.h:616
@ T8
T8, TA - Prefix after the 0x0F prefix.
Definition: X86BaseInfo.h:751
@ MRMDestMemCC
MRMDestMemCC - This form is used for the cfcmov instructions, which use the Mod/RM byte to specify th...
Definition: X86BaseInfo.h:555
@ XOP9
XOP9 - Prefix to exclude use of imm byte.
Definition: X86BaseInfo.h:756
@ MRMXmCC
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source,...
Definition: X86BaseInfo.h:584
@ RawFrmImm16
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:541
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:603
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:525
@ MRMDestReg
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination,...
Definition: X86BaseInfo.h:600
@ MRMSrcMem
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:571
@ MRMSrcMemOp4
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:577
@ Pseudo
PseudoFrm - This represents an instruction that is a pseudo instruction or one that has not been impl...
Definition: X86BaseInfo.h:513
@ VEX_4VShift
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:845
@ CD8_Scale_Shift
The scaling factor for the AVX512's 8-bit compressed displacement.
Definition: X86BaseInfo.h:866
@ MRMSrcRegCC
MRMSrcRegCC - This form is used for instructions that use the Mod/RM byte to specify the operands and...
Definition: X86BaseInfo.h:612
@ SSEDomainShift
Execution domain for SSE instructions.
Definition: X86BaseInfo.h:825
@ CondMovFP
CondMovFP - "2 operand" floating point conditional move instructions.
Definition: X86BaseInfo.h:814
@ MRM0m
MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use reg field to hold extended op...
Definition: X86BaseInfo.h:590
@ ThreeDNow
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow!...
Definition: X86BaseInfo.h:765
@ XS
XS, XD - These prefix codes are for single and double precision scalar floating point operations perf...
Definition: X86BaseInfo.h:738
@ ExplicitOpPrefixMask
Definition: X86BaseInfo.h:883
@ FPTypeShift
FP Instruction Classification... Zero is non-fp instruction.
Definition: X86BaseInfo.h:795
@ XOPA
XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
Definition: X86BaseInfo.h:758
@ MRMSrcReg4VOp3
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX....
Definition: X86BaseInfo.h:606
@ OpMapShift
OpMap - This field determines which opcode map this instruction belongs to.
Definition: X86BaseInfo.h:743
@ LEGACY
LEGACY - encoding using REX/REX2 or w/o opcode prefix.
Definition: X86BaseInfo.h:830
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:522
@ TwoArgFP
TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an explicit argument,...
Definition: X86BaseInfo.h:809
@ EVEX_NFShift
EVEX_NF - Set if this instruction has EVEX.NF field set.
Definition: X86BaseInfo.h:885
bool isZMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1190
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:1318
bool isYMMReg(unsigned RegNo)
Definition: X86BaseInfo.h:1180
bool canUseApxExtendedReg(const MCInstrDesc &Desc)
Definition: X86BaseInfo.h:1270
bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode)
Definition: X86BaseInfo.h:1334
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:898
bool isImmPCRel(uint64_t TSFlags)
Definition: X86BaseInfo.h:934
unsigned getSizeOfImm(uint64_t TSFlags)
Decode the "size of immediate" field from the TSFlags field of the specified instruction.
Definition: X86BaseInfo.h:912
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:904
bool isKMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1324
bool isApxExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1196
int getMemoryOperandNo(uint64_t TSFlags)
Definition: X86BaseInfo.h:1022
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
Definition: X86BaseInfo.h:979
static bool is32ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1312
bool isImmSigned(uint64_t TSFlags)
Definition: X86BaseInfo.h:954
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
Definition: X86BaseInfo.h:124
@ OPERAND_COND_CODE
Definition: X86BaseInfo.h:70
@ OPERAND_ROUNDING_CONTROL
Definition: X86BaseInfo.h:69
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
@ LAST_VALID_COND
Definition: X86BaseInfo.h:92
@ COND_E_AND_NP
Definition: X86BaseInfo.h:99
@ COND_NE_OR_P
Definition: X86BaseInfo.h:98
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
Definition: X86BaseInfo.h:323
@ AlignBranchJmp
Definition: X86BaseInfo.h:327
@ AlignBranchIndirect
Definition: X86BaseInfo.h:330
@ AlignBranchJcc
Definition: X86BaseInfo.h:326
@ AlignBranchCall
Definition: X86BaseInfo.h:328
@ AlignBranchRet
Definition: X86BaseInfo.h:329
@ AlignBranchNone
Definition: X86BaseInfo.h:324
@ AlignBranchFused
Definition: X86BaseInfo.h:325
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:41
@ TO_NEAREST_INT
Definition: X86BaseInfo.h:42
@ CUR_DIRECTION
Definition: X86BaseInfo.h:46
EncodingOfSegmentOverridePrefix
Defines the encoding values for segment override prefix.
Definition: X86BaseInfo.h:334
SecondMacroFusionInstKind
Definition: X86BaseInfo.h:114
FirstMacroFusionInstKind
Definition: X86BaseInfo.h:105
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:51
@ IP_HAS_NOTRACK
Definition: X86BaseInfo.h:58
@ IP_USE_DISP8
Definition: X86BaseInfo.h:63
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_USE_DISP32
Definition: X86BaseInfo.h:64
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:53
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:52
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)
Definition: X86BaseInfo.h:272
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
Definition: X86BaseInfo.h:346
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
Definition: X86BaseInfo.h:304
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Description of the encoding of one expression Op.