LLVM  9.0.0svn
X86BaseInfo.h
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1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the X86 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 
19 #include "X86MCTargetDesc.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/DataTypes.h"
23 
24 namespace llvm {
25 
26 namespace X86 {
27  // Enums for memory operand decoding. Each memory operand is represented with
28  // a 5 operand sequence in the form:
29  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30  // These enums help decode this.
31  enum {
35  AddrDisp = 3,
36 
37  /// AddrSegmentReg - The operand # of the segment in the memory operand.
39 
40  /// AddrNumOperands - Total number of operands in a memory reference.
42  };
43 
44  /// AVX512 static rounding constants. These need to match the values in
45  /// avx512fintrin.h.
50  TO_ZERO = 3,
52  };
53 
54  /// The constants to describe instr prefixes if there are
55  enum IPREFIXES {
62  NO_SCHED_INFO = 32, // Don't add sched comment to the current instr because
63  // it was already added
65  };
66 } // end namespace X86;
67 
68 /// X86II - This namespace holds all of the target specific flags that
69 /// instruction info tracks.
70 ///
71 namespace X86II {
72  /// Target Operand Flag enum.
73  enum TOF {
74  //===------------------------------------------------------------------===//
75  // X86 Specific MachineOperand flags.
76 
78 
79  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80  /// relocation of:
81  /// SYMBOL_LABEL + [. - PICBASELABEL]
83 
84  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
85  /// immediate should get the value of the symbol minus the PIC base label:
86  /// SYMBOL_LABEL - PICBASELABEL
88 
89  /// MO_GOT - On a symbol operand this indicates that the immediate is the
90  /// offset to the GOT entry for the symbol name from the base of the GOT.
91  ///
92  /// See the X86-64 ELF ABI supplement for more details.
93  /// SYMBOL_LABEL @GOT
95 
96  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
97  /// the offset to the location of the symbol name from the base of the GOT.
98  ///
99  /// See the X86-64 ELF ABI supplement for more details.
100  /// SYMBOL_LABEL @GOTOFF
102 
103  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
104  /// offset to the GOT entry for the symbol name from the current code
105  /// location.
106  ///
107  /// See the X86-64 ELF ABI supplement for more details.
108  /// SYMBOL_LABEL @GOTPCREL
110 
111  /// MO_PLT - On a symbol operand this indicates that the immediate is
112  /// offset to the PLT entry of symbol name from the current code location.
113  ///
114  /// See the X86-64 ELF ABI supplement for more details.
115  /// SYMBOL_LABEL @PLT
117 
118  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
119  /// the offset of the GOT entry with the TLS index structure that contains
120  /// the module number and variable offset for the symbol. Used in the
121  /// general dynamic TLS access model.
122  ///
123  /// See 'ELF Handling for Thread-Local Storage' for more details.
124  /// SYMBOL_LABEL @TLSGD
126 
127  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
128  /// the offset of the GOT entry with the TLS index for the module that
129  /// contains the symbol. When this index is passed to a call to
130  /// __tls_get_addr, the function will return the base address of the TLS
131  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
132  ///
133  /// See 'ELF Handling for Thread-Local Storage' for more details.
134  /// SYMBOL_LABEL @TLSLD
136 
137  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
138  /// the offset of the GOT entry with the TLS index for the module that
139  /// contains the symbol. When this index is passed to a call to
140  /// ___tls_get_addr, the function will return the base address of the TLS
141  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
142  ///
143  /// See 'ELF Handling for Thread-Local Storage' for more details.
144  /// SYMBOL_LABEL @TLSLDM
146 
147  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
148  /// the offset of the GOT entry with the thread-pointer offset for the
149  /// symbol. Used in the x86-64 initial exec TLS access model.
150  ///
151  /// See 'ELF Handling for Thread-Local Storage' for more details.
152  /// SYMBOL_LABEL @GOTTPOFF
154 
155  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
156  /// the absolute address of the GOT entry with the negative thread-pointer
157  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
158  /// model.
159  ///
160  /// See 'ELF Handling for Thread-Local Storage' for more details.
161  /// SYMBOL_LABEL @INDNTPOFF
163 
164  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
165  /// the thread-pointer offset for the symbol. Used in the x86-64 local
166  /// exec TLS access model.
167  ///
168  /// See 'ELF Handling for Thread-Local Storage' for more details.
169  /// SYMBOL_LABEL @TPOFF
171 
172  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
173  /// the offset of the GOT entry with the TLS offset of the symbol. Used
174  /// in the local dynamic TLS access model.
175  ///
176  /// See 'ELF Handling for Thread-Local Storage' for more details.
177  /// SYMBOL_LABEL @DTPOFF
179 
180  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
181  /// the negative thread-pointer offset for the symbol. Used in the IA32
182  /// local exec TLS access model.
183  ///
184  /// See 'ELF Handling for Thread-Local Storage' for more details.
185  /// SYMBOL_LABEL @NTPOFF
187 
188  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
189  /// the offset of the GOT entry with the negative thread-pointer offset for
190  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
191  ///
192  /// See 'ELF Handling for Thread-Local Storage' for more details.
193  /// SYMBOL_LABEL @GOTNTPOFF
195 
196  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
197  /// reference is actually to the "__imp_FOO" symbol. This is used for
198  /// dllimport linkage on windows.
200 
201  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
202  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
203  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
205 
206  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
207  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
208  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
210 
211  /// MO_TLVP - On a symbol operand this indicates that the immediate is
212  /// some TLS offset.
213  ///
214  /// This is the TLS offset for the Darwin TLS mechanism.
216 
217  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
218  /// is some TLS offset from the picbase.
219  ///
220  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
222 
223  /// MO_SECREL - On a symbol operand this indicates that the immediate is
224  /// the offset from beginning of section.
225  ///
226  /// This is the TLS offset for the COFF/Windows TLS mechanism.
228 
229  /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
230  /// to be an absolute symbol in range [0,128), so we can use the @ABS8
231  /// symbol modifier.
233 
234  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
235  /// reference is actually to the ".refptr.FOO" symbol. This is used for
236  /// stub symbols on windows.
238  };
239 
240  enum : uint64_t {
241  //===------------------------------------------------------------------===//
242  // Instruction encodings. These are the standard/most common forms for X86
243  // instructions.
244  //
245 
246  // PseudoFrm - This represents an instruction that is a pseudo instruction
247  // or one that has not been implemented yet. It is illegal to code generate
248  // it, but tolerated for intermediate implementation stages.
249  Pseudo = 0,
250 
251  /// Raw - This form is for instructions that don't have any operands, so
252  /// they are just a fixed opcode value, like 'leave'.
253  RawFrm = 1,
254 
255  /// AddRegFrm - This form is used for instructions like 'push r32' that have
256  /// their one register operand added to their opcode.
258 
259  /// RawFrmMemOffs - This form is for instructions that store an absolute
260  /// memory offset as an immediate with a possible segment override.
262 
263  /// RawFrmSrc - This form is for instructions that use the source index
264  /// register SI/ESI/RSI with a possible segment override.
266 
267  /// RawFrmDst - This form is for instructions that use the destination index
268  /// register DI/EDI/RDI.
270 
271  /// RawFrmDstSrc - This form is for instructions that use the source index
272  /// register SI/ESI/RSI with a possible segment override, and also the
273  /// destination index register DI/EDI/RDI.
275 
276  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
277  /// immediates, the first of which is a 16-bit immediate (specified by
278  /// the imm encoding) and the second is a 8-bit fixed value.
280 
281  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
282  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
283  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
284  /// manual, this operand is described as pntr16:32 and pntr16:16
286 
287  /// MRM[0-7][rm] - These forms are used to represent instructions that use
288  /// a Mod/RM byte, and use the middle field to hold extended opcode
289  /// information. In the intel manual these are represented as /0, /1, ...
290  ///
291 
292  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
293  /// to specify a destination, which in this case is memory.
294  ///
296 
297  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
298  /// to specify a source, which in this case is memory.
299  ///
300  MRMSrcMem = 33,
301 
302  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
303  /// operand 3 with VEX.VVVV and load from memory.
304  ///
306 
307  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
308  /// byte to specify the fourth source, which in this case is memory.
309  ///
311 
312  /// MRMXm - This form is used for instructions that use the Mod/RM byte
313  /// to specify a memory source, but doesn't use the middle field.
314  ///
315  MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
316 
317  // Next, instructions that operate on a memory r/m operand...
318  MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
319  MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
320 
321  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
322  /// to specify a destination, which in this case is a register.
323  ///
325 
326  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
327  /// to specify a source, which in this case is a register.
328  ///
329  MRMSrcReg = 49,
330 
331  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
332  /// operand 3 with VEX.VVVV and do not load from memory.
333  ///
335 
336  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
337  /// byte to specify the fourth source, which in this case is a register.
338  ///
340 
341  /// MRMXr - This form is used for instructions that use the Mod/RM byte
342  /// to specify a register source, but doesn't use the middle field.
343  ///
344  MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
345 
346  // Instructions that operate on a register r/m operand...
347  MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
348  MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
349 
350  /// MRM_XX - A mod/rm byte of exactly 0xXX.
351  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
352  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
353  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
354  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
355  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
356  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
357  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
358  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
359  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
360  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
361  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
362  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
363  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
364  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
365  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
366  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
367 
368  FormMask = 127,
369 
370  //===------------------------------------------------------------------===//
371  // Actual flags...
372 
373  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
374  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
375  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
376  // prefix in 16-bit mode.
379 
383 
384  // AsSize - AdSizeX implies this instruction determines its need of 0x67
385  // prefix from a normal ModRM memory operand. The other types indicate that
386  // an operand is encoded with a specific width and a prefix is needed if
387  // it differs from the current mode.
390 
395 
396  //===------------------------------------------------------------------===//
397  // OpPrefix - There are several prefix bytes that are used as opcode
398  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
399  // no prefix.
400  //
403 
404  // PD - Prefix code for packed double precision vector floating point
405  // operations performed in the SSE registers.
407 
408  // XS, XD - These prefix codes are for single and double precision scalar
409  // floating point operations performed in the SSE registers.
411 
412  //===------------------------------------------------------------------===//
413  // OpMap - This field determines which opcode map this instruction
414  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
415  //
418 
419  // OB - OneByte - Set if this instruction has a one byte opcode.
420  OB = 0 << OpMapShift,
421 
422  // TB - TwoByte - Set if this instruction has a two byte opcode, which
423  // starts with a 0x0F byte before the real opcode.
424  TB = 1 << OpMapShift,
425 
426  // T8, TA - Prefix after the 0x0F prefix.
427  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
428 
429  // XOP8 - Prefix to include use of imm byte.
430  XOP8 = 4 << OpMapShift,
431 
432  // XOP9 - Prefix to exclude use of imm byte.
433  XOP9 = 5 << OpMapShift,
434 
435  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
436  XOPA = 6 << OpMapShift,
437 
438  /// ThreeDNow - This indicates that the instruction uses the
439  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
440  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
441  /// storing a classifier in the imm8 field. To simplify our implementation,
442  /// we handle this by storeing the classifier in the opcode field and using
443  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
445 
446  //===------------------------------------------------------------------===//
447  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
448  // They are used to specify GPRs and SSE registers, 64-bit operand size,
449  // etc. We only cares about REX.W and REX.R bits and only the former is
450  // statically determined.
451  //
453  REX_W = 1 << REXShift,
454 
455  //===------------------------------------------------------------------===//
456  // This three-bit field describes the size of an immediate operand. Zero is
457  // unused so that we can tell if we forgot to set a value.
459  ImmMask = 15 << ImmShift,
460  Imm8 = 1 << ImmShift,
463  Imm16 = 4 << ImmShift,
465  Imm32 = 6 << ImmShift,
467  Imm32S = 8 << ImmShift,
468  Imm64 = 9 << ImmShift,
469 
470  //===------------------------------------------------------------------===//
471  // FP Instruction Classification... Zero is non-fp instruction.
472 
473  // FPTypeMask - Mask for all of the FP types...
476 
477  // NotFP - The default, set for instructions that do not use FP registers.
479 
480  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
482 
483  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
485 
486  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
487  // result back to ST(0). For example, fcos, fsqrt, etc.
488  //
490 
491  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
492  // explicit argument, storing the result to either ST(0) or the implicit
493  // argument. For example: fadd, fsub, fmul, etc...
495 
496  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
497  // explicit argument, but have no destination. Example: fucom, fucomi, ...
499 
500  // CondMovFP - "2 operand" floating point conditional move instructions.
502 
503  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
505 
506  // Lock prefix
508  LOCK = 1 << LOCKShift,
509 
510  // REP prefix
512  REP = 1 << REPShift,
513 
514  // Execution domain for SSE instructions.
515  // 0 means normal, non-SSE instruction.
517 
518  // Encoding
521 
522  // VEX - encoding using 0xC4/0xC5
524 
525  /// XOP - Opcode prefix used by XOP instructions.
527 
528  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
529  // syntax support up to 32 512-bit register operands and up to 7 16-bit
530  // mask operands as well as source operand data swizzling/memory operand
531  // conversion, eviction hint, and rounding mode.
533 
534  // Opcode
536 
537  /// VEX_W - Has a opcode specific functionality, but is used in the same
538  /// way as REX_W is for regular SSE instructions.
540  VEX_W = 1ULL << VEX_WShift,
541 
542  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
543  /// address instructions in SSE are represented as 3 address ones in AVX
544  /// and the additional register is encoded in VEX_VVVV prefix.
545  VEX_4VShift = VEX_WShift + 1,
546  VEX_4V = 1ULL << VEX_4VShift,
547 
548  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
549  /// instruction uses 256-bit wide registers. This is usually auto detected
550  /// if a VR256 register is used, but some AVX instructions also have this
551  /// field marked when using a f256 memory references.
552  VEX_LShift = VEX_4VShift + 1,
553  VEX_L = 1ULL << VEX_LShift,
554 
555  // EVEX_K - Set if this instruction requires masking
556  EVEX_KShift = VEX_LShift + 1,
557  EVEX_K = 1ULL << EVEX_KShift,
558 
559  // EVEX_Z - Set if this instruction has EVEX.Z field set.
560  EVEX_ZShift = EVEX_KShift + 1,
561  EVEX_Z = 1ULL << EVEX_ZShift,
562 
563  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
564  EVEX_L2Shift = EVEX_ZShift + 1,
566 
567  // EVEX_B - Set if this instruction has EVEX.B field set.
568  EVEX_BShift = EVEX_L2Shift + 1,
569  EVEX_B = 1ULL << EVEX_BShift,
570 
571  // The scaling factor for the AVX512's 8-bit compressed displacement.
572  CD8_Scale_Shift = EVEX_BShift + 1,
574 
575  /// Explicitly specified rounding control
576  EVEX_RCShift = CD8_Scale_Shift + 7,
578 
579  // NOTRACK prefix
580  NoTrackShift = EVEX_RCShift + 1,
582  };
583 
584  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
585  // specified machine instruction.
586  //
587  inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
588  return TSFlags >> X86II::OpcodeShift;
589  }
590 
591  inline bool hasImm(uint64_t TSFlags) {
592  return (TSFlags & X86II::ImmMask) != 0;
593  }
594 
595  /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
596  /// of the specified instruction.
597  inline unsigned getSizeOfImm(uint64_t TSFlags) {
598  switch (TSFlags & X86II::ImmMask) {
599  default: llvm_unreachable("Unknown immediate size");
600  case X86II::Imm8:
601  case X86II::Imm8PCRel:
602  case X86II::Imm8Reg: return 1;
603  case X86II::Imm16:
604  case X86II::Imm16PCRel: return 2;
605  case X86II::Imm32:
606  case X86II::Imm32S:
607  case X86II::Imm32PCRel: return 4;
608  case X86II::Imm64: return 8;
609  }
610  }
611 
612  /// isImmPCRel - Return true if the immediate of the specified instruction's
613  /// TSFlags indicates that it is pc relative.
614  inline unsigned isImmPCRel(uint64_t TSFlags) {
615  switch (TSFlags & X86II::ImmMask) {
616  default: llvm_unreachable("Unknown immediate size");
617  case X86II::Imm8PCRel:
618  case X86II::Imm16PCRel:
619  case X86II::Imm32PCRel:
620  return true;
621  case X86II::Imm8:
622  case X86II::Imm8Reg:
623  case X86II::Imm16:
624  case X86II::Imm32:
625  case X86II::Imm32S:
626  case X86II::Imm64:
627  return false;
628  }
629  }
630 
631  /// isImmSigned - Return true if the immediate of the specified instruction's
632  /// TSFlags indicates that it is signed.
633  inline unsigned isImmSigned(uint64_t TSFlags) {
634  switch (TSFlags & X86II::ImmMask) {
635  default: llvm_unreachable("Unknown immediate signedness");
636  case X86II::Imm32S:
637  return true;
638  case X86II::Imm8:
639  case X86II::Imm8PCRel:
640  case X86II::Imm8Reg:
641  case X86II::Imm16:
642  case X86II::Imm16PCRel:
643  case X86II::Imm32:
644  case X86II::Imm32PCRel:
645  case X86II::Imm64:
646  return false;
647  }
648  }
649 
650  /// getOperandBias - compute whether all of the def operands are repeated
651  /// in the uses and therefore should be skipped.
652  /// This determines the start of the unique operand list. We need to determine
653  /// if all of the defs have a corresponding tied operand in the uses.
654  /// Unfortunately, the tied operand information is encoded in the uses not
655  /// the defs so we have to use some heuristics to find which operands to
656  /// query.
657  inline unsigned getOperandBias(const MCInstrDesc& Desc) {
658  unsigned NumDefs = Desc.getNumDefs();
659  unsigned NumOps = Desc.getNumOperands();
660  switch (NumDefs) {
661  default: llvm_unreachable("Unexpected number of defs");
662  case 0:
663  return 0;
664  case 1:
665  // Common two addr case.
666  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
667  return 1;
668  // Check for AVX-512 scatter which has a TIED_TO in the second to last
669  // operand.
670  if (NumOps == 8 &&
671  Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
672  return 1;
673  return 0;
674  case 2:
675  // XCHG/XADD have two destinations and two sources.
676  if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
677  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
678  return 2;
679  // Check for gather. AVX-512 has the second tied operand early. AVX2
680  // has it as the last op.
681  if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
682  (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
683  Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) &&
684  "Instruction with 2 defs isn't gather?")
685  return 2;
686  return 0;
687  }
688  }
689 
690  /// getMemoryOperandNo - The function returns the MCInst operand # for the
691  /// first field of the memory operand. If the instruction doesn't have a
692  /// memory operand, this returns -1.
693  ///
694  /// Note that this ignores tied operands. If there is a tied register which
695  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
696  /// counted as one operand.
697  ///
698  inline int getMemoryOperandNo(uint64_t TSFlags) {
699  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
700  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
701 
702  switch (TSFlags & X86II::FormMask) {
703  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
704  case X86II::Pseudo:
705  case X86II::RawFrm:
706  case X86II::AddRegFrm:
707  case X86II::RawFrmImm8:
708  case X86II::RawFrmImm16:
710  case X86II::RawFrmSrc:
711  case X86II::RawFrmDst:
712  case X86II::RawFrmDstSrc:
713  return -1;
714  case X86II::MRMDestMem:
715  return 0;
716  case X86II::MRMSrcMem:
717  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
718  // mask register.
719  return 1 + HasVEX_4V + HasEVEX_K;
721  // Skip registers encoded in reg.
722  return 1 + HasEVEX_K;
723  case X86II::MRMSrcMemOp4:
724  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
725  return 3;
726  case X86II::MRMDestReg:
727  case X86II::MRMSrcReg:
729  case X86II::MRMSrcRegOp4:
730  case X86II::MRMXr:
731  case X86II::MRM0r: case X86II::MRM1r:
732  case X86II::MRM2r: case X86II::MRM3r:
733  case X86II::MRM4r: case X86II::MRM5r:
734  case X86II::MRM6r: case X86II::MRM7r:
735  return -1;
736  case X86II::MRMXm:
737  case X86II::MRM0m: case X86II::MRM1m:
738  case X86II::MRM2m: case X86II::MRM3m:
739  case X86II::MRM4m: case X86II::MRM5m:
740  case X86II::MRM6m: case X86II::MRM7m:
741  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
742  return 0 + HasVEX_4V + HasEVEX_K;
743  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
744  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
745  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
746  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
747  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
748  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
749  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
750  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
751  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
752  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
753  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
754  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
755  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
756  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
757  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
758  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
759  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
760  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
761  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
762  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
763  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
764  case X86II::MRM_FF:
765  return -1;
766  }
767  }
768 
769  /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
770  /// higher) register? e.g. r8, xmm8, xmm13, etc.
771  inline bool isX86_64ExtendedReg(unsigned RegNo) {
772  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
773  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
774  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
775  return true;
776 
777  switch (RegNo) {
778  default: break;
779  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
780  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
781  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
782  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
783  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
784  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
785  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
786  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
787  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
788  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
789  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
790  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
791  return true;
792  }
793  return false;
794  }
795 
796  /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
797  /// registers? e.g. zmm21, etc.
798  static inline bool is32ExtendedReg(unsigned RegNo) {
799  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
800  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
801  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
802  }
803 
804 
805  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
806  return (reg == X86::SPL || reg == X86::BPL ||
807  reg == X86::SIL || reg == X86::DIL);
808  }
809 
810  /// isKMasked - Is this a masked instruction.
811  inline bool isKMasked(uint64_t TSFlags) {
812  return (TSFlags & X86II::EVEX_K) != 0;
813  }
814 
815  /// isKMergedMasked - Is this a merge masked instruction.
816  inline bool isKMergeMasked(uint64_t TSFlags) {
817  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
818  }
819 }
820 
821 } // end namespace llvm;
822 
823 #endif
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:227
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:339
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:237
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:805
Explicitly specified rounding control.
Definition: X86BaseInfo.h:576
#define REP(f, t)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:135
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:221
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:274
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:261
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:552
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:109
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:178
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:315
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:295
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:351
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI...
Definition: X86BaseInfo.h:269
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:614
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:209
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:310
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:444
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:329
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:324
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:539
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:587
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:94
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:153
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:232
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:591
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:204
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:305
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:771
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:257
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:82
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:55
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:194
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:215
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:145
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:186
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:657
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:633
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:279
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Windows x64, Windows Itanium (IA-64)
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:125
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:170
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:798
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:344
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:253
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:285
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
Definition: X86BaseInfo.h:816
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:300
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:101
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:334
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:162
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:545
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:597
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:73
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:46
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
Definition: X86BaseInfo.h:811
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:526
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:116
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:87
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:199
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:698
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:265