LLVM  9.0.0svn
X86BaseInfo.h
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1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the X86 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 
19 #include "X86MCTargetDesc.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/DataTypes.h"
23 
24 namespace llvm {
25 
26 namespace X86 {
27  // Enums for memory operand decoding. Each memory operand is represented with
28  // a 5 operand sequence in the form:
29  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30  // These enums help decode this.
31  enum {
35  AddrDisp = 3,
36 
37  /// AddrSegmentReg - The operand # of the segment in the memory operand.
39 
40  /// AddrNumOperands - Total number of operands in a memory reference.
42  };
43 
44  /// AVX512 static rounding constants. These need to match the values in
45  /// avx512fintrin.h.
50  TO_ZERO = 3,
52  NO_EXC = 8
53  };
54 
55  /// The constants to describe instr prefixes if there are
56  enum IPREFIXES {
64  };
65 } // end namespace X86;
66 
67 /// X86II - This namespace holds all of the target specific flags that
68 /// instruction info tracks.
69 ///
70 namespace X86II {
71  /// Target Operand Flag enum.
72  enum TOF {
73  //===------------------------------------------------------------------===//
74  // X86 Specific MachineOperand flags.
75 
77 
78  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
79  /// relocation of:
80  /// SYMBOL_LABEL + [. - PICBASELABEL]
82 
83  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
84  /// immediate should get the value of the symbol minus the PIC base label:
85  /// SYMBOL_LABEL - PICBASELABEL
87 
88  /// MO_GOT - On a symbol operand this indicates that the immediate is the
89  /// offset to the GOT entry for the symbol name from the base of the GOT.
90  ///
91  /// See the X86-64 ELF ABI supplement for more details.
92  /// SYMBOL_LABEL @GOT
94 
95  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
96  /// the offset to the location of the symbol name from the base of the GOT.
97  ///
98  /// See the X86-64 ELF ABI supplement for more details.
99  /// SYMBOL_LABEL @GOTOFF
101 
102  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
103  /// offset to the GOT entry for the symbol name from the current code
104  /// location.
105  ///
106  /// See the X86-64 ELF ABI supplement for more details.
107  /// SYMBOL_LABEL @GOTPCREL
109 
110  /// MO_PLT - On a symbol operand this indicates that the immediate is
111  /// offset to the PLT entry of symbol name from the current code location.
112  ///
113  /// See the X86-64 ELF ABI supplement for more details.
114  /// SYMBOL_LABEL @PLT
116 
117  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
118  /// the offset of the GOT entry with the TLS index structure that contains
119  /// the module number and variable offset for the symbol. Used in the
120  /// general dynamic TLS access model.
121  ///
122  /// See 'ELF Handling for Thread-Local Storage' for more details.
123  /// SYMBOL_LABEL @TLSGD
125 
126  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
127  /// the offset of the GOT entry with the TLS index for the module that
128  /// contains the symbol. When this index is passed to a call to
129  /// __tls_get_addr, the function will return the base address of the TLS
130  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
131  ///
132  /// See 'ELF Handling for Thread-Local Storage' for more details.
133  /// SYMBOL_LABEL @TLSLD
135 
136  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
137  /// the offset of the GOT entry with the TLS index for the module that
138  /// contains the symbol. When this index is passed to a call to
139  /// ___tls_get_addr, the function will return the base address of the TLS
140  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
141  ///
142  /// See 'ELF Handling for Thread-Local Storage' for more details.
143  /// SYMBOL_LABEL @TLSLDM
145 
146  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
147  /// the offset of the GOT entry with the thread-pointer offset for the
148  /// symbol. Used in the x86-64 initial exec TLS access model.
149  ///
150  /// See 'ELF Handling for Thread-Local Storage' for more details.
151  /// SYMBOL_LABEL @GOTTPOFF
153 
154  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
155  /// the absolute address of the GOT entry with the negative thread-pointer
156  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
157  /// model.
158  ///
159  /// See 'ELF Handling for Thread-Local Storage' for more details.
160  /// SYMBOL_LABEL @INDNTPOFF
162 
163  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
164  /// the thread-pointer offset for the symbol. Used in the x86-64 local
165  /// exec TLS access model.
166  ///
167  /// See 'ELF Handling for Thread-Local Storage' for more details.
168  /// SYMBOL_LABEL @TPOFF
170 
171  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
172  /// the offset of the GOT entry with the TLS offset of the symbol. Used
173  /// in the local dynamic TLS access model.
174  ///
175  /// See 'ELF Handling for Thread-Local Storage' for more details.
176  /// SYMBOL_LABEL @DTPOFF
178 
179  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
180  /// the negative thread-pointer offset for the symbol. Used in the IA32
181  /// local exec TLS access model.
182  ///
183  /// See 'ELF Handling for Thread-Local Storage' for more details.
184  /// SYMBOL_LABEL @NTPOFF
186 
187  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
188  /// the offset of the GOT entry with the negative thread-pointer offset for
189  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
190  ///
191  /// See 'ELF Handling for Thread-Local Storage' for more details.
192  /// SYMBOL_LABEL @GOTNTPOFF
194 
195  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
196  /// reference is actually to the "__imp_FOO" symbol. This is used for
197  /// dllimport linkage on windows.
199 
200  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
201  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
202  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
204 
205  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
206  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
207  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
209 
210  /// MO_TLVP - On a symbol operand this indicates that the immediate is
211  /// some TLS offset.
212  ///
213  /// This is the TLS offset for the Darwin TLS mechanism.
215 
216  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
217  /// is some TLS offset from the picbase.
218  ///
219  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
221 
222  /// MO_SECREL - On a symbol operand this indicates that the immediate is
223  /// the offset from beginning of section.
224  ///
225  /// This is the TLS offset for the COFF/Windows TLS mechanism.
227 
228  /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
229  /// to be an absolute symbol in range [0,128), so we can use the @ABS8
230  /// symbol modifier.
232 
233  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
234  /// reference is actually to the ".refptr.FOO" symbol. This is used for
235  /// stub symbols on windows.
237  };
238 
239  enum : uint64_t {
240  //===------------------------------------------------------------------===//
241  // Instruction encodings. These are the standard/most common forms for X86
242  // instructions.
243  //
244 
245  // PseudoFrm - This represents an instruction that is a pseudo instruction
246  // or one that has not been implemented yet. It is illegal to code generate
247  // it, but tolerated for intermediate implementation stages.
248  Pseudo = 0,
249 
250  /// Raw - This form is for instructions that don't have any operands, so
251  /// they are just a fixed opcode value, like 'leave'.
252  RawFrm = 1,
253 
254  /// AddRegFrm - This form is used for instructions like 'push r32' that have
255  /// their one register operand added to their opcode.
257 
258  /// RawFrmMemOffs - This form is for instructions that store an absolute
259  /// memory offset as an immediate with a possible segment override.
261 
262  /// RawFrmSrc - This form is for instructions that use the source index
263  /// register SI/ESI/RSI with a possible segment override.
265 
266  /// RawFrmDst - This form is for instructions that use the destination index
267  /// register DI/EDI/RDI.
269 
270  /// RawFrmDstSrc - This form is for instructions that use the source index
271  /// register SI/ESI/RSI with a possible segment override, and also the
272  /// destination index register DI/EDI/RDI.
274 
275  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
276  /// immediates, the first of which is a 16-bit immediate (specified by
277  /// the imm encoding) and the second is a 8-bit fixed value.
279 
280  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
281  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
282  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
283  /// manual, this operand is described as pntr16:32 and pntr16:16
285 
286  /// MRM[0-7][rm] - These forms are used to represent instructions that use
287  /// a Mod/RM byte, and use the middle field to hold extended opcode
288  /// information. In the intel manual these are represented as /0, /1, ...
289  ///
290 
291  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
292  /// to specify a destination, which in this case is memory.
293  ///
295 
296  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
297  /// to specify a source, which in this case is memory.
298  ///
299  MRMSrcMem = 33,
300 
301  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
302  /// operand 3 with VEX.VVVV and load from memory.
303  ///
305 
306  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
307  /// byte to specify the fourth source, which in this case is memory.
308  ///
310 
311  /// MRMXm - This form is used for instructions that use the Mod/RM byte
312  /// to specify a memory source, but doesn't use the middle field.
313  ///
314  MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
315 
316  // Next, instructions that operate on a memory r/m operand...
317  MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
318  MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
319 
320  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
321  /// to specify a destination, which in this case is a register.
322  ///
324 
325  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
326  /// to specify a source, which in this case is a register.
327  ///
328  MRMSrcReg = 49,
329 
330  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
331  /// operand 3 with VEX.VVVV and do not load from memory.
332  ///
334 
335  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
336  /// byte to specify the fourth source, which in this case is a register.
337  ///
339 
340  /// MRMXr - This form is used for instructions that use the Mod/RM byte
341  /// to specify a register source, but doesn't use the middle field.
342  ///
343  MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
344 
345  // Instructions that operate on a register r/m operand...
346  MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
347  MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
348 
349  /// MRM_XX - A mod/rm byte of exactly 0xXX.
350  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
351  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
352  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
353  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
354  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
355  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
356  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
357  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
358  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
359  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
360  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
361  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
362  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
363  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
364  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
365  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
366 
367  FormMask = 127,
368 
369  //===------------------------------------------------------------------===//
370  // Actual flags...
371 
372  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
373  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
374  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
375  // prefix in 16-bit mode.
378 
382 
383  // AsSize - AdSizeX implies this instruction determines its need of 0x67
384  // prefix from a normal ModRM memory operand. The other types indicate that
385  // an operand is encoded with a specific width and a prefix is needed if
386  // it differs from the current mode.
389 
394 
395  //===------------------------------------------------------------------===//
396  // OpPrefix - There are several prefix bytes that are used as opcode
397  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
398  // no prefix.
399  //
402 
403  // PD - Prefix code for packed double precision vector floating point
404  // operations performed in the SSE registers.
406 
407  // XS, XD - These prefix codes are for single and double precision scalar
408  // floating point operations performed in the SSE registers.
410 
411  //===------------------------------------------------------------------===//
412  // OpMap - This field determines which opcode map this instruction
413  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
414  //
417 
418  // OB - OneByte - Set if this instruction has a one byte opcode.
419  OB = 0 << OpMapShift,
420 
421  // TB - TwoByte - Set if this instruction has a two byte opcode, which
422  // starts with a 0x0F byte before the real opcode.
423  TB = 1 << OpMapShift,
424 
425  // T8, TA - Prefix after the 0x0F prefix.
426  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
427 
428  // XOP8 - Prefix to include use of imm byte.
429  XOP8 = 4 << OpMapShift,
430 
431  // XOP9 - Prefix to exclude use of imm byte.
432  XOP9 = 5 << OpMapShift,
433 
434  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
435  XOPA = 6 << OpMapShift,
436 
437  /// ThreeDNow - This indicates that the instruction uses the
438  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
439  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
440  /// storing a classifier in the imm8 field. To simplify our implementation,
441  /// we handle this by storeing the classifier in the opcode field and using
442  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
444 
445  //===------------------------------------------------------------------===//
446  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
447  // They are used to specify GPRs and SSE registers, 64-bit operand size,
448  // etc. We only cares about REX.W and REX.R bits and only the former is
449  // statically determined.
450  //
452  REX_W = 1 << REXShift,
453 
454  //===------------------------------------------------------------------===//
455  // This three-bit field describes the size of an immediate operand. Zero is
456  // unused so that we can tell if we forgot to set a value.
458  ImmMask = 15 << ImmShift,
459  Imm8 = 1 << ImmShift,
462  Imm16 = 4 << ImmShift,
464  Imm32 = 6 << ImmShift,
466  Imm32S = 8 << ImmShift,
467  Imm64 = 9 << ImmShift,
468 
469  //===------------------------------------------------------------------===//
470  // FP Instruction Classification... Zero is non-fp instruction.
471 
472  // FPTypeMask - Mask for all of the FP types...
475 
476  // NotFP - The default, set for instructions that do not use FP registers.
478 
479  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
481 
482  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
484 
485  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
486  // result back to ST(0). For example, fcos, fsqrt, etc.
487  //
489 
490  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
491  // explicit argument, storing the result to either ST(0) or the implicit
492  // argument. For example: fadd, fsub, fmul, etc...
494 
495  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
496  // explicit argument, but have no destination. Example: fucom, fucomi, ...
498 
499  // CondMovFP - "2 operand" floating point conditional move instructions.
501 
502  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
504 
505  // Lock prefix
507  LOCK = 1 << LOCKShift,
508 
509  // REP prefix
511  REP = 1 << REPShift,
512 
513  // Execution domain for SSE instructions.
514  // 0 means normal, non-SSE instruction.
516 
517  // Encoding
520 
521  // VEX - encoding using 0xC4/0xC5
523 
524  /// XOP - Opcode prefix used by XOP instructions.
526 
527  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
528  // syntax support up to 32 512-bit register operands and up to 7 16-bit
529  // mask operands as well as source operand data swizzling/memory operand
530  // conversion, eviction hint, and rounding mode.
532 
533  // Opcode
535 
536  /// VEX_W - Has a opcode specific functionality, but is used in the same
537  /// way as REX_W is for regular SSE instructions.
539  VEX_W = 1ULL << VEX_WShift,
540 
541  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
542  /// address instructions in SSE are represented as 3 address ones in AVX
543  /// and the additional register is encoded in VEX_VVVV prefix.
544  VEX_4VShift = VEX_WShift + 1,
545  VEX_4V = 1ULL << VEX_4VShift,
546 
547  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
548  /// instruction uses 256-bit wide registers. This is usually auto detected
549  /// if a VR256 register is used, but some AVX instructions also have this
550  /// field marked when using a f256 memory references.
551  VEX_LShift = VEX_4VShift + 1,
552  VEX_L = 1ULL << VEX_LShift,
553 
554  // EVEX_K - Set if this instruction requires masking
555  EVEX_KShift = VEX_LShift + 1,
556  EVEX_K = 1ULL << EVEX_KShift,
557 
558  // EVEX_Z - Set if this instruction has EVEX.Z field set.
559  EVEX_ZShift = EVEX_KShift + 1,
560  EVEX_Z = 1ULL << EVEX_ZShift,
561 
562  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
563  EVEX_L2Shift = EVEX_ZShift + 1,
565 
566  // EVEX_B - Set if this instruction has EVEX.B field set.
567  EVEX_BShift = EVEX_L2Shift + 1,
568  EVEX_B = 1ULL << EVEX_BShift,
569 
570  // The scaling factor for the AVX512's 8-bit compressed displacement.
571  CD8_Scale_Shift = EVEX_BShift + 1,
573 
574  /// Explicitly specified rounding control
575  EVEX_RCShift = CD8_Scale_Shift + 7,
577 
578  // NOTRACK prefix
579  NoTrackShift = EVEX_RCShift + 1,
581  };
582 
583  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
584  // specified machine instruction.
585  //
586  inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
587  return TSFlags >> X86II::OpcodeShift;
588  }
589 
590  inline bool hasImm(uint64_t TSFlags) {
591  return (TSFlags & X86II::ImmMask) != 0;
592  }
593 
594  /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
595  /// of the specified instruction.
596  inline unsigned getSizeOfImm(uint64_t TSFlags) {
597  switch (TSFlags & X86II::ImmMask) {
598  default: llvm_unreachable("Unknown immediate size");
599  case X86II::Imm8:
600  case X86II::Imm8PCRel:
601  case X86II::Imm8Reg: return 1;
602  case X86II::Imm16:
603  case X86II::Imm16PCRel: return 2;
604  case X86II::Imm32:
605  case X86II::Imm32S:
606  case X86II::Imm32PCRel: return 4;
607  case X86II::Imm64: return 8;
608  }
609  }
610 
611  /// isImmPCRel - Return true if the immediate of the specified instruction's
612  /// TSFlags indicates that it is pc relative.
613  inline unsigned isImmPCRel(uint64_t TSFlags) {
614  switch (TSFlags & X86II::ImmMask) {
615  default: llvm_unreachable("Unknown immediate size");
616  case X86II::Imm8PCRel:
617  case X86II::Imm16PCRel:
618  case X86II::Imm32PCRel:
619  return true;
620  case X86II::Imm8:
621  case X86II::Imm8Reg:
622  case X86II::Imm16:
623  case X86II::Imm32:
624  case X86II::Imm32S:
625  case X86II::Imm64:
626  return false;
627  }
628  }
629 
630  /// isImmSigned - Return true if the immediate of the specified instruction's
631  /// TSFlags indicates that it is signed.
632  inline unsigned isImmSigned(uint64_t TSFlags) {
633  switch (TSFlags & X86II::ImmMask) {
634  default: llvm_unreachable("Unknown immediate signedness");
635  case X86II::Imm32S:
636  return true;
637  case X86II::Imm8:
638  case X86II::Imm8PCRel:
639  case X86II::Imm8Reg:
640  case X86II::Imm16:
641  case X86II::Imm16PCRel:
642  case X86II::Imm32:
643  case X86II::Imm32PCRel:
644  case X86II::Imm64:
645  return false;
646  }
647  }
648 
649  /// getOperandBias - compute whether all of the def operands are repeated
650  /// in the uses and therefore should be skipped.
651  /// This determines the start of the unique operand list. We need to determine
652  /// if all of the defs have a corresponding tied operand in the uses.
653  /// Unfortunately, the tied operand information is encoded in the uses not
654  /// the defs so we have to use some heuristics to find which operands to
655  /// query.
656  inline unsigned getOperandBias(const MCInstrDesc& Desc) {
657  unsigned NumDefs = Desc.getNumDefs();
658  unsigned NumOps = Desc.getNumOperands();
659  switch (NumDefs) {
660  default: llvm_unreachable("Unexpected number of defs");
661  case 0:
662  return 0;
663  case 1:
664  // Common two addr case.
665  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
666  return 1;
667  // Check for AVX-512 scatter which has a TIED_TO in the second to last
668  // operand.
669  if (NumOps == 8 &&
670  Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
671  return 1;
672  return 0;
673  case 2:
674  // XCHG/XADD have two destinations and two sources.
675  if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
676  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
677  return 2;
678  // Check for gather. AVX-512 has the second tied operand early. AVX2
679  // has it as the last op.
680  if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
681  (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
682  Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) &&
683  "Instruction with 2 defs isn't gather?")
684  return 2;
685  return 0;
686  }
687  }
688 
689  /// getMemoryOperandNo - The function returns the MCInst operand # for the
690  /// first field of the memory operand. If the instruction doesn't have a
691  /// memory operand, this returns -1.
692  ///
693  /// Note that this ignores tied operands. If there is a tied register which
694  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
695  /// counted as one operand.
696  ///
697  inline int getMemoryOperandNo(uint64_t TSFlags) {
698  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
699  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
700 
701  switch (TSFlags & X86II::FormMask) {
702  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
703  case X86II::Pseudo:
704  case X86II::RawFrm:
705  case X86II::AddRegFrm:
706  case X86II::RawFrmImm8:
707  case X86II::RawFrmImm16:
709  case X86II::RawFrmSrc:
710  case X86II::RawFrmDst:
711  case X86II::RawFrmDstSrc:
712  return -1;
713  case X86II::MRMDestMem:
714  return 0;
715  case X86II::MRMSrcMem:
716  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
717  // mask register.
718  return 1 + HasVEX_4V + HasEVEX_K;
720  // Skip registers encoded in reg.
721  return 1 + HasEVEX_K;
722  case X86II::MRMSrcMemOp4:
723  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
724  return 3;
725  case X86II::MRMDestReg:
726  case X86II::MRMSrcReg:
728  case X86II::MRMSrcRegOp4:
729  case X86II::MRMXr:
730  case X86II::MRM0r: case X86II::MRM1r:
731  case X86II::MRM2r: case X86II::MRM3r:
732  case X86II::MRM4r: case X86II::MRM5r:
733  case X86II::MRM6r: case X86II::MRM7r:
734  return -1;
735  case X86II::MRMXm:
736  case X86II::MRM0m: case X86II::MRM1m:
737  case X86II::MRM2m: case X86II::MRM3m:
738  case X86II::MRM4m: case X86II::MRM5m:
739  case X86II::MRM6m: case X86II::MRM7m:
740  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
741  return 0 + HasVEX_4V + HasEVEX_K;
742  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
743  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
744  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
745  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
746  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
747  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
748  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
749  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
750  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
751  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
752  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
753  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
754  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
755  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
756  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
757  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
758  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
759  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
760  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
761  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
762  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
763  case X86II::MRM_FF:
764  return -1;
765  }
766  }
767 
768  /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
769  /// higher) register? e.g. r8, xmm8, xmm13, etc.
770  inline bool isX86_64ExtendedReg(unsigned RegNo) {
771  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
772  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
773  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
774  return true;
775 
776  switch (RegNo) {
777  default: break;
778  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
779  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
780  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
781  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
782  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
783  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
784  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
785  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
786  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
787  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
788  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
789  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
790  return true;
791  }
792  return false;
793  }
794 
795  /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
796  /// registers? e.g. zmm21, etc.
797  static inline bool is32ExtendedReg(unsigned RegNo) {
798  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
799  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
800  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
801  }
802 
803 
804  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
805  return (reg == X86::SPL || reg == X86::BPL ||
806  reg == X86::SIL || reg == X86::DIL);
807  }
808 
809  /// isKMasked - Is this a masked instruction.
810  inline bool isKMasked(uint64_t TSFlags) {
811  return (TSFlags & X86II::EVEX_K) != 0;
812  }
813 
814  /// isKMergedMasked - Is this a merge masked instruction.
815  inline bool isKMergeMasked(uint64_t TSFlags) {
816  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
817  }
818 }
819 
820 } // end namespace llvm;
821 
822 #endif
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:226
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:252
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:236
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:804
#define REP(f, t)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:134
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:220
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:108
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:177
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:613
ThreeDNow - This indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DNow! instructio...
Definition: X86BaseInfo.h:443
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:208
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:333
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:343
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:304
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:299
uint8_t getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:586
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:93
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:152
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:231
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:590
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:203
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:328
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:770
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:350
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:81
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:56
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:193
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:214
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:525
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:256
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:144
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:538
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/RDI...
Definition: X86BaseInfo.h:268
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:185
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:656
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:260
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:632
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:544
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Windows x64, Windows Itanium (IA-64)
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:124
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:169
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:797
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
Definition: X86BaseInfo.h:273
Explicitly specified rounding control.
Definition: X86BaseInfo.h:575
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
Definition: X86BaseInfo.h:815
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:100
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:338
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:161
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:278
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:596
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:72
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:46
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
Definition: X86BaseInfo.h:810
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:323
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:115
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:264
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:86
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:314
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:551
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:294
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:284
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:309
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:198
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:697