LLVM  6.0.0svn
X86BaseInfo.h
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1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
19 
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/DataTypes.h"
24 
25 namespace llvm {
26 
27 namespace X86 {
28  // Enums for memory operand decoding. Each memory operand is represented with
29  // a 5 operand sequence in the form:
30  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31  // These enums help decode this.
32  enum {
36  AddrDisp = 3,
37 
38  /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 
41  /// AddrNumOperands - Total number of operands in a memory reference.
43  };
44 
45  /// AVX512 static rounding constants. These need to match the values in
46  /// avx512fintrin.h.
51  TO_ZERO = 3,
53  };
54 
55  /// The constants to describe instr prefixes if there are
56  enum IPREFIXES {
63  NO_SCHED_INFO = 32 // Don't add sched comment to the current instr because
64  // it was already added
65  };
66 } // end namespace X86;
67 
68 /// X86II - This namespace holds all of the target specific flags that
69 /// instruction info tracks.
70 ///
71 namespace X86II {
72  /// Target Operand Flag enum.
73  enum TOF {
74  //===------------------------------------------------------------------===//
75  // X86 Specific MachineOperand flags.
76 
78 
79  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80  /// relocation of:
81  /// SYMBOL_LABEL + [. - PICBASELABEL]
83 
84  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
85  /// immediate should get the value of the symbol minus the PIC base label:
86  /// SYMBOL_LABEL - PICBASELABEL
88 
89  /// MO_GOT - On a symbol operand this indicates that the immediate is the
90  /// offset to the GOT entry for the symbol name from the base of the GOT.
91  ///
92  /// See the X86-64 ELF ABI supplement for more details.
93  /// SYMBOL_LABEL @GOT
95 
96  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
97  /// the offset to the location of the symbol name from the base of the GOT.
98  ///
99  /// See the X86-64 ELF ABI supplement for more details.
100  /// SYMBOL_LABEL @GOTOFF
102 
103  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
104  /// offset to the GOT entry for the symbol name from the current code
105  /// location.
106  ///
107  /// See the X86-64 ELF ABI supplement for more details.
108  /// SYMBOL_LABEL @GOTPCREL
110 
111  /// MO_PLT - On a symbol operand this indicates that the immediate is
112  /// offset to the PLT entry of symbol name from the current code location.
113  ///
114  /// See the X86-64 ELF ABI supplement for more details.
115  /// SYMBOL_LABEL @PLT
117 
118  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
119  /// the offset of the GOT entry with the TLS index structure that contains
120  /// the module number and variable offset for the symbol. Used in the
121  /// general dynamic TLS access model.
122  ///
123  /// See 'ELF Handling for Thread-Local Storage' for more details.
124  /// SYMBOL_LABEL @TLSGD
126 
127  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
128  /// the offset of the GOT entry with the TLS index for the module that
129  /// contains the symbol. When this index is passed to a call to
130  /// __tls_get_addr, the function will return the base address of the TLS
131  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
132  ///
133  /// See 'ELF Handling for Thread-Local Storage' for more details.
134  /// SYMBOL_LABEL @TLSLD
136 
137  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
138  /// the offset of the GOT entry with the TLS index for the module that
139  /// contains the symbol. When this index is passed to a call to
140  /// ___tls_get_addr, the function will return the base address of the TLS
141  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
142  ///
143  /// See 'ELF Handling for Thread-Local Storage' for more details.
144  /// SYMBOL_LABEL @TLSLDM
146 
147  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
148  /// the offset of the GOT entry with the thread-pointer offset for the
149  /// symbol. Used in the x86-64 initial exec TLS access model.
150  ///
151  /// See 'ELF Handling for Thread-Local Storage' for more details.
152  /// SYMBOL_LABEL @GOTTPOFF
154 
155  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
156  /// the absolute address of the GOT entry with the negative thread-pointer
157  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
158  /// model.
159  ///
160  /// See 'ELF Handling for Thread-Local Storage' for more details.
161  /// SYMBOL_LABEL @INDNTPOFF
163 
164  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
165  /// the thread-pointer offset for the symbol. Used in the x86-64 local
166  /// exec TLS access model.
167  ///
168  /// See 'ELF Handling for Thread-Local Storage' for more details.
169  /// SYMBOL_LABEL @TPOFF
171 
172  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
173  /// the offset of the GOT entry with the TLS offset of the symbol. Used
174  /// in the local dynamic TLS access model.
175  ///
176  /// See 'ELF Handling for Thread-Local Storage' for more details.
177  /// SYMBOL_LABEL @DTPOFF
179 
180  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
181  /// the negative thread-pointer offset for the symbol. Used in the IA32
182  /// local exec TLS access model.
183  ///
184  /// See 'ELF Handling for Thread-Local Storage' for more details.
185  /// SYMBOL_LABEL @NTPOFF
187 
188  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
189  /// the offset of the GOT entry with the negative thread-pointer offset for
190  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
191  ///
192  /// See 'ELF Handling for Thread-Local Storage' for more details.
193  /// SYMBOL_LABEL @GOTNTPOFF
195 
196  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
197  /// reference is actually to the "__imp_FOO" symbol. This is used for
198  /// dllimport linkage on windows.
200 
201  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
202  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
203  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
205 
206  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
207  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
208  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
210 
211  /// MO_TLVP - On a symbol operand this indicates that the immediate is
212  /// some TLS offset.
213  ///
214  /// This is the TLS offset for the Darwin TLS mechanism.
216 
217  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
218  /// is some TLS offset from the picbase.
219  ///
220  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
222 
223  /// MO_SECREL - On a symbol operand this indicates that the immediate is
224  /// the offset from beginning of section.
225  ///
226  /// This is the TLS offset for the COFF/Windows TLS mechanism.
228 
229  /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
230  /// to be an absolute symbol in range [0,128), so we can use the @ABS8
231  /// symbol modifier.
233  };
234 
235  enum : uint64_t {
236  //===------------------------------------------------------------------===//
237  // Instruction encodings. These are the standard/most common forms for X86
238  // instructions.
239  //
240 
241  // PseudoFrm - This represents an instruction that is a pseudo instruction
242  // or one that has not been implemented yet. It is illegal to code generate
243  // it, but tolerated for intermediate implementation stages.
244  Pseudo = 0,
245 
246  /// Raw - This form is for instructions that don't have any operands, so
247  /// they are just a fixed opcode value, like 'leave'.
248  RawFrm = 1,
249 
250  /// AddRegFrm - This form is used for instructions like 'push r32' that have
251  /// their one register operand added to their opcode.
253 
254  /// RawFrmMemOffs - This form is for instructions that store an absolute
255  /// memory offset as an immediate with a possible segment override.
257 
258  /// RawFrmSrc - This form is for instructions that use the source index
259  /// register SI/ESI/RSI with a possible segment override.
261 
262  /// RawFrmDst - This form is for instructions that use the destination index
263  /// register DI/EDI/ESI.
265 
266  /// RawFrmSrc - This form is for instructions that use the source index
267  /// register SI/ESI/ERI with a possible segment override, and also the
268  /// destination index register DI/ESI/RDI.
270 
271  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
272  /// immediates, the first of which is a 16-bit immediate (specified by
273  /// the imm encoding) and the second is a 8-bit fixed value.
275 
276  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
277  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
278  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
279  /// manual, this operand is described as pntr16:32 and pntr16:16
281 
282  /// MRM[0-7][rm] - These forms are used to represent instructions that use
283  /// a Mod/RM byte, and use the middle field to hold extended opcode
284  /// information. In the intel manual these are represented as /0, /1, ...
285  ///
286 
287  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
288  /// to specify a destination, which in this case is memory.
289  ///
291 
292  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
293  /// to specify a source, which in this case is memory.
294  ///
295  MRMSrcMem = 33,
296 
297  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
298  /// operand 3 with VEX.VVVV and load from memory.
299  ///
301 
302  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
303  /// byte to specify the fourth source, which in this case is memory.
304  ///
306 
307  /// MRMXm - This form is used for instructions that use the Mod/RM byte
308  /// to specify a memory source, but doesn't use the middle field.
309  ///
310  MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
311 
312  // Next, instructions that operate on a memory r/m operand...
313  MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
314  MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
315 
316  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
317  /// to specify a destination, which in this case is a register.
318  ///
320 
321  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
322  /// to specify a source, which in this case is a register.
323  ///
324  MRMSrcReg = 49,
325 
326  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
327  /// operand 3 with VEX.VVVV and do not load from memory.
328  ///
330 
331  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
332  /// byte to specify the fourth source, which in this case is a register.
333  ///
335 
336  /// MRMXr - This form is used for instructions that use the Mod/RM byte
337  /// to specify a register source, but doesn't use the middle field.
338  ///
339  MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
340 
341  // Instructions that operate on a register r/m operand...
342  MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
343  MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
344 
345  /// MRM_XX - A mod/rm byte of exactly 0xXX.
346  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
347  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
348  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
349  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
350  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
351  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
352  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
353  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
354  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
355  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
356  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
357  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
358  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
359  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
360  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
361  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
362 
363  FormMask = 127,
364 
365  //===------------------------------------------------------------------===//
366  // Actual flags...
367 
368  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
369  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
370  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
371  // prefix in 16-bit mode. OpSizeIgnore means that the instruction may
372  // take a optional 0x66 byte but should not emit with one.
375 
380 
381  // AsSize - AdSizeX implies this instruction determines its need of 0x67
382  // prefix from a normal ModRM memory operand. The other types indicate that
383  // an operand is encoded with a specific width and a prefix is needed if
384  // it differs from the current mode.
387 
392 
393  //===------------------------------------------------------------------===//
394  // OpPrefix - There are several prefix bytes that are used as opcode
395  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
396  // no prefix.
397  //
400 
401  // PS, PD - Prefix code for packed single and double precision vector
402  // floating point operations performed in the SSE registers.
404 
405  // XS, XD - These prefix codes are for single and double precision scalar
406  // floating point operations performed in the SSE registers.
408 
409  //===------------------------------------------------------------------===//
410  // OpMap - This field determines which opcode map this instruction
411  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
412  //
415 
416  // OB - OneByte - Set if this instruction has a one byte opcode.
417  OB = 0 << OpMapShift,
418 
419  // TB - TwoByte - Set if this instruction has a two byte opcode, which
420  // starts with a 0x0F byte before the real opcode.
421  TB = 1 << OpMapShift,
422 
423  // T8, TA - Prefix after the 0x0F prefix.
424  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
425 
426  // XOP8 - Prefix to include use of imm byte.
427  XOP8 = 4 << OpMapShift,
428 
429  // XOP9 - Prefix to exclude use of imm byte.
430  XOP9 = 5 << OpMapShift,
431 
432  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
433  XOPA = 6 << OpMapShift,
434 
435  //===------------------------------------------------------------------===//
436  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
437  // They are used to specify GPRs and SSE registers, 64-bit operand size,
438  // etc. We only cares about REX.W and REX.R bits and only the former is
439  // statically determined.
440  //
442  REX_W = 1 << REXShift,
443 
444  //===------------------------------------------------------------------===//
445  // This three-bit field describes the size of an immediate operand. Zero is
446  // unused so that we can tell if we forgot to set a value.
448  ImmMask = 15 << ImmShift,
449  Imm8 = 1 << ImmShift,
452  Imm16 = 4 << ImmShift,
454  Imm32 = 6 << ImmShift,
456  Imm32S = 8 << ImmShift,
457  Imm64 = 9 << ImmShift,
458 
459  //===------------------------------------------------------------------===//
460  // FP Instruction Classification... Zero is non-fp instruction.
461 
462  // FPTypeMask - Mask for all of the FP types...
465 
466  // NotFP - The default, set for instructions that do not use FP registers.
468 
469  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
471 
472  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
474 
475  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
476  // result back to ST(0). For example, fcos, fsqrt, etc.
477  //
479 
480  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
481  // explicit argument, storing the result to either ST(0) or the implicit
482  // argument. For example: fadd, fsub, fmul, etc...
484 
485  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
486  // explicit argument, but have no destination. Example: fucom, fucomi, ...
488 
489  // CondMovFP - "2 operand" floating point conditional move instructions.
491 
492  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
494 
495  // Lock prefix
497  LOCK = 1 << LOCKShift,
498 
499  // REP prefix
501  REP = 1 << REPShift,
502 
503  // Execution domain for SSE instructions.
504  // 0 means normal, non-SSE instruction.
506 
507  // Encoding
510 
511  // VEX - encoding using 0xC4/0xC5
513 
514  /// XOP - Opcode prefix used by XOP instructions.
516 
517  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
518  // syntax support up to 32 512-bit register operands and up to 7 16-bit
519  // mask operands as well as source operand data swizzling/memory operand
520  // conversion, eviction hint, and rounding mode.
522 
523  // Opcode
525 
526  /// VEX_W - Has a opcode specific functionality, but is used in the same
527  /// way as REX_W is for regular SSE instructions.
529  VEX_W = 1ULL << VEX_WShift,
530 
531  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
532  /// address instructions in SSE are represented as 3 address ones in AVX
533  /// and the additional register is encoded in VEX_VVVV prefix.
534  VEX_4VShift = VEX_WShift + 1,
535  VEX_4V = 1ULL << VEX_4VShift,
536 
537  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
538  /// instruction uses 256-bit wide registers. This is usually auto detected
539  /// if a VR256 register is used, but some AVX instructions also have this
540  /// field marked when using a f256 memory references.
541  VEX_LShift = VEX_4VShift + 1,
542  VEX_L = 1ULL << VEX_LShift,
543 
544  // EVEX_K - Set if this instruction requires masking
545  EVEX_KShift = VEX_LShift + 1,
546  EVEX_K = 1ULL << EVEX_KShift,
547 
548  // EVEX_Z - Set if this instruction has EVEX.Z field set.
549  EVEX_ZShift = EVEX_KShift + 1,
550  EVEX_Z = 1ULL << EVEX_ZShift,
551 
552  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
553  EVEX_L2Shift = EVEX_ZShift + 1,
555 
556  // EVEX_B - Set if this instruction has EVEX.B field set.
557  EVEX_BShift = EVEX_L2Shift + 1,
558  EVEX_B = 1ULL << EVEX_BShift,
559 
560  // The scaling factor for the AVX512's 8-bit compressed displacement.
561  CD8_Scale_Shift = EVEX_BShift + 1,
563 
564  /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
565  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
566  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
567  /// storing a classifier in the imm8 field. To simplify our implementation,
568  /// we handle this by storeing the classifier in the opcode field and using
569  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
570  Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7,
572 
573  /// Explicitly specified rounding control
574  EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1,
576  };
577 
578  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
579  // specified machine instruction.
580  //
581  inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
582  return TSFlags >> X86II::OpcodeShift;
583  }
584 
585  inline bool hasImm(uint64_t TSFlags) {
586  return (TSFlags & X86II::ImmMask) != 0;
587  }
588 
589  /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
590  /// of the specified instruction.
591  inline unsigned getSizeOfImm(uint64_t TSFlags) {
592  switch (TSFlags & X86II::ImmMask) {
593  default: llvm_unreachable("Unknown immediate size");
594  case X86II::Imm8:
595  case X86II::Imm8PCRel:
596  case X86II::Imm8Reg: return 1;
597  case X86II::Imm16:
598  case X86II::Imm16PCRel: return 2;
599  case X86II::Imm32:
600  case X86II::Imm32S:
601  case X86II::Imm32PCRel: return 4;
602  case X86II::Imm64: return 8;
603  }
604  }
605 
606  /// isImmPCRel - Return true if the immediate of the specified instruction's
607  /// TSFlags indicates that it is pc relative.
608  inline unsigned isImmPCRel(uint64_t TSFlags) {
609  switch (TSFlags & X86II::ImmMask) {
610  default: llvm_unreachable("Unknown immediate size");
611  case X86II::Imm8PCRel:
612  case X86II::Imm16PCRel:
613  case X86II::Imm32PCRel:
614  return true;
615  case X86II::Imm8:
616  case X86II::Imm8Reg:
617  case X86II::Imm16:
618  case X86II::Imm32:
619  case X86II::Imm32S:
620  case X86II::Imm64:
621  return false;
622  }
623  }
624 
625  /// isImmSigned - Return true if the immediate of the specified instruction's
626  /// TSFlags indicates that it is signed.
627  inline unsigned isImmSigned(uint64_t TSFlags) {
628  switch (TSFlags & X86II::ImmMask) {
629  default: llvm_unreachable("Unknown immediate signedness");
630  case X86II::Imm32S:
631  return true;
632  case X86II::Imm8:
633  case X86II::Imm8PCRel:
634  case X86II::Imm8Reg:
635  case X86II::Imm16:
636  case X86II::Imm16PCRel:
637  case X86II::Imm32:
638  case X86II::Imm32PCRel:
639  case X86II::Imm64:
640  return false;
641  }
642  }
643 
644  /// getOperandBias - compute any additional adjustment needed to
645  /// the offset to the start of the memory operand
646  /// in this instruction.
647  /// If this is a two-address instruction,skip one of the register operands.
648  /// FIXME: This should be handled during MCInst lowering.
649  inline unsigned getOperandBias(const MCInstrDesc& Desc)
650  {
651  unsigned NumOps = Desc.getNumOperands();
652  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
653  return 1;
654  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
655  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
656  // Special case for AVX-512 GATHER with 2 TIED_TO operands
657  // Skip the first 2 operands: dst, mask_wb
658  return 2;
659  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
660  Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
661  // Special case for GATHER with 2 TIED_TO operands
662  // Skip the first 2 operands: dst, mask_wb
663  return 2;
664  if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
665  // SCATTER
666  return 1;
667  return 0;
668  }
669 
670  /// getMemoryOperandNo - The function returns the MCInst operand # for the
671  /// first field of the memory operand. If the instruction doesn't have a
672  /// memory operand, this returns -1.
673  ///
674  /// Note that this ignores tied operands. If there is a tied register which
675  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
676  /// counted as one operand.
677  ///
678  inline int getMemoryOperandNo(uint64_t TSFlags) {
679  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
680  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
681 
682  switch (TSFlags & X86II::FormMask) {
683  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
684  case X86II::Pseudo:
685  case X86II::RawFrm:
686  case X86II::AddRegFrm:
687  case X86II::RawFrmImm8:
688  case X86II::RawFrmImm16:
690  case X86II::RawFrmSrc:
691  case X86II::RawFrmDst:
692  case X86II::RawFrmDstSrc:
693  return -1;
694  case X86II::MRMDestMem:
695  return 0;
696  case X86II::MRMSrcMem:
697  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
698  // mask register.
699  return 1 + HasVEX_4V + HasEVEX_K;
701  // Skip registers encoded in reg.
702  return 1 + HasEVEX_K;
703  case X86II::MRMSrcMemOp4:
704  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
705  return 3;
706  case X86II::MRMDestReg:
707  case X86II::MRMSrcReg:
709  case X86II::MRMSrcRegOp4:
710  case X86II::MRMXr:
711  case X86II::MRM0r: case X86II::MRM1r:
712  case X86II::MRM2r: case X86II::MRM3r:
713  case X86II::MRM4r: case X86II::MRM5r:
714  case X86II::MRM6r: case X86II::MRM7r:
715  return -1;
716  case X86II::MRMXm:
717  case X86II::MRM0m: case X86II::MRM1m:
718  case X86II::MRM2m: case X86II::MRM3m:
719  case X86II::MRM4m: case X86II::MRM5m:
720  case X86II::MRM6m: case X86II::MRM7m:
721  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
722  return 0 + HasVEX_4V + HasEVEX_K;
723  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
724  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
725  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
726  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
727  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
728  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
729  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
730  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
731  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
732  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
733  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
734  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
735  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
736  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
737  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
738  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
739  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
740  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
741  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
742  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
743  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
744  case X86II::MRM_FF:
745  return -1;
746  }
747  }
748 
749  /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
750  /// higher) register? e.g. r8, xmm8, xmm13, etc.
751  inline bool isX86_64ExtendedReg(unsigned RegNo) {
752  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
753  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
754  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
755  return true;
756 
757  switch (RegNo) {
758  default: break;
759  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
760  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
761  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
762  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
763  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
764  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
765  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
766  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
767  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
768  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
769  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
770  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
771  return true;
772  }
773  return false;
774  }
775 
776  /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
777  /// registers? e.g. zmm21, etc.
778  static inline bool is32ExtendedReg(unsigned RegNo) {
779  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
780  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
781  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
782  }
783 
784 
785  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
786  return (reg == X86::SPL || reg == X86::BPL ||
787  reg == X86::SIL || reg == X86::DIL);
788  }
789 
790  /// isKMasked - Is this a masked instruction.
791  inline bool isKMasked(uint64_t TSFlags) {
792  return (TSFlags & X86II::EVEX_K) != 0;
793  }
794 
795  /// isKMergedMasked - Is this a merge masked instruction.
796  inline bool isKMergeMasked(uint64_t TSFlags) {
797  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
798  }
799 }
800 
801 } // end namespace llvm;
802 
803 #endif
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:227
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:785
#define REP(f, t)
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:515
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:135
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:221
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:256
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:109
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:178
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:608
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:339
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:209
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:310
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:260
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:329
Has3DNow0F0FOpcode - This flag indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DN...
Definition: X86BaseInfo.h:570
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:528
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:94
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:534
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:153
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:232
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:541
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:585
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:274
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:204
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:252
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:751
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
Definition: X86BaseInfo.h:264
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
Definition: X86BaseInfo.h:269
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:82
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:56
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:194
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:215
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:145
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:324
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:290
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:186
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:649
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:627
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:300
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:280
Explicitly specified rounding control.
Definition: X86BaseInfo.h:574
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Windows x64, Windows Itanium (IA-64)
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:125
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:170
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:778
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:346
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:581
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
Definition: X86BaseInfo.h:796
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:295
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:101
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:248
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:162
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:591
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:73
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:305
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:47
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
Definition: X86BaseInfo.h:791
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:116
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:319
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:87
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:334
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:199
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:678