LLVM  6.0.0svn
X86BaseInfo.h
Go to the documentation of this file.
1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
19 
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/DataTypes.h"
24 
25 namespace llvm {
26 
27 namespace X86 {
28  // Enums for memory operand decoding. Each memory operand is represented with
29  // a 5 operand sequence in the form:
30  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31  // These enums help decode this.
32  enum {
36  AddrDisp = 3,
37 
38  /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 
41  /// AddrNumOperands - Total number of operands in a memory reference.
43  };
44 
45  /// AVX512 static rounding constants. These need to match the values in
46  /// avx512fintrin.h.
51  TO_ZERO = 3,
53  };
54 
55  /// The constants to describe instr prefixes if there are
56  enum IPREFIXES {
63  };
64 } // end namespace X86;
65 
66 /// X86II - This namespace holds all of the target specific flags that
67 /// instruction info tracks.
68 ///
69 namespace X86II {
70  /// Target Operand Flag enum.
71  enum TOF {
72  //===------------------------------------------------------------------===//
73  // X86 Specific MachineOperand flags.
74 
76 
77  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
78  /// relocation of:
79  /// SYMBOL_LABEL + [. - PICBASELABEL]
81 
82  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
83  /// immediate should get the value of the symbol minus the PIC base label:
84  /// SYMBOL_LABEL - PICBASELABEL
86 
87  /// MO_GOT - On a symbol operand this indicates that the immediate is the
88  /// offset to the GOT entry for the symbol name from the base of the GOT.
89  ///
90  /// See the X86-64 ELF ABI supplement for more details.
91  /// SYMBOL_LABEL @GOT
93 
94  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
95  /// the offset to the location of the symbol name from the base of the GOT.
96  ///
97  /// See the X86-64 ELF ABI supplement for more details.
98  /// SYMBOL_LABEL @GOTOFF
100 
101  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
102  /// offset to the GOT entry for the symbol name from the current code
103  /// location.
104  ///
105  /// See the X86-64 ELF ABI supplement for more details.
106  /// SYMBOL_LABEL @GOTPCREL
108 
109  /// MO_PLT - On a symbol operand this indicates that the immediate is
110  /// offset to the PLT entry of symbol name from the current code location.
111  ///
112  /// See the X86-64 ELF ABI supplement for more details.
113  /// SYMBOL_LABEL @PLT
115 
116  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
117  /// the offset of the GOT entry with the TLS index structure that contains
118  /// the module number and variable offset for the symbol. Used in the
119  /// general dynamic TLS access model.
120  ///
121  /// See 'ELF Handling for Thread-Local Storage' for more details.
122  /// SYMBOL_LABEL @TLSGD
124 
125  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
126  /// the offset of the GOT entry with the TLS index for the module that
127  /// contains the symbol. When this index is passed to a call to
128  /// __tls_get_addr, the function will return the base address of the TLS
129  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
130  ///
131  /// See 'ELF Handling for Thread-Local Storage' for more details.
132  /// SYMBOL_LABEL @TLSLD
134 
135  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
136  /// the offset of the GOT entry with the TLS index for the module that
137  /// contains the symbol. When this index is passed to a call to
138  /// ___tls_get_addr, the function will return the base address of the TLS
139  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
140  ///
141  /// See 'ELF Handling for Thread-Local Storage' for more details.
142  /// SYMBOL_LABEL @TLSLDM
144 
145  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
146  /// the offset of the GOT entry with the thread-pointer offset for the
147  /// symbol. Used in the x86-64 initial exec TLS access model.
148  ///
149  /// See 'ELF Handling for Thread-Local Storage' for more details.
150  /// SYMBOL_LABEL @GOTTPOFF
152 
153  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
154  /// the absolute address of the GOT entry with the negative thread-pointer
155  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
156  /// model.
157  ///
158  /// See 'ELF Handling for Thread-Local Storage' for more details.
159  /// SYMBOL_LABEL @INDNTPOFF
161 
162  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
163  /// the thread-pointer offset for the symbol. Used in the x86-64 local
164  /// exec TLS access model.
165  ///
166  /// See 'ELF Handling for Thread-Local Storage' for more details.
167  /// SYMBOL_LABEL @TPOFF
169 
170  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
171  /// the offset of the GOT entry with the TLS offset of the symbol. Used
172  /// in the local dynamic TLS access model.
173  ///
174  /// See 'ELF Handling for Thread-Local Storage' for more details.
175  /// SYMBOL_LABEL @DTPOFF
177 
178  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
179  /// the negative thread-pointer offset for the symbol. Used in the IA32
180  /// local exec TLS access model.
181  ///
182  /// See 'ELF Handling for Thread-Local Storage' for more details.
183  /// SYMBOL_LABEL @NTPOFF
185 
186  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
187  /// the offset of the GOT entry with the negative thread-pointer offset for
188  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
189  ///
190  /// See 'ELF Handling for Thread-Local Storage' for more details.
191  /// SYMBOL_LABEL @GOTNTPOFF
193 
194  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
195  /// reference is actually to the "__imp_FOO" symbol. This is used for
196  /// dllimport linkage on windows.
198 
199  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
200  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
201  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
203 
204  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
205  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
206  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
208 
209  /// MO_TLVP - On a symbol operand this indicates that the immediate is
210  /// some TLS offset.
211  ///
212  /// This is the TLS offset for the Darwin TLS mechanism.
214 
215  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
216  /// is some TLS offset from the picbase.
217  ///
218  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
220 
221  /// MO_SECREL - On a symbol operand this indicates that the immediate is
222  /// the offset from beginning of section.
223  ///
224  /// This is the TLS offset for the COFF/Windows TLS mechanism.
226 
227  /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
228  /// to be an absolute symbol in range [0,128), so we can use the @ABS8
229  /// symbol modifier.
231  };
232 
233  enum : uint64_t {
234  //===------------------------------------------------------------------===//
235  // Instruction encodings. These are the standard/most common forms for X86
236  // instructions.
237  //
238 
239  // PseudoFrm - This represents an instruction that is a pseudo instruction
240  // or one that has not been implemented yet. It is illegal to code generate
241  // it, but tolerated for intermediate implementation stages.
242  Pseudo = 0,
243 
244  /// Raw - This form is for instructions that don't have any operands, so
245  /// they are just a fixed opcode value, like 'leave'.
246  RawFrm = 1,
247 
248  /// AddRegFrm - This form is used for instructions like 'push r32' that have
249  /// their one register operand added to their opcode.
251 
252  /// RawFrmMemOffs - This form is for instructions that store an absolute
253  /// memory offset as an immediate with a possible segment override.
255 
256  /// RawFrmSrc - This form is for instructions that use the source index
257  /// register SI/ESI/RSI with a possible segment override.
259 
260  /// RawFrmDst - This form is for instructions that use the destination index
261  /// register DI/EDI/ESI.
263 
264  /// RawFrmSrc - This form is for instructions that use the source index
265  /// register SI/ESI/ERI with a possible segment override, and also the
266  /// destination index register DI/ESI/RDI.
268 
269  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
270  /// immediates, the first of which is a 16-bit immediate (specified by
271  /// the imm encoding) and the second is a 8-bit fixed value.
273 
274  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
275  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
276  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
277  /// manual, this operand is described as pntr16:32 and pntr16:16
279 
280  /// MRM[0-7][rm] - These forms are used to represent instructions that use
281  /// a Mod/RM byte, and use the middle field to hold extended opcode
282  /// information. In the intel manual these are represented as /0, /1, ...
283  ///
284 
285  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
286  /// to specify a destination, which in this case is memory.
287  ///
289 
290  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
291  /// to specify a source, which in this case is memory.
292  ///
293  MRMSrcMem = 33,
294 
295  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
296  /// operand 3 with VEX.VVVV and load from memory.
297  ///
299 
300  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
301  /// byte to specify the fourth source, which in this case is memory.
302  ///
304 
305  /// MRMXm - This form is used for instructions that use the Mod/RM byte
306  /// to specify a memory source, but doesn't use the middle field.
307  ///
308  MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
309 
310  // Next, instructions that operate on a memory r/m operand...
311  MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
312  MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
313 
314  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
315  /// to specify a destination, which in this case is a register.
316  ///
318 
319  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
320  /// to specify a source, which in this case is a register.
321  ///
322  MRMSrcReg = 49,
323 
324  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
325  /// operand 3 with VEX.VVVV and do not load from memory.
326  ///
328 
329  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
330  /// byte to specify the fourth source, which in this case is a register.
331  ///
333 
334  /// MRMXr - This form is used for instructions that use the Mod/RM byte
335  /// to specify a register source, but doesn't use the middle field.
336  ///
337  MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
338 
339  // Instructions that operate on a register r/m operand...
340  MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
341  MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
342 
343  /// MRM_XX - A mod/rm byte of exactly 0xXX.
344  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
345  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
346  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
347  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
348  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
349  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
350  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
351  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
352  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
353  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
354  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
355  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
356  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
357  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
358  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
359  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
360 
361  FormMask = 127,
362 
363  //===------------------------------------------------------------------===//
364  // Actual flags...
365 
366  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
367  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
368  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
369  // prefix in 16-bit mode.
372 
376 
377  // AsSize - AdSizeX implies this instruction determines its need of 0x67
378  // prefix from a normal ModRM memory operand. The other types indicate that
379  // an operand is encoded with a specific width and a prefix is needed if
380  // it differs from the current mode.
383 
388 
389  //===------------------------------------------------------------------===//
390  // OpPrefix - There are several prefix bytes that are used as opcode
391  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
392  // no prefix.
393  //
396 
397  // PS, PD - Prefix code for packed single and double precision vector
398  // floating point operations performed in the SSE registers.
400 
401  // XS, XD - These prefix codes are for single and double precision scalar
402  // floating point operations performed in the SSE registers.
404 
405  //===------------------------------------------------------------------===//
406  // OpMap - This field determines which opcode map this instruction
407  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
408  //
411 
412  // OB - OneByte - Set if this instruction has a one byte opcode.
413  OB = 0 << OpMapShift,
414 
415  // TB - TwoByte - Set if this instruction has a two byte opcode, which
416  // starts with a 0x0F byte before the real opcode.
417  TB = 1 << OpMapShift,
418 
419  // T8, TA - Prefix after the 0x0F prefix.
420  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
421 
422  // XOP8 - Prefix to include use of imm byte.
423  XOP8 = 4 << OpMapShift,
424 
425  // XOP9 - Prefix to exclude use of imm byte.
426  XOP9 = 5 << OpMapShift,
427 
428  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
429  XOPA = 6 << OpMapShift,
430 
431  //===------------------------------------------------------------------===//
432  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
433  // They are used to specify GPRs and SSE registers, 64-bit operand size,
434  // etc. We only cares about REX.W and REX.R bits and only the former is
435  // statically determined.
436  //
438  REX_W = 1 << REXShift,
439 
440  //===------------------------------------------------------------------===//
441  // This three-bit field describes the size of an immediate operand. Zero is
442  // unused so that we can tell if we forgot to set a value.
444  ImmMask = 15 << ImmShift,
445  Imm8 = 1 << ImmShift,
448  Imm16 = 4 << ImmShift,
450  Imm32 = 6 << ImmShift,
452  Imm32S = 8 << ImmShift,
453  Imm64 = 9 << ImmShift,
454 
455  //===------------------------------------------------------------------===//
456  // FP Instruction Classification... Zero is non-fp instruction.
457 
458  // FPTypeMask - Mask for all of the FP types...
461 
462  // NotFP - The default, set for instructions that do not use FP registers.
464 
465  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
467 
468  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
470 
471  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
472  // result back to ST(0). For example, fcos, fsqrt, etc.
473  //
475 
476  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
477  // explicit argument, storing the result to either ST(0) or the implicit
478  // argument. For example: fadd, fsub, fmul, etc...
480 
481  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
482  // explicit argument, but have no destination. Example: fucom, fucomi, ...
484 
485  // CondMovFP - "2 operand" floating point conditional move instructions.
487 
488  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
490 
491  // Lock prefix
493  LOCK = 1 << LOCKShift,
494 
495  // REP prefix
497  REP = 1 << REPShift,
498 
499  // Execution domain for SSE instructions.
500  // 0 means normal, non-SSE instruction.
502 
503  // Encoding
506 
507  // VEX - encoding using 0xC4/0xC5
509 
510  /// XOP - Opcode prefix used by XOP instructions.
512 
513  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
514  // syntax support up to 32 512-bit register operands and up to 7 16-bit
515  // mask operands as well as source operand data swizzling/memory operand
516  // conversion, eviction hint, and rounding mode.
518 
519  // Opcode
521 
522  /// VEX_W - Has a opcode specific functionality, but is used in the same
523  /// way as REX_W is for regular SSE instructions.
525  VEX_W = 1ULL << VEX_WShift,
526 
527  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
528  /// address instructions in SSE are represented as 3 address ones in AVX
529  /// and the additional register is encoded in VEX_VVVV prefix.
530  VEX_4VShift = VEX_WShift + 1,
531  VEX_4V = 1ULL << VEX_4VShift,
532 
533  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
534  /// instruction uses 256-bit wide registers. This is usually auto detected
535  /// if a VR256 register is used, but some AVX instructions also have this
536  /// field marked when using a f256 memory references.
537  VEX_LShift = VEX_4VShift + 1,
538  VEX_L = 1ULL << VEX_LShift,
539 
540  // EVEX_K - Set if this instruction requires masking
541  EVEX_KShift = VEX_LShift + 1,
542  EVEX_K = 1ULL << EVEX_KShift,
543 
544  // EVEX_Z - Set if this instruction has EVEX.Z field set.
545  EVEX_ZShift = EVEX_KShift + 1,
546  EVEX_Z = 1ULL << EVEX_ZShift,
547 
548  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
549  EVEX_L2Shift = EVEX_ZShift + 1,
551 
552  // EVEX_B - Set if this instruction has EVEX.B field set.
553  EVEX_BShift = EVEX_L2Shift + 1,
554  EVEX_B = 1ULL << EVEX_BShift,
555 
556  // The scaling factor for the AVX512's 8-bit compressed displacement.
557  CD8_Scale_Shift = EVEX_BShift + 1,
559 
560  /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
561  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
562  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
563  /// storing a classifier in the imm8 field. To simplify our implementation,
564  /// we handle this by storeing the classifier in the opcode field and using
565  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
566  Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7,
568 
569  /// Explicitly specified rounding control
570  EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1,
572  };
573 
574  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
575  // specified machine instruction.
576  //
577  inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
578  return TSFlags >> X86II::OpcodeShift;
579  }
580 
581  inline bool hasImm(uint64_t TSFlags) {
582  return (TSFlags & X86II::ImmMask) != 0;
583  }
584 
585  /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
586  /// of the specified instruction.
587  inline unsigned getSizeOfImm(uint64_t TSFlags) {
588  switch (TSFlags & X86II::ImmMask) {
589  default: llvm_unreachable("Unknown immediate size");
590  case X86II::Imm8:
591  case X86II::Imm8PCRel:
592  case X86II::Imm8Reg: return 1;
593  case X86II::Imm16:
594  case X86II::Imm16PCRel: return 2;
595  case X86II::Imm32:
596  case X86II::Imm32S:
597  case X86II::Imm32PCRel: return 4;
598  case X86II::Imm64: return 8;
599  }
600  }
601 
602  /// isImmPCRel - Return true if the immediate of the specified instruction's
603  /// TSFlags indicates that it is pc relative.
604  inline unsigned isImmPCRel(uint64_t TSFlags) {
605  switch (TSFlags & X86II::ImmMask) {
606  default: llvm_unreachable("Unknown immediate size");
607  case X86II::Imm8PCRel:
608  case X86II::Imm16PCRel:
609  case X86II::Imm32PCRel:
610  return true;
611  case X86II::Imm8:
612  case X86II::Imm8Reg:
613  case X86II::Imm16:
614  case X86II::Imm32:
615  case X86II::Imm32S:
616  case X86II::Imm64:
617  return false;
618  }
619  }
620 
621  /// isImmSigned - Return true if the immediate of the specified instruction's
622  /// TSFlags indicates that it is signed.
623  inline unsigned isImmSigned(uint64_t TSFlags) {
624  switch (TSFlags & X86II::ImmMask) {
625  default: llvm_unreachable("Unknown immediate signedness");
626  case X86II::Imm32S:
627  return true;
628  case X86II::Imm8:
629  case X86II::Imm8PCRel:
630  case X86II::Imm8Reg:
631  case X86II::Imm16:
632  case X86II::Imm16PCRel:
633  case X86II::Imm32:
634  case X86II::Imm32PCRel:
635  case X86II::Imm64:
636  return false;
637  }
638  }
639 
640  /// getOperandBias - compute any additional adjustment needed to
641  /// the offset to the start of the memory operand
642  /// in this instruction.
643  /// If this is a two-address instruction,skip one of the register operands.
644  /// FIXME: This should be handled during MCInst lowering.
645  inline unsigned getOperandBias(const MCInstrDesc& Desc)
646  {
647  unsigned NumOps = Desc.getNumOperands();
648  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
649  return 1;
650  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
651  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
652  // Special case for AVX-512 GATHER with 2 TIED_TO operands
653  // Skip the first 2 operands: dst, mask_wb
654  return 2;
655  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
656  Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
657  // Special case for GATHER with 2 TIED_TO operands
658  // Skip the first 2 operands: dst, mask_wb
659  return 2;
660  if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
661  // SCATTER
662  return 1;
663  return 0;
664  }
665 
666  /// getMemoryOperandNo - The function returns the MCInst operand # for the
667  /// first field of the memory operand. If the instruction doesn't have a
668  /// memory operand, this returns -1.
669  ///
670  /// Note that this ignores tied operands. If there is a tied register which
671  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
672  /// counted as one operand.
673  ///
674  inline int getMemoryOperandNo(uint64_t TSFlags) {
675  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
676  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
677 
678  switch (TSFlags & X86II::FormMask) {
679  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
680  case X86II::Pseudo:
681  case X86II::RawFrm:
682  case X86II::AddRegFrm:
683  case X86II::RawFrmImm8:
684  case X86II::RawFrmImm16:
686  case X86II::RawFrmSrc:
687  case X86II::RawFrmDst:
688  case X86II::RawFrmDstSrc:
689  return -1;
690  case X86II::MRMDestMem:
691  return 0;
692  case X86II::MRMSrcMem:
693  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
694  // mask register.
695  return 1 + HasVEX_4V + HasEVEX_K;
697  // Skip registers encoded in reg.
698  return 1 + HasEVEX_K;
699  case X86II::MRMSrcMemOp4:
700  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
701  return 3;
702  case X86II::MRMDestReg:
703  case X86II::MRMSrcReg:
705  case X86II::MRMSrcRegOp4:
706  case X86II::MRMXr:
707  case X86II::MRM0r: case X86II::MRM1r:
708  case X86II::MRM2r: case X86II::MRM3r:
709  case X86II::MRM4r: case X86II::MRM5r:
710  case X86II::MRM6r: case X86II::MRM7r:
711  return -1;
712  case X86II::MRMXm:
713  case X86II::MRM0m: case X86II::MRM1m:
714  case X86II::MRM2m: case X86II::MRM3m:
715  case X86II::MRM4m: case X86II::MRM5m:
716  case X86II::MRM6m: case X86II::MRM7m:
717  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
718  return 0 + HasVEX_4V + HasEVEX_K;
719  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
720  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
721  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
722  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
723  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
724  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
725  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
726  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
727  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
728  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
729  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
730  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
731  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
732  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
733  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
734  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
735  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
736  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
737  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
738  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
739  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
740  case X86II::MRM_FF:
741  return -1;
742  }
743  }
744 
745  /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
746  /// higher) register? e.g. r8, xmm8, xmm13, etc.
747  inline bool isX86_64ExtendedReg(unsigned RegNo) {
748  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
749  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
750  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
751  return true;
752 
753  switch (RegNo) {
754  default: break;
755  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
756  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
757  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
758  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
759  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
760  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
761  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
762  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
763  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
764  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
765  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
766  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
767  return true;
768  }
769  return false;
770  }
771 
772  /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
773  /// registers? e.g. zmm21, etc.
774  static inline bool is32ExtendedReg(unsigned RegNo) {
775  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
776  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
777  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
778  }
779 
780 
781  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
782  return (reg == X86::SPL || reg == X86::BPL ||
783  reg == X86::SIL || reg == X86::DIL);
784  }
785 
786  /// isKMasked - Is this a masked instruction.
787  inline bool isKMasked(uint64_t TSFlags) {
788  return (TSFlags & X86II::EVEX_K) != 0;
789  }
790 
791  /// isKMergedMasked - Is this a merge masked instruction.
792  inline bool isKMergeMasked(uint64_t TSFlags) {
793  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
794  }
795 }
796 
797 } // end namespace llvm;
798 
799 #endif
Explicitly specified rounding control.
Definition: X86BaseInfo.h:570
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:225
AddRegFrm - This form is used for instructions like &#39;push r32&#39; that have their one register operand a...
Definition: X86BaseInfo.h:250
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:781
#define REP(f, t)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:133
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:219
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:272
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:107
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:176
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:322
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it is...
Definition: X86BaseInfo.h:604
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:530
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:207
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:258
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:254
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:317
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:537
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
Definition: X86BaseInfo.h:267
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:327
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:92
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:151
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:230
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:308
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:581
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:202
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:747
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:80
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:344
IPREFIXES
The constants to describe instr prefixes if there are.
Definition: X86BaseInfo.h:56
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:192
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:213
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
Definition: X86BaseInfo.h:262
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:337
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:143
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:511
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:184
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:645
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction&#39;s TSFlags indicates that it i...
Definition: X86BaseInfo.h:623
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:293
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Windows x64, Windows Itanium (IA-64)
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:123
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:168
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:774
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:288
Raw - This form is for instructions that don&#39;t have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:246
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:577
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
Definition: X86BaseInfo.h:792
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:99
Has3DNow0F0FOpcode - This flag indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DN...
Definition: X86BaseInfo.h:566
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:160
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:587
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:71
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:524
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:47
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
Definition: X86BaseInfo.h:787
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:114
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:298
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:85
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:278
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:303
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:332
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:197
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:674