LLVM  6.0.0svn
Namespaces | Enumerations | Functions
X86BaseInfo.h File Reference
#include "X86MCTargetDesc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h"
Include dependency graph for X86BaseInfo.h:
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Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::X86
 Define some predicates that are used for node matching.
 
 llvm::X86II
 X86II - This namespace holds all of the target specific flags that instruction info tracks.
 

Enumerations

enum  {
  llvm::X86::AddrBaseReg = 0, llvm::X86::AddrScaleAmt = 1, llvm::X86::AddrIndexReg = 2, llvm::X86::AddrDisp = 3,
  llvm::X86::AddrSegmentReg = 4, llvm::X86::AddrNumOperands = 5
}
 
enum  llvm::X86::STATIC_ROUNDING {
  llvm::X86::TO_NEAREST_INT = 0, llvm::X86::TO_NEG_INF = 1, llvm::X86::TO_POS_INF = 2, llvm::X86::TO_ZERO = 3,
  llvm::X86::CUR_DIRECTION = 4
}
 AVX512 static rounding constants. More...
 
enum  llvm::X86::IPREFIXES {
  llvm::X86::IP_NO_PREFIX = 0, llvm::X86::IP_HAS_OP_SIZE = 1, llvm::X86::IP_HAS_AD_SIZE = 2, llvm::X86::IP_HAS_REPEAT_NE = 4,
  llvm::X86::IP_HAS_REPEAT = 8, llvm::X86::IP_HAS_LOCK = 16
}
 The constants to describe instr prefixes if there are. More...
 
enum  llvm::X86II::TOF {
  llvm::X86II::MO_NO_FLAG, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_PIC_BASE_OFFSET, llvm::X86II::MO_GOT,
  llvm::X86II::MO_GOTOFF, llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_PLT, llvm::X86II::MO_TLSGD,
  llvm::X86II::MO_TLSLD, llvm::X86II::MO_TLSLDM, llvm::X86II::MO_GOTTPOFF, llvm::X86II::MO_INDNTPOFF,
  llvm::X86II::MO_TPOFF, llvm::X86II::MO_DTPOFF, llvm::X86II::MO_NTPOFF, llvm::X86II::MO_GOTNTPOFF,
  llvm::X86II::MO_DLLIMPORT, llvm::X86II::MO_DARWIN_NONLAZY, llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::X86II::MO_TLVP,
  llvm::X86II::MO_TLVP_PIC_BASE, llvm::X86II::MO_SECREL, llvm::X86II::MO_ABS8
}
 Target Operand Flag enum. More...
 
enum  : uint64_t {
  llvm::X86II::Pseudo = 0, llvm::X86II::RawFrm = 1, llvm::X86II::AddRegFrm = 2, llvm::X86II::RawFrmMemOffs = 3,
  llvm::X86II::RawFrmSrc = 4, llvm::X86II::RawFrmDst = 5, llvm::X86II::RawFrmDstSrc = 6, llvm::X86II::RawFrmImm8 = 7,
  llvm::X86II::RawFrmImm16 = 8, llvm::X86II::MRMDestMem = 32, llvm::X86II::MRMSrcMem = 33, llvm::X86II::MRMSrcMem4VOp3 = 34,
  llvm::X86II::MRMSrcMemOp4 = 35, llvm::X86II::MRMXm = 39, llvm::X86II::MRM0m = 40, llvm::X86II::MRM1m = 41,
  llvm::X86II::MRM2m = 42, llvm::X86II::MRM3m = 43, llvm::X86II::MRM4m = 44, llvm::X86II::MRM5m = 45,
  llvm::X86II::MRM6m = 46, llvm::X86II::MRM7m = 47, llvm::X86II::MRMDestReg = 48, llvm::X86II::MRMSrcReg = 49,
  llvm::X86II::MRMSrcReg4VOp3 = 50, llvm::X86II::MRMSrcRegOp4 = 51, llvm::X86II::MRMXr = 55, llvm::X86II::MRM0r = 56,
  llvm::X86II::MRM1r = 57, llvm::X86II::MRM2r = 58, llvm::X86II::MRM3r = 59, llvm::X86II::MRM4r = 60,
  llvm::X86II::MRM5r = 61, llvm::X86II::MRM6r = 62, llvm::X86II::MRM7r = 63, llvm::X86II::MRM_C0 = 64,
  llvm::X86II::MRM_C1 = 65, llvm::X86II::MRM_C2 = 66, llvm::X86II::MRM_C3 = 67, llvm::X86II::MRM_C4 = 68,
  llvm::X86II::MRM_C5 = 69, llvm::X86II::MRM_C6 = 70, llvm::X86II::MRM_C7 = 71, llvm::X86II::MRM_C8 = 72,
  llvm::X86II::MRM_C9 = 73, llvm::X86II::MRM_CA = 74, llvm::X86II::MRM_CB = 75, llvm::X86II::MRM_CC = 76,
  llvm::X86II::MRM_CD = 77, llvm::X86II::MRM_CE = 78, llvm::X86II::MRM_CF = 79, llvm::X86II::MRM_D0 = 80,
  llvm::X86II::MRM_D1 = 81, llvm::X86II::MRM_D2 = 82, llvm::X86II::MRM_D3 = 83, llvm::X86II::MRM_D4 = 84,
  llvm::X86II::MRM_D5 = 85, llvm::X86II::MRM_D6 = 86, llvm::X86II::MRM_D7 = 87, llvm::X86II::MRM_D8 = 88,
  llvm::X86II::MRM_D9 = 89, llvm::X86II::MRM_DA = 90, llvm::X86II::MRM_DB = 91, llvm::X86II::MRM_DC = 92,
  llvm::X86II::MRM_DD = 93, llvm::X86II::MRM_DE = 94, llvm::X86II::MRM_DF = 95, llvm::X86II::MRM_E0 = 96,
  llvm::X86II::MRM_E1 = 97, llvm::X86II::MRM_E2 = 98, llvm::X86II::MRM_E3 = 99, llvm::X86II::MRM_E4 = 100,
  llvm::X86II::MRM_E5 = 101, llvm::X86II::MRM_E6 = 102, llvm::X86II::MRM_E7 = 103, llvm::X86II::MRM_E8 = 104,
  llvm::X86II::MRM_E9 = 105, llvm::X86II::MRM_EA = 106, llvm::X86II::MRM_EB = 107, llvm::X86II::MRM_EC = 108,
  llvm::X86II::MRM_ED = 109, llvm::X86II::MRM_EE = 110, llvm::X86II::MRM_EF = 111, llvm::X86II::MRM_F0 = 112,
  llvm::X86II::MRM_F1 = 113, llvm::X86II::MRM_F2 = 114, llvm::X86II::MRM_F3 = 115, llvm::X86II::MRM_F4 = 116,
  llvm::X86II::MRM_F5 = 117, llvm::X86II::MRM_F6 = 118, llvm::X86II::MRM_F7 = 119, llvm::X86II::MRM_F8 = 120,
  llvm::X86II::MRM_F9 = 121, llvm::X86II::MRM_FA = 122, llvm::X86II::MRM_FB = 123, llvm::X86II::MRM_FC = 124,
  llvm::X86II::MRM_FD = 125, llvm::X86II::MRM_FE = 126, llvm::X86II::MRM_FF = 127, llvm::X86II::FormMask = 127,
  llvm::X86II::OpSizeShift = 7, llvm::X86II::OpSizeMask = 0x3 << OpSizeShift, llvm::X86II::OpSizeFixed = 0 << OpSizeShift, llvm::X86II::OpSize16 = 1 << OpSizeShift,
  llvm::X86II::OpSize32 = 2 << OpSizeShift, llvm::X86II::AdSizeShift = OpSizeShift + 2, llvm::X86II::AdSizeMask = 0x3 << AdSizeShift, llvm::X86II::AdSizeX = 1 << AdSizeShift,
  llvm::X86II::AdSize16 = 1 << AdSizeShift, llvm::X86II::AdSize32 = 2 << AdSizeShift, llvm::X86II::AdSize64 = 3 << AdSizeShift, llvm::X86II::OpPrefixShift = AdSizeShift + 2,
  llvm::X86II::OpPrefixMask = 0x7 << OpPrefixShift, llvm::X86II::PS = 1 << OpPrefixShift, llvm::X86II::PD = 2 << OpPrefixShift, llvm::X86II::XS = 3 << OpPrefixShift,
  llvm::X86II::XD = 4 << OpPrefixShift, llvm::X86II::OpMapShift = OpPrefixShift + 3, llvm::X86II::OpMapMask = 0x7 << OpMapShift, llvm::X86II::OB = 0 << OpMapShift,
  llvm::X86II::TB = 1 << OpMapShift, llvm::X86II::T8 = 2 << OpMapShift, llvm::X86II::TA = 3 << OpMapShift, llvm::X86II::XOP8 = 4 << OpMapShift,
  llvm::X86II::XOP9 = 5 << OpMapShift, llvm::X86II::XOPA = 6 << OpMapShift, llvm::X86II::REXShift = OpMapShift + 3, llvm::X86II::REX_W = 1 << REXShift,
  llvm::X86II::ImmShift = REXShift + 1, llvm::X86II::ImmMask = 15 << ImmShift, llvm::X86II::Imm8 = 1 << ImmShift, llvm::X86II::Imm8PCRel = 2 << ImmShift,
  llvm::X86II::Imm8Reg = 3 << ImmShift, llvm::X86II::Imm16 = 4 << ImmShift, llvm::X86II::Imm16PCRel = 5 << ImmShift, llvm::X86II::Imm32 = 6 << ImmShift,
  llvm::X86II::Imm32PCRel = 7 << ImmShift, llvm::X86II::Imm32S = 8 << ImmShift, llvm::X86II::Imm64 = 9 << ImmShift, llvm::X86II::FPTypeShift = ImmShift + 4,
  llvm::X86II::FPTypeMask = 7 << FPTypeShift, llvm::X86II::NotFP = 0 << FPTypeShift, llvm::X86II::ZeroArgFP = 1 << FPTypeShift, llvm::X86II::OneArgFP = 2 << FPTypeShift,
  llvm::X86II::OneArgFPRW = 3 << FPTypeShift, llvm::X86II::TwoArgFP = 4 << FPTypeShift, llvm::X86II::CompareFP = 5 << FPTypeShift, llvm::X86II::CondMovFP = 6 << FPTypeShift,
  llvm::X86II::SpecialFP = 7 << FPTypeShift, llvm::X86II::LOCKShift = FPTypeShift + 3, llvm::X86II::LOCK = 1 << LOCKShift, llvm::X86II::REPShift = LOCKShift + 1,
  llvm::X86II::REP = 1 << REPShift, llvm::X86II::SSEDomainShift = REPShift + 1, llvm::X86II::EncodingShift = SSEDomainShift + 2, llvm::X86II::EncodingMask = 0x3 << EncodingShift,
  llvm::X86II::VEX = 1 << EncodingShift, llvm::X86II::XOP = 2 << EncodingShift, llvm::X86II::EVEX = 3 << EncodingShift, llvm::X86II::OpcodeShift = EncodingShift + 2,
  llvm::X86II::VEX_WShift = OpcodeShift + 8, llvm::X86II::VEX_W = 1ULL << VEX_WShift, llvm::X86II::VEX_4VShift = VEX_WShift + 1, llvm::X86II::VEX_4V = 1ULL << VEX_4VShift,
  llvm::X86II::VEX_LShift = VEX_4VShift + 1, llvm::X86II::VEX_L = 1ULL << VEX_LShift, llvm::X86II::EVEX_KShift = VEX_LShift + 1, llvm::X86II::EVEX_K = 1ULL << EVEX_KShift,
  llvm::X86II::EVEX_ZShift = EVEX_KShift + 1, llvm::X86II::EVEX_Z = 1ULL << EVEX_ZShift, llvm::X86II::EVEX_L2Shift = EVEX_ZShift + 1, llvm::X86II::EVEX_L2 = 1ULL << EVEX_L2Shift,
  llvm::X86II::EVEX_BShift = EVEX_L2Shift + 1, llvm::X86II::EVEX_B = 1ULL << EVEX_BShift, llvm::X86II::CD8_Scale_Shift = EVEX_BShift + 1, llvm::X86II::CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
  llvm::X86II::Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7, llvm::X86II::Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift, llvm::X86II::EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1, llvm::X86II::EVEX_RC = 1ULL << EVEX_RCShift
}
 

Functions

unsigned char llvm::X86II::getBaseOpcodeFor (uint64_t TSFlags)
 
bool llvm::X86II::hasImm (uint64_t TSFlags)
 
unsigned llvm::X86II::getSizeOfImm (uint64_t TSFlags)
 getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instruction. More...
 
unsigned llvm::X86II::isImmPCRel (uint64_t TSFlags)
 isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is pc relative. More...
 
unsigned llvm::X86II::isImmSigned (uint64_t TSFlags)
 isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it is signed. More...
 
unsigned llvm::X86II::getOperandBias (const MCInstrDesc &Desc)
 getOperandBias - compute any additional adjustment needed to the offset to the start of the memory operand in this instruction. More...
 
int llvm::X86II::getMemoryOperandNo (uint64_t TSFlags)
 getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory operand. More...
 
bool llvm::X86II::isX86_64ExtendedReg (unsigned RegNo)
 isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g. More...
 
static bool llvm::X86II::is32ExtendedReg (unsigned RegNo)
 is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e.g. More...
 
bool llvm::X86II::isX86_64NonExtLowByteReg (unsigned reg)
 
bool llvm::X86II::isKMasked (uint64_t TSFlags)
 isKMasked - Is this a masked instruction. More...
 
bool llvm::X86II::isKMergeMasked (uint64_t TSFlags)
 isKMergedMasked - Is this a merge masked instruction. More...