LLVM  7.0.0svn
X86Subtarget.cpp
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1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/ConstantRange.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/Debug.h"
36 
37 #if defined(_MSC_VER)
38 #include <intrin.h>
39 #endif
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "subtarget"
44 
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "X86GenSubtargetInfo.inc"
48 
49 // Temporary option to control early if-conversion for x86 while adding machine
50 // models.
51 static cl::opt<bool>
52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
53  cl::desc("Enable early if-conversion on X86"));
54 
55 
56 /// Classify a blockaddress reference for the current subtarget according to how
57 /// we should reference it in a non-pcrel context.
59  return classifyLocalReference(nullptr);
60 }
61 
62 /// Classify a global variable reference for the current subtarget according to
63 /// how we should reference it in a non-pcrel context.
64 unsigned char
66  return classifyGlobalReference(GV, *GV->getParent());
67 }
68 
69 unsigned char
71  // 64 bits can use %rip addressing for anything local.
72  if (is64Bit())
73  return X86II::MO_NO_FLAG;
74 
75  // If this is for a position dependent executable, the static linker can
76  // figure it out.
77  if (!isPositionIndependent())
78  return X86II::MO_NO_FLAG;
79 
80  // The COFF dynamic linker just patches the executable sections.
81  if (isTargetCOFF())
82  return X86II::MO_NO_FLAG;
83 
84  if (isTargetDarwin()) {
85  // 32 bit macho has no relocation for a-b if a is undefined, even if
86  // b is in the section that is being relocated.
87  // This means we have to use o load even for GVs that are known to be
88  // local to the dso.
89  if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
91 
93  }
94 
95  return X86II::MO_GOTOFF;
96 }
97 
99  const Module &M) const {
100  // Large model never uses stubs.
102  return X86II::MO_NO_FLAG;
103 
104  // Absolute symbols can be referenced directly.
105  if (GV) {
107  // See if we can use the 8-bit immediate form. Note that some instructions
108  // will sign extend the immediate operand, so to be conservative we only
109  // accept the range [0,128).
110  if (CR->getUnsignedMax().ult(128))
111  return X86II::MO_ABS8;
112  else
113  return X86II::MO_NO_FLAG;
114  }
115  }
116 
117  if (TM.shouldAssumeDSOLocal(M, GV))
118  return classifyLocalReference(GV);
119 
120  if (isTargetCOFF())
121  return X86II::MO_DLLIMPORT;
122 
123  if (is64Bit())
124  return X86II::MO_GOTPCREL;
125 
126  if (isTargetDarwin()) {
127  if (!isPositionIndependent())
130  }
131 
132  return X86II::MO_GOT;
133 }
134 
135 unsigned char
137  return classifyGlobalFunctionReference(GV, *GV->getParent());
138 }
139 
140 unsigned char
142  const Module &M) const {
143  if (TM.shouldAssumeDSOLocal(M, GV))
144  return X86II::MO_NO_FLAG;
145 
146  if (isTargetCOFF()) {
148  "shouldAssumeDSOLocal gave inconsistent answer");
149  return X86II::MO_DLLIMPORT;
150  }
151 
152  const Function *F = dyn_cast_or_null<Function>(GV);
153 
154  if (isTargetELF()) {
155  if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
156  // According to psABI, PLT stub clobbers XMM8-XMM15.
157  // In Regcall calling convention those registers are used for passing
158  // parameters. Thus we need to prevent lazy binding in Regcall.
159  return X86II::MO_GOTPCREL;
160  if (F && F->hasFnAttribute(Attribute::NonLazyBind) && is64Bit())
161  return X86II::MO_GOTPCREL;
162  return X86II::MO_PLT;
163  }
164 
165  if (is64Bit()) {
166  if (F && F->hasFnAttribute(Attribute::NonLazyBind))
167  // If the function is marked as non-lazy, generate an indirect call
168  // which loads from the GOT directly. This avoids runtime overhead
169  // at the cost of eager binding (and one extra byte of encoding).
170  return X86II::MO_GOTPCREL;
171  return X86II::MO_NO_FLAG;
172  }
173 
174  return X86II::MO_NO_FLAG;
175 }
176 
177 /// Return true if the subtarget allows calls to immediate address.
179  // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
180  // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
181  // the following check for Win32 should be removed.
182  if (In64BitMode || isTargetWin32())
183  return false;
185 }
186 
187 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
188  std::string CPUName = CPU;
189  if (CPUName.empty())
190  CPUName = "generic";
191 
192  // Make sure 64-bit features are available in 64-bit mode. (But make sure
193  // SSE2 can be turned off explicitly.)
194  std::string FullFS = FS;
195  if (In64BitMode) {
196  if (!FullFS.empty())
197  FullFS = "+64bit,+sse2," + FullFS;
198  else
199  FullFS = "+64bit,+sse2";
200  }
201 
202  // LAHF/SAHF are always supported in non-64-bit mode.
203  if (!In64BitMode) {
204  if (!FullFS.empty())
205  FullFS = "+sahf," + FullFS;
206  else
207  FullFS = "+sahf";
208  }
209 
210  // Parse features string and set the CPU.
211  ParseSubtargetFeatures(CPUName, FullFS);
212 
213  // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
214  // 16-bytes and under that are reasonably fast. These features were
215  // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
216  // micro-architectures respectively.
217  if (hasSSE42() || hasSSE4A())
218  IsUAMem16Slow = false;
219 
220  InstrItins = getInstrItineraryForCPU(CPUName);
221 
222  // It's important to keep the MCSubtargetInfo feature bits in sync with
223  // target data structure which is shared with MC code emitter, etc.
224  if (In64BitMode)
225  ToggleFeature(X86::Mode64Bit);
226  else if (In32BitMode)
227  ToggleFeature(X86::Mode32Bit);
228  else if (In16BitMode)
229  ToggleFeature(X86::Mode16Bit);
230  else
231  llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
232 
233  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
234  << ", 3DNowLevel " << X863DNowLevel
235  << ", 64bit " << HasX86_64 << "\n");
236  assert((!In64BitMode || HasX86_64) &&
237  "64-bit code requested on a subtarget that doesn't support it!");
238 
239  // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
240  // 32 and 64 bit) and for all 64-bit targets.
241  if (StackAlignOverride)
242  stackAlignment = StackAlignOverride;
243  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
244  isTargetKFreeBSD() || In64BitMode)
245  stackAlignment = 16;
246 
247  // Some CPUs have more overhead for gather. The specified overhead is relative
248  // to the Load operation. "2" is the number provided by Intel architects. This
249  // parameter is used for cost estimation of Gather Op and comparison with
250  // other alternatives.
251  // TODO: Remove the explicit hasAVX512()?, That would mean we would only
252  // enable gather with a -march.
253  if (hasAVX512() || (hasAVX2() && hasFastGather()))
254  GatherOverhead = 2;
255  if (hasAVX512())
256  ScatterOverhead = 2;
257 }
258 
259 void X86Subtarget::initializeEnvironment() {
260  X86SSELevel = NoSSE;
262  HasX87 = false;
263  HasNOPL = false;
264  HasCMov = false;
265  HasX86_64 = false;
266  HasPOPCNT = false;
267  HasSSE4A = false;
268  HasAES = false;
269  HasVAES = false;
270  HasFXSR = false;
271  HasXSAVE = false;
272  HasXSAVEOPT = false;
273  HasXSAVEC = false;
274  HasXSAVES = false;
275  HasPCLMUL = false;
276  HasVPCLMULQDQ = false;
277  HasGFNI = false;
278  HasFMA = false;
279  HasFMA4 = false;
280  HasXOP = false;
281  HasTBM = false;
282  HasLWP = false;
283  HasMOVBE = false;
284  HasRDRAND = false;
285  HasF16C = false;
286  HasFSGSBase = false;
287  HasLZCNT = false;
288  HasBMI = false;
289  HasBMI2 = false;
290  HasVBMI = false;
291  HasVBMI2 = false;
292  HasIFMA = false;
293  HasRTM = false;
294  HasERI = false;
295  HasCDI = false;
296  HasPFI = false;
297  HasDQI = false;
298  HasVPOPCNTDQ = false;
299  HasBWI = false;
300  HasVLX = false;
301  HasADX = false;
302  HasPKU = false;
303  HasVNNI = false;
304  HasBITALG = false;
305  HasSHA = false;
306  HasPREFETCHWT1 = false;
307  HasPRFCHW = false;
308  HasRDSEED = false;
309  HasLAHFSAHF = false;
310  HasMWAITX = false;
311  HasCLZERO = false;
312  HasMPX = false;
313  HasSHSTK = false;
314  HasIBT = false;
315  HasSGX = false;
316  HasCLFLUSHOPT = false;
317  HasCLWB = false;
318  IsPMULLDSlow = false;
319  IsSHLDSlow = false;
320  IsUAMem16Slow = false;
321  IsUAMem32Slow = false;
322  HasSSEUnalignedMem = false;
323  HasCmpxchg16b = false;
324  UseLeaForSP = false;
325  HasFastVariableShuffle = false;
327  HasFastGather = false;
328  HasFastScalarFSQRT = false;
329  HasFastVectorFSQRT = false;
330  HasFastLZCNT = false;
331  HasFastSHLDRotate = false;
332  HasMacroFusion = false;
333  HasERMSB = false;
334  HasSlowDivide32 = false;
335  HasSlowDivide64 = false;
336  PadShortFunctions = false;
337  SlowTwoMemOps = false;
338  LEAUsesAG = false;
339  SlowLEA = false;
340  Slow3OpsLEA = false;
341  SlowIncDec = false;
342  stackAlignment = 4;
343  // FIXME: this is a known good value for Yonah. How about others?
345  UseSoftFloat = false;
347  GatherOverhead = 1024;
348  ScatterOverhead = 1024;
349 }
350 
351 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
352  StringRef FS) {
353  initializeEnvironment();
354  initSubtargetFeatures(CPU, FS);
355  return *this;
356 }
357 
359  const X86TargetMachine &TM,
360  unsigned StackAlignOverride)
361  : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
362  PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
363  StackAlignOverride(StackAlignOverride),
364  In64BitMode(TargetTriple.getArch() == Triple::x86_64),
365  In32BitMode(TargetTriple.getArch() == Triple::x86 &&
366  TargetTriple.getEnvironment() != Triple::CODE16),
367  In16BitMode(TargetTriple.getArch() == Triple::x86 &&
368  TargetTriple.getEnvironment() == Triple::CODE16),
369  InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
370  FrameLowering(*this, getStackAlignment()) {
371  // Determine the PICStyle based on the target selected.
372  if (!isPositionIndependent())
374  else if (is64Bit())
376  else if (isTargetCOFF())
378  else if (isTargetDarwin())
380  else if (isTargetELF())
382 
384  Legalizer.reset(new X86LegalizerInfo(*this, TM));
385 
386  auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
387  RegBankInfo.reset(RBI);
388  InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
389 }
390 
392  return CallLoweringInfo.get();
393 }
394 
396  return InstSelector.get();
397 }
398 
400  return Legalizer.get();
401 }
402 
404  return RegBankInfo.get();
405 }
406 
408  return hasCMov() && X86EarlyIfConv;
409 }
bool isDeclarationForLinker() const
Definition: GlobalValue.h:517
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:193
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:117
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:148
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:448
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:172
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:340
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasAVX2() const
Definition: X86Subtarget.h:485
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:199
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:305
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:113
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:473
const TargetMachine & TM
Definition: X86Subtarget.h:84
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:302
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:357
bool HasERMSB
True if the processor has enhanced REP MOVSB/STOSB.
Definition: X86Subtarget.h:273
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:285
bool HasVPOPCNTDQ
Processor has AVX-512 population count Instructions.
Definition: X86Subtarget.h:308
const LegalizerInfo * getLegalizerInfo() const override
bool HasFastGather
True if gather is reasonably fast.
Definition: X86Subtarget.h:245
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:249
static cl::opt< bool > X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, cl::desc("Enable early if-conversion on X86"))
Optional< ConstantRange > getAbsoluteSymbolRange() const
If this is an absolute symbol reference, returns the range of the symbol, otherwise returns None...
Definition: Globals.cpp:272
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:270
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:221
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:254
bool HasLWP
Target has LWP instructions.
Definition: X86Subtarget.h:151
bool HasPREFETCHWT1
Processor has Prefetch with intent to Write instruction.
Definition: X86Subtarget.h:208
F(f)
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:109
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:215
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:157
bool HasFastPartialYMMorZMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register with...
Definition: X86Subtarget.h:241
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:346
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:139
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:253
Holds all the information related to register banks.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:209
bool HasGFNI
Target has Galois Field Arithmetic instructions.
Definition: X86Subtarget.h:136
bool HasVBMI2
Processor has VBMI2 instructions.
Definition: X86Subtarget.h:178
bool isTargetSolaris() const
Definition: X86Subtarget.h:602
bool HasCLFLUSHOPT
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:343
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:107
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:320
This class provides the information for the target register banks.
bool HasBITALG
Processor has AVX-512 Bit Algorithms instructions.
Definition: X86Subtarget.h:326
const InstructionSelector * getInstructionSelector() const override
This file contains the simple types necessary to represent the attributes associated with functions a...
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:257
bool HasSHSTK
Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack.
Definition: X86Subtarget.h:333
bool hasCommonLinkage() const
Definition: GlobalValue.h:432
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:299
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:366
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:94
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:181
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:229
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:232
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:93
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:233
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:90
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:204
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:110
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:166
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:160
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:296
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:402
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:610
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:202
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:423
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:187
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:314
bool HasFastSHLDRotate
True if SHLD based rotate is fast.
Definition: X86Subtarget.h:267
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:82
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:145
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:288
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:311
bool isPositionIndependent() const
Definition: X86Subtarget.h:658
bool hasCMov() const
Definition: X86Subtarget.h:477
bool enableEarlyIfConversion() const override
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:211
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:363
bool isTargetDarwin() const
Definition: X86Subtarget.h:599
bool hasSSE42() const
Definition: X86Subtarget.h:483
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:163
bool SlowTwoMemOps
True if two memory operand instructions should use a temporary register instead.
Definition: X86Subtarget.h:281
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:218
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This file declares the targeting of the RegisterBankInfo class for X86.
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
bool isTargetELF() const
Definition: X86Subtarget.h:605
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:416
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:369
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:329
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:79
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:104
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:225
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:129
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:190
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:169
bool HasNOPL
True if this processor has NOPL instruction (generally pentium pro+).
Definition: X86Subtarget.h:97
bool isTargetWin32() const
Definition: X86Subtarget.h:649
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:175
InstructionSelector * createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &, X86RegisterBankInfo &)
bool Slow3OpsLEA
True if the LEA instruction has all three source operands: base, index, and offset or if the LEA inst...
Definition: X86Subtarget.h:293
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
CodeModel::Model getCodeModel() const
Returns the code model.
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:349
This file describes how to lower LLVM calls to machine code calls.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:368
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:132
bool HasIBT
Processor supports CET IBT - Control-Flow Enforcement Technology using Indirect Branch Tracking...
Definition: X86Subtarget.h:337
Provides the logic to select generic machine instructions.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:101
This class provides the information for the target register banks.
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:123
bool HasFastVariableShuffle
True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuff...
Definition: X86Subtarget.h:237
bool HasMacroFusion
True if the processor supports macrofusion.
Definition: X86Subtarget.h:270
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:87
bool isTargetCOFF() const
Definition: X86Subtarget.h:606
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:120
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:116
bool HasVNNI
Processor has AVX-512 Vector Neural Network Instructions.
Definition: X86Subtarget.h:323
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:101
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:559
bool isTargetLinux() const
Definition: X86Subtarget.h:609
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:142
This file describes how to lower LLVM calls to machine code calls.
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:184
This file declares the targeting of the Machinelegalizer class for X86.
bool hasAVX512() const
Definition: X86Subtarget.h:486
const RegisterBankInfo * getRegBankInfo() const override
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
#define DEBUG(X)
Definition: Debug.h:118
bool hasSSE4A() const
Definition: X86Subtarget.h:489
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:126
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:317
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:264
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:87
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:196
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:353
bool hasFastGather() const
Definition: X86Subtarget.h:552
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:360
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:154
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:277
bool HasCLZERO
Processor has Cache Line Zero instruction.
Definition: X86Subtarget.h:205
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:199
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:261