LLVM  6.0.0svn
X86Subtarget.cpp
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1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/ConstantRange.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalValue.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/CodeGen.h"
34 #include "llvm/Support/Debug.h"
38 #include <cassert>
39 #include <string>
40 
41 #if defined(_MSC_VER)
42 #include <intrin.h>
43 #endif
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "subtarget"
48 
49 #define GET_SUBTARGETINFO_TARGET_DESC
50 #define GET_SUBTARGETINFO_CTOR
51 #include "X86GenSubtargetInfo.inc"
52 
53 // Temporary option to control early if-conversion for x86 while adding machine
54 // models.
55 static cl::opt<bool>
56 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
57  cl::desc("Enable early if-conversion on X86"));
58 
59 
60 /// Classify a blockaddress reference for the current subtarget according to how
61 /// we should reference it in a non-pcrel context.
63  return classifyLocalReference(nullptr);
64 }
65 
66 /// Classify a global variable reference for the current subtarget according to
67 /// how we should reference it in a non-pcrel context.
68 unsigned char
70  return classifyGlobalReference(GV, *GV->getParent());
71 }
72 
73 unsigned char
75  // 64 bits can use %rip addressing for anything local.
76  if (is64Bit())
77  return X86II::MO_NO_FLAG;
78 
79  // If this is for a position dependent executable, the static linker can
80  // figure it out.
81  if (!isPositionIndependent())
82  return X86II::MO_NO_FLAG;
83 
84  // The COFF dynamic linker just patches the executable sections.
85  if (isTargetCOFF())
86  return X86II::MO_NO_FLAG;
87 
88  if (isTargetDarwin()) {
89  // 32 bit macho has no relocation for a-b if a is undefined, even if
90  // b is in the section that is being relocated.
91  // This means we have to use o load even for GVs that are known to be
92  // local to the dso.
93  if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
95 
97  }
98 
99  return X86II::MO_GOTOFF;
100 }
101 
103  const Module &M) const {
104  // Large model never uses stubs.
106  return X86II::MO_NO_FLAG;
107 
108  // Absolute symbols can be referenced directly.
109  if (GV) {
111  // See if we can use the 8-bit immediate form. Note that some instructions
112  // will sign extend the immediate operand, so to be conservative we only
113  // accept the range [0,128).
114  if (CR->getUnsignedMax().ult(128))
115  return X86II::MO_ABS8;
116  else
117  return X86II::MO_NO_FLAG;
118  }
119  }
120 
121  if (TM.shouldAssumeDSOLocal(M, GV))
122  return classifyLocalReference(GV);
123 
124  if (isTargetCOFF())
125  return X86II::MO_DLLIMPORT;
126 
127  if (is64Bit())
128  return X86II::MO_GOTPCREL;
129 
130  if (isTargetDarwin()) {
131  if (!isPositionIndependent())
134  }
135 
136  return X86II::MO_GOT;
137 }
138 
139 unsigned char
141  return classifyGlobalFunctionReference(GV, *GV->getParent());
142 }
143 
144 unsigned char
146  const Module &M) const {
147  if (TM.shouldAssumeDSOLocal(M, GV))
148  return X86II::MO_NO_FLAG;
149 
150  if (isTargetCOFF()) {
152  "shouldAssumeDSOLocal gave inconsistent answer");
153  return X86II::MO_DLLIMPORT;
154  }
155 
156  const Function *F = dyn_cast_or_null<Function>(GV);
157 
158  if (isTargetELF()) {
159  if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
160  // According to psABI, PLT stub clobbers XMM8-XMM15.
161  // In Regcall calling convention those registers are used for passing
162  // parameters. Thus we need to prevent lazy binding in Regcall.
163  return X86II::MO_GOTPCREL;
164  if (F && F->hasFnAttribute(Attribute::NonLazyBind) && is64Bit())
165  return X86II::MO_GOTPCREL;
166  return X86II::MO_PLT;
167  }
168 
169  if (is64Bit()) {
170  if (F && F->hasFnAttribute(Attribute::NonLazyBind))
171  // If the function is marked as non-lazy, generate an indirect call
172  // which loads from the GOT directly. This avoids runtime overhead
173  // at the cost of eager binding (and one extra byte of encoding).
174  return X86II::MO_GOTPCREL;
175  return X86II::MO_NO_FLAG;
176  }
177 
178  return X86II::MO_NO_FLAG;
179 }
180 
181 /// This function returns the name of a function which has an interface like
182 /// the non-standard bzero function, if such a function exists on the
183 /// current subtarget and it is considered preferable over memset with zero
184 /// passed as the second argument. Otherwise it returns null.
185 const char *X86Subtarget::getBZeroEntry() const {
186  // Darwin 10 has a __bzero entry point for this purpose.
187  if (getTargetTriple().isMacOSX() &&
188  !getTargetTriple().isMacOSXVersionLT(10, 6))
189  return "__bzero";
190 
191  return nullptr;
192 }
193 
195  if (getTargetTriple().isMacOSX()) {
196  return !getTargetTriple().isMacOSXVersionLT(10, 9) && is64Bit();
197  } else if (getTargetTriple().isOSFuchsia()) {
198  return true;
199  }
200  return false;
201 }
202 
203 /// Return true if the subtarget allows calls to immediate address.
205  // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
206  // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
207  // the following check for Win32 should be removed.
208  if (In64BitMode || isTargetWin32())
209  return false;
211 }
212 
213 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
214  std::string CPUName = CPU;
215  if (CPUName.empty())
216  CPUName = "generic";
217 
218  // Make sure 64-bit features are available in 64-bit mode. (But make sure
219  // SSE2 can be turned off explicitly.)
220  std::string FullFS = FS;
221  if (In64BitMode) {
222  if (!FullFS.empty())
223  FullFS = "+64bit,+sse2," + FullFS;
224  else
225  FullFS = "+64bit,+sse2";
226  }
227 
228  // LAHF/SAHF are always supported in non-64-bit mode.
229  if (!In64BitMode) {
230  if (!FullFS.empty())
231  FullFS = "+sahf," + FullFS;
232  else
233  FullFS = "+sahf";
234  }
235 
236  // Parse features string and set the CPU.
237  ParseSubtargetFeatures(CPUName, FullFS);
238 
239  // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
240  // 16-bytes and under that are reasonably fast. These features were
241  // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
242  // micro-architectures respectively.
243  if (hasSSE42() || hasSSE4A())
244  IsUAMem16Slow = false;
245 
246  InstrItins = getInstrItineraryForCPU(CPUName);
247 
248  // It's important to keep the MCSubtargetInfo feature bits in sync with
249  // target data structure which is shared with MC code emitter, etc.
250  if (In64BitMode)
251  ToggleFeature(X86::Mode64Bit);
252  else if (In32BitMode)
253  ToggleFeature(X86::Mode32Bit);
254  else if (In16BitMode)
255  ToggleFeature(X86::Mode16Bit);
256  else
257  llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
258 
259  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
260  << ", 3DNowLevel " << X863DNowLevel
261  << ", 64bit " << HasX86_64 << "\n");
262  assert((!In64BitMode || HasX86_64) &&
263  "64-bit code requested on a subtarget that doesn't support it!");
264 
265  // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
266  // 32 and 64 bit) and for all 64-bit targets.
267  if (StackAlignOverride)
268  stackAlignment = StackAlignOverride;
269  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
270  isTargetKFreeBSD() || In64BitMode)
271  stackAlignment = 16;
272 
273  // Gather is available since Haswell (AVX2 set). So technically, we can
274  // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
275  // Skylake Client processor has faster Gathers than HSW and performance is
276  // similar to Skylake Server (AVX-512). The specified overhead is relative to
277  // the Load operation. "2" is the number provided by Intel architects. This
278  // parameter is used for cost estimation of Gather Op and comparison with
279  // other alternatives.
281  GatherOverhead = 2;
282  if (hasAVX512())
283  ScatterOverhead = 2;
284 }
285 
286 void X86Subtarget::initializeEnvironment() {
287  X86SSELevel = NoSSE;
289  HasX87 = false;
290  HasCMov = false;
291  HasX86_64 = false;
292  HasPOPCNT = false;
293  HasSSE4A = false;
294  HasAES = false;
295  HasFXSR = false;
296  HasXSAVE = false;
297  HasXSAVEOPT = false;
298  HasXSAVEC = false;
299  HasXSAVES = false;
300  HasPCLMUL = false;
301  HasFMA = false;
302  HasFMA4 = false;
303  HasXOP = false;
304  HasTBM = false;
305  HasLWP = false;
306  HasMOVBE = false;
307  HasRDRAND = false;
308  HasF16C = false;
309  HasFSGSBase = false;
310  HasLZCNT = false;
311  HasBMI = false;
312  HasBMI2 = false;
313  HasVBMI = false;
314  HasIFMA = false;
315  HasRTM = false;
316  HasERI = false;
317  HasCDI = false;
318  HasPFI = false;
319  HasDQI = false;
320  HasVPOPCNTDQ = false;
321  HasBWI = false;
322  HasVLX = false;
323  HasADX = false;
324  HasPKU = false;
325  HasSHA = false;
326  HasPRFCHW = false;
327  HasRDSEED = false;
328  HasLAHFSAHF = false;
329  HasMWAITX = false;
330  HasCLZERO = false;
331  HasMPX = false;
332  HasSGX = false;
333  HasCLFLUSHOPT = false;
334  HasCLWB = false;
335  IsPMULLDSlow = false;
336  IsSHLDSlow = false;
337  IsUAMem16Slow = false;
338  IsUAMem32Slow = false;
339  HasSSEUnalignedMem = false;
340  HasCmpxchg16b = false;
341  UseLeaForSP = false;
343  HasFastScalarFSQRT = false;
344  HasFastVectorFSQRT = false;
345  HasFastLZCNT = false;
346  HasFastSHLDRotate = false;
347  HasMacroFusion = false;
348  HasERMSB = false;
349  HasSlowDivide32 = false;
350  HasSlowDivide64 = false;
351  PadShortFunctions = false;
352  SlowTwoMemOps = false;
353  LEAUsesAG = false;
354  SlowLEA = false;
355  Slow3OpsLEA = false;
356  SlowIncDec = false;
357  stackAlignment = 4;
358  // FIXME: this is a known good value for Yonah. How about others?
360  UseSoftFloat = false;
362  GatherOverhead = 1024;
363  ScatterOverhead = 1024;
364 }
365 
366 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
367  StringRef FS) {
368  initializeEnvironment();
369  initSubtargetFeatures(CPU, FS);
370  return *this;
371 }
372 
374  const X86TargetMachine &TM,
375  unsigned StackAlignOverride)
376  : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
377  PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
378  StackAlignOverride(StackAlignOverride),
379  In64BitMode(TargetTriple.getArch() == Triple::x86_64),
380  In32BitMode(TargetTriple.getArch() == Triple::x86 &&
381  TargetTriple.getEnvironment() != Triple::CODE16),
382  In16BitMode(TargetTriple.getArch() == Triple::x86 &&
383  TargetTriple.getEnvironment() == Triple::CODE16),
384  InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
385  FrameLowering(*this, getStackAlignment()) {
386  // Determine the PICStyle based on the target selected.
387  if (!isPositionIndependent())
389  else if (is64Bit())
391  else if (isTargetCOFF())
393  else if (isTargetDarwin())
395  else if (isTargetELF())
397 
399  Legalizer.reset(new X86LegalizerInfo(*this, TM));
400 
401  auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
402  RegBankInfo.reset(RBI);
403  InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
404 }
405 
407  return CallLoweringInfo.get();
408 }
409 
411  return InstSelector.get();
412 }
413 
415  return Legalizer.get();
416 }
417 
419  return RegBankInfo.get();
420 }
421 
423  return hasCMov() && X86EarlyIfConv;
424 }
bool isDeclarationForLinker() const
Definition: GlobalValue.h:514
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:180
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:111
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:138
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:413
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:162
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:305
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:186
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:284
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:108
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:438
const TargetMachine & TM
Definition: X86Subtarget.h:83
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:281
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:322
bool HasERMSB
True if the processor has enhanced REP MOVSB/STOSB.
Definition: X86Subtarget.h:252
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:264
bool HasVPOPCNTDQ
Processor has AVX-512 population count Instructions.
Definition: X86Subtarget.h:287
const LegalizerInfo * getLegalizerInfo() const override
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:228
static cl::opt< bool > X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, cl::desc("Enable early if-conversion on X86"))
Optional< ConstantRange > getAbsoluteSymbolRange() const
If this is an absolute symbol reference, returns the range of the symbol, otherwise returns None...
Definition: Globals.cpp:272
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:208
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:253
bool HasLWP
Target has LWP instructions.
Definition: X86Subtarget.h:141
F(f)
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:107
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:202
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:147
bool HasFastPartialYMMorZMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register with...
Definition: X86Subtarget.h:224
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:311
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:129
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:232
Holds all the information related to register banks.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:207
bool isTargetSolaris() const
Definition: X86Subtarget.h:547
bool HasCLFLUSHOPT
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:308
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:102
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:299
This class provides the information for the target register banks.
const InstructionSelector * getInstructionSelector() const override
This file contains the simple types necessary to represent the attributes associated with functions a...
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:236
bool hasCommonLinkage() const
Definition: GlobalValue.h:431
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:278
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:331
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:92
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:168
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:216
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:230
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:92
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:220
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:89
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:202
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:105
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:156
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:150
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:275
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:367
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:555
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:189
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:388
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:174
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:293
bool HasFastSHLDRotate
True if SHLD based rotate is fast.
Definition: X86Subtarget.h:246
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:81
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:135
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:267
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:290
bool isPositionIndependent() const
Definition: X86Subtarget.h:603
bool hasCMov() const
Definition: X86Subtarget.h:441
bool enableEarlyIfConversion() const override
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:542
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:198
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:328
bool isTargetDarwin() const
Definition: X86Subtarget.h:544
bool hasSSE42() const
Definition: X86Subtarget.h:447
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:153
bool SlowTwoMemOps
True if two memory operand instructions should use a temporary register instead.
Definition: X86Subtarget.h:260
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:205
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This file declares the targeting of the RegisterBankInfo class for X86.
bool isTargetELF() const
Definition: X86Subtarget.h:550
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:381
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:334
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:302
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:78
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:99
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:212
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:123
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:177
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:159
bool isTargetWin32() const
Definition: X86Subtarget.h:594
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:165
InstructionSelector * createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &, X86RegisterBankInfo &)
bool Slow3OpsLEA
True if the LEA instruction has all three source operands: base, index, and offset or if the LEA inst...
Definition: X86Subtarget.h:272
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
CodeModel::Model getCodeModel() const
Returns the code model.
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:314
This file describes how to lower LLVM calls to machine code calls.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:333
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:126
Provides the logic to select generic machine instructions.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:99
This class provides the information for the target register banks.
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:117
bool HasMacroFusion
True if the processor supports macrofusion.
Definition: X86Subtarget.h:249
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:86
bool isTargetCOFF() const
Definition: X86Subtarget.h:551
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:114
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:427
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:114
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:96
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
bool isTargetLinux() const
Definition: X86Subtarget.h:554
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:132
This file describes how to lower LLVM calls to machine code calls.
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:171
This file declares the targeting of the Machinelegalizer class for X86.
bool hasAVX512() const
Definition: X86Subtarget.h:450
const RegisterBankInfo * getRegBankInfo() const override
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
#define DEBUG(X)
Definition: Debug.h:118
bool hasSSE4A() const
Definition: X86Subtarget.h:453
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:120
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:296
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:243
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:85
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:183
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:318
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:325
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:144
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:256
bool HasCLZERO
Processor has Cache Line Zero instruction.
Definition: X86Subtarget.h:192
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:197
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:240