LLVM  7.0.0svn
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1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/ConstantRange.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/Debug.h"
37 #if defined(_MSC_VER)
38 #include <intrin.h>
39 #endif
41 using namespace llvm;
43 #define DEBUG_TYPE "subtarget"
47 #include "X86GenSubtargetInfo.inc"
49 // Temporary option to control early if-conversion for x86 while adding machine
50 // models.
51 static cl::opt<bool>
52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
53  cl::desc("Enable early if-conversion on X86"));
56 /// Classify a blockaddress reference for the current subtarget according to how
57 /// we should reference it in a non-pcrel context.
59  return classifyLocalReference(nullptr);
60 }
62 /// Classify a global variable reference for the current subtarget according to
63 /// how we should reference it in a non-pcrel context.
64 unsigned char
66  return classifyGlobalReference(GV, *GV->getParent());
67 }
69 unsigned char
71  // 64 bits can use %rip addressing for anything local.
72  if (is64Bit())
73  return X86II::MO_NO_FLAG;
75  // If this is for a position dependent executable, the static linker can
76  // figure it out.
77  if (!isPositionIndependent())
78  return X86II::MO_NO_FLAG;
80  // The COFF dynamic linker just patches the executable sections.
81  if (isTargetCOFF())
82  return X86II::MO_NO_FLAG;
84  if (isTargetDarwin()) {
85  // 32 bit macho has no relocation for a-b if a is undefined, even if
86  // b is in the section that is being relocated.
87  // This means we have to use o load even for GVs that are known to be
88  // local to the dso.
89  if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
93  }
95  return X86II::MO_GOTOFF;
96 }
99  const Module &M) const {
100  // Large model never uses stubs.
102  return X86II::MO_NO_FLAG;
104  // Absolute symbols can be referenced directly.
105  if (GV) {
107  // See if we can use the 8-bit immediate form. Note that some instructions
108  // will sign extend the immediate operand, so to be conservative we only
109  // accept the range [0,128).
110  if (CR->getUnsignedMax().ult(128))
111  return X86II::MO_ABS8;
112  else
113  return X86II::MO_NO_FLAG;
114  }
115  }
117  if (TM.shouldAssumeDSOLocal(M, GV))
118  return classifyLocalReference(GV);
120  if (isTargetCOFF())
121  return X86II::MO_DLLIMPORT;
123  if (is64Bit())
124  return X86II::MO_GOTPCREL;
126  if (isTargetDarwin()) {
127  if (!isPositionIndependent())
130  }
132  return X86II::MO_GOT;
133 }
135 unsigned char
137  return classifyGlobalFunctionReference(GV, *GV->getParent());
138 }
140 unsigned char
142  const Module &M) const {
143  if (TM.shouldAssumeDSOLocal(M, GV))
144  return X86II::MO_NO_FLAG;
146  if (isTargetCOFF()) {
148  "shouldAssumeDSOLocal gave inconsistent answer");
149  return X86II::MO_DLLIMPORT;
150  }
152  const Function *F = dyn_cast_or_null<Function>(GV);
154  if (isTargetELF()) {
155  if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
156  // According to psABI, PLT stub clobbers XMM8-XMM15.
157  // In Regcall calling convention those registers are used for passing
158  // parameters. Thus we need to prevent lazy binding in Regcall.
159  return X86II::MO_GOTPCREL;
160  // If PLT must be avoided then the call should be via GOTPCREL.
161  if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
162  (!F && M.getRtLibUseGOT())) &&
163  is64Bit())
164  return X86II::MO_GOTPCREL;
165  return X86II::MO_PLT;
166  }
168  if (is64Bit()) {
169  if (F && F->hasFnAttribute(Attribute::NonLazyBind))
170  // If the function is marked as non-lazy, generate an indirect call
171  // which loads from the GOT directly. This avoids runtime overhead
172  // at the cost of eager binding (and one extra byte of encoding).
173  return X86II::MO_GOTPCREL;
174  return X86II::MO_NO_FLAG;
175  }
177  return X86II::MO_NO_FLAG;
178 }
180 /// Return true if the subtarget allows calls to immediate address.
182  // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
183  // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
184  // the following check for Win32 should be removed.
185  if (In64BitMode || isTargetWin32())
186  return false;
188 }
190 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
191  std::string CPUName = CPU;
192  if (CPUName.empty())
193  CPUName = "generic";
195  // Make sure 64-bit features are available in 64-bit mode. (But make sure
196  // SSE2 can be turned off explicitly.)
197  std::string FullFS = FS;
198  if (In64BitMode) {
199  if (!FullFS.empty())
200  FullFS = "+64bit,+sse2," + FullFS;
201  else
202  FullFS = "+64bit,+sse2";
203  }
205  // LAHF/SAHF are always supported in non-64-bit mode.
206  if (!In64BitMode) {
207  if (!FullFS.empty())
208  FullFS = "+sahf," + FullFS;
209  else
210  FullFS = "+sahf";
211  }
213  // Parse features string and set the CPU.
214  ParseSubtargetFeatures(CPUName, FullFS);
216  // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
217  // 16-bytes and under that are reasonably fast. These features were
218  // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
219  // micro-architectures respectively.
220  if (hasSSE42() || hasSSE4A())
221  IsUAMem16Slow = false;
223  InstrItins = getInstrItineraryForCPU(CPUName);
225  // It's important to keep the MCSubtargetInfo feature bits in sync with
226  // target data structure which is shared with MC code emitter, etc.
227  if (In64BitMode)
228  ToggleFeature(X86::Mode64Bit);
229  else if (In32BitMode)
230  ToggleFeature(X86::Mode32Bit);
231  else if (In16BitMode)
232  ToggleFeature(X86::Mode16Bit);
233  else
234  llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
236  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
237  << ", 3DNowLevel " << X863DNowLevel
238  << ", 64bit " << HasX86_64 << "\n");
239  assert((!In64BitMode || HasX86_64) &&
240  "64-bit code requested on a subtarget that doesn't support it!");
242  // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
243  // 32 and 64 bit) and for all 64-bit targets.
244  if (StackAlignOverride)
245  stackAlignment = StackAlignOverride;
246  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
247  isTargetKFreeBSD() || In64BitMode)
248  stackAlignment = 16;
250  // Some CPUs have more overhead for gather. The specified overhead is relative
251  // to the Load operation. "2" is the number provided by Intel architects. This
252  // parameter is used for cost estimation of Gather Op and comparison with
253  // other alternatives.
254  // TODO: Remove the explicit hasAVX512()?, That would mean we would only
255  // enable gather with a -march.
256  if (hasAVX512() || (hasAVX2() && hasFastGather()))
257  GatherOverhead = 2;
258  if (hasAVX512())
259  ScatterOverhead = 2;
261  // Consume the vector width attribute or apply any target specific limit.
262  if (PreferVectorWidthOverride)
263  PreferVectorWidth = PreferVectorWidthOverride;
264  else if (Prefer256Bit)
265  PreferVectorWidth = 256;
266 }
268 void X86Subtarget::initializeEnvironment() {
269  X86SSELevel = NoSSE;
271  HasX87 = false;
272  HasNOPL = false;
273  HasCMov = false;
274  HasX86_64 = false;
275  HasPOPCNT = false;
276  HasSSE4A = false;
277  HasAES = false;
278  HasVAES = false;
279  HasFXSR = false;
280  HasXSAVE = false;
281  HasXSAVEOPT = false;
282  HasXSAVEC = false;
283  HasXSAVES = false;
284  HasPCLMUL = false;
285  HasVPCLMULQDQ = false;
286  HasGFNI = false;
287  HasFMA = false;
288  HasFMA4 = false;
289  HasXOP = false;
290  HasTBM = false;
291  HasLWP = false;
292  HasMOVBE = false;
293  HasRDRAND = false;
294  HasF16C = false;
295  HasFSGSBase = false;
296  HasLZCNT = false;
297  HasBMI = false;
298  HasBMI2 = false;
299  HasVBMI = false;
300  HasVBMI2 = false;
301  HasIFMA = false;
302  HasRTM = false;
303  HasERI = false;
304  HasCDI = false;
305  HasPFI = false;
306  HasDQI = false;
307  HasVPOPCNTDQ = false;
308  HasBWI = false;
309  HasVLX = false;
310  HasADX = false;
311  HasPKU = false;
312  HasVNNI = false;
313  HasBITALG = false;
314  HasSHA = false;
315  HasPREFETCHWT1 = false;
316  HasPRFCHW = false;
317  HasRDSEED = false;
318  HasLAHFSAHF = false;
319  HasMWAITX = false;
320  HasCLZERO = false;
321  HasMPX = false;
322  HasSHSTK = false;
323  HasIBT = false;
324  HasSGX = false;
325  HasCLFLUSHOPT = false;
326  HasCLWB = false;
327  HasRDPID = false;
328  UseRetpoline = false;
330  IsPMULLDSlow = false;
331  IsSHLDSlow = false;
332  IsUAMem16Slow = false;
333  IsUAMem32Slow = false;
334  HasSSEUnalignedMem = false;
335  HasCmpxchg16b = false;
336  UseLeaForSP = false;
337  HasPOPCNTFalseDeps = false;
338  HasLZCNTFalseDeps = false;
339  HasFastVariableShuffle = false;
341  HasFast11ByteNOP = false;
342  HasFast15ByteNOP = false;
343  HasFastGather = false;
344  HasFastScalarFSQRT = false;
345  HasFastVectorFSQRT = false;
346  HasFastLZCNT = false;
347  HasFastSHLDRotate = false;
348  HasMacroFusion = false;
349  HasERMSB = false;
350  HasSlowDivide32 = false;
351  HasSlowDivide64 = false;
352  PadShortFunctions = false;
353  SlowTwoMemOps = false;
354  LEAUsesAG = false;
355  SlowLEA = false;
356  Slow3OpsLEA = false;
357  SlowIncDec = false;
358  stackAlignment = 4;
359  // FIXME: this is a known good value for Yonah. How about others?
361  UseSoftFloat = false;
363  GatherOverhead = 1024;
364  ScatterOverhead = 1024;
365  PreferVectorWidth = UINT32_MAX;
366  Prefer256Bit = false;
367 }
369 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
370  StringRef FS) {
371  initializeEnvironment();
372  initSubtargetFeatures(CPU, FS);
373  return *this;
374 }
377  const X86TargetMachine &TM,
378  unsigned StackAlignOverride,
379  unsigned PreferVectorWidthOverride,
380  unsigned RequiredVectorWidth)
381  : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
382  PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
383  StackAlignOverride(StackAlignOverride),
384  PreferVectorWidthOverride(PreferVectorWidthOverride),
385  RequiredVectorWidth(RequiredVectorWidth),
386  In64BitMode(TargetTriple.getArch() == Triple::x86_64),
387  In32BitMode(TargetTriple.getArch() == Triple::x86 &&
388  TargetTriple.getEnvironment() != Triple::CODE16),
389  In16BitMode(TargetTriple.getArch() == Triple::x86 &&
390  TargetTriple.getEnvironment() == Triple::CODE16),
391  InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
392  FrameLowering(*this, getStackAlignment()) {
393  // Determine the PICStyle based on the target selected.
394  if (!isPositionIndependent())
396  else if (is64Bit())
398  else if (isTargetCOFF())
400  else if (isTargetDarwin())
402  else if (isTargetELF())
406  Legalizer.reset(new X86LegalizerInfo(*this, TM));
408  auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
409  RegBankInfo.reset(RBI);
410  InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
411 }
414  return CallLoweringInfo.get();
415 }
418  return InstSelector.get();
419 }
422  return Legalizer.get();
423 }
426  return RegBankInfo.get();
427 }
430  return hasCMov() && X86EarlyIfConv;
431 }
bool isDeclarationForLinker() const
Definition: GlobalValue.h:523
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:193
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:117
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:148
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:488
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:172
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:354
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
bool HasPOPCNTFalseDeps
True if POPCNT instruction has a false dependency on the destination register.
Definition: X86Subtarget.h:236
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasAVX2() const
Definition: X86Subtarget.h:525
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:199
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:319
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:113
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:513
const TargetMachine & TM
Definition: X86Subtarget.h:84
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:316
unsigned MaxInlineSizeThreshold
Definition: X86Subtarget.h:382
bool HasERMSB
True if the processor has enhanced REP MOVSB/STOSB.
Definition: X86Subtarget.h:287
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:299
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
Processor has AVX-512 population count Instructions.
Definition: X86Subtarget.h:322
const LegalizerInfo * getLegalizerInfo() const override
bool HasFastGather
True if gather is reasonably fast.
Definition: X86Subtarget.h:259
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:263
static cl::opt< bool > X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, cl::desc("Enable early if-conversion on X86"))
Optional< ConstantRange > getAbsoluteSymbolRange() const
If this is an absolute symbol reference, returns the range of the symbol, otherwise returns None...
Definition: Globals.cpp:272
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:221
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:261
bool HasLWP
Target has LWP instructions.
Definition: X86Subtarget.h:151
bool HasFast15ByteNOP
True if there is no performance penalty for writing NOPs with up to 15 bytes.
Definition: X86Subtarget.h:255
Processor has Prefetch with intent to Write instruction.
Definition: X86Subtarget.h:208
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:110
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:215
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:157
bool HasFastPartialYMMorZMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM or ZMM register with...
Definition: X86Subtarget.h:247
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:360
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:139
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:267
Holds all the information related to register banks.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:210
bool HasGFNI
Target has Galois Field Arithmetic instructions.
Definition: X86Subtarget.h:136
bool HasVBMI2
Processor has VBMI2 instructions.
Definition: X86Subtarget.h:178
bool isTargetSolaris() const
Definition: X86Subtarget.h:670
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:357
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:107
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:334
This class provides the information for the target register banks.
bool HasBITALG
Processor has AVX-512 Bit Algorithms instructions.
Definition: X86Subtarget.h:340
const InstructionSelector * getInstructionSelector() const override
This file contains the simple types necessary to represent the attributes associated with functions a...
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:271
bool HasSHSTK
Processor supports CET SHSTK - Control-Flow Enforcement Technology using Shadow Stack.
Definition: X86Subtarget.h:347
bool HasFast11ByteNOP
True if there is no performance penalty for writing NOPs with up to 11 bytes.
Definition: X86Subtarget.h:251
bool hasCommonLinkage() const
Definition: GlobalValue.h:439
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:313
bool Prefer256Bit
Indicates target prefers 256 bit instructions.
Definition: X86Subtarget.h:385
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: X86Subtarget.h:394
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:95
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:181
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:229
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:233
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:93
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:233
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:90
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride, unsigned PreferVectorWidthOverride, unsigned RequiredVectorWidth)
This constructor initializes the data members to match that of the specified triple.
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:205
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:110
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:166
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:160
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:310
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:442
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:678
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:202
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:463
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:187
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:328
bool HasFastSHLDRotate
True if SHLD based rotate is fast.
Definition: X86Subtarget.h:281
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:82
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:145
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:302
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:325
bool isPositionIndependent() const
Definition: X86Subtarget.h:726
bool hasCMov() const
Definition: X86Subtarget.h:517
bool enableEarlyIfConversion() const override
bool UseRetpoline
Use a retpoline thunk rather than indirect calls to block speculative execution.
Definition: X86Subtarget.h:367
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:211
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:391
bool isTargetDarwin() const
Definition: X86Subtarget.h:667
bool hasSSE42() const
Definition: X86Subtarget.h:523
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:163
bool SlowTwoMemOps
True if two memory operand instructions should use a temporary register instead.
Definition: X86Subtarget.h:295
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:218
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This file declares the targeting of the RegisterBankInfo class for X86.
bool isTargetELF() const
Definition: X86Subtarget.h:673
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:456
std::unique_ptr< InstructionSelector > InstSelector
Definition: X86Subtarget.h:397
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:343
bool HasLZCNTFalseDeps
True if LZCNT/TZCNT instructions have a false dependency on the destination register.
Definition: X86Subtarget.h:239
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:79
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:104
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:225
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:129
bool UseRetpolineExternalThunk
When using a retpoline thunk, call an externally provided thunk rather than emitting one inside the c...
Definition: X86Subtarget.h:371
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:190
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:169
bool HasNOPL
True if this processor has NOPL instruction (generally pentium pro+).
Definition: X86Subtarget.h:97
bool isTargetWin32() const
Definition: X86Subtarget.h:717
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:175
InstructionSelector * createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &, X86RegisterBankInfo &)
bool Slow3OpsLEA
True if the LEA instruction has all three source operands: base, index, and offset or if the LEA inst...
Definition: X86Subtarget.h:307
bool HasRDPID
Processor support RDPID instruction.
Definition: X86Subtarget.h:363
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
CodeModel::Model getCodeModel() const
Returns the code model.
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:374
This file describes how to lower LLVM calls to machine code calls.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: X86Subtarget.h:396
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Definition: Module.cpp:513
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:132
bool HasIBT
Processor supports CET IBT - Control-Flow Enforcement Technology using Indirect Branch Tracking...
Definition: X86Subtarget.h:351
Provides the logic to select generic machine instructions.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:102
This class provides the information for the target register banks.
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:123
bool HasFastVariableShuffle
True if its preferable to combine to a single shuffle using a variable mask over multiple fixed shuff...
Definition: X86Subtarget.h:243
bool HasMacroFusion
True if the processor supports macrofusion.
Definition: X86Subtarget.h:284
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:87
bool isTargetCOFF() const
Definition: X86Subtarget.h:674
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:120
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:117
bool HasVNNI
Processor has AVX-512 Vector Neural Network Instructions.
Definition: X86Subtarget.h:337
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:101
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
bool isTargetLinux() const
Definition: X86Subtarget.h:677
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:142
This file describes how to lower LLVM calls to machine code calls.
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:184
This file declares the targeting of the Machinelegalizer class for X86.
bool hasAVX512() const
Definition: X86Subtarget.h:526
const RegisterBankInfo * getRegBankInfo() const override
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
#define DEBUG(X)
Definition: Debug.h:118
bool hasSSE4A() const
Definition: X86Subtarget.h:528
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:126
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:331
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:278
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:88
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:196
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:378
bool hasFastGather() const
Definition: X86Subtarget.h:593
Triple TargetTriple
What processor and OS we&#39;re targeting.
Definition: X86Subtarget.h:388
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:154
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:291
bool HasCLZERO
Processor has Cache Line Zero instruction.
Definition: X86Subtarget.h:205
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:200
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:275