LLVM  9.0.0svn
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/Debug.h"
33 #include <cstdlib>
34 
35 using namespace llvm;
36 
38  unsigned StackAlignOverride)
39  : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40  STI.is64Bit() ? -8 : -4),
41  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42  // Cache a bunch of frame-related predicates for this subtarget.
44  Is64Bit = STI.is64Bit();
45  IsLP64 = STI.isTarget64BitLP64();
46  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
49 }
50 
52  return !MF.getFrameInfo().hasVarSizedObjects() &&
53  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
54 }
55 
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
60 bool
62  return hasReservedCallFrame(MF) ||
63  (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64  TRI->hasBasePointer(MF);
65 }
66 
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
74 bool
76  return MF.getFrameInfo().hasStackObjects() ||
77  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
78 }
79 
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
84  const MachineFrameInfo &MFI = MF.getFrameInfo();
85  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
86  TRI->needsStackRealignment(MF) ||
87  MFI.hasVarSizedObjects() ||
89  MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
90  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
91  MFI.hasStackMap() || MFI.hasPatchPoint() ||
93 }
94 
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
96  if (IsLP64) {
97  if (isInt<8>(Imm))
98  return X86::SUB64ri8;
99  return X86::SUB64ri32;
100  } else {
101  if (isInt<8>(Imm))
102  return X86::SUB32ri8;
103  return X86::SUB32ri;
104  }
105 }
106 
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
108  if (IsLP64) {
109  if (isInt<8>(Imm))
110  return X86::ADD64ri8;
111  return X86::ADD64ri32;
112  } else {
113  if (isInt<8>(Imm))
114  return X86::ADD32ri8;
115  return X86::ADD32ri;
116  }
117 }
118 
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120  return isLP64 ? X86::SUB64rr : X86::SUB32rr;
121 }
122 
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124  return isLP64 ? X86::ADD64rr : X86::ADD32rr;
125 }
126 
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
128  if (IsLP64) {
129  if (isInt<8>(Imm))
130  return X86::AND64ri8;
131  return X86::AND64ri32;
132  }
133  if (isInt<8>(Imm))
134  return X86::AND32ri8;
135  return X86::AND32ri;
136 }
137 
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139  return IsLP64 ? X86::LEA64r : X86::LEA32r;
140 }
141 
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
147  const X86RegisterInfo *TRI,
148  bool Is64Bit) {
149  const MachineFunction *MF = MBB.getParent();
150  if (MF->callsEHReturn())
151  return 0;
152 
153  const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
154 
155  if (MBBI == MBB.end())
156  return 0;
157 
158  switch (MBBI->getOpcode()) {
159  default: return 0;
160  case TargetOpcode::PATCHABLE_RET:
161  case X86::RET:
162  case X86::RETL:
163  case X86::RETQ:
164  case X86::RETIL:
165  case X86::RETIQ:
166  case X86::TCRETURNdi:
167  case X86::TCRETURNri:
168  case X86::TCRETURNmi:
169  case X86::TCRETURNdi64:
170  case X86::TCRETURNri64:
171  case X86::TCRETURNmi64:
172  case X86::EH_RETURN:
173  case X86::EH_RETURN64: {
175  for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
176  MachineOperand &MO = MBBI->getOperand(i);
177  if (!MO.isReg() || MO.isDef())
178  continue;
179  unsigned Reg = MO.getReg();
180  if (!Reg)
181  continue;
182  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
183  Uses.insert(*AI);
184  }
185 
186  for (auto CS : AvailableRegs)
187  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
188  CS != X86::ESP)
189  return CS;
190  }
191  }
192 
193  return 0;
194 }
195 
196 static bool isEAXLiveIn(MachineBasicBlock &MBB) {
197  for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
198  unsigned Reg = RegMask.PhysReg;
199 
200  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
201  Reg == X86::AH || Reg == X86::AL)
202  return true;
203  }
204 
205  return false;
206 }
207 
208 /// Check if the flags need to be preserved before the terminators.
209 /// This would be the case, if the eflags is live-in of the region
210 /// composed by the terminators or live-out of that region, without
211 /// being defined by a terminator.
212 static bool
214  for (const MachineInstr &MI : MBB.terminators()) {
215  bool BreakNext = false;
216  for (const MachineOperand &MO : MI.operands()) {
217  if (!MO.isReg())
218  continue;
219  unsigned Reg = MO.getReg();
220  if (Reg != X86::EFLAGS)
221  continue;
222 
223  // This terminator needs an eflags that is not defined
224  // by a previous another terminator:
225  // EFLAGS is live-in of the region composed by the terminators.
226  if (!MO.isDef())
227  return true;
228  // This terminator defines the eflags, i.e., we don't need to preserve it.
229  // However, we still need to check this specific terminator does not
230  // read a live-in value.
231  BreakNext = true;
232  }
233  // We found a definition of the eflags, no need to preserve them.
234  if (BreakNext)
235  return false;
236  }
237 
238  // None of the terminators use or define the eflags.
239  // Check if they are live-out, that would imply we need to preserve them.
240  for (const MachineBasicBlock *Succ : MBB.successors())
241  if (Succ->isLiveIn(X86::EFLAGS))
242  return true;
243 
244  return false;
245 }
246 
247 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
248 /// stack pointer by a constant value.
251  const DebugLoc &DL,
252  int64_t NumBytes, bool InEpilogue) const {
253  bool isSub = NumBytes < 0;
254  uint64_t Offset = isSub ? -NumBytes : NumBytes;
257 
258  uint64_t Chunk = (1LL << 31) - 1;
259 
260  if (Offset > Chunk) {
261  // Rather than emit a long series of instructions for large offsets,
262  // load the offset into a register and do one sub/add
263  unsigned Reg = 0;
264  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
265 
266  if (isSub && !isEAXLiveIn(MBB))
267  Reg = Rax;
268  else
269  Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
270 
271  unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
272  unsigned AddSubRROpc =
274  if (Reg) {
275  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
276  .addImm(Offset)
277  .setMIFlag(Flag);
278  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
279  .addReg(StackPtr)
280  .addReg(Reg);
281  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
282  return;
283  } else if (Offset > 8 * Chunk) {
284  // If we would need more than 8 add or sub instructions (a >16GB stack
285  // frame), it's worth spilling RAX to materialize this immediate.
286  // pushq %rax
287  // movabsq +-$Offset+-SlotSize, %rax
288  // addq %rsp, %rax
289  // xchg %rax, (%rsp)
290  // movq (%rsp), %rsp
291  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
292  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
293  .addReg(Rax, RegState::Kill)
294  .setMIFlag(Flag);
295  // Subtract is not commutative, so negate the offset and always use add.
296  // Subtract 8 less and add 8 more to account for the PUSH we just did.
297  if (isSub)
298  Offset = -(Offset - SlotSize);
299  else
300  Offset = Offset + SlotSize;
301  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
302  .addImm(Offset)
303  .setMIFlag(Flag);
304  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
305  .addReg(Rax)
306  .addReg(StackPtr);
307  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
308  // Exchange the new SP in RAX with the top of the stack.
309  addRegOffset(
310  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
311  StackPtr, false, 0);
312  // Load new SP from the top of the stack into RSP.
313  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
314  StackPtr, false, 0);
315  return;
316  }
317  }
318 
319  while (Offset) {
320  uint64_t ThisVal = std::min(Offset, Chunk);
321  if (ThisVal == SlotSize) {
322  // Use push / pop for slot sized adjustments as a size optimization. We
323  // need to find a dead register when using pop.
324  unsigned Reg = isSub
325  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
326  : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
327  if (Reg) {
328  unsigned Opc = isSub
329  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
330  : (Is64Bit ? X86::POP64r : X86::POP32r);
331  BuildMI(MBB, MBBI, DL, TII.get(Opc))
332  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
333  .setMIFlag(Flag);
334  Offset -= ThisVal;
335  continue;
336  }
337  }
338 
339  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
340  .setMIFlag(Flag);
341 
342  Offset -= ThisVal;
343  }
344 }
345 
346 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
348  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
349  assert(Offset != 0 && "zero offset stack adjustment requested");
350 
351  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
352  // is tricky.
353  bool UseLEA;
354  if (!InEpilogue) {
355  // Check if inserting the prologue at the beginning
356  // of MBB would require to use LEA operations.
357  // We need to use LEA operations if EFLAGS is live in, because
358  // it means an instruction will read it before it gets defined.
359  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
360  } else {
361  // If we can use LEA for SP but we shouldn't, check that none
362  // of the terminators uses the eflags. Otherwise we will insert
363  // a ADD that will redefine the eflags and break the condition.
364  // Alternatively, we could move the ADD, but this may not be possible
365  // and is an optimization anyway.
366  UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
367  if (UseLEA && !STI.useLeaForSP())
369  // If that assert breaks, that means we do not do the right thing
370  // in canUseAsEpilogue.
372  "We shouldn't have allowed this insertion point");
373  }
374 
376  if (UseLEA) {
377  MI = addRegOffset(BuildMI(MBB, MBBI, DL,
379  StackPtr),
380  StackPtr, false, Offset);
381  } else {
382  bool IsSub = Offset < 0;
383  uint64_t AbsOffset = IsSub ? -Offset : Offset;
384  unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
385  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
386  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
387  .addReg(StackPtr)
388  .addImm(AbsOffset);
389  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
390  }
391  return MI;
392 }
393 
396  bool doMergeWithPrevious) const {
397  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
398  (!doMergeWithPrevious && MBBI == MBB.end()))
399  return 0;
400 
401  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
402 
403  PI = skipDebugInstructionsBackward(PI, MBB.begin());
404  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
405  // instruction, and that there are no DBG_VALUE or other instructions between
406  // ADD/SUB/LEA and its corresponding CFI instruction.
407  /* TODO: Add support for the case where there are multiple CFI instructions
408  below the ADD/SUB/LEA, e.g.:
409  ...
410  add
411  cfi_def_cfa_offset
412  cfi_offset
413  ...
414  */
415  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
416  PI = std::prev(PI);
417 
418  unsigned Opc = PI->getOpcode();
419  int Offset = 0;
420 
421  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
422  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
423  PI->getOperand(0).getReg() == StackPtr){
424  assert(PI->getOperand(1).getReg() == StackPtr);
425  Offset = PI->getOperand(2).getImm();
426  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
427  PI->getOperand(0).getReg() == StackPtr &&
428  PI->getOperand(1).getReg() == StackPtr &&
429  PI->getOperand(2).getImm() == 1 &&
430  PI->getOperand(3).getReg() == X86::NoRegister &&
431  PI->getOperand(5).getReg() == X86::NoRegister) {
432  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
433  Offset = PI->getOperand(4).getImm();
434  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
435  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
436  PI->getOperand(0).getReg() == StackPtr) {
437  assert(PI->getOperand(1).getReg() == StackPtr);
438  Offset = -PI->getOperand(2).getImm();
439  } else
440  return 0;
441 
442  PI = MBB.erase(PI);
443  if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
444  if (!doMergeWithPrevious)
445  MBBI = skipDebugInstructionsForward(PI, MBB.end());
446 
447  return Offset;
448 }
449 
452  const DebugLoc &DL,
453  const MCCFIInstruction &CFIInst) const {
454  MachineFunction &MF = *MBB.getParent();
455  unsigned CFIIndex = MF.addFrameInst(CFIInst);
456  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
457  .addCFIIndex(CFIIndex);
458 }
459 
462  const DebugLoc &DL) const {
463  MachineFunction &MF = *MBB.getParent();
464  MachineFrameInfo &MFI = MF.getFrameInfo();
465  MachineModuleInfo &MMI = MF.getMMI();
466  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
467 
468  // Add callee saved registers to move list.
469  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
470  if (CSI.empty()) return;
471 
472  // Calculate offsets.
473  for (std::vector<CalleeSavedInfo>::const_iterator
474  I = CSI.begin(), E = CSI.end(); I != E; ++I) {
475  int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
476  unsigned Reg = I->getReg();
477 
478  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
479  BuildCFI(MBB, MBBI, DL,
480  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
481  }
482 }
483 
485  MachineBasicBlock &MBB,
487  const DebugLoc &DL, bool InProlog) const {
488  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
489  if (STI.isTargetWindowsCoreCLR()) {
490  if (InProlog) {
491  emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
492  } else {
493  emitStackProbeInline(MF, MBB, MBBI, DL, false);
494  }
495  } else {
496  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
497  }
498 }
499 
501  MachineBasicBlock &PrologMBB) const {
502  const StringRef ChkStkStubSymbol = "__chkstk_stub";
503  MachineInstr *ChkStkStub = nullptr;
504 
505  for (MachineInstr &MI : PrologMBB) {
506  if (MI.isCall() && MI.getOperand(0).isSymbol() &&
507  ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
508  ChkStkStub = &MI;
509  break;
510  }
511  }
512 
513  if (ChkStkStub != nullptr) {
514  assert(!ChkStkStub->isBundled() &&
515  "Not expecting bundled instructions here");
516  MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
517  assert(std::prev(MBBI) == ChkStkStub &&
518  "MBBI expected after __chkstk_stub.");
519  DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
520  emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
521  ChkStkStub->eraseFromParent();
522  }
523 }
524 
525 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
526  MachineBasicBlock &MBB,
528  const DebugLoc &DL,
529  bool InProlog) const {
530  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
531  assert(STI.is64Bit() && "different expansion needed for 32 bit");
532  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
533  const TargetInstrInfo &TII = *STI.getInstrInfo();
534  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
535 
536  // RAX contains the number of bytes of desired stack adjustment.
537  // The handling here assumes this value has already been updated so as to
538  // maintain stack alignment.
539  //
540  // We need to exit with RSP modified by this amount and execute suitable
541  // page touches to notify the OS that we're growing the stack responsibly.
542  // All stack probing must be done without modifying RSP.
543  //
544  // MBB:
545  // SizeReg = RAX;
546  // ZeroReg = 0
547  // CopyReg = RSP
548  // Flags, TestReg = CopyReg - SizeReg
549  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
550  // LimitReg = gs magic thread env access
551  // if FinalReg >= LimitReg goto ContinueMBB
552  // RoundBB:
553  // RoundReg = page address of FinalReg
554  // LoopMBB:
555  // LoopReg = PHI(LimitReg,ProbeReg)
556  // ProbeReg = LoopReg - PageSize
557  // [ProbeReg] = 0
558  // if (ProbeReg > RoundReg) goto LoopMBB
559  // ContinueMBB:
560  // RSP = RSP - RAX
561  // [rest of original MBB]
562 
563  // Set up the new basic blocks
564  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
565  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
566  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
567 
568  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
569  MF.insert(MBBIter, RoundMBB);
570  MF.insert(MBBIter, LoopMBB);
571  MF.insert(MBBIter, ContinueMBB);
572 
573  // Split MBB and move the tail portion down to ContinueMBB.
574  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
575  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
576  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
577 
578  // Some useful constants
579  const int64_t ThreadEnvironmentStackLimit = 0x10;
580  const int64_t PageSize = 0x1000;
581  const int64_t PageMask = ~(PageSize - 1);
582 
583  // Registers we need. For the normal case we use virtual
584  // registers. For the prolog expansion we use RAX, RCX and RDX.
586  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
587  const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
588  : MRI.createVirtualRegister(RegClass),
589  ZeroReg = InProlog ? (unsigned)X86::RCX
590  : MRI.createVirtualRegister(RegClass),
591  CopyReg = InProlog ? (unsigned)X86::RDX
592  : MRI.createVirtualRegister(RegClass),
593  TestReg = InProlog ? (unsigned)X86::RDX
594  : MRI.createVirtualRegister(RegClass),
595  FinalReg = InProlog ? (unsigned)X86::RDX
596  : MRI.createVirtualRegister(RegClass),
597  RoundedReg = InProlog ? (unsigned)X86::RDX
598  : MRI.createVirtualRegister(RegClass),
599  LimitReg = InProlog ? (unsigned)X86::RCX
600  : MRI.createVirtualRegister(RegClass),
601  JoinReg = InProlog ? (unsigned)X86::RCX
602  : MRI.createVirtualRegister(RegClass),
603  ProbeReg = InProlog ? (unsigned)X86::RCX
604  : MRI.createVirtualRegister(RegClass);
605 
606  // SP-relative offsets where we can save RCX and RDX.
607  int64_t RCXShadowSlot = 0;
608  int64_t RDXShadowSlot = 0;
609 
610  // If inlining in the prolog, save RCX and RDX.
611  if (InProlog) {
612  // Compute the offsets. We need to account for things already
613  // pushed onto the stack at this point: return address, frame
614  // pointer (if used), and callee saves.
616  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
617  const bool HasFP = hasFP(MF);
618 
619  // Check if we need to spill RCX and/or RDX.
620  // Here we assume that no earlier prologue instruction changes RCX and/or
621  // RDX, so checking the block live-ins is enough.
622  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
623  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
624  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
625  // Assign the initial slot to both registers, then change RDX's slot if both
626  // need to be spilled.
627  if (IsRCXLiveIn)
628  RCXShadowSlot = InitSlot;
629  if (IsRDXLiveIn)
630  RDXShadowSlot = InitSlot;
631  if (IsRDXLiveIn && IsRCXLiveIn)
632  RDXShadowSlot += 8;
633  // Emit the saves if needed.
634  if (IsRCXLiveIn)
635  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
636  RCXShadowSlot)
637  .addReg(X86::RCX);
638  if (IsRDXLiveIn)
639  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
640  RDXShadowSlot)
641  .addReg(X86::RDX);
642  } else {
643  // Not in the prolog. Copy RAX to a virtual reg.
644  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
645  }
646 
647  // Add code to MBB to check for overflow and set the new target stack pointer
648  // to zero if so.
649  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
650  .addReg(ZeroReg, RegState::Undef)
651  .addReg(ZeroReg, RegState::Undef);
652  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
653  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
654  .addReg(CopyReg)
655  .addReg(SizeReg);
656  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
657  .addReg(TestReg)
658  .addReg(ZeroReg)
660 
661  // FinalReg now holds final stack pointer value, or zero if
662  // allocation would overflow. Compare against the current stack
663  // limit from the thread environment block. Note this limit is the
664  // lowest touched page on the stack, not the point at which the OS
665  // will cause an overflow exception, so this is just an optimization
666  // to avoid unnecessarily touching pages that are below the current
667  // SP but already committed to the stack by the OS.
668  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
669  .addReg(0)
670  .addImm(1)
671  .addReg(0)
672  .addImm(ThreadEnvironmentStackLimit)
673  .addReg(X86::GS);
674  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
675  // Jump if the desired stack pointer is at or above the stack limit.
676  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
677 
678  // Add code to roundMBB to round the final stack pointer to a page boundary.
679  RoundMBB->addLiveIn(FinalReg);
680  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
681  .addReg(FinalReg)
682  .addImm(PageMask);
683  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
684 
685  // LimitReg now holds the current stack limit, RoundedReg page-rounded
686  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
687  // and probe until we reach RoundedReg.
688  if (!InProlog) {
689  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
690  .addReg(LimitReg)
691  .addMBB(RoundMBB)
692  .addReg(ProbeReg)
693  .addMBB(LoopMBB);
694  }
695 
696  LoopMBB->addLiveIn(JoinReg);
697  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
698  false, -PageSize);
699 
700  // Probe by storing a byte onto the stack.
701  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
702  .addReg(ProbeReg)
703  .addImm(1)
704  .addReg(0)
705  .addImm(0)
706  .addReg(0)
707  .addImm(0);
708 
709  LoopMBB->addLiveIn(RoundedReg);
710  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
711  .addReg(RoundedReg)
712  .addReg(ProbeReg);
713  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
714 
715  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
716 
717  // If in prolog, restore RDX and RCX.
718  if (InProlog) {
719  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
720  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
721  TII.get(X86::MOV64rm), X86::RCX),
722  X86::RSP, false, RCXShadowSlot);
723  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
724  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
725  TII.get(X86::MOV64rm), X86::RDX),
726  X86::RSP, false, RDXShadowSlot);
727  }
728 
729  // Now that the probing is done, add code to continueMBB to update
730  // the stack pointer for real.
731  ContinueMBB->addLiveIn(SizeReg);
732  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
733  .addReg(X86::RSP)
734  .addReg(SizeReg);
735 
736  // Add the control flow edges we need.
737  MBB.addSuccessor(ContinueMBB);
738  MBB.addSuccessor(RoundMBB);
739  RoundMBB->addSuccessor(LoopMBB);
740  LoopMBB->addSuccessor(ContinueMBB);
741  LoopMBB->addSuccessor(LoopMBB);
742 
743  // Mark all the instructions added to the prolog as frame setup.
744  if (InProlog) {
745  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
746  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
747  }
748  for (MachineInstr &MI : *RoundMBB) {
749  MI.setFlag(MachineInstr::FrameSetup);
750  }
751  for (MachineInstr &MI : *LoopMBB) {
752  MI.setFlag(MachineInstr::FrameSetup);
753  }
754  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
755  CMBBI != ContinueMBBI; ++CMBBI) {
756  CMBBI->setFlag(MachineInstr::FrameSetup);
757  }
758  }
759 }
760 
761 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
762  MachineBasicBlock &MBB,
764  const DebugLoc &DL,
765  bool InProlog) const {
766  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
767 
768  // FIXME: Add retpoline support and remove this.
769  if (Is64Bit && IsLargeCodeModel && STI.useRetpolineIndirectCalls())
770  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
771  "code model and retpoline not yet implemented.");
772 
773  unsigned CallOp;
774  if (Is64Bit)
775  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
776  else
777  CallOp = X86::CALLpcrel32;
778 
780 
782  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
783 
784  // All current stack probes take AX and SP as input, clobber flags, and
785  // preserve all registers. x86_64 probes leave RSP unmodified.
786  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
787  // For the large code model, we have to call through a register. Use R11,
788  // as it is scratch in all supported calling conventions.
789  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
790  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
791  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
792  } else {
793  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
794  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
795  }
796 
797  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
798  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
799  CI.addReg(AX, RegState::Implicit)
803  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
804 
805  if (STI.isTargetWin64() || !STI.isOSWindows()) {
806  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
807  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
808  // themselves. They also does not clobber %rax so we can reuse it when
809  // adjusting %rsp.
810  // All other platforms do not specify a particular ABI for the stack probe
811  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
812  BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
813  .addReg(SP)
814  .addReg(AX);
815  }
816 
817  if (InProlog) {
818  // Apply the frame setup flag to all inserted instrs.
819  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
820  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
821  }
822 }
823 
824 void X86FrameLowering::emitStackProbeInlineStub(
826  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
827 
828  assert(InProlog && "ChkStkStub called outside prolog!");
829 
830  BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
831  .addExternalSymbol("__chkstk_stub");
832 }
833 
834 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
835  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
836  // and might require smaller successive adjustments.
837  const uint64_t Win64MaxSEHOffset = 128;
838  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
839  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
840  return SEHFrameOffset & -16;
841 }
842 
843 // If we're forcing a stack realignment we can't rely on just the frame
844 // info, we need to know the ABI stack alignment as well in case we
845 // have a call out. Otherwise just make sure we have some alignment - we'll
846 // go with the minimum SlotSize.
847 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
848  const MachineFrameInfo &MFI = MF.getFrameInfo();
849  uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
850  unsigned StackAlign = getStackAlignment();
851  if (MF.getFunction().hasFnAttribute("stackrealign")) {
852  if (MFI.hasCalls())
853  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
854  else if (MaxAlign < SlotSize)
855  MaxAlign = SlotSize;
856  }
857  return MaxAlign;
858 }
859 
860 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
862  const DebugLoc &DL, unsigned Reg,
863  uint64_t MaxAlign) const {
864  uint64_t Val = -MaxAlign;
865  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
866  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
867  .addReg(Reg)
868  .addImm(Val)
870 
871  // The EFLAGS implicit def is dead.
872  MI->getOperand(3).setIsDead();
873 }
874 
875 /// emitPrologue - Push callee-saved registers onto the stack, which
876 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
877 /// space for local variables. Also emit labels used by the exception handler to
878 /// generate the exception handling frames.
879 
880 /*
881  Here's a gist of what gets emitted:
882 
883  ; Establish frame pointer, if needed
884  [if needs FP]
885  push %rbp
886  .cfi_def_cfa_offset 16
887  .cfi_offset %rbp, -16
888  .seh_pushreg %rpb
889  mov %rsp, %rbp
890  .cfi_def_cfa_register %rbp
891 
892  ; Spill general-purpose registers
893  [for all callee-saved GPRs]
894  pushq %<reg>
895  [if not needs FP]
896  .cfi_def_cfa_offset (offset from RETADDR)
897  .seh_pushreg %<reg>
898 
899  ; If the required stack alignment > default stack alignment
900  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
901  ; of unknown size in the stack frame.
902  [if stack needs re-alignment]
903  and $MASK, %rsp
904 
905  ; Allocate space for locals
906  [if target is Windows and allocated space > 4096 bytes]
907  ; Windows needs special care for allocations larger
908  ; than one page.
909  mov $NNN, %rax
910  call ___chkstk_ms/___chkstk
911  sub %rax, %rsp
912  [else]
913  sub $NNN, %rsp
914 
915  [if needs FP]
916  .seh_stackalloc (size of XMM spill slots)
917  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
918  [else]
919  .seh_stackalloc NNN
920 
921  ; Spill XMMs
922  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
923  ; they may get spilled on any platform, if the current function
924  ; calls @llvm.eh.unwind.init
925  [if needs FP]
926  [for all callee-saved XMM registers]
927  movaps %<xmm reg>, -MMM(%rbp)
928  [for all callee-saved XMM registers]
929  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
930  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
931  [else]
932  [for all callee-saved XMM registers]
933  movaps %<xmm reg>, KKK(%rsp)
934  [for all callee-saved XMM registers]
935  .seh_savexmm %<xmm reg>, KKK
936 
937  .seh_endprologue
938 
939  [if needs base pointer]
940  mov %rsp, %rbx
941  [if needs to restore base pointer]
942  mov %rsp, -MMM(%rbp)
943 
944  ; Emit CFI info
945  [if needs FP]
946  [for all callee-saved registers]
947  .cfi_offset %<reg>, (offset from %rbp)
948  [else]
949  .cfi_def_cfa_offset (offset from RETADDR)
950  [for all callee-saved registers]
951  .cfi_offset %<reg>, (offset from %rsp)
952 
953  Notes:
954  - .seh directives are emitted only for Windows 64 ABI
955  - .cv_fpo directives are emitted on win32 when emitting CodeView
956  - .cfi directives are emitted for all other ABIs
957  - for 32-bit code, substitute %e?? registers for %r??
958 */
959 
961  MachineBasicBlock &MBB) const {
962  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
963  "MF used frame lowering for wrong subtarget");
964  MachineBasicBlock::iterator MBBI = MBB.begin();
965  MachineFrameInfo &MFI = MF.getFrameInfo();
966  const Function &Fn = MF.getFunction();
967  MachineModuleInfo &MMI = MF.getMMI();
969  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
970  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
971  bool IsFunclet = MBB.isEHFuncletEntry();
973  if (Fn.hasPersonalityFn())
974  Personality = classifyEHPersonality(Fn.getPersonalityFn());
975  bool FnHasClrFunclet =
976  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
977  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
978  bool HasFP = hasFP(MF);
979  bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
980  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
981  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
982  // FIXME: Emit FPO data for EH funclets.
983  bool NeedsWinFPO =
984  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
985  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
986  bool NeedsDwarfCFI =
987  !IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
988  unsigned FramePtr = TRI->getFrameRegister(MF);
989  const unsigned MachineFramePtr =
991  ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
992  unsigned BasePtr = TRI->getBaseRegister();
993  bool HasWinCFI = false;
994 
995  // Debug location must be unknown since the first debug location is used
996  // to determine the end of the prologue.
997  DebugLoc DL;
998 
999  // Add RETADDR move area to callee saved frame size.
1000  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1001  if (TailCallReturnAddrDelta && IsWin64Prologue)
1002  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1003 
1004  if (TailCallReturnAddrDelta < 0)
1005  X86FI->setCalleeSavedFrameSize(
1006  X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
1007 
1008  bool UseStackProbe = !STI.getTargetLowering()->getStackProbeSymbolName(MF).empty();
1009 
1010  // The default stack probe size is 4096 if the function has no stackprobesize
1011  // attribute.
1012  unsigned StackProbeSize = 4096;
1013  if (Fn.hasFnAttribute("stack-probe-size"))
1014  Fn.getFnAttribute("stack-probe-size")
1015  .getValueAsString()
1016  .getAsInteger(0, StackProbeSize);
1017 
1018  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1019  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1020  // stack alignment.
1021  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1022  Fn.arg_size() == 2) {
1023  StackSize += 8;
1024  MFI.setStackSize(StackSize);
1025  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1026  }
1027 
1028  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1029  // function, and use up to 128 bytes of stack space, don't have a frame
1030  // pointer, calls, or dynamic alloca then we do not need to adjust the
1031  // stack pointer (we fit in the Red Zone). We also check that we don't
1032  // push and pop from the stack.
1033  if (Is64Bit && !Fn.hasFnAttribute(Attribute::NoRedZone) &&
1034  !TRI->needsStackRealignment(MF) &&
1035  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1036  !MFI.adjustsStack() && // No calls.
1037  !UseStackProbe && // No stack probes.
1038  !IsWin64CC && // Win64 has no Red Zone
1039  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1040  !MF.shouldSplitStack()) { // Regular stack
1041  uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
1042  if (HasFP) MinSize += SlotSize;
1043  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1044  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1045  MFI.setStackSize(StackSize);
1046  }
1047 
1048  // Insert stack pointer adjustment for later moving of return addr. Only
1049  // applies to tail call optimized functions where the callee argument stack
1050  // size is bigger than the callers.
1051  if (TailCallReturnAddrDelta < 0) {
1052  BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
1053  /*InEpilogue=*/false)
1055  }
1056 
1057  // Mapping for machine moves:
1058  //
1059  // DST: VirtualFP AND
1060  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1061  // ELSE => DW_CFA_def_cfa
1062  //
1063  // SRC: VirtualFP AND
1064  // DST: Register => DW_CFA_def_cfa_register
1065  //
1066  // ELSE
1067  // OFFSET < 0 => DW_CFA_offset_extended_sf
1068  // REG < 64 => DW_CFA_offset + Reg
1069  // ELSE => DW_CFA_offset_extended
1070 
1071  uint64_t NumBytes = 0;
1072  int stackGrowth = -SlotSize;
1073 
1074  // Find the funclet establisher parameter
1075  unsigned Establisher = X86::NoRegister;
1076  if (IsClrFunclet)
1077  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1078  else if (IsFunclet)
1079  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1080 
1081  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1082  // Immediately spill establisher into the home slot.
1083  // The runtime cares about this.
1084  // MOV64mr %rdx, 16(%rsp)
1085  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1086  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1087  .addReg(Establisher)
1089  MBB.addLiveIn(Establisher);
1090  }
1091 
1092  if (HasFP) {
1093  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1094 
1095  // Calculate required stack adjustment.
1096  uint64_t FrameSize = StackSize - SlotSize;
1097  // If required, include space for extra hidden slot for stashing base pointer.
1098  if (X86FI->getRestoreBasePointer())
1099  FrameSize += SlotSize;
1100 
1101  NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1102 
1103  // Callee-saved registers are pushed on stack before the stack is realigned.
1104  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1105  NumBytes = alignTo(NumBytes, MaxAlign);
1106 
1107  // Save EBP/RBP into the appropriate stack slot.
1108  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1109  .addReg(MachineFramePtr, RegState::Kill)
1111 
1112  if (NeedsDwarfCFI) {
1113  // Mark the place where EBP/RBP was saved.
1114  // Define the current CFA rule to use the provided offset.
1115  assert(StackSize);
1116  BuildCFI(MBB, MBBI, DL,
1117  MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1118 
1119  // Change the rule for the FramePtr to be an "offset" rule.
1120  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1122  nullptr, DwarfFramePtr, 2 * stackGrowth));
1123  }
1124 
1125  if (NeedsWinCFI) {
1126  HasWinCFI = true;
1127  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1128  .addImm(FramePtr)
1130  }
1131 
1132  if (!IsWin64Prologue && !IsFunclet) {
1133  // Update EBP with the new base value.
1134  BuildMI(MBB, MBBI, DL,
1135  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1136  FramePtr)
1137  .addReg(StackPtr)
1139 
1140  if (NeedsDwarfCFI) {
1141  // Mark effective beginning of when frame pointer becomes valid.
1142  // Define the current CFA to use the EBP/RBP register.
1143  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1145  nullptr, DwarfFramePtr));
1146  }
1147 
1148  if (NeedsWinFPO) {
1149  // .cv_fpo_setframe $FramePtr
1150  HasWinCFI = true;
1151  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1152  .addImm(FramePtr)
1153  .addImm(0)
1155  }
1156  }
1157  } else {
1158  assert(!IsFunclet && "funclets without FPs not yet implemented");
1159  NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1160  }
1161 
1162  // Update the offset adjustment, which is mainly used by codeview to translate
1163  // from ESP to VFRAME relative local variable offsets.
1164  if (!IsFunclet) {
1165  if (HasFP && TRI->needsStackRealignment(MF))
1166  MFI.setOffsetAdjustment(-NumBytes);
1167  else
1168  MFI.setOffsetAdjustment(-StackSize);
1169  }
1170 
1171  // For EH funclets, only allocate enough space for outgoing calls. Save the
1172  // NumBytes value that we would've used for the parent frame.
1173  unsigned ParentFrameNumBytes = NumBytes;
1174  if (IsFunclet)
1175  NumBytes = getWinEHFuncletFrameSize(MF);
1176 
1177  // Skip the callee-saved push instructions.
1178  bool PushedRegs = false;
1179  int StackOffset = 2 * stackGrowth;
1180 
1181  while (MBBI != MBB.end() &&
1182  MBBI->getFlag(MachineInstr::FrameSetup) &&
1183  (MBBI->getOpcode() == X86::PUSH32r ||
1184  MBBI->getOpcode() == X86::PUSH64r)) {
1185  PushedRegs = true;
1186  unsigned Reg = MBBI->getOperand(0).getReg();
1187  ++MBBI;
1188 
1189  if (!HasFP && NeedsDwarfCFI) {
1190  // Mark callee-saved push instruction.
1191  // Define the current CFA rule to use the provided offset.
1192  assert(StackSize);
1193  BuildCFI(MBB, MBBI, DL,
1194  MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1195  StackOffset += stackGrowth;
1196  }
1197 
1198  if (NeedsWinCFI) {
1199  HasWinCFI = true;
1200  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1201  .addImm(Reg)
1203  }
1204  }
1205 
1206  // Realign stack after we pushed callee-saved registers (so that we'll be
1207  // able to calculate their offsets from the frame pointer).
1208  // Don't do this for Win64, it needs to realign the stack after the prologue.
1209  if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1210  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1211  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1212 
1213  if (NeedsWinCFI) {
1214  HasWinCFI = true;
1215  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1216  .addImm(MaxAlign)
1218  }
1219  }
1220 
1221  // If there is an SUB32ri of ESP immediately before this instruction, merge
1222  // the two. This can be the case when tail call elimination is enabled and
1223  // the callee has more arguments then the caller.
1224  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1225 
1226  // Adjust stack pointer: ESP -= numbytes.
1227 
1228  // Windows and cygwin/mingw require a prologue helper routine when allocating
1229  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1230  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1231  // stack and adjust the stack pointer in one go. The 64-bit version of
1232  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1233  // responsible for adjusting the stack pointer. Touching the stack at 4K
1234  // increments is necessary to ensure that the guard pages used by the OS
1235  // virtual memory manager are allocated in correct sequence.
1236  uint64_t AlignedNumBytes = NumBytes;
1237  if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1238  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1239  if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1240  assert(!X86FI->getUsesRedZone() &&
1241  "The Red Zone is not accounted for in stack probes");
1242 
1243  // Check whether EAX is livein for this block.
1244  bool isEAXAlive = isEAXLiveIn(MBB);
1245 
1246  if (isEAXAlive) {
1247  if (Is64Bit) {
1248  // Save RAX
1249  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1250  .addReg(X86::RAX, RegState::Kill)
1252  } else {
1253  // Save EAX
1254  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1255  .addReg(X86::EAX, RegState::Kill)
1257  }
1258  }
1259 
1260  if (Is64Bit) {
1261  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1262  // Function prologue is responsible for adjusting the stack pointer.
1263  int Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1264  if (isUInt<32>(Alloc)) {
1265  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1266  .addImm(Alloc)
1268  } else if (isInt<32>(Alloc)) {
1269  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1270  .addImm(Alloc)
1272  } else {
1273  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1274  .addImm(Alloc)
1276  }
1277  } else {
1278  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1279  // We'll also use 4 already allocated bytes for EAX.
1280  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1281  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1283  }
1284 
1285  // Call __chkstk, __chkstk_ms, or __alloca.
1286  emitStackProbe(MF, MBB, MBBI, DL, true);
1287 
1288  if (isEAXAlive) {
1289  // Restore RAX/EAX
1290  MachineInstr *MI;
1291  if (Is64Bit)
1292  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1293  StackPtr, false, NumBytes - 8);
1294  else
1295  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1296  StackPtr, false, NumBytes - 4);
1298  MBB.insert(MBBI, MI);
1299  }
1300  } else if (NumBytes) {
1301  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1302  }
1303 
1304  if (NeedsWinCFI && NumBytes) {
1305  HasWinCFI = true;
1306  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1307  .addImm(NumBytes)
1309  }
1310 
1311  int SEHFrameOffset = 0;
1312  unsigned SPOrEstablisher;
1313  if (IsFunclet) {
1314  if (IsClrFunclet) {
1315  // The establisher parameter passed to a CLR funclet is actually a pointer
1316  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1317  // to find the root function establisher frame by loading the PSPSym from
1318  // the intermediate frame.
1319  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1320  MachinePointerInfo NoInfo;
1321  MBB.addLiveIn(Establisher);
1322  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1323  Establisher, false, PSPSlotOffset)
1326  ;
1327  // Save the root establisher back into the current funclet's (mostly
1328  // empty) frame, in case a sub-funclet or the GC needs it.
1329  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1330  false, PSPSlotOffset)
1331  .addReg(Establisher)
1332  .addMemOperand(
1335  SlotSize, SlotSize));
1336  }
1337  SPOrEstablisher = Establisher;
1338  } else {
1339  SPOrEstablisher = StackPtr;
1340  }
1341 
1342  if (IsWin64Prologue && HasFP) {
1343  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1344  // this calculation on the incoming establisher, which holds the value of
1345  // RSP from the parent frame at the end of the prologue.
1346  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1347  if (SEHFrameOffset)
1348  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1349  SPOrEstablisher, false, SEHFrameOffset);
1350  else
1351  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1352  .addReg(SPOrEstablisher);
1353 
1354  // If this is not a funclet, emit the CFI describing our frame pointer.
1355  if (NeedsWinCFI && !IsFunclet) {
1356  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1357  HasWinCFI = true;
1358  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1359  .addImm(FramePtr)
1360  .addImm(SEHFrameOffset)
1362  if (isAsynchronousEHPersonality(Personality))
1363  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1364  }
1365  } else if (IsFunclet && STI.is32Bit()) {
1366  // Reset EBP / ESI to something good for funclets.
1367  MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1368  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1369  // into the registration node so that the runtime will restore it for us.
1370  if (!MBB.isCleanupFuncletEntry()) {
1371  assert(Personality == EHPersonality::MSVC_CXX);
1372  unsigned FrameReg;
1373  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1374  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg);
1375  // ESP is the first field, so no extra displacement is needed.
1376  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1377  false, EHRegOffset)
1378  .addReg(X86::ESP);
1379  }
1380  }
1381 
1382  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1383  const MachineInstr &FrameInstr = *MBBI;
1384  ++MBBI;
1385 
1386  if (NeedsWinCFI) {
1387  int FI;
1388  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1389  if (X86::FR64RegClass.contains(Reg)) {
1390  unsigned IgnoredFrameReg;
1391  int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1392  Offset += SEHFrameOffset;
1393 
1394  HasWinCFI = true;
1395  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1396  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1397  .addImm(Reg)
1398  .addImm(Offset)
1400  }
1401  }
1402  }
1403  }
1404 
1405  if (NeedsWinCFI && HasWinCFI)
1406  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1407  .setMIFlag(MachineInstr::FrameSetup);
1408 
1409  if (FnHasClrFunclet && !IsFunclet) {
1410  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1411  // immediately after the prolog) into the PSPSlot so that funclets
1412  // and the GC can recover it.
1413  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1414  auto PSPInfo = MachinePointerInfo::getFixedStack(
1415  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1416  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1417  PSPSlotOffset)
1418  .addReg(StackPtr)
1421  SlotSize, SlotSize));
1422  }
1423 
1424  // Realign stack after we spilled callee-saved registers (so that we'll be
1425  // able to calculate their offsets from the frame pointer).
1426  // Win64 requires aligning the stack after the prologue.
1427  if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1428  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1429  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1430  }
1431 
1432  // We already dealt with stack realignment and funclets above.
1433  if (IsFunclet && STI.is32Bit())
1434  return;
1435 
1436  // If we need a base pointer, set it up here. It's whatever the value
1437  // of the stack pointer is at this point. Any variable size objects
1438  // will be allocated after this, so we can still use the base pointer
1439  // to reference locals.
1440  if (TRI->hasBasePointer(MF)) {
1441  // Update the base pointer with the current stack pointer.
1442  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1443  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1444  .addReg(SPOrEstablisher)
1446  if (X86FI->getRestoreBasePointer()) {
1447  // Stash value of base pointer. Saving RSP instead of EBP shortens
1448  // dependence chain. Used by SjLj EH.
1449  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1450  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1451  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1452  .addReg(SPOrEstablisher)
1454  }
1455 
1456  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1457  // Stash the value of the frame pointer relative to the base pointer for
1458  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1459  // it recovers the frame pointer from the base pointer rather than the
1460  // other way around.
1461  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1462  unsigned UsedReg;
1463  int Offset =
1464  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1465  assert(UsedReg == BasePtr);
1466  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1467  .addReg(FramePtr)
1469  }
1470  }
1471 
1472  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1473  // Mark end of stack pointer adjustment.
1474  if (!HasFP && NumBytes) {
1475  // Define the current CFA rule to use the provided offset.
1476  assert(StackSize);
1478  nullptr, -StackSize + stackGrowth));
1479  }
1480 
1481  // Emit DWARF info specifying the offsets of the callee-saved registers.
1482  emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1483  }
1484 
1485  // X86 Interrupt handling function cannot assume anything about the direction
1486  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1487  // in each prologue of interrupt handler function.
1488  //
1489  // FIXME: Create "cld" instruction only in these cases:
1490  // 1. The interrupt handling function uses any of the "rep" instructions.
1491  // 2. Interrupt handling function calls another function.
1492  //
1494  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1495  .setMIFlag(MachineInstr::FrameSetup);
1496 
1497  // At this point we know if the function has WinCFI or not.
1498  MF.setHasWinCFI(HasWinCFI);
1499 }
1500 
1502  const MachineFunction &MF) const {
1503  // We can't use LEA instructions for adjusting the stack pointer if we don't
1504  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1505  // to deallocate the stack.
1506  // This means that we can use LEA for SP in two situations:
1507  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1508  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1509  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1510 }
1511 
1513  switch (MI.getOpcode()) {
1514  case X86::CATCHRET:
1515  case X86::CLEANUPRET:
1516  return true;
1517  default:
1518  return false;
1519  }
1520  llvm_unreachable("impossible");
1521 }
1522 
1523 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1524 // stack. It holds a pointer to the bottom of the root function frame. The
1525 // establisher frame pointer passed to a nested funclet may point to the
1526 // (mostly empty) frame of its parent funclet, but it will need to find
1527 // the frame of the root function to access locals. To facilitate this,
1528 // every funclet copies the pointer to the bottom of the root function
1529 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1530 // same offset for the PSPSym in the root function frame that's used in the
1531 // funclets' frames allows each funclet to dynamically accept any ancestor
1532 // frame as its establisher argument (the runtime doesn't guarantee the
1533 // immediate parent for some reason lost to history), and also allows the GC,
1534 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1535 // frame with only a single offset reported for the entire method.
1536 unsigned
1537 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1538  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1539  unsigned SPReg;
1541  /*IgnoreSPUpdates*/ true);
1542  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1543  return static_cast<unsigned>(Offset);
1544 }
1545 
1546 unsigned
1547 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1548  // This is the size of the pushed CSRs.
1549  unsigned CSSize =
1550  MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1551  // This is the amount of stack a funclet needs to allocate.
1552  unsigned UsedSize;
1553  EHPersonality Personality =
1555  if (Personality == EHPersonality::CoreCLR) {
1556  // CLR funclets need to hold enough space to include the PSPSym, at the
1557  // same offset from the stack pointer (immediately after the prolog) as it
1558  // resides at in the main function.
1559  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1560  } else {
1561  // Other funclets just need enough stack for outgoing call arguments.
1562  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1563  }
1564  // RBP is not included in the callee saved register block. After pushing RBP,
1565  // everything is 16 byte aligned. Everything we allocate before an outgoing
1566  // call must also be 16 byte aligned.
1567  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
1568  // Subtract out the size of the callee saved registers. This is how much stack
1569  // each funclet will allocate.
1570  return FrameSizeMinusRBP - CSSize;
1571 }
1572 
1573 static bool isTailCallOpcode(unsigned Opc) {
1574  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
1575  Opc == X86::TCRETURNmi ||
1576  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
1577  Opc == X86::TCRETURNmi64;
1578 }
1579 
1581  MachineBasicBlock &MBB) const {
1582  const MachineFrameInfo &MFI = MF.getFrameInfo();
1586  DebugLoc DL;
1587  if (MBBI != MBB.end())
1588  DL = MBBI->getDebugLoc();
1589  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1590  const bool Is64BitILP32 = STI.isTarget64BitILP32();
1591  unsigned FramePtr = TRI->getFrameRegister(MF);
1592  unsigned MachineFramePtr =
1593  Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1594 
1595  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1596  bool NeedsWin64CFI =
1597  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
1598  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
1599 
1600  // Get the number of bytes to allocate from the FrameInfo.
1601  uint64_t StackSize = MFI.getStackSize();
1602  uint64_t MaxAlign = calculateMaxStackAlign(MF);
1603  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1604  bool HasFP = hasFP(MF);
1605  uint64_t NumBytes = 0;
1606 
1607  bool NeedsDwarfCFI =
1608  (!MF.getTarget().getTargetTriple().isOSDarwin() &&
1609  !MF.getTarget().getTargetTriple().isOSWindows()) &&
1611 
1612  if (IsFunclet) {
1613  assert(HasFP && "EH funclets without FP not yet implemented");
1614  NumBytes = getWinEHFuncletFrameSize(MF);
1615  } else if (HasFP) {
1616  // Calculate required stack adjustment.
1617  uint64_t FrameSize = StackSize - SlotSize;
1618  NumBytes = FrameSize - CSSize;
1619 
1620  // Callee-saved registers were pushed on stack before the stack was
1621  // realigned.
1622  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1623  NumBytes = alignTo(FrameSize, MaxAlign);
1624  } else {
1625  NumBytes = StackSize - CSSize;
1626  }
1627  uint64_t SEHStackAllocAmt = NumBytes;
1628 
1629  if (HasFP) {
1630  // Pop EBP.
1631  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1632  MachineFramePtr)
1633  .setMIFlag(MachineInstr::FrameDestroy);
1634  if (NeedsDwarfCFI) {
1635  unsigned DwarfStackPtr =
1636  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
1638  nullptr, DwarfStackPtr, -SlotSize));
1639  --MBBI;
1640  }
1641  }
1642 
1643  MachineBasicBlock::iterator FirstCSPop = MBBI;
1644  // Skip the callee-saved pop instructions.
1645  while (MBBI != MBB.begin()) {
1646  MachineBasicBlock::iterator PI = std::prev(MBBI);
1647  unsigned Opc = PI->getOpcode();
1648 
1649  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1650  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1651  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1652  break;
1653  FirstCSPop = PI;
1654  }
1655 
1656  --MBBI;
1657  }
1658  MBBI = FirstCSPop;
1659 
1660  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1661  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
1662 
1663  if (MBBI != MBB.end())
1664  DL = MBBI->getDebugLoc();
1665 
1666  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1667  // instruction, merge the two instructions.
1668  if (NumBytes || MFI.hasVarSizedObjects())
1669  NumBytes += mergeSPUpdates(MBB, MBBI, true);
1670 
1671  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1672  // slot before popping them off! Same applies for the case, when stack was
1673  // realigned. Don't do this if this was a funclet epilogue, since the funclets
1674  // will not do realignment or dynamic stack allocation.
1675  if ((TRI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) &&
1676  !IsFunclet) {
1677  if (TRI->needsStackRealignment(MF))
1678  MBBI = FirstCSPop;
1679  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1680  uint64_t LEAAmount =
1681  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1682 
1683  // There are only two legal forms of epilogue:
1684  // - add SEHAllocationSize, %rsp
1685  // - lea SEHAllocationSize(%FramePtr), %rsp
1686  //
1687  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1688  // However, we may use this sequence if we have a frame pointer because the
1689  // effects of the prologue can safely be undone.
1690  if (LEAAmount != 0) {
1691  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1692  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1693  FramePtr, false, LEAAmount);
1694  --MBBI;
1695  } else {
1696  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1697  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1698  .addReg(FramePtr);
1699  --MBBI;
1700  }
1701  } else if (NumBytes) {
1702  // Adjust stack pointer back: ESP += numbytes.
1703  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
1704  if (!hasFP(MF) && NeedsDwarfCFI) {
1705  // Define the current CFA rule to use the provided offset.
1707  nullptr, -CSSize - SlotSize));
1708  }
1709  --MBBI;
1710  }
1711 
1712  // Windows unwinder will not invoke function's exception handler if IP is
1713  // either in prologue or in epilogue. This behavior causes a problem when a
1714  // call immediately precedes an epilogue, because the return address points
1715  // into the epilogue. To cope with that, we insert an epilogue marker here,
1716  // then replace it with a 'nop' if it ends up immediately after a CALL in the
1717  // final emitted code.
1718  if (NeedsWin64CFI && MF.hasWinCFI())
1719  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1720 
1721  if (!hasFP(MF) && NeedsDwarfCFI) {
1722  MBBI = FirstCSPop;
1723  int64_t Offset = -CSSize - SlotSize;
1724  // Mark callee-saved pop instruction.
1725  // Define the current CFA rule to use the provided offset.
1726  while (MBBI != MBB.end()) {
1727  MachineBasicBlock::iterator PI = MBBI;
1728  unsigned Opc = PI->getOpcode();
1729  ++MBBI;
1730  if (Opc == X86::POP32r || Opc == X86::POP64r) {
1731  Offset += SlotSize;
1732  BuildCFI(MBB, MBBI, DL,
1733  MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
1734  }
1735  }
1736  }
1737 
1738  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
1739  // Add the return addr area delta back since we are not tail calling.
1740  int Offset = -1 * X86FI->getTCReturnAddrDelta();
1741  assert(Offset >= 0 && "TCDelta should never be positive");
1742  if (Offset) {
1743  // Check for possible merge with preceding ADD instruction.
1744  Offset += mergeSPUpdates(MBB, Terminator, true);
1745  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
1746  }
1747  }
1748 }
1749 
1751  unsigned &FrameReg) const {
1752  const MachineFrameInfo &MFI = MF.getFrameInfo();
1753 
1754  bool IsFixed = MFI.isFixedObjectIndex(FI);
1755  // We can't calculate offset from frame pointer if the stack is realigned,
1756  // so enforce usage of stack/base pointer. The base pointer is used when we
1757  // have dynamic allocas in addition to dynamic realignment.
1758  if (TRI->hasBasePointer(MF))
1759  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
1760  else if (TRI->needsStackRealignment(MF))
1761  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
1762  else
1763  FrameReg = TRI->getFrameRegister(MF);
1764 
1765  // Offset will hold the offset from the stack pointer at function entry to the
1766  // object.
1767  // We need to factor in additional offsets applied during the prologue to the
1768  // frame, base, and stack pointer depending on which is used.
1769  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
1771  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1772  uint64_t StackSize = MFI.getStackSize();
1773  bool HasFP = hasFP(MF);
1774  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1775  int64_t FPDelta = 0;
1776 
1777  // In an x86 interrupt, remove the offset we added to account for the return
1778  // address from any stack object allocated in the caller's frame. Interrupts
1779  // do not have a standard return address. Fixed objects in the current frame,
1780  // such as SSE register spills, should not get this treatment.
1782  Offset >= 0) {
1783  Offset += getOffsetOfLocalArea();
1784  }
1785 
1786  if (IsWin64Prologue) {
1787  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
1788 
1789  // Calculate required stack adjustment.
1790  uint64_t FrameSize = StackSize - SlotSize;
1791  // If required, include space for extra hidden slot for stashing base pointer.
1792  if (X86FI->getRestoreBasePointer())
1793  FrameSize += SlotSize;
1794  uint64_t NumBytes = FrameSize - CSSize;
1795 
1796  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1797  if (FI && FI == X86FI->getFAIndex())
1798  return -SEHFrameOffset;
1799 
1800  // FPDelta is the offset from the "traditional" FP location of the old base
1801  // pointer followed by return address and the location required by the
1802  // restricted Win64 prologue.
1803  // Add FPDelta to all offsets below that go through the frame pointer.
1804  FPDelta = FrameSize - SEHFrameOffset;
1805  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
1806  "FPDelta isn't aligned per the Win64 ABI!");
1807  }
1808 
1809 
1810  if (TRI->hasBasePointer(MF)) {
1811  assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1812  if (FI < 0) {
1813  // Skip the saved EBP.
1814  return Offset + SlotSize + FPDelta;
1815  } else {
1816  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1817  return Offset + StackSize;
1818  }
1819  } else if (TRI->needsStackRealignment(MF)) {
1820  if (FI < 0) {
1821  // Skip the saved EBP.
1822  return Offset + SlotSize + FPDelta;
1823  } else {
1824  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1825  return Offset + StackSize;
1826  }
1827  // FIXME: Support tail calls
1828  } else {
1829  if (!HasFP)
1830  return Offset + StackSize;
1831 
1832  // Skip the saved EBP.
1833  Offset += SlotSize;
1834 
1835  // Skip the RETADDR move area
1836  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1837  if (TailCallReturnAddrDelta < 0)
1838  Offset -= TailCallReturnAddrDelta;
1839  }
1840 
1841  return Offset + FPDelta;
1842 }
1843 
1845  int FI, unsigned &FrameReg,
1846  int Adjustment) const {
1847  const MachineFrameInfo &MFI = MF.getFrameInfo();
1848  FrameReg = TRI->getStackRegister();
1849  return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment;
1850 }
1851 
1852 int
1854  int FI, unsigned &FrameReg,
1855  bool IgnoreSPUpdates) const {
1856 
1857  const MachineFrameInfo &MFI = MF.getFrameInfo();
1858  // Does not include any dynamic realign.
1859  const uint64_t StackSize = MFI.getStackSize();
1860  // LLVM arranges the stack as follows:
1861  // ...
1862  // ARG2
1863  // ARG1
1864  // RETADDR
1865  // PUSH RBP <-- RBP points here
1866  // PUSH CSRs
1867  // ~~~~~~~ <-- possible stack realignment (non-win64)
1868  // ...
1869  // STACK OBJECTS
1870  // ... <-- RSP after prologue points here
1871  // ~~~~~~~ <-- possible stack realignment (win64)
1872  //
1873  // if (hasVarSizedObjects()):
1874  // ... <-- "base pointer" (ESI/RBX) points here
1875  // DYNAMIC ALLOCAS
1876  // ... <-- RSP points here
1877  //
1878  // Case 1: In the simple case of no stack realignment and no dynamic
1879  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1880  // with fixed offsets from RSP.
1881  //
1882  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1883  // stack objects are addressed with RBP and regular stack objects with RSP.
1884  //
1885  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1886  // to address stack arguments for outgoing calls and nothing else. The "base
1887  // pointer" points to local variables, and RBP points to fixed objects.
1888  //
1889  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1890  // answer we give is relative to the SP after the prologue, and not the
1891  // SP in the middle of the function.
1892 
1893  if (MFI.isFixedObjectIndex(FI) && TRI->needsStackRealignment(MF) &&
1894  !STI.isTargetWin64())
1895  return getFrameIndexReference(MF, FI, FrameReg);
1896 
1897  // If !hasReservedCallFrame the function might have SP adjustement in the
1898  // body. So, even though the offset is statically known, it depends on where
1899  // we are in the function.
1901  if (!IgnoreSPUpdates && !TFI->hasReservedCallFrame(MF))
1902  return getFrameIndexReference(MF, FI, FrameReg);
1903 
1904  // We don't handle tail calls, and shouldn't be seeing them either.
1906  "we don't handle this case!");
1907 
1908  // This is how the math works out:
1909  //
1910  // %rsp grows (i.e. gets lower) left to right. Each box below is
1911  // one word (eight bytes). Obj0 is the stack slot we're trying to
1912  // get to.
1913  //
1914  // ----------------------------------
1915  // | BP | Obj0 | Obj1 | ... | ObjN |
1916  // ----------------------------------
1917  // ^ ^ ^ ^
1918  // A B C E
1919  //
1920  // A is the incoming stack pointer.
1921  // (B - A) is the local area offset (-8 for x86-64) [1]
1922  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
1923  //
1924  // |(E - B)| is the StackSize (absolute value, positive). For a
1925  // stack that grown down, this works out to be (B - E). [3]
1926  //
1927  // E is also the value of %rsp after stack has been set up, and we
1928  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1929  // (C - E) == (C - A) - (B - A) + (B - E)
1930  // { Using [1], [2] and [3] above }
1931  // == getObjectOffset - LocalAreaOffset + StackSize
1932 
1933  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
1934 }
1935 
1938  std::vector<CalleeSavedInfo> &CSI) const {
1939  MachineFrameInfo &MFI = MF.getFrameInfo();
1941 
1942  unsigned CalleeSavedFrameSize = 0;
1943  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1944 
1945  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1946 
1947  if (TailCallReturnAddrDelta < 0) {
1948  // create RETURNADDR area
1949  // arg
1950  // arg
1951  // RETADDR
1952  // { ...
1953  // RETADDR area
1954  // ...
1955  // }
1956  // [EBP]
1957  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
1958  TailCallReturnAddrDelta - SlotSize, true);
1959  }
1960 
1961  // Spill the BasePtr if it's used.
1962  if (this->TRI->hasBasePointer(MF)) {
1963  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1964  if (MF.hasEHFunclets()) {
1965  int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
1966  X86FI->setHasSEHFramePtrSave(true);
1967  X86FI->setSEHFramePtrSaveIndex(FI);
1968  }
1969  }
1970 
1971  if (hasFP(MF)) {
1972  // emitPrologue always spills frame register the first thing.
1973  SpillSlotOffset -= SlotSize;
1974  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1975 
1976  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1977  // the frame register, we can delete it from CSI list and not have to worry
1978  // about avoiding it later.
1979  unsigned FPReg = TRI->getFrameRegister(MF);
1980  for (unsigned i = 0; i < CSI.size(); ++i) {
1981  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1982  CSI.erase(CSI.begin() + i);
1983  break;
1984  }
1985  }
1986  }
1987 
1988  // Assign slots for GPRs. It increases frame size.
1989  for (unsigned i = CSI.size(); i != 0; --i) {
1990  unsigned Reg = CSI[i - 1].getReg();
1991 
1992  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1993  continue;
1994 
1995  SpillSlotOffset -= SlotSize;
1996  CalleeSavedFrameSize += SlotSize;
1997 
1998  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1999  CSI[i - 1].setFrameIdx(SlotIndex);
2000  }
2001 
2002  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2003  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2004 
2005  // Assign slots for XMMs.
2006  for (unsigned i = CSI.size(); i != 0; --i) {
2007  unsigned Reg = CSI[i - 1].getReg();
2008  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2009  continue;
2010 
2011  // If this is k-register make sure we lookup via the largest legal type.
2012  MVT VT = MVT::Other;
2013  if (X86::VK16RegClass.contains(Reg))
2014  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2015 
2016  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2017  unsigned Size = TRI->getSpillSize(*RC);
2018  unsigned Align = TRI->getSpillAlignment(*RC);
2019  // ensure alignment
2020  SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
2021  // spill into slot
2022  SpillSlotOffset -= Size;
2023  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2024  CSI[i - 1].setFrameIdx(SlotIndex);
2025  MFI.ensureMaxAlignment(Align);
2026  }
2027 
2028  return true;
2029 }
2030 
2033  const std::vector<CalleeSavedInfo> &CSI,
2034  const TargetRegisterInfo *TRI) const {
2035  DebugLoc DL = MBB.findDebugLoc(MI);
2036 
2037  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2038  // for us, and there are no XMM CSRs on Win32.
2039  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2040  return true;
2041 
2042  // Push GPRs. It increases frame size.
2043  const MachineFunction &MF = *MBB.getParent();
2044  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2045  for (unsigned i = CSI.size(); i != 0; --i) {
2046  unsigned Reg = CSI[i - 1].getReg();
2047 
2048  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2049  continue;
2050 
2051  const MachineRegisterInfo &MRI = MF.getRegInfo();
2052  bool isLiveIn = MRI.isLiveIn(Reg);
2053  if (!isLiveIn)
2054  MBB.addLiveIn(Reg);
2055 
2056  // Decide whether we can add a kill flag to the use.
2057  bool CanKill = !isLiveIn;
2058  // Check if any subregister is live-in
2059  if (CanKill) {
2060  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2061  if (MRI.isLiveIn(*AReg)) {
2062  CanKill = false;
2063  break;
2064  }
2065  }
2066  }
2067 
2068  // Do not set a kill flag on values that are also marked as live-in. This
2069  // happens with the @llvm-returnaddress intrinsic and with arguments
2070  // passed in callee saved registers.
2071  // Omitting the kill flags is conservatively correct even if the live-in
2072  // is not used after all.
2073  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2074  .setMIFlag(MachineInstr::FrameSetup);
2075  }
2076 
2077  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2078  // It can be done by spilling XMMs to stack frame.
2079  for (unsigned i = CSI.size(); i != 0; --i) {
2080  unsigned Reg = CSI[i-1].getReg();
2081  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2082  continue;
2083 
2084  // If this is k-register make sure we lookup via the largest legal type.
2085  MVT VT = MVT::Other;
2086  if (X86::VK16RegClass.contains(Reg))
2087  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2088 
2089  // Add the callee-saved register as live-in. It's killed at the spill.
2090  MBB.addLiveIn(Reg);
2091  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2092 
2093  TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2094  TRI);
2095  --MI;
2096  MI->setFlag(MachineInstr::FrameSetup);
2097  ++MI;
2098  }
2099 
2100  return true;
2101 }
2102 
2103 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2105  MachineInstr *CatchRet) const {
2106  // SEH shouldn't use catchret.
2108  MBB.getParent()->getFunction().getPersonalityFn())) &&
2109  "SEH should not use CATCHRET");
2110  DebugLoc DL = CatchRet->getDebugLoc();
2111  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2112 
2113  // Fill EAX/RAX with the address of the target block.
2114  if (STI.is64Bit()) {
2115  // LEA64r CatchRetTarget(%rip), %rax
2116  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2117  .addReg(X86::RIP)
2118  .addImm(0)
2119  .addReg(0)
2120  .addMBB(CatchRetTarget)
2121  .addReg(0);
2122  } else {
2123  // MOV32ri $CatchRetTarget, %eax
2124  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2125  .addMBB(CatchRetTarget);
2126  }
2127 
2128  // Record that we've taken the address of CatchRetTarget and no longer just
2129  // reference it in a terminator.
2130  CatchRetTarget->setHasAddressTaken();
2131 }
2132 
2135  std::vector<CalleeSavedInfo> &CSI,
2136  const TargetRegisterInfo *TRI) const {
2137  if (CSI.empty())
2138  return false;
2139 
2140  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2141  // Don't restore CSRs in 32-bit EH funclets. Matches
2142  // spillCalleeSavedRegisters.
2143  if (STI.is32Bit())
2144  return true;
2145  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2146  // funclets. emitEpilogue transforms these to normal jumps.
2147  if (MI->getOpcode() == X86::CATCHRET) {
2148  const Function &F = MBB.getParent()->getFunction();
2149  bool IsSEH = isAsynchronousEHPersonality(
2151  if (IsSEH)
2152  return true;
2153  }
2154  }
2155 
2156  DebugLoc DL = MBB.findDebugLoc(MI);
2157 
2158  // Reload XMMs from stack frame.
2159  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2160  unsigned Reg = CSI[i].getReg();
2161  if (X86::GR64RegClass.contains(Reg) ||
2162  X86::GR32RegClass.contains(Reg))
2163  continue;
2164 
2165  // If this is k-register make sure we lookup via the largest legal type.
2166  MVT VT = MVT::Other;
2167  if (X86::VK16RegClass.contains(Reg))
2168  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2169 
2170  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2171  TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2172  }
2173 
2174  // POP GPRs.
2175  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2176  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2177  unsigned Reg = CSI[i].getReg();
2178  if (!X86::GR64RegClass.contains(Reg) &&
2179  !X86::GR32RegClass.contains(Reg))
2180  continue;
2181 
2182  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2183  .setMIFlag(MachineInstr::FrameDestroy);
2184  }
2185  return true;
2186 }
2187 
2189  BitVector &SavedRegs,
2190  RegScavenger *RS) const {
2191  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2192 
2193  // Spill the BasePtr if it's used.
2194  if (TRI->hasBasePointer(MF)){
2195  unsigned BasePtr = TRI->getBaseRegister();
2196  if (STI.isTarget64BitILP32())
2197  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2198  SavedRegs.set(BasePtr);
2199  }
2200 }
2201 
2202 static bool
2204  const Function &F = MF->getFunction();
2205  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2206  I != E; I++) {
2207  if (I->hasNestAttr())
2208  return true;
2209  }
2210  return false;
2211 }
2212 
2213 /// GetScratchRegister - Get a temp register for performing work in the
2214 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2215 /// and the properties of the function either one or two registers will be
2216 /// needed. Set primary to true for the first register, false for the second.
2217 static unsigned
2218 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2220 
2221  // Erlang stuff.
2222  if (CallingConvention == CallingConv::HiPE) {
2223  if (Is64Bit)
2224  return Primary ? X86::R14 : X86::R13;
2225  else
2226  return Primary ? X86::EBX : X86::EDI;
2227  }
2228 
2229  if (Is64Bit) {
2230  if (IsLP64)
2231  return Primary ? X86::R11 : X86::R12;
2232  else
2233  return Primary ? X86::R11D : X86::R12D;
2234  }
2235 
2236  bool IsNested = HasNestArgument(&MF);
2237 
2238  if (CallingConvention == CallingConv::X86_FastCall ||
2239  CallingConvention == CallingConv::Fast) {
2240  if (IsNested)
2241  report_fatal_error("Segmented stacks does not support fastcall with "
2242  "nested function.");
2243  return Primary ? X86::EAX : X86::ECX;
2244  }
2245  if (IsNested)
2246  return Primary ? X86::EDX : X86::EAX;
2247  return Primary ? X86::ECX : X86::EAX;
2248 }
2249 
2250 // The stack limit in the TCB is set to this many bytes above the actual stack
2251 // limit.
2252 static const uint64_t kSplitStackAvailable = 256;
2253 
2255  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2256  MachineFrameInfo &MFI = MF.getFrameInfo();
2257  uint64_t StackSize;
2258  unsigned TlsReg, TlsOffset;
2259  DebugLoc DL;
2260 
2261  // To support shrink-wrapping we would need to insert the new blocks
2262  // at the right place and update the branches to PrologueMBB.
2263  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2264 
2265  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2266  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2267  "Scratch register is live-in");
2268 
2269  if (MF.getFunction().isVarArg())
2270  report_fatal_error("Segmented stacks do not support vararg functions.");
2271  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2272  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2274  report_fatal_error("Segmented stacks not supported on this platform.");
2275 
2276  // Eventually StackSize will be calculated by a link-time pass; which will
2277  // also decide whether checking code needs to be injected into this particular
2278  // prologue.
2279  StackSize = MFI.getStackSize();
2280 
2281  // Do not generate a prologue for leaf functions with a stack of size zero.
2282  // For non-leaf functions we have to allow for the possibility that the
2283  // callis to a non-split function, as in PR37807. This function could also
2284  // take the address of a non-split function. When the linker tries to adjust
2285  // its non-existent prologue, it would fail with an error. Mark the object
2286  // file so that such failures are not errors. See this Go language bug-report
2287  // https://go-review.googlesource.com/c/go/+/148819/
2288  if (StackSize == 0 && !MFI.hasTailCall()) {
2289  MF.getMMI().setHasNosplitStack(true);
2290  return;
2291  }
2292 
2293  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2294  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2296  bool IsNested = false;
2297 
2298  // We need to know if the function has a nest argument only in 64 bit mode.
2299  if (Is64Bit)
2300  IsNested = HasNestArgument(&MF);
2301 
2302  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2303  // allocMBB needs to be last (terminating) instruction.
2304 
2305  for (const auto &LI : PrologueMBB.liveins()) {
2306  allocMBB->addLiveIn(LI);
2307  checkMBB->addLiveIn(LI);
2308  }
2309 
2310  if (IsNested)
2311  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2312 
2313  MF.push_front(allocMBB);
2314  MF.push_front(checkMBB);
2315 
2316  // When the frame size is less than 256 we just compare the stack
2317  // boundary directly to the value of the stack pointer, per gcc.
2318  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2319 
2320  // Read the limit off the current stacklet off the stack_guard location.
2321  if (Is64Bit) {
2322  if (STI.isTargetLinux()) {
2323  TlsReg = X86::FS;
2324  TlsOffset = IsLP64 ? 0x70 : 0x40;
2325  } else if (STI.isTargetDarwin()) {
2326  TlsReg = X86::GS;
2327  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2328  } else if (STI.isTargetWin64()) {
2329  TlsReg = X86::GS;
2330  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2331  } else if (STI.isTargetFreeBSD()) {
2332  TlsReg = X86::FS;
2333  TlsOffset = 0x18;
2334  } else if (STI.isTargetDragonFly()) {
2335  TlsReg = X86::FS;
2336  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2337  } else {
2338  report_fatal_error("Segmented stacks not supported on this platform.");
2339  }
2340 
2341  if (CompareStackPointer)
2342  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2343  else
2344  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2345  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2346 
2347  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2348  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2349  } else {
2350  if (STI.isTargetLinux()) {
2351  TlsReg = X86::GS;
2352  TlsOffset = 0x30;
2353  } else if (STI.isTargetDarwin()) {
2354  TlsReg = X86::GS;
2355  TlsOffset = 0x48 + 90*4;
2356  } else if (STI.isTargetWin32()) {
2357  TlsReg = X86::FS;
2358  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2359  } else if (STI.isTargetDragonFly()) {
2360  TlsReg = X86::FS;
2361  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2362  } else if (STI.isTargetFreeBSD()) {
2363  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2364  } else {
2365  report_fatal_error("Segmented stacks not supported on this platform.");
2366  }
2367 
2368  if (CompareStackPointer)
2369  ScratchReg = X86::ESP;
2370  else
2371  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2372  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2373 
2374  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2375  STI.isTargetDragonFly()) {
2376  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2377  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2378  } else if (STI.isTargetDarwin()) {
2379 
2380  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2381  unsigned ScratchReg2;
2382  bool SaveScratch2;
2383  if (CompareStackPointer) {
2384  // The primary scratch register is available for holding the TLS offset.
2385  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2386  SaveScratch2 = false;
2387  } else {
2388  // Need to use a second register to hold the TLS offset
2389  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2390 
2391  // Unfortunately, with fastcc the second scratch register may hold an
2392  // argument.
2393  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2394  }
2395 
2396  // If Scratch2 is live-in then it needs to be saved.
2397  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2398  "Scratch register is live-in and not saved");
2399 
2400  if (SaveScratch2)
2401  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2402  .addReg(ScratchReg2, RegState::Kill);
2403 
2404  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2405  .addImm(TlsOffset);
2406  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2407  .addReg(ScratchReg)
2408  .addReg(ScratchReg2).addImm(1).addReg(0)
2409  .addImm(0)
2410  .addReg(TlsReg);
2411 
2412  if (SaveScratch2)
2413  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2414  }
2415  }
2416 
2417  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2418  // It jumps to normal execution of the function body.
2419  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2420 
2421  // On 32 bit we first push the arguments size and then the frame size. On 64
2422  // bit, we pass the stack frame size in r10 and the argument size in r11.
2423  if (Is64Bit) {
2424  // Functions with nested arguments use R10, so it needs to be saved across
2425  // the call to _morestack
2426 
2427  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2428  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2429  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2430  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2431  const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2432 
2433  if (IsNested)
2434  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2435 
2436  BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2437  .addImm(StackSize);
2438  BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2439  .addImm(X86FI->getArgumentStackSize());
2440  } else {
2441  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2442  .addImm(X86FI->getArgumentStackSize());
2443  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2444  .addImm(StackSize);
2445  }
2446 
2447  // __morestack is in libgcc
2448  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2449  // Under the large code model, we cannot assume that __morestack lives
2450  // within 2^31 bytes of the call site, so we cannot use pc-relative
2451  // addressing. We cannot perform the call via a temporary register,
2452  // as the rax register may be used to store the static chain, and all
2453  // other suitable registers may be either callee-save or used for
2454  // parameter passing. We cannot use the stack at this point either
2455  // because __morestack manipulates the stack directly.
2456  //
2457  // To avoid these issues, perform an indirect call via a read-only memory
2458  // location containing the address.
2459  //
2460  // This solution is not perfect, as it assumes that the .rodata section
2461  // is laid out within 2^31 bytes of each function body, but this seems
2462  // to be sufficient for JIT.
2463  // FIXME: Add retpoline support and remove the error here..
2465  report_fatal_error("Emitting morestack calls on 64-bit with the large "
2466  "code model and retpoline not yet implemented.");
2467  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2468  .addReg(X86::RIP)
2469  .addImm(0)
2470  .addReg(0)
2471  .addExternalSymbol("__morestack_addr")
2472  .addReg(0);
2473  MF.getMMI().setUsesMorestackAddr(true);
2474  } else {
2475  if (Is64Bit)
2476  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2477  .addExternalSymbol("__morestack");
2478  else
2479  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2480  .addExternalSymbol("__morestack");
2481  }
2482 
2483  if (IsNested)
2484  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2485  else
2486  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2487 
2488  allocMBB->addSuccessor(&PrologueMBB);
2489 
2490  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2491  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2492 
2493 #ifdef EXPENSIVE_CHECKS
2494  MF.verify();
2495 #endif
2496 }
2497 
2498 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
2499 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
2500 /// to fields it needs, through a named metadata node "hipe.literals" containing
2501 /// name-value pairs.
2502 static unsigned getHiPELiteral(
2503  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
2504  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
2505  MDNode *Node = HiPELiteralsMD->getOperand(i);
2506  if (Node->getNumOperands() != 2) continue;
2507  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
2508  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
2509  if (!NodeName || !NodeVal) continue;
2510  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
2511  if (ValConst && NodeName->getString() == LiteralName) {
2512  return ValConst->getZExtValue();
2513  }
2514  }
2515 
2516  report_fatal_error("HiPE literal " + LiteralName
2517  + " required but not provided");
2518 }
2519 
2520 /// Erlang programs may need a special prologue to handle the stack size they
2521 /// might need at runtime. That is because Erlang/OTP does not implement a C
2522 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2523 /// (for more information see Eric Stenman's Ph.D. thesis:
2524 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2525 ///
2526 /// CheckStack:
2527 /// temp0 = sp - MaxStack
2528 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2529 /// OldStart:
2530 /// ...
2531 /// IncStack:
2532 /// call inc_stack # doubles the stack space
2533 /// temp0 = sp - MaxStack
2534 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2536  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2537  MachineFrameInfo &MFI = MF.getFrameInfo();
2538  DebugLoc DL;
2539 
2540  // To support shrink-wrapping we would need to insert the new blocks
2541  // at the right place and update the branches to PrologueMBB.
2542  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2543 
2544  // HiPE-specific values
2545  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
2546  ->getNamedMetadata("hipe.literals");
2547  if (!HiPELiteralsMD)
2549  "Can't generate HiPE prologue without runtime parameters");
2550  const unsigned HipeLeafWords
2551  = getHiPELiteral(HiPELiteralsMD,
2552  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
2553  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2554  const unsigned Guaranteed = HipeLeafWords * SlotSize;
2555  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
2556  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
2557  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
2558 
2559  assert(STI.isTargetLinux() &&
2560  "HiPE prologue is only supported on Linux operating systems.");
2561 
2562  // Compute the largest caller's frame that is needed to fit the callees'
2563  // frames. This 'MaxStack' is computed from:
2564  //
2565  // a) the fixed frame size, which is the space needed for all spilled temps,
2566  // b) outgoing on-stack parameter areas, and
2567  // c) the minimum stack space this function needs to make available for the
2568  // functions it calls (a tunable ABI property).
2569  if (MFI.hasCalls()) {
2570  unsigned MoreStackForCalls = 0;
2571 
2572  for (auto &MBB : MF) {
2573  for (auto &MI : MBB) {
2574  if (!MI.isCall())
2575  continue;
2576 
2577  // Get callee operand.
2578  const MachineOperand &MO = MI.getOperand(0);
2579 
2580  // Only take account of global function calls (no closures etc.).
2581  if (!MO.isGlobal())
2582  continue;
2583 
2584  const Function *F = dyn_cast<Function>(MO.getGlobal());
2585  if (!F)
2586  continue;
2587 
2588  // Do not update 'MaxStack' for primitive and built-in functions
2589  // (encoded with names either starting with "erlang."/"bif_" or not
2590  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2591  // "_", such as the BIF "suspend_0") as they are executed on another
2592  // stack.
2593  if (F->getName().find("erlang.") != StringRef::npos ||
2594  F->getName().find("bif_") != StringRef::npos ||
2595  F->getName().find_first_of("._") == StringRef::npos)
2596  continue;
2597 
2598  unsigned CalleeStkArity =
2599  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2600  if (HipeLeafWords - 1 > CalleeStkArity)
2601  MoreStackForCalls = std::max(MoreStackForCalls,
2602  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2603  }
2604  }
2605  MaxStack += MoreStackForCalls;
2606  }
2607 
2608  // If the stack frame needed is larger than the guaranteed then runtime checks
2609  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2610  if (MaxStack > Guaranteed) {
2611  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2612  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2613 
2614  for (const auto &LI : PrologueMBB.liveins()) {
2615  stackCheckMBB->addLiveIn(LI);
2616  incStackMBB->addLiveIn(LI);
2617  }
2618 
2619  MF.push_front(incStackMBB);
2620  MF.push_front(stackCheckMBB);
2621 
2622  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2623  unsigned LEAop, CMPop, CALLop;
2624  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
2625  if (Is64Bit) {
2626  SPReg = X86::RSP;
2627  PReg = X86::RBP;
2628  LEAop = X86::LEA64r;
2629  CMPop = X86::CMP64rm;
2630  CALLop = X86::CALL64pcrel32;
2631  } else {
2632  SPReg = X86::ESP;
2633  PReg = X86::EBP;
2634  LEAop = X86::LEA32r;
2635  CMPop = X86::CMP32rm;
2636  CALLop = X86::CALLpcrel32;
2637  }
2638 
2639  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2640  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2641  "HiPE prologue scratch register is live-in");
2642 
2643  // Create new MBB for StackCheck:
2644  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2645  SPReg, false, -MaxStack);
2646  // SPLimitOffset is in a fixed heap location (pointed by BP).
2647  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2648  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2649  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2650 
2651  // Create new MBB for IncStack:
2652  BuildMI(incStackMBB, DL, TII.get(CALLop)).
2653  addExternalSymbol("inc_stack_0");
2654  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2655  SPReg, false, -MaxStack);
2656  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2657  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2658  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2659 
2660  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
2661  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
2662  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
2663  incStackMBB->addSuccessor(incStackMBB, {1, 100});
2664  }
2665 #ifdef EXPENSIVE_CHECKS
2666  MF.verify();
2667 #endif
2668 }
2669 
2670 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2672  const DebugLoc &DL,
2673  int Offset) const {
2674 
2675  if (Offset <= 0)
2676  return false;
2677 
2678  if (Offset % SlotSize)
2679  return false;
2680 
2681  int NumPops = Offset / SlotSize;
2682  // This is only worth it if we have at most 2 pops.
2683  if (NumPops != 1 && NumPops != 2)
2684  return false;
2685 
2686  // Handle only the trivial case where the adjustment directly follows
2687  // a call. This is the most common one, anyway.
2688  if (MBBI == MBB.begin())
2689  return false;
2690  MachineBasicBlock::iterator Prev = std::prev(MBBI);
2691  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2692  return false;
2693 
2694  unsigned Regs[2];
2695  unsigned FoundRegs = 0;
2696 
2697  auto &MRI = MBB.getParent()->getRegInfo();
2698  auto RegMask = Prev->getOperand(1);
2699 
2700  auto &RegClass =
2701  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2702  // Try to find up to NumPops free registers.
2703  for (auto Candidate : RegClass) {
2704 
2705  // Poor man's liveness:
2706  // Since we're immediately after a call, any register that is clobbered
2707  // by the call and not defined by it can be considered dead.
2708  if (!RegMask.clobbersPhysReg(Candidate))
2709  continue;
2710 
2711  // Don't clobber reserved registers
2712  if (MRI.isReserved(Candidate))
2713  continue;
2714 
2715  bool IsDef = false;
2716  for (const MachineOperand &MO : Prev->implicit_operands()) {
2717  if (MO.isReg() && MO.isDef() &&
2718  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
2719  IsDef = true;
2720  break;
2721  }
2722  }
2723 
2724  if (IsDef)
2725  continue;
2726 
2727  Regs[FoundRegs++] = Candidate;
2728  if (FoundRegs == (unsigned)NumPops)
2729  break;
2730  }
2731 
2732  if (FoundRegs == 0)
2733  return false;
2734 
2735  // If we found only one free register, but need two, reuse the same one twice.
2736  while (FoundRegs < (unsigned)NumPops)
2737  Regs[FoundRegs++] = Regs[0];
2738 
2739  for (int i = 0; i < NumPops; ++i)
2740  BuildMI(MBB, MBBI, DL,
2741  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2742 
2743  return true;
2744 }
2745 
2749  bool reserveCallFrame = hasReservedCallFrame(MF);
2750  unsigned Opcode = I->getOpcode();
2751  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2752  DebugLoc DL = I->getDebugLoc();
2753  uint64_t Amount = !reserveCallFrame ? TII.getFrameSize(*I) : 0;
2754  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2755  I = MBB.erase(I);
2756  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
2757 
2758  if (!reserveCallFrame) {
2759  // If the stack pointer can be changed after prologue, turn the
2760  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2761  // adjcallstackdown instruction into 'add ESP, <amt>'
2762 
2763  // We need to keep the stack aligned properly. To do this, we round the
2764  // amount of space needed for the outgoing arguments up to the next
2765  // alignment boundary.
2766  unsigned StackAlign = getStackAlignment();
2767  Amount = alignTo(Amount, StackAlign);
2768 
2769  MachineModuleInfo &MMI = MF.getMMI();
2770  const Function &F = MF.getFunction();
2771  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2772  bool DwarfCFI = !WindowsCFI &&
2773  (MMI.hasDebugInfo() || F.needsUnwindTableEntry());
2774 
2775  // If we have any exception handlers in this function, and we adjust
2776  // the SP before calls, we may need to indicate this to the unwinder
2777  // using GNU_ARGS_SIZE. Note that this may be necessary even when
2778  // Amount == 0, because the preceding function may have set a non-0
2779  // GNU_ARGS_SIZE.
2780  // TODO: We don't need to reset this between subsequent functions,
2781  // if it didn't change.
2782  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
2783 
2784  if (HasDwarfEHHandlers && !isDestroy &&
2786  BuildCFI(MBB, InsertPos, DL,
2787  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2788 
2789  if (Amount == 0)
2790  return I;
2791 
2792  // Factor out the amount that gets handled inside the sequence
2793  // (Pushes of argument for frame setup, callee pops for frame destroy)
2794  Amount -= InternalAmt;
2795 
2796  // TODO: This is needed only if we require precise CFA.
2797  // If this is a callee-pop calling convention, emit a CFA adjust for
2798  // the amount the callee popped.
2799  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
2800  BuildCFI(MBB, InsertPos, DL,
2801  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2802 
2803  // Add Amount to SP to destroy a frame, or subtract to setup.
2804  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
2805 
2806  if (StackAdjustment) {
2807  // Merge with any previous or following adjustment instruction. Note: the
2808  // instructions merged with here do not have CFI, so their stack
2809  // adjustments do not feed into CfaAdjustment.
2810  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
2811  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
2812 
2813  if (StackAdjustment) {
2814  if (!(F.hasMinSize() &&
2815  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
2816  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
2817  /*InEpilogue=*/false);
2818  }
2819  }
2820 
2821  if (DwarfCFI && !hasFP(MF)) {
2822  // If we don't have FP, but need to generate unwind information,
2823  // we need to set the correct CFA offset after the stack adjustment.
2824  // How much we adjust the CFA offset depends on whether we're emitting
2825  // CFI only for EH purposes or for debugging. EH only requires the CFA
2826  // offset to be correct at each call site, while for debugging we want
2827  // it to be more precise.
2828 
2829  int64_t CfaAdjustment = -StackAdjustment;
2830  // TODO: When not using precise CFA, we also need to adjust for the
2831  // InternalAmt here.
2832  if (CfaAdjustment) {
2833  BuildCFI(MBB, InsertPos, DL,
2835  CfaAdjustment));
2836  }
2837  }
2838 
2839  return I;
2840  }
2841 
2842  if (isDestroy && InternalAmt) {
2843  // If we are performing frame pointer elimination and if the callee pops
2844  // something off the stack pointer, add it back. We do this until we have
2845  // more advanced stack pointer tracking ability.
2846  // We are not tracking the stack pointer adjustment by the callee, so make
2847  // sure we restore the stack pointer immediately after the call, there may
2848  // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2851  while (CI != B && !std::prev(CI)->isCall())
2852  --CI;
2853  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
2854  }
2855 
2856  return I;
2857 }
2858 
2860  assert(MBB.getParent() && "Block is not attached to a function!");
2861  const MachineFunction &MF = *MBB.getParent();
2862  return !TRI->needsStackRealignment(MF) || !MBB.isLiveIn(X86::EFLAGS);
2863 }
2864 
2866  assert(MBB.getParent() && "Block is not attached to a function!");
2867 
2868  // Win64 has strict requirements in terms of epilogue and we are
2869  // not taking a chance at messing with them.
2870  // I.e., unless this block is already an exit block, we can't use
2871  // it as an epilogue.
2872  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
2873  return false;
2874 
2875  if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2876  return true;
2877 
2878  // If we cannot use LEA to adjust SP, we may need to use ADD, which
2879  // clobbers the EFLAGS. Check that we do not need to preserve it,
2880  // otherwise, conservatively assume this is not
2881  // safe to insert the epilogue here.
2883 }
2884 
2886  // If we may need to emit frameless compact unwind information, give
2887  // up as this is currently broken: PR25614.
2888  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF)) &&
2889  // The lowering of segmented stack and HiPE only support entry blocks
2890  // as prologue blocks: PR26107.
2891  // This limitation may be lifted if we fix:
2892  // - adjustForSegmentedStacks
2893  // - adjustForHiPEPrologue
2895  !MF.shouldSplitStack();
2896 }
2897 
2900  const DebugLoc &DL, bool RestoreSP) const {
2901  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2902  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2904  "restoring EBP/ESI on non-32-bit target");
2905 
2906  MachineFunction &MF = *MBB.getParent();
2907  unsigned FramePtr = TRI->getFrameRegister(MF);
2908  unsigned BasePtr = TRI->getBaseRegister();
2909  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
2910  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2911  MachineFrameInfo &MFI = MF.getFrameInfo();
2912 
2913  // FIXME: Don't set FrameSetup flag in catchret case.
2914 
2915  int FI = FuncInfo.EHRegNodeFrameIndex;
2916  int EHRegSize = MFI.getObjectSize(FI);
2917 
2918  if (RestoreSP) {
2919  // MOV32rm -EHRegSize(%ebp), %esp
2920  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2921  X86::EBP, true, -EHRegSize)
2923  }
2924 
2925  unsigned UsedReg;
2926  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2927  int EndOffset = -EHRegOffset - EHRegSize;
2928  FuncInfo.EHRegNodeEndOffset = EndOffset;
2929 
2930  if (UsedReg == FramePtr) {
2931  // ADD $offset, %ebp
2932  unsigned ADDri = getADDriOpcode(false, EndOffset);
2933  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2934  .addReg(FramePtr)
2935  .addImm(EndOffset)
2937  ->getOperand(3)
2938  .setIsDead();
2939  assert(EndOffset >= 0 &&
2940  "end of registration object above normal EBP position!");
2941  } else if (UsedReg == BasePtr) {
2942  // LEA offset(%ebp), %esi
2943  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2944  FramePtr, false, EndOffset)
2946  // MOV32rm SavedEBPOffset(%esi), %ebp
2947  assert(X86FI->getHasSEHFramePtrSave());
2948  int Offset =
2949  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2950  assert(UsedReg == BasePtr);
2951  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2952  UsedReg, true, Offset)
2954  } else {
2955  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2956  }
2957  return MBBI;
2958 }
2959 
2961  return TRI->getSlotSize();
2962 }
2963 
2965  const {
2966  return TRI->getDwarfRegNum(StackPtr, true);
2967 }
2968 
2969 namespace {
2970 // Struct used by orderFrameObjects to help sort the stack objects.
2971 struct X86FrameSortingObject {
2972  bool IsValid = false; // true if we care about this Object.
2973  unsigned ObjectIndex = 0; // Index of Object into MFI list.
2974  unsigned ObjectSize = 0; // Size of Object in bytes.
2975  unsigned ObjectAlignment = 1; // Alignment of Object in bytes.
2976  unsigned ObjectNumUses = 0; // Object static number of uses.
2977 };
2978 
2979 // The comparison function we use for std::sort to order our local
2980 // stack symbols. The current algorithm is to use an estimated
2981 // "density". This takes into consideration the size and number of
2982 // uses each object has in order to roughly minimize code size.
2983 // So, for example, an object of size 16B that is referenced 5 times
2984 // will get higher priority than 4 4B objects referenced 1 time each.
2985 // It's not perfect and we may be able to squeeze a few more bytes out of
2986 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
2987 // fringe end can have special consideration, given their size is less
2988 // important, etc.), but the algorithmic complexity grows too much to be
2989 // worth the extra gains we get. This gets us pretty close.
2990 // The final order leaves us with objects with highest priority going
2991 // at the end of our list.
2992 struct X86FrameSortingComparator {
2993  inline bool operator()(const X86FrameSortingObject &A,
2994  const X86FrameSortingObject &B) {
2995  uint64_t DensityAScaled, DensityBScaled;
2996 
2997  // For consistency in our comparison, all invalid objects are placed
2998  // at the end. This also allows us to stop walking when we hit the
2999  // first invalid item after it's all sorted.
3000  if (!A.IsValid)
3001  return false;
3002  if (!B.IsValid)
3003  return true;
3004 
3005  // The density is calculated by doing :
3006  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3007  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3008  // Since this approach may cause inconsistencies in
3009  // the floating point <, >, == comparisons, depending on the floating
3010  // point model with which the compiler was built, we're going
3011  // to scale both sides by multiplying with
3012  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3013  // the division and, with it, the need for any floating point
3014  // arithmetic.
3015  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3016  static_cast<uint64_t>(B.ObjectSize);
3017  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3018  static_cast<uint64_t>(A.ObjectSize);
3019 
3020  // If the two densities are equal, prioritize highest alignment
3021  // objects. This allows for similar alignment objects
3022  // to be packed together (given the same density).
3023  // There's room for improvement here, also, since we can pack
3024  // similar alignment (different density) objects next to each
3025  // other to save padding. This will also require further
3026  // complexity/iterations, and the overall gain isn't worth it,
3027  // in general. Something to keep in mind, though.
3028  if (DensityAScaled == DensityBScaled)
3029  return A.ObjectAlignment < B.ObjectAlignment;
3030 
3031  return DensityAScaled < DensityBScaled;
3032  }
3033 };
3034 } // namespace
3035 
3036 // Order the symbols in the local stack.
3037 // We want to place the local stack objects in some sort of sensible order.
3038 // The heuristic we use is to try and pack them according to static number
3039 // of uses and size of object in order to minimize code size.
3041  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3042  const MachineFrameInfo &MFI = MF.getFrameInfo();
3043 
3044  // Don't waste time if there's nothing to do.
3045  if (ObjectsToAllocate.empty())
3046  return;
3047 
3048  // Create an array of all MFI objects. We won't need all of these
3049  // objects, but we're going to create a full array of them to make
3050  // it easier to index into when we're counting "uses" down below.
3051  // We want to be able to easily/cheaply access an object by simply
3052  // indexing into it, instead of having to search for it every time.
3053  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3054 
3055  // Walk the objects we care about and mark them as such in our working
3056  // struct.
3057  for (auto &Obj : ObjectsToAllocate) {
3058  SortingObjects[Obj].IsValid = true;
3059  SortingObjects[Obj].ObjectIndex = Obj;
3060  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlignment(Obj);
3061  // Set the size.
3062  int ObjectSize = MFI.getObjectSize(Obj);
3063  if (ObjectSize == 0)
3064  // Variable size. Just use 4.
3065  SortingObjects[Obj].ObjectSize = 4;
3066  else
3067  SortingObjects[Obj].ObjectSize = ObjectSize;
3068  }
3069 
3070  // Count the number of uses for each object.
3071  for (auto &MBB : MF) {
3072  for (auto &MI : MBB) {
3073  if (MI.isDebugInstr())
3074  continue;
3075  for (const MachineOperand &MO : MI.operands()) {
3076  // Check to see if it's a local stack symbol.
3077  if (!MO.isFI())
3078  continue;
3079  int Index = MO.getIndex();
3080  // Check to see if it falls within our range, and is tagged
3081  // to require ordering.
3082  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3083  SortingObjects[Index].IsValid)
3084  SortingObjects[Index].ObjectNumUses++;
3085  }
3086  }
3087  }
3088 
3089  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3090  // info).
3091  std::stable_sort(SortingObjects.begin(), SortingObjects.end(),
3092  X86FrameSortingComparator());
3093 
3094  // Now modify the original list to represent the final order that
3095  // we want. The order will depend on whether we're going to access them
3096  // from the stack pointer or the frame pointer. For SP, the list should
3097  // end up with the END containing objects that we want with smaller offsets.
3098  // For FP, it should be flipped.
3099  int i = 0;
3100  for (auto &Obj : SortingObjects) {
3101  // All invalid items are sorted at the end, so it's safe to stop.
3102  if (!Obj.IsValid)
3103  break;
3104  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3105  }
3106 
3107  // Flip it if we're accessing off of the FP.
3108  if (!TRI->needsStackRealignment(MF) && hasFP(MF))
3109  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3110 }
3111 
3112 
3114  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3115  unsigned Offset = 16;
3116  // RBP is immediately pushed.
3117  Offset += SlotSize;
3118  // All callee-saved registers are then pushed.
3119  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3120  // Every funclet allocates enough stack space for the largest outgoing call.
3121  Offset += getWinEHFuncletFrameSize(MF);
3122  return Offset;
3123 }
3124 
3126  MachineFunction &MF, RegScavenger *RS) const {
3127  // Mark the function as not having WinCFI. We will set it back to true in
3128  // emitPrologue if it gets called and emits CFI.
3129  MF.setHasWinCFI(false);
3130 
3131  // If this function isn't doing Win64-style C++ EH, we don't need to do
3132  // anything.
3133  const Function &F = MF.getFunction();
3134  if (!STI.is64Bit() || !MF.hasEHFunclets() ||
3136  return;
3137 
3138  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3139  // relative to RSP after the prologue. Find the offset of the last fixed
3140  // object, so that we can allocate a slot immediately following it. If there
3141  // were no fixed objects, use offset -SlotSize, which is immediately after the
3142  // return address. Fixed objects have negative frame indices.
3143  MachineFrameInfo &MFI = MF.getFrameInfo();
3144  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3145  int64_t MinFixedObjOffset = -SlotSize;
3146  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3147  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3148 
3149  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3150  for (WinEHHandlerType &H : TBME.HandlerArray) {
3151  int FrameIndex = H.CatchObj.FrameIndex;
3152  if (FrameIndex != INT_MAX) {
3153  // Ensure alignment.
3154  unsigned Align = MFI.getObjectAlignment(FrameIndex);
3155  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3156  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3157  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3158  }
3159  }
3160  }
3161 
3162  // Ensure alignment.
3163  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3164  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3165  int UnwindHelpFI =
3166  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*Immutable=*/false);
3167  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3168 
3169  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3170  // other frame setup instructions.
3171  MachineBasicBlock &MBB = MF.front();
3172  auto MBBI = MBB.begin();
3173  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3174  ++MBBI;
3175 
3176  DebugLoc DL = MBB.findDebugLoc(MBBI);
3177  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3178  UnwindHelpFI)
3179  .addImm(-2);
3180 }
void push_front(MachineBasicBlock *MBB)
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:476
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:527
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:583
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:397
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
MachineBasicBlock * getMBB() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1080
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSWindows() const
Definition: X86Subtarget.h:776
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:486
bool hasStackObjects() const
Return true if there are any stack objects in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
static unsigned getLEArOpcode(unsigned IsLP64)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:504
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned Reg
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
void setCalleeSavedFrameSize(unsigned bytes)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
arg_iterator arg_end()
Definition: Function.h:682
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1068
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:173
static BranchProbability getOne()
bool isTargetNaCl64() const
Definition: X86Subtarget.h:746
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:491
unsigned getSlotSize() const
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:498
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:750
X86FrameLowering(const X86Subtarget &STI, unsigned StackAlignOverride)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:694
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A tuple of MDNodes.
Definition: Metadata.h:1325
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:546
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool is32Bit() const
Definition: X86Subtarget.h:531
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
iterator_range< iterator > terminators()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime...
unsigned getNumOperands() const
Definition: Metadata.cpp:1076
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static const uint64_t kSplitStackAvailable
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getBaseRegister() const
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const override
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
Definition: ARMWinEH.h:196
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool needsFrameIndexResolution(const MachineFunction &MF) const override
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
const MCContext & getContext() const
int getObjectIndexBegin() const
Return the minimum frame object index.
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:250
static unsigned getHiPELiteral(NamedMDNode *HiPELiteralsMD, const StringRef LiteralName)
Lookup an ERTS parameter in the !hipe.literals named metadata node.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:704
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
Value wrapper in the Metadata hierarchy.
Definition: Metadata.h:338
static unsigned calculateSetFPREG(uint64_t SPAdjust)
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getKillRegState(bool B)
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:468
unsigned getStackRegister() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getInitialCFARegister(const MachineFunction &MF) const override
Return initial CFA register value i.e.
StringRef getString() const
Definition: Metadata.cpp:463
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:529
unsigned getDefRegState(bool B)
The memory access is volatile.
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:482
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:477
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:484
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:355
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasEHFunclets() const
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const GlobalValue * getGlobal() const
const X86InstrInfo & TII
#define H(x, y, z)
Definition: MD5.cpp:57
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:570
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
MCRegAliasIterator enumerates all registers aliasing Reg.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
bool useLeaForSP() const
Definition: X86Subtarget.h:631
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
unsigned getFramePtr() const
Returns physical register used as frame pointer.
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:731
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const Triple & getTargetTriple() const
size_t arg_size() const
Definition: Function.h:700
arg_iterator arg_begin()
Definition: Function.h:673
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
union llvm::WinEHHandlerType::@197 CatchObj
The CatchObj starts out life as an LLVM alloca and is eventually turned frame index.
bool isTargetDarwin() const
Definition: X86Subtarget.h:730
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:679
bool isTargetWin64() const
Definition: X86Subtarget.h:778
This class contains a discriminated union of information about pointers in memory operands...
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm)
static bool isFuncletReturnInstr(MachineInstr &MI)
static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const
Emit target stack probe code.
The memory access writes data.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
const X86Subtarget & STI
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value...
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool isTargetWin32() const
Definition: X86Subtarget.h:780
int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling...
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:152
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
bool callsUnwindInit() const
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
IterT skipDebugInstructionsBackward(IterT It, IterT Begin)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:540
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:572
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isTailCallOpcode(unsigned Opc)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
CodeModel::Model getCodeModel() const
Returns the code model.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:690
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
static const size_t npos
Definition: StringRef.h:50
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTargetDragonFly() const
Definition: X86Subtarget.h:732
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
LLVM_NODISCARD size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
Definition: StringRef.h:380
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Pair of physical register and lane mask.
virtual const TargetFrameLowering * getFrameLowering() const
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:597
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
void setCVBytesOfCalleeSavedRegisters(unsigned S)
uint32_t Size
Definition: Profile.cpp:46
static unsigned getSUBrrOpcode(unsigned isLP64)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const X86RegisterInfo * TRI
const Module * getModule() const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
CallingConvention
Definition: Dwarf.h:202
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isEAXLiveIn(MachineBasicBlock &MBB)
static unsigned getADDrrOpcode(unsigned isLP64)
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1302
bool isTargetLinux() const
Definition: X86Subtarget.h:740
static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const X86RegisterInfo *TRI, bool Is64Bit)
findDeadCallerSavedReg - Return a caller-saved register that isn&#39;t live when it reaches the "return" ...
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:791
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
int getInitialCFAOffset(const MachineFunction &MF) const override
Return initial CFA offset value i.e.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasBWI() const
Definition: X86Subtarget.h:663
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
A single uniqued string.
Definition: Metadata.h:603
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL) const
unsigned getFrameRegister(const MachineFunction &MF) const override
static BranchProbability getZero()
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
DWARF-like instruction based exceptions.
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1074
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static bool HasNestArgument(const MachineFunction *MF)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
Function Alias Analysis false
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:758