LLVM  9.0.0svn
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/Debug.h"
33 #include <cstdlib>
34 
35 using namespace llvm;
36 
38  unsigned StackAlignOverride)
39  : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40  STI.is64Bit() ? -8 : -4),
41  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42  // Cache a bunch of frame-related predicates for this subtarget.
44  Is64Bit = STI.is64Bit();
45  IsLP64 = STI.isTarget64BitLP64();
46  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
49 }
50 
52  return !MF.getFrameInfo().hasVarSizedObjects() &&
53  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
54 }
55 
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
60 bool
62  return hasReservedCallFrame(MF) ||
63  (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64  TRI->hasBasePointer(MF);
65 }
66 
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
74 bool
76  return MF.getFrameInfo().hasStackObjects() ||
77  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
78 }
79 
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
84  const MachineFrameInfo &MFI = MF.getFrameInfo();
85  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
86  TRI->needsStackRealignment(MF) ||
87  MFI.hasVarSizedObjects() ||
89  MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
90  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
91  MFI.hasStackMap() || MFI.hasPatchPoint() ||
93 }
94 
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
96  if (IsLP64) {
97  if (isInt<8>(Imm))
98  return X86::SUB64ri8;
99  return X86::SUB64ri32;
100  } else {
101  if (isInt<8>(Imm))
102  return X86::SUB32ri8;
103  return X86::SUB32ri;
104  }
105 }
106 
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
108  if (IsLP64) {
109  if (isInt<8>(Imm))
110  return X86::ADD64ri8;
111  return X86::ADD64ri32;
112  } else {
113  if (isInt<8>(Imm))
114  return X86::ADD32ri8;
115  return X86::ADD32ri;
116  }
117 }
118 
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120  return isLP64 ? X86::SUB64rr : X86::SUB32rr;
121 }
122 
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124  return isLP64 ? X86::ADD64rr : X86::ADD32rr;
125 }
126 
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
128  if (IsLP64) {
129  if (isInt<8>(Imm))
130  return X86::AND64ri8;
131  return X86::AND64ri32;
132  }
133  if (isInt<8>(Imm))
134  return X86::AND32ri8;
135  return X86::AND32ri;
136 }
137 
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139  return IsLP64 ? X86::LEA64r : X86::LEA32r;
140 }
141 
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
147  const X86RegisterInfo *TRI,
148  bool Is64Bit) {
149  const MachineFunction *MF = MBB.getParent();
150  if (MF->callsEHReturn())
151  return 0;
152 
153  const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
154 
155  if (MBBI == MBB.end())
156  return 0;
157 
158  switch (MBBI->getOpcode()) {
159  default: return 0;
160  case TargetOpcode::PATCHABLE_RET:
161  case X86::RET:
162  case X86::RETL:
163  case X86::RETQ:
164  case X86::RETIL:
165  case X86::RETIQ:
166  case X86::TCRETURNdi:
167  case X86::TCRETURNri:
168  case X86::TCRETURNmi:
169  case X86::TCRETURNdi64:
170  case X86::TCRETURNri64:
171  case X86::TCRETURNmi64:
172  case X86::EH_RETURN:
173  case X86::EH_RETURN64: {
175  for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
176  MachineOperand &MO = MBBI->getOperand(i);
177  if (!MO.isReg() || MO.isDef())
178  continue;
179  unsigned Reg = MO.getReg();
180  if (!Reg)
181  continue;
182  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
183  Uses.insert(*AI);
184  }
185 
186  for (auto CS : AvailableRegs)
187  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
188  CS != X86::ESP)
189  return CS;
190  }
191  }
192 
193  return 0;
194 }
195 
196 static bool isEAXLiveIn(MachineBasicBlock &MBB) {
197  for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
198  unsigned Reg = RegMask.PhysReg;
199 
200  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
201  Reg == X86::AH || Reg == X86::AL)
202  return true;
203  }
204 
205  return false;
206 }
207 
208 /// Check if the flags need to be preserved before the terminators.
209 /// This would be the case, if the eflags is live-in of the region
210 /// composed by the terminators or live-out of that region, without
211 /// being defined by a terminator.
212 static bool
214  for (const MachineInstr &MI : MBB.terminators()) {
215  bool BreakNext = false;
216  for (const MachineOperand &MO : MI.operands()) {
217  if (!MO.isReg())
218  continue;
219  unsigned Reg = MO.getReg();
220  if (Reg != X86::EFLAGS)
221  continue;
222 
223  // This terminator needs an eflags that is not defined
224  // by a previous another terminator:
225  // EFLAGS is live-in of the region composed by the terminators.
226  if (!MO.isDef())
227  return true;
228  // This terminator defines the eflags, i.e., we don't need to preserve it.
229  // However, we still need to check this specific terminator does not
230  // read a live-in value.
231  BreakNext = true;
232  }
233  // We found a definition of the eflags, no need to preserve them.
234  if (BreakNext)
235  return false;
236  }
237 
238  // None of the terminators use or define the eflags.
239  // Check if they are live-out, that would imply we need to preserve them.
240  for (const MachineBasicBlock *Succ : MBB.successors())
241  if (Succ->isLiveIn(X86::EFLAGS))
242  return true;
243 
244  return false;
245 }
246 
247 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
248 /// stack pointer by a constant value.
251  const DebugLoc &DL,
252  int64_t NumBytes, bool InEpilogue) const {
253  bool isSub = NumBytes < 0;
254  uint64_t Offset = isSub ? -NumBytes : NumBytes;
257 
258  uint64_t Chunk = (1LL << 31) - 1;
259 
260  if (Offset > Chunk) {
261  // Rather than emit a long series of instructions for large offsets,
262  // load the offset into a register and do one sub/add
263  unsigned Reg = 0;
264  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
265 
266  if (isSub && !isEAXLiveIn(MBB))
267  Reg = Rax;
268  else
269  Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
270 
271  unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
272  unsigned AddSubRROpc =
274  if (Reg) {
275  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
276  .addImm(Offset)
277  .setMIFlag(Flag);
278  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
279  .addReg(StackPtr)
280  .addReg(Reg);
281  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
282  return;
283  } else if (Offset > 8 * Chunk) {
284  // If we would need more than 8 add or sub instructions (a >16GB stack
285  // frame), it's worth spilling RAX to materialize this immediate.
286  // pushq %rax
287  // movabsq +-$Offset+-SlotSize, %rax
288  // addq %rsp, %rax
289  // xchg %rax, (%rsp)
290  // movq (%rsp), %rsp
291  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
292  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
293  .addReg(Rax, RegState::Kill)
294  .setMIFlag(Flag);
295  // Subtract is not commutative, so negate the offset and always use add.
296  // Subtract 8 less and add 8 more to account for the PUSH we just did.
297  if (isSub)
298  Offset = -(Offset - SlotSize);
299  else
300  Offset = Offset + SlotSize;
301  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
302  .addImm(Offset)
303  .setMIFlag(Flag);
304  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
305  .addReg(Rax)
306  .addReg(StackPtr);
307  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
308  // Exchange the new SP in RAX with the top of the stack.
309  addRegOffset(
310  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
311  StackPtr, false, 0);
312  // Load new SP from the top of the stack into RSP.
313  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
314  StackPtr, false, 0);
315  return;
316  }
317  }
318 
319  while (Offset) {
320  uint64_t ThisVal = std::min(Offset, Chunk);
321  if (ThisVal == SlotSize) {
322  // Use push / pop for slot sized adjustments as a size optimization. We
323  // need to find a dead register when using pop.
324  unsigned Reg = isSub
325  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
326  : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
327  if (Reg) {
328  unsigned Opc = isSub
329  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
330  : (Is64Bit ? X86::POP64r : X86::POP32r);
331  BuildMI(MBB, MBBI, DL, TII.get(Opc))
332  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
333  .setMIFlag(Flag);
334  Offset -= ThisVal;
335  continue;
336  }
337  }
338 
339  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
340  .setMIFlag(Flag);
341 
342  Offset -= ThisVal;
343  }
344 }
345 
346 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
348  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
349  assert(Offset != 0 && "zero offset stack adjustment requested");
350 
351  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
352  // is tricky.
353  bool UseLEA;
354  if (!InEpilogue) {
355  // Check if inserting the prologue at the beginning
356  // of MBB would require to use LEA operations.
357  // We need to use LEA operations if EFLAGS is live in, because
358  // it means an instruction will read it before it gets defined.
359  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
360  } else {
361  // If we can use LEA for SP but we shouldn't, check that none
362  // of the terminators uses the eflags. Otherwise we will insert
363  // a ADD that will redefine the eflags and break the condition.
364  // Alternatively, we could move the ADD, but this may not be possible
365  // and is an optimization anyway.
366  UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
367  if (UseLEA && !STI.useLeaForSP())
369  // If that assert breaks, that means we do not do the right thing
370  // in canUseAsEpilogue.
372  "We shouldn't have allowed this insertion point");
373  }
374 
376  if (UseLEA) {
377  MI = addRegOffset(BuildMI(MBB, MBBI, DL,
379  StackPtr),
380  StackPtr, false, Offset);
381  } else {
382  bool IsSub = Offset < 0;
383  uint64_t AbsOffset = IsSub ? -Offset : Offset;
384  unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
385  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
386  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
387  .addReg(StackPtr)
388  .addImm(AbsOffset);
389  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
390  }
391  return MI;
392 }
393 
396  bool doMergeWithPrevious) const {
397  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
398  (!doMergeWithPrevious && MBBI == MBB.end()))
399  return 0;
400 
401  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
402 
403  PI = skipDebugInstructionsBackward(PI, MBB.begin());
404  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
405  // instruction, and that there are no DBG_VALUE or other instructions between
406  // ADD/SUB/LEA and its corresponding CFI instruction.
407  /* TODO: Add support for the case where there are multiple CFI instructions
408  below the ADD/SUB/LEA, e.g.:
409  ...
410  add
411  cfi_def_cfa_offset
412  cfi_offset
413  ...
414  */
415  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
416  PI = std::prev(PI);
417 
418  unsigned Opc = PI->getOpcode();
419  int Offset = 0;
420 
421  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
422  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
423  PI->getOperand(0).getReg() == StackPtr){
424  assert(PI->getOperand(1).getReg() == StackPtr);
425  Offset = PI->getOperand(2).getImm();
426  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
427  PI->getOperand(0).getReg() == StackPtr &&
428  PI->getOperand(1).getReg() == StackPtr &&
429  PI->getOperand(2).getImm() == 1 &&
430  PI->getOperand(3).getReg() == X86::NoRegister &&
431  PI->getOperand(5).getReg() == X86::NoRegister) {
432  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
433  Offset = PI->getOperand(4).getImm();
434  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
435  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
436  PI->getOperand(0).getReg() == StackPtr) {
437  assert(PI->getOperand(1).getReg() == StackPtr);
438  Offset = -PI->getOperand(2).getImm();
439  } else
440  return 0;
441 
442  PI = MBB.erase(PI);
443  if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
444  if (!doMergeWithPrevious)
445  MBBI = skipDebugInstructionsForward(PI, MBB.end());
446 
447  return Offset;
448 }
449 
452  const DebugLoc &DL,
453  const MCCFIInstruction &CFIInst) const {
454  MachineFunction &MF = *MBB.getParent();
455  unsigned CFIIndex = MF.addFrameInst(CFIInst);
456  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
457  .addCFIIndex(CFIIndex);
458 }
459 
462  const DebugLoc &DL) const {
463  MachineFunction &MF = *MBB.getParent();
464  MachineFrameInfo &MFI = MF.getFrameInfo();
465  MachineModuleInfo &MMI = MF.getMMI();
466  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
467 
468  // Add callee saved registers to move list.
469  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
470  if (CSI.empty()) return;
471 
472  // Calculate offsets.
473  for (std::vector<CalleeSavedInfo>::const_iterator
474  I = CSI.begin(), E = CSI.end(); I != E; ++I) {
475  int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
476  unsigned Reg = I->getReg();
477 
478  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
479  BuildCFI(MBB, MBBI, DL,
480  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
481  }
482 }
483 
485  MachineBasicBlock &MBB,
487  const DebugLoc &DL, bool InProlog) const {
488  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
489  if (STI.isTargetWindowsCoreCLR()) {
490  if (InProlog) {
491  emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
492  } else {
493  emitStackProbeInline(MF, MBB, MBBI, DL, false);
494  }
495  } else {
496  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
497  }
498 }
499 
501  MachineBasicBlock &PrologMBB) const {
502  const StringRef ChkStkStubSymbol = "__chkstk_stub";
503  MachineInstr *ChkStkStub = nullptr;
504 
505  for (MachineInstr &MI : PrologMBB) {
506  if (MI.isCall() && MI.getOperand(0).isSymbol() &&
507  ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
508  ChkStkStub = &MI;
509  break;
510  }
511  }
512 
513  if (ChkStkStub != nullptr) {
514  assert(!ChkStkStub->isBundled() &&
515  "Not expecting bundled instructions here");
516  MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
517  assert(std::prev(MBBI) == ChkStkStub &&
518  "MBBI expected after __chkstk_stub.");
519  DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
520  emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
521  ChkStkStub->eraseFromParent();
522  }
523 }
524 
525 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
526  MachineBasicBlock &MBB,
528  const DebugLoc &DL,
529  bool InProlog) const {
530  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
531  assert(STI.is64Bit() && "different expansion needed for 32 bit");
532  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
533  const TargetInstrInfo &TII = *STI.getInstrInfo();
534  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
535 
536  // RAX contains the number of bytes of desired stack adjustment.
537  // The handling here assumes this value has already been updated so as to
538  // maintain stack alignment.
539  //
540  // We need to exit with RSP modified by this amount and execute suitable
541  // page touches to notify the OS that we're growing the stack responsibly.
542  // All stack probing must be done without modifying RSP.
543  //
544  // MBB:
545  // SizeReg = RAX;
546  // ZeroReg = 0
547  // CopyReg = RSP
548  // Flags, TestReg = CopyReg - SizeReg
549  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
550  // LimitReg = gs magic thread env access
551  // if FinalReg >= LimitReg goto ContinueMBB
552  // RoundBB:
553  // RoundReg = page address of FinalReg
554  // LoopMBB:
555  // LoopReg = PHI(LimitReg,ProbeReg)
556  // ProbeReg = LoopReg - PageSize
557  // [ProbeReg] = 0
558  // if (ProbeReg > RoundReg) goto LoopMBB
559  // ContinueMBB:
560  // RSP = RSP - RAX
561  // [rest of original MBB]
562 
563  // Set up the new basic blocks
564  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
565  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
566  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
567 
568  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
569  MF.insert(MBBIter, RoundMBB);
570  MF.insert(MBBIter, LoopMBB);
571  MF.insert(MBBIter, ContinueMBB);
572 
573  // Split MBB and move the tail portion down to ContinueMBB.
574  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
575  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
576  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
577 
578  // Some useful constants
579  const int64_t ThreadEnvironmentStackLimit = 0x10;
580  const int64_t PageSize = 0x1000;
581  const int64_t PageMask = ~(PageSize - 1);
582 
583  // Registers we need. For the normal case we use virtual
584  // registers. For the prolog expansion we use RAX, RCX and RDX.
586  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
587  const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
588  : MRI.createVirtualRegister(RegClass),
589  ZeroReg = InProlog ? (unsigned)X86::RCX
590  : MRI.createVirtualRegister(RegClass),
591  CopyReg = InProlog ? (unsigned)X86::RDX
592  : MRI.createVirtualRegister(RegClass),
593  TestReg = InProlog ? (unsigned)X86::RDX
594  : MRI.createVirtualRegister(RegClass),
595  FinalReg = InProlog ? (unsigned)X86::RDX
596  : MRI.createVirtualRegister(RegClass),
597  RoundedReg = InProlog ? (unsigned)X86::RDX
598  : MRI.createVirtualRegister(RegClass),
599  LimitReg = InProlog ? (unsigned)X86::RCX
600  : MRI.createVirtualRegister(RegClass),
601  JoinReg = InProlog ? (unsigned)X86::RCX
602  : MRI.createVirtualRegister(RegClass),
603  ProbeReg = InProlog ? (unsigned)X86::RCX
604  : MRI.createVirtualRegister(RegClass);
605 
606  // SP-relative offsets where we can save RCX and RDX.
607  int64_t RCXShadowSlot = 0;
608  int64_t RDXShadowSlot = 0;
609 
610  // If inlining in the prolog, save RCX and RDX.
611  if (InProlog) {
612  // Compute the offsets. We need to account for things already
613  // pushed onto the stack at this point: return address, frame
614  // pointer (if used), and callee saves.
616  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
617  const bool HasFP = hasFP(MF);
618 
619  // Check if we need to spill RCX and/or RDX.
620  // Here we assume that no earlier prologue instruction changes RCX and/or
621  // RDX, so checking the block live-ins is enough.
622  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
623  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
624  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
625  // Assign the initial slot to both registers, then change RDX's slot if both
626  // need to be spilled.
627  if (IsRCXLiveIn)
628  RCXShadowSlot = InitSlot;
629  if (IsRDXLiveIn)
630  RDXShadowSlot = InitSlot;
631  if (IsRDXLiveIn && IsRCXLiveIn)
632  RDXShadowSlot += 8;
633  // Emit the saves if needed.
634  if (IsRCXLiveIn)
635  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
636  RCXShadowSlot)
637  .addReg(X86::RCX);
638  if (IsRDXLiveIn)
639  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
640  RDXShadowSlot)
641  .addReg(X86::RDX);
642  } else {
643  // Not in the prolog. Copy RAX to a virtual reg.
644  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
645  }
646 
647  // Add code to MBB to check for overflow and set the new target stack pointer
648  // to zero if so.
649  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
650  .addReg(ZeroReg, RegState::Undef)
651  .addReg(ZeroReg, RegState::Undef);
652  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
653  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
654  .addReg(CopyReg)
655  .addReg(SizeReg);
656  BuildMI(&MBB, DL, TII.get(X86::CMOVB64rr), FinalReg)
657  .addReg(TestReg)
658  .addReg(ZeroReg);
659 
660  // FinalReg now holds final stack pointer value, or zero if
661  // allocation would overflow. Compare against the current stack
662  // limit from the thread environment block. Note this limit is the
663  // lowest touched page on the stack, not the point at which the OS
664  // will cause an overflow exception, so this is just an optimization
665  // to avoid unnecessarily touching pages that are below the current
666  // SP but already committed to the stack by the OS.
667  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
668  .addReg(0)
669  .addImm(1)
670  .addReg(0)
671  .addImm(ThreadEnvironmentStackLimit)
672  .addReg(X86::GS);
673  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
674  // Jump if the desired stack pointer is at or above the stack limit.
675  BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
676 
677  // Add code to roundMBB to round the final stack pointer to a page boundary.
678  RoundMBB->addLiveIn(FinalReg);
679  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
680  .addReg(FinalReg)
681  .addImm(PageMask);
682  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
683 
684  // LimitReg now holds the current stack limit, RoundedReg page-rounded
685  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
686  // and probe until we reach RoundedReg.
687  if (!InProlog) {
688  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
689  .addReg(LimitReg)
690  .addMBB(RoundMBB)
691  .addReg(ProbeReg)
692  .addMBB(LoopMBB);
693  }
694 
695  LoopMBB->addLiveIn(JoinReg);
696  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
697  false, -PageSize);
698 
699  // Probe by storing a byte onto the stack.
700  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
701  .addReg(ProbeReg)
702  .addImm(1)
703  .addReg(0)
704  .addImm(0)
705  .addReg(0)
706  .addImm(0);
707 
708  LoopMBB->addLiveIn(RoundedReg);
709  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
710  .addReg(RoundedReg)
711  .addReg(ProbeReg);
712  BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
713 
714  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
715 
716  // If in prolog, restore RDX and RCX.
717  if (InProlog) {
718  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
719  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
720  TII.get(X86::MOV64rm), X86::RCX),
721  X86::RSP, false, RCXShadowSlot);
722  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
723  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
724  TII.get(X86::MOV64rm), X86::RDX),
725  X86::RSP, false, RDXShadowSlot);
726  }
727 
728  // Now that the probing is done, add code to continueMBB to update
729  // the stack pointer for real.
730  ContinueMBB->addLiveIn(SizeReg);
731  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
732  .addReg(X86::RSP)
733  .addReg(SizeReg);
734 
735  // Add the control flow edges we need.
736  MBB.addSuccessor(ContinueMBB);
737  MBB.addSuccessor(RoundMBB);
738  RoundMBB->addSuccessor(LoopMBB);
739  LoopMBB->addSuccessor(ContinueMBB);
740  LoopMBB->addSuccessor(LoopMBB);
741 
742  // Mark all the instructions added to the prolog as frame setup.
743  if (InProlog) {
744  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
745  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
746  }
747  for (MachineInstr &MI : *RoundMBB) {
748  MI.setFlag(MachineInstr::FrameSetup);
749  }
750  for (MachineInstr &MI : *LoopMBB) {
751  MI.setFlag(MachineInstr::FrameSetup);
752  }
753  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
754  CMBBI != ContinueMBBI; ++CMBBI) {
755  CMBBI->setFlag(MachineInstr::FrameSetup);
756  }
757  }
758 }
759 
760 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
761  MachineBasicBlock &MBB,
763  const DebugLoc &DL,
764  bool InProlog) const {
765  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
766 
767  // FIXME: Add retpoline support and remove this.
768  if (Is64Bit && IsLargeCodeModel && STI.useRetpolineIndirectCalls())
769  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
770  "code model and retpoline not yet implemented.");
771 
772  unsigned CallOp;
773  if (Is64Bit)
774  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
775  else
776  CallOp = X86::CALLpcrel32;
777 
779 
781  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
782 
783  // All current stack probes take AX and SP as input, clobber flags, and
784  // preserve all registers. x86_64 probes leave RSP unmodified.
785  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
786  // For the large code model, we have to call through a register. Use R11,
787  // as it is scratch in all supported calling conventions.
788  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
789  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
790  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
791  } else {
792  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
793  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
794  }
795 
796  unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
797  unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
798  CI.addReg(AX, RegState::Implicit)
802  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
803 
804  if (STI.isTargetWin64() || !STI.isOSWindows()) {
805  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
806  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
807  // themselves. They also does not clobber %rax so we can reuse it when
808  // adjusting %rsp.
809  // All other platforms do not specify a particular ABI for the stack probe
810  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
811  BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Is64Bit)), SP)
812  .addReg(SP)
813  .addReg(AX);
814  }
815 
816  if (InProlog) {
817  // Apply the frame setup flag to all inserted instrs.
818  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
819  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
820  }
821 }
822 
823 void X86FrameLowering::emitStackProbeInlineStub(
825  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
826 
827  assert(InProlog && "ChkStkStub called outside prolog!");
828 
829  BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
830  .addExternalSymbol("__chkstk_stub");
831 }
832 
833 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
834  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
835  // and might require smaller successive adjustments.
836  const uint64_t Win64MaxSEHOffset = 128;
837  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
838  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
839  return SEHFrameOffset & -16;
840 }
841 
842 // If we're forcing a stack realignment we can't rely on just the frame
843 // info, we need to know the ABI stack alignment as well in case we
844 // have a call out. Otherwise just make sure we have some alignment - we'll
845 // go with the minimum SlotSize.
846 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
847  const MachineFrameInfo &MFI = MF.getFrameInfo();
848  uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
849  unsigned StackAlign = getStackAlignment();
850  if (MF.getFunction().hasFnAttribute("stackrealign")) {
851  if (MFI.hasCalls())
852  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
853  else if (MaxAlign < SlotSize)
854  MaxAlign = SlotSize;
855  }
856  return MaxAlign;
857 }
858 
859 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
861  const DebugLoc &DL, unsigned Reg,
862  uint64_t MaxAlign) const {
863  uint64_t Val = -MaxAlign;
864  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
865  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
866  .addReg(Reg)
867  .addImm(Val)
869 
870  // The EFLAGS implicit def is dead.
871  MI->getOperand(3).setIsDead();
872 }
873 
874 /// emitPrologue - Push callee-saved registers onto the stack, which
875 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
876 /// space for local variables. Also emit labels used by the exception handler to
877 /// generate the exception handling frames.
878 
879 /*
880  Here's a gist of what gets emitted:
881 
882  ; Establish frame pointer, if needed
883  [if needs FP]
884  push %rbp
885  .cfi_def_cfa_offset 16
886  .cfi_offset %rbp, -16
887  .seh_pushreg %rpb
888  mov %rsp, %rbp
889  .cfi_def_cfa_register %rbp
890 
891  ; Spill general-purpose registers
892  [for all callee-saved GPRs]
893  pushq %<reg>
894  [if not needs FP]
895  .cfi_def_cfa_offset (offset from RETADDR)
896  .seh_pushreg %<reg>
897 
898  ; If the required stack alignment > default stack alignment
899  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
900  ; of unknown size in the stack frame.
901  [if stack needs re-alignment]
902  and $MASK, %rsp
903 
904  ; Allocate space for locals
905  [if target is Windows and allocated space > 4096 bytes]
906  ; Windows needs special care for allocations larger
907  ; than one page.
908  mov $NNN, %rax
909  call ___chkstk_ms/___chkstk
910  sub %rax, %rsp
911  [else]
912  sub $NNN, %rsp
913 
914  [if needs FP]
915  .seh_stackalloc (size of XMM spill slots)
916  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
917  [else]
918  .seh_stackalloc NNN
919 
920  ; Spill XMMs
921  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
922  ; they may get spilled on any platform, if the current function
923  ; calls @llvm.eh.unwind.init
924  [if needs FP]
925  [for all callee-saved XMM registers]
926  movaps %<xmm reg>, -MMM(%rbp)
927  [for all callee-saved XMM registers]
928  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
929  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
930  [else]
931  [for all callee-saved XMM registers]
932  movaps %<xmm reg>, KKK(%rsp)
933  [for all callee-saved XMM registers]
934  .seh_savexmm %<xmm reg>, KKK
935 
936  .seh_endprologue
937 
938  [if needs base pointer]
939  mov %rsp, %rbx
940  [if needs to restore base pointer]
941  mov %rsp, -MMM(%rbp)
942 
943  ; Emit CFI info
944  [if needs FP]
945  [for all callee-saved registers]
946  .cfi_offset %<reg>, (offset from %rbp)
947  [else]
948  .cfi_def_cfa_offset (offset from RETADDR)
949  [for all callee-saved registers]
950  .cfi_offset %<reg>, (offset from %rsp)
951 
952  Notes:
953  - .seh directives are emitted only for Windows 64 ABI
954  - .cv_fpo directives are emitted on win32 when emitting CodeView
955  - .cfi directives are emitted for all other ABIs
956  - for 32-bit code, substitute %e?? registers for %r??
957 */
958 
960  MachineBasicBlock &MBB) const {
961  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
962  "MF used frame lowering for wrong subtarget");
963  MachineBasicBlock::iterator MBBI = MBB.begin();
964  MachineFrameInfo &MFI = MF.getFrameInfo();
965  const Function &Fn = MF.getFunction();
966  MachineModuleInfo &MMI = MF.getMMI();
968  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
969  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
970  bool IsFunclet = MBB.isEHFuncletEntry();
972  if (Fn.hasPersonalityFn())
973  Personality = classifyEHPersonality(Fn.getPersonalityFn());
974  bool FnHasClrFunclet =
975  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
976  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
977  bool HasFP = hasFP(MF);
978  bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
979  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
980  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
981  // FIXME: Emit FPO data for EH funclets.
982  bool NeedsWinFPO =
983  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
984  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
985  bool NeedsDwarfCFI =
986  !IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
987  unsigned FramePtr = TRI->getFrameRegister(MF);
988  const unsigned MachineFramePtr =
990  ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
991  unsigned BasePtr = TRI->getBaseRegister();
992  bool HasWinCFI = false;
993 
994  // Debug location must be unknown since the first debug location is used
995  // to determine the end of the prologue.
996  DebugLoc DL;
997 
998  // Add RETADDR move area to callee saved frame size.
999  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1000  if (TailCallReturnAddrDelta && IsWin64Prologue)
1001  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1002 
1003  if (TailCallReturnAddrDelta < 0)
1004  X86FI->setCalleeSavedFrameSize(
1005  X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
1006 
1007  bool UseStackProbe = !STI.getTargetLowering()->getStackProbeSymbolName(MF).empty();
1008 
1009  // The default stack probe size is 4096 if the function has no stackprobesize
1010  // attribute.
1011  unsigned StackProbeSize = 4096;
1012  if (Fn.hasFnAttribute("stack-probe-size"))
1013  Fn.getFnAttribute("stack-probe-size")
1014  .getValueAsString()
1015  .getAsInteger(0, StackProbeSize);
1016 
1017  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1018  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1019  // stack alignment.
1020  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1021  Fn.arg_size() == 2) {
1022  StackSize += 8;
1023  MFI.setStackSize(StackSize);
1024  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1025  }
1026 
1027  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1028  // function, and use up to 128 bytes of stack space, don't have a frame
1029  // pointer, calls, or dynamic alloca then we do not need to adjust the
1030  // stack pointer (we fit in the Red Zone). We also check that we don't
1031  // push and pop from the stack.
1032  if (Is64Bit && !Fn.hasFnAttribute(Attribute::NoRedZone) &&
1033  !TRI->needsStackRealignment(MF) &&
1034  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1035  !MFI.adjustsStack() && // No calls.
1036  !UseStackProbe && // No stack probes.
1037  !IsWin64CC && // Win64 has no Red Zone
1038  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1039  !MF.shouldSplitStack()) { // Regular stack
1040  uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
1041  if (HasFP) MinSize += SlotSize;
1042  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1043  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1044  MFI.setStackSize(StackSize);
1045  }
1046 
1047  // Insert stack pointer adjustment for later moving of return addr. Only
1048  // applies to tail call optimized functions where the callee argument stack
1049  // size is bigger than the callers.
1050  if (TailCallReturnAddrDelta < 0) {
1051  BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
1052  /*InEpilogue=*/false)
1054  }
1055 
1056  // Mapping for machine moves:
1057  //
1058  // DST: VirtualFP AND
1059  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1060  // ELSE => DW_CFA_def_cfa
1061  //
1062  // SRC: VirtualFP AND
1063  // DST: Register => DW_CFA_def_cfa_register
1064  //
1065  // ELSE
1066  // OFFSET < 0 => DW_CFA_offset_extended_sf
1067  // REG < 64 => DW_CFA_offset + Reg
1068  // ELSE => DW_CFA_offset_extended
1069 
1070  uint64_t NumBytes = 0;
1071  int stackGrowth = -SlotSize;
1072 
1073  // Find the funclet establisher parameter
1074  unsigned Establisher = X86::NoRegister;
1075  if (IsClrFunclet)
1076  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1077  else if (IsFunclet)
1078  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1079 
1080  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1081  // Immediately spill establisher into the home slot.
1082  // The runtime cares about this.
1083  // MOV64mr %rdx, 16(%rsp)
1084  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1085  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1086  .addReg(Establisher)
1088  MBB.addLiveIn(Establisher);
1089  }
1090 
1091  if (HasFP) {
1092  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1093 
1094  // Calculate required stack adjustment.
1095  uint64_t FrameSize = StackSize - SlotSize;
1096  // If required, include space for extra hidden slot for stashing base pointer.
1097  if (X86FI->getRestoreBasePointer())
1098  FrameSize += SlotSize;
1099 
1100  NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1101 
1102  // Callee-saved registers are pushed on stack before the stack is realigned.
1103  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1104  NumBytes = alignTo(NumBytes, MaxAlign);
1105 
1106  // Save EBP/RBP into the appropriate stack slot.
1107  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1108  .addReg(MachineFramePtr, RegState::Kill)
1110 
1111  if (NeedsDwarfCFI) {
1112  // Mark the place where EBP/RBP was saved.
1113  // Define the current CFA rule to use the provided offset.
1114  assert(StackSize);
1115  BuildCFI(MBB, MBBI, DL,
1116  MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1117 
1118  // Change the rule for the FramePtr to be an "offset" rule.
1119  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1121  nullptr, DwarfFramePtr, 2 * stackGrowth));
1122  }
1123 
1124  if (NeedsWinCFI) {
1125  HasWinCFI = true;
1126  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1127  .addImm(FramePtr)
1129  }
1130 
1131  if (!IsWin64Prologue && !IsFunclet) {
1132  // Update EBP with the new base value.
1133  BuildMI(MBB, MBBI, DL,
1134  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1135  FramePtr)
1136  .addReg(StackPtr)
1138 
1139  if (NeedsDwarfCFI) {
1140  // Mark effective beginning of when frame pointer becomes valid.
1141  // Define the current CFA to use the EBP/RBP register.
1142  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1144  nullptr, DwarfFramePtr));
1145  }
1146 
1147  if (NeedsWinFPO) {
1148  // .cv_fpo_setframe $FramePtr
1149  HasWinCFI = true;
1150  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1151  .addImm(FramePtr)
1152  .addImm(0)
1154  }
1155  }
1156  } else {
1157  assert(!IsFunclet && "funclets without FPs not yet implemented");
1158  NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1159  }
1160 
1161  // Update the offset adjustment, which is mainly used by codeview to translate
1162  // from ESP to VFRAME relative local variable offsets.
1163  if (!IsFunclet) {
1164  if (HasFP && TRI->needsStackRealignment(MF))
1165  MFI.setOffsetAdjustment(-NumBytes);
1166  else
1167  MFI.setOffsetAdjustment(-StackSize);
1168  }
1169 
1170  // For EH funclets, only allocate enough space for outgoing calls. Save the
1171  // NumBytes value that we would've used for the parent frame.
1172  unsigned ParentFrameNumBytes = NumBytes;
1173  if (IsFunclet)
1174  NumBytes = getWinEHFuncletFrameSize(MF);
1175 
1176  // Skip the callee-saved push instructions.
1177  bool PushedRegs = false;
1178  int StackOffset = 2 * stackGrowth;
1179 
1180  while (MBBI != MBB.end() &&
1181  MBBI->getFlag(MachineInstr::FrameSetup) &&
1182  (MBBI->getOpcode() == X86::PUSH32r ||
1183  MBBI->getOpcode() == X86::PUSH64r)) {
1184  PushedRegs = true;
1185  unsigned Reg = MBBI->getOperand(0).getReg();
1186  ++MBBI;
1187 
1188  if (!HasFP && NeedsDwarfCFI) {
1189  // Mark callee-saved push instruction.
1190  // Define the current CFA rule to use the provided offset.
1191  assert(StackSize);
1192  BuildCFI(MBB, MBBI, DL,
1193  MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1194  StackOffset += stackGrowth;
1195  }
1196 
1197  if (NeedsWinCFI) {
1198  HasWinCFI = true;
1199  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1200  .addImm(Reg)
1202  }
1203  }
1204 
1205  // Realign stack after we pushed callee-saved registers (so that we'll be
1206  // able to calculate their offsets from the frame pointer).
1207  // Don't do this for Win64, it needs to realign the stack after the prologue.
1208  if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1209  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1210  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1211 
1212  if (NeedsWinCFI) {
1213  HasWinCFI = true;
1214  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1215  .addImm(MaxAlign)
1217  }
1218  }
1219 
1220  // If there is an SUB32ri of ESP immediately before this instruction, merge
1221  // the two. This can be the case when tail call elimination is enabled and
1222  // the callee has more arguments then the caller.
1223  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1224 
1225  // Adjust stack pointer: ESP -= numbytes.
1226 
1227  // Windows and cygwin/mingw require a prologue helper routine when allocating
1228  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1229  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1230  // stack and adjust the stack pointer in one go. The 64-bit version of
1231  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1232  // responsible for adjusting the stack pointer. Touching the stack at 4K
1233  // increments is necessary to ensure that the guard pages used by the OS
1234  // virtual memory manager are allocated in correct sequence.
1235  uint64_t AlignedNumBytes = NumBytes;
1236  if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1237  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1238  if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1239  assert(!X86FI->getUsesRedZone() &&
1240  "The Red Zone is not accounted for in stack probes");
1241 
1242  // Check whether EAX is livein for this block.
1243  bool isEAXAlive = isEAXLiveIn(MBB);
1244 
1245  if (isEAXAlive) {
1246  if (Is64Bit) {
1247  // Save RAX
1248  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1249  .addReg(X86::RAX, RegState::Kill)
1251  } else {
1252  // Save EAX
1253  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1254  .addReg(X86::EAX, RegState::Kill)
1256  }
1257  }
1258 
1259  if (Is64Bit) {
1260  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1261  // Function prologue is responsible for adjusting the stack pointer.
1262  int Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1263  if (isUInt<32>(Alloc)) {
1264  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1265  .addImm(Alloc)
1267  } else if (isInt<32>(Alloc)) {
1268  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1269  .addImm(Alloc)
1271  } else {
1272  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1273  .addImm(Alloc)
1275  }
1276  } else {
1277  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1278  // We'll also use 4 already allocated bytes for EAX.
1279  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1280  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1282  }
1283 
1284  // Call __chkstk, __chkstk_ms, or __alloca.
1285  emitStackProbe(MF, MBB, MBBI, DL, true);
1286 
1287  if (isEAXAlive) {
1288  // Restore RAX/EAX
1289  MachineInstr *MI;
1290  if (Is64Bit)
1291  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1292  StackPtr, false, NumBytes - 8);
1293  else
1294  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1295  StackPtr, false, NumBytes - 4);
1297  MBB.insert(MBBI, MI);
1298  }
1299  } else if (NumBytes) {
1300  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1301  }
1302 
1303  if (NeedsWinCFI && NumBytes) {
1304  HasWinCFI = true;
1305  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1306  .addImm(NumBytes)
1308  }
1309 
1310  int SEHFrameOffset = 0;
1311  unsigned SPOrEstablisher;
1312  if (IsFunclet) {
1313  if (IsClrFunclet) {
1314  // The establisher parameter passed to a CLR funclet is actually a pointer
1315  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1316  // to find the root function establisher frame by loading the PSPSym from
1317  // the intermediate frame.
1318  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1319  MachinePointerInfo NoInfo;
1320  MBB.addLiveIn(Establisher);
1321  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1322  Establisher, false, PSPSlotOffset)
1325  ;
1326  // Save the root establisher back into the current funclet's (mostly
1327  // empty) frame, in case a sub-funclet or the GC needs it.
1328  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1329  false, PSPSlotOffset)
1330  .addReg(Establisher)
1331  .addMemOperand(
1334  SlotSize, SlotSize));
1335  }
1336  SPOrEstablisher = Establisher;
1337  } else {
1338  SPOrEstablisher = StackPtr;
1339  }
1340 
1341  if (IsWin64Prologue && HasFP) {
1342  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1343  // this calculation on the incoming establisher, which holds the value of
1344  // RSP from the parent frame at the end of the prologue.
1345  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1346  if (SEHFrameOffset)
1347  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1348  SPOrEstablisher, false, SEHFrameOffset);
1349  else
1350  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1351  .addReg(SPOrEstablisher);
1352 
1353  // If this is not a funclet, emit the CFI describing our frame pointer.
1354  if (NeedsWinCFI && !IsFunclet) {
1355  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1356  HasWinCFI = true;
1357  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1358  .addImm(FramePtr)
1359  .addImm(SEHFrameOffset)
1361  if (isAsynchronousEHPersonality(Personality))
1362  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1363  }
1364  } else if (IsFunclet && STI.is32Bit()) {
1365  // Reset EBP / ESI to something good for funclets.
1366  MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1367  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1368  // into the registration node so that the runtime will restore it for us.
1369  if (!MBB.isCleanupFuncletEntry()) {
1370  assert(Personality == EHPersonality::MSVC_CXX);
1371  unsigned FrameReg;
1372  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1373  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg);
1374  // ESP is the first field, so no extra displacement is needed.
1375  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1376  false, EHRegOffset)
1377  .addReg(X86::ESP);
1378  }
1379  }
1380 
1381  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1382  const MachineInstr &FrameInstr = *MBBI;
1383  ++MBBI;
1384 
1385  if (NeedsWinCFI) {
1386  int FI;
1387  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1388  if (X86::FR64RegClass.contains(Reg)) {
1389  unsigned IgnoredFrameReg;
1390  int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1391  Offset += SEHFrameOffset;
1392 
1393  HasWinCFI = true;
1394  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1395  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1396  .addImm(Reg)
1397  .addImm(Offset)
1399  }
1400  }
1401  }
1402  }
1403 
1404  if (NeedsWinCFI && HasWinCFI)
1405  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1406  .setMIFlag(MachineInstr::FrameSetup);
1407 
1408  if (FnHasClrFunclet && !IsFunclet) {
1409  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1410  // immediately after the prolog) into the PSPSlot so that funclets
1411  // and the GC can recover it.
1412  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1413  auto PSPInfo = MachinePointerInfo::getFixedStack(
1414  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1415  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1416  PSPSlotOffset)
1417  .addReg(StackPtr)
1420  SlotSize, SlotSize));
1421  }
1422 
1423  // Realign stack after we spilled callee-saved registers (so that we'll be
1424  // able to calculate their offsets from the frame pointer).
1425  // Win64 requires aligning the stack after the prologue.
1426  if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1427  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1428  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1429  }
1430 
1431  // We already dealt with stack realignment and funclets above.
1432  if (IsFunclet && STI.is32Bit())
1433  return;
1434 
1435  // If we need a base pointer, set it up here. It's whatever the value
1436  // of the stack pointer is at this point. Any variable size objects
1437  // will be allocated after this, so we can still use the base pointer
1438  // to reference locals.
1439  if (TRI->hasBasePointer(MF)) {
1440  // Update the base pointer with the current stack pointer.
1441  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1442  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1443  .addReg(SPOrEstablisher)
1445  if (X86FI->getRestoreBasePointer()) {
1446  // Stash value of base pointer. Saving RSP instead of EBP shortens
1447  // dependence chain. Used by SjLj EH.
1448  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1449  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1450  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1451  .addReg(SPOrEstablisher)
1453  }
1454 
1455  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1456  // Stash the value of the frame pointer relative to the base pointer for
1457  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1458  // it recovers the frame pointer from the base pointer rather than the
1459  // other way around.
1460  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1461  unsigned UsedReg;
1462  int Offset =
1463  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1464  assert(UsedReg == BasePtr);
1465  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1466  .addReg(FramePtr)
1468  }
1469  }
1470 
1471  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1472  // Mark end of stack pointer adjustment.
1473  if (!HasFP && NumBytes) {
1474  // Define the current CFA rule to use the provided offset.
1475  assert(StackSize);
1477  nullptr, -StackSize + stackGrowth));
1478  }
1479 
1480  // Emit DWARF info specifying the offsets of the callee-saved registers.
1481  emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1482  }
1483 
1484  // X86 Interrupt handling function cannot assume anything about the direction
1485  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1486  // in each prologue of interrupt handler function.
1487  //
1488  // FIXME: Create "cld" instruction only in these cases:
1489  // 1. The interrupt handling function uses any of the "rep" instructions.
1490  // 2. Interrupt handling function calls another function.
1491  //
1493  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1494  .setMIFlag(MachineInstr::FrameSetup);
1495 
1496  // At this point we know if the function has WinCFI or not.
1497  MF.setHasWinCFI(HasWinCFI);
1498 }
1499 
1501  const MachineFunction &MF) const {
1502  // We can't use LEA instructions for adjusting the stack pointer if we don't
1503  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1504  // to deallocate the stack.
1505  // This means that we can use LEA for SP in two situations:
1506  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1507  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1508  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1509 }
1510 
1512  switch (MI.getOpcode()) {
1513  case X86::CATCHRET:
1514  case X86::CLEANUPRET:
1515  return true;
1516  default:
1517  return false;
1518  }
1519  llvm_unreachable("impossible");
1520 }
1521 
1522 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1523 // stack. It holds a pointer to the bottom of the root function frame. The
1524 // establisher frame pointer passed to a nested funclet may point to the
1525 // (mostly empty) frame of its parent funclet, but it will need to find
1526 // the frame of the root function to access locals. To facilitate this,
1527 // every funclet copies the pointer to the bottom of the root function
1528 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1529 // same offset for the PSPSym in the root function frame that's used in the
1530 // funclets' frames allows each funclet to dynamically accept any ancestor
1531 // frame as its establisher argument (the runtime doesn't guarantee the
1532 // immediate parent for some reason lost to history), and also allows the GC,
1533 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1534 // frame with only a single offset reported for the entire method.
1535 unsigned
1536 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1537  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1538  unsigned SPReg;
1540  /*IgnoreSPUpdates*/ true);
1541  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1542  return static_cast<unsigned>(Offset);
1543 }
1544 
1545 unsigned
1546 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1547  // This is the size of the pushed CSRs.
1548  unsigned CSSize =
1549  MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1550  // This is the amount of stack a funclet needs to allocate.
1551  unsigned UsedSize;
1552  EHPersonality Personality =
1554  if (Personality == EHPersonality::CoreCLR) {
1555  // CLR funclets need to hold enough space to include the PSPSym, at the
1556  // same offset from the stack pointer (immediately after the prolog) as it
1557  // resides at in the main function.
1558  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1559  } else {
1560  // Other funclets just need enough stack for outgoing call arguments.
1561  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1562  }
1563  // RBP is not included in the callee saved register block. After pushing RBP,
1564  // everything is 16 byte aligned. Everything we allocate before an outgoing
1565  // call must also be 16 byte aligned.
1566  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
1567  // Subtract out the size of the callee saved registers. This is how much stack
1568  // each funclet will allocate.
1569  return FrameSizeMinusRBP - CSSize;
1570 }
1571 
1572 static bool isTailCallOpcode(unsigned Opc) {
1573  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
1574  Opc == X86::TCRETURNmi ||
1575  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
1576  Opc == X86::TCRETURNmi64;
1577 }
1578 
1580  MachineBasicBlock &MBB) const {
1581  const MachineFrameInfo &MFI = MF.getFrameInfo();
1585  DebugLoc DL;
1586  if (MBBI != MBB.end())
1587  DL = MBBI->getDebugLoc();
1588  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1589  const bool Is64BitILP32 = STI.isTarget64BitILP32();
1590  unsigned FramePtr = TRI->getFrameRegister(MF);
1591  unsigned MachineFramePtr =
1592  Is64BitILP32 ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
1593 
1594  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1595  bool NeedsWin64CFI =
1596  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
1597  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
1598 
1599  // Get the number of bytes to allocate from the FrameInfo.
1600  uint64_t StackSize = MFI.getStackSize();
1601  uint64_t MaxAlign = calculateMaxStackAlign(MF);
1602  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1603  bool HasFP = hasFP(MF);
1604  uint64_t NumBytes = 0;
1605 
1606  bool NeedsDwarfCFI =
1607  (!MF.getTarget().getTargetTriple().isOSDarwin() &&
1608  !MF.getTarget().getTargetTriple().isOSWindows()) &&
1610 
1611  if (IsFunclet) {
1612  assert(HasFP && "EH funclets without FP not yet implemented");
1613  NumBytes = getWinEHFuncletFrameSize(MF);
1614  } else if (HasFP) {
1615  // Calculate required stack adjustment.
1616  uint64_t FrameSize = StackSize - SlotSize;
1617  NumBytes = FrameSize - CSSize;
1618 
1619  // Callee-saved registers were pushed on stack before the stack was
1620  // realigned.
1621  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1622  NumBytes = alignTo(FrameSize, MaxAlign);
1623  } else {
1624  NumBytes = StackSize - CSSize;
1625  }
1626  uint64_t SEHStackAllocAmt = NumBytes;
1627 
1628  if (HasFP) {
1629  // Pop EBP.
1630  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1631  MachineFramePtr)
1632  .setMIFlag(MachineInstr::FrameDestroy);
1633  if (NeedsDwarfCFI) {
1634  unsigned DwarfStackPtr =
1635  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
1637  nullptr, DwarfStackPtr, -SlotSize));
1638  --MBBI;
1639  }
1640  }
1641 
1642  MachineBasicBlock::iterator FirstCSPop = MBBI;
1643  // Skip the callee-saved pop instructions.
1644  while (MBBI != MBB.begin()) {
1645  MachineBasicBlock::iterator PI = std::prev(MBBI);
1646  unsigned Opc = PI->getOpcode();
1647 
1648  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1649  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1650  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1651  break;
1652  FirstCSPop = PI;
1653  }
1654 
1655  --MBBI;
1656  }
1657  MBBI = FirstCSPop;
1658 
1659  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1660  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
1661 
1662  if (MBBI != MBB.end())
1663  DL = MBBI->getDebugLoc();
1664 
1665  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1666  // instruction, merge the two instructions.
1667  if (NumBytes || MFI.hasVarSizedObjects())
1668  NumBytes += mergeSPUpdates(MBB, MBBI, true);
1669 
1670  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1671  // slot before popping them off! Same applies for the case, when stack was
1672  // realigned. Don't do this if this was a funclet epilogue, since the funclets
1673  // will not do realignment or dynamic stack allocation.
1674  if ((TRI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) &&
1675  !IsFunclet) {
1676  if (TRI->needsStackRealignment(MF))
1677  MBBI = FirstCSPop;
1678  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1679  uint64_t LEAAmount =
1680  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1681 
1682  // There are only two legal forms of epilogue:
1683  // - add SEHAllocationSize, %rsp
1684  // - lea SEHAllocationSize(%FramePtr), %rsp
1685  //
1686  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1687  // However, we may use this sequence if we have a frame pointer because the
1688  // effects of the prologue can safely be undone.
1689  if (LEAAmount != 0) {
1690  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1691  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1692  FramePtr, false, LEAAmount);
1693  --MBBI;
1694  } else {
1695  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1696  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1697  .addReg(FramePtr);
1698  --MBBI;
1699  }
1700  } else if (NumBytes) {
1701  // Adjust stack pointer back: ESP += numbytes.
1702  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
1703  if (!hasFP(MF) && NeedsDwarfCFI) {
1704  // Define the current CFA rule to use the provided offset.
1706  nullptr, -CSSize - SlotSize));
1707  }
1708  --MBBI;
1709  }
1710 
1711  // Windows unwinder will not invoke function's exception handler if IP is
1712  // either in prologue or in epilogue. This behavior causes a problem when a
1713  // call immediately precedes an epilogue, because the return address points
1714  // into the epilogue. To cope with that, we insert an epilogue marker here,
1715  // then replace it with a 'nop' if it ends up immediately after a CALL in the
1716  // final emitted code.
1717  if (NeedsWin64CFI && MF.hasWinCFI())
1718  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1719 
1720  if (!hasFP(MF) && NeedsDwarfCFI) {
1721  MBBI = FirstCSPop;
1722  int64_t Offset = -CSSize - SlotSize;
1723  // Mark callee-saved pop instruction.
1724  // Define the current CFA rule to use the provided offset.
1725  while (MBBI != MBB.end()) {
1726  MachineBasicBlock::iterator PI = MBBI;
1727  unsigned Opc = PI->getOpcode();
1728  ++MBBI;
1729  if (Opc == X86::POP32r || Opc == X86::POP64r) {
1730  Offset += SlotSize;
1731  BuildCFI(MBB, MBBI, DL,
1732  MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
1733  }
1734  }
1735  }
1736 
1737  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
1738  // Add the return addr area delta back since we are not tail calling.
1739  int Offset = -1 * X86FI->getTCReturnAddrDelta();
1740  assert(Offset >= 0 && "TCDelta should never be positive");
1741  if (Offset) {
1742  // Check for possible merge with preceding ADD instruction.
1743  Offset += mergeSPUpdates(MBB, Terminator, true);
1744  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
1745  }
1746  }
1747 }
1748 
1750  unsigned &FrameReg) const {
1751  const MachineFrameInfo &MFI = MF.getFrameInfo();
1752 
1753  bool IsFixed = MFI.isFixedObjectIndex(FI);
1754  // We can't calculate offset from frame pointer if the stack is realigned,
1755  // so enforce usage of stack/base pointer. The base pointer is used when we
1756  // have dynamic allocas in addition to dynamic realignment.
1757  if (TRI->hasBasePointer(MF))
1758  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
1759  else if (TRI->needsStackRealignment(MF))
1760  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
1761  else
1762  FrameReg = TRI->getFrameRegister(MF);
1763 
1764  // Offset will hold the offset from the stack pointer at function entry to the
1765  // object.
1766  // We need to factor in additional offsets applied during the prologue to the
1767  // frame, base, and stack pointer depending on which is used.
1768  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
1770  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1771  uint64_t StackSize = MFI.getStackSize();
1772  bool HasFP = hasFP(MF);
1773  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1774  int64_t FPDelta = 0;
1775 
1776  if (IsWin64Prologue) {
1777  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
1778 
1779  // Calculate required stack adjustment.
1780  uint64_t FrameSize = StackSize - SlotSize;
1781  // If required, include space for extra hidden slot for stashing base pointer.
1782  if (X86FI->getRestoreBasePointer())
1783  FrameSize += SlotSize;
1784  uint64_t NumBytes = FrameSize - CSSize;
1785 
1786  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1787  if (FI && FI == X86FI->getFAIndex())
1788  return -SEHFrameOffset;
1789 
1790  // FPDelta is the offset from the "traditional" FP location of the old base
1791  // pointer followed by return address and the location required by the
1792  // restricted Win64 prologue.
1793  // Add FPDelta to all offsets below that go through the frame pointer.
1794  FPDelta = FrameSize - SEHFrameOffset;
1795  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
1796  "FPDelta isn't aligned per the Win64 ABI!");
1797  }
1798 
1799 
1800  if (TRI->hasBasePointer(MF)) {
1801  assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1802  if (FI < 0) {
1803  // Skip the saved EBP.
1804  return Offset + SlotSize + FPDelta;
1805  } else {
1806  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1807  return Offset + StackSize;
1808  }
1809  } else if (TRI->needsStackRealignment(MF)) {
1810  if (FI < 0) {
1811  // Skip the saved EBP.
1812  return Offset + SlotSize + FPDelta;
1813  } else {
1814  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1815  return Offset + StackSize;
1816  }
1817  // FIXME: Support tail calls
1818  } else {
1819  if (!HasFP)
1820  return Offset + StackSize;
1821 
1822  // Skip the saved EBP.
1823  Offset += SlotSize;
1824 
1825  // Skip the RETADDR move area
1826  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1827  if (TailCallReturnAddrDelta < 0)
1828  Offset -= TailCallReturnAddrDelta;
1829  }
1830 
1831  return Offset + FPDelta;
1832 }
1833 
1835  int FI, unsigned &FrameReg,
1836  int Adjustment) const {
1837  const MachineFrameInfo &MFI = MF.getFrameInfo();
1838  FrameReg = TRI->getStackRegister();
1839  return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment;
1840 }
1841 
1842 int
1844  int FI, unsigned &FrameReg,
1845  bool IgnoreSPUpdates) const {
1846 
1847  const MachineFrameInfo &MFI = MF.getFrameInfo();
1848  // Does not include any dynamic realign.
1849  const uint64_t StackSize = MFI.getStackSize();
1850  // LLVM arranges the stack as follows:
1851  // ...
1852  // ARG2
1853  // ARG1
1854  // RETADDR
1855  // PUSH RBP <-- RBP points here
1856  // PUSH CSRs
1857  // ~~~~~~~ <-- possible stack realignment (non-win64)
1858  // ...
1859  // STACK OBJECTS
1860  // ... <-- RSP after prologue points here
1861  // ~~~~~~~ <-- possible stack realignment (win64)
1862  //
1863  // if (hasVarSizedObjects()):
1864  // ... <-- "base pointer" (ESI/RBX) points here
1865  // DYNAMIC ALLOCAS
1866  // ... <-- RSP points here
1867  //
1868  // Case 1: In the simple case of no stack realignment and no dynamic
1869  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1870  // with fixed offsets from RSP.
1871  //
1872  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1873  // stack objects are addressed with RBP and regular stack objects with RSP.
1874  //
1875  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1876  // to address stack arguments for outgoing calls and nothing else. The "base
1877  // pointer" points to local variables, and RBP points to fixed objects.
1878  //
1879  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1880  // answer we give is relative to the SP after the prologue, and not the
1881  // SP in the middle of the function.
1882 
1883  if (MFI.isFixedObjectIndex(FI) && TRI->needsStackRealignment(MF) &&
1884  !STI.isTargetWin64())
1885  return getFrameIndexReference(MF, FI, FrameReg);
1886 
1887  // If !hasReservedCallFrame the function might have SP adjustement in the
1888  // body. So, even though the offset is statically known, it depends on where
1889  // we are in the function.
1891  if (!IgnoreSPUpdates && !TFI->hasReservedCallFrame(MF))
1892  return getFrameIndexReference(MF, FI, FrameReg);
1893 
1894  // We don't handle tail calls, and shouldn't be seeing them either.
1896  "we don't handle this case!");
1897 
1898  // This is how the math works out:
1899  //
1900  // %rsp grows (i.e. gets lower) left to right. Each box below is
1901  // one word (eight bytes). Obj0 is the stack slot we're trying to
1902  // get to.
1903  //
1904  // ----------------------------------
1905  // | BP | Obj0 | Obj1 | ... | ObjN |
1906  // ----------------------------------
1907  // ^ ^ ^ ^
1908  // A B C E
1909  //
1910  // A is the incoming stack pointer.
1911  // (B - A) is the local area offset (-8 for x86-64) [1]
1912  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
1913  //
1914  // |(E - B)| is the StackSize (absolute value, positive). For a
1915  // stack that grown down, this works out to be (B - E). [3]
1916  //
1917  // E is also the value of %rsp after stack has been set up, and we
1918  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1919  // (C - E) == (C - A) - (B - A) + (B - E)
1920  // { Using [1], [2] and [3] above }
1921  // == getObjectOffset - LocalAreaOffset + StackSize
1922 
1923  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
1924 }
1925 
1928  std::vector<CalleeSavedInfo> &CSI) const {
1929  MachineFrameInfo &MFI = MF.getFrameInfo();
1931 
1932  unsigned CalleeSavedFrameSize = 0;
1933  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1934 
1935  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1936 
1937  if (TailCallReturnAddrDelta < 0) {
1938  // create RETURNADDR area
1939  // arg
1940  // arg
1941  // RETADDR
1942  // { ...
1943  // RETADDR area
1944  // ...
1945  // }
1946  // [EBP]
1947  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
1948  TailCallReturnAddrDelta - SlotSize, true);
1949  }
1950 
1951  // Spill the BasePtr if it's used.
1952  if (this->TRI->hasBasePointer(MF)) {
1953  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1954  if (MF.hasEHFunclets()) {
1955  int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
1956  X86FI->setHasSEHFramePtrSave(true);
1957  X86FI->setSEHFramePtrSaveIndex(FI);
1958  }
1959  }
1960 
1961  if (hasFP(MF)) {
1962  // emitPrologue always spills frame register the first thing.
1963  SpillSlotOffset -= SlotSize;
1964  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1965 
1966  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1967  // the frame register, we can delete it from CSI list and not have to worry
1968  // about avoiding it later.
1969  unsigned FPReg = TRI->getFrameRegister(MF);
1970  for (unsigned i = 0; i < CSI.size(); ++i) {
1971  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1972  CSI.erase(CSI.begin() + i);
1973  break;
1974  }
1975  }
1976  }
1977 
1978  // Assign slots for GPRs. It increases frame size.
1979  for (unsigned i = CSI.size(); i != 0; --i) {
1980  unsigned Reg = CSI[i - 1].getReg();
1981 
1982  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1983  continue;
1984 
1985  SpillSlotOffset -= SlotSize;
1986  CalleeSavedFrameSize += SlotSize;
1987 
1988  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1989  CSI[i - 1].setFrameIdx(SlotIndex);
1990  }
1991 
1992  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1993  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
1994 
1995  // Assign slots for XMMs.
1996  for (unsigned i = CSI.size(); i != 0; --i) {
1997  unsigned Reg = CSI[i - 1].getReg();
1998  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1999  continue;
2000 
2001  // If this is k-register make sure we lookup via the largest legal type.
2002  MVT VT = MVT::Other;
2003  if (X86::VK16RegClass.contains(Reg))
2004  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2005 
2006  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2007  unsigned Size = TRI->getSpillSize(*RC);
2008  unsigned Align = TRI->getSpillAlignment(*RC);
2009  // ensure alignment
2010  SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
2011  // spill into slot
2012  SpillSlotOffset -= Size;
2013  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2014  CSI[i - 1].setFrameIdx(SlotIndex);
2015  MFI.ensureMaxAlignment(Align);
2016  }
2017 
2018  return true;
2019 }
2020 
2023  const std::vector<CalleeSavedInfo> &CSI,
2024  const TargetRegisterInfo *TRI) const {
2025  DebugLoc DL = MBB.findDebugLoc(MI);
2026 
2027  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2028  // for us, and there are no XMM CSRs on Win32.
2029  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2030  return true;
2031 
2032  // Push GPRs. It increases frame size.
2033  const MachineFunction &MF = *MBB.getParent();
2034  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2035  for (unsigned i = CSI.size(); i != 0; --i) {
2036  unsigned Reg = CSI[i - 1].getReg();
2037 
2038  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2039  continue;
2040 
2041  const MachineRegisterInfo &MRI = MF.getRegInfo();
2042  bool isLiveIn = MRI.isLiveIn(Reg);
2043  if (!isLiveIn)
2044  MBB.addLiveIn(Reg);
2045 
2046  // Decide whether we can add a kill flag to the use.
2047  bool CanKill = !isLiveIn;
2048  // Check if any subregister is live-in
2049  if (CanKill) {
2050  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2051  if (MRI.isLiveIn(*AReg)) {
2052  CanKill = false;
2053  break;
2054  }
2055  }
2056  }
2057 
2058  // Do not set a kill flag on values that are also marked as live-in. This
2059  // happens with the @llvm-returnaddress intrinsic and with arguments
2060  // passed in callee saved registers.
2061  // Omitting the kill flags is conservatively correct even if the live-in
2062  // is not used after all.
2063  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2064  .setMIFlag(MachineInstr::FrameSetup);
2065  }
2066 
2067  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2068  // It can be done by spilling XMMs to stack frame.
2069  for (unsigned i = CSI.size(); i != 0; --i) {
2070  unsigned Reg = CSI[i-1].getReg();
2071  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2072  continue;
2073 
2074  // If this is k-register make sure we lookup via the largest legal type.
2075  MVT VT = MVT::Other;
2076  if (X86::VK16RegClass.contains(Reg))
2077  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2078 
2079  // Add the callee-saved register as live-in. It's killed at the spill.
2080  MBB.addLiveIn(Reg);
2081  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2082 
2083  TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2084  TRI);
2085  --MI;
2086  MI->setFlag(MachineInstr::FrameSetup);
2087  ++MI;
2088  }
2089 
2090  return true;
2091 }
2092 
2093 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2095  MachineInstr *CatchRet) const {
2096  // SEH shouldn't use catchret.
2098  MBB.getParent()->getFunction().getPersonalityFn())) &&
2099  "SEH should not use CATCHRET");
2100  DebugLoc DL = CatchRet->getDebugLoc();
2101  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2102 
2103  // Fill EAX/RAX with the address of the target block.
2104  if (STI.is64Bit()) {
2105  // LEA64r CatchRetTarget(%rip), %rax
2106  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2107  .addReg(X86::RIP)
2108  .addImm(0)
2109  .addReg(0)
2110  .addMBB(CatchRetTarget)
2111  .addReg(0);
2112  } else {
2113  // MOV32ri $CatchRetTarget, %eax
2114  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2115  .addMBB(CatchRetTarget);
2116  }
2117 
2118  // Record that we've taken the address of CatchRetTarget and no longer just
2119  // reference it in a terminator.
2120  CatchRetTarget->setHasAddressTaken();
2121 }
2122 
2125  std::vector<CalleeSavedInfo> &CSI,
2126  const TargetRegisterInfo *TRI) const {
2127  if (CSI.empty())
2128  return false;
2129 
2130  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2131  // Don't restore CSRs in 32-bit EH funclets. Matches
2132  // spillCalleeSavedRegisters.
2133  if (STI.is32Bit())
2134  return true;
2135  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2136  // funclets. emitEpilogue transforms these to normal jumps.
2137  if (MI->getOpcode() == X86::CATCHRET) {
2138  const Function &F = MBB.getParent()->getFunction();
2139  bool IsSEH = isAsynchronousEHPersonality(
2141  if (IsSEH)
2142  return true;
2143  }
2144  }
2145 
2146  DebugLoc DL = MBB.findDebugLoc(MI);
2147 
2148  // Reload XMMs from stack frame.
2149  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2150  unsigned Reg = CSI[i].getReg();
2151  if (X86::GR64RegClass.contains(Reg) ||
2152  X86::GR32RegClass.contains(Reg))
2153  continue;
2154 
2155  // If this is k-register make sure we lookup via the largest legal type.
2156  MVT VT = MVT::Other;
2157  if (X86::VK16RegClass.contains(Reg))
2158  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2159 
2160  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2161  TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2162  }
2163 
2164  // POP GPRs.
2165  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2166  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2167  unsigned Reg = CSI[i].getReg();
2168  if (!X86::GR64RegClass.contains(Reg) &&
2169  !X86::GR32RegClass.contains(Reg))
2170  continue;
2171 
2172  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2173  .setMIFlag(MachineInstr::FrameDestroy);
2174  }
2175  return true;
2176 }
2177 
2179  BitVector &SavedRegs,
2180  RegScavenger *RS) const {
2181  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2182 
2183  // Spill the BasePtr if it's used.
2184  if (TRI->hasBasePointer(MF)){
2185  unsigned BasePtr = TRI->getBaseRegister();
2186  if (STI.isTarget64BitILP32())
2187  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2188  SavedRegs.set(BasePtr);
2189  }
2190 }
2191 
2192 static bool
2194  const Function &F = MF->getFunction();
2195  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2196  I != E; I++) {
2197  if (I->hasNestAttr())
2198  return true;
2199  }
2200  return false;
2201 }
2202 
2203 /// GetScratchRegister - Get a temp register for performing work in the
2204 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2205 /// and the properties of the function either one or two registers will be
2206 /// needed. Set primary to true for the first register, false for the second.
2207 static unsigned
2208 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2210 
2211  // Erlang stuff.
2212  if (CallingConvention == CallingConv::HiPE) {
2213  if (Is64Bit)
2214  return Primary ? X86::R14 : X86::R13;
2215  else
2216  return Primary ? X86::EBX : X86::EDI;
2217  }
2218 
2219  if (Is64Bit) {
2220  if (IsLP64)
2221  return Primary ? X86::R11 : X86::R12;
2222  else
2223  return Primary ? X86::R11D : X86::R12D;
2224  }
2225 
2226  bool IsNested = HasNestArgument(&MF);
2227 
2228  if (CallingConvention == CallingConv::X86_FastCall ||
2229  CallingConvention == CallingConv::Fast) {
2230  if (IsNested)
2231  report_fatal_error("Segmented stacks does not support fastcall with "
2232  "nested function.");
2233  return Primary ? X86::EAX : X86::ECX;
2234  }
2235  if (IsNested)
2236  return Primary ? X86::EDX : X86::EAX;
2237  return Primary ? X86::ECX : X86::EAX;
2238 }
2239 
2240 // The stack limit in the TCB is set to this many bytes above the actual stack
2241 // limit.
2242 static const uint64_t kSplitStackAvailable = 256;
2243 
2245  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2246  MachineFrameInfo &MFI = MF.getFrameInfo();
2247  uint64_t StackSize;
2248  unsigned TlsReg, TlsOffset;
2249  DebugLoc DL;
2250 
2251  // To support shrink-wrapping we would need to insert the new blocks
2252  // at the right place and update the branches to PrologueMBB.
2253  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2254 
2255  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2256  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2257  "Scratch register is live-in");
2258 
2259  if (MF.getFunction().isVarArg())
2260  report_fatal_error("Segmented stacks do not support vararg functions.");
2261  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2262  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2264  report_fatal_error("Segmented stacks not supported on this platform.");
2265 
2266  // Eventually StackSize will be calculated by a link-time pass; which will
2267  // also decide whether checking code needs to be injected into this particular
2268  // prologue.
2269  StackSize = MFI.getStackSize();
2270 
2271  // Do not generate a prologue for leaf functions with a stack of size zero.
2272  // For non-leaf functions we have to allow for the possibility that the
2273  // callis to a non-split function, as in PR37807. This function could also
2274  // take the address of a non-split function. When the linker tries to adjust
2275  // its non-existent prologue, it would fail with an error. Mark the object
2276  // file so that such failures are not errors. See this Go language bug-report
2277  // https://go-review.googlesource.com/c/go/+/148819/
2278  if (StackSize == 0 && !MFI.hasTailCall()) {
2279  MF.getMMI().setHasNosplitStack(true);
2280  return;
2281  }
2282 
2283  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2284  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2286  bool IsNested = false;
2287 
2288  // We need to know if the function has a nest argument only in 64 bit mode.
2289  if (Is64Bit)
2290  IsNested = HasNestArgument(&MF);
2291 
2292  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2293  // allocMBB needs to be last (terminating) instruction.
2294 
2295  for (const auto &LI : PrologueMBB.liveins()) {
2296  allocMBB->addLiveIn(LI);
2297  checkMBB->addLiveIn(LI);
2298  }
2299 
2300  if (IsNested)
2301  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2302 
2303  MF.push_front(allocMBB);
2304  MF.push_front(checkMBB);
2305 
2306  // When the frame size is less than 256 we just compare the stack
2307  // boundary directly to the value of the stack pointer, per gcc.
2308  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2309 
2310  // Read the limit off the current stacklet off the stack_guard location.
2311  if (Is64Bit) {
2312  if (STI.isTargetLinux()) {
2313  TlsReg = X86::FS;
2314  TlsOffset = IsLP64 ? 0x70 : 0x40;
2315  } else if (STI.isTargetDarwin()) {
2316  TlsReg = X86::GS;
2317  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2318  } else if (STI.isTargetWin64()) {
2319  TlsReg = X86::GS;
2320  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2321  } else if (STI.isTargetFreeBSD()) {
2322  TlsReg = X86::FS;
2323  TlsOffset = 0x18;
2324  } else if (STI.isTargetDragonFly()) {
2325  TlsReg = X86::FS;
2326  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2327  } else {
2328  report_fatal_error("Segmented stacks not supported on this platform.");
2329  }
2330 
2331  if (CompareStackPointer)
2332  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2333  else
2334  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2335  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2336 
2337  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2338  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2339  } else {
2340  if (STI.isTargetLinux()) {
2341  TlsReg = X86::GS;
2342  TlsOffset = 0x30;
2343  } else if (STI.isTargetDarwin()) {
2344  TlsReg = X86::GS;
2345  TlsOffset = 0x48 + 90*4;
2346  } else if (STI.isTargetWin32()) {
2347  TlsReg = X86::FS;
2348  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2349  } else if (STI.isTargetDragonFly()) {
2350  TlsReg = X86::FS;
2351  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2352  } else if (STI.isTargetFreeBSD()) {
2353  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2354  } else {
2355  report_fatal_error("Segmented stacks not supported on this platform.");
2356  }
2357 
2358  if (CompareStackPointer)
2359  ScratchReg = X86::ESP;
2360  else
2361  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2362  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2363 
2364  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2365  STI.isTargetDragonFly()) {
2366  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2367  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2368  } else if (STI.isTargetDarwin()) {
2369 
2370  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2371  unsigned ScratchReg2;
2372  bool SaveScratch2;
2373  if (CompareStackPointer) {
2374  // The primary scratch register is available for holding the TLS offset.
2375  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2376  SaveScratch2 = false;
2377  } else {
2378  // Need to use a second register to hold the TLS offset
2379  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2380 
2381  // Unfortunately, with fastcc the second scratch register may hold an
2382  // argument.
2383  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2384  }
2385 
2386  // If Scratch2 is live-in then it needs to be saved.
2387  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2388  "Scratch register is live-in and not saved");
2389 
2390  if (SaveScratch2)
2391  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2392  .addReg(ScratchReg2, RegState::Kill);
2393 
2394  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2395  .addImm(TlsOffset);
2396  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2397  .addReg(ScratchReg)
2398  .addReg(ScratchReg2).addImm(1).addReg(0)
2399  .addImm(0)
2400  .addReg(TlsReg);
2401 
2402  if (SaveScratch2)
2403  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2404  }
2405  }
2406 
2407  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2408  // It jumps to normal execution of the function body.
2409  BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
2410 
2411  // On 32 bit we first push the arguments size and then the frame size. On 64
2412  // bit, we pass the stack frame size in r10 and the argument size in r11.
2413  if (Is64Bit) {
2414  // Functions with nested arguments use R10, so it needs to be saved across
2415  // the call to _morestack
2416 
2417  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2418  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2419  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2420  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2421  const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2422 
2423  if (IsNested)
2424  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2425 
2426  BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2427  .addImm(StackSize);
2428  BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2429  .addImm(X86FI->getArgumentStackSize());
2430  } else {
2431  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2432  .addImm(X86FI->getArgumentStackSize());
2433  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2434  .addImm(StackSize);
2435  }
2436 
2437  // __morestack is in libgcc
2438  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2439  // Under the large code model, we cannot assume that __morestack lives
2440  // within 2^31 bytes of the call site, so we cannot use pc-relative
2441  // addressing. We cannot perform the call via a temporary register,
2442  // as the rax register may be used to store the static chain, and all
2443  // other suitable registers may be either callee-save or used for
2444  // parameter passing. We cannot use the stack at this point either
2445  // because __morestack manipulates the stack directly.
2446  //
2447  // To avoid these issues, perform an indirect call via a read-only memory
2448  // location containing the address.
2449  //
2450  // This solution is not perfect, as it assumes that the .rodata section
2451  // is laid out within 2^31 bytes of each function body, but this seems
2452  // to be sufficient for JIT.
2453  // FIXME: Add retpoline support and remove the error here..
2455  report_fatal_error("Emitting morestack calls on 64-bit with the large "
2456  "code model and retpoline not yet implemented.");
2457  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2458  .addReg(X86::RIP)
2459  .addImm(0)
2460  .addReg(0)
2461  .addExternalSymbol("__morestack_addr")
2462  .addReg(0);
2463  MF.getMMI().setUsesMorestackAddr(true);
2464  } else {
2465  if (Is64Bit)
2466  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2467  .addExternalSymbol("__morestack");
2468  else
2469  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2470  .addExternalSymbol("__morestack");
2471  }
2472 
2473  if (IsNested)
2474  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2475  else
2476  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2477 
2478  allocMBB->addSuccessor(&PrologueMBB);
2479 
2480  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2481  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2482 
2483 #ifdef EXPENSIVE_CHECKS
2484  MF.verify();
2485 #endif
2486 }
2487 
2488 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
2489 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
2490 /// to fields it needs, through a named metadata node "hipe.literals" containing
2491 /// name-value pairs.
2492 static unsigned getHiPELiteral(
2493  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
2494  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
2495  MDNode *Node = HiPELiteralsMD->getOperand(i);
2496  if (Node->getNumOperands() != 2) continue;
2497  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
2498  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
2499  if (!NodeName || !NodeVal) continue;
2500  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
2501  if (ValConst && NodeName->getString() == LiteralName) {
2502  return ValConst->getZExtValue();
2503  }
2504  }
2505 
2506  report_fatal_error("HiPE literal " + LiteralName
2507  + " required but not provided");
2508 }
2509 
2510 /// Erlang programs may need a special prologue to handle the stack size they
2511 /// might need at runtime. That is because Erlang/OTP does not implement a C
2512 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2513 /// (for more information see Eric Stenman's Ph.D. thesis:
2514 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2515 ///
2516 /// CheckStack:
2517 /// temp0 = sp - MaxStack
2518 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2519 /// OldStart:
2520 /// ...
2521 /// IncStack:
2522 /// call inc_stack # doubles the stack space
2523 /// temp0 = sp - MaxStack
2524 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2526  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2527  MachineFrameInfo &MFI = MF.getFrameInfo();
2528  DebugLoc DL;
2529 
2530  // To support shrink-wrapping we would need to insert the new blocks
2531  // at the right place and update the branches to PrologueMBB.
2532  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2533 
2534  // HiPE-specific values
2535  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
2536  ->getNamedMetadata("hipe.literals");
2537  if (!HiPELiteralsMD)
2539  "Can't generate HiPE prologue without runtime parameters");
2540  const unsigned HipeLeafWords
2541  = getHiPELiteral(HiPELiteralsMD,
2542  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
2543  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2544  const unsigned Guaranteed = HipeLeafWords * SlotSize;
2545  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
2546  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
2547  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
2548 
2549  assert(STI.isTargetLinux() &&
2550  "HiPE prologue is only supported on Linux operating systems.");
2551 
2552  // Compute the largest caller's frame that is needed to fit the callees'
2553  // frames. This 'MaxStack' is computed from:
2554  //
2555  // a) the fixed frame size, which is the space needed for all spilled temps,
2556  // b) outgoing on-stack parameter areas, and
2557  // c) the minimum stack space this function needs to make available for the
2558  // functions it calls (a tunable ABI property).
2559  if (MFI.hasCalls()) {
2560  unsigned MoreStackForCalls = 0;
2561 
2562  for (auto &MBB : MF) {
2563  for (auto &MI : MBB) {
2564  if (!MI.isCall())
2565  continue;
2566 
2567  // Get callee operand.
2568  const MachineOperand &MO = MI.getOperand(0);
2569 
2570  // Only take account of global function calls (no closures etc.).
2571  if (!MO.isGlobal())
2572  continue;
2573 
2574  const Function *F = dyn_cast<Function>(MO.getGlobal());
2575  if (!F)
2576  continue;
2577 
2578  // Do not update 'MaxStack' for primitive and built-in functions
2579  // (encoded with names either starting with "erlang."/"bif_" or not
2580  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2581  // "_", such as the BIF "suspend_0") as they are executed on another
2582  // stack.
2583  if (F->getName().find("erlang.") != StringRef::npos ||
2584  F->getName().find("bif_") != StringRef::npos ||
2585  F->getName().find_first_of("._") == StringRef::npos)
2586  continue;
2587 
2588  unsigned CalleeStkArity =
2589  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2590  if (HipeLeafWords - 1 > CalleeStkArity)
2591  MoreStackForCalls = std::max(MoreStackForCalls,
2592  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2593  }
2594  }
2595  MaxStack += MoreStackForCalls;
2596  }
2597 
2598  // If the stack frame needed is larger than the guaranteed then runtime checks
2599  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2600  if (MaxStack > Guaranteed) {
2601  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2602  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2603 
2604  for (const auto &LI : PrologueMBB.liveins()) {
2605  stackCheckMBB->addLiveIn(LI);
2606  incStackMBB->addLiveIn(LI);
2607  }
2608 
2609  MF.push_front(incStackMBB);
2610  MF.push_front(stackCheckMBB);
2611 
2612  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2613  unsigned LEAop, CMPop, CALLop;
2614  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
2615  if (Is64Bit) {
2616  SPReg = X86::RSP;
2617  PReg = X86::RBP;
2618  LEAop = X86::LEA64r;
2619  CMPop = X86::CMP64rm;
2620  CALLop = X86::CALL64pcrel32;
2621  } else {
2622  SPReg = X86::ESP;
2623  PReg = X86::EBP;
2624  LEAop = X86::LEA32r;
2625  CMPop = X86::CMP32rm;
2626  CALLop = X86::CALLpcrel32;
2627  }
2628 
2629  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2630  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2631  "HiPE prologue scratch register is live-in");
2632 
2633  // Create new MBB for StackCheck:
2634  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2635  SPReg, false, -MaxStack);
2636  // SPLimitOffset is in a fixed heap location (pointed by BP).
2637  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2638  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2639  BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
2640 
2641  // Create new MBB for IncStack:
2642  BuildMI(incStackMBB, DL, TII.get(CALLop)).
2643  addExternalSymbol("inc_stack_0");
2644  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2645  SPReg, false, -MaxStack);
2646  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2647  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2648  BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
2649 
2650  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
2651  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
2652  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
2653  incStackMBB->addSuccessor(incStackMBB, {1, 100});
2654  }
2655 #ifdef EXPENSIVE_CHECKS
2656  MF.verify();
2657 #endif
2658 }
2659 
2660 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2662  const DebugLoc &DL,
2663  int Offset) const {
2664 
2665  if (Offset <= 0)
2666  return false;
2667 
2668  if (Offset % SlotSize)
2669  return false;
2670 
2671  int NumPops = Offset / SlotSize;
2672  // This is only worth it if we have at most 2 pops.
2673  if (NumPops != 1 && NumPops != 2)
2674  return false;
2675 
2676  // Handle only the trivial case where the adjustment directly follows
2677  // a call. This is the most common one, anyway.
2678  if (MBBI == MBB.begin())
2679  return false;
2680  MachineBasicBlock::iterator Prev = std::prev(MBBI);
2681  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2682  return false;
2683 
2684  unsigned Regs[2];
2685  unsigned FoundRegs = 0;
2686 
2687  auto &MRI = MBB.getParent()->getRegInfo();
2688  auto RegMask = Prev->getOperand(1);
2689 
2690  auto &RegClass =
2691  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2692  // Try to find up to NumPops free registers.
2693  for (auto Candidate : RegClass) {
2694 
2695  // Poor man's liveness:
2696  // Since we're immediately after a call, any register that is clobbered
2697  // by the call and not defined by it can be considered dead.
2698  if (!RegMask.clobbersPhysReg(Candidate))
2699  continue;
2700 
2701  // Don't clobber reserved registers
2702  if (MRI.isReserved(Candidate))
2703  continue;
2704 
2705  bool IsDef = false;
2706  for (const MachineOperand &MO : Prev->implicit_operands()) {
2707  if (MO.isReg() && MO.isDef() &&
2708  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
2709  IsDef = true;
2710  break;
2711  }
2712  }
2713 
2714  if (IsDef)
2715  continue;
2716 
2717  Regs[FoundRegs++] = Candidate;
2718  if (FoundRegs == (unsigned)NumPops)
2719  break;
2720  }
2721 
2722  if (FoundRegs == 0)
2723  return false;
2724 
2725  // If we found only one free register, but need two, reuse the same one twice.
2726  while (FoundRegs < (unsigned)NumPops)
2727  Regs[FoundRegs++] = Regs[0];
2728 
2729  for (int i = 0; i < NumPops; ++i)
2730  BuildMI(MBB, MBBI, DL,
2731  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2732 
2733  return true;
2734 }
2735 
2739  bool reserveCallFrame = hasReservedCallFrame(MF);
2740  unsigned Opcode = I->getOpcode();
2741  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2742  DebugLoc DL = I->getDebugLoc();
2743  uint64_t Amount = !reserveCallFrame ? TII.getFrameSize(*I) : 0;
2744  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2745  I = MBB.erase(I);
2746  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
2747 
2748  if (!reserveCallFrame) {
2749  // If the stack pointer can be changed after prologue, turn the
2750  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2751  // adjcallstackdown instruction into 'add ESP, <amt>'
2752 
2753  // We need to keep the stack aligned properly. To do this, we round the
2754  // amount of space needed for the outgoing arguments up to the next
2755  // alignment boundary.
2756  unsigned StackAlign = getStackAlignment();
2757  Amount = alignTo(Amount, StackAlign);
2758 
2759  MachineModuleInfo &MMI = MF.getMMI();
2760  const Function &F = MF.getFunction();
2761  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2762  bool DwarfCFI = !WindowsCFI &&
2763  (MMI.hasDebugInfo() || F.needsUnwindTableEntry());
2764 
2765  // If we have any exception handlers in this function, and we adjust
2766  // the SP before calls, we may need to indicate this to the unwinder
2767  // using GNU_ARGS_SIZE. Note that this may be necessary even when
2768  // Amount == 0, because the preceding function may have set a non-0
2769  // GNU_ARGS_SIZE.
2770  // TODO: We don't need to reset this between subsequent functions,
2771  // if it didn't change.
2772  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
2773 
2774  if (HasDwarfEHHandlers && !isDestroy &&
2776  BuildCFI(MBB, InsertPos, DL,
2777  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2778 
2779  if (Amount == 0)
2780  return I;
2781 
2782  // Factor out the amount that gets handled inside the sequence
2783  // (Pushes of argument for frame setup, callee pops for frame destroy)
2784  Amount -= InternalAmt;
2785 
2786  // TODO: This is needed only if we require precise CFA.
2787  // If this is a callee-pop calling convention, emit a CFA adjust for
2788  // the amount the callee popped.
2789  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
2790  BuildCFI(MBB, InsertPos, DL,
2791  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2792 
2793  // Add Amount to SP to destroy a frame, or subtract to setup.
2794  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
2795 
2796  if (StackAdjustment) {
2797  // Merge with any previous or following adjustment instruction. Note: the
2798  // instructions merged with here do not have CFI, so their stack
2799  // adjustments do not feed into CfaAdjustment.
2800  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
2801  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
2802 
2803  if (StackAdjustment) {
2804  if (!(F.optForMinSize() &&
2805  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
2806  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
2807  /*InEpilogue=*/false);
2808  }
2809  }
2810 
2811  if (DwarfCFI && !hasFP(MF)) {
2812  // If we don't have FP, but need to generate unwind information,
2813  // we need to set the correct CFA offset after the stack adjustment.
2814  // How much we adjust the CFA offset depends on whether we're emitting
2815  // CFI only for EH purposes or for debugging. EH only requires the CFA
2816  // offset to be correct at each call site, while for debugging we want
2817  // it to be more precise.
2818 
2819  int64_t CfaAdjustment = -StackAdjustment;
2820  // TODO: When not using precise CFA, we also need to adjust for the
2821  // InternalAmt here.
2822  if (CfaAdjustment) {
2823  BuildCFI(MBB, InsertPos, DL,
2825  CfaAdjustment));
2826  }
2827  }
2828 
2829  return I;
2830  }
2831 
2832  if (isDestroy && InternalAmt) {
2833  // If we are performing frame pointer elimination and if the callee pops
2834  // something off the stack pointer, add it back. We do this until we have
2835  // more advanced stack pointer tracking ability.
2836  // We are not tracking the stack pointer adjustment by the callee, so make
2837  // sure we restore the stack pointer immediately after the call, there may
2838  // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2841  while (CI != B && !std::prev(CI)->isCall())
2842  --CI;
2843  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
2844  }
2845 
2846  return I;
2847 }
2848 
2850  assert(MBB.getParent() && "Block is not attached to a function!");
2851  const MachineFunction &MF = *MBB.getParent();
2852  return !TRI->needsStackRealignment(MF) || !MBB.isLiveIn(X86::EFLAGS);
2853 }
2854 
2856  assert(MBB.getParent() && "Block is not attached to a function!");
2857 
2858  // Win64 has strict requirements in terms of epilogue and we are
2859  // not taking a chance at messing with them.
2860  // I.e., unless this block is already an exit block, we can't use
2861  // it as an epilogue.
2862  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
2863  return false;
2864 
2865  if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2866  return true;
2867 
2868  // If we cannot use LEA to adjust SP, we may need to use ADD, which
2869  // clobbers the EFLAGS. Check that we do not need to preserve it,
2870  // otherwise, conservatively assume this is not
2871  // safe to insert the epilogue here.
2873 }
2874 
2876  // If we may need to emit frameless compact unwind information, give
2877  // up as this is currently broken: PR25614.
2878  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF)) &&
2879  // The lowering of segmented stack and HiPE only support entry blocks
2880  // as prologue blocks: PR26107.
2881  // This limitation may be lifted if we fix:
2882  // - adjustForSegmentedStacks
2883  // - adjustForHiPEPrologue
2885  !MF.shouldSplitStack();
2886 }
2887 
2890  const DebugLoc &DL, bool RestoreSP) const {
2891  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2892  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2894  "restoring EBP/ESI on non-32-bit target");
2895 
2896  MachineFunction &MF = *MBB.getParent();
2897  unsigned FramePtr = TRI->getFrameRegister(MF);
2898  unsigned BasePtr = TRI->getBaseRegister();
2899  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
2900  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2901  MachineFrameInfo &MFI = MF.getFrameInfo();
2902 
2903  // FIXME: Don't set FrameSetup flag in catchret case.
2904 
2905  int FI = FuncInfo.EHRegNodeFrameIndex;
2906  int EHRegSize = MFI.getObjectSize(FI);
2907 
2908  if (RestoreSP) {
2909  // MOV32rm -EHRegSize(%ebp), %esp
2910  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2911  X86::EBP, true, -EHRegSize)
2913  }
2914 
2915  unsigned UsedReg;
2916  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2917  int EndOffset = -EHRegOffset - EHRegSize;
2918  FuncInfo.EHRegNodeEndOffset = EndOffset;
2919 
2920  if (UsedReg == FramePtr) {
2921  // ADD $offset, %ebp
2922  unsigned ADDri = getADDriOpcode(false, EndOffset);
2923  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2924  .addReg(FramePtr)
2925  .addImm(EndOffset)
2927  ->getOperand(3)
2928  .setIsDead();
2929  assert(EndOffset >= 0 &&
2930  "end of registration object above normal EBP position!");
2931  } else if (UsedReg == BasePtr) {
2932  // LEA offset(%ebp), %esi
2933  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2934  FramePtr, false, EndOffset)
2936  // MOV32rm SavedEBPOffset(%esi), %ebp
2937  assert(X86FI->getHasSEHFramePtrSave());
2938  int Offset =
2939  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2940  assert(UsedReg == BasePtr);
2941  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2942  UsedReg, true, Offset)
2944  } else {
2945  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2946  }
2947  return MBBI;
2948 }
2949 
2951  return TRI->getSlotSize();
2952 }
2953 
2955  const {
2956  return TRI->getDwarfRegNum(StackPtr, true);
2957 }
2958 
2959 namespace {
2960 // Struct used by orderFrameObjects to help sort the stack objects.
2961 struct X86FrameSortingObject {
2962  bool IsValid = false; // true if we care about this Object.
2963  unsigned ObjectIndex = 0; // Index of Object into MFI list.
2964  unsigned ObjectSize = 0; // Size of Object in bytes.
2965  unsigned ObjectAlignment = 1; // Alignment of Object in bytes.
2966  unsigned ObjectNumUses = 0; // Object static number of uses.
2967 };
2968 
2969 // The comparison function we use for std::sort to order our local
2970 // stack symbols. The current algorithm is to use an estimated
2971 // "density". This takes into consideration the size and number of
2972 // uses each object has in order to roughly minimize code size.
2973 // So, for example, an object of size 16B that is referenced 5 times
2974 // will get higher priority than 4 4B objects referenced 1 time each.
2975 // It's not perfect and we may be able to squeeze a few more bytes out of
2976 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
2977 // fringe end can have special consideration, given their size is less
2978 // important, etc.), but the algorithmic complexity grows too much to be
2979 // worth the extra gains we get. This gets us pretty close.
2980 // The final order leaves us with objects with highest priority going
2981 // at the end of our list.
2982 struct X86FrameSortingComparator {
2983  inline bool operator()(const X86FrameSortingObject &A,
2984  const X86FrameSortingObject &B) {
2985  uint64_t DensityAScaled, DensityBScaled;
2986 
2987  // For consistency in our comparison, all invalid objects are placed
2988  // at the end. This also allows us to stop walking when we hit the
2989  // first invalid item after it's all sorted.
2990  if (!A.IsValid)
2991  return false;
2992  if (!B.IsValid)
2993  return true;
2994 
2995  // The density is calculated by doing :
2996  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
2997  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
2998  // Since this approach may cause inconsistencies in
2999  // the floating point <, >, == comparisons, depending on the floating
3000  // point model with which the compiler was built, we're going
3001  // to scale both sides by multiplying with
3002  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3003  // the division and, with it, the need for any floating point
3004  // arithmetic.
3005  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3006  static_cast<uint64_t>(B.ObjectSize);
3007  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3008  static_cast<uint64_t>(A.ObjectSize);
3009 
3010  // If the two densities are equal, prioritize highest alignment
3011  // objects. This allows for similar alignment objects
3012  // to be packed together (given the same density).
3013  // There's room for improvement here, also, since we can pack
3014  // similar alignment (different density) objects next to each
3015  // other to save padding. This will also require further
3016  // complexity/iterations, and the overall gain isn't worth it,
3017  // in general. Something to keep in mind, though.
3018  if (DensityAScaled == DensityBScaled)
3019  return A.ObjectAlignment < B.ObjectAlignment;
3020 
3021  return DensityAScaled < DensityBScaled;
3022  }
3023 };
3024 } // namespace
3025 
3026 // Order the symbols in the local stack.
3027 // We want to place the local stack objects in some sort of sensible order.
3028 // The heuristic we use is to try and pack them according to static number
3029 // of uses and size of object in order to minimize code size.
3031  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3032  const MachineFrameInfo &MFI = MF.getFrameInfo();
3033 
3034  // Don't waste time if there's nothing to do.
3035  if (ObjectsToAllocate.empty())
3036  return;
3037 
3038  // Create an array of all MFI objects. We won't need all of these
3039  // objects, but we're going to create a full array of them to make
3040  // it easier to index into when we're counting "uses" down below.
3041  // We want to be able to easily/cheaply access an object by simply
3042  // indexing into it, instead of having to search for it every time.
3043  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3044 
3045  // Walk the objects we care about and mark them as such in our working
3046  // struct.
3047  for (auto &Obj : ObjectsToAllocate) {
3048  SortingObjects[Obj].IsValid = true;
3049  SortingObjects[Obj].ObjectIndex = Obj;
3050  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlignment(Obj);
3051  // Set the size.
3052  int ObjectSize = MFI.getObjectSize(Obj);
3053  if (ObjectSize == 0)
3054  // Variable size. Just use 4.
3055  SortingObjects[Obj].ObjectSize = 4;
3056  else
3057  SortingObjects[Obj].ObjectSize = ObjectSize;
3058  }
3059 
3060  // Count the number of uses for each object.
3061  for (auto &MBB : MF) {
3062  for (auto &MI : MBB) {
3063  if (MI.isDebugInstr())
3064  continue;
3065  for (const MachineOperand &MO : MI.operands()) {
3066  // Check to see if it's a local stack symbol.
3067  if (!MO.isFI())
3068  continue;
3069  int Index = MO.getIndex();
3070  // Check to see if it falls within our range, and is tagged
3071  // to require ordering.
3072  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3073  SortingObjects[Index].IsValid)
3074  SortingObjects[Index].ObjectNumUses++;
3075  }
3076  }
3077  }
3078 
3079  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3080  // info).
3081  std::stable_sort(SortingObjects.begin(), SortingObjects.end(),
3082  X86FrameSortingComparator());
3083 
3084  // Now modify the original list to represent the final order that
3085  // we want. The order will depend on whether we're going to access them
3086  // from the stack pointer or the frame pointer. For SP, the list should
3087  // end up with the END containing objects that we want with smaller offsets.
3088  // For FP, it should be flipped.
3089  int i = 0;
3090  for (auto &Obj : SortingObjects) {
3091  // All invalid items are sorted at the end, so it's safe to stop.
3092  if (!Obj.IsValid)
3093  break;
3094  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3095  }
3096 
3097  // Flip it if we're accessing off of the FP.
3098  if (!TRI->needsStackRealignment(MF) && hasFP(MF))
3099  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3100 }
3101 
3102 
3104  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3105  unsigned Offset = 16;
3106  // RBP is immediately pushed.
3107  Offset += SlotSize;
3108  // All callee-saved registers are then pushed.
3109  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3110  // Every funclet allocates enough stack space for the largest outgoing call.
3111  Offset += getWinEHFuncletFrameSize(MF);
3112  return Offset;
3113 }
3114 
3116  MachineFunction &MF, RegScavenger *RS) const {
3117  // Mark the function as not having WinCFI. We will set it back to true in
3118  // emitPrologue if it gets called and emits CFI.
3119  MF.setHasWinCFI(false);
3120 
3121  // If this function isn't doing Win64-style C++ EH, we don't need to do
3122  // anything.
3123  const Function &F = MF.getFunction();
3124  if (!STI.is64Bit() || !MF.hasEHFunclets() ||
3126  return;
3127 
3128  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3129  // relative to RSP after the prologue. Find the offset of the last fixed
3130  // object, so that we can allocate a slot immediately following it. If there
3131  // were no fixed objects, use offset -SlotSize, which is immediately after the
3132  // return address. Fixed objects have negative frame indices.
3133  MachineFrameInfo &MFI = MF.getFrameInfo();
3134  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3135  int64_t MinFixedObjOffset = -SlotSize;
3136  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3137  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3138 
3139  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3140  for (WinEHHandlerType &H : TBME.HandlerArray) {
3141  int FrameIndex = H.CatchObj.FrameIndex;
3142  if (FrameIndex != INT_MAX) {
3143  // Ensure alignment.
3144  unsigned Align = MFI.getObjectAlignment(FrameIndex);
3145  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3146  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3147  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3148  }
3149  }
3150  }
3151 
3152  // Ensure alignment.
3153  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3154  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3155  int UnwindHelpFI =
3156  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*Immutable=*/false);
3157  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3158 
3159  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3160  // other frame setup instructions.
3161  MachineBasicBlock &MBB = MF.front();
3162  auto MBBI = MBB.begin();
3163  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3164  ++MBBI;
3165 
3166  DebugLoc DL = MBB.findDebugLoc(MBBI);
3167  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3168  UnwindHelpFI)
3169  .addImm(-2);
3170 }
void push_front(MachineBasicBlock *MBB)
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:521
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:583
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:397
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
MachineBasicBlock * getMBB() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1080
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSWindows() const
Definition: X86Subtarget.h:768
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:480
bool hasStackObjects() const
Return true if there are any stack objects in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
static unsigned getLEArOpcode(unsigned IsLP64)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:487
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned Reg
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
void setCalleeSavedFrameSize(unsigned bytes)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
arg_iterator arg_end()
Definition: Function.h:679
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1068
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static BranchProbability getOne()
bool isTargetNaCl64() const
Definition: X86Subtarget.h:738
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:474
unsigned getSlotSize() const
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:481
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:742
X86FrameLowering(const X86Subtarget &STI, unsigned StackAlignOverride)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
union llvm::WinEHHandlerType::@189 CatchObj
The CatchObj starts out life as an LLVM alloca and is eventually turned frame index.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:694
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A tuple of MDNodes.
Definition: Metadata.h:1325
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:540
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool is32Bit() const
Definition: X86Subtarget.h:525
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
iterator_range< iterator > terminators()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime...
unsigned getNumOperands() const
Definition: Metadata.cpp:1076
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
static const uint64_t kSplitStackAvailable
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getBaseRegister() const
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:266
unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const override
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
Definition: ARMWinEH.h:196
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool needsFrameIndexResolution(const MachineFunction &MF) const override
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
const MCContext & getContext() const
int getObjectIndexBegin() const
Return the minimum frame object index.
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:250
static unsigned getHiPELiteral(NamedMDNode *HiPELiteralsMD, const StringRef LiteralName)
Lookup an ERTS parameter in the !hipe.literals named metadata node.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:701
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
Value wrapper in the Metadata hierarchy.
Definition: Metadata.h:338
static unsigned calculateSetFPREG(uint64_t SPAdjust)
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getKillRegState(bool B)
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:468
unsigned getStackRegister() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getInitialCFARegister(const MachineFunction &MF) const override
Return initial CFA register value i.e.
StringRef getString() const
Definition: Metadata.cpp:463
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:527
unsigned getDefRegState(bool B)
The memory access is volatile.
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:476
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:467
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:355
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasEHFunclets() const
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const GlobalValue * getGlobal() const
const X86InstrInfo & TII
#define H(x, y, z)
Definition: MD5.cpp:57
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:553
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:299
MCRegAliasIterator enumerates all registers aliasing Reg.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
bool useLeaForSP() const
Definition: X86Subtarget.h:624
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
unsigned getFramePtr() const
Returns physical register used as frame pointer.
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:723
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const Triple & getTargetTriple() const
size_t arg_size() const
Definition: Function.h:697
arg_iterator arg_begin()
Definition: Function.h:670
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isTargetDarwin() const
Definition: X86Subtarget.h:722
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:671
bool isTargetWin64() const
Definition: X86Subtarget.h:770
This class contains a discriminated union of information about pointers in memory operands...
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm)
static bool isFuncletReturnInstr(MachineInstr &MI)
static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const
Emit target stack probe code.
The memory access writes data.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
const X86Subtarget & STI
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value...
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool isTargetWin32() const
Definition: X86Subtarget.h:772
int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling...
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:190
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
bool callsUnwindInit() const
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
IterT skipDebugInstructionsBackward(IterT It, IterT Begin)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:534
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:572
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isTailCallOpcode(unsigned Opc)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
CodeModel::Model getCodeModel() const
Returns the code model.
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:690
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
static const size_t npos
Definition: StringRef.h:50
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTargetDragonFly() const
Definition: X86Subtarget.h:724
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
Definition: TargetMachine.h:96
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
LLVM_NODISCARD size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
Definition: StringRef.h:380
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:594
Pair of physical register and lane mask.
virtual const TargetFrameLowering * getFrameLowering() const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
void setCVBytesOfCalleeSavedRegisters(unsigned S)
uint32_t Size
Definition: Profile.cpp:46
static unsigned getSUBrrOpcode(unsigned isLP64)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:173
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const X86RegisterInfo * TRI
const Module * getModule() const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
CallingConvention
Definition: Dwarf.h:201
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isEAXLiveIn(MachineBasicBlock &MBB)
static unsigned getADDrrOpcode(unsigned isLP64)
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1302
bool isTargetLinux() const
Definition: X86Subtarget.h:732
static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const X86RegisterInfo *TRI, bool Is64Bit)
findDeadCallerSavedReg - Return a caller-saved register that isn&#39;t live when it reaches the "return" ...
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:783
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
int getInitialCFAOffset(const MachineFunction &MF) const override
Return initial CFA offset value i.e.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasBWI() const
Definition: X86Subtarget.h:655
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
A single uniqued string.
Definition: Metadata.h:603
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL) const
unsigned getFrameRegister(const MachineFunction &MF) const override
static BranchProbability getZero()
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
No exception support.
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1074
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static bool HasNestArgument(const MachineFunction *MF)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
Function Alias Analysis false
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
This class contains meta information specific to a module.
bool hasCalls() const
Return true if the current function has any function calls.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:750