LLVM  10.0.0svn
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Support/Debug.h"
33 #include <cstdlib>
34 
35 using namespace llvm;
36 
38  unsigned StackAlignOverride)
39  : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40  STI.is64Bit() ? -8 : -4),
41  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42  // Cache a bunch of frame-related predicates for this subtarget.
44  Is64Bit = STI.is64Bit();
45  IsLP64 = STI.isTarget64BitLP64();
46  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
49 }
50 
52  return !MF.getFrameInfo().hasVarSizedObjects() &&
53  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
54 }
55 
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
60 bool
62  return hasReservedCallFrame(MF) ||
63  (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64  TRI->hasBasePointer(MF);
65 }
66 
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
74 bool
76  return MF.getFrameInfo().hasStackObjects() ||
77  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
78 }
79 
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
84  const MachineFrameInfo &MFI = MF.getFrameInfo();
85  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
86  TRI->needsStackRealignment(MF) ||
87  MFI.hasVarSizedObjects() ||
89  MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
90  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
91  MFI.hasStackMap() || MFI.hasPatchPoint() ||
93 }
94 
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
96  if (IsLP64) {
97  if (isInt<8>(Imm))
98  return X86::SUB64ri8;
99  return X86::SUB64ri32;
100  } else {
101  if (isInt<8>(Imm))
102  return X86::SUB32ri8;
103  return X86::SUB32ri;
104  }
105 }
106 
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
108  if (IsLP64) {
109  if (isInt<8>(Imm))
110  return X86::ADD64ri8;
111  return X86::ADD64ri32;
112  } else {
113  if (isInt<8>(Imm))
114  return X86::ADD32ri8;
115  return X86::ADD32ri;
116  }
117 }
118 
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120  return isLP64 ? X86::SUB64rr : X86::SUB32rr;
121 }
122 
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124  return isLP64 ? X86::ADD64rr : X86::ADD32rr;
125 }
126 
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
128  if (IsLP64) {
129  if (isInt<8>(Imm))
130  return X86::AND64ri8;
131  return X86::AND64ri32;
132  }
133  if (isInt<8>(Imm))
134  return X86::AND32ri8;
135  return X86::AND32ri;
136 }
137 
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139  return IsLP64 ? X86::LEA64r : X86::LEA32r;
140 }
141 
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
147  const X86RegisterInfo *TRI,
148  bool Is64Bit) {
149  const MachineFunction *MF = MBB.getParent();
150  if (MF->callsEHReturn())
151  return 0;
152 
153  const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
154 
155  if (MBBI == MBB.end())
156  return 0;
157 
158  switch (MBBI->getOpcode()) {
159  default: return 0;
160  case TargetOpcode::PATCHABLE_RET:
161  case X86::RET:
162  case X86::RETL:
163  case X86::RETQ:
164  case X86::RETIL:
165  case X86::RETIQ:
166  case X86::TCRETURNdi:
167  case X86::TCRETURNri:
168  case X86::TCRETURNmi:
169  case X86::TCRETURNdi64:
170  case X86::TCRETURNri64:
171  case X86::TCRETURNmi64:
172  case X86::EH_RETURN:
173  case X86::EH_RETURN64: {
175  for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
176  MachineOperand &MO = MBBI->getOperand(i);
177  if (!MO.isReg() || MO.isDef())
178  continue;
179  Register Reg = MO.getReg();
180  if (!Reg)
181  continue;
182  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
183  Uses.insert(*AI);
184  }
185 
186  for (auto CS : AvailableRegs)
187  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
188  CS != X86::ESP)
189  return CS;
190  }
191  }
192 
193  return 0;
194 }
195 
196 static bool isEAXLiveIn(MachineBasicBlock &MBB) {
197  for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
198  unsigned Reg = RegMask.PhysReg;
199 
200  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
201  Reg == X86::AH || Reg == X86::AL)
202  return true;
203  }
204 
205  return false;
206 }
207 
208 /// Check if the flags need to be preserved before the terminators.
209 /// This would be the case, if the eflags is live-in of the region
210 /// composed by the terminators or live-out of that region, without
211 /// being defined by a terminator.
212 static bool
214  for (const MachineInstr &MI : MBB.terminators()) {
215  bool BreakNext = false;
216  for (const MachineOperand &MO : MI.operands()) {
217  if (!MO.isReg())
218  continue;
219  Register Reg = MO.getReg();
220  if (Reg != X86::EFLAGS)
221  continue;
222 
223  // This terminator needs an eflags that is not defined
224  // by a previous another terminator:
225  // EFLAGS is live-in of the region composed by the terminators.
226  if (!MO.isDef())
227  return true;
228  // This terminator defines the eflags, i.e., we don't need to preserve it.
229  // However, we still need to check this specific terminator does not
230  // read a live-in value.
231  BreakNext = true;
232  }
233  // We found a definition of the eflags, no need to preserve them.
234  if (BreakNext)
235  return false;
236  }
237 
238  // None of the terminators use or define the eflags.
239  // Check if they are live-out, that would imply we need to preserve them.
240  for (const MachineBasicBlock *Succ : MBB.successors())
241  if (Succ->isLiveIn(X86::EFLAGS))
242  return true;
243 
244  return false;
245 }
246 
247 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
248 /// stack pointer by a constant value.
251  const DebugLoc &DL,
252  int64_t NumBytes, bool InEpilogue) const {
253  bool isSub = NumBytes < 0;
254  uint64_t Offset = isSub ? -NumBytes : NumBytes;
257 
258  uint64_t Chunk = (1LL << 31) - 1;
259 
260  if (Offset > Chunk) {
261  // Rather than emit a long series of instructions for large offsets,
262  // load the offset into a register and do one sub/add
263  unsigned Reg = 0;
264  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
265 
266  if (isSub && !isEAXLiveIn(MBB))
267  Reg = Rax;
268  else
269  Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
270 
271  unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
272  unsigned AddSubRROpc =
274  if (Reg) {
275  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
276  .addImm(Offset)
277  .setMIFlag(Flag);
278  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
279  .addReg(StackPtr)
280  .addReg(Reg);
281  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
282  return;
283  } else if (Offset > 8 * Chunk) {
284  // If we would need more than 8 add or sub instructions (a >16GB stack
285  // frame), it's worth spilling RAX to materialize this immediate.
286  // pushq %rax
287  // movabsq +-$Offset+-SlotSize, %rax
288  // addq %rsp, %rax
289  // xchg %rax, (%rsp)
290  // movq (%rsp), %rsp
291  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
292  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
293  .addReg(Rax, RegState::Kill)
294  .setMIFlag(Flag);
295  // Subtract is not commutative, so negate the offset and always use add.
296  // Subtract 8 less and add 8 more to account for the PUSH we just did.
297  if (isSub)
298  Offset = -(Offset - SlotSize);
299  else
300  Offset = Offset + SlotSize;
301  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
302  .addImm(Offset)
303  .setMIFlag(Flag);
304  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
305  .addReg(Rax)
306  .addReg(StackPtr);
307  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
308  // Exchange the new SP in RAX with the top of the stack.
309  addRegOffset(
310  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
311  StackPtr, false, 0);
312  // Load new SP from the top of the stack into RSP.
313  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
314  StackPtr, false, 0);
315  return;
316  }
317  }
318 
319  while (Offset) {
320  uint64_t ThisVal = std::min(Offset, Chunk);
321  if (ThisVal == SlotSize) {
322  // Use push / pop for slot sized adjustments as a size optimization. We
323  // need to find a dead register when using pop.
324  unsigned Reg = isSub
325  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
326  : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
327  if (Reg) {
328  unsigned Opc = isSub
329  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
330  : (Is64Bit ? X86::POP64r : X86::POP32r);
331  BuildMI(MBB, MBBI, DL, TII.get(Opc))
332  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
333  .setMIFlag(Flag);
334  Offset -= ThisVal;
335  continue;
336  }
337  }
338 
339  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
340  .setMIFlag(Flag);
341 
342  Offset -= ThisVal;
343  }
344 }
345 
346 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
348  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
349  assert(Offset != 0 && "zero offset stack adjustment requested");
350 
351  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
352  // is tricky.
353  bool UseLEA;
354  if (!InEpilogue) {
355  // Check if inserting the prologue at the beginning
356  // of MBB would require to use LEA operations.
357  // We need to use LEA operations if EFLAGS is live in, because
358  // it means an instruction will read it before it gets defined.
359  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
360  } else {
361  // If we can use LEA for SP but we shouldn't, check that none
362  // of the terminators uses the eflags. Otherwise we will insert
363  // a ADD that will redefine the eflags and break the condition.
364  // Alternatively, we could move the ADD, but this may not be possible
365  // and is an optimization anyway.
366  UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
367  if (UseLEA && !STI.useLeaForSP())
369  // If that assert breaks, that means we do not do the right thing
370  // in canUseAsEpilogue.
372  "We shouldn't have allowed this insertion point");
373  }
374 
376  if (UseLEA) {
377  MI = addRegOffset(BuildMI(MBB, MBBI, DL,
379  StackPtr),
380  StackPtr, false, Offset);
381  } else {
382  bool IsSub = Offset < 0;
383  uint64_t AbsOffset = IsSub ? -Offset : Offset;
384  unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
385  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
386  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
387  .addReg(StackPtr)
388  .addImm(AbsOffset);
389  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
390  }
391  return MI;
392 }
393 
396  bool doMergeWithPrevious) const {
397  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
398  (!doMergeWithPrevious && MBBI == MBB.end()))
399  return 0;
400 
401  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
402 
403  PI = skipDebugInstructionsBackward(PI, MBB.begin());
404  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
405  // instruction, and that there are no DBG_VALUE or other instructions between
406  // ADD/SUB/LEA and its corresponding CFI instruction.
407  /* TODO: Add support for the case where there are multiple CFI instructions
408  below the ADD/SUB/LEA, e.g.:
409  ...
410  add
411  cfi_def_cfa_offset
412  cfi_offset
413  ...
414  */
415  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
416  PI = std::prev(PI);
417 
418  unsigned Opc = PI->getOpcode();
419  int Offset = 0;
420 
421  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
422  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
423  PI->getOperand(0).getReg() == StackPtr){
424  assert(PI->getOperand(1).getReg() == StackPtr);
425  Offset = PI->getOperand(2).getImm();
426  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
427  PI->getOperand(0).getReg() == StackPtr &&
428  PI->getOperand(1).getReg() == StackPtr &&
429  PI->getOperand(2).getImm() == 1 &&
430  PI->getOperand(3).getReg() == X86::NoRegister &&
431  PI->getOperand(5).getReg() == X86::NoRegister) {
432  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
433  Offset = PI->getOperand(4).getImm();
434  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
435  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
436  PI->getOperand(0).getReg() == StackPtr) {
437  assert(PI->getOperand(1).getReg() == StackPtr);
438  Offset = -PI->getOperand(2).getImm();
439  } else
440  return 0;
441 
442  PI = MBB.erase(PI);
443  if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
444  if (!doMergeWithPrevious)
445  MBBI = skipDebugInstructionsForward(PI, MBB.end());
446 
447  return Offset;
448 }
449 
452  const DebugLoc &DL,
453  const MCCFIInstruction &CFIInst) const {
454  MachineFunction &MF = *MBB.getParent();
455  unsigned CFIIndex = MF.addFrameInst(CFIInst);
456  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
457  .addCFIIndex(CFIIndex);
458 }
459 
462  const DebugLoc &DL) const {
463  MachineFunction &MF = *MBB.getParent();
464  MachineFrameInfo &MFI = MF.getFrameInfo();
465  MachineModuleInfo &MMI = MF.getMMI();
466  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
467 
468  // Add callee saved registers to move list.
469  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
470  if (CSI.empty()) return;
471 
472  // Calculate offsets.
473  for (std::vector<CalleeSavedInfo>::const_iterator
474  I = CSI.begin(), E = CSI.end(); I != E; ++I) {
475  int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
476  unsigned Reg = I->getReg();
477 
478  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
479  BuildCFI(MBB, MBBI, DL,
480  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
481  }
482 }
483 
485  MachineBasicBlock &MBB,
487  const DebugLoc &DL, bool InProlog) const {
488  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
489  if (STI.isTargetWindowsCoreCLR()) {
490  if (InProlog) {
491  emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
492  } else {
493  emitStackProbeInline(MF, MBB, MBBI, DL, false);
494  }
495  } else {
496  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
497  }
498 }
499 
501  MachineBasicBlock &PrologMBB) const {
502  const StringRef ChkStkStubSymbol = "__chkstk_stub";
503  MachineInstr *ChkStkStub = nullptr;
504 
505  for (MachineInstr &MI : PrologMBB) {
506  if (MI.isCall() && MI.getOperand(0).isSymbol() &&
507  ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
508  ChkStkStub = &MI;
509  break;
510  }
511  }
512 
513  if (ChkStkStub != nullptr) {
514  assert(!ChkStkStub->isBundled() &&
515  "Not expecting bundled instructions here");
516  MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
517  assert(std::prev(MBBI) == ChkStkStub &&
518  "MBBI expected after __chkstk_stub.");
519  DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
520  emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
521  ChkStkStub->eraseFromParent();
522  }
523 }
524 
525 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
526  MachineBasicBlock &MBB,
528  const DebugLoc &DL,
529  bool InProlog) const {
530  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
531  assert(STI.is64Bit() && "different expansion needed for 32 bit");
532  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
533  const TargetInstrInfo &TII = *STI.getInstrInfo();
534  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
535 
536  // RAX contains the number of bytes of desired stack adjustment.
537  // The handling here assumes this value has already been updated so as to
538  // maintain stack alignment.
539  //
540  // We need to exit with RSP modified by this amount and execute suitable
541  // page touches to notify the OS that we're growing the stack responsibly.
542  // All stack probing must be done without modifying RSP.
543  //
544  // MBB:
545  // SizeReg = RAX;
546  // ZeroReg = 0
547  // CopyReg = RSP
548  // Flags, TestReg = CopyReg - SizeReg
549  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
550  // LimitReg = gs magic thread env access
551  // if FinalReg >= LimitReg goto ContinueMBB
552  // RoundBB:
553  // RoundReg = page address of FinalReg
554  // LoopMBB:
555  // LoopReg = PHI(LimitReg,ProbeReg)
556  // ProbeReg = LoopReg - PageSize
557  // [ProbeReg] = 0
558  // if (ProbeReg > RoundReg) goto LoopMBB
559  // ContinueMBB:
560  // RSP = RSP - RAX
561  // [rest of original MBB]
562 
563  // Set up the new basic blocks
564  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
565  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
566  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
567 
568  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
569  MF.insert(MBBIter, RoundMBB);
570  MF.insert(MBBIter, LoopMBB);
571  MF.insert(MBBIter, ContinueMBB);
572 
573  // Split MBB and move the tail portion down to ContinueMBB.
574  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
575  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
576  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
577 
578  // Some useful constants
579  const int64_t ThreadEnvironmentStackLimit = 0x10;
580  const int64_t PageSize = 0x1000;
581  const int64_t PageMask = ~(PageSize - 1);
582 
583  // Registers we need. For the normal case we use virtual
584  // registers. For the prolog expansion we use RAX, RCX and RDX.
586  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
587  const Register SizeReg = InProlog ? X86::RAX
588  : MRI.createVirtualRegister(RegClass),
589  ZeroReg = InProlog ? X86::RCX
590  : MRI.createVirtualRegister(RegClass),
591  CopyReg = InProlog ? X86::RDX
592  : MRI.createVirtualRegister(RegClass),
593  TestReg = InProlog ? X86::RDX
594  : MRI.createVirtualRegister(RegClass),
595  FinalReg = InProlog ? X86::RDX
596  : MRI.createVirtualRegister(RegClass),
597  RoundedReg = InProlog ? X86::RDX
598  : MRI.createVirtualRegister(RegClass),
599  LimitReg = InProlog ? X86::RCX
600  : MRI.createVirtualRegister(RegClass),
601  JoinReg = InProlog ? X86::RCX
602  : MRI.createVirtualRegister(RegClass),
603  ProbeReg = InProlog ? X86::RCX
604  : MRI.createVirtualRegister(RegClass);
605 
606  // SP-relative offsets where we can save RCX and RDX.
607  int64_t RCXShadowSlot = 0;
608  int64_t RDXShadowSlot = 0;
609 
610  // If inlining in the prolog, save RCX and RDX.
611  if (InProlog) {
612  // Compute the offsets. We need to account for things already
613  // pushed onto the stack at this point: return address, frame
614  // pointer (if used), and callee saves.
616  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
617  const bool HasFP = hasFP(MF);
618 
619  // Check if we need to spill RCX and/or RDX.
620  // Here we assume that no earlier prologue instruction changes RCX and/or
621  // RDX, so checking the block live-ins is enough.
622  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
623  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
624  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
625  // Assign the initial slot to both registers, then change RDX's slot if both
626  // need to be spilled.
627  if (IsRCXLiveIn)
628  RCXShadowSlot = InitSlot;
629  if (IsRDXLiveIn)
630  RDXShadowSlot = InitSlot;
631  if (IsRDXLiveIn && IsRCXLiveIn)
632  RDXShadowSlot += 8;
633  // Emit the saves if needed.
634  if (IsRCXLiveIn)
635  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
636  RCXShadowSlot)
637  .addReg(X86::RCX);
638  if (IsRDXLiveIn)
639  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
640  RDXShadowSlot)
641  .addReg(X86::RDX);
642  } else {
643  // Not in the prolog. Copy RAX to a virtual reg.
644  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
645  }
646 
647  // Add code to MBB to check for overflow and set the new target stack pointer
648  // to zero if so.
649  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
650  .addReg(ZeroReg, RegState::Undef)
651  .addReg(ZeroReg, RegState::Undef);
652  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
653  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
654  .addReg(CopyReg)
655  .addReg(SizeReg);
656  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
657  .addReg(TestReg)
658  .addReg(ZeroReg)
660 
661  // FinalReg now holds final stack pointer value, or zero if
662  // allocation would overflow. Compare against the current stack
663  // limit from the thread environment block. Note this limit is the
664  // lowest touched page on the stack, not the point at which the OS
665  // will cause an overflow exception, so this is just an optimization
666  // to avoid unnecessarily touching pages that are below the current
667  // SP but already committed to the stack by the OS.
668  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
669  .addReg(0)
670  .addImm(1)
671  .addReg(0)
672  .addImm(ThreadEnvironmentStackLimit)
673  .addReg(X86::GS);
674  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
675  // Jump if the desired stack pointer is at or above the stack limit.
676  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
677 
678  // Add code to roundMBB to round the final stack pointer to a page boundary.
679  RoundMBB->addLiveIn(FinalReg);
680  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
681  .addReg(FinalReg)
682  .addImm(PageMask);
683  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
684 
685  // LimitReg now holds the current stack limit, RoundedReg page-rounded
686  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
687  // and probe until we reach RoundedReg.
688  if (!InProlog) {
689  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
690  .addReg(LimitReg)
691  .addMBB(RoundMBB)
692  .addReg(ProbeReg)
693  .addMBB(LoopMBB);
694  }
695 
696  LoopMBB->addLiveIn(JoinReg);
697  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
698  false, -PageSize);
699 
700  // Probe by storing a byte onto the stack.
701  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
702  .addReg(ProbeReg)
703  .addImm(1)
704  .addReg(0)
705  .addImm(0)
706  .addReg(0)
707  .addImm(0);
708 
709  LoopMBB->addLiveIn(RoundedReg);
710  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
711  .addReg(RoundedReg)
712  .addReg(ProbeReg);
713  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
714 
715  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
716 
717  // If in prolog, restore RDX and RCX.
718  if (InProlog) {
719  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
720  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
721  TII.get(X86::MOV64rm), X86::RCX),
722  X86::RSP, false, RCXShadowSlot);
723  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
724  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
725  TII.get(X86::MOV64rm), X86::RDX),
726  X86::RSP, false, RDXShadowSlot);
727  }
728 
729  // Now that the probing is done, add code to continueMBB to update
730  // the stack pointer for real.
731  ContinueMBB->addLiveIn(SizeReg);
732  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
733  .addReg(X86::RSP)
734  .addReg(SizeReg);
735 
736  // Add the control flow edges we need.
737  MBB.addSuccessor(ContinueMBB);
738  MBB.addSuccessor(RoundMBB);
739  RoundMBB->addSuccessor(LoopMBB);
740  LoopMBB->addSuccessor(ContinueMBB);
741  LoopMBB->addSuccessor(LoopMBB);
742 
743  // Mark all the instructions added to the prolog as frame setup.
744  if (InProlog) {
745  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
746  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
747  }
748  for (MachineInstr &MI : *RoundMBB) {
749  MI.setFlag(MachineInstr::FrameSetup);
750  }
751  for (MachineInstr &MI : *LoopMBB) {
752  MI.setFlag(MachineInstr::FrameSetup);
753  }
754  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
755  CMBBI != ContinueMBBI; ++CMBBI) {
756  CMBBI->setFlag(MachineInstr::FrameSetup);
757  }
758  }
759 }
760 
761 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
762  MachineBasicBlock &MBB,
764  const DebugLoc &DL,
765  bool InProlog) const {
766  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
767 
768  // FIXME: Add retpoline support and remove this.
769  if (Is64Bit && IsLargeCodeModel && STI.useRetpolineIndirectCalls())
770  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
771  "code model and retpoline not yet implemented.");
772 
773  unsigned CallOp;
774  if (Is64Bit)
775  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
776  else
777  CallOp = X86::CALLpcrel32;
778 
780 
782  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
783 
784  // All current stack probes take AX and SP as input, clobber flags, and
785  // preserve all registers. x86_64 probes leave RSP unmodified.
786  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
787  // For the large code model, we have to call through a register. Use R11,
788  // as it is scratch in all supported calling conventions.
789  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
790  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
791  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
792  } else {
793  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
794  .addExternalSymbol(MF.createExternalSymbolName(Symbol));
795  }
796 
797  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
798  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
799  CI.addReg(AX, RegState::Implicit)
803  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
804 
805  if (STI.isTargetWin64() || !STI.isOSWindows()) {
806  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
807  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
808  // themselves. They also does not clobber %rax so we can reuse it when
809  // adjusting %rsp.
810  // All other platforms do not specify a particular ABI for the stack probe
811  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
812  BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
813  .addReg(SP)
814  .addReg(AX);
815  }
816 
817  if (InProlog) {
818  // Apply the frame setup flag to all inserted instrs.
819  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
820  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
821  }
822 }
823 
824 void X86FrameLowering::emitStackProbeInlineStub(
826  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
827 
828  assert(InProlog && "ChkStkStub called outside prolog!");
829 
830  BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
831  .addExternalSymbol("__chkstk_stub");
832 }
833 
834 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
835  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
836  // and might require smaller successive adjustments.
837  const uint64_t Win64MaxSEHOffset = 128;
838  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
839  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
840  return SEHFrameOffset & -16;
841 }
842 
843 // If we're forcing a stack realignment we can't rely on just the frame
844 // info, we need to know the ABI stack alignment as well in case we
845 // have a call out. Otherwise just make sure we have some alignment - we'll
846 // go with the minimum SlotSize.
847 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
848  const MachineFrameInfo &MFI = MF.getFrameInfo();
849  uint64_t MaxAlign = MFI.getMaxAlignment(); // Desired stack alignment.
850  unsigned StackAlign = getStackAlignment();
851  if (MF.getFunction().hasFnAttribute("stackrealign")) {
852  if (MFI.hasCalls())
853  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
854  else if (MaxAlign < SlotSize)
855  MaxAlign = SlotSize;
856  }
857  return MaxAlign;
858 }
859 
860 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
862  const DebugLoc &DL, unsigned Reg,
863  uint64_t MaxAlign) const {
864  uint64_t Val = -MaxAlign;
865  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
866  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
867  .addReg(Reg)
868  .addImm(Val)
870 
871  // The EFLAGS implicit def is dead.
872  MI->getOperand(3).setIsDead();
873 }
874 
876  // x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
877  // clobbered by any interrupt handler.
878  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
879  "MF used frame lowering for wrong subtarget");
880  const Function &Fn = MF.getFunction();
881  const bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
882  return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone);
883 }
884 
885 
886 /// emitPrologue - Push callee-saved registers onto the stack, which
887 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
888 /// space for local variables. Also emit labels used by the exception handler to
889 /// generate the exception handling frames.
890 
891 /*
892  Here's a gist of what gets emitted:
893 
894  ; Establish frame pointer, if needed
895  [if needs FP]
896  push %rbp
897  .cfi_def_cfa_offset 16
898  .cfi_offset %rbp, -16
899  .seh_pushreg %rpb
900  mov %rsp, %rbp
901  .cfi_def_cfa_register %rbp
902 
903  ; Spill general-purpose registers
904  [for all callee-saved GPRs]
905  pushq %<reg>
906  [if not needs FP]
907  .cfi_def_cfa_offset (offset from RETADDR)
908  .seh_pushreg %<reg>
909 
910  ; If the required stack alignment > default stack alignment
911  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
912  ; of unknown size in the stack frame.
913  [if stack needs re-alignment]
914  and $MASK, %rsp
915 
916  ; Allocate space for locals
917  [if target is Windows and allocated space > 4096 bytes]
918  ; Windows needs special care for allocations larger
919  ; than one page.
920  mov $NNN, %rax
921  call ___chkstk_ms/___chkstk
922  sub %rax, %rsp
923  [else]
924  sub $NNN, %rsp
925 
926  [if needs FP]
927  .seh_stackalloc (size of XMM spill slots)
928  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
929  [else]
930  .seh_stackalloc NNN
931 
932  ; Spill XMMs
933  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
934  ; they may get spilled on any platform, if the current function
935  ; calls @llvm.eh.unwind.init
936  [if needs FP]
937  [for all callee-saved XMM registers]
938  movaps %<xmm reg>, -MMM(%rbp)
939  [for all callee-saved XMM registers]
940  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
941  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
942  [else]
943  [for all callee-saved XMM registers]
944  movaps %<xmm reg>, KKK(%rsp)
945  [for all callee-saved XMM registers]
946  .seh_savexmm %<xmm reg>, KKK
947 
948  .seh_endprologue
949 
950  [if needs base pointer]
951  mov %rsp, %rbx
952  [if needs to restore base pointer]
953  mov %rsp, -MMM(%rbp)
954 
955  ; Emit CFI info
956  [if needs FP]
957  [for all callee-saved registers]
958  .cfi_offset %<reg>, (offset from %rbp)
959  [else]
960  .cfi_def_cfa_offset (offset from RETADDR)
961  [for all callee-saved registers]
962  .cfi_offset %<reg>, (offset from %rsp)
963 
964  Notes:
965  - .seh directives are emitted only for Windows 64 ABI
966  - .cv_fpo directives are emitted on win32 when emitting CodeView
967  - .cfi directives are emitted for all other ABIs
968  - for 32-bit code, substitute %e?? registers for %r??
969 */
970 
972  MachineBasicBlock &MBB) const {
973  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
974  "MF used frame lowering for wrong subtarget");
975  MachineBasicBlock::iterator MBBI = MBB.begin();
976  MachineFrameInfo &MFI = MF.getFrameInfo();
977  const Function &Fn = MF.getFunction();
978  MachineModuleInfo &MMI = MF.getMMI();
980  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
981  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
982  bool IsFunclet = MBB.isEHFuncletEntry();
984  if (Fn.hasPersonalityFn())
985  Personality = classifyEHPersonality(Fn.getPersonalityFn());
986  bool FnHasClrFunclet =
987  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
988  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
989  bool HasFP = hasFP(MF);
990  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
991  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
992  // FIXME: Emit FPO data for EH funclets.
993  bool NeedsWinFPO =
994  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
995  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
996  bool NeedsDwarfCFI =
997  !IsWin64Prologue && (MMI.hasDebugInfo() || Fn.needsUnwindTableEntry());
998  Register FramePtr = TRI->getFrameRegister(MF);
999  const Register MachineFramePtr =
1001  ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
1002  Register BasePtr = TRI->getBaseRegister();
1003  bool HasWinCFI = false;
1004 
1005  // Debug location must be unknown since the first debug location is used
1006  // to determine the end of the prologue.
1007  DebugLoc DL;
1008 
1009  // Add RETADDR move area to callee saved frame size.
1010  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1011  if (TailCallReturnAddrDelta && IsWin64Prologue)
1012  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1013 
1014  if (TailCallReturnAddrDelta < 0)
1015  X86FI->setCalleeSavedFrameSize(
1016  X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
1017 
1018  bool UseStackProbe = !STI.getTargetLowering()->getStackProbeSymbolName(MF).empty();
1019  unsigned StackProbeSize = STI.getTargetLowering()->getStackProbeSize(MF);
1020 
1021  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1022  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1023  // stack alignment.
1024  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1025  Fn.arg_size() == 2) {
1026  StackSize += 8;
1027  MFI.setStackSize(StackSize);
1028  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1029  }
1030 
1031  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1032  // function, and use up to 128 bytes of stack space, don't have a frame
1033  // pointer, calls, or dynamic alloca then we do not need to adjust the
1034  // stack pointer (we fit in the Red Zone). We also check that we don't
1035  // push and pop from the stack.
1036  if (has128ByteRedZone(MF) &&
1037  !TRI->needsStackRealignment(MF) &&
1038  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1039  !MFI.adjustsStack() && // No calls.
1040  !UseStackProbe && // No stack probes.
1041  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1042  !MF.shouldSplitStack()) { // Regular stack
1043  uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
1044  if (HasFP) MinSize += SlotSize;
1045  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1046  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1047  MFI.setStackSize(StackSize);
1048  }
1049 
1050  // Insert stack pointer adjustment for later moving of return addr. Only
1051  // applies to tail call optimized functions where the callee argument stack
1052  // size is bigger than the callers.
1053  if (TailCallReturnAddrDelta < 0) {
1054  BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
1055  /*InEpilogue=*/false)
1057  }
1058 
1059  // Mapping for machine moves:
1060  //
1061  // DST: VirtualFP AND
1062  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1063  // ELSE => DW_CFA_def_cfa
1064  //
1065  // SRC: VirtualFP AND
1066  // DST: Register => DW_CFA_def_cfa_register
1067  //
1068  // ELSE
1069  // OFFSET < 0 => DW_CFA_offset_extended_sf
1070  // REG < 64 => DW_CFA_offset + Reg
1071  // ELSE => DW_CFA_offset_extended
1072 
1073  uint64_t NumBytes = 0;
1074  int stackGrowth = -SlotSize;
1075 
1076  // Find the funclet establisher parameter
1077  Register Establisher = X86::NoRegister;
1078  if (IsClrFunclet)
1079  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1080  else if (IsFunclet)
1081  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1082 
1083  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1084  // Immediately spill establisher into the home slot.
1085  // The runtime cares about this.
1086  // MOV64mr %rdx, 16(%rsp)
1087  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1088  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1089  .addReg(Establisher)
1091  MBB.addLiveIn(Establisher);
1092  }
1093 
1094  if (HasFP) {
1095  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1096 
1097  // Calculate required stack adjustment.
1098  uint64_t FrameSize = StackSize - SlotSize;
1099  // If required, include space for extra hidden slot for stashing base pointer.
1100  if (X86FI->getRestoreBasePointer())
1101  FrameSize += SlotSize;
1102 
1103  NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1104 
1105  // Callee-saved registers are pushed on stack before the stack is realigned.
1106  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1107  NumBytes = alignTo(NumBytes, MaxAlign);
1108 
1109  // Save EBP/RBP into the appropriate stack slot.
1110  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1111  .addReg(MachineFramePtr, RegState::Kill)
1113 
1114  if (NeedsDwarfCFI) {
1115  // Mark the place where EBP/RBP was saved.
1116  // Define the current CFA rule to use the provided offset.
1117  assert(StackSize);
1118  BuildCFI(MBB, MBBI, DL,
1119  MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1120 
1121  // Change the rule for the FramePtr to be an "offset" rule.
1122  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1124  nullptr, DwarfFramePtr, 2 * stackGrowth));
1125  }
1126 
1127  if (NeedsWinCFI) {
1128  HasWinCFI = true;
1129  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1130  .addImm(FramePtr)
1132  }
1133 
1134  if (!IsWin64Prologue && !IsFunclet) {
1135  // Update EBP with the new base value.
1136  BuildMI(MBB, MBBI, DL,
1137  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1138  FramePtr)
1139  .addReg(StackPtr)
1141 
1142  if (NeedsDwarfCFI) {
1143  // Mark effective beginning of when frame pointer becomes valid.
1144  // Define the current CFA to use the EBP/RBP register.
1145  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1147  nullptr, DwarfFramePtr));
1148  }
1149 
1150  if (NeedsWinFPO) {
1151  // .cv_fpo_setframe $FramePtr
1152  HasWinCFI = true;
1153  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1154  .addImm(FramePtr)
1155  .addImm(0)
1157  }
1158  }
1159  } else {
1160  assert(!IsFunclet && "funclets without FPs not yet implemented");
1161  NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1162  }
1163 
1164  // Update the offset adjustment, which is mainly used by codeview to translate
1165  // from ESP to VFRAME relative local variable offsets.
1166  if (!IsFunclet) {
1167  if (HasFP && TRI->needsStackRealignment(MF))
1168  MFI.setOffsetAdjustment(-NumBytes);
1169  else
1170  MFI.setOffsetAdjustment(-StackSize);
1171  }
1172 
1173  // For EH funclets, only allocate enough space for outgoing calls. Save the
1174  // NumBytes value that we would've used for the parent frame.
1175  unsigned ParentFrameNumBytes = NumBytes;
1176  if (IsFunclet)
1177  NumBytes = getWinEHFuncletFrameSize(MF);
1178 
1179  // Skip the callee-saved push instructions.
1180  bool PushedRegs = false;
1181  int StackOffset = 2 * stackGrowth;
1182 
1183  while (MBBI != MBB.end() &&
1184  MBBI->getFlag(MachineInstr::FrameSetup) &&
1185  (MBBI->getOpcode() == X86::PUSH32r ||
1186  MBBI->getOpcode() == X86::PUSH64r)) {
1187  PushedRegs = true;
1188  Register Reg = MBBI->getOperand(0).getReg();
1189  ++MBBI;
1190 
1191  if (!HasFP && NeedsDwarfCFI) {
1192  // Mark callee-saved push instruction.
1193  // Define the current CFA rule to use the provided offset.
1194  assert(StackSize);
1195  BuildCFI(MBB, MBBI, DL,
1196  MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1197  StackOffset += stackGrowth;
1198  }
1199 
1200  if (NeedsWinCFI) {
1201  HasWinCFI = true;
1202  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1203  .addImm(Reg)
1205  }
1206  }
1207 
1208  // Realign stack after we pushed callee-saved registers (so that we'll be
1209  // able to calculate their offsets from the frame pointer).
1210  // Don't do this for Win64, it needs to realign the stack after the prologue.
1211  if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1212  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1213  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1214 
1215  if (NeedsWinCFI) {
1216  HasWinCFI = true;
1217  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1218  .addImm(MaxAlign)
1220  }
1221  }
1222 
1223  // If there is an SUB32ri of ESP immediately before this instruction, merge
1224  // the two. This can be the case when tail call elimination is enabled and
1225  // the callee has more arguments then the caller.
1226  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1227 
1228  // Adjust stack pointer: ESP -= numbytes.
1229 
1230  // Windows and cygwin/mingw require a prologue helper routine when allocating
1231  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1232  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1233  // stack and adjust the stack pointer in one go. The 64-bit version of
1234  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1235  // responsible for adjusting the stack pointer. Touching the stack at 4K
1236  // increments is necessary to ensure that the guard pages used by the OS
1237  // virtual memory manager are allocated in correct sequence.
1238  uint64_t AlignedNumBytes = NumBytes;
1239  if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1240  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1241  if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1242  assert(!X86FI->getUsesRedZone() &&
1243  "The Red Zone is not accounted for in stack probes");
1244 
1245  // Check whether EAX is livein for this block.
1246  bool isEAXAlive = isEAXLiveIn(MBB);
1247 
1248  if (isEAXAlive) {
1249  if (Is64Bit) {
1250  // Save RAX
1251  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1252  .addReg(X86::RAX, RegState::Kill)
1254  } else {
1255  // Save EAX
1256  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1257  .addReg(X86::EAX, RegState::Kill)
1259  }
1260  }
1261 
1262  if (Is64Bit) {
1263  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1264  // Function prologue is responsible for adjusting the stack pointer.
1265  int Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1266  if (isUInt<32>(Alloc)) {
1267  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1268  .addImm(Alloc)
1270  } else if (isInt<32>(Alloc)) {
1271  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1272  .addImm(Alloc)
1274  } else {
1275  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1276  .addImm(Alloc)
1278  }
1279  } else {
1280  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1281  // We'll also use 4 already allocated bytes for EAX.
1282  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1283  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1285  }
1286 
1287  // Call __chkstk, __chkstk_ms, or __alloca.
1288  emitStackProbe(MF, MBB, MBBI, DL, true);
1289 
1290  if (isEAXAlive) {
1291  // Restore RAX/EAX
1292  MachineInstr *MI;
1293  if (Is64Bit)
1294  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1295  StackPtr, false, NumBytes - 8);
1296  else
1297  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1298  StackPtr, false, NumBytes - 4);
1300  MBB.insert(MBBI, MI);
1301  }
1302  } else if (NumBytes) {
1303  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1304  }
1305 
1306  if (NeedsWinCFI && NumBytes) {
1307  HasWinCFI = true;
1308  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1309  .addImm(NumBytes)
1311  }
1312 
1313  int SEHFrameOffset = 0;
1314  unsigned SPOrEstablisher;
1315  if (IsFunclet) {
1316  if (IsClrFunclet) {
1317  // The establisher parameter passed to a CLR funclet is actually a pointer
1318  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1319  // to find the root function establisher frame by loading the PSPSym from
1320  // the intermediate frame.
1321  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1322  MachinePointerInfo NoInfo;
1323  MBB.addLiveIn(Establisher);
1324  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1325  Establisher, false, PSPSlotOffset)
1328  ;
1329  // Save the root establisher back into the current funclet's (mostly
1330  // empty) frame, in case a sub-funclet or the GC needs it.
1331  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1332  false, PSPSlotOffset)
1333  .addReg(Establisher)
1334  .addMemOperand(
1337  SlotSize, SlotSize));
1338  }
1339  SPOrEstablisher = Establisher;
1340  } else {
1341  SPOrEstablisher = StackPtr;
1342  }
1343 
1344  if (IsWin64Prologue && HasFP) {
1345  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1346  // this calculation on the incoming establisher, which holds the value of
1347  // RSP from the parent frame at the end of the prologue.
1348  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1349  if (SEHFrameOffset)
1350  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1351  SPOrEstablisher, false, SEHFrameOffset);
1352  else
1353  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1354  .addReg(SPOrEstablisher);
1355 
1356  // If this is not a funclet, emit the CFI describing our frame pointer.
1357  if (NeedsWinCFI && !IsFunclet) {
1358  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1359  HasWinCFI = true;
1360  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1361  .addImm(FramePtr)
1362  .addImm(SEHFrameOffset)
1364  if (isAsynchronousEHPersonality(Personality))
1365  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1366  }
1367  } else if (IsFunclet && STI.is32Bit()) {
1368  // Reset EBP / ESI to something good for funclets.
1369  MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1370  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1371  // into the registration node so that the runtime will restore it for us.
1372  if (!MBB.isCleanupFuncletEntry()) {
1373  assert(Personality == EHPersonality::MSVC_CXX);
1374  unsigned FrameReg;
1375  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1376  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg);
1377  // ESP is the first field, so no extra displacement is needed.
1378  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1379  false, EHRegOffset)
1380  .addReg(X86::ESP);
1381  }
1382  }
1383 
1384  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1385  const MachineInstr &FrameInstr = *MBBI;
1386  ++MBBI;
1387 
1388  if (NeedsWinCFI) {
1389  int FI;
1390  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1391  if (X86::FR64RegClass.contains(Reg)) {
1392  unsigned IgnoredFrameReg;
1393  int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1394  Offset += SEHFrameOffset;
1395 
1396  HasWinCFI = true;
1397  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1398  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1399  .addImm(Reg)
1400  .addImm(Offset)
1402  }
1403  }
1404  }
1405  }
1406 
1407  if (NeedsWinCFI && HasWinCFI)
1408  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1409  .setMIFlag(MachineInstr::FrameSetup);
1410 
1411  if (FnHasClrFunclet && !IsFunclet) {
1412  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1413  // immediately after the prolog) into the PSPSlot so that funclets
1414  // and the GC can recover it.
1415  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1416  auto PSPInfo = MachinePointerInfo::getFixedStack(
1417  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1418  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1419  PSPSlotOffset)
1420  .addReg(StackPtr)
1423  SlotSize, SlotSize));
1424  }
1425 
1426  // Realign stack after we spilled callee-saved registers (so that we'll be
1427  // able to calculate their offsets from the frame pointer).
1428  // Win64 requires aligning the stack after the prologue.
1429  if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1430  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1431  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1432  }
1433 
1434  // We already dealt with stack realignment and funclets above.
1435  if (IsFunclet && STI.is32Bit())
1436  return;
1437 
1438  // If we need a base pointer, set it up here. It's whatever the value
1439  // of the stack pointer is at this point. Any variable size objects
1440  // will be allocated after this, so we can still use the base pointer
1441  // to reference locals.
1442  if (TRI->hasBasePointer(MF)) {
1443  // Update the base pointer with the current stack pointer.
1444  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1445  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1446  .addReg(SPOrEstablisher)
1448  if (X86FI->getRestoreBasePointer()) {
1449  // Stash value of base pointer. Saving RSP instead of EBP shortens
1450  // dependence chain. Used by SjLj EH.
1451  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1452  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1453  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1454  .addReg(SPOrEstablisher)
1456  }
1457 
1458  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1459  // Stash the value of the frame pointer relative to the base pointer for
1460  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1461  // it recovers the frame pointer from the base pointer rather than the
1462  // other way around.
1463  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1464  unsigned UsedReg;
1465  int Offset =
1466  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1467  assert(UsedReg == BasePtr);
1468  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1469  .addReg(FramePtr)
1471  }
1472  }
1473 
1474  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1475  // Mark end of stack pointer adjustment.
1476  if (!HasFP && NumBytes) {
1477  // Define the current CFA rule to use the provided offset.
1478  assert(StackSize);
1480  nullptr, -StackSize + stackGrowth));
1481  }
1482 
1483  // Emit DWARF info specifying the offsets of the callee-saved registers.
1484  emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1485  }
1486 
1487  // X86 Interrupt handling function cannot assume anything about the direction
1488  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1489  // in each prologue of interrupt handler function.
1490  //
1491  // FIXME: Create "cld" instruction only in these cases:
1492  // 1. The interrupt handling function uses any of the "rep" instructions.
1493  // 2. Interrupt handling function calls another function.
1494  //
1496  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1497  .setMIFlag(MachineInstr::FrameSetup);
1498 
1499  // At this point we know if the function has WinCFI or not.
1500  MF.setHasWinCFI(HasWinCFI);
1501 }
1502 
1504  const MachineFunction &MF) const {
1505  // We can't use LEA instructions for adjusting the stack pointer if we don't
1506  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1507  // to deallocate the stack.
1508  // This means that we can use LEA for SP in two situations:
1509  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1510  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1511  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1512 }
1513 
1515  switch (MI.getOpcode()) {
1516  case X86::CATCHRET:
1517  case X86::CLEANUPRET:
1518  return true;
1519  default:
1520  return false;
1521  }
1522  llvm_unreachable("impossible");
1523 }
1524 
1525 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1526 // stack. It holds a pointer to the bottom of the root function frame. The
1527 // establisher frame pointer passed to a nested funclet may point to the
1528 // (mostly empty) frame of its parent funclet, but it will need to find
1529 // the frame of the root function to access locals. To facilitate this,
1530 // every funclet copies the pointer to the bottom of the root function
1531 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1532 // same offset for the PSPSym in the root function frame that's used in the
1533 // funclets' frames allows each funclet to dynamically accept any ancestor
1534 // frame as its establisher argument (the runtime doesn't guarantee the
1535 // immediate parent for some reason lost to history), and also allows the GC,
1536 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1537 // frame with only a single offset reported for the entire method.
1538 unsigned
1539 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1540  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1541  unsigned SPReg;
1543  /*IgnoreSPUpdates*/ true);
1544  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1545  return static_cast<unsigned>(Offset);
1546 }
1547 
1548 unsigned
1549 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1550  // This is the size of the pushed CSRs.
1551  unsigned CSSize =
1552  MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1553  // This is the amount of stack a funclet needs to allocate.
1554  unsigned UsedSize;
1555  EHPersonality Personality =
1557  if (Personality == EHPersonality::CoreCLR) {
1558  // CLR funclets need to hold enough space to include the PSPSym, at the
1559  // same offset from the stack pointer (immediately after the prolog) as it
1560  // resides at in the main function.
1561  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1562  } else {
1563  // Other funclets just need enough stack for outgoing call arguments.
1564  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1565  }
1566  // RBP is not included in the callee saved register block. After pushing RBP,
1567  // everything is 16 byte aligned. Everything we allocate before an outgoing
1568  // call must also be 16 byte aligned.
1569  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
1570  // Subtract out the size of the callee saved registers. This is how much stack
1571  // each funclet will allocate.
1572  return FrameSizeMinusRBP - CSSize;
1573 }
1574 
1575 static bool isTailCallOpcode(unsigned Opc) {
1576  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
1577  Opc == X86::TCRETURNmi ||
1578  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
1579  Opc == X86::TCRETURNmi64;
1580 }
1581 
1583  MachineBasicBlock &MBB) const {
1584  const MachineFrameInfo &MFI = MF.getFrameInfo();
1588  DebugLoc DL;
1589  if (MBBI != MBB.end())
1590  DL = MBBI->getDebugLoc();
1591  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1592  const bool Is64BitILP32 = STI.isTarget64BitILP32();
1593  Register FramePtr = TRI->getFrameRegister(MF);
1594  unsigned MachineFramePtr =
1595  Is64BitILP32 ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
1596 
1597  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1598  bool NeedsWin64CFI =
1599  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
1600  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
1601 
1602  // Get the number of bytes to allocate from the FrameInfo.
1603  uint64_t StackSize = MFI.getStackSize();
1604  uint64_t MaxAlign = calculateMaxStackAlign(MF);
1605  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1606  bool HasFP = hasFP(MF);
1607  uint64_t NumBytes = 0;
1608 
1609  bool NeedsDwarfCFI =
1610  (!MF.getTarget().getTargetTriple().isOSDarwin() &&
1611  !MF.getTarget().getTargetTriple().isOSWindows()) &&
1613 
1614  if (IsFunclet) {
1615  assert(HasFP && "EH funclets without FP not yet implemented");
1616  NumBytes = getWinEHFuncletFrameSize(MF);
1617  } else if (HasFP) {
1618  // Calculate required stack adjustment.
1619  uint64_t FrameSize = StackSize - SlotSize;
1620  NumBytes = FrameSize - CSSize;
1621 
1622  // Callee-saved registers were pushed on stack before the stack was
1623  // realigned.
1624  if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1625  NumBytes = alignTo(FrameSize, MaxAlign);
1626  } else {
1627  NumBytes = StackSize - CSSize;
1628  }
1629  uint64_t SEHStackAllocAmt = NumBytes;
1630 
1631  if (HasFP) {
1632  // Pop EBP.
1633  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1634  MachineFramePtr)
1635  .setMIFlag(MachineInstr::FrameDestroy);
1636  if (NeedsDwarfCFI) {
1637  unsigned DwarfStackPtr =
1638  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
1640  nullptr, DwarfStackPtr, -SlotSize));
1641  --MBBI;
1642  }
1643  }
1644 
1645  MachineBasicBlock::iterator FirstCSPop = MBBI;
1646  // Skip the callee-saved pop instructions.
1647  while (MBBI != MBB.begin()) {
1648  MachineBasicBlock::iterator PI = std::prev(MBBI);
1649  unsigned Opc = PI->getOpcode();
1650 
1651  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1652  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1653  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1654  break;
1655  FirstCSPop = PI;
1656  }
1657 
1658  --MBBI;
1659  }
1660  MBBI = FirstCSPop;
1661 
1662  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1663  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
1664 
1665  if (MBBI != MBB.end())
1666  DL = MBBI->getDebugLoc();
1667 
1668  // If there is an ADD32ri or SUB32ri of ESP immediately before this
1669  // instruction, merge the two instructions.
1670  if (NumBytes || MFI.hasVarSizedObjects())
1671  NumBytes += mergeSPUpdates(MBB, MBBI, true);
1672 
1673  // If dynamic alloca is used, then reset esp to point to the last callee-saved
1674  // slot before popping them off! Same applies for the case, when stack was
1675  // realigned. Don't do this if this was a funclet epilogue, since the funclets
1676  // will not do realignment or dynamic stack allocation.
1677  if ((TRI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) &&
1678  !IsFunclet) {
1679  if (TRI->needsStackRealignment(MF))
1680  MBBI = FirstCSPop;
1681  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1682  uint64_t LEAAmount =
1683  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1684 
1685  // There are only two legal forms of epilogue:
1686  // - add SEHAllocationSize, %rsp
1687  // - lea SEHAllocationSize(%FramePtr), %rsp
1688  //
1689  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1690  // However, we may use this sequence if we have a frame pointer because the
1691  // effects of the prologue can safely be undone.
1692  if (LEAAmount != 0) {
1693  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1694  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1695  FramePtr, false, LEAAmount);
1696  --MBBI;
1697  } else {
1698  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1699  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1700  .addReg(FramePtr);
1701  --MBBI;
1702  }
1703  } else if (NumBytes) {
1704  // Adjust stack pointer back: ESP += numbytes.
1705  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
1706  if (!hasFP(MF) && NeedsDwarfCFI) {
1707  // Define the current CFA rule to use the provided offset.
1709  nullptr, -CSSize - SlotSize));
1710  }
1711  --MBBI;
1712  }
1713 
1714  // Windows unwinder will not invoke function's exception handler if IP is
1715  // either in prologue or in epilogue. This behavior causes a problem when a
1716  // call immediately precedes an epilogue, because the return address points
1717  // into the epilogue. To cope with that, we insert an epilogue marker here,
1718  // then replace it with a 'nop' if it ends up immediately after a CALL in the
1719  // final emitted code.
1720  if (NeedsWin64CFI && MF.hasWinCFI())
1721  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1722 
1723  if (!hasFP(MF) && NeedsDwarfCFI) {
1724  MBBI = FirstCSPop;
1725  int64_t Offset = -CSSize - SlotSize;
1726  // Mark callee-saved pop instruction.
1727  // Define the current CFA rule to use the provided offset.
1728  while (MBBI != MBB.end()) {
1729  MachineBasicBlock::iterator PI = MBBI;
1730  unsigned Opc = PI->getOpcode();
1731  ++MBBI;
1732  if (Opc == X86::POP32r || Opc == X86::POP64r) {
1733  Offset += SlotSize;
1734  BuildCFI(MBB, MBBI, DL,
1735  MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
1736  }
1737  }
1738  }
1739 
1740  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
1741  // Add the return addr area delta back since we are not tail calling.
1742  int Offset = -1 * X86FI->getTCReturnAddrDelta();
1743  assert(Offset >= 0 && "TCDelta should never be positive");
1744  if (Offset) {
1745  // Check for possible merge with preceding ADD instruction.
1746  Offset += mergeSPUpdates(MBB, Terminator, true);
1747  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
1748  }
1749  }
1750 }
1751 
1753  unsigned &FrameReg) const {
1754  const MachineFrameInfo &MFI = MF.getFrameInfo();
1755 
1756  bool IsFixed = MFI.isFixedObjectIndex(FI);
1757  // We can't calculate offset from frame pointer if the stack is realigned,
1758  // so enforce usage of stack/base pointer. The base pointer is used when we
1759  // have dynamic allocas in addition to dynamic realignment.
1760  if (TRI->hasBasePointer(MF))
1761  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
1762  else if (TRI->needsStackRealignment(MF))
1763  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
1764  else
1765  FrameReg = TRI->getFrameRegister(MF);
1766 
1767  // Offset will hold the offset from the stack pointer at function entry to the
1768  // object.
1769  // We need to factor in additional offsets applied during the prologue to the
1770  // frame, base, and stack pointer depending on which is used.
1771  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
1773  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1774  uint64_t StackSize = MFI.getStackSize();
1775  bool HasFP = hasFP(MF);
1776  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1777  int64_t FPDelta = 0;
1778 
1779  // In an x86 interrupt, remove the offset we added to account for the return
1780  // address from any stack object allocated in the caller's frame. Interrupts
1781  // do not have a standard return address. Fixed objects in the current frame,
1782  // such as SSE register spills, should not get this treatment.
1784  Offset >= 0) {
1785  Offset += getOffsetOfLocalArea();
1786  }
1787 
1788  if (IsWin64Prologue) {
1789  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
1790 
1791  // Calculate required stack adjustment.
1792  uint64_t FrameSize = StackSize - SlotSize;
1793  // If required, include space for extra hidden slot for stashing base pointer.
1794  if (X86FI->getRestoreBasePointer())
1795  FrameSize += SlotSize;
1796  uint64_t NumBytes = FrameSize - CSSize;
1797 
1798  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1799  if (FI && FI == X86FI->getFAIndex())
1800  return -SEHFrameOffset;
1801 
1802  // FPDelta is the offset from the "traditional" FP location of the old base
1803  // pointer followed by return address and the location required by the
1804  // restricted Win64 prologue.
1805  // Add FPDelta to all offsets below that go through the frame pointer.
1806  FPDelta = FrameSize - SEHFrameOffset;
1807  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
1808  "FPDelta isn't aligned per the Win64 ABI!");
1809  }
1810 
1811 
1812  if (TRI->hasBasePointer(MF)) {
1813  assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1814  if (FI < 0) {
1815  // Skip the saved EBP.
1816  return Offset + SlotSize + FPDelta;
1817  } else {
1818  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1819  return Offset + StackSize;
1820  }
1821  } else if (TRI->needsStackRealignment(MF)) {
1822  if (FI < 0) {
1823  // Skip the saved EBP.
1824  return Offset + SlotSize + FPDelta;
1825  } else {
1826  assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
1827  return Offset + StackSize;
1828  }
1829  // FIXME: Support tail calls
1830  } else {
1831  if (!HasFP)
1832  return Offset + StackSize;
1833 
1834  // Skip the saved EBP.
1835  Offset += SlotSize;
1836 
1837  // Skip the RETADDR move area
1838  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1839  if (TailCallReturnAddrDelta < 0)
1840  Offset -= TailCallReturnAddrDelta;
1841  }
1842 
1843  return Offset + FPDelta;
1844 }
1845 
1847  int FI, unsigned &FrameReg,
1848  int Adjustment) const {
1849  const MachineFrameInfo &MFI = MF.getFrameInfo();
1850  FrameReg = TRI->getStackRegister();
1851  return MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + Adjustment;
1852 }
1853 
1854 int
1856  int FI, unsigned &FrameReg,
1857  bool IgnoreSPUpdates) const {
1858 
1859  const MachineFrameInfo &MFI = MF.getFrameInfo();
1860  // Does not include any dynamic realign.
1861  const uint64_t StackSize = MFI.getStackSize();
1862  // LLVM arranges the stack as follows:
1863  // ...
1864  // ARG2
1865  // ARG1
1866  // RETADDR
1867  // PUSH RBP <-- RBP points here
1868  // PUSH CSRs
1869  // ~~~~~~~ <-- possible stack realignment (non-win64)
1870  // ...
1871  // STACK OBJECTS
1872  // ... <-- RSP after prologue points here
1873  // ~~~~~~~ <-- possible stack realignment (win64)
1874  //
1875  // if (hasVarSizedObjects()):
1876  // ... <-- "base pointer" (ESI/RBX) points here
1877  // DYNAMIC ALLOCAS
1878  // ... <-- RSP points here
1879  //
1880  // Case 1: In the simple case of no stack realignment and no dynamic
1881  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1882  // with fixed offsets from RSP.
1883  //
1884  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1885  // stack objects are addressed with RBP and regular stack objects with RSP.
1886  //
1887  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1888  // to address stack arguments for outgoing calls and nothing else. The "base
1889  // pointer" points to local variables, and RBP points to fixed objects.
1890  //
1891  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1892  // answer we give is relative to the SP after the prologue, and not the
1893  // SP in the middle of the function.
1894 
1895  if (MFI.isFixedObjectIndex(FI) && TRI->needsStackRealignment(MF) &&
1896  !STI.isTargetWin64())
1897  return getFrameIndexReference(MF, FI, FrameReg);
1898 
1899  // If !hasReservedCallFrame the function might have SP adjustement in the
1900  // body. So, even though the offset is statically known, it depends on where
1901  // we are in the function.
1902  if (!IgnoreSPUpdates && !hasReservedCallFrame(MF))
1903  return getFrameIndexReference(MF, FI, FrameReg);
1904 
1905  // We don't handle tail calls, and shouldn't be seeing them either.
1907  "we don't handle this case!");
1908 
1909  // This is how the math works out:
1910  //
1911  // %rsp grows (i.e. gets lower) left to right. Each box below is
1912  // one word (eight bytes). Obj0 is the stack slot we're trying to
1913  // get to.
1914  //
1915  // ----------------------------------
1916  // | BP | Obj0 | Obj1 | ... | ObjN |
1917  // ----------------------------------
1918  // ^ ^ ^ ^
1919  // A B C E
1920  //
1921  // A is the incoming stack pointer.
1922  // (B - A) is the local area offset (-8 for x86-64) [1]
1923  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
1924  //
1925  // |(E - B)| is the StackSize (absolute value, positive). For a
1926  // stack that grown down, this works out to be (B - E). [3]
1927  //
1928  // E is also the value of %rsp after stack has been set up, and we
1929  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1930  // (C - E) == (C - A) - (B - A) + (B - E)
1931  // { Using [1], [2] and [3] above }
1932  // == getObjectOffset - LocalAreaOffset + StackSize
1933 
1934  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
1935 }
1936 
1939  std::vector<CalleeSavedInfo> &CSI) const {
1940  MachineFrameInfo &MFI = MF.getFrameInfo();
1942 
1943  unsigned CalleeSavedFrameSize = 0;
1944  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1945 
1946  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1947 
1948  if (TailCallReturnAddrDelta < 0) {
1949  // create RETURNADDR area
1950  // arg
1951  // arg
1952  // RETADDR
1953  // { ...
1954  // RETADDR area
1955  // ...
1956  // }
1957  // [EBP]
1958  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
1959  TailCallReturnAddrDelta - SlotSize, true);
1960  }
1961 
1962  // Spill the BasePtr if it's used.
1963  if (this->TRI->hasBasePointer(MF)) {
1964  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1965  if (MF.hasEHFunclets()) {
1966  int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
1967  X86FI->setHasSEHFramePtrSave(true);
1968  X86FI->setSEHFramePtrSaveIndex(FI);
1969  }
1970  }
1971 
1972  if (hasFP(MF)) {
1973  // emitPrologue always spills frame register the first thing.
1974  SpillSlotOffset -= SlotSize;
1975  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1976 
1977  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1978  // the frame register, we can delete it from CSI list and not have to worry
1979  // about avoiding it later.
1980  Register FPReg = TRI->getFrameRegister(MF);
1981  for (unsigned i = 0; i < CSI.size(); ++i) {
1982  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1983  CSI.erase(CSI.begin() + i);
1984  break;
1985  }
1986  }
1987  }
1988 
1989  // Assign slots for GPRs. It increases frame size.
1990  for (unsigned i = CSI.size(); i != 0; --i) {
1991  unsigned Reg = CSI[i - 1].getReg();
1992 
1993  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1994  continue;
1995 
1996  SpillSlotOffset -= SlotSize;
1997  CalleeSavedFrameSize += SlotSize;
1998 
1999  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2000  CSI[i - 1].setFrameIdx(SlotIndex);
2001  }
2002 
2003  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2004  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2005 
2006  // Assign slots for XMMs.
2007  for (unsigned i = CSI.size(); i != 0; --i) {
2008  unsigned Reg = CSI[i - 1].getReg();
2009  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2010  continue;
2011 
2012  // If this is k-register make sure we lookup via the largest legal type.
2013  MVT VT = MVT::Other;
2014  if (X86::VK16RegClass.contains(Reg))
2015  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2016 
2017  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2018  unsigned Size = TRI->getSpillSize(*RC);
2019  unsigned Align = TRI->getSpillAlignment(*RC);
2020  // ensure alignment
2021  SpillSlotOffset -= std::abs(SpillSlotOffset) % Align;
2022  // spill into slot
2023  SpillSlotOffset -= Size;
2024  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2025  CSI[i - 1].setFrameIdx(SlotIndex);
2026  MFI.ensureMaxAlignment(Align);
2027  }
2028 
2029  return true;
2030 }
2031 
2034  const std::vector<CalleeSavedInfo> &CSI,
2035  const TargetRegisterInfo *TRI) const {
2036  DebugLoc DL = MBB.findDebugLoc(MI);
2037 
2038  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2039  // for us, and there are no XMM CSRs on Win32.
2040  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2041  return true;
2042 
2043  // Push GPRs. It increases frame size.
2044  const MachineFunction &MF = *MBB.getParent();
2045  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2046  for (unsigned i = CSI.size(); i != 0; --i) {
2047  unsigned Reg = CSI[i - 1].getReg();
2048 
2049  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2050  continue;
2051 
2052  const MachineRegisterInfo &MRI = MF.getRegInfo();
2053  bool isLiveIn = MRI.isLiveIn(Reg);
2054  if (!isLiveIn)
2055  MBB.addLiveIn(Reg);
2056 
2057  // Decide whether we can add a kill flag to the use.
2058  bool CanKill = !isLiveIn;
2059  // Check if any subregister is live-in
2060  if (CanKill) {
2061  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2062  if (MRI.isLiveIn(*AReg)) {
2063  CanKill = false;
2064  break;
2065  }
2066  }
2067  }
2068 
2069  // Do not set a kill flag on values that are also marked as live-in. This
2070  // happens with the @llvm-returnaddress intrinsic and with arguments
2071  // passed in callee saved registers.
2072  // Omitting the kill flags is conservatively correct even if the live-in
2073  // is not used after all.
2074  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2075  .setMIFlag(MachineInstr::FrameSetup);
2076  }
2077 
2078  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2079  // It can be done by spilling XMMs to stack frame.
2080  for (unsigned i = CSI.size(); i != 0; --i) {
2081  unsigned Reg = CSI[i-1].getReg();
2082  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2083  continue;
2084 
2085  // If this is k-register make sure we lookup via the largest legal type.
2086  MVT VT = MVT::Other;
2087  if (X86::VK16RegClass.contains(Reg))
2088  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2089 
2090  // Add the callee-saved register as live-in. It's killed at the spill.
2091  MBB.addLiveIn(Reg);
2092  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2093 
2094  TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2095  TRI);
2096  --MI;
2097  MI->setFlag(MachineInstr::FrameSetup);
2098  ++MI;
2099  }
2100 
2101  return true;
2102 }
2103 
2104 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2106  MachineInstr *CatchRet) const {
2107  // SEH shouldn't use catchret.
2109  MBB.getParent()->getFunction().getPersonalityFn())) &&
2110  "SEH should not use CATCHRET");
2111  DebugLoc DL = CatchRet->getDebugLoc();
2112  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2113 
2114  // Fill EAX/RAX with the address of the target block.
2115  if (STI.is64Bit()) {
2116  // LEA64r CatchRetTarget(%rip), %rax
2117  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2118  .addReg(X86::RIP)
2119  .addImm(0)
2120  .addReg(0)
2121  .addMBB(CatchRetTarget)
2122  .addReg(0);
2123  } else {
2124  // MOV32ri $CatchRetTarget, %eax
2125  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2126  .addMBB(CatchRetTarget);
2127  }
2128 
2129  // Record that we've taken the address of CatchRetTarget and no longer just
2130  // reference it in a terminator.
2131  CatchRetTarget->setHasAddressTaken();
2132 }
2133 
2136  std::vector<CalleeSavedInfo> &CSI,
2137  const TargetRegisterInfo *TRI) const {
2138  if (CSI.empty())
2139  return false;
2140 
2141  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2142  // Don't restore CSRs in 32-bit EH funclets. Matches
2143  // spillCalleeSavedRegisters.
2144  if (STI.is32Bit())
2145  return true;
2146  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2147  // funclets. emitEpilogue transforms these to normal jumps.
2148  if (MI->getOpcode() == X86::CATCHRET) {
2149  const Function &F = MBB.getParent()->getFunction();
2150  bool IsSEH = isAsynchronousEHPersonality(
2152  if (IsSEH)
2153  return true;
2154  }
2155  }
2156 
2157  DebugLoc DL = MBB.findDebugLoc(MI);
2158 
2159  // Reload XMMs from stack frame.
2160  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2161  unsigned Reg = CSI[i].getReg();
2162  if (X86::GR64RegClass.contains(Reg) ||
2163  X86::GR32RegClass.contains(Reg))
2164  continue;
2165 
2166  // If this is k-register make sure we lookup via the largest legal type.
2167  MVT VT = MVT::Other;
2168  if (X86::VK16RegClass.contains(Reg))
2169  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2170 
2171  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2172  TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2173  }
2174 
2175  // POP GPRs.
2176  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2177  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2178  unsigned Reg = CSI[i].getReg();
2179  if (!X86::GR64RegClass.contains(Reg) &&
2180  !X86::GR32RegClass.contains(Reg))
2181  continue;
2182 
2183  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2184  .setMIFlag(MachineInstr::FrameDestroy);
2185  }
2186  return true;
2187 }
2188 
2190  BitVector &SavedRegs,
2191  RegScavenger *RS) const {
2192  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2193 
2194  // Spill the BasePtr if it's used.
2195  if (TRI->hasBasePointer(MF)){
2196  Register BasePtr = TRI->getBaseRegister();
2197  if (STI.isTarget64BitILP32())
2198  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2199  SavedRegs.set(BasePtr);
2200  }
2201 }
2202 
2203 static bool
2205  const Function &F = MF->getFunction();
2206  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2207  I != E; I++) {
2208  if (I->hasNestAttr() && !I->use_empty())
2209  return true;
2210  }
2211  return false;
2212 }
2213 
2214 /// GetScratchRegister - Get a temp register for performing work in the
2215 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2216 /// and the properties of the function either one or two registers will be
2217 /// needed. Set primary to true for the first register, false for the second.
2218 static unsigned
2219 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2221 
2222  // Erlang stuff.
2223  if (CallingConvention == CallingConv::HiPE) {
2224  if (Is64Bit)
2225  return Primary ? X86::R14 : X86::R13;
2226  else
2227  return Primary ? X86::EBX : X86::EDI;
2228  }
2229 
2230  if (Is64Bit) {
2231  if (IsLP64)
2232  return Primary ? X86::R11 : X86::R12;
2233  else
2234  return Primary ? X86::R11D : X86::R12D;
2235  }
2236 
2237  bool IsNested = HasNestArgument(&MF);
2238 
2239  if (CallingConvention == CallingConv::X86_FastCall ||
2240  CallingConvention == CallingConv::Fast) {
2241  if (IsNested)
2242  report_fatal_error("Segmented stacks does not support fastcall with "
2243  "nested function.");
2244  return Primary ? X86::EAX : X86::ECX;
2245  }
2246  if (IsNested)
2247  return Primary ? X86::EDX : X86::EAX;
2248  return Primary ? X86::ECX : X86::EAX;
2249 }
2250 
2251 // The stack limit in the TCB is set to this many bytes above the actual stack
2252 // limit.
2253 static const uint64_t kSplitStackAvailable = 256;
2254 
2256  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2257  MachineFrameInfo &MFI = MF.getFrameInfo();
2258  uint64_t StackSize;
2259  unsigned TlsReg, TlsOffset;
2260  DebugLoc DL;
2261 
2262  // To support shrink-wrapping we would need to insert the new blocks
2263  // at the right place and update the branches to PrologueMBB.
2264  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2265 
2266  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2267  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2268  "Scratch register is live-in");
2269 
2270  if (MF.getFunction().isVarArg())
2271  report_fatal_error("Segmented stacks do not support vararg functions.");
2272  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2273  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2275  report_fatal_error("Segmented stacks not supported on this platform.");
2276 
2277  // Eventually StackSize will be calculated by a link-time pass; which will
2278  // also decide whether checking code needs to be injected into this particular
2279  // prologue.
2280  StackSize = MFI.getStackSize();
2281 
2282  // Do not generate a prologue for leaf functions with a stack of size zero.
2283  // For non-leaf functions we have to allow for the possibility that the
2284  // callis to a non-split function, as in PR37807. This function could also
2285  // take the address of a non-split function. When the linker tries to adjust
2286  // its non-existent prologue, it would fail with an error. Mark the object
2287  // file so that such failures are not errors. See this Go language bug-report
2288  // https://go-review.googlesource.com/c/go/+/148819/
2289  if (StackSize == 0 && !MFI.hasTailCall()) {
2290  MF.getMMI().setHasNosplitStack(true);
2291  return;
2292  }
2293 
2294  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2295  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2297  bool IsNested = false;
2298 
2299  // We need to know if the function has a nest argument only in 64 bit mode.
2300  if (Is64Bit)
2301  IsNested = HasNestArgument(&MF);
2302 
2303  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2304  // allocMBB needs to be last (terminating) instruction.
2305 
2306  for (const auto &LI : PrologueMBB.liveins()) {
2307  allocMBB->addLiveIn(LI);
2308  checkMBB->addLiveIn(LI);
2309  }
2310 
2311  if (IsNested)
2312  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2313 
2314  MF.push_front(allocMBB);
2315  MF.push_front(checkMBB);
2316 
2317  // When the frame size is less than 256 we just compare the stack
2318  // boundary directly to the value of the stack pointer, per gcc.
2319  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2320 
2321  // Read the limit off the current stacklet off the stack_guard location.
2322  if (Is64Bit) {
2323  if (STI.isTargetLinux()) {
2324  TlsReg = X86::FS;
2325  TlsOffset = IsLP64 ? 0x70 : 0x40;
2326  } else if (STI.isTargetDarwin()) {
2327  TlsReg = X86::GS;
2328  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2329  } else if (STI.isTargetWin64()) {
2330  TlsReg = X86::GS;
2331  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2332  } else if (STI.isTargetFreeBSD()) {
2333  TlsReg = X86::FS;
2334  TlsOffset = 0x18;
2335  } else if (STI.isTargetDragonFly()) {
2336  TlsReg = X86::FS;
2337  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2338  } else {
2339  report_fatal_error("Segmented stacks not supported on this platform.");
2340  }
2341 
2342  if (CompareStackPointer)
2343  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2344  else
2345  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2346  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2347 
2348  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2349  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2350  } else {
2351  if (STI.isTargetLinux()) {
2352  TlsReg = X86::GS;
2353  TlsOffset = 0x30;
2354  } else if (STI.isTargetDarwin()) {
2355  TlsReg = X86::GS;
2356  TlsOffset = 0x48 + 90*4;
2357  } else if (STI.isTargetWin32()) {
2358  TlsReg = X86::FS;
2359  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2360  } else if (STI.isTargetDragonFly()) {
2361  TlsReg = X86::FS;
2362  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2363  } else if (STI.isTargetFreeBSD()) {
2364  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2365  } else {
2366  report_fatal_error("Segmented stacks not supported on this platform.");
2367  }
2368 
2369  if (CompareStackPointer)
2370  ScratchReg = X86::ESP;
2371  else
2372  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2373  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2374 
2375  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2376  STI.isTargetDragonFly()) {
2377  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2378  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2379  } else if (STI.isTargetDarwin()) {
2380 
2381  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2382  unsigned ScratchReg2;
2383  bool SaveScratch2;
2384  if (CompareStackPointer) {
2385  // The primary scratch register is available for holding the TLS offset.
2386  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2387  SaveScratch2 = false;
2388  } else {
2389  // Need to use a second register to hold the TLS offset
2390  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2391 
2392  // Unfortunately, with fastcc the second scratch register may hold an
2393  // argument.
2394  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2395  }
2396 
2397  // If Scratch2 is live-in then it needs to be saved.
2398  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2399  "Scratch register is live-in and not saved");
2400 
2401  if (SaveScratch2)
2402  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2403  .addReg(ScratchReg2, RegState::Kill);
2404 
2405  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2406  .addImm(TlsOffset);
2407  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2408  .addReg(ScratchReg)
2409  .addReg(ScratchReg2).addImm(1).addReg(0)
2410  .addImm(0)
2411  .addReg(TlsReg);
2412 
2413  if (SaveScratch2)
2414  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2415  }
2416  }
2417 
2418  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2419  // It jumps to normal execution of the function body.
2420  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2421 
2422  // On 32 bit we first push the arguments size and then the frame size. On 64
2423  // bit, we pass the stack frame size in r10 and the argument size in r11.
2424  if (Is64Bit) {
2425  // Functions with nested arguments use R10, so it needs to be saved across
2426  // the call to _morestack
2427 
2428  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2429  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2430  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2431  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2432  const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2433 
2434  if (IsNested)
2435  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2436 
2437  BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2438  .addImm(StackSize);
2439  BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2440  .addImm(X86FI->getArgumentStackSize());
2441  } else {
2442  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2443  .addImm(X86FI->getArgumentStackSize());
2444  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2445  .addImm(StackSize);
2446  }
2447 
2448  // __morestack is in libgcc
2449  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2450  // Under the large code model, we cannot assume that __morestack lives
2451  // within 2^31 bytes of the call site, so we cannot use pc-relative
2452  // addressing. We cannot perform the call via a temporary register,
2453  // as the rax register may be used to store the static chain, and all
2454  // other suitable registers may be either callee-save or used for
2455  // parameter passing. We cannot use the stack at this point either
2456  // because __morestack manipulates the stack directly.
2457  //
2458  // To avoid these issues, perform an indirect call via a read-only memory
2459  // location containing the address.
2460  //
2461  // This solution is not perfect, as it assumes that the .rodata section
2462  // is laid out within 2^31 bytes of each function body, but this seems
2463  // to be sufficient for JIT.
2464  // FIXME: Add retpoline support and remove the error here..
2466  report_fatal_error("Emitting morestack calls on 64-bit with the large "
2467  "code model and retpoline not yet implemented.");
2468  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2469  .addReg(X86::RIP)
2470  .addImm(0)
2471  .addReg(0)
2472  .addExternalSymbol("__morestack_addr")
2473  .addReg(0);
2474  MF.getMMI().setUsesMorestackAddr(true);
2475  } else {
2476  if (Is64Bit)
2477  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2478  .addExternalSymbol("__morestack");
2479  else
2480  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2481  .addExternalSymbol("__morestack");
2482  }
2483 
2484  if (IsNested)
2485  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2486  else
2487  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2488 
2489  allocMBB->addSuccessor(&PrologueMBB);
2490 
2491  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2492  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2493 
2494 #ifdef EXPENSIVE_CHECKS
2495  MF.verify();
2496 #endif
2497 }
2498 
2499 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
2500 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
2501 /// to fields it needs, through a named metadata node "hipe.literals" containing
2502 /// name-value pairs.
2503 static unsigned getHiPELiteral(
2504  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
2505  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
2506  MDNode *Node = HiPELiteralsMD->getOperand(i);
2507  if (Node->getNumOperands() != 2) continue;
2508  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
2509  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
2510  if (!NodeName || !NodeVal) continue;
2511  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
2512  if (ValConst && NodeName->getString() == LiteralName) {
2513  return ValConst->getZExtValue();
2514  }
2515  }
2516 
2517  report_fatal_error("HiPE literal " + LiteralName
2518  + " required but not provided");
2519 }
2520 
2521 /// Erlang programs may need a special prologue to handle the stack size they
2522 /// might need at runtime. That is because Erlang/OTP does not implement a C
2523 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2524 /// (for more information see Eric Stenman's Ph.D. thesis:
2525 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2526 ///
2527 /// CheckStack:
2528 /// temp0 = sp - MaxStack
2529 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2530 /// OldStart:
2531 /// ...
2532 /// IncStack:
2533 /// call inc_stack # doubles the stack space
2534 /// temp0 = sp - MaxStack
2535 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2537  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2538  MachineFrameInfo &MFI = MF.getFrameInfo();
2539  DebugLoc DL;
2540 
2541  // To support shrink-wrapping we would need to insert the new blocks
2542  // at the right place and update the branches to PrologueMBB.
2543  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2544 
2545  // HiPE-specific values
2546  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
2547  ->getNamedMetadata("hipe.literals");
2548  if (!HiPELiteralsMD)
2550  "Can't generate HiPE prologue without runtime parameters");
2551  const unsigned HipeLeafWords
2552  = getHiPELiteral(HiPELiteralsMD,
2553  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
2554  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2555  const unsigned Guaranteed = HipeLeafWords * SlotSize;
2556  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
2557  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
2558  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
2559 
2560  assert(STI.isTargetLinux() &&
2561  "HiPE prologue is only supported on Linux operating systems.");
2562 
2563  // Compute the largest caller's frame that is needed to fit the callees'
2564  // frames. This 'MaxStack' is computed from:
2565  //
2566  // a) the fixed frame size, which is the space needed for all spilled temps,
2567  // b) outgoing on-stack parameter areas, and
2568  // c) the minimum stack space this function needs to make available for the
2569  // functions it calls (a tunable ABI property).
2570  if (MFI.hasCalls()) {
2571  unsigned MoreStackForCalls = 0;
2572 
2573  for (auto &MBB : MF) {
2574  for (auto &MI : MBB) {
2575  if (!MI.isCall())
2576  continue;
2577 
2578  // Get callee operand.
2579  const MachineOperand &MO = MI.getOperand(0);
2580 
2581  // Only take account of global function calls (no closures etc.).
2582  if (!MO.isGlobal())
2583  continue;
2584 
2585  const Function *F = dyn_cast<Function>(MO.getGlobal());
2586  if (!F)
2587  continue;
2588 
2589  // Do not update 'MaxStack' for primitive and built-in functions
2590  // (encoded with names either starting with "erlang."/"bif_" or not
2591  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2592  // "_", such as the BIF "suspend_0") as they are executed on another
2593  // stack.
2594  if (F->getName().find("erlang.") != StringRef::npos ||
2595  F->getName().find("bif_") != StringRef::npos ||
2596  F->getName().find_first_of("._") == StringRef::npos)
2597  continue;
2598 
2599  unsigned CalleeStkArity =
2600  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2601  if (HipeLeafWords - 1 > CalleeStkArity)
2602  MoreStackForCalls = std::max(MoreStackForCalls,
2603  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2604  }
2605  }
2606  MaxStack += MoreStackForCalls;
2607  }
2608 
2609  // If the stack frame needed is larger than the guaranteed then runtime checks
2610  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2611  if (MaxStack > Guaranteed) {
2612  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2613  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2614 
2615  for (const auto &LI : PrologueMBB.liveins()) {
2616  stackCheckMBB->addLiveIn(LI);
2617  incStackMBB->addLiveIn(LI);
2618  }
2619 
2620  MF.push_front(incStackMBB);
2621  MF.push_front(stackCheckMBB);
2622 
2623  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2624  unsigned LEAop, CMPop, CALLop;
2625  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
2626  if (Is64Bit) {
2627  SPReg = X86::RSP;
2628  PReg = X86::RBP;
2629  LEAop = X86::LEA64r;
2630  CMPop = X86::CMP64rm;
2631  CALLop = X86::CALL64pcrel32;
2632  } else {
2633  SPReg = X86::ESP;
2634  PReg = X86::EBP;
2635  LEAop = X86::LEA32r;
2636  CMPop = X86::CMP32rm;
2637  CALLop = X86::CALLpcrel32;
2638  }
2639 
2640  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2641  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2642  "HiPE prologue scratch register is live-in");
2643 
2644  // Create new MBB for StackCheck:
2645  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2646  SPReg, false, -MaxStack);
2647  // SPLimitOffset is in a fixed heap location (pointed by BP).
2648  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2649  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2650  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2651 
2652  // Create new MBB for IncStack:
2653  BuildMI(incStackMBB, DL, TII.get(CALLop)).
2654  addExternalSymbol("inc_stack_0");
2655  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2656  SPReg, false, -MaxStack);
2657  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2658  .addReg(ScratchReg), PReg, false, SPLimitOffset);
2659  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2660 
2661  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
2662  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
2663  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
2664  incStackMBB->addSuccessor(incStackMBB, {1, 100});
2665  }
2666 #ifdef EXPENSIVE_CHECKS
2667  MF.verify();
2668 #endif
2669 }
2670 
2671 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2673  const DebugLoc &DL,
2674  int Offset) const {
2675 
2676  if (Offset <= 0)
2677  return false;
2678 
2679  if (Offset % SlotSize)
2680  return false;
2681 
2682  int NumPops = Offset / SlotSize;
2683  // This is only worth it if we have at most 2 pops.
2684  if (NumPops != 1 && NumPops != 2)
2685  return false;
2686 
2687  // Handle only the trivial case where the adjustment directly follows
2688  // a call. This is the most common one, anyway.
2689  if (MBBI == MBB.begin())
2690  return false;
2691  MachineBasicBlock::iterator Prev = std::prev(MBBI);
2692  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2693  return false;
2694 
2695  unsigned Regs[2];
2696  unsigned FoundRegs = 0;
2697 
2698  auto &MRI = MBB.getParent()->getRegInfo();
2699  auto RegMask = Prev->getOperand(1);
2700 
2701  auto &RegClass =
2702  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2703  // Try to find up to NumPops free registers.
2704  for (auto Candidate : RegClass) {
2705 
2706  // Poor man's liveness:
2707  // Since we're immediately after a call, any register that is clobbered
2708  // by the call and not defined by it can be considered dead.
2709  if (!RegMask.clobbersPhysReg(Candidate))
2710  continue;
2711 
2712  // Don't clobber reserved registers
2713  if (MRI.isReserved(Candidate))
2714  continue;
2715 
2716  bool IsDef = false;
2717  for (const MachineOperand &MO : Prev->implicit_operands()) {
2718  if (MO.isReg() && MO.isDef() &&
2719  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
2720  IsDef = true;
2721  break;
2722  }
2723  }
2724 
2725  if (IsDef)
2726  continue;
2727 
2728  Regs[FoundRegs++] = Candidate;
2729  if (FoundRegs == (unsigned)NumPops)
2730  break;
2731  }
2732 
2733  if (FoundRegs == 0)
2734  return false;
2735 
2736  // If we found only one free register, but need two, reuse the same one twice.
2737  while (FoundRegs < (unsigned)NumPops)
2738  Regs[FoundRegs++] = Regs[0];
2739 
2740  for (int i = 0; i < NumPops; ++i)
2741  BuildMI(MBB, MBBI, DL,
2742  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2743 
2744  return true;
2745 }
2746 
2750  bool reserveCallFrame = hasReservedCallFrame(MF);
2751  unsigned Opcode = I->getOpcode();
2752  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2753  DebugLoc DL = I->getDebugLoc();
2754  uint64_t Amount = !reserveCallFrame ? TII.getFrameSize(*I) : 0;
2755  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2756  I = MBB.erase(I);
2757  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
2758 
2759  if (!reserveCallFrame) {
2760  // If the stack pointer can be changed after prologue, turn the
2761  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2762  // adjcallstackdown instruction into 'add ESP, <amt>'
2763 
2764  // We need to keep the stack aligned properly. To do this, we round the
2765  // amount of space needed for the outgoing arguments up to the next
2766  // alignment boundary.
2767  unsigned StackAlign = getStackAlignment();
2768  Amount = alignTo(Amount, StackAlign);
2769 
2770  MachineModuleInfo &MMI = MF.getMMI();
2771  const Function &F = MF.getFunction();
2772  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2773  bool DwarfCFI = !WindowsCFI &&
2774  (MMI.hasDebugInfo() || F.needsUnwindTableEntry());
2775 
2776  // If we have any exception handlers in this function, and we adjust
2777  // the SP before calls, we may need to indicate this to the unwinder
2778  // using GNU_ARGS_SIZE. Note that this may be necessary even when
2779  // Amount == 0, because the preceding function may have set a non-0
2780  // GNU_ARGS_SIZE.
2781  // TODO: We don't need to reset this between subsequent functions,
2782  // if it didn't change.
2783  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
2784 
2785  if (HasDwarfEHHandlers && !isDestroy &&
2787  BuildCFI(MBB, InsertPos, DL,
2788  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2789 
2790  if (Amount == 0)
2791  return I;
2792 
2793  // Factor out the amount that gets handled inside the sequence
2794  // (Pushes of argument for frame setup, callee pops for frame destroy)
2795  Amount -= InternalAmt;
2796 
2797  // TODO: This is needed only if we require precise CFA.
2798  // If this is a callee-pop calling convention, emit a CFA adjust for
2799  // the amount the callee popped.
2800  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
2801  BuildCFI(MBB, InsertPos, DL,
2802  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2803 
2804  // Add Amount to SP to destroy a frame, or subtract to setup.
2805  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
2806 
2807  if (StackAdjustment) {
2808  // Merge with any previous or following adjustment instruction. Note: the
2809  // instructions merged with here do not have CFI, so their stack
2810  // adjustments do not feed into CfaAdjustment.
2811  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
2812  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
2813 
2814  if (StackAdjustment) {
2815  if (!(F.hasMinSize() &&
2816  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
2817  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
2818  /*InEpilogue=*/false);
2819  }
2820  }
2821 
2822  if (DwarfCFI && !hasFP(MF)) {
2823  // If we don't have FP, but need to generate unwind information,
2824  // we need to set the correct CFA offset after the stack adjustment.
2825  // How much we adjust the CFA offset depends on whether we're emitting
2826  // CFI only for EH purposes or for debugging. EH only requires the CFA
2827  // offset to be correct at each call site, while for debugging we want
2828  // it to be more precise.
2829 
2830  int64_t CfaAdjustment = -StackAdjustment;
2831  // TODO: When not using precise CFA, we also need to adjust for the
2832  // InternalAmt here.
2833  if (CfaAdjustment) {
2834  BuildCFI(MBB, InsertPos, DL,
2836  CfaAdjustment));
2837  }
2838  }
2839 
2840  return I;
2841  }
2842 
2843  if (isDestroy && InternalAmt) {
2844  // If we are performing frame pointer elimination and if the callee pops
2845  // something off the stack pointer, add it back. We do this until we have
2846  // more advanced stack pointer tracking ability.
2847  // We are not tracking the stack pointer adjustment by the callee, so make
2848  // sure we restore the stack pointer immediately after the call, there may
2849  // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2852  while (CI != B && !std::prev(CI)->isCall())
2853  --CI;
2854  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
2855  }
2856 
2857  return I;
2858 }
2859 
2861  assert(MBB.getParent() && "Block is not attached to a function!");
2862  const MachineFunction &MF = *MBB.getParent();
2863  return !TRI->needsStackRealignment(MF) || !MBB.isLiveIn(X86::EFLAGS);
2864 }
2865 
2867  assert(MBB.getParent() && "Block is not attached to a function!");
2868 
2869  // Win64 has strict requirements in terms of epilogue and we are
2870  // not taking a chance at messing with them.
2871  // I.e., unless this block is already an exit block, we can't use
2872  // it as an epilogue.
2873  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
2874  return false;
2875 
2876  if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2877  return true;
2878 
2879  // If we cannot use LEA to adjust SP, we may need to use ADD, which
2880  // clobbers the EFLAGS. Check that we do not need to preserve it,
2881  // otherwise, conservatively assume this is not
2882  // safe to insert the epilogue here.
2884 }
2885 
2887  // If we may need to emit frameless compact unwind information, give
2888  // up as this is currently broken: PR25614.
2889  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF)) &&
2890  // The lowering of segmented stack and HiPE only support entry blocks
2891  // as prologue blocks: PR26107.
2892  // This limitation may be lifted if we fix:
2893  // - adjustForSegmentedStacks
2894  // - adjustForHiPEPrologue
2896  !MF.shouldSplitStack();
2897 }
2898 
2901  const DebugLoc &DL, bool RestoreSP) const {
2902  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2903  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2905  "restoring EBP/ESI on non-32-bit target");
2906 
2907  MachineFunction &MF = *MBB.getParent();
2908  Register FramePtr = TRI->getFrameRegister(MF);
2909  Register BasePtr = TRI->getBaseRegister();
2910  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
2911  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2912  MachineFrameInfo &MFI = MF.getFrameInfo();
2913 
2914  // FIXME: Don't set FrameSetup flag in catchret case.
2915 
2916  int FI = FuncInfo.EHRegNodeFrameIndex;
2917  int EHRegSize = MFI.getObjectSize(FI);
2918 
2919  if (RestoreSP) {
2920  // MOV32rm -EHRegSize(%ebp), %esp
2921  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2922  X86::EBP, true, -EHRegSize)
2924  }
2925 
2926  unsigned UsedReg;
2927  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2928  int EndOffset = -EHRegOffset - EHRegSize;
2929  FuncInfo.EHRegNodeEndOffset = EndOffset;
2930 
2931  if (UsedReg == FramePtr) {
2932  // ADD $offset, %ebp
2933  unsigned ADDri = getADDriOpcode(false, EndOffset);
2934  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2935  .addReg(FramePtr)
2936  .addImm(EndOffset)
2938  ->getOperand(3)
2939  .setIsDead();
2940  assert(EndOffset >= 0 &&
2941  "end of registration object above normal EBP position!");
2942  } else if (UsedReg == BasePtr) {
2943  // LEA offset(%ebp), %esi
2944  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2945  FramePtr, false, EndOffset)
2947  // MOV32rm SavedEBPOffset(%esi), %ebp
2948  assert(X86FI->getHasSEHFramePtrSave());
2949  int Offset =
2950  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2951  assert(UsedReg == BasePtr);
2952  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2953  UsedReg, true, Offset)
2955  } else {
2956  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2957  }
2958  return MBBI;
2959 }
2960 
2962  return TRI->getSlotSize();
2963 }
2964 
2966  const {
2967  return TRI->getDwarfRegNum(StackPtr, true);
2968 }
2969 
2970 namespace {
2971 // Struct used by orderFrameObjects to help sort the stack objects.
2972 struct X86FrameSortingObject {
2973  bool IsValid = false; // true if we care about this Object.
2974  unsigned ObjectIndex = 0; // Index of Object into MFI list.
2975  unsigned ObjectSize = 0; // Size of Object in bytes.
2976  unsigned ObjectAlignment = 1; // Alignment of Object in bytes.
2977  unsigned ObjectNumUses = 0; // Object static number of uses.
2978 };
2979 
2980 // The comparison function we use for std::sort to order our local
2981 // stack symbols. The current algorithm is to use an estimated
2982 // "density". This takes into consideration the size and number of
2983 // uses each object has in order to roughly minimize code size.
2984 // So, for example, an object of size 16B that is referenced 5 times
2985 // will get higher priority than 4 4B objects referenced 1 time each.
2986 // It's not perfect and we may be able to squeeze a few more bytes out of
2987 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
2988 // fringe end can have special consideration, given their size is less
2989 // important, etc.), but the algorithmic complexity grows too much to be
2990 // worth the extra gains we get. This gets us pretty close.
2991 // The final order leaves us with objects with highest priority going
2992 // at the end of our list.
2993 struct X86FrameSortingComparator {
2994  inline bool operator()(const X86FrameSortingObject &A,
2995  const X86FrameSortingObject &B) {
2996  uint64_t DensityAScaled, DensityBScaled;
2997 
2998  // For consistency in our comparison, all invalid objects are placed
2999  // at the end. This also allows us to stop walking when we hit the
3000  // first invalid item after it's all sorted.
3001  if (!A.IsValid)
3002  return false;
3003  if (!B.IsValid)
3004  return true;
3005 
3006  // The density is calculated by doing :
3007  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3008  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3009  // Since this approach may cause inconsistencies in
3010  // the floating point <, >, == comparisons, depending on the floating
3011  // point model with which the compiler was built, we're going
3012  // to scale both sides by multiplying with
3013  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3014  // the division and, with it, the need for any floating point
3015  // arithmetic.
3016  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3017  static_cast<uint64_t>(B.ObjectSize);
3018  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3019  static_cast<uint64_t>(A.ObjectSize);
3020 
3021  // If the two densities are equal, prioritize highest alignment
3022  // objects. This allows for similar alignment objects
3023  // to be packed together (given the same density).
3024  // There's room for improvement here, also, since we can pack
3025  // similar alignment (different density) objects next to each
3026  // other to save padding. This will also require further
3027  // complexity/iterations, and the overall gain isn't worth it,
3028  // in general. Something to keep in mind, though.
3029  if (DensityAScaled == DensityBScaled)
3030  return A.ObjectAlignment < B.ObjectAlignment;
3031 
3032  return DensityAScaled < DensityBScaled;
3033  }
3034 };
3035 } // namespace
3036 
3037 // Order the symbols in the local stack.
3038 // We want to place the local stack objects in some sort of sensible order.
3039 // The heuristic we use is to try and pack them according to static number
3040 // of uses and size of object in order to minimize code size.
3042  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3043  const MachineFrameInfo &MFI = MF.getFrameInfo();
3044 
3045  // Don't waste time if there's nothing to do.
3046  if (ObjectsToAllocate.empty())
3047  return;
3048 
3049  // Create an array of all MFI objects. We won't need all of these
3050  // objects, but we're going to create a full array of them to make
3051  // it easier to index into when we're counting "uses" down below.
3052  // We want to be able to easily/cheaply access an object by simply
3053  // indexing into it, instead of having to search for it every time.
3054  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3055 
3056  // Walk the objects we care about and mark them as such in our working
3057  // struct.
3058  for (auto &Obj : ObjectsToAllocate) {
3059  SortingObjects[Obj].IsValid = true;
3060  SortingObjects[Obj].ObjectIndex = Obj;
3061  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlignment(Obj);
3062  // Set the size.
3063  int ObjectSize = MFI.getObjectSize(Obj);
3064  if (ObjectSize == 0)
3065  // Variable size. Just use 4.
3066  SortingObjects[Obj].ObjectSize = 4;
3067  else
3068  SortingObjects[Obj].ObjectSize = ObjectSize;
3069  }
3070 
3071  // Count the number of uses for each object.
3072  for (auto &MBB : MF) {
3073  for (auto &MI : MBB) {
3074  if (MI.isDebugInstr())
3075  continue;
3076  for (const MachineOperand &MO : MI.operands()) {
3077  // Check to see if it's a local stack symbol.
3078  if (!MO.isFI())
3079  continue;
3080  int Index = MO.getIndex();
3081  // Check to see if it falls within our range, and is tagged
3082  // to require ordering.
3083  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3084  SortingObjects[Index].IsValid)
3085  SortingObjects[Index].ObjectNumUses++;
3086  }
3087  }
3088  }
3089 
3090  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3091  // info).
3092  llvm::stable_sort(SortingObjects, X86FrameSortingComparator());
3093 
3094  // Now modify the original list to represent the final order that
3095  // we want. The order will depend on whether we're going to access them
3096  // from the stack pointer or the frame pointer. For SP, the list should
3097  // end up with the END containing objects that we want with smaller offsets.
3098  // For FP, it should be flipped.
3099  int i = 0;
3100  for (auto &Obj : SortingObjects) {
3101  // All invalid items are sorted at the end, so it's safe to stop.
3102  if (!Obj.IsValid)
3103  break;
3104  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3105  }
3106 
3107  // Flip it if we're accessing off of the FP.
3108  if (!TRI->needsStackRealignment(MF) && hasFP(MF))
3109  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3110 }
3111 
3112 
3114  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3115  unsigned Offset = 16;
3116  // RBP is immediately pushed.
3117  Offset += SlotSize;
3118  // All callee-saved registers are then pushed.
3119  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3120  // Every funclet allocates enough stack space for the largest outgoing call.
3121  Offset += getWinEHFuncletFrameSize(MF);
3122  return Offset;
3123 }
3124 
3126  MachineFunction &MF, RegScavenger *RS) const {
3127  // Mark the function as not having WinCFI. We will set it back to true in
3128  // emitPrologue if it gets called and emits CFI.
3129  MF.setHasWinCFI(false);
3130 
3131  // If this function isn't doing Win64-style C++ EH, we don't need to do
3132  // anything.
3133  const Function &F = MF.getFunction();
3134  if (!STI.is64Bit() || !MF.hasEHFunclets() ||
3136  return;
3137 
3138  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3139  // relative to RSP after the prologue. Find the offset of the last fixed
3140  // object, so that we can allocate a slot immediately following it. If there
3141  // were no fixed objects, use offset -SlotSize, which is immediately after the
3142  // return address. Fixed objects have negative frame indices.
3143  MachineFrameInfo &MFI = MF.getFrameInfo();
3144  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3145  int64_t MinFixedObjOffset = -SlotSize;
3146  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3147  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3148 
3149  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3150  for (WinEHHandlerType &H : TBME.HandlerArray) {
3151  int FrameIndex = H.CatchObj.FrameIndex;
3152  if (FrameIndex != INT_MAX) {
3153  // Ensure alignment.
3154  unsigned Align = MFI.getObjectAlignment(FrameIndex);
3155  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3156  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3157  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3158  }
3159  }
3160  }
3161 
3162  // Ensure alignment.
3163  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3164  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3165  int UnwindHelpFI =
3166  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*IsImmutable=*/false);
3167  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3168 
3169  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3170  // other frame setup instructions.
3171  MachineBasicBlock &MBB = MF.front();
3172  auto MBBI = MBB.begin();
3173  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3174  ++MBBI;
3175 
3176  DebugLoc DL = MBB.findDebugLoc(MBBI);
3177  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3178  UnwindHelpFI)
3179  .addImm(-2);
3180 }
void push_front(MachineBasicBlock *MBB)
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:348
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:542
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:590
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:397
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
MachineBasicBlock * getMBB() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1080
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSWindows() const
Definition: X86Subtarget.h:792
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:501
bool hasStackObjects() const
Return true if there are any stack objects in this function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
static unsigned getLEArOpcode(unsigned IsLP64)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:507
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned Reg
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
void setCalleeSavedFrameSize(unsigned bytes)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
arg_iterator arg_end()
Definition: Function.h:704
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
MachineModuleInfo & getMMI() const
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1068
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
static BranchProbability getOne()
bool isTargetNaCl64() const
Definition: X86Subtarget.h:766
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:494
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
unsigned getSlotSize() const
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:501
Register getFramePtr() const
Returns physical register used as frame pointer.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:770
X86FrameLowering(const X86Subtarget &STI, unsigned StackAlignOverride)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:721
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
A tuple of MDNodes.
Definition: Metadata.h:1325
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:561
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool is32Bit() const
Definition: X86Subtarget.h:546
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
iterator_range< iterator > terminators()
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime...
unsigned getNumOperands() const
Definition: Metadata.cpp:1076
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
static const uint64_t kSplitStackAvailable
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:261
unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const override
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
Definition: ARMWinEH.h:196
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool needsFrameIndexResolution(const MachineFunction &MF) const override
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
const MCContext & getContext() const
int getObjectIndexBegin() const
Return the minimum frame object index.
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:250
static unsigned getHiPELiteral(NamedMDNode *HiPELiteralsMD, const StringRef LiteralName)
Lookup an ERTS parameter in the !hipe.literals named metadata node.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:732
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
Value wrapper in the Metadata hierarchy.
Definition: Metadata.h:338
static unsigned calculateSetFPREG(uint64_t SPAdjust)
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:173
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void ensureMaxAlignment(llvm::Align Align)
Make sure the function is at least Align bytes aligned.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
unsigned getKillRegState(bool B)
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:468
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned getInitialCFARegister(const MachineFunction &MF) const override
Return initial CFA register value i.e.
StringRef getString() const
Definition: Metadata.cpp:463
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
unsigned getDefRegState(bool B)
The memory access is volatile.
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:497
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:480
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:487
unsigned getStackProbeSize(MachineFunction &MF) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:358
X86_FastCall - &#39;fast&#39; analog of X86_StdCall.
Definition: CallingConv.h:91
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasEHFunclets() const
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const GlobalValue * getGlobal() const
const X86InstrInfo & TII
#define H(x, y, z)
Definition: MD5.cpp:57
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:573
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:302
MCRegAliasIterator enumerates all registers aliasing Reg.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
bool useLeaForSP() const
Definition: X86Subtarget.h:646
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:751
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const Triple & getTargetTriple() const
size_t arg_size() const
Definition: Function.h:728
arg_iterator arg_begin()
Definition: Function.h:695
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
bool isTargetDarwin() const
Definition: X86Subtarget.h:750
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
bool useRetpolineIndirectCalls() const
Definition: X86Subtarget.h:699
bool isTargetWin64() const
Definition: X86Subtarget.h:794
This class contains a discriminated union of information about pointers in memory operands...
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm)
static bool isFuncletReturnInstr(MachineInstr &MI)
static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const
Emit target stack probe code.
The memory access writes data.
Register getFrameRegister(const MachineFunction &MF) const override
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
const X86Subtarget & STI
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
int CreateSpillStackObject(uint64_t Size, llvm::Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value...
MachineOperand class - Representation of each machine instruction operand.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
Information about stack frame layout on the target.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool isTargetWin32() const
Definition: X86Subtarget.h:796
int getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling...
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:152
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
bool callsUnwindInit() const
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
IterT skipDebugInstructionsBackward(IterT It, IterT Begin)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:555
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:594
bool callsEHReturn() const
static bool isTailCallOpcode(unsigned Opc)
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
CodeModel::Model getCodeModel() const
Returns the code model.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
union llvm::WinEHHandlerType::@202 CatchObj
The CatchObj starts out life as an LLVM alloca and is eventually turned frame index.
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:717
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:126
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static const size_t npos
Definition: StringRef.h:50
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTargetDragonFly() const
Definition: X86Subtarget.h:752
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
TargetOptions Options
LLVM_NODISCARD size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
Definition: StringRef.h:380
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1223
Pair of physical register and lane mask.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:619
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
void setCVBytesOfCalleeSavedRegisters(unsigned S)
uint32_t Size
Definition: Profile.cpp:46
static unsigned getSUBrrOpcode(unsigned isLP64)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const X86RegisterInfo * TRI
const Module * getModule() const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
iterator_range< livein_iterator > liveins() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
CallingConvention
Definition: Dwarf.h:191
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isEAXLiveIn(MachineBasicBlock &MBB)
static unsigned getADDrrOpcode(unsigned isLP64)
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
void stable_sort(R &&Range)
Definition: STLExtras.h:1289
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:320
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1384
bool isTargetLinux() const
Definition: X86Subtarget.h:760
static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const X86RegisterInfo *TRI, bool Is64Bit)
findDeadCallerSavedReg - Return a caller-saved register that isn&#39;t live when it reaches the "return" ...
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:807
int getInitialCFAOffset(const MachineFunction &MF) const override
Return initial CFA offset value i.e.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasBWI() const
Definition: X86Subtarget.h:680
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
A single uniqued string.
Definition: Metadata.h:603
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL) const
static BranchProbability getZero()
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
DWARF-like instruction based exceptions.
Register getReg() const
getReg - Returns the register number.
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1074
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
static bool HasNestArgument(const MachineFunction *MF)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
bool hasTailCall() const
Returns true if the function contains a tail call.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
Function Alias Analysis false
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getStackRegister() const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class contains meta information specific to a module.
Register getBaseRegister() const
bool hasCalls() const
Return true if the current function has any function calls.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:774