LLVM  9.0.0svn
X86RegisterInfo.h
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1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
14 #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
15 
17 
18 #define GET_REGINFO_HEADER
19 #include "X86GenRegisterInfo.inc"
20 
21 namespace llvm {
22  class Triple;
23 
24 class X86RegisterInfo final : public X86GenRegisterInfo {
25 private:
26  /// Is64Bit - Is the target 64-bits.
27  ///
28  bool Is64Bit;
29 
30  /// IsWin64 - Is the target on of win64 flavours
31  ///
32  bool IsWin64;
33 
34  /// SlotSize - Stack slot size in bytes.
35  ///
36  unsigned SlotSize;
37 
38  /// StackPtr - X86 physical register used as stack ptr.
39  ///
40  unsigned StackPtr;
41 
42  /// FramePtr - X86 physical register used as frame ptr.
43  ///
44  unsigned FramePtr;
45 
46  /// BasePtr - X86 physical register used as a base ptr in complex stack
47  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
48  /// variable size stack objects.
49  unsigned BasePtr;
50 
51 public:
52  X86RegisterInfo(const Triple &TT);
53 
54  // FIXME: This should be tablegen'd like getDwarfRegNum is
55  int getSEHRegNum(unsigned i) const;
56 
57  /// Code Generation virtual methods...
58  ///
59  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
60 
61  /// getMatchingSuperRegClass - Return a subclass of the specified register
62  /// class A so that each register in it has a sub-register of the
63  /// specified sub-register index which is in the specified register class B.
64  const TargetRegisterClass *
66  const TargetRegisterClass *B,
67  unsigned Idx) const override;
68 
69  const TargetRegisterClass *
71  unsigned Idx) const override;
72 
73  const TargetRegisterClass *
75  const MachineFunction &MF) const override;
76 
77  /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
78  /// values.
79  const TargetRegisterClass *
81  unsigned Kind = 0) const override;
82 
83  /// getCrossCopyRegClass - Returns a legal register class to copy a register
84  /// in the specified class to or from. Returns NULL if it is possible to copy
85  /// between a two registers of the specified class.
86  const TargetRegisterClass *
87  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
88 
89  /// getGPRsForTailCall - Returns a register class with registers that can be
90  /// used in forming tail calls.
91  const TargetRegisterClass *
92  getGPRsForTailCall(const MachineFunction &MF) const;
93 
94  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
95  MachineFunction &MF) const override;
96 
97  /// getCalleeSavedRegs - Return a null-terminated list of all of the
98  /// callee-save registers on this target.
99  const MCPhysReg *
100  getCalleeSavedRegs(const MachineFunction* MF) const override;
101  const MCPhysReg *
104  CallingConv::ID) const override;
105  const uint32_t *getNoPreservedMask() const override;
106 
107  // Calls involved in thread-local variable lookup save more registers than
108  // normal calls, so they need a different mask to represent this.
110 
111  /// getReservedRegs - Returns a bitset indexed by physical register number
112  /// indicating if a register is a special register that has particular uses and
113  /// should be considered unavailable at all times, e.g. SP, RA. This is used by
114  /// register scavenger to determine what registers are free.
115  BitVector getReservedRegs(const MachineFunction &MF) const override;
116 
117  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
118 
119  bool hasBasePointer(const MachineFunction &MF) const;
120 
121  bool canRealignStack(const MachineFunction &MF) const override;
122 
123  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
124  int &FrameIdx) const override;
125 
127  int SPAdj, unsigned FIOperandNum,
128  RegScavenger *RS = nullptr) const override;
129 
130  // Debug information queries.
131  unsigned getFrameRegister(const MachineFunction &MF) const override;
132  unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
133  unsigned getPtrSizedStackRegister(const MachineFunction &MF) const;
134  unsigned getStackRegister() const { return StackPtr; }
135  unsigned getBaseRegister() const { return BasePtr; }
136  /// Returns physical register used as frame pointer.
137  /// This will always returns the frame pointer register, contrary to
138  /// getFrameRegister() which returns the "base pointer" in situations
139  /// involving a stack, frame and base pointer.
140  unsigned getFramePtr() const { return FramePtr; }
141  // FIXME: Move to FrameInfok
142  unsigned getSlotSize() const { return SlotSize; }
143 };
144 
145 } // End llvm namespace
146 
147 #endif
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
unsigned Reg
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
unsigned getSlotSize() const
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned getBaseRegister() const
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
unsigned getStackRegister() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getNoPreservedMask() const override
unsigned getFramePtr() const
Returns physical register used as frame pointer.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
int getSEHRegNum(unsigned i) const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
const uint32_t * getDarwinTLSCallPreservedMask() const
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool canRealignStack(const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
unsigned getFrameRegister(const MachineFunction &MF) const override