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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
21 
22 namespace llvm {
23  class X86Subtarget;
24  class X86TargetMachine;
25 
26  namespace X86ISD {
27  // X86 Specific DAG Nodes
28  enum NodeType : unsigned {
29  // Start the numbering where the builtin ops leave off.
31 
32  /// Bit scan forward.
33  BSF,
34  /// Bit scan reverse.
35  BSR,
36 
37  /// Double shift instructions. These correspond to
38  /// X86::SHLDxx and X86::SHRDxx instructions.
41 
42  /// Bitwise logical AND of floating point values. This corresponds
43  /// to X86::ANDPS or X86::ANDPD.
45 
46  /// Bitwise logical OR of floating point values. This corresponds
47  /// to X86::ORPS or X86::ORPD.
48  FOR,
49 
50  /// Bitwise logical XOR of floating point values. This corresponds
51  /// to X86::XORPS or X86::XORPD.
53 
54  /// Bitwise logical ANDNOT of floating point values. This
55  /// corresponds to X86::ANDNPS or X86::ANDNPD.
57 
58  /// These operations represent an abstract X86 call
59  /// instruction, which includes a bunch of information. In particular the
60  /// operands of these node are:
61  ///
62  /// #0 - The incoming token chain
63  /// #1 - The callee
64  /// #2 - The number of arg bytes the caller pushes on the stack.
65  /// #3 - The number of arg bytes the callee pops off the stack.
66  /// #4 - The value to pass in AL/AX/EAX (optional)
67  /// #5 - The value to pass in DL/DX/EDX (optional)
68  ///
69  /// The result values of these nodes are:
70  ///
71  /// #0 - The outgoing token chain
72  /// #1 - The first register result value (optional)
73  /// #2 - The second register result value (optional)
74  ///
76 
77  /// Same as call except it adds the NoTrack prefix.
79 
80  /// X86 compare and logical compare instructions.
82 
83  /// X86 bit-test instructions.
84  BT,
85 
86  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
87  /// operand, usually produced by a CMP instruction.
89 
90  /// X86 Select
92 
93  // Same as SETCC except it's materialized with a sbb and the value is all
94  // one's or all zero's.
95  SETCC_CARRY, // R = carry_bit ? ~0 : 0
96 
97  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98  /// Operands are two FP values to compare; result is a mask of
99  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
101 
102  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
103  /// and a version with SAE.
105 
106  /// X86 conditional moves. Operand 0 and operand 1 are the two values
107  /// to select from. Operand 2 is the condition code, and operand 3 is the
108  /// flag operand produced by a CMP or TEST instruction. It also writes a
109  /// flag result.
111 
112  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113  /// is the block to branch if condition is true, operand 2 is the
114  /// condition code, and operand 3 is the flag operand produced by a CMP
115  /// or TEST instruction.
117 
118  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
119  /// operand 1 is the target address.
121 
122  /// Return with a flag operand. Operand 0 is the chain operand, operand
123  /// 1 is the number of bytes of stack to pop.
125 
126  /// Return from interrupt. Operand 0 is the number of bytes to pop.
128 
129  /// Repeat fill, corresponds to X86::REP_STOSx.
131 
132  /// Repeat move, corresponds to X86::REP_MOVSx.
134 
135  /// On Darwin, this node represents the result of the popl
136  /// at function entry, used for PIC code.
138 
139  /// A wrapper node for TargetConstantPool, TargetJumpTable,
140  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
141  /// MCSymbol and TargetBlockAddress.
143 
144  /// Special wrapper used under X86-64 PIC mode for RIP
145  /// relative displacements.
147 
148  /// Copies a 64-bit value from the low word of an XMM vector
149  /// to an MMX vector.
151 
152  /// Copies a 32-bit value from the low word of a MMX
153  /// vector to a GPR.
155 
156  /// Copies a GPR into the low 32-bit word of a MMX vector
157  /// and zero out the high word.
159 
160  /// Extract an 8-bit value from a vector and zero extend it to
161  /// i32, corresponds to X86::PEXTRB.
163 
164  /// Extract a 16-bit value from a vector and zero extend it to
165  /// i32, corresponds to X86::PEXTRW.
167 
168  /// Insert any element of a 4 x float vector into any element
169  /// of a destination 4 x floatvector.
171 
172  /// Insert the lower 8-bits of a 32-bit value to a vector,
173  /// corresponds to X86::PINSRB.
175 
176  /// Insert the lower 16-bits of a 32-bit value to a vector,
177  /// corresponds to X86::PINSRW.
179 
180  /// Shuffle 16 8-bit values within a vector.
182 
183  /// Compute Sum of Absolute Differences.
185  /// Compute Double Block Packed Sum-Absolute-Differences
187 
188  /// Bitwise Logical AND NOT of Packed FP values.
190 
191  /// Blend where the selector is an immediate.
193 
194  /// Dynamic (non-constant condition) vector blend where only the sign bits
195  /// of the condition elements are used. This is used to enforce that the
196  /// condition mask is not valid for generic VSELECT optimizations. This
197  /// is also used to implement the intrinsics.
198  /// Operands are in VSELECT order: MASK, TRUE, FALSE
200 
201  /// Combined add and sub on an FP vector.
203 
204  // FP vector ops with rounding mode.
212 
213  // FP vector get exponent.
215  // Extract Normalized Mantissas.
217  // FP Scale.
220 
221  // Unsigned Integer average.
223 
224  /// Integer horizontal add/sub.
227 
228  /// Floating point horizontal add/sub.
231 
232  // Detect Conflicts Within a Vector
234 
235  /// Floating point max and min.
237 
238  /// Commutative FMIN and FMAX.
240 
241  /// Scalar intrinsic floating point max and min.
243 
244  /// Floating point reciprocal-sqrt and reciprocal approximation.
245  /// Note that these typically require refinement
246  /// in order to obtain suitable precision.
248 
249  // AVX-512 reciprocal approximations with a little more precision.
251 
252  // Thread Local Storage.
254 
255  // Thread Local Storage. A call to get the start address
256  // of the TLS block for the current module.
258 
259  // Thread Local Storage. When calling to an OS provided
260  // thunk at the address from an earlier relocation.
262 
263  // Exception Handling helpers.
265 
266  // SjLj exception handling setjmp.
268 
269  // SjLj exception handling longjmp.
271 
272  // SjLj exception handling dispatch.
274 
275  /// Tail call return. See X86TargetLowering::LowerCall for
276  /// the list of operands.
278 
279  // Vector move to low scalar and zero higher vector elements.
281 
282  // Vector integer truncate.
284  // Vector integer truncate with unsigned/signed saturation.
286 
287  // Masked version of the above. Used when less than a 128-bit result is
288  // produced since the mask only applies to the lower elements and can't
289  // be represented by a select.
290  // SRC, PASSTHRU, MASK
292 
293  // Vector FP extend.
295 
296  // Vector FP round.
298 
299  // Masked version of above. Used for v2f64->v4f32.
300  // SRC, PASSTHRU, MASK
302 
303  // 128-bit vector logical left / right shift
305 
306  // Vector shift elements
308 
309  // Vector variable shift
311 
312  // Vector shift elements by immediate
314 
315  // Shifts of mask registers.
317 
318  // Bit rotate by immediate
320 
321  // Vector packed double/float comparison.
323 
324  // Vector integer comparisons.
326 
327  // v8i16 Horizontal minimum and position.
329 
331 
332  /// Vector comparison generating mask bits for fp and
333  /// integer signed and unsigned data types.
335  // Vector comparison with SAE for FP values
337 
338  // Arithmetic operations with FLAGS results.
340  OR, XOR, AND,
341 
342  // Bit field extract.
344 
345  // Zero High Bits Starting with Specified Bit Position.
347 
348  // X86-specific multiply by immediate.
350 
351  // Vector sign bit extraction.
353 
354  // Vector bitwise comparisons.
356 
357  // Vector packed fp sign bitwise comparisons.
359 
360  // OR/AND test for masks.
363 
364  // ADD for masks.
366 
367  // Several flavors of instructions with vector shuffle behaviors.
368  // Saturated signed/unnsigned packing.
371  // Intra-lane alignr.
373  // AVX512 inter-lane alignr.
379  // VBMI2 Concat & Shift.
384  //Shuffle Packed Values at 128-bit granularity.
399 
400  // Variable Permute (VPERM).
401  // Res = VPERMV MaskV, V0
403 
404  // 3-op Variable Permute (VPERMT2).
405  // Res = VPERMV3 V0, MaskV, V1
407 
408  // Bitwise ternary logic.
410  // Fix Up Special Packed Float32/64 values.
413  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
415  // Reduce - Perform Reduction Transformation on scalar\packed FP.
417  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
418  // Also used by the legacy (V)ROUND intrinsics where we mask out the
419  // scaling part of the immediate.
421  // Tests Types Of a FP Values for packed types.
423  // Tests Types Of a FP Values for scalar types.
425 
426  // Broadcast scalar to vector.
428  // Broadcast mask to vector.
430  // Broadcast subvector to vector.
432 
433  /// SSE4A Extraction and Insertion.
435 
436  // XOP arithmetic/logical shifts.
438  // XOP signed/unsigned integer comparisons.
440  // XOP packed permute bytes.
442  // XOP two source permutation.
444 
445  // Vector multiply packed unsigned doubleword integers.
447  // Vector multiply packed signed doubleword integers.
449  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
451 
452  // Multiply and Add Packed Integers.
454 
455  // AVX512IFMA multiply and add.
456  // NOTE: These are different than the instruction and perform
457  // op0 x op1 + op2.
459 
460  // VNNI
465 
466  // FMA nodes.
467  // We use the target independent ISD::FMA for the non-inverted case.
473 
474  // FMA with rounding mode.
481 
482  // Compress and expand.
485 
486  // Bits shuffle
488 
489  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
493 
494  // Vector float/double to signed/unsigned integer.
496  // Scalar float/double to signed/unsigned integer.
498 
499  // Vector float/double to signed/unsigned integer with truncation.
501  // Scalar float/double to signed/unsigned integer with truncation.
503 
504  // Vector signed/unsigned integer to float/double.
506 
507  // Masked versions of above. Used for v2f64->v4f32.
508  // SRC, PASSTHRU, MASK
511 
512  // Save xmm argument registers to the stack, according to %al. An operator
513  // is needed so that this can be expanded with control flow.
515 
516  // Windows's _chkstk call to do stack probing.
518 
519  // For allocating variable amounts of stack space when using
520  // segmented stacks. Check if the current stacklet has enough space, and
521  // falls back to heap allocation if not.
523 
524  // Memory barriers.
527 
528  // Store FP status word into i16 register.
530 
531  // Store contents of %ah into %eflags.
533 
534  // Get a random integer and indicate whether it is valid in CF.
536 
537  // Get a NIST SP800-90B & C compliant random integer and
538  // indicate whether it is valid in CF.
540 
541  // Protection keys
542  // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
543  // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
544  // value for ECX.
546 
547  // SSE42 string comparisons.
548  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
549  // will emit one or two instructions based on which results are used. If
550  // flags and index/mask this allows us to use a single instruction since
551  // we won't have to pick and opcode for flags. Instead we can rely on the
552  // DAG to CSE everything and decide at isel.
555 
556  // Test if in transactional execution.
558 
559  // ERI instructions.
562 
563  // Conversions between float and half-float.
565 
566  // Masked version of above.
567  // SRC, RND, PASSTHRU, MASK
569 
570  // Galois Field Arithmetic Instructions
572 
573  // LWP insert record.
575 
576  // User level wait
578 
579  // Compare and swap.
585 
586  /// LOCK-prefixed arithmetic read-modify-write instructions.
587  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
589 
590  // Load, scalar_to_vector, and zero extend.
592 
593  // Store FP control world into i16 memory.
595 
596  /// This instruction implements FP_TO_SINT with the
597  /// integer destination in memory and a FP reg source. This corresponds
598  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
599  /// has two inputs (token chain and address) and two outputs (int value
600  /// and token chain). Memory VT specifies the type to store to.
602 
603  /// This instruction implements SINT_TO_FP with the
604  /// integer source in memory and FP reg result. This corresponds to the
605  /// X86::FILD*m instructions. It has two inputs (token chain and address)
606  /// and two outputs (FP value and token chain). FILD_FLAG also produces a
607  /// flag). The integer source type is specified by the memory VT.
610 
611  /// This instruction implements a fp->int store from FP stack
612  /// slots. This corresponds to the fist instruction. It takes a
613  /// chain operand, value to store, address, and glue. The memory VT
614  /// specifies the type to store as.
616 
617  /// This instruction implements an extending load to FP stack slots.
618  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
619  /// operand, and ptr to load from. The memory VT specifies the type to
620  /// load from.
622 
623  /// This instruction implements a truncating store from FP stack
624  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
625  /// chain operand, value to store, address, and glue. The memory VT
626  /// specifies the type to store as.
628 
629  /// This instruction grabs the address of the next argument
630  /// from a va_list. (reads and modifies the va_list in memory)
632 
633  // Vector truncating store with unsigned/signed saturation
635  // Vector truncating masked store with unsigned/signed saturation
637 
638  // X86 specific gather and scatter
640 
641  // WARNING: Do not add anything in the end unless you want the node to
642  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
643  // opcodes will be thought as target memory ops!
644  };
645  } // end namespace X86ISD
646 
647  /// Define some predicates that are used for node matching.
648  namespace X86 {
649  /// Returns true if Elt is a constant zero or floating point constant +0.0.
650  bool isZeroNode(SDValue Elt);
651 
652  /// Returns true of the given offset can be
653  /// fit into displacement field of the instruction.
655  bool hasSymbolicDisplacement = true);
656 
657  /// Determines whether the callee is required to pop its
658  /// own arguments. Callee pop is necessary to support tail calls.
660  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
661 
662  } // end namespace X86
663 
664  //===--------------------------------------------------------------------===//
665  // X86 Implementation of the TargetLowering interface
666  class X86TargetLowering final : public TargetLowering {
667  public:
668  explicit X86TargetLowering(const X86TargetMachine &TM,
669  const X86Subtarget &STI);
670 
671  unsigned getJumpTableEncoding() const override;
672  bool useSoftFloat() const override;
673 
674  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
675  ArgListTy &Args) const override;
676 
677  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
678  return MVT::i8;
679  }
680 
681  const MCExpr *
682  LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
683  const MachineBasicBlock *MBB, unsigned uid,
684  MCContext &Ctx) const override;
685 
686  /// Returns relocation base for the given PIC jumptable.
687  SDValue getPICJumpTableRelocBase(SDValue Table,
688  SelectionDAG &DAG) const override;
689  const MCExpr *
690  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
691  unsigned JTI, MCContext &Ctx) const override;
692 
693  /// Return the desired alignment for ByVal aggregate
694  /// function arguments in the caller parameter area. For X86, aggregates
695  /// that contains are placed at 16-byte boundaries while the rest are at
696  /// 4-byte boundaries.
697  unsigned getByValTypeAlignment(Type *Ty,
698  const DataLayout &DL) const override;
699 
700  /// Returns the target specific optimal type for load
701  /// and store operations as a result of memset, memcpy, and memmove
702  /// lowering. If DstAlign is zero that means it's safe to destination
703  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
704  /// means there isn't a need to check it against alignment requirement,
705  /// probably because the source does not need to be loaded. If 'IsMemset' is
706  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
707  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
708  /// source is constant so it does not need to be loaded.
709  /// It returns EVT::Other if the type should be determined using generic
710  /// target-independent logic.
711  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
712  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
713  MachineFunction &MF) const override;
714 
715  /// Returns true if it's safe to use load / store of the
716  /// specified type to expand memcpy / memset inline. This is mostly true
717  /// for all types except for some special cases. For example, on X86
718  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
719  /// also does type conversion. Note the specified type doesn't have to be
720  /// legal as the hook is used before type legalization.
721  bool isSafeMemOpType(MVT VT) const override;
722 
723  /// Returns true if the target allows unaligned memory accesses of the
724  /// specified type. Returns whether it is "fast" in the last argument.
725  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
726  bool *Fast) const override;
727 
728  /// Provide custom lowering hooks for some operations.
729  ///
730  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
731 
732  /// Places new result values for the node in Results (their number
733  /// and types must exactly match those of the original return values of
734  /// the node), or leaves Results empty, which indicates that the node is not
735  /// to be custom lowered after all.
736  void LowerOperationWrapper(SDNode *N,
738  SelectionDAG &DAG) const override;
739 
740  /// Replace the results of node with an illegal result
741  /// type with new values built out of custom code.
742  ///
743  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
744  SelectionDAG &DAG) const override;
745 
746  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
747 
748  // Return true if it is profitable to combine a BUILD_VECTOR with a
749  // stride-pattern to a shuffle and a truncate.
750  // Example of such a combine:
751  // v4i32 build_vector((extract_elt V, 1),
752  // (extract_elt V, 3),
753  // (extract_elt V, 5),
754  // (extract_elt V, 7))
755  // -->
756  // v4i32 truncate (bitcast (shuffle<1,u,3,u,4,u,5,u,6,u,7,u> V, u) to
757  // v4i64)
758  bool isDesirableToCombineBuildVectorToShuffleTruncate(
759  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const override;
760 
761  /// Return true if the target has native support for
762  /// the specified value type and it is 'desirable' to use the type for the
763  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
764  /// instruction encodings are longer and some i16 instructions are slow.
765  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
766 
767  /// Return true if the target has native support for the
768  /// specified value type and it is 'desirable' to use the type. e.g. On x86
769  /// i16 is legal, but undesirable since i16 instruction encodings are longer
770  /// and some i16 instructions are slow.
771  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
772 
774  EmitInstrWithCustomInserter(MachineInstr &MI,
775  MachineBasicBlock *MBB) const override;
776 
777  /// This method returns the name of a target specific DAG node.
778  const char *getTargetNodeName(unsigned Opcode) const override;
779 
780  bool mergeStoresAfterLegalization() const override { return true; }
781 
782  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
783  const SelectionDAG &DAG) const override;
784 
785  bool isCheapToSpeculateCttz() const override;
786 
787  bool isCheapToSpeculateCtlz() const override;
788 
789  bool isCtlzFast() const override;
790 
791  bool hasBitPreservingFPLogic(EVT VT) const override {
792  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
793  }
794 
795  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
796  // If the pair to store is a mixture of float and int values, we will
797  // save two bitwise instructions and one float-to-int instruction and
798  // increase one store instruction. There is potentially a more
799  // significant benefit because it avoids the float->int domain switch
800  // for input value. So It is more likely a win.
801  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
802  (LTy.isInteger() && HTy.isFloatingPoint()))
803  return true;
804  // If the pair only contains int values, we will save two bitwise
805  // instructions and increase one store instruction (costing one more
806  // store buffer). Since the benefit is more blurred so we leave
807  // such pair out until we get testcase to prove it is a win.
808  return false;
809  }
810 
811  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
812 
813  bool hasAndNotCompare(SDValue Y) const override;
814 
815  bool hasAndNot(SDValue Y) const override;
816 
817  bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;
818 
819  bool
821  unsigned KeptBits) const override {
822  // For vectors, we don't have a preference..
823  if (XVT.isVector())
824  return false;
825 
826  auto VTIsOk = [](EVT VT) -> bool {
827  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
828  VT == MVT::i64;
829  };
830 
831  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
832  // XVT will be larger than KeptBitsVT.
833  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
834  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
835  }
836 
837  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
839  return false;
840  return true;
841  }
842 
843  bool shouldSplatInsEltVarIndex(EVT VT) const override;
844 
845  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
846  return VT.isScalarInteger();
847  }
848 
849  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
850  MVT hasFastEqualityCompare(unsigned NumBits) const override;
851 
852  /// Allow multiple load pairs per block for smaller and faster code.
853  unsigned getMemcmpEqZeroLoadsPerBlock() const override {
854  return 2;
855  }
856 
857  /// Return the value type to use for ISD::SETCC.
858  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
859  EVT VT) const override;
860 
861  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
862  TargetLoweringOpt &TLO) const override;
863 
864  /// Determine which of the bits specified in Mask are known to be either
865  /// zero or one and return them in the KnownZero/KnownOne bitsets.
866  void computeKnownBitsForTargetNode(const SDValue Op,
867  KnownBits &Known,
868  const APInt &DemandedElts,
869  const SelectionDAG &DAG,
870  unsigned Depth = 0) const override;
871 
872  /// Determine the number of bits in the operation that are sign bits.
873  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
874  const APInt &DemandedElts,
875  const SelectionDAG &DAG,
876  unsigned Depth) const override;
877 
878  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
879  const APInt &DemandedElts,
880  APInt &KnownUndef,
881  APInt &KnownZero,
882  TargetLoweringOpt &TLO,
883  unsigned Depth) const override;
884 
885  bool SimplifyDemandedBitsForTargetNode(SDValue Op,
886  const APInt &DemandedBits,
887  const APInt &DemandedElts,
888  KnownBits &Known,
889  TargetLoweringOpt &TLO,
890  unsigned Depth) const override;
891 
892  SDValue unwrapAddress(SDValue N) const override;
893 
894  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
895 
896  bool ExpandInlineAsm(CallInst *CI) const override;
897 
898  ConstraintType getConstraintType(StringRef Constraint) const override;
899 
900  /// Examine constraint string and operand type and determine a weight value.
901  /// The operand object must already have been set up with the operand type.
903  getSingleConstraintMatchWeight(AsmOperandInfo &info,
904  const char *constraint) const override;
905 
906  const char *LowerXConstraint(EVT ConstraintVT) const override;
907 
908  /// Lower the specified operand into the Ops vector. If it is invalid, don't
909  /// add anything to Ops. If hasMemory is true it means one of the asm
910  /// constraint of the inline asm instruction being processed is 'm'.
911  void LowerAsmOperandForConstraint(SDValue Op,
912  std::string &Constraint,
913  std::vector<SDValue> &Ops,
914  SelectionDAG &DAG) const override;
915 
916  unsigned
917  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
918  if (ConstraintCode == "i")
920  else if (ConstraintCode == "o")
922  else if (ConstraintCode == "v")
924  else if (ConstraintCode == "X")
926  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
927  }
928 
929  /// Handle Lowering flag assembly outputs.
930  SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, SDLoc DL,
931  const AsmOperandInfo &Constraint,
932  SelectionDAG &DAG) const override;
933 
934  /// Given a physical register constraint
935  /// (e.g. {edx}), return the register number and the register class for the
936  /// register. This should only be used for C_Register constraints. On
937  /// error, this returns a register number of 0.
938  std::pair<unsigned, const TargetRegisterClass *>
939  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
940  StringRef Constraint, MVT VT) const override;
941 
942  /// Return true if the addressing mode represented
943  /// by AM is legal for this target, for a load/store of the specified type.
944  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
945  Type *Ty, unsigned AS,
946  Instruction *I = nullptr) const override;
947 
948  /// Return true if the specified immediate is legal
949  /// icmp immediate, that is the target has icmp instructions which can
950  /// compare a register against the immediate without having to materialize
951  /// the immediate into a register.
952  bool isLegalICmpImmediate(int64_t Imm) const override;
953 
954  /// Return true if the specified immediate is legal
955  /// add immediate, that is the target has add instructions which can
956  /// add a register and the immediate without having to materialize
957  /// the immediate into a register.
958  bool isLegalAddImmediate(int64_t Imm) const override;
959 
960  bool isLegalStoreImmediate(int64_t Imm) const override;
961 
962  /// Return the cost of the scaling factor used in the addressing
963  /// mode represented by AM for this target, for a load/store
964  /// of the specified type.
965  /// If the AM is supported, the return value must be >= 0.
966  /// If the AM is not supported, it returns a negative value.
967  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
968  unsigned AS) const override;
969 
970  bool isVectorShiftByScalarCheap(Type *Ty) const override;
971 
972  /// Returns true if the opcode is a commutative binary operation.
973  bool isCommutativeBinOp(unsigned Opcode) const override;
974 
975  /// Return true if it's free to truncate a value of
976  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
977  /// register EAX to i16 by referencing its sub-register AX.
978  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
979  bool isTruncateFree(EVT VT1, EVT VT2) const override;
980 
981  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
982 
983  /// Return true if any actual instruction that defines a
984  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
985  /// register. This does not necessarily include registers defined in
986  /// unknown ways, such as incoming arguments, or copies from unknown
987  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
988  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
989  /// all instructions that define 32-bit values implicit zero-extend the
990  /// result out to 64 bits.
991  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
992  bool isZExtFree(EVT VT1, EVT VT2) const override;
993  bool isZExtFree(SDValue Val, EVT VT2) const override;
994 
995  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
996  /// extend node) is profitable.
997  bool isVectorLoadExtDesirable(SDValue) const override;
998 
999  /// Return true if an FMA operation is faster than a pair of fmul and fadd
1000  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
1001  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
1002  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
1003 
1004  /// Return true if it's profitable to narrow
1005  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1006  /// from i32 to i8 but not from i32 to i16.
1007  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1008 
1009  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1010  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1011  /// true and stores the intrinsic information into the IntrinsicInfo that was
1012  /// passed to the function.
1013  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1014  MachineFunction &MF,
1015  unsigned Intrinsic) const override;
1016 
1017  /// Returns true if the target can instruction select the
1018  /// specified FP immediate natively. If false, the legalizer will
1019  /// materialize the FP immediate as a load from a constant pool.
1020  bool isFPImmLegal(const APFloat &Imm, EVT VT,
1021  bool ForCodeSize) const override;
1022 
1023  /// Targets can use this to indicate that they only support *some*
1024  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1025  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1026  /// be legal.
1027  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1028 
1029  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1030  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1031  /// constant pool entry.
1032  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1033 
1034  /// Returns true if lowering to a jump table is allowed.
1035  bool areJTsAllowed(const Function *Fn) const override;
1036 
1037  /// If true, then instruction selection should
1038  /// seek to shrink the FP constant of the specified type to a smaller type
1039  /// in order to save space and / or reduce runtime.
1040  bool ShouldShrinkFPConstant(EVT VT) const override {
1041  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
1042  // expensive than a straight movsd. On the other hand, it's important to
1043  // shrink long double fp constant since fldt is very slow.
1044  return !X86ScalarSSEf64 || VT == MVT::f80;
1045  }
1046 
1047  /// Return true if we believe it is correct and profitable to reduce the
1048  /// load node to a smaller type.
1049  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1050  EVT NewVT) const override;
1051 
1052  /// Return true if the specified scalar FP type is computed in an SSE
1053  /// register, not on the X87 floating point stack.
1054  bool isScalarFPTypeInSSEReg(EVT VT) const {
1055  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
1056  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
1057  }
1058 
1059  /// Returns true if it is beneficial to convert a load of a constant
1060  /// to just the constant itself.
1061  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1062  Type *Ty) const override;
1063 
1064  bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const override;
1065 
1066  bool convertSelectOfConstantsToMath(EVT VT) const override;
1067 
1068  bool decomposeMulByConstant(EVT VT, SDValue C) const override;
1069 
1070  bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1071  bool IsSigned) const override;
1072 
1073  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1074  /// with this index.
1075  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1076  unsigned Index) const override;
1077 
1078  /// Scalar ops always have equal or better analysis/performance/power than
1079  /// the vector equivalent, so this always makes sense if the scalar op is
1080  /// supported.
1081  bool shouldScalarizeBinop(SDValue) const override;
1082 
1083  /// Extract of a scalar FP value from index 0 of a vector is free.
1084  bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
1085  EVT EltVT = VT.getScalarType();
1086  return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
1087  }
1088 
1089  /// Overflow nodes should get combined/lowered to optimal instructions
1090  /// (they should allow eliminating explicit compares by getting flags from
1091  /// math ops).
1092  bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const override;
1093 
1094  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1095  unsigned AddrSpace) const override {
1096  // If we can replace more than 2 scalar stores, there will be a reduction
1097  // in instructions even after we add a vector constant load.
1098  return NumElem > 2;
1099  }
1100 
1101  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const override;
1102 
1103  /// Intel processors have a unified instruction and data cache
1104  const char * getClearCacheBuiltinName() const override {
1105  return nullptr; // nothing to do, move along.
1106  }
1107 
1108  unsigned getRegisterByName(const char* RegName, EVT VT,
1109  SelectionDAG &DAG) const override;
1110 
1111  /// If a physical register, this returns the register that receives the
1112  /// exception address on entry to an EH pad.
1113  unsigned
1114  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1115 
1116  /// If a physical register, this returns the register that receives the
1117  /// exception typeid on entry to a landing pad.
1118  unsigned
1119  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1120 
1121  virtual bool needsFixedCatchObjects() const override;
1122 
1123  /// This method returns a target specific FastISel object,
1124  /// or null if the target does not support "fast" ISel.
1126  const TargetLibraryInfo *libInfo) const override;
1127 
1128  /// If the target has a standard location for the stack protector cookie,
1129  /// returns the address of that location. Otherwise, returns nullptr.
1130  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
1131 
1132  bool useLoadStackGuardNode() const override;
1133  bool useStackGuardXorFP() const override;
1134  void insertSSPDeclarations(Module &M) const override;
1135  Value *getSDagStackGuard(const Module &M) const override;
1136  Function *getSSPStackGuardCheck(const Module &M) const override;
1137  SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
1138  const SDLoc &DL) const override;
1139 
1140 
1141  /// Return true if the target stores SafeStack pointer at a fixed offset in
1142  /// some non-standard address space, and populates the address space and
1143  /// offset as appropriate.
1144  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
1145 
1146  SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
1147  SelectionDAG &DAG) const;
1148 
1149  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
1150 
1151  /// Customize the preferred legalization strategy for certain types.
1152  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1153 
1154  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
1155  EVT VT) const override;
1156 
1157  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1158  CallingConv::ID CC,
1159  EVT VT) const override;
1160 
1161  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1162 
1163  bool supportSwiftError() const override;
1164 
1165  StringRef getStackProbeSymbolName(MachineFunction &MF) const override;
1166 
1167  bool hasVectorBlend() const override { return true; }
1168 
1169  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1170 
1171  /// Lower interleaved load(s) into target specific
1172  /// instructions/intrinsics.
1173  bool lowerInterleavedLoad(LoadInst *LI,
1175  ArrayRef<unsigned> Indices,
1176  unsigned Factor) const override;
1177 
1178  /// Lower interleaved store(s) into target specific
1179  /// instructions/intrinsics.
1180  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1181  unsigned Factor) const override;
1182 
1183  SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value,
1184  SDValue Addr, SelectionDAG &DAG)
1185  const override;
1186 
1187  protected:
1188  std::pair<const TargetRegisterClass *, uint8_t>
1189  findRepresentativeClass(const TargetRegisterInfo *TRI,
1190  MVT VT) const override;
1191 
1192  private:
1193  /// Keep a reference to the X86Subtarget around so that we can
1194  /// make the right decision when generating code for different targets.
1195  const X86Subtarget &Subtarget;
1196 
1197  /// Select between SSE or x87 floating point ops.
1198  /// When SSE is available, use it for f32 operations.
1199  /// When SSE2 is available, use it for f64 operations.
1200  bool X86ScalarSSEf32;
1201  bool X86ScalarSSEf64;
1202 
1203  /// A list of legal FP immediates.
1204  std::vector<APFloat> LegalFPImmediates;
1205 
1206  /// Indicate that this x86 target can instruction
1207  /// select the specified FP immediate natively.
1208  void addLegalFPImmediate(const APFloat& Imm) {
1209  LegalFPImmediates.push_back(Imm);
1210  }
1211 
1212  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1213  CallingConv::ID CallConv, bool isVarArg,
1215  const SDLoc &dl, SelectionDAG &DAG,
1216  SmallVectorImpl<SDValue> &InVals,
1217  uint32_t *RegMask) const;
1218  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1219  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1220  const SDLoc &dl, SelectionDAG &DAG,
1221  const CCValAssign &VA, MachineFrameInfo &MFI,
1222  unsigned i) const;
1224  const SDLoc &dl, SelectionDAG &DAG,
1225  const CCValAssign &VA,
1226  ISD::ArgFlagsTy Flags) const;
1227 
1228  // Call lowering helpers.
1229 
1230  /// Check whether the call is eligible for tail call optimization. Targets
1231  /// that want to do tail call optimization should implement this function.
1232  bool IsEligibleForTailCallOptimization(SDValue Callee,
1233  CallingConv::ID CalleeCC,
1234  bool isVarArg,
1235  bool isCalleeStructRet,
1236  bool isCallerStructRet,
1237  Type *RetTy,
1238  const SmallVectorImpl<ISD::OutputArg> &Outs,
1239  const SmallVectorImpl<SDValue> &OutVals,
1240  const SmallVectorImpl<ISD::InputArg> &Ins,
1241  SelectionDAG& DAG) const;
1242  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1243  SDValue Chain, bool IsTailCall,
1244  bool Is64Bit, int FPDiff,
1245  const SDLoc &dl) const;
1246 
1247  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1248  SelectionDAG &DAG) const;
1249 
1250  unsigned getAddressSpace(void) const;
1251 
1252  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned) const;
1253 
1254  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1255  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1258 
1259  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1260  const unsigned char OpFlags = 0) const;
1261  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1262  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1263  SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &dl,
1264  int64_t Offset, SelectionDAG &DAG) const;
1265  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1266  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1267  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1268 
1269  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1270  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1271  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1272  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1273  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1274  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1275  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1276  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1277  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1279  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1280  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1281  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1282  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1283  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1284  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1285  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1286  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1287  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1288  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1289  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1290  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1291  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1292  SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1293  SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1294  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1295 
1296  SDValue
1297  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1298  const SmallVectorImpl<ISD::InputArg> &Ins,
1299  const SDLoc &dl, SelectionDAG &DAG,
1300  SmallVectorImpl<SDValue> &InVals) const override;
1301  SDValue LowerCall(CallLoweringInfo &CLI,
1302  SmallVectorImpl<SDValue> &InVals) const override;
1303 
1304  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1305  const SmallVectorImpl<ISD::OutputArg> &Outs,
1306  const SmallVectorImpl<SDValue> &OutVals,
1307  const SDLoc &dl, SelectionDAG &DAG) const override;
1308 
1309  bool supportSplitCSR(MachineFunction *MF) const override {
1311  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1312  }
1313  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1314  void insertCopiesSplitCSR(
1315  MachineBasicBlock *Entry,
1316  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1317 
1318  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1319 
1320  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1321 
1322  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1323  ISD::NodeType ExtendKind) const override;
1324 
1325  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1326  bool isVarArg,
1327  const SmallVectorImpl<ISD::OutputArg> &Outs,
1328  LLVMContext &Context) const override;
1329 
1330  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1331 
1333  shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1334  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1336  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1337 
1338  LoadInst *
1339  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1340 
1341  bool needsCmpXchgNb(Type *MemType) const;
1342 
1343  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1344  MachineBasicBlock *DispatchBB, int FI) const;
1345 
1346  // Utility function to emit the low-level va_arg code for X86-64.
1348  EmitVAARG64WithCustomInserter(MachineInstr &MI,
1349  MachineBasicBlock *MBB) const;
1350 
1351  /// Utility function to emit the xmm reg save portion of va_start.
1353  EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
1354  MachineBasicBlock *BB) const;
1355 
1356  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1357  MachineInstr &MI2,
1358  MachineBasicBlock *BB) const;
1359 
1360  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1361  MachineBasicBlock *BB) const;
1362 
1363  MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I,
1364  MachineBasicBlock *BB) const;
1365 
1366  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1367  MachineBasicBlock *BB) const;
1368 
1369  MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
1370  MachineBasicBlock *BB) const;
1371 
1372  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1373  MachineBasicBlock *BB) const;
1374 
1375  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1376  MachineBasicBlock *BB) const;
1377 
1378  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1379  MachineBasicBlock *BB) const;
1380 
1381  MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI,
1382  MachineBasicBlock *BB) const;
1383 
1384  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1385  MachineBasicBlock *MBB) const;
1386 
1387  void emitSetJmpShadowStackFix(MachineInstr &MI,
1388  MachineBasicBlock *MBB) const;
1389 
1390  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1391  MachineBasicBlock *MBB) const;
1392 
1393  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1394  MachineBasicBlock *MBB) const;
1395 
1396  MachineBasicBlock *emitFMA3Instr(MachineInstr &MI,
1397  MachineBasicBlock *MBB) const;
1398 
1399  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1400  MachineBasicBlock *MBB) const;
1401 
1402  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1403  /// equivalent, for use with the given x86 condition code.
1404  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
1405  SelectionDAG &DAG) const;
1406 
1407  /// Convert a comparison if required by the subtarget.
1408  SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1409 
1410  /// Emit flags for the given setcc condition and operands. Also returns the
1411  /// corresponding X86 condition code constant in X86CC.
1412  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
1413  ISD::CondCode CC, const SDLoc &dl,
1414  SelectionDAG &DAG,
1415  SDValue &X86CC) const;
1416 
1417  /// Check if replacement of SQRT with RSQRT should be disabled.
1418  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
1419 
1420  /// Use rsqrt* to speed up sqrt calculations.
1421  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1422  int &RefinementSteps, bool &UseOneConstNR,
1423  bool Reciprocal) const override;
1424 
1425  /// Use rcp* to speed up fdiv calculations.
1426  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1427  int &RefinementSteps) const override;
1428 
1429  /// Reassociate floating point divisions into multiply by reciprocal.
1430  unsigned combineRepeatedFPDivisors() const override;
1431  };
1432 
1433  namespace X86 {
1435  const TargetLibraryInfo *libInfo);
1436  } // end namespace X86
1437 
1438  // Base class for all X86 non-masked store operations.
1439  class X86StoreSDNode : public MemSDNode {
1440  public:
1441  X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1442  SDVTList VTs, EVT MemVT,
1443  MachineMemOperand *MMO)
1444  :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1445  const SDValue &getValue() const { return getOperand(1); }
1446  const SDValue &getBasePtr() const { return getOperand(2); }
1447 
1448  static bool classof(const SDNode *N) {
1449  return N->getOpcode() == X86ISD::VTRUNCSTORES ||
1451  }
1452  };
1453 
1454  // Base class for all X86 masked store operations.
1455  // The class has the same order of operands as MaskedStoreSDNode for
1456  // convenience.
1458  public:
1459  X86MaskedStoreSDNode(unsigned Opcode, unsigned Order,
1460  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1461  MachineMemOperand *MMO)
1462  : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1463 
1464  const SDValue &getValue() const { return getOperand(1); }
1465  const SDValue &getBasePtr() const { return getOperand(2); }
1466  const SDValue &getMask() const { return getOperand(3); }
1467 
1468  static bool classof(const SDNode *N) {
1469  return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
1471  }
1472  };
1473 
1474  // X86 Truncating Store with Signed saturation.
1476  public:
1477  TruncSStoreSDNode(unsigned Order, const DebugLoc &dl,
1478  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1479  : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1480 
1481  static bool classof(const SDNode *N) {
1482  return N->getOpcode() == X86ISD::VTRUNCSTORES;
1483  }
1484  };
1485 
1486  // X86 Truncating Store with Unsigned saturation.
1488  public:
1489  TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl,
1490  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1491  : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1492 
1493  static bool classof(const SDNode *N) {
1494  return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1495  }
1496  };
1497 
1498  // X86 Truncating Masked Store with Signed saturation.
1500  public:
1501  MaskedTruncSStoreSDNode(unsigned Order,
1502  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1503  MachineMemOperand *MMO)
1504  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1505 
1506  static bool classof(const SDNode *N) {
1507  return N->getOpcode() == X86ISD::VMTRUNCSTORES;
1508  }
1509  };
1510 
1511  // X86 Truncating Masked Store with Unsigned saturation.
1513  public:
1515  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1516  MachineMemOperand *MMO)
1517  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1518 
1519  static bool classof(const SDNode *N) {
1520  return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1521  }
1522  };
1523 
1524  // X86 specific Gather/Scatter nodes.
1525  // The class has the same order of operands as MaskedGatherScatterSDNode for
1526  // convenience.
1528  public:
1529  X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order,
1530  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1531  MachineMemOperand *MMO)
1532  : MemSDNode(Opc, Order, dl, VTs, MemVT, MMO) {}
1533 
1534  const SDValue &getBasePtr() const { return getOperand(3); }
1535  const SDValue &getIndex() const { return getOperand(4); }
1536  const SDValue &getMask() const { return getOperand(2); }
1537  const SDValue &getScale() const { return getOperand(5); }
1538 
1539  static bool classof(const SDNode *N) {
1540  return N->getOpcode() == X86ISD::MGATHER ||
1541  N->getOpcode() == X86ISD::MSCATTER;
1542  }
1543  };
1544 
1546  public:
1547  X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1548  EVT MemVT, MachineMemOperand *MMO)
1549  : X86MaskedGatherScatterSDNode(X86ISD::MGATHER, Order, dl, VTs, MemVT,
1550  MMO) {}
1551 
1552  const SDValue &getPassThru() const { return getOperand(1); }
1553 
1554  static bool classof(const SDNode *N) {
1555  return N->getOpcode() == X86ISD::MGATHER;
1556  }
1557  };
1558 
1560  public:
1561  X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1562  EVT MemVT, MachineMemOperand *MMO)
1563  : X86MaskedGatherScatterSDNode(X86ISD::MSCATTER, Order, dl, VTs, MemVT,
1564  MMO) {}
1565 
1566  const SDValue &getValue() const { return getOperand(1); }
1567 
1568  static bool classof(const SDNode *N) {
1569  return N->getOpcode() == X86ISD::MSCATTER;
1570  }
1571  };
1572 
1573  /// Generate unpacklo/unpackhi shuffle mask.
1574  template <typename T = int>
1576  bool Unary) {
1577  assert(Mask.empty() && "Expected an empty shuffle mask vector");
1578  int NumElts = VT.getVectorNumElements();
1579  int NumEltsInLane = 128 / VT.getScalarSizeInBits();
1580  for (int i = 0; i < NumElts; ++i) {
1581  unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
1582  int Pos = (i % NumEltsInLane) / 2 + LaneStart;
1583  Pos += (Unary ? 0 : NumElts * (i % 2));
1584  Pos += (Lo ? 0 : NumEltsInLane / 2);
1585  Mask.push_back(Pos);
1586  }
1587  }
1588 
1589  /// Helper function to scale a shuffle or target shuffle mask, replacing each
1590  /// mask index with the scaled sequential indices for an equivalent narrowed
1591  /// mask. This is the reverse process to canWidenShuffleElements, but can
1592  /// always succeed.
1593  template <typename T>
1595  SmallVectorImpl<T> &ScaledMask) {
1596  assert(0 < Scale && "Unexpected scaling factor");
1597  int NumElts = Mask.size();
1598  ScaledMask.assign(static_cast<size_t>(NumElts * Scale), -1);
1599 
1600  for (int i = 0; i != NumElts; ++i) {
1601  int M = Mask[i];
1602 
1603  // Repeat sentinel values in every mask element.
1604  if (M < 0) {
1605  for (int s = 0; s != Scale; ++s)
1606  ScaledMask[(Scale * i) + s] = M;
1607  continue;
1608  }
1609 
1610  // Scale mask element and increment across each mask element.
1611  for (int s = 0; s != Scale; ++s)
1612  ScaledMask[(Scale * i) + s] = (Scale * M) + s;
1613  }
1614  }
1615 } // end namespace llvm
1616 
1617 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const SDValue & getIndex() const
Double shift instructions.
uint64_t CallInst * C
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
static MVT getIntegerVT(unsigned BitWidth)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
This instruction implements a fp->int store from FP stack slots.
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:886
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
Repeat move, corresponds to X86::REP_MOVSx.
void createUnpackShuffleMask(MVT VT, SmallVectorImpl< T > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
static bool classof(const SDNode *N)
Return with a flag operand.
const SDValue & getValue() const
const SDValue & getBasePtr() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const SDValue & getScale() const
Tail call return.
Compute Double Block Packed Sum-Absolute-Differences.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
static bool classof(const SDNode *N)
Same as call except it adds the NoTrack prefix.
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
X86 conditional moves.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned getVectorNumElements() const
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool isExtractVecEltCheap(EVT VT, unsigned Index) const override
Extract of a scalar FP value from index 0 of a vector is free.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
static bool classof(const SDNode *N)
SSE4A Extraction and Insertion.
static bool classof(const SDNode *N)
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Bitwise logical ANDNOT of floating point values.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
X86 compare and logical compare instructions.
MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
A description of a memory reference used in the backend.
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Bitwise Logical AND NOT of Packed FP values.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Integer horizontal add/sub.
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:416
Context object for machine code objects.
Definition: MCContext.h:62
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
X86 FP SETCC, similar to above, but with output as an i1 mask and and a version with SAE...
Return from interrupt. Operand 0 is the number of bytes to pop.
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:968
static bool classof(const SDNode *N)
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
const SDValue & getBasePtr() const
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Floating point horizontal add/sub.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Bitwise logical XOR of floating point values.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
static bool classof(const SDNode *N)
const SDValue & getMask() const
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
unsigned getScalarSizeInBits() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
This is an important base class in LLVM.
Definition: Constant.h:41
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:943
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
X86 conditional branches.
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Commutative FMIN and FMAX.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
const SDValue & getValue() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG)
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:21
unsigned getMemcmpEqZeroLoadsPerBlock() const override
Allow multiple load pairs per block for smaller and faster code.
X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Bit scan reverse.
Floating point reciprocal-sqrt and reciprocal approximation.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:893
const SDValue & getValue() const
Represents one node in the SelectionDAG.
X86 bit-test instructions.
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static bool classof(const SDNode *N)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool classof(const SDNode *N)
Bit scan forward.
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Representation of each machine instruction.
Definition: MachineInstr.h:63
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.
Bitwise logical AND of floating point values.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:597
static bool classof(const SDNode *N)
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
uint32_t Size
Definition: Profile.cpp:46
LOCK-prefixed arithmetic read-modify-write instructions.
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Blend where the selector is an immediate.
X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This instruction implements a truncating store from FP stack slots.
Combined add and sub on an FP vector.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This instruction grabs the address of the next argument from a va_list.
LLVM Value Representation.
Definition: Value.h:72
Bitwise logical OR of floating point values.
const SDValue & getBasePtr() const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
IRTranslator LLVM IR MI
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
const SDValue & getPassThru() const
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Compute Sum of Absolute Differences.
Scalar intrinsic floating point max and min.
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void scaleShuffleMask(int Scale, ArrayRef< T > Mask, SmallVectorImpl< T > &ScaledMask)
Helper function to scale a shuffle or target shuffle mask, replacing each mask index with the scaled ...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
BRIND node with NoTrack prefix.
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.