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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
15 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 
21 
22 namespace llvm {
23  class X86Subtarget;
24  class X86TargetMachine;
25 
26  namespace X86ISD {
27  // X86 Specific DAG Nodes
28  enum NodeType : unsigned {
29  // Start the numbering where the builtin ops leave off.
31 
32  /// Bit scan forward.
33  BSF,
34  /// Bit scan reverse.
35  BSR,
36 
37  /// Double shift instructions. These correspond to
38  /// X86::SHLDxx and X86::SHRDxx instructions.
41 
42  /// Bitwise logical AND of floating point values. This corresponds
43  /// to X86::ANDPS or X86::ANDPD.
45 
46  /// Bitwise logical OR of floating point values. This corresponds
47  /// to X86::ORPS or X86::ORPD.
48  FOR,
49 
50  /// Bitwise logical XOR of floating point values. This corresponds
51  /// to X86::XORPS or X86::XORPD.
53 
54  /// Bitwise logical ANDNOT of floating point values. This
55  /// corresponds to X86::ANDNPS or X86::ANDNPD.
57 
58  /// These operations represent an abstract X86 call
59  /// instruction, which includes a bunch of information. In particular the
60  /// operands of these node are:
61  ///
62  /// #0 - The incoming token chain
63  /// #1 - The callee
64  /// #2 - The number of arg bytes the caller pushes on the stack.
65  /// #3 - The number of arg bytes the callee pops off the stack.
66  /// #4 - The value to pass in AL/AX/EAX (optional)
67  /// #5 - The value to pass in DL/DX/EDX (optional)
68  ///
69  /// The result values of these nodes are:
70  ///
71  /// #0 - The outgoing token chain
72  /// #1 - The first register result value (optional)
73  /// #2 - The second register result value (optional)
74  ///
76 
77  /// Same as call except it adds the NoTrack prefix.
79 
80  /// This operation implements the lowering for readcyclecounter.
82 
83  /// X86 Read Time-Stamp Counter and Processor ID.
85 
86  /// X86 Read Performance Monitoring Counters.
88 
89  /// X86 compare and logical compare instructions.
91 
92  /// X86 bit-test instructions.
93  BT,
94 
95  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
96  /// operand, usually produced by a CMP instruction.
98 
99  /// X86 Select
101 
102  // Same as SETCC except it's materialized with a sbb and the value is all
103  // one's or all zero's.
104  SETCC_CARRY, // R = carry_bit ? ~0 : 0
105 
106  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
107  /// Operands are two FP values to compare; result is a mask of
108  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
110 
111  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
112  /// with optional rounding mode.
114 
115  /// X86 conditional moves. Operand 0 and operand 1 are the two values
116  /// to select from. Operand 2 is the condition code, and operand 3 is the
117  /// flag operand produced by a CMP or TEST instruction. It also writes a
118  /// flag result.
120 
121  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
122  /// is the block to branch if condition is true, operand 2 is the
123  /// condition code, and operand 3 is the flag operand produced by a CMP
124  /// or TEST instruction.
126 
127  /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
128  /// operand 1 is the target address.
130 
131  /// Return with a flag operand. Operand 0 is the chain operand, operand
132  /// 1 is the number of bytes of stack to pop.
134 
135  /// Return from interrupt. Operand 0 is the number of bytes to pop.
137 
138  /// Repeat fill, corresponds to X86::REP_STOSx.
140 
141  /// Repeat move, corresponds to X86::REP_MOVSx.
143 
144  /// On Darwin, this node represents the result of the popl
145  /// at function entry, used for PIC code.
147 
148  /// A wrapper node for TargetConstantPool, TargetJumpTable,
149  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
150  /// MCSymbol and TargetBlockAddress.
152 
153  /// Special wrapper used under X86-64 PIC mode for RIP
154  /// relative displacements.
156 
157  /// Copies a 64-bit value from the low word of an XMM vector
158  /// to an MMX vector.
160 
161  /// Copies a 32-bit value from the low word of a MMX
162  /// vector to a GPR.
164 
165  /// Copies a GPR into the low 32-bit word of a MMX vector
166  /// and zero out the high word.
168 
169  /// Extract an 8-bit value from a vector and zero extend it to
170  /// i32, corresponds to X86::PEXTRB.
172 
173  /// Extract a 16-bit value from a vector and zero extend it to
174  /// i32, corresponds to X86::PEXTRW.
176 
177  /// Insert any element of a 4 x float vector into any element
178  /// of a destination 4 x floatvector.
180 
181  /// Insert the lower 8-bits of a 32-bit value to a vector,
182  /// corresponds to X86::PINSRB.
184 
185  /// Insert the lower 16-bits of a 32-bit value to a vector,
186  /// corresponds to X86::PINSRW.
188 
189  /// Shuffle 16 8-bit values within a vector.
191 
192  /// Compute Sum of Absolute Differences.
194  /// Compute Double Block Packed Sum-Absolute-Differences
196 
197  /// Bitwise Logical AND NOT of Packed FP values.
199 
200  /// Blend where the selector is an immediate.
202 
203  /// Dynamic (non-constant condition) vector blend where only the sign bits
204  /// of the condition elements are used. This is used to enforce that the
205  /// condition mask is not valid for generic VSELECT optimizations. This
206  /// is also used to implement the intrinsics.
207  /// Operands are in VSELECT order: MASK, TRUE, FALSE
209 
210  /// Combined add and sub on an FP vector.
212 
213  // FP vector ops with rounding mode.
221 
222  // FP vector get exponent.
224  // Extract Normalized Mantissas.
226  // FP Scale.
229 
230  // Unsigned Integer average.
232 
233  /// Integer horizontal add/sub.
236 
237  /// Floating point horizontal add/sub.
240 
241  // Detect Conflicts Within a Vector
243 
244  /// Floating point max and min.
246 
247  /// Commutative FMIN and FMAX.
249 
250  /// Scalar intrinsic floating point max and min.
252 
253  /// Floating point reciprocal-sqrt and reciprocal approximation.
254  /// Note that these typically require refinement
255  /// in order to obtain suitable precision.
257 
258  // AVX-512 reciprocal approximations with a little more precision.
260 
261  // Thread Local Storage.
263 
264  // Thread Local Storage. A call to get the start address
265  // of the TLS block for the current module.
267 
268  // Thread Local Storage. When calling to an OS provided
269  // thunk at the address from an earlier relocation.
271 
272  // Exception Handling helpers.
274 
275  // SjLj exception handling setjmp.
277 
278  // SjLj exception handling longjmp.
280 
281  // SjLj exception handling dispatch.
283 
284  /// Tail call return. See X86TargetLowering::LowerCall for
285  /// the list of operands.
287 
288  // Vector move to low scalar and zero higher vector elements.
290 
291  // Vector integer truncate.
293  // Vector integer truncate with unsigned/signed saturation.
295 
296  // Masked version of the above. Used when less than a 128-bit result is
297  // produced since the mask only applies to the lower elements and can't
298  // be represented by a select.
299  // SRC, PASSTHRU, MASK
301 
302  // Vector FP extend.
304 
305  // Vector FP round.
307 
308  // Masked version of above. Used for v2f64->v4f32.
309  // SRC, PASSTHRU, MASK
311 
312  // 128-bit vector logical left / right shift
314 
315  // Vector shift elements
317 
318  // Vector variable shift
320 
321  // Vector shift elements by immediate
323 
324  // Shifts of mask registers.
326 
327  // Bit rotate by immediate
329 
330  // Vector packed double/float comparison.
332 
333  // Vector integer comparisons.
335 
336  // v8i16 Horizontal minimum and position.
338 
340 
341  /// Vector comparison generating mask bits for fp and
342  /// integer signed and unsigned data types.
344  // Vector comparison with rounding mode for FP values
346 
347  // Arithmetic operations with FLAGS results.
349  OR, XOR, AND,
350 
351  // Bit field extract.
353 
354  // Zero High Bits Starting with Specified Bit Position.
356 
357  // X86-specific multiply by immediate.
359 
360  // Vector sign bit extraction.
362 
363  // Vector bitwise comparisons.
365 
366  // Vector packed fp sign bitwise comparisons.
368 
369  // OR/AND test for masks.
372 
373  // ADD for masks.
375 
376  // Several flavors of instructions with vector shuffle behaviors.
377  // Saturated signed/unnsigned packing.
380  // Intra-lane alignr.
382  // AVX512 inter-lane alignr.
388  // VBMI2 Concat & Shift.
393  //Shuffle Packed Values at 128-bit granularity.
408 
409  // Variable Permute (VPERM).
410  // Res = VPERMV MaskV, V0
412 
413  // 3-op Variable Permute (VPERMT2).
414  // Res = VPERMV3 V0, MaskV, V1
416 
417  // Bitwise ternary logic.
419  // Fix Up Special Packed Float32/64 values.
422  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
424  // Reduce - Perform Reduction Transformation on scalar\packed FP.
426  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
427  // Also used by the legacy (V)ROUND intrinsics where we mask out the
428  // scaling part of the immediate.
430  // Tests Types Of a FP Values for packed types.
432  // Tests Types Of a FP Values for scalar types.
434 
435  // Broadcast scalar to vector.
437  // Broadcast mask to vector.
439  // Broadcast subvector to vector.
441 
442  /// SSE4A Extraction and Insertion.
444 
445  // XOP arithmetic/logical shifts.
447  // XOP signed/unsigned integer comparisons.
449  // XOP packed permute bytes.
451  // XOP two source permutation.
453 
454  // Vector multiply packed unsigned doubleword integers.
456  // Vector multiply packed signed doubleword integers.
458  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
460 
461  // Multiply and Add Packed Integers.
463 
464  // AVX512IFMA multiply and add.
465  // NOTE: These are different than the instruction and perform
466  // op0 x op1 + op2.
468 
469  // VNNI
474 
475  // FMA nodes.
476  // We use the target independent ISD::FMA for the non-inverted case.
482 
483  // FMA with rounding mode.
490 
491  // Compress and expand.
494 
495  // Bits shuffle
497 
498  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
501 
502  // Vector float/double to signed/unsigned integer.
504  // Scalar float/double to signed/unsigned integer.
506 
507  // Vector float/double to signed/unsigned integer with truncation.
509  // Scalar float/double to signed/unsigned integer with truncation.
511 
512  // Vector signed/unsigned integer to float/double.
514 
515  // Masked versions of above. Used for v2f64->v4f32.
516  // SRC, PASSTHRU, MASK
519 
520  // Save xmm argument registers to the stack, according to %al. An operator
521  // is needed so that this can be expanded with control flow.
523 
524  // Windows's _chkstk call to do stack probing.
526 
527  // For allocating variable amounts of stack space when using
528  // segmented stacks. Check if the current stacklet has enough space, and
529  // falls back to heap allocation if not.
531 
532  // Memory barriers.
535 
536  // Store FP status word into i16 register.
538 
539  // Store contents of %ah into %eflags.
541 
542  // Get a random integer and indicate whether it is valid in CF.
544 
545  // Get a NIST SP800-90B & C compliant random integer and
546  // indicate whether it is valid in CF.
548 
549  // SSE42 string comparisons.
550  // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
551  // will emit one or two instructions based on which results are used. If
552  // flags and index/mask this allows us to use a single instruction since
553  // we won't have to pick and opcode for flags. Instead we can rely on the
554  // DAG to CSE everything and decide at isel.
557 
558  // Test if in transactional execution.
560 
561  // ERI instructions.
563 
564  // Conversions between float and half-float.
566 
567  // Masked version of above.
568  // SRC, RND, PASSTHRU, MASK
570 
571  // Galois Field Arithmetic Instructions
573 
574  // LWP insert record.
576 
577  // User level wait
579 
580  // Compare and swap.
586 
587  /// LOCK-prefixed arithmetic read-modify-write instructions.
588  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
590 
591  // Load, scalar_to_vector, and zero extend.
593 
594  // Store FP control world into i16 memory.
596 
597  /// This instruction implements FP_TO_SINT with the
598  /// integer destination in memory and a FP reg source. This corresponds
599  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
600  /// has two inputs (token chain and address) and two outputs (int value
601  /// and token chain). Memory VT specifies the type to store to.
603 
604  /// This instruction implements SINT_TO_FP with the
605  /// integer source in memory and FP reg result. This corresponds to the
606  /// X86::FILD*m instructions. It has two inputs (token chain and address)
607  /// and two outputs (FP value and token chain). FILD_FLAG also produces a
608  /// flag). The integer source type is specified by the memory VT.
611 
612  /// This instruction implements an extending load to FP stack slots.
613  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
614  /// operand, and ptr to load from. The memory VT specifies the type to
615  /// load from.
617 
618  /// This instruction implements a truncating store to FP stack
619  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
620  /// chain operand, value to store, and address. The memory VT specifies
621  /// the type to store as.
623 
624  /// This instruction grabs the address of the next argument
625  /// from a va_list. (reads and modifies the va_list in memory)
627 
628  // Vector truncating store with unsigned/signed saturation
630  // Vector truncating masked store with unsigned/signed saturation
632 
633  // X86 specific gather and scatter
635 
636  // WARNING: Do not add anything in the end unless you want the node to
637  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
638  // opcodes will be thought as target memory ops!
639  };
640  } // end namespace X86ISD
641 
642  /// Define some predicates that are used for node matching.
643  namespace X86 {
644  /// Returns true if Elt is a constant zero or floating point constant +0.0.
645  bool isZeroNode(SDValue Elt);
646 
647  /// Returns true of the given offset can be
648  /// fit into displacement field of the instruction.
650  bool hasSymbolicDisplacement = true);
651 
652  /// Determines whether the callee is required to pop its
653  /// own arguments. Callee pop is necessary to support tail calls.
655  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
656 
657  } // end namespace X86
658 
659  //===--------------------------------------------------------------------===//
660  // X86 Implementation of the TargetLowering interface
661  class X86TargetLowering final : public TargetLowering {
662  public:
663  explicit X86TargetLowering(const X86TargetMachine &TM,
664  const X86Subtarget &STI);
665 
666  unsigned getJumpTableEncoding() const override;
667  bool useSoftFloat() const override;
668 
669  void markLibCallAttributes(MachineFunction *MF, unsigned CC,
670  ArgListTy &Args) const override;
671 
672  MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override {
673  return MVT::i8;
674  }
675 
676  const MCExpr *
677  LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
678  const MachineBasicBlock *MBB, unsigned uid,
679  MCContext &Ctx) const override;
680 
681  /// Returns relocation base for the given PIC jumptable.
682  SDValue getPICJumpTableRelocBase(SDValue Table,
683  SelectionDAG &DAG) const override;
684  const MCExpr *
685  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
686  unsigned JTI, MCContext &Ctx) const override;
687 
688  /// Return the desired alignment for ByVal aggregate
689  /// function arguments in the caller parameter area. For X86, aggregates
690  /// that contains are placed at 16-byte boundaries while the rest are at
691  /// 4-byte boundaries.
692  unsigned getByValTypeAlignment(Type *Ty,
693  const DataLayout &DL) const override;
694 
695  /// Returns the target specific optimal type for load
696  /// and store operations as a result of memset, memcpy, and memmove
697  /// lowering. If DstAlign is zero that means it's safe to destination
698  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
699  /// means there isn't a need to check it against alignment requirement,
700  /// probably because the source does not need to be loaded. If 'IsMemset' is
701  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
702  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
703  /// source is constant so it does not need to be loaded.
704  /// It returns EVT::Other if the type should be determined using generic
705  /// target-independent logic.
706  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
707  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
708  MachineFunction &MF) const override;
709 
710  /// Returns true if it's safe to use load / store of the
711  /// specified type to expand memcpy / memset inline. This is mostly true
712  /// for all types except for some special cases. For example, on X86
713  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
714  /// also does type conversion. Note the specified type doesn't have to be
715  /// legal as the hook is used before type legalization.
716  bool isSafeMemOpType(MVT VT) const override;
717 
718  /// Returns true if the target allows unaligned memory accesses of the
719  /// specified type. Returns whether it is "fast" in the last argument.
720  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
721  bool *Fast) const override;
722 
723  /// Provide custom lowering hooks for some operations.
724  ///
725  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
726 
727  /// Places new result values for the node in Results (their number
728  /// and types must exactly match those of the original return values of
729  /// the node), or leaves Results empty, which indicates that the node is not
730  /// to be custom lowered after all.
731  void LowerOperationWrapper(SDNode *N,
733  SelectionDAG &DAG) const override;
734 
735  /// Replace the results of node with an illegal result
736  /// type with new values built out of custom code.
737  ///
738  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
739  SelectionDAG &DAG) const override;
740 
741  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
742 
743  // Return true if it is profitable to combine a BUILD_VECTOR with a
744  // stride-pattern to a shuffle and a truncate.
745  // Example of such a combine:
746  // v4i32 build_vector((extract_elt V, 1),
747  // (extract_elt V, 3),
748  // (extract_elt V, 5),
749  // (extract_elt V, 7))
750  // -->
751  // v4i32 truncate (bitcast (shuffle<1,u,3,u,4,u,5,u,6,u,7,u> V, u) to
752  // v4i64)
753  bool isDesirableToCombineBuildVectorToShuffleTruncate(
754  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const override;
755 
756  /// Return true if the target has native support for
757  /// the specified value type and it is 'desirable' to use the type for the
758  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
759  /// instruction encodings are longer and some i16 instructions are slow.
760  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
761 
762  /// Return true if the target has native support for the
763  /// specified value type and it is 'desirable' to use the type. e.g. On x86
764  /// i16 is legal, but undesirable since i16 instruction encodings are longer
765  /// and some i16 instructions are slow.
766  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
767 
769  EmitInstrWithCustomInserter(MachineInstr &MI,
770  MachineBasicBlock *MBB) const override;
771 
772  /// This method returns the name of a target specific DAG node.
773  const char *getTargetNodeName(unsigned Opcode) const override;
774 
775  bool mergeStoresAfterLegalization() const override { return true; }
776 
777  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
778  const SelectionDAG &DAG) const override;
779 
780  bool isCheapToSpeculateCttz() const override;
781 
782  bool isCheapToSpeculateCtlz() const override;
783 
784  bool isCtlzFast() const override;
785 
786  bool hasBitPreservingFPLogic(EVT VT) const override {
787  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
788  }
789 
790  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
791  // If the pair to store is a mixture of float and int values, we will
792  // save two bitwise instructions and one float-to-int instruction and
793  // increase one store instruction. There is potentially a more
794  // significant benefit because it avoids the float->int domain switch
795  // for input value. So It is more likely a win.
796  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
797  (LTy.isInteger() && HTy.isFloatingPoint()))
798  return true;
799  // If the pair only contains int values, we will save two bitwise
800  // instructions and increase one store instruction (costing one more
801  // store buffer). Since the benefit is more blurred so we leave
802  // such pair out until we get testcase to prove it is a win.
803  return false;
804  }
805 
806  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
807 
808  bool hasAndNotCompare(SDValue Y) const override;
809 
810  bool hasAndNot(SDValue Y) const override;
811 
812  bool preferShiftsToClearExtremeBits(SDValue Y) const override;
813 
814  bool
816  unsigned KeptBits) const override {
817  // For vectors, we don't have a preference..
818  if (XVT.isVector())
819  return false;
820 
821  auto VTIsOk = [](EVT VT) -> bool {
822  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
823  VT == MVT::i64;
824  };
825 
826  // We are ok with KeptBitsVT being byte/word/dword, what MOVS supports.
827  // XVT will be larger than KeptBitsVT.
828  MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
829  return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
830  }
831 
832  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
834  return false;
835  return true;
836  }
837 
838  bool shouldSplatInsEltVarIndex(EVT VT) const override;
839 
840  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
841  return VT.isScalarInteger();
842  }
843 
844  /// Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
845  MVT hasFastEqualityCompare(unsigned NumBits) const override;
846 
847  /// Allow multiple load pairs per block for smaller and faster code.
848  unsigned getMemcmpEqZeroLoadsPerBlock() const override {
849  return 2;
850  }
851 
852  /// Return the value type to use for ISD::SETCC.
853  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
854  EVT VT) const override;
855 
856  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
857  TargetLoweringOpt &TLO) const override;
858 
859  /// Determine which of the bits specified in Mask are known to be either
860  /// zero or one and return them in the KnownZero/KnownOne bitsets.
861  void computeKnownBitsForTargetNode(const SDValue Op,
862  KnownBits &Known,
863  const APInt &DemandedElts,
864  const SelectionDAG &DAG,
865  unsigned Depth = 0) const override;
866 
867  /// Determine the number of bits in the operation that are sign bits.
868  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
869  const APInt &DemandedElts,
870  const SelectionDAG &DAG,
871  unsigned Depth) const override;
872 
873  bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op,
874  const APInt &DemandedElts,
875  APInt &KnownUndef,
876  APInt &KnownZero,
877  TargetLoweringOpt &TLO,
878  unsigned Depth) const override;
879 
880  bool SimplifyDemandedBitsForTargetNode(SDValue Op,
881  const APInt &DemandedBits,
882  const APInt &DemandedElts,
883  KnownBits &Known,
884  TargetLoweringOpt &TLO,
885  unsigned Depth) const override;
886 
887  SDValue unwrapAddress(SDValue N) const override;
888 
889  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
890 
891  bool ExpandInlineAsm(CallInst *CI) const override;
892 
893  ConstraintType getConstraintType(StringRef Constraint) const override;
894 
895  /// Examine constraint string and operand type and determine a weight value.
896  /// The operand object must already have been set up with the operand type.
898  getSingleConstraintMatchWeight(AsmOperandInfo &info,
899  const char *constraint) const override;
900 
901  const char *LowerXConstraint(EVT ConstraintVT) const override;
902 
903  /// Lower the specified operand into the Ops vector. If it is invalid, don't
904  /// add anything to Ops. If hasMemory is true it means one of the asm
905  /// constraint of the inline asm instruction being processed is 'm'.
906  void LowerAsmOperandForConstraint(SDValue Op,
907  std::string &Constraint,
908  std::vector<SDValue> &Ops,
909  SelectionDAG &DAG) const override;
910 
911  unsigned
912  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
913  if (ConstraintCode == "i")
915  else if (ConstraintCode == "o")
917  else if (ConstraintCode == "v")
919  else if (ConstraintCode == "X")
921  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
922  }
923 
924  /// Handle Lowering flag assembly outputs.
925  SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, SDLoc DL,
926  const AsmOperandInfo &Constraint,
927  SelectionDAG &DAG) const override;
928 
929  /// Given a physical register constraint
930  /// (e.g. {edx}), return the register number and the register class for the
931  /// register. This should only be used for C_Register constraints. On
932  /// error, this returns a register number of 0.
933  std::pair<unsigned, const TargetRegisterClass *>
934  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
935  StringRef Constraint, MVT VT) const override;
936 
937  /// Return true if the addressing mode represented
938  /// by AM is legal for this target, for a load/store of the specified type.
939  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
940  Type *Ty, unsigned AS,
941  Instruction *I = nullptr) const override;
942 
943  /// Return true if the specified immediate is legal
944  /// icmp immediate, that is the target has icmp instructions which can
945  /// compare a register against the immediate without having to materialize
946  /// the immediate into a register.
947  bool isLegalICmpImmediate(int64_t Imm) const override;
948 
949  /// Return true if the specified immediate is legal
950  /// add immediate, that is the target has add instructions which can
951  /// add a register and the immediate without having to materialize
952  /// the immediate into a register.
953  bool isLegalAddImmediate(int64_t Imm) const override;
954 
955  bool isLegalStoreImmediate(int64_t Imm) const override;
956 
957  /// Return the cost of the scaling factor used in the addressing
958  /// mode represented by AM for this target, for a load/store
959  /// of the specified type.
960  /// If the AM is supported, the return value must be >= 0.
961  /// If the AM is not supported, it returns a negative value.
962  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
963  unsigned AS) const override;
964 
965  bool isVectorShiftByScalarCheap(Type *Ty) const override;
966 
967  /// Return true if it's free to truncate a value of
968  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
969  /// register EAX to i16 by referencing its sub-register AX.
970  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
971  bool isTruncateFree(EVT VT1, EVT VT2) const override;
972 
973  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
974 
975  /// Return true if any actual instruction that defines a
976  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
977  /// register. This does not necessarily include registers defined in
978  /// unknown ways, such as incoming arguments, or copies from unknown
979  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
980  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
981  /// all instructions that define 32-bit values implicit zero-extend the
982  /// result out to 64 bits.
983  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
984  bool isZExtFree(EVT VT1, EVT VT2) const override;
985  bool isZExtFree(SDValue Val, EVT VT2) const override;
986 
987  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
988  /// extend node) is profitable.
989  bool isVectorLoadExtDesirable(SDValue) const override;
990 
991  /// Return true if an FMA operation is faster than a pair of fmul and fadd
992  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
993  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
994  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
995 
996  /// Return true if it's profitable to narrow
997  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
998  /// from i32 to i8 but not from i32 to i16.
999  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
1000 
1001  /// Given an intrinsic, checks if on the target the intrinsic will need to map
1002  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1003  /// true and stores the intrinsic information into the IntrinsicInfo that was
1004  /// passed to the function.
1005  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
1006  MachineFunction &MF,
1007  unsigned Intrinsic) const override;
1008 
1009  /// Returns true if the target can instruction select the
1010  /// specified FP immediate natively. If false, the legalizer will
1011  /// materialize the FP immediate as a load from a constant pool.
1012  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
1013 
1014  /// Targets can use this to indicate that they only support *some*
1015  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
1016  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
1017  /// be legal.
1018  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1019 
1020  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
1021  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
1022  /// constant pool entry.
1023  bool isVectorClearMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
1024 
1025  /// Returns true if lowering to a jump table is allowed.
1026  bool areJTsAllowed(const Function *Fn) const override;
1027 
1028  /// If true, then instruction selection should
1029  /// seek to shrink the FP constant of the specified type to a smaller type
1030  /// in order to save space and / or reduce runtime.
1031  bool ShouldShrinkFPConstant(EVT VT) const override {
1032  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
1033  // expensive than a straight movsd. On the other hand, it's important to
1034  // shrink long double fp constant since fldt is very slow.
1035  return !X86ScalarSSEf64 || VT == MVT::f80;
1036  }
1037 
1038  /// Return true if we believe it is correct and profitable to reduce the
1039  /// load node to a smaller type.
1040  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1041  EVT NewVT) const override;
1042 
1043  /// Return true if the specified scalar FP type is computed in an SSE
1044  /// register, not on the X87 floating point stack.
1045  bool isScalarFPTypeInSSEReg(EVT VT) const {
1046  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
1047  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
1048  }
1049 
1050  /// Returns true if it is beneficial to convert a load of a constant
1051  /// to just the constant itself.
1052  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1053  Type *Ty) const override;
1054 
1055  bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const override;
1056 
1057  bool convertSelectOfConstantsToMath(EVT VT) const override;
1058 
1059  bool decomposeMulByConstant(EVT VT, SDValue C) const override;
1060 
1061  bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1062  bool IsSigned) const override;
1063 
1064  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1065  /// with this index.
1066  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1067  unsigned Index) const override;
1068 
1069  /// Scalar ops always have equal or better analysis/performance/power than
1070  /// the vector equivalent, so this always makes sense if the scalar op is
1071  /// supported.
1072  bool shouldScalarizeBinop(SDValue) const override;
1073 
1074  /// Overflow nodes should get combined/lowered to optimal instructions
1075  /// (they should allow eliminating explicit compares by getting flags from
1076  /// math ops).
1077  bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const override;
1078 
1079  bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem,
1080  unsigned AddrSpace) const override {
1081  // If we can replace more than 2 scalar stores, there will be a reduction
1082  // in instructions even after we add a vector constant load.
1083  return NumElem > 2;
1084  }
1085 
1086  bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const override;
1087 
1088  /// Intel processors have a unified instruction and data cache
1089  const char * getClearCacheBuiltinName() const override {
1090  return nullptr; // nothing to do, move along.
1091  }
1092 
1093  unsigned getRegisterByName(const char* RegName, EVT VT,
1094  SelectionDAG &DAG) const override;
1095 
1096  /// If a physical register, this returns the register that receives the
1097  /// exception address on entry to an EH pad.
1098  unsigned
1099  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1100 
1101  /// If a physical register, this returns the register that receives the
1102  /// exception typeid on entry to a landing pad.
1103  unsigned
1104  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1105 
1106  virtual bool needsFixedCatchObjects() const override;
1107 
1108  /// This method returns a target specific FastISel object,
1109  /// or null if the target does not support "fast" ISel.
1111  const TargetLibraryInfo *libInfo) const override;
1112 
1113  /// If the target has a standard location for the stack protector cookie,
1114  /// returns the address of that location. Otherwise, returns nullptr.
1115  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
1116 
1117  bool useLoadStackGuardNode() const override;
1118  bool useStackGuardXorFP() const override;
1119  void insertSSPDeclarations(Module &M) const override;
1120  Value *getSDagStackGuard(const Module &M) const override;
1121  Function *getSSPStackGuardCheck(const Module &M) const override;
1122  SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
1123  const SDLoc &DL) const override;
1124 
1125 
1126  /// Return true if the target stores SafeStack pointer at a fixed offset in
1127  /// some non-standard address space, and populates the address space and
1128  /// offset as appropriate.
1129  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
1130 
1131  SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
1132  SelectionDAG &DAG) const;
1133 
1134  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
1135 
1136  /// Customize the preferred legalization strategy for certain types.
1137  LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
1138 
1139  MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
1140  EVT VT) const override;
1141 
1142  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1143  CallingConv::ID CC,
1144  EVT VT) const override;
1145 
1146  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
1147 
1148  bool supportSwiftError() const override;
1149 
1150  StringRef getStackProbeSymbolName(MachineFunction &MF) const override;
1151 
1152  bool hasVectorBlend() const override { return true; }
1153 
1154  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1155 
1156  /// Lower interleaved load(s) into target specific
1157  /// instructions/intrinsics.
1158  bool lowerInterleavedLoad(LoadInst *LI,
1160  ArrayRef<unsigned> Indices,
1161  unsigned Factor) const override;
1162 
1163  /// Lower interleaved store(s) into target specific
1164  /// instructions/intrinsics.
1165  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1166  unsigned Factor) const override;
1167 
1168  SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value,
1169  SDValue Addr, SelectionDAG &DAG)
1170  const override;
1171 
1172  protected:
1173  std::pair<const TargetRegisterClass *, uint8_t>
1174  findRepresentativeClass(const TargetRegisterInfo *TRI,
1175  MVT VT) const override;
1176 
1177  private:
1178  /// Keep a reference to the X86Subtarget around so that we can
1179  /// make the right decision when generating code for different targets.
1180  const X86Subtarget &Subtarget;
1181 
1182  /// Select between SSE or x87 floating point ops.
1183  /// When SSE is available, use it for f32 operations.
1184  /// When SSE2 is available, use it for f64 operations.
1185  bool X86ScalarSSEf32;
1186  bool X86ScalarSSEf64;
1187 
1188  /// A list of legal FP immediates.
1189  std::vector<APFloat> LegalFPImmediates;
1190 
1191  /// Indicate that this x86 target can instruction
1192  /// select the specified FP immediate natively.
1193  void addLegalFPImmediate(const APFloat& Imm) {
1194  LegalFPImmediates.push_back(Imm);
1195  }
1196 
1197  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1198  CallingConv::ID CallConv, bool isVarArg,
1200  const SDLoc &dl, SelectionDAG &DAG,
1201  SmallVectorImpl<SDValue> &InVals,
1202  uint32_t *RegMask) const;
1203  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1204  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1205  const SDLoc &dl, SelectionDAG &DAG,
1206  const CCValAssign &VA, MachineFrameInfo &MFI,
1207  unsigned i) const;
1209  const SDLoc &dl, SelectionDAG &DAG,
1210  const CCValAssign &VA,
1211  ISD::ArgFlagsTy Flags) const;
1212 
1213  // Call lowering helpers.
1214 
1215  /// Check whether the call is eligible for tail call optimization. Targets
1216  /// that want to do tail call optimization should implement this function.
1217  bool IsEligibleForTailCallOptimization(SDValue Callee,
1218  CallingConv::ID CalleeCC,
1219  bool isVarArg,
1220  bool isCalleeStructRet,
1221  bool isCallerStructRet,
1222  Type *RetTy,
1223  const SmallVectorImpl<ISD::OutputArg> &Outs,
1224  const SmallVectorImpl<SDValue> &OutVals,
1225  const SmallVectorImpl<ISD::InputArg> &Ins,
1226  SelectionDAG& DAG) const;
1227  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1228  SDValue Chain, bool IsTailCall,
1229  bool Is64Bit, int FPDiff,
1230  const SDLoc &dl) const;
1231 
1232  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1233  SelectionDAG &DAG) const;
1234 
1235  unsigned getAddressSpace(void) const;
1236 
1237  SDValue FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned) const;
1238 
1239  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1240  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1243 
1244  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr,
1245  const unsigned char OpFlags = 0) const;
1246  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1247  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1248  SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &dl,
1249  int64_t Offset, SelectionDAG &DAG) const;
1250  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1251  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1252  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1253 
1254  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1255  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1256  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1257  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
1258  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1259  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
1260  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1261  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1262  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1264  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1265  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1266  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1267  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1268  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1269  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1270  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1271  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1272  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1273  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1274  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1275  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1276  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1277  SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1278  SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1279  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1280 
1281  SDValue
1282  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1283  const SmallVectorImpl<ISD::InputArg> &Ins,
1284  const SDLoc &dl, SelectionDAG &DAG,
1285  SmallVectorImpl<SDValue> &InVals) const override;
1286  SDValue LowerCall(CallLoweringInfo &CLI,
1287  SmallVectorImpl<SDValue> &InVals) const override;
1288 
1289  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1290  const SmallVectorImpl<ISD::OutputArg> &Outs,
1291  const SmallVectorImpl<SDValue> &OutVals,
1292  const SDLoc &dl, SelectionDAG &DAG) const override;
1293 
1294  bool supportSplitCSR(MachineFunction *MF) const override {
1296  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
1297  }
1298  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1299  void insertCopiesSplitCSR(
1300  MachineBasicBlock *Entry,
1301  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1302 
1303  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1304 
1305  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1306 
1307  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1308  ISD::NodeType ExtendKind) const override;
1309 
1310  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1311  bool isVarArg,
1312  const SmallVectorImpl<ISD::OutputArg> &Outs,
1313  LLVMContext &Context) const override;
1314 
1315  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1316 
1318  shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1319  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1321  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1322 
1323  LoadInst *
1324  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1325 
1326  bool needsCmpXchgNb(Type *MemType) const;
1327 
1328  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1329  MachineBasicBlock *DispatchBB, int FI) const;
1330 
1331  // Utility function to emit the low-level va_arg code for X86-64.
1333  EmitVAARG64WithCustomInserter(MachineInstr &MI,
1334  MachineBasicBlock *MBB) const;
1335 
1336  /// Utility function to emit the xmm reg save portion of va_start.
1338  EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
1339  MachineBasicBlock *BB) const;
1340 
1341  MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
1342  MachineInstr &MI2,
1343  MachineBasicBlock *BB) const;
1344 
1345  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1346  MachineBasicBlock *BB) const;
1347 
1348  MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I,
1349  MachineBasicBlock *BB) const;
1350 
1351  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1352  MachineBasicBlock *BB) const;
1353 
1354  MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
1355  MachineBasicBlock *BB) const;
1356 
1357  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1358  MachineBasicBlock *BB) const;
1359 
1360  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1361  MachineBasicBlock *BB) const;
1362 
1363  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1364  MachineBasicBlock *BB) const;
1365 
1366  MachineBasicBlock *EmitLoweredRetpoline(MachineInstr &MI,
1367  MachineBasicBlock *BB) const;
1368 
1369  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1370  MachineBasicBlock *MBB) const;
1371 
1372  void emitSetJmpShadowStackFix(MachineInstr &MI,
1373  MachineBasicBlock *MBB) const;
1374 
1375  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1376  MachineBasicBlock *MBB) const;
1377 
1378  MachineBasicBlock *emitLongJmpShadowStackFix(MachineInstr &MI,
1379  MachineBasicBlock *MBB) const;
1380 
1381  MachineBasicBlock *emitFMA3Instr(MachineInstr &MI,
1382  MachineBasicBlock *MBB) const;
1383 
1384  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1385  MachineBasicBlock *MBB) const;
1386 
1387  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1388  /// equivalent, for use with the given x86 condition code.
1389  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
1390  SelectionDAG &DAG) const;
1391 
1392  /// Convert a comparison if required by the subtarget.
1393  SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1394 
1395  /// Emit flags for the given setcc condition and operands. Also returns the
1396  /// corresponding X86 condition code constant in X86CC.
1397  SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
1398  ISD::CondCode CC, const SDLoc &dl,
1399  SelectionDAG &DAG,
1400  SDValue &X86CC) const;
1401 
1402  /// Check if replacement of SQRT with RSQRT should be disabled.
1403  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
1404 
1405  /// Use rsqrt* to speed up sqrt calculations.
1406  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1407  int &RefinementSteps, bool &UseOneConstNR,
1408  bool Reciprocal) const override;
1409 
1410  /// Use rcp* to speed up fdiv calculations.
1411  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1412  int &RefinementSteps) const override;
1413 
1414  /// Reassociate floating point divisions into multiply by reciprocal.
1415  unsigned combineRepeatedFPDivisors() const override;
1416  };
1417 
1418  namespace X86 {
1420  const TargetLibraryInfo *libInfo);
1421  } // end namespace X86
1422 
1423  // Base class for all X86 non-masked store operations.
1424  class X86StoreSDNode : public MemSDNode {
1425  public:
1426  X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1427  SDVTList VTs, EVT MemVT,
1428  MachineMemOperand *MMO)
1429  :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1430  const SDValue &getValue() const { return getOperand(1); }
1431  const SDValue &getBasePtr() const { return getOperand(2); }
1432 
1433  static bool classof(const SDNode *N) {
1434  return N->getOpcode() == X86ISD::VTRUNCSTORES ||
1436  }
1437  };
1438 
1439  // Base class for all X86 masked store operations.
1440  // The class has the same order of operands as MaskedStoreSDNode for
1441  // convenience.
1443  public:
1444  X86MaskedStoreSDNode(unsigned Opcode, unsigned Order,
1445  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1446  MachineMemOperand *MMO)
1447  : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1448 
1449  const SDValue &getValue() const { return getOperand(1); }
1450  const SDValue &getBasePtr() const { return getOperand(2); }
1451  const SDValue &getMask() const { return getOperand(3); }
1452 
1453  static bool classof(const SDNode *N) {
1454  return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
1456  }
1457  };
1458 
1459  // X86 Truncating Store with Signed saturation.
1461  public:
1462  TruncSStoreSDNode(unsigned Order, const DebugLoc &dl,
1463  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1464  : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1465 
1466  static bool classof(const SDNode *N) {
1467  return N->getOpcode() == X86ISD::VTRUNCSTORES;
1468  }
1469  };
1470 
1471  // X86 Truncating Store with Unsigned saturation.
1473  public:
1474  TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl,
1475  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1476  : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1477 
1478  static bool classof(const SDNode *N) {
1479  return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1480  }
1481  };
1482 
1483  // X86 Truncating Masked Store with Signed saturation.
1485  public:
1486  MaskedTruncSStoreSDNode(unsigned Order,
1487  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1488  MachineMemOperand *MMO)
1489  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1490 
1491  static bool classof(const SDNode *N) {
1492  return N->getOpcode() == X86ISD::VMTRUNCSTORES;
1493  }
1494  };
1495 
1496  // X86 Truncating Masked Store with Unsigned saturation.
1498  public:
1500  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1501  MachineMemOperand *MMO)
1502  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1503 
1504  static bool classof(const SDNode *N) {
1505  return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1506  }
1507  };
1508 
1509  // X86 specific Gather/Scatter nodes.
1510  // The class has the same order of operands as MaskedGatherScatterSDNode for
1511  // convenience.
1513  public:
1514  X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order,
1515  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1516  MachineMemOperand *MMO)
1517  : MemSDNode(Opc, Order, dl, VTs, MemVT, MMO) {}
1518 
1519  const SDValue &getBasePtr() const { return getOperand(3); }
1520  const SDValue &getIndex() const { return getOperand(4); }
1521  const SDValue &getMask() const { return getOperand(2); }
1522  const SDValue &getScale() const { return getOperand(5); }
1523 
1524  static bool classof(const SDNode *N) {
1525  return N->getOpcode() == X86ISD::MGATHER ||
1526  N->getOpcode() == X86ISD::MSCATTER;
1527  }
1528  };
1529 
1531  public:
1532  X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1533  EVT MemVT, MachineMemOperand *MMO)
1534  : X86MaskedGatherScatterSDNode(X86ISD::MGATHER, Order, dl, VTs, MemVT,
1535  MMO) {}
1536 
1537  const SDValue &getPassThru() const { return getOperand(1); }
1538 
1539  static bool classof(const SDNode *N) {
1540  return N->getOpcode() == X86ISD::MGATHER;
1541  }
1542  };
1543 
1545  public:
1546  X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1547  EVT MemVT, MachineMemOperand *MMO)
1548  : X86MaskedGatherScatterSDNode(X86ISD::MSCATTER, Order, dl, VTs, MemVT,
1549  MMO) {}
1550 
1551  const SDValue &getValue() const { return getOperand(1); }
1552 
1553  static bool classof(const SDNode *N) {
1554  return N->getOpcode() == X86ISD::MSCATTER;
1555  }
1556  };
1557 
1558  /// Generate unpacklo/unpackhi shuffle mask.
1559  template <typename T = int>
1561  bool Unary) {
1562  assert(Mask.empty() && "Expected an empty shuffle mask vector");
1563  int NumElts = VT.getVectorNumElements();
1564  int NumEltsInLane = 128 / VT.getScalarSizeInBits();
1565  for (int i = 0; i < NumElts; ++i) {
1566  unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
1567  int Pos = (i % NumEltsInLane) / 2 + LaneStart;
1568  Pos += (Unary ? 0 : NumElts * (i % 2));
1569  Pos += (Lo ? 0 : NumEltsInLane / 2);
1570  Mask.push_back(Pos);
1571  }
1572  }
1573 
1574  /// Helper function to scale a shuffle or target shuffle mask, replacing each
1575  /// mask index with the scaled sequential indices for an equivalent narrowed
1576  /// mask. This is the reverse process to canWidenShuffleElements, but can
1577  /// always succeed.
1578  template <typename T>
1580  SmallVectorImpl<T> &ScaledMask) {
1581  assert(0 < Scale && "Unexpected scaling factor");
1582  int NumElts = Mask.size();
1583  ScaledMask.assign(static_cast<size_t>(NumElts * Scale), -1);
1584 
1585  for (int i = 0; i != NumElts; ++i) {
1586  int M = Mask[i];
1587 
1588  // Repeat sentinel values in every mask element.
1589  if (M < 0) {
1590  for (int s = 0; s != Scale; ++s)
1591  ScaledMask[(Scale * i) + s] = M;
1592  continue;
1593  }
1594 
1595  // Scale mask element and increment across each mask element.
1596  for (int s = 0; s != Scale; ++s)
1597  ScaledMask[(Scale * i) + s] = (Scale * M) + s;
1598  }
1599  }
1600 } // end namespace llvm
1601 
1602 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const SDValue & getIndex() const
Double shift instructions.
uint64_t CallInst * C
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
static MVT getIntegerVT(unsigned BitWidth)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:883
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
Repeat move, corresponds to X86::REP_MOVSx.
void createUnpackShuffleMask(MVT VT, SmallVectorImpl< T > &Mask, bool Lo, bool Unary)
Generate unpacklo/unpackhi shuffle mask.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
static bool classof(const SDNode *N)
Return with a flag operand.
const SDValue & getValue() const
const SDValue & getBasePtr() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const SDValue & getScale() const
Tail call return.
Compute Double Block Packed Sum-Absolute-Differences.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
static bool classof(const SDNode *N)
Same as call except it adds the NoTrack prefix.
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
X86 conditional moves.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned getVectorNumElements() const
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
static bool classof(const SDNode *N)
SSE4A Extraction and Insertion.
static bool classof(const SDNode *N)
An instruction for reading from memory.
Definition: Instructions.h:167
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Bitwise logical ANDNOT of floating point values.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
This operation implements the lowering for readcyclecounter.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
X86 compare and logical compare instructions.
MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
A description of a memory reference used in the backend.
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Dynamic (non-constant condition) vector blend where only the sign bits of the condition elements are ...
Bitwise Logical AND NOT of Packed FP values.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Integer horizontal add/sub.
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
void assign(size_type NumElts, const T &Elt)
Definition: SmallVector.h:415
Context object for machine code objects.
Definition: MCContext.h:62
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:397
X86 FP SETCC, similar to above, but with output as an i1 mask and with optional rounding mode...
Return from interrupt. Operand 0 is the number of bytes to pop.
This contains information for each constraint that we are lowering.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
An instruction for storing to memory.
Definition: Instructions.h:320
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
static bool classof(const SDNode *N)
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
const SDValue & getBasePtr() const
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Floating point horizontal add/sub.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Bitwise logical XOR of floating point values.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
static bool classof(const SDNode *N)
const SDValue & getMask() const
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
unsigned getScalarSizeInBits() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
This is an important base class in LLVM.
Definition: Constant.h:41
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:940
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
X86 conditional branches.
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
Commutative FMIN and FMAX.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
const SDValue & getValue() const
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG)
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Provides information about what library functions are available for the current target.
X86 Read Time-Stamp Counter and Processor ID.
CCValAssign - Represent assignment of one arg/retval to a location.
AddressSpace
Definition: NVPTXBaseInfo.h:21
unsigned getMemcmpEqZeroLoadsPerBlock() const override
Allow multiple load pairs per block for smaller and faster code.
X86MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Bit scan reverse.
Floating point reciprocal-sqrt and reciprocal approximation.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:890
const SDValue & getValue() const
Represents one node in the SelectionDAG.
X86 bit-test instructions.
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static bool classof(const SDNode *N)
MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool classof(const SDNode *N)
Bit scan forward.
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Representation of each machine instruction.
Definition: MachineInstr.h:63
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.
Bitwise logical AND of floating point values.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:594
static bool classof(const SDNode *N)
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
uint32_t Size
Definition: Profile.cpp:46
LOCK-prefixed arithmetic read-modify-write instructions.
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
bool hasVectorBlend() const override
Return true if the target has a vector blend instruction.
Blend where the selector is an immediate.
X86MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
This instruction implements a truncating store to FP stack slots.
Combined add and sub on an FP vector.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This instruction grabs the address of the next argument from a va_list.
LLVM Value Representation.
Definition: Value.h:72
Bitwise logical OR of floating point values.
X86 Read Performance Monitoring Counters.
const SDValue & getBasePtr() const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
IRTranslator LLVM IR MI
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
const SDValue & getPassThru() const
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Compute Sum of Absolute Differences.
Scalar intrinsic floating point max and min.
MVT getScalarShiftAmountTy(const DataLayout &, EVT VT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void scaleShuffleMask(int Scale, ArrayRef< T > Mask, SmallVectorImpl< T > &ScaledMask)
Helper function to scale a shuffle or target shuffle mask, replacing each mask index with the scaled ...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
BRIND node with NoTrack prefix.
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.