LLVM  7.0.0svn
FunctionLoweringInfo.h
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1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating functions from LLVM IR into
11 // Machine IR.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
17 
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/IndexedMap.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/IR/Value.h"
30 #include "llvm/Support/KnownBits.h"
31 #include <cassert>
32 #include <utility>
33 #include <vector>
34 
35 namespace llvm {
36 
37 class Argument;
38 class BasicBlock;
39 class BranchProbabilityInfo;
40 class Function;
41 class Instruction;
42 class MachineFunction;
43 class MachineInstr;
44 class MachineRegisterInfo;
45 class MVT;
46 class SelectionDAG;
47 class TargetLowering;
48 
49 //===--------------------------------------------------------------------===//
50 /// FunctionLoweringInfo - This contains information that is global to a
51 /// function that is used when lowering a region of the function.
52 ///
54 public:
55  const Function *Fn;
60  /// CanLowerReturn - true iff the function's return value can be lowered to
61  /// registers.
63 
64  /// True if part of the CSRs will be handled via explicit copies.
65  bool SplitCSR;
66 
67  /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
68  /// allocated to hold a pointer to the hidden sret parameter.
69  unsigned DemoteRegister;
70 
71  /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
73 
74  /// A map from swifterror value in a basic block to the virtual register it is
75  /// currently represented by.
78 
79  /// A list of upward exposed vreg uses that need to be satisfied by either a
80  /// copy def or a phi node at the beginning of the basic block representing
81  /// the predecessor(s) swifterror value.
84 
85  /// A map from instructions that define/use a swifterror value to the virtual
86  /// register that represents that def/use.
89 
90  /// The swifterror argument of the current function.
92 
94  /// A function can only have a single swifterror argument. And if it does
95  /// have a swifterror argument, it must be the first entry in
96  /// SwiftErrorVals.
98 
99  /// Get or create the swifterror value virtual register in
100  /// SwiftErrorVRegDefMap for this basic block.
102  const Value *);
103 
104  /// Set the swifterror virtual register in the SwiftErrorVRegDefMap for this
105  /// basic block.
107  unsigned);
108 
109  /// Get or create the swifterror value virtual register for a def of a
110  /// swifterror by an instruction.
111  std::pair<unsigned, bool> getOrCreateSwiftErrorVRegDefAt(const Instruction *);
112  std::pair<unsigned, bool>
114  const Value *);
115 
116  /// ValueMap - Since we emit code for the function a basic block at a time,
117  /// we must remember which virtual registers hold the values for
118  /// cross-basic-block values.
120 
121  /// VirtReg2Value map is needed by the Divergence Analysis driven
122  /// instruction selection. It is reverted ValueMap. It is computed
123  /// in lazy style - on demand. It is used to get the Value corresponding
124  /// to the live in virtual register and is called from the
125  /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
127 
128  /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
129  /// to get the Value corresponding to the live-in virtual register.
130  const Value * getValueFromVirtualReg(unsigned Vreg);
131 
132  /// Track virtual registers created for exception pointers.
134 
135  /// Keep track of frame indices allocated for statepoints as they could be
136  /// used across basic block boundaries. This struct is more complex than a
137  /// simple map because the stateopint lowering code de-duplicates gc pointers
138  /// based on their SDValue (so %p and (bitcast %p to T) will get the same
139  /// slot), and we track that here.
140 
143 
144  /// Maps uniqued llvm IR values to the slots they were spilled in. If a
145  /// value is mapped to None it means we visited the value but didn't spill
146  /// it (because it was a constant, for instance).
148 
149  /// Maps llvm IR values to the values they were de-duplicated to.
151 
153  auto DuplIt = DuplicateMap.find(V);
154  if (DuplIt != DuplicateMap.end())
155  V = DuplIt->second;
156  return SlotMap.find(V);
157  }
158 
159  SlotMapTy::const_iterator end() const { return SlotMap.end(); }
160  };
161 
162  /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
163  /// instances.
165 
166  /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
167  /// the entry block. This allows the allocas to be efficiently referenced
168  /// anywhere in the function.
170 
171  /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
173 
174  /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
175  /// function arguments that are inserted after scheduling is completed.
177 
178  /// RegFixups - Registers which need to be replaced after isel is done.
180 
182 
183  /// StatepointStackSlots - A list of temporary stack slots (frame indices)
184  /// used to spill values at a statepoint. We store them here to enable
185  /// reuse of the same stack slots across different statepoints in different
186  /// basic blocks.
188 
189  /// MBB - The current block.
191 
192  /// MBB - The current insert position inside the current block.
194 
195  struct LiveOutInfo {
196  unsigned NumSignBits : 31;
197  unsigned IsValid : 1;
198  KnownBits Known = 1;
199 
200  LiveOutInfo() : NumSignBits(0), IsValid(true) {}
201  };
202 
203  /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
204  /// for a value.
206 
207  /// VisitedBBs - The set of basic blocks visited thus far by instruction
208  /// selection.
210 
211  /// PHINodesToUpdate - A list of phi instructions whose operand list will
212  /// be updated after processing the current basic block.
213  /// TODO: This isn't per-function state, it's per-basic-block state. But
214  /// there's no other convenient place for it to live right now.
215  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
217 
218  /// If the current MBB is a landing pad, the exception pointer and exception
219  /// selector registers are copied into these virtual registers by
220  /// SelectionDAGISel::PrepareEHLandingPad().
222 
223  /// set - Initialize this FunctionLoweringInfo with the given Function
224  /// and its associated MachineFunction.
225  ///
226  void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
227 
228  /// clear - Clear out all the function-specific state. This returns this
229  /// FunctionLoweringInfo to an empty state, ready to be used for a
230  /// different function.
231  void clear();
232 
233  /// isExportedInst - Return true if the specified value is an instruction
234  /// exported from its block.
235  bool isExportedInst(const Value *V) {
236  return ValueMap.count(V);
237  }
238 
239  unsigned CreateReg(MVT VT);
240 
241  unsigned CreateRegs(Type *Ty);
242 
243  unsigned InitializeRegForValue(const Value *V) {
244  // Tokens never live in vregs.
245  if (V->getType()->isTokenTy())
246  return 0;
247  unsigned &R = ValueMap[V];
248  assert(R == 0 && "Already initialized this value register!");
249  return R = CreateRegs(V->getType());
250  }
251 
252  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
253  /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
254  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
255  if (!LiveOutRegInfo.inBounds(Reg))
256  return nullptr;
257 
258  const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
259  if (!LOI->IsValid)
260  return nullptr;
261 
262  return LOI;
263  }
264 
265  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
266  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
267  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
268  /// the larger bit width by zero extension. The bit width must be no smaller
269  /// than the LiveOutInfo's existing bit width.
270  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
271 
272  /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
273  void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
274  const KnownBits &Known) {
275  // Only install this information if it tells us something.
276  if (NumSignBits == 1 && Known.isUnknown())
277  return;
278 
279  LiveOutRegInfo.grow(Reg);
280  LiveOutInfo &LOI = LiveOutRegInfo[Reg];
281  LOI.NumSignBits = NumSignBits;
282  LOI.Known.One = Known.One;
283  LOI.Known.Zero = Known.Zero;
284  }
285 
286  /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
287  /// register based on the LiveOutInfo of its operands.
288  void ComputePHILiveOutRegInfo(const PHINode*);
289 
290  /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
291  /// called when a block is visited before all of its predecessors.
293  // PHIs with no uses have no ValueMap entry.
295  if (It == ValueMap.end())
296  return;
297 
298  unsigned Reg = It->second;
299  if (Reg == 0)
300  return;
301 
302  LiveOutRegInfo.grow(Reg);
303  LiveOutRegInfo[Reg].IsValid = false;
304  }
305 
306  /// setArgumentFrameIndex - Record frame index for the byval
307  /// argument.
308  void setArgumentFrameIndex(const Argument *A, int FI);
309 
310  /// getArgumentFrameIndex - Get frame index for the byval argument.
311  int getArgumentFrameIndex(const Argument *A);
312 
313  unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
314  const TargetRegisterClass *RC);
315 
316 private:
317  void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
318 
319  /// LiveOutRegInfo - Information about live out vregs.
321 };
322 
323 } // end namespace llvm
324 
325 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Various leaf nodes.
Definition: ISDOpcodes.h:60
unsigned getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
unsigned Reg
DenseMap< const Value *, unsigned > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
bool CanLowerReturn
CanLowerReturn - true iff the function&#39;s return value can be lowered to registers.
void setCurrentSwiftErrorVReg(const MachineBasicBlock *MBB, const Value *, unsigned)
Set the swifterror virtual register in the SwiftErrorVRegDefMap for this basic block.
Keep track of frame indices allocated for statepoints as they could be used across basic block bounda...
std::pair< unsigned, bool > getOrCreateSwiftErrorVRegDefAt(const Instruction *)
Get or create the swifterror value virtual register for a def of a swifterror by an instruction...
unsigned DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
const Value * SwiftErrorArg
The swifterror argument of the current function.
DenseMap< const Value *, unsigned > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
const LiveOutInfo * GetLiveOutRegInfo(unsigned Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
DenseSet< unsigned > RegsWithFixups
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
void clear()
clear - Clear out all the function-specific state.
SlotMapTy SlotMap
Maps uniqued llvm IR values to the slots they were spilled in.
DenseMap< unsigned, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
std::pair< unsigned, bool > getOrCreateSwiftErrorVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)
void grow(unsigned AtLeast)
Definition: DenseMap.h:728
void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, const KnownBits &Known)
AddLiveOutRegInfo - Adds LiveOutInfo for a register.
DenseMap< const Instruction *, StatepointSpillMap > StatepointSpillMaps
Maps gc.statepoint instructions to their corresponding StatepointSpillMap instances.
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI&#39;s destination register based on the LiveOutI...
MachineBasicBlock * MBB
MBB - The current block.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
bool SplitCSR
True if part of the CSRs will be handled via explicit copies.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:418
DenseMap< std::pair< const MachineBasicBlock *, const Value * >, unsigned > SwiftErrorVRegDefMap
A map from swifterror value in a basic block to the virtual register it is currently represented by...
DenseMap< unsigned, unsigned > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
DenseMap< const Value *, const Value * > DuplicateMap
Maps llvm IR values to the values they were de-duplicated to.
DenseMap< std::pair< const MachineBasicBlock *, const Value * >, unsigned > SwiftErrorVRegUpwardsUse
A list of upward exposed vreg uses that need to be satisfied by either a copy def or a phi node at th...
unsigned CreateRegs(Type *Ty)
CreateRegs - Allocate the appropriate number of virtual registers of the correctly promoted or expand...
BranchProbabilityInfo * BPI
bool isUnknown() const
Returns true if we don&#39;t know any bits.
Definition: KnownBits.h:63
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Basic Alias true
Analysis providing branch probability information.
MachineRegisterInfo * RegInfo
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:194
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
const Value * getValueFromVirtualReg(unsigned Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
unsigned CreateReg(MVT VT)
CreateReg - Allocate a single virtual register for the given type.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:141
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void InvalidatePHILiveOutRegInfo(const PHINode *PN)
InvalidatePHILiveOutRegInfo - Invalidates a PHI&#39;s LiveOutInfo, to be called when a block is visited b...
LLVM Value Representation.
Definition: Value.h:73
llvm::DenseMap< PointerIntPair< const Instruction *, 1, bool >, unsigned > SwiftErrorVRegDefUses
A map from instructions that define/use a swifterror value to the virtual register that represents th...
SlotMapTy::const_iterator find(const Value *V) const
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
SwiftErrorValues SwiftErrorVals
A function can only have a single swifterror argument.
const TargetLowering * TLI
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
bool isExportedInst(const Value *V)
isExportedInst - Return true if the specified value is an instruction exported from its block...
unsigned InitializeRegForValue(const Value *V)
unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register in SwiftErrorVRegDefMap for this basic block...