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FunctionLoweringInfo.h
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1 //===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements routines for translating functions from LLVM IR into
10 // Machine IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/IR/Value.h"
30 #include "llvm/Support/KnownBits.h"
31 #include <cassert>
32 #include <utility>
33 #include <vector>
34 
35 namespace llvm {
36 
37 class Argument;
38 class BasicBlock;
39 class BranchProbabilityInfo;
40 class Function;
41 class Instruction;
42 class MachineFunction;
43 class MachineInstr;
44 class MachineRegisterInfo;
45 class MVT;
46 class SelectionDAG;
47 class TargetLowering;
48 
49 //===--------------------------------------------------------------------===//
50 /// FunctionLoweringInfo - This contains information that is global to a
51 /// function that is used when lowering a region of the function.
52 ///
54 public:
55  const Function *Fn;
61  /// CanLowerReturn - true iff the function's return value can be lowered to
62  /// registers.
64 
65  /// True if part of the CSRs will be handled via explicit copies.
66  bool SplitCSR;
67 
68  /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
69  /// allocated to hold a pointer to the hidden sret parameter.
70  unsigned DemoteRegister;
71 
72  /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
74 
75  /// ValueMap - Since we emit code for the function a basic block at a time,
76  /// we must remember which virtual registers hold the values for
77  /// cross-basic-block values.
79 
80  /// VirtReg2Value map is needed by the Divergence Analysis driven
81  /// instruction selection. It is reverted ValueMap. It is computed
82  /// in lazy style - on demand. It is used to get the Value corresponding
83  /// to the live in virtual register and is called from the
84  /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
86 
87  /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
88  /// to get the Value corresponding to the live-in virtual register.
89  const Value * getValueFromVirtualReg(unsigned Vreg);
90 
91  /// Track virtual registers created for exception pointers.
93 
94  /// Keep track of frame indices allocated for statepoints as they could be
95  /// used across basic block boundaries. This struct is more complex than a
96  /// simple map because the stateopint lowering code de-duplicates gc pointers
97  /// based on their SDValue (so %p and (bitcast %p to T) will get the same
98  /// slot), and we track that here.
99 
102 
103  /// Maps uniqued llvm IR values to the slots they were spilled in. If a
104  /// value is mapped to None it means we visited the value but didn't spill
105  /// it (because it was a constant, for instance).
107 
108  /// Maps llvm IR values to the values they were de-duplicated to.
110 
112  auto DuplIt = DuplicateMap.find(V);
113  if (DuplIt != DuplicateMap.end())
114  V = DuplIt->second;
115  return SlotMap.find(V);
116  }
117 
118  SlotMapTy::const_iterator end() const { return SlotMap.end(); }
119  };
120 
121  /// Maps gc.statepoint instructions to their corresponding StatepointSpillMap
122  /// instances.
124 
125  /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
126  /// the entry block. This allows the allocas to be efficiently referenced
127  /// anywhere in the function.
129 
130  /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
132 
133  /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
134  /// function arguments that are inserted after scheduling is completed.
136 
137  /// Bitvector with a bit set if corresponding argument is described in
138  /// ArgDbgValues. Using arg numbers according to Argument numbering.
140 
141  /// RegFixups - Registers which need to be replaced after isel is done.
143 
145 
146  /// StatepointStackSlots - A list of temporary stack slots (frame indices)
147  /// used to spill values at a statepoint. We store them here to enable
148  /// reuse of the same stack slots across different statepoints in different
149  /// basic blocks.
151 
152  /// MBB - The current block.
154 
155  /// MBB - The current insert position inside the current block.
157 
158  struct LiveOutInfo {
159  unsigned NumSignBits : 31;
160  unsigned IsValid : 1;
161  KnownBits Known = 1;
162 
163  LiveOutInfo() : NumSignBits(0), IsValid(true) {}
164  };
165 
166  /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
167  /// for a value.
169 
170  /// VisitedBBs - The set of basic blocks visited thus far by instruction
171  /// selection.
173 
174  /// PHINodesToUpdate - A list of phi instructions whose operand list will
175  /// be updated after processing the current basic block.
176  /// TODO: This isn't per-function state, it's per-basic-block state. But
177  /// there's no other convenient place for it to live right now.
178  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
180 
181  /// If the current MBB is a landing pad, the exception pointer and exception
182  /// selector registers are copied into these virtual registers by
183  /// SelectionDAGISel::PrepareEHLandingPad().
185 
186  /// set - Initialize this FunctionLoweringInfo with the given Function
187  /// and its associated MachineFunction.
188  ///
189  void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
190 
191  /// clear - Clear out all the function-specific state. This returns this
192  /// FunctionLoweringInfo to an empty state, ready to be used for a
193  /// different function.
194  void clear();
195 
196  /// isExportedInst - Return true if the specified value is an instruction
197  /// exported from its block.
198  bool isExportedInst(const Value *V) {
199  return ValueMap.count(V);
200  }
201 
202  unsigned CreateReg(MVT VT, bool isDivergent = false);
203 
204  unsigned CreateRegs(const Value *V);
205 
206  unsigned CreateRegs(Type *Ty, bool isDivergent = false);
207 
208  unsigned InitializeRegForValue(const Value *V) {
209  // Tokens never live in vregs.
210  if (V->getType()->isTokenTy())
211  return 0;
212  unsigned &R = ValueMap[V];
213  assert(R == 0 && "Already initialized this value register!");
214  assert(VirtReg2Value.empty());
215  return R = CreateRegs(V);
216  }
217 
218  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
219  /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
220  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
221  if (!LiveOutRegInfo.inBounds(Reg))
222  return nullptr;
223 
224  const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
225  if (!LOI->IsValid)
226  return nullptr;
227 
228  return LOI;
229  }
230 
231  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
232  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
233  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
234  /// the larger bit width by zero extension. The bit width must be no smaller
235  /// than the LiveOutInfo's existing bit width.
236  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
237 
238  /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
239  void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
240  const KnownBits &Known) {
241  // Only install this information if it tells us something.
242  if (NumSignBits == 1 && Known.isUnknown())
243  return;
244 
245  LiveOutRegInfo.grow(Reg);
246  LiveOutInfo &LOI = LiveOutRegInfo[Reg];
247  LOI.NumSignBits = NumSignBits;
248  LOI.Known.One = Known.One;
249  LOI.Known.Zero = Known.Zero;
250  }
251 
252  /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
253  /// register based on the LiveOutInfo of its operands.
254  void ComputePHILiveOutRegInfo(const PHINode*);
255 
256  /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
257  /// called when a block is visited before all of its predecessors.
259  // PHIs with no uses have no ValueMap entry.
261  if (It == ValueMap.end())
262  return;
263 
264  unsigned Reg = It->second;
265  if (Reg == 0)
266  return;
267 
268  LiveOutRegInfo.grow(Reg);
269  LiveOutRegInfo[Reg].IsValid = false;
270  }
271 
272  /// setArgumentFrameIndex - Record frame index for the byval
273  /// argument.
274  void setArgumentFrameIndex(const Argument *A, int FI);
275 
276  /// getArgumentFrameIndex - Get frame index for the byval argument.
277  int getArgumentFrameIndex(const Argument *A);
278 
279  unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
280  const TargetRegisterClass *RC);
281 
282 private:
283  void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
284 
285  /// LiveOutRegInfo - Information about live out vregs.
287 };
288 
289 } // end namespace llvm
290 
291 #endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
unsigned CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Various leaf nodes.
Definition: ISDOpcodes.h:59
unsigned getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
unsigned Reg
block Block Frequency true
DenseMap< const Value *, unsigned > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
bool CanLowerReturn
CanLowerReturn - true iff the function&#39;s return value can be lowered to registers.
Keep track of frame indices allocated for statepoints as they could be used across basic block bounda...
unsigned DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
DenseMap< const Value *, unsigned > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
const LiveOutInfo * GetLiveOutRegInfo(unsigned Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
DenseSet< unsigned > RegsWithFixups
const LegacyDivergenceAnalysis * DA
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void clear()
clear - Clear out all the function-specific state.
SlotMapTy SlotMap
Maps uniqued llvm IR values to the slots they were spilled in.
DenseMap< unsigned, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void grow(unsigned AtLeast)
Definition: DenseMap.h:798
void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, const KnownBits &Known)
AddLiveOutRegInfo - Adds LiveOutInfo for a register.
DenseMap< const Instruction *, StatepointSpillMap > StatepointSpillMaps
Maps gc.statepoint instructions to their corresponding StatepointSpillMap instances.
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI&#39;s destination register based on the LiveOutI...
MachineBasicBlock * MBB
MBB - The current block.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
bool SplitCSR
True if part of the CSRs will be handled via explicit copies.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
DenseMap< unsigned, unsigned > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
DenseMap< const Value *, const Value * > DuplicateMap
Maps llvm IR values to the values they were de-duplicated to.
BranchProbabilityInfo * BPI
bool isUnknown() const
Returns true if we don&#39;t know any bits.
Definition: KnownBits.h:62
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
unsigned CreateRegs(const Value *V)
Analysis providing branch probability information.
MachineRegisterInfo * RegInfo
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:193
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
const Value * getValueFromVirtualReg(unsigned Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:171
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void InvalidatePHILiveOutRegInfo(const PHINode *PN)
InvalidatePHILiveOutRegInfo - Invalidates a PHI&#39;s LiveOutInfo, to be called when a block is visited b...
LLVM Value Representation.
Definition: Value.h:72
SlotMapTy::const_iterator find(const Value *V) const
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
const TargetLowering * TLI
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
bool isExportedInst(const Value *V)
isExportedInst - Return true if the specified value is an instruction exported from its block...
unsigned InitializeRegForValue(const Value *V)