LLVM  6.0.0svn
Public Member Functions | Friends | List of all members
llvm::SDValue Class Reference

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...

#include "llvm/CodeGen/SelectionDAGNodes.h"

Public Member Functions

 SDValue ()=default
 
 SDValue (SDNode *node, unsigned resno)
 
unsigned getResNo () const
 get the index which selects a specific result in the SDNode More...
 
SDNodegetNode () const
 get the SDNode which holds the desired result More...
 
void setNode (SDNode *N)
 set the SDNode More...
 
SDNodeoperator-> () const
 
bool operator== (const SDValue &O) const
 
bool operator!= (const SDValue &O) const
 
bool operator< (const SDValue &O) const
 
 operator bool () const
 
SDValue getValue (unsigned R) const
 
bool isOperandOf (const SDNode *N) const
 Return true if this node is an operand of N. More...
 
EVT getValueType () const
 Return the ValueType of the referenced return value. More...
 
MVT getSimpleValueType () const
 Return the simple ValueType of the referenced return value. More...
 
unsigned getValueSizeInBits () const
 Returns the size of the value in bits. More...
 
unsigned getScalarValueSizeInBits () const
 
unsigned getOpcode () const
 
unsigned getNumOperands () const
 
const SDValuegetOperand (unsigned i) const
 
uint64_t getConstantOperandVal (unsigned i) const
 
bool isTargetMemoryOpcode () const
 
bool isTargetOpcode () const
 
bool isMachineOpcode () const
 
bool isUndef () const
 
unsigned getMachineOpcode () const
 
const DebugLocgetDebugLoc () const
 
void dump () const
 
void dumpr () const
 
bool reachesChainWithoutSideEffects (SDValue Dest, unsigned Depth=2) const
 Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions. More...
 
bool use_empty () const
 Return true if there are no nodes using value ResNo of Node. More...
 
bool hasOneUse () const
 Return true if there is exactly one node using value ResNo of Node. More...
 

Friends

struct DenseMapInfo< SDValue >
 

Detailed Description

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).

As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.

Definition at line 123 of file SelectionDAGNodes.h.

Constructor & Destructor Documentation

◆ SDValue() [1/2]

llvm::SDValue::SDValue ( )
default

◆ SDValue() [2/2]

llvm::SDValue::SDValue ( SDNode node,
unsigned  resno 
)
inline

Definition at line 1030 of file SelectionDAGNodes.h.

References assert().

Member Function Documentation

◆ dump()

void llvm::SDValue::dump ( ) const
inline

◆ dumpr()

void llvm::SDValue::dumpr ( ) const
inline

◆ getConstantOperandVal()

uint64_t llvm::SDValue::getConstantOperandVal ( unsigned  i) const
inline

◆ getDebugLoc()

const DebugLoc & llvm::SDValue::getDebugLoc ( ) const
inline

Definition at line 1088 of file SelectionDAGNodes.h.

References llvm::SDNode::getDebugLoc().

Referenced by countOperands(), and findUser().

◆ getMachineOpcode()

unsigned llvm::SDValue::getMachineOpcode ( ) const
inline

◆ getNode()

SDNode* llvm::SDValue::getNode ( ) const
inline

get the SDNode which holds the desired result

Definition at line 137 of file SelectionDAGNodes.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), AddGlue(), addStackMapLiveVars(), llvm::AMDGPUTargetLowering::addTokenForArgument(), llvm::analyzeArguments(), AnalyzeReturnValues(), BuildExactSDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), buildVector(), calculateByteProvider(), CalculateTailCallArgDest(), CallingConvSupported(), canChangeToInt(), canClobberPhysRegDefs(), canEnableCoalescing(), canFoldInAddressingMode(), canReduceVMulWidth(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), ChangeVSETULTtoVSETULE(), llvm::checkForCycles(), checkForCyclesHelper(), CheckForLiveRegDef(), CheckForMaskedLoad(), checkHighLaneIndex(), checkV64LaneV128(), checkValueWidth(), ChooseConstraint(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndnp(), combineANDXORWithAllOnesIntoANDNP(), CombineBaseUpdate(), combineBitcastForMaskedOp(), combineBVOfVecSExt(), combineConcatVectorOfExtracts(), combineExtractSubvector(), combineExtractVectorElt(), combineFMADDSUB(), combineFneg(), combineGatherScatter(), combineIncDecVector(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineMaskedLoadConstantMask(), combineMaskedStore(), combineMinNumMaxNum(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineSetCCAtomicArith(), combineShuffleOfScalars(), combineShuffleOfSplat(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineTestM(), combineToExtendCMOV(), combineTruncatedArithmetic(), combineVectorPack(), combineVectorShiftImm(), CombineVLDDUP(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::SelectionDAG::computeKnownBits(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), ConvertSelectToConcatVector(), countOperands(), createBSWAPShuffleMask(), createGPRPairNode(), llvm::createMSP430ISelDag(), createVirtualRegs(), detectUSatPattern(), detectZextAbsDiff(), distributeOpThroughSelect(), DumpNodesr(), dumpr(), EltsFromConsecutiveLoads(), emitCmp(), emitConjunctionDisjunctionTreeRec(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithChainAndGlue(), EmitKTEST(), emitRemovedIntrinsicError(), EmitVectorComparison(), ExpandBVWithShuffles(), expandf64Toi32(), llvm::TargetLowering::expandMUL_LOHI(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), findBaseOffset(), FindBFIToCombineWith(), findConsecutiveLoad(), findUnwindDestinations(), findUser(), foldBitcastedFPLogic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToScale(), foldVectorXorShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getAArch64Cmp(), getAbsolute(), getAL(), getARClassRegisterMask(), getAsCarry(), getAsNonOpaqueConstant(), getAVX2GatherNode(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), getCCResult(), getConstantValue(), getContiguousRangeOfSetBits(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::DAGTypeLegalizer::getDAG(), llvm::SelectionDAG::GetDemandedBits(), getDivRemArgList(), getDUPLANEOp(), getEstimate(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), getGeneralPermuteNode(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::DenseMapInfo< SDValue >::getHashValue(), getInputChainForNode(), getIntOperandFromRegisterString(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getMad64_32(), getMemCmpLoad(), llvm::SelectionDAG::getMemcpy(), getMemcpyLoadsAndStores(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMemsetStores(), getMOVL(), GetNegatedExpression(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAGBuilder::getNonRegisterValue(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getPowerOf2Factor(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), getPromotedVectorElementType(), GetPromotionOpcode(), getPSHUFShuffleMask(), getPTXCmpMode(), llvm::AVRTargetLowering::getSetCCResultType(), getShuffleScalarElt(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), getStrictFPOpcodeAction(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetVShiftByConstNode(), getUnderlyingArgReg(), getUniformBase(), getUsefulBits(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::getValueImpl(), GetVBR(), getVCmpInst(), getVectorCompareInfo(), getVShiftImm(), getZeroVector(), hasNormalLoadOperand(), hasOnlySelectUsers(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), insertDAGNode(), isADDADDMUL(), isAddSubSExt(), isAddSubZExt(), isBitfieldExtractOp(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBLACompatibleAddress(), isBoolSGPR(), isBSwapHWordElement(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), isCalleeLoad(), isConsecutiveLSLoc(), isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isContractable(), isDivRemLibcallAvailable(), isExpandWithZeros(), isExtendedBUILD_VECTOR(), isFloatingPointZero(), isFMulNegTwo(), isFusableLoadOpStorePattern(), llvm::TargetLowering::isGAPlusOffset(), isHorizontalBinOp(), isInt32Immediate(), isInt64Immediate(), isIntImmediate(), llvm::isIntS16Immediate(), isLegalMaskCompare(), llvm::SelectionDAGISel::IsLegalToFold(), isMemOPCandidate(), isNaturalMemoryOperand(), isNegatibleForFree(), isNullFPScalarOrVectorConst(), isOpcodeHandled(), isOpcWithIntImmediate(), llvm::SDNode::isOperandOf(), isPerfectIncrement(), IsPredicateKnownToFail(), isPreferredADD(), isSaturatingConditional(), isScaledConstantInRange(), isSETCCorConvertedSETCC(), isSeveralBitsExtractOpFromShr(), isShuffleFoldableLoad(), IsSingleInstrConstant(), isSlicingProfitable(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isTypePromotionOfi1ZeroUpBits(), isValidIndexedLoad(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isVSplat(), isWordAligned(), isWorthFoldingADDlow(), isWorthFoldingSHL(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), lower1BitVectorShuffle(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), lowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundle(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORSvXi1(), lowerCTPOP32BitElements(), lowerDSPIntr(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), LowerFNEGorFABS(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerFPOWI(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), LowerIntVSETCC_AVX512(), LowerLOAD(), LowerMGATHER(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperationWrapper(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShift(), llvm::MSP430TargetLowering::LowerShifts(), lowerStatepointMetaArgs(), LowerSTORE(), LowerTruncateVecI1(), LowerTruncatingStore(), LowerVAARG(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZeroTest(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerXALUO(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), maskMatters(), matchBinaryPredicate(), matchBinOpReduction(), matchRotateSub(), matchVectorShuffleAsBlend(), materializeVectorConstant(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(), mayTailCallThisCC(), moveBelowOrigChain(), narrowIfNeeded(), NewSDValueDbgMsg(), NormalizeBuildVector(), llvm::SDNodeIterator::operator*(), parsePhysicalReg(), Passv64i1ArgInRegs(), peekThroughBitcast(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddSubLongCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformInsertEltCombine(), performIntegerAbsCombine(), performIntToFpCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), performNEONPostLDSTCombine(), performORCombine(), PerformORCombine(), PerformORCombineToSMULWBT(), performPostLD1Combine(), PerformSTORECombine(), PerformSUBCombine(), PerformUMLALCombine(), PerformVDIVCombine(), PerformVDUPCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performXORCombine(), performXorCombine(), pickOpcodeForVT(), PrepareCall(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), recoverFramePointer(), RemoveUnusedGlue(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), reportFastISelFailure(), reservePreviousStackSlotForValue(), resolveBuildVector(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::DAGTypeLegalizer::run(), llvm::SelectionDAG::salvageDebugInfo(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(), llvm::HexagonDAGToDAGISel::SelectZeroExtend(), llvm::SelectionDAG::setRoot(), setTargetShuffleZeroElements(), llvm::SelectionDAGBuilder::setUnusedArgValue(), llvm::SelectionDAGBuilder::setValue(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), spillIncomingStatepointValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), stripExtractLoElt(), llvm::SelectionDAG::transferDbgValues(), TranslateX86CC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineLongOpWithDup(), tryFoldToZero(), llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(), tryLowerToSLI(), tryToElideArgumentCopy(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), useSinCos(), Widen(), WinDBZCheckDenominator(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getNumOperands()

unsigned llvm::SDValue::getNumOperands ( ) const
inline

Definition at line 1048 of file SelectionDAGNodes.h.

References llvm::SDNode::getNumOperands().

Referenced by buildFromShuffleMostly(), buildVector(), CallingConvSupported(), CheckChildInteger(), CheckChildSame(), CheckChildType(), combineShuffleOfConcatUndef(), combineShuffleOfSplat(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), llvm::InstrEmitter::EmitDbgValue(), emitIntrinsicWithChainAndGlue(), emitIntrinsicWithGlue(), ExtendToType(), findBaseOffset(), generateEquivalentSub(), llvm::SelectionDAG::getNode(), getZeroVector(), isBSwapHWordElement(), isCalleeLoad(), isExpandWithZeros(), isFusableLoadOpStorePattern(), isScalarToVector(), isTruncateOf(), isXor1OfSetCC(), LowerAVXCONCAT_VECTORS(), LowerBUILD_VECTORAsVariablePermute(), llvm::NVPTXTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), LowerVECTOR_SHUFFLE(), matchBinaryPredicate(), matchUnaryPredicate(), mayTailCallThisCC(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), partitionShuffleOfConcats(), PerformVECTOR_SHUFFLECombine(), PrepareCall(), recoverFramePointer(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::TargetLowering::ShrinkDemandedOp(), and simplifyDivRem().

◆ getOpcode()

unsigned llvm::SDValue::getOpcode ( ) const
inline

Definition at line 1040 of file SelectionDAGNodes.h.

References llvm::SDNode::getOpcode().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), buildFromShuffleMostly(), buildScalarToVector(), buildVector(), calculateByteProvider(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canFoldInAddressingMode(), canReduceVMulWidth(), checkBoolTestAndOrSetCCCombine(), checkBoolTestSetCCCombine(), checkHighLaneIndex(), checkV64LaneV128(), combineAddOrSubToADCOrSBB(), combineAnd(), combineANDXORWithAllOnesIntoANDNP(), combineBasicSADPattern(), combineBitcast(), combineBitcastForMaskedOp(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineExtractVectorElt(), combineFAndFNotToFAndn(), combineFneg(), combineGatherScatter(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMaskedStore(), combineMinNumMaxNum(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfSplat(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineTruncate(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineVectorShiftImm(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SelectionDAG::computeOverflowKind(), computeZeroableShuffleElements(), ConstantAddressBlock(), convertBuildVectorCastElt(), convertIntLogicToFPLogic(), ConvertSelectToConcatVector(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::createARCISelDag(), createBSWAPShuffleMask(), createFPCmp(), llvm::createMSP430ISelDag(), llvm::createXCoreISelDag(), detectAVGPattern(), detectUSatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), EmitCMP(), emitComparison(), emitConditionalComparison(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), emitRemovedIntrinsicError(), expandDisp(), ExtendToType(), ExtendUsesToFormExtLoad(), extractSubVector(), findBaseOffset(), FindBFIToCombineWith(), findEXTRHalf(), findUser(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), getAArch64XALUOOp(), getAbsolute(), getARMIndexedAddressParts(), getAsCarry(), getAsNonOpaqueConstant(), llvm::MemSDNode::getBasePtr(), getBuildPairElt(), getCmp(), getConstantValue(), getContiguousRangeOfSetBits(), llvm::SelectionDAGBuilder::getControlRoot(), llvm::SelectionDAG::GetDemandedBits(), getDivRem8(), getDUPLANEOp(), getExtendTypeForNode(), getFauxShuffleMask(), GetFPLibCall(), getFPTernOp(), getGeneralPermuteNode(), getInputChainForNode(), getMad64_32(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::LSBaseSDNode::getOffset(), getPowerOf2Factor(), getPSHUFShuffleMask(), getReductionSDNode(), getScalarMaskingNode(), getScalarValueForVectorElement(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftTypeForNode(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), getSplatConstantFP(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleMask(), getTargetVShiftNode(), getUnderlyingArgReg(), getVCmpInst(), getVectorCompareInfo(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), getVShiftImm(), getZeroVector(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insert1BitVector(), insertDAGNode(), isAbsolute(), isADDADDMUL(), isAddSub(), isAndOrOfSetCCs(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isBitwiseNot(), isBoolSGPR(), isBSwapHWordElement(), isCalleeLoad(), isCanonicalized(), isClampZeroToOne(), llvm::AtomicSDNode::isCompareAndSwap(), isConditionalZeroOrAllOnes(), isConsecutiveLSLoc(), llvm::BuildVectorSDNode::isConstant(), isConstantOrConstantVector(), isConstOrDemandedConstSplat(), isContractable(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isDispSafeForFrameIndex(), isEssentiallyExtractSubvector(), isExpandWithZeros(), llvm::TargetLowering::isExtendedTrueVal(), isExtractHiElt(), isFloatingPointZero(), isFMAddSub(), isFMulNegTwo(), isFNEG(), isFrameIndexOp(), isFunctionGlobalAddress(), isFusableLoadOpStorePattern(), isHorizontalBinOp(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLegalMaskCompare(), isMemOPCandidate(), isMemSrcFromConstant(), IsMulWideOperandDemotable(), isNegatibleForFree(), isOpcodeHandled(), isOpcWithIntImmediate(), isOverflowIntrOpRes(), isPerfectIncrement(), isPreferredADD(), isSaturatingConditional(), isScaledConstantInRange(), isSetCC(), isSETCCorConvertedSETCC(), isSetCCOrZExtSetCC(), isSExtFree(), isSHL16(), IsSingleInstrConstant(), isSlicingProfitable(), isSRA16(), isSRL16(), isStackPtrRelative(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isTypePromotionOfi1ZeroUpBits(), isValidIndexedLoad(), isVShiftRImm(), isWordAligned(), isWorthFoldingADDlow(), isWorthFoldingSHL(), isX86LogicalCmp(), isXor1OfSetCC(), llvm::XCoreTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), LookThroughSetCC(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerAndToBT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAVXExtend(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTTZ(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerFABSorFNEG(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), llvm::HexagonTargetLowering::LowerINLINEASM(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerIntVSETCC_AVX512(), LowerMUL_LOHI(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::MipsSETargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerOperation(), llvm::ARCTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerOperation(), llvm::MSP430TargetLowering::LowerOperation(), llvm::AVRTargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::AMDGPUTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::AArch64TargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::MipsTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperation(), llvm::PPCTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerRotate(), LowerScalarImmediateShift(), LowerScalarVariableShift(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorCTLZ_AVX512CDI(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), lowerVectorShuffleAsTruncBroadcast(), LowerVSETCC(), LowerXALUO(), LowerXOR(), maskMatters(), matchBinaryPredicate(), matchBinOpReduction(), MatchingStackOffset(), matchRotateSub(), matchUnaryPredicate(), mayTailCallThisCC(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowIfNeeded(), NormalizeBuildVector(), optimizeLogicalImm(), peekThroughBitcast(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::AMDGPUTargetLowering::performCtlz_CttzCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performIntegerAbsCombine(), performMADD_MSUBCombine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSHLCombine(), PerformSHLSimplify(), performSRLCombine(), PerformVCVTCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), performVSELECTCombine(), performVSelectCombine(), pickOpcodeForVT(), PrepareCall(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReorganizeVector(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAddrFI(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectSHL(), setTargetShuffleZeroElements(), llvm::X86TargetLowering::shouldReduceLoadWidth(), shouldUseLA(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleMask(), simplifyShuffleOperandRecursively(), stripBitcast(), stripExtractLoElt(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), tryBuildVectorByteMask(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineToBSL(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryLowerToSLI(), tryToElideArgumentCopy(), useSinCos(), Widen(), WidenMaskArithmetic(), willShiftRightEliminate(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getOperand()

const SDValue & llvm::SDValue::getOperand ( unsigned  i) const
inline

Definition at line 1052 of file SelectionDAGNodes.h.

References llvm::SDNode::getOperand().

Referenced by AddCombineTo64BitSMLAL16(), AddCombineVUZPToVPADDL(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), buildVector(), calculateByteProvider(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canLowerToLDG(), canReduceVMulWidth(), CheckAndImm(), checkBoolTestSetCCCombine(), CheckChildInteger(), CheckChildSame(), CheckChildType(), checkHighLaneIndex(), CheckOrImm(), checkV64LaneV128(), combineAddOrSubToADCOrSBB(), combineAnd(), combineANDXORWithAllOnesIntoANDNP(), combineBasicSADPattern(), combineBitcast(), combineBitcastForMaskedOp(), combineBitcastvxi1(), combineBVOfConsecutiveLoads(), combineBVOfVecSExt(), combineCarryThroughADD(), combineCMov(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineFAndFNotToFAndn(), combineFneg(), combineGatherScatter(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineMaskedStore(), combineMinNumMaxNum(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplat(), combineSignExtendInReg(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineTruncate(), combineTruncatedArithmetic(), combineTruncationShuffle(), combineVectorShiftImm(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), computeZeroableShuffleElements(), ConstantAddressBlock(), convertBuildVectorCastElt(), ConvertI1VectorToInteger(), convertIntLogicToFPLogic(), ConvertSelectToConcatVector(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::createARCISelDag(), createBSWAPShuffleMask(), createCMovFP(), createFPCmp(), llvm::createMSP430ISelDag(), createPSADBW(), llvm::createXCoreISelDag(), detectAVGPattern(), detectUSatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), distributeOpThroughSelect(), emitComparison(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithChainAndGlue(), emitIntrinsicWithGlue(), EmitKTEST(), emitRemovedIntrinsicError(), EmitVectorComparison(), expandDisp(), expandf64Toi32(), expandV4F32ToV2F64(), ExtendToType(), ExtendUsesToFormExtLoad(), findBaseOffset(), FindBFIToCombineWith(), findEXTRHalf(), findUser(), foldBitcastedFPLogic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldShuffleOfHorizOp(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64XALUOOp(), getAbsolute(), getAsCarry(), getAsNonOpaqueConstant(), llvm::MemSDNode::getBasePtr(), llvm::AtomicSDNode::getBasePtr(), llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::MaskedLoadStoreSDNode::getBasePtr(), llvm::MaskedGatherScatterSDNode::getBasePtr(), getBaseWithConstantOffset(), getBuildPairElt(), getCCResult(), llvm::MemSDNode::getChain(), llvm::SDNode::getConstantOperandVal(), getConstantValue(), getContiguousRangeOfSetBits(), llvm::SelectionDAG::GetDemandedBits(), getDivRem8(), getDivRemArgList(), getDUPLANEOp(), getExtendTypeForNode(), getFauxShuffleMask(), getFPTernOp(), getGeneralPermuteNode(), llvm::MaskedGatherScatterSDNode::getIndex(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getMad64_32(), llvm::MaskedLoadStoreSDNode::getMask(), llvm::MaskedGatherScatterSDNode::getMask(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), llvm::LSBaseSDNode::getOffset(), llvm::LoadSDNode::getOffset(), llvm::StoreSDNode::getOffset(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPowerOf2Factor(), getReductionSDNode(), getScalarValueForVectorElement(), getShuffleScalarElt(), getSplatConstantFP(), llvm::MaskedLoadSDNode::getSrc0(), getStrictFPOpcodeAction(), getTargetConstantBitsFromNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleMask(), getTargetVShiftNode(), getUnderlyingArgReg(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), llvm::AtomicSDNode::getVal(), getValidShiftAmountConstant(), llvm::StoreSDNode::getValue(), llvm::MaskedStoreSDNode::getValue(), llvm::MaskedGatherScatterSDNode::getValue(), getVCmpInst(), getVectorCompareInfo(), getVShiftImm(), getZeroVector(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), InferPointerInfo(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), insertDAGNode(), llvm::intCCToAVRCC(), isAbsolute(), isADDADDMUL(), isAddSub(), isAndOrOfSetCCs(), llvm::SelectionDAG::isBaseWithConstantOffset(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), llvm::isBitwiseNot(), isBoolSGPR(), isBSwapHWordElement(), isCalleeLoad(), isCanonicalized(), isClampZeroToOne(), isConstOrDemandedConstSplat(), isContractable(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isDispSafeForFrameIndex(), isEssentiallyExtractSubvector(), isExpandWithZeros(), llvm::TargetLowering::isExtendedTrueVal(), isExtractHiElt(), isFloatingPointZero(), isFMAddSub(), isFMulNegTwo(), isFNEG(), isFrameIndexOp(), isFusableLoadOpStorePattern(), isHorizontalBinOp(), isIntrinsicWithCC(), isIntrinsicWithCCAndChain(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), isLegalMaskCompare(), isMemOPCandidate(), isMemSrcFromConstant(), IsMulWideOperandDemotable(), isNegatibleForFree(), isOpcodeHandled(), isOpcWithIntImmediate(), isPerfectIncrement(), isPreferredADD(), llvm::ARMTargetLowering::isReadOnly(), isS16(), isSaturatingConditional(), isScalarToVector(), isScaledConstantInRange(), isSetCC(), isSETCCorConvertedSETCC(), isSeveralBitsExtractOpFromShr(), isSExtFree(), isSHL16(), isSimpleShift(), IsSingleInstrConstant(), isSlicingProfitable(), isSRA16(), isSRL16(), isStackPtrRelative(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isTypePromotionOfi1ZeroUpBits(), isVShiftRImm(), isWordAligned(), isWorthFoldingADDlow(), isWorthFoldingSHL(), isXor1OfSetCC(), LookThroughSetCC(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerABS(), LowerADD_SUB(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerAVXCONCAT_VECTORS(), llvm::SparcTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBoolVSETCC_AVX512(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), LowerCMP_SWAP(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerEH_SJLJ_LONGJMP(), llvm::SparcTargetLowering::LowerEH_SJLJ_SETJMP(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), llvm::SparcTargetLowering::LowerF128Op(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerINLINEASM(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerINSERT_VECTOR_ELT(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), LowerIntVSETCC_AVX512(), LowerMGATHER(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), LowerTruncateVecI1(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), llvm::SparcTargetLowering::LowerUINT_TO_FP(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), lowerVectorShuffle(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsTruncBroadcast(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), lowerX86CmpEqZeroToCtlzSrl(), LowerXOR(), LowerZERO_EXTEND(), MarkEHGuard(), MarkEHRegistrationNode(), maskMatters(), matchBinaryPredicate(), matchBinOpReduction(), MatchingStackOffset(), matchRotateSub(), matchUnaryPredicate(), mayTailCallThisCC(), minMaxOpcToMin3Max3Opc(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowIfNeeded(), llvm::X86TargetLowering::needsFixedCatchObjects(), NegateCC(), NormalizeBuildVector(), optimizeLogicalImm(), partitionShuffleOfConcats(), peekThroughBitcast(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::AMDGPUTargetLowering::performCtlz_CttzCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performIntegerAbsCombine(), performORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSHLCombine(), PerformSHLSimplify(), performSRLCombine(), PerformSTORECombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performVSELECTCombine(), performVSelectCombine(), pickOpcodeForVT(), PrepareCall(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), ReorganizeVector(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), resolveBuildVector(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectSHL(), setTargetShuffleZeroElements(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleMask(), stripBitcast(), stripExtractLoElt(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), tryToElideArgumentCopy(), useSinCos(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), Widen(), willShiftRightEliminate(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ getResNo()

unsigned llvm::SDValue::getResNo ( ) const
inline

get the index which selects a specific result in the SDNode

Definition at line 134 of file SelectionDAGNodes.h.

Referenced by llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), checkBoolTestSetCCCombine(), CheckForPhysRegDependency(), combineAddOrSubToADCOrSBB(), CombineBaseUpdate(), combineExtractVectorElt(), CombineVLDDUP(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::SelectionDAG::computeOverflowKind(), countOperands(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), ExtendUsesToFormExtLoad(), findUnwindDestinations(), foldMaskAndShiftToScale(), getAsCarry(), getBuildPairElt(), getCmp(), getContiguousRangeOfSetBits(), llvm::RegsForValue::getCopyToRegs(), getDivRem8(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), getUnderlyingArgReg(), hasOnlySelectUsers(), isFloatingPointZero(), isFusableLoadOpStorePattern(), isOverflowIntrOpRes(), isX86LogicalCmp(), isXor1OfSetCC(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVMOVDRRCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SelectionDAG::salvageDebugInfo(), llvm::ResourcePriorityQueue::scheduledNode(), simplifyDivRem(), and llvm::SelectionDAG::transferDbgValues().

◆ getScalarValueSizeInBits()

unsigned llvm::SDValue::getScalarValueSizeInBits ( ) const
inline

◆ getSimpleValueType()

MVT llvm::SDValue::getSimpleValueType ( ) const
inline

Return the simple ValueType of the referenced return value.

Definition at line 168 of file SelectionDAGNodes.h.

References llvm::EVT::getSimpleVT().

Referenced by llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), calculateByteProvider(), canFoldInAddressingMode(), ChangeVSETULTtoVSETULE(), combineAcrossLanesIntrinsic(), combineBasicSADPattern(), combineBitcastForMaskedOp(), combineInsertSubvector(), combineLoopMAddPattern(), combineRedundantDWordShuffle(), combineTargetShuffle(), combineVSZext(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), ConvertI1VectorToInteger(), countOperands(), ExpandHorizontalBinOp(), ExtendToType(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), getAVX2GatherNode(), getCopyFromPartsVector(), getFauxShuffleMask(), getGatherNode(), getMaskNode(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getPrefetchNode(), getPromotedVectorElementType(), getPSHUFShuffleMask(), getPTXCmpMode(), getReductionSDNode(), getScalarMaskingNode(), getScalarValueForVectorElement(), getScatterNode(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getStrictFPOpcodeAction(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), getVectorCompareInfo(), getVectorMaskingNode(), hasSingleUsesFromRoot(), insert1BitVector(), isAddSub(), isCalleeLoad(), llvm::TargetLowering::isExtendedTrueVal(), isFusableLoadOpStorePattern(), isHorizontalBinOp(), isStackPtrRelative(), isTruncWithZeroHighBitsInput(), isTypePromotionOfi1ZeroUpBits(), Lower256IntArith(), Lower256IntUnary(), Lower256IntVSETCC(), Lower512IntArith(), Lower512IntUnary(), LowerABS(), LowerADD_SUB(), LowerADJUST_TRAMPOLINE(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBoolVSETCC_AVX512(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), LowerBuildVectorv4x32(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerExtendedLoad(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFCOPYSIGN64(), LowerFGETSIGN(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerHorizontalByteSum(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerIntVSETCC_AVX512(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSETCCE(), LowerShift(), LowerShiftParts(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16F32VectorShuffle(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV32I16VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV64I8VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I16VectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPBitmath(), LowerVectorCTPOPInRegLUT(), LowerVectorIntUnary(), lowerVectorShuffle(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsInsertPS(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerZERO_EXTEND(), LowerZERO_EXTEND_AVX512(), matchVectorShuffleAsInsertPS(), materializeVectorConstant(), llvm::R600TargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PrepareCall(), recoverFramePointer(), setTargetShuffleZeroElements(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), splitAndLowerVectorShuffle(), tryExtendDUPToExtractHigh(), and useSinCos().

◆ getValue()

SDValue llvm::SDValue::getValue ( unsigned  R) const
inline

Definition at line 157 of file SelectionDAGNodes.h.

References isOperandOf(), and N.

Referenced by AddCombineTo64bitMLAL(), addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::X86TargetLowering::BuildFILD(), BuildVectorFromScalar(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), checkVSELConstraints(), combineLoad(), combineMaskedLoad(), combineMaskedLoadConstantMask(), combineSetCCAtomicArith(), combineShuffleOfSplat(), combineSIntToFP(), ConvertSelectToConcatVector(), llvm::createR600ISelDag(), createVirtualRegs(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitRemovedIntrinsicError(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EnsureStackAlignment(), Expand64BitShift(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendUsesToFormExtLoad(), findUser(), foldBitcastedFPLogic(), FoldIntToFPToInt(), generateEquivalentSub(), getAArch64XALUOOp(), getAbsolute(), getARClassRegisterMask(), getAsCarry(), getBoundedStrlen(), getContiguousRangeOfSetBits(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), getDivRem8(), getDivRemArgList(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getExtendedControlRegister(), getFPBinOp(), GetFPLibCall(), getFPTernOp(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMOVL(), getMul24(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPromotedVectorElementType(), GetPromotionOpcode(), getReadPerformanceCounter(), getReadTimeStampCounter(), getStrictFPOpcodeAction(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), GetTLSADDR(), getUnderlyingArgReg(), getUniformBase(), getv64i1Argument(), GetVBR(), getVCmpInst(), getVectorCompareInfo(), hasOnlySelectUsers(), isADDADDMUL(), isCalleeLoad(), isDivRemLibcallAvailable(), isFusableLoadOpStorePattern(), isSlicingProfitable(), isStackPtrRelative(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundle(), llvm::TargetLowering::LowerCallTo(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), lowerFCOPYSIGN64(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerMGATHER(), LowerMLOAD(), LowerMUL_LOHI(), llvm::BPFTargetLowering::LowerOperation(), llvm::MipsTargetLowering::LowerOperationWrapper(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::X86TargetLowering::LowerOperationWrapper(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerSETCCE(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vXi32(), LowerVAARG(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVectorINT_TO_FP(), LowerVSETCC(), LowerXOR(), matchBinaryPredicate(), mayTailCallThisCC(), parsePhysicalReg(), Passv64i1ArgInRegs(), peekThroughBitcast(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformSETCCCombine(), PerformSTORECombine(), PerformVDUPCombine(), PerformVMOVRRDCombine(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), PrepareTailCall(), reduceMaskedLoadToScalarLoad(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::SelectionDAGISel::SelectCodeCommon(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), SkipExtensionForVMULL(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToElideArgumentCopy(), UnpackFromArgumentSlot(), useSinCos(), and llvm::SelectionDAGBuilder::visitJumpTable().

◆ getValueSizeInBits()

unsigned llvm::SDValue::getValueSizeInBits ( ) const
inline

Returns the size of the value in bits.

Definition at line 173 of file SelectionDAGNodes.h.

References llvm::EVT::getSizeInBits().

Referenced by llvm::X86TargetLowering::BuildFILD(), calculateByteProvider(), CalculateTailCallArgDest(), llvm::SelectionDAGISel::CheckAndMask(), CheckForMaskedLoad(), llvm::SelectionDAGISel::CheckOrMask(), combineAddOrSubToADCOrSBB(), combineBT(), combineHorizontalPredicateResult(), combineLoopSADPattern(), combineShiftLeft(), combineStore(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), ConvertI1VectorToInteger(), createBSWAPShuffleMask(), EltsFromConsecutiveLoads(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), foldBitcastedFPLogic(), foldShuffleOfHorizOp(), generateEquivalentSub(), GenerateTBL(), llvm::SelectionDAG::getAnyExtendVectorInReg(), getBitTestCondition(), getExpandedMinMaxOps(), getNextIntArgReg(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignExtendVectorInReg(), getStrictFPOpcodeAction(), llvm::SystemZTargetLowering::getTargetNodeName(), getVCmpInst(), llvm::SelectionDAG::getZeroExtendVectorInReg(), insertDAGNode(), isSimpleShift(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isWorthFoldingSHL(), LowerAndToBT(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), lowerFCOPYSIGN64(), lowerFP_TO_SINT_STORE(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), llvm::NVPTXTargetLowering::LowerReturn(), LowerScalarImmediateShift(), llvm::MipsTargetLowering::lowerSTORE(), lowerV8I16GeneralSingleInputVectorShuffle(), maskMatters(), MatchingStackOffset(), mayTailCallThisCC(), narrowExtractedVectorBinOp(), NormalizeBuildVector(), peekThroughBitcast(), performIntToFpCombine(), pickOpcodeForVT(), llvm::DAGTypeLegalizer::run(), selectI64Imm(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), useSinCos(), and VerifySDNode().

◆ getValueType()

EVT llvm::SDValue::getValueType ( ) const
inline

Return the ValueType of the referenced return value.

Definition at line 1044 of file SelectionDAGNodes.h.

References llvm::SDNode::getValueType().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), BuildExactSDIV(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), BuildIntrinsicOp(), buildPCRelGlobalAddress(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), buildVector(), BuildVectorFromScalar(), calculateByteProvider(), CallingConvSupported(), canChangeToInt(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canFoldInAddressingMode(), canReduceVMulWidth(), CheckForLiveRegDef(), CheckForMaskedLoad(), CheckType(), clampDynamicVectorIndex(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndMaskToShift(), CombineBaseUpdate(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineBVOfVecSExt(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFneg(), combineGatherScatter(), combineHorizontalPredicateResult(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfScalars(), combineShuffleOfSplat(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToExtendVectorInReg(), combineTruncate(), combineTruncateWithUSat(), combineUIntToFP(), combineVectorShiftImm(), combineVectorSignBitsTruncation(), combineVectorSizedSetCCEquality(), combineVectorTruncation(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), ConstantAddressBlock(), convertBuildVectorCastElt(), convertIntLogicToFPLogic(), ConvertSelectToConcatVector(), countOperands(), createBSWAPShuffleMask(), createCMovFP(), createFPCmp(), createLoadLR(), llvm::createMSP430ISelDag(), createPSADBW(), createStoreLR(), createVirtualRegs(), detectAVGPattern(), detectAVX512USatPattern(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), detectZextAbsDiff(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), emitCLC(), EmitCMP(), emitComparison(), emitConditionalComparison(), emitConjunctionDisjunctionTreeRec(), llvm::InstrEmitter::EmitDbgValue(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKTEST(), emitMemMem(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTruncSStore(), EmitVectorComparison(), EnsureStackAlignment(), ExpandBITCAST(), ExpandBVWithShuffles(), expandExp(), expandExp2(), expandf64Toi32(), llvm::TargetLowering::expandFP_TO_SINT(), expandLog(), expandLog10(), expandLog2(), expandPow(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandV4F32ToV2F64(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), findChainOperand(), findUnwindDestinations(), findUser(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToScale(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::SelectionDAG::getAnyExtendVectorInReg(), llvm::SelectionDAG::getAnyExtOrTrunc(), getAsCarry(), getAsNonOpaqueConstant(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), getAVX2GatherNode(), llvm::SelectionDAG::getBitcast(), getBitTestCondition(), llvm::SelectionDAG::getBoolExtOrTrunc(), getBoundedStrlen(), getCCResult(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::getCopyToReg(), llvm::DAGTypeLegalizer::getDAG(), llvm::SelectionDAG::GetDemandedBits(), getDivRem8(), getDivRemArgList(), getDUPLANEOp(), llvm::DOTGraphTraits< SelectionDAG * >::getEdgeAttributes(), getEstimate(), getEstimateRefinementSteps(), getExpandedMinMaxOps(), getExtendInVec(), getExtendTypeForNode(), getExtFactor(), llvm::SelectionDAG::getExtLoad(), getFauxShuffleMask(), llvm::SelectionDAG::getFPExtendOrRound(), GetFPLibCall(), getFPTernOp(), getFRAMEADDR(), getGatherNode(), getGeneralPermuteNode(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), getInputChainForNode(), getIntOperandFromRegisterString(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getLeftShift(), llvm::SelectionDAG::getLoad(), getMad64_32(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getMaskedStore(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getMemBasePlusOffset(), getMemCmpLoad(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMemsetStores(), getMemsetValue(), getMOVL(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getNumOperandsNoGlue(), llvm::MipsTargetLowering::getOpndList(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPromotedVectorElementType(), GetPromotionOpcode(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetCC(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getShiftAmountOperand(), getShuffleScalarElt(), llvm::SelectionDAG::getSignExtendVectorInReg(), llvm::SelectionDAG::getSplatBuildVector(), getSplatConstantFP(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::SelectionDAG::getStore(), getStrictFPOpcodeAction(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetShuffleMask(), getTOCEntry(), llvm::SelectionDAG::getTruncStore(), getUnderlyingArgReg(), getUniformBase(), llvm::SDUse::getValueType(), GetVBR(), getVCmpInst(), getVectorCompareInfo(), llvm::SelectionDAG::getVectorShuffle(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendVectorInReg(), getZeroVector(), llvm::SelectionDAG::getZExtOrTrunc(), HandleMergeInputChains(), llvm::X86TargetLowering::hasAndNotCompare(), hasOnlySelectUsers(), hasSingleUsesFromRoot(), haveEfficientBuildVectorPattern(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::TargetLowering::IncrementMemoryAddress(), insert128BitVector(), insert256BitVector(), insertDAGNode(), insertSubVector(), llvm::intCCToAVRCC(), IntCondCCodeToICC(), isADDADDMUL(), isBitfieldPositioningOp(), isBoolSGPR(), isBSwapHWordElement(), isCanonicalized(), isConditionalZeroOrAllOnes(), isConjunctionDisjunctionTree(), llvm::isConstOrConstSplat(), isConstOrDemandedConstSplat(), isContractable(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), isFNEG(), isFusableLoadOpStorePattern(), isHorizontalBinOp(), isI24(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), isLegalMaskCompare(), llvm::SelectionDAGISel::IsLegalToFold(), isMemOPCandidate(), IsMulWideOperandDemotable(), isNegatibleForFree(), isNegativeOne(), isNEONModifiedImm(), isOpcodeHandled(), isOpcWithIntImmediate(), isPerfectIncrement(), isPreferredADD(), llvm::ARMTargetLowering::isReadOnly(), isSaturatingConditional(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSmallObject(), llvm::ShuffleVectorSDNode::isSplat(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isVectorReductionOp(), isVShiftRImm(), isWordAligned(), isXor1OfSetCC(), llvm::XCoreTargetLowering::isZExtFree(), llvm::MSP430TargetLowering::isZExtFree(), llvm::AMDGPUTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::TargetLoweringBase::isZExtFree(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::SparcTargetLowering::LowerBITCAST(), LowerBITCAST(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), LowerF128Store(), LowerF64Op(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerIncomingStatepointValue(), llvm::HexagonTargetLowering::LowerINLINEASM(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), lowerMasksToReg(), LowerMGATHER(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), LowerPREFETCH(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), lowerStatepointMetaArgs(), llvm::MipsTargetLowering::lowerSTORE(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), llvm::SparcTargetLowering::LowerUINT_TO_FP(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), lowerUnalignedIntStore(), LowerVAARG(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleToEXPAND(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerXOR(), llvm::SparcTargetLowering::makeHiLoPair(), llvm::TargetLowering::makeLibCall(), maskMatters(), matchBinaryPredicate(), matchBinOpReduction(), MatchingStackOffset(), matchRotateSub(), matchUnaryPredicate(), mayTailCallThisCC(), llvm::SelectionDAG::mutateStrictFPToFP(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowIfNeeded(), NarrowVector(), NegateCC(), NormalizeBuildVector(), llvm::AMDGPUTargetLowering::numBitsSigned(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), optimizeLogicalImm(), parsePhysicalReg(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), peekThroughBitcast(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), PerformIntrinsicCombine(), performNEONPostLDSTCombine(), performNVCASTCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), PerformSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), PerformSTORECombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVECTOR_SHUFFLECombine(), performVSelectCombine(), pickOpcodeForVT(), llvm::SITargetLowering::PostISelFolding(), PrepareCall(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), RemoveUnusedGlue(), ReorganizeVector(), ReplaceBITCASTResults(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), reportFastISelFailure(), resolveBuildVector(), llvm::DAGTypeLegalizer::run(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::HexagonDAGToDAGISel::SelectAnyInt(), llvm::HexagonDAGToDAGISel::SelectBitcast(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectZeroExtend(), llvm::SelectionDAG::setRoot(), setTargetShuffleZeroElements(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), simplifyI24(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleOperandRecursively(), llvm::TargetLowering::softenSetCCOperands(), spillIncomingStatepointValue(), splitStores(), splitStoreSplat(), llvm::SelectionDAG::SplitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), SplitVSETCC(), stripExtractLoElt(), stripModuloOnShift(), llvm::AArch64TargetLowering::targetShrinkDemandedConstant(), TranslateX86CC(), truncateVectorWithPACK(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), tryToElideArgumentCopy(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAGBuilder::UpdateSplitBlock(), useSinCos(), VerifySDNode(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenVector(), willShiftRightEliminate(), WinDBZCheckDenominator(), llvm::SparcTargetLowering::withTargetFlags(), XFormVExtractWithShuffleIntoLoad(), and zeroExtendToMatch().

◆ hasOneUse()

bool llvm::SDValue::hasOneUse ( ) const
inline

Return true if there is exactly one node using value ResNo of Node.

Definition at line 1084 of file SelectionDAGNodes.h.

References llvm::SDNode::hasNUsesOfValue().

Referenced by calculateByteProvider(), combineAddOrSubToADCOrSBB(), combineBitcast(), combineBitcastForMaskedOp(), combineExtractVectorElt(), combineFneg(), combineInsertSubvector(), combineMinNumMaxNum(), combineOr(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfSplat(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendCMOV(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesConstants(), combineZext(), ConvertSelectToConcatVector(), countOperands(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), ExtendUsesToFormExtLoad(), foldBitcastedFPLogic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), GeneratePerfectShuffle(), getAsNonOpaqueConstant(), getGeneralPermuteNode(), getInputChainForNode(), GetNegatedExpression(), getSplatConstantFP(), llvm::SystemZTargetLowering::getTargetNodeName(), isADDADDMUL(), isAndOrOfSetCCs(), isBitfieldPositioningOp(), isCalleeLoad(), isConjunctionDisjunctionTree(), isContractable(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), isFMulNegTwo(), isFusableLoadOpStorePattern(), isLegalMaskCompare(), isNegatibleForFree(), llvm::SelectionDAGISel::IsProfitableToFold(), isScaledConstantInRange(), isStackPtrRelative(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isValidIndexedLoad(), isWorthFoldingSHL(), isXor1OfSetCC(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::MSP430TargetLowering::LowerSETCC(), LowerVSETCC(), matchBinaryPredicate(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), peekThroughBitcast(), peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performIntToFpCombine(), performMADD_MSUBCombine(), PerformORCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformVDUPCombine(), reachesChainWithoutSideEffects(), replaceZeroVectorStore(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and XFormVExtractWithShuffleIntoLoad().

◆ isMachineOpcode()

bool llvm::SDValue::isMachineOpcode ( ) const
inline

◆ isOperandOf()

bool SDValue::isOperandOf ( const SDNode N) const

Return true if this node is an operand of N.

isOperand - Return true if this node is an operand of N.

Definition at line 7745 of file SelectionDAG.cpp.

References llvm::SDNode::op_values().

Referenced by isCalleeLoad().

◆ isTargetMemoryOpcode()

bool llvm::SDValue::isTargetMemoryOpcode ( ) const
inline

Definition at line 1064 of file SelectionDAGNodes.h.

References llvm::SDNode::isTargetMemoryOpcode().

◆ isTargetOpcode()

bool llvm::SDValue::isTargetOpcode ( ) const
inline

Definition at line 1060 of file SelectionDAGNodes.h.

References llvm::SDNode::isTargetOpcode().

◆ isUndef()

bool llvm::SDValue::isUndef ( ) const
inline

Definition at line 1076 of file SelectionDAGNodes.h.

References llvm::SDNode::isUndef().

Referenced by buildMergeScalars(), buildScalarToVector(), buildVector(), calculateByteProvider(), canFoldInAddressingMode(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineInsertSubvector(), combineMaskedLoad(), combineMaskedLoadConstantMask(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplat(), combineTargetShuffle(), computeZeroableShuffleElements(), ConstantAddressBlock(), convertBuildVectorCastElt(), ConvertI1VectorToInteger(), ConvertSelectToConcatVector(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), ExtendToType(), findBaseOffset(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldShuffleOfHorizOp(), fp16SrcZerosHighBits(), generateEquivalentSub(), GeneratePerfectShuffle(), llvm::PPC::get_VSPLTI_elt(), getAsNonOpaqueConstant(), getAVX2GatherNode(), getFauxShuffleMask(), getGatherNode(), getGeneralPermuteNode(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetValue(), llvm::SelectionDAG::getNode(), getOneTrueElt(), getScalarMaskingNode(), llvm::BuildVectorSDNode::getSplatValue(), getStrictFPOpcodeAction(), getTargetConstantBitsFromNode(), getVCmpInst(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insert1BitVector(), insertSubVector(), isAddSub(), isBSwapHWordElement(), llvm::ISD::isBuildVectorAllOnes(), isClampZeroToOne(), isConstantOrConstantVector(), llvm::BuildVectorSDNode::isConstantSplat(), isHorizontalBinOp(), isScalarToVector(), IsSingleInstrConstant(), isSplatZeroExtended(), isStackPtrRelative(), isTruncateOf(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), llvm::PPC::isXXSLDWIShuffleMask(), joinDwords(), lower1BitVectorShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), LowerScalarVariableShift(), LowerToHorizontalOp(), lowerV16F32VectorShuffle(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV32I16VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVectorShuffle(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsSplitOrBlend(), lowerVectorShuffleByMerging128BitLanes(), lowerVectorShuffleWithPERMV(), matchVectorShuffleAsBlend(), matchVectorShuffleWithPACK(), narrowExtractedVectorLoad(), NormalizeBuildVector(), partitionShuffleOfConcats(), peekThroughBitcast(), PerformARMBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), PerformVECTOR_SHUFFLECombine(), PrepareCall(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::R600TargetLowering::ReplaceNodeResults(), setTargetShuffleZeroElements(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), simplifyShuffleMask(), stripExtractLoElt(), tryBuildVectorByteMask(), tryBuildVectorShuffle(), tryFoldToZero(), and useSinCos().

◆ operator bool()

llvm::SDValue::operator bool ( ) const
inlineexplicit

Definition at line 153 of file SelectionDAGNodes.h.

◆ operator!=()

bool llvm::SDValue::operator!= ( const SDValue O) const
inline

Definition at line 147 of file SelectionDAGNodes.h.

References llvm::operator==().

◆ operator->()

SDNode* llvm::SDValue::operator-> ( ) const
inline

Definition at line 142 of file SelectionDAGNodes.h.

◆ operator<()

bool llvm::SDValue::operator< ( const SDValue O) const
inline

Definition at line 150 of file SelectionDAGNodes.h.

◆ operator==()

bool llvm::SDValue::operator== ( const SDValue O) const
inline

Definition at line 144 of file SelectionDAGNodes.h.

Referenced by llvm::SDNodeIterator::operator!=().

◆ reachesChainWithoutSideEffects()

bool SDValue::reachesChainWithoutSideEffects ( SDValue  Dest,
unsigned  Depth = 2 
) const

Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.

reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.

Note that we only need to examine chains when we're searching for side-effects; SelectionDAG requires that all side-effects are represented by chains, even if another operand would force a specific ordering. This constraint is necessary to allow transformations like splitting loads.

Definition at line 7769 of file SelectionDAG.cpp.

References llvm::all_of(), llvm::SDNode::getOpcode(), hasOneUse(), llvm::is_contained(), reachesChainWithoutSideEffects(), and llvm::ISD::TokenFactor.

Referenced by llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), getStrictFPOpcodeAction(), and reachesChainWithoutSideEffects().

◆ setNode()

void llvm::SDValue::setNode ( SDNode N)
inline

set the SDNode

Definition at line 140 of file SelectionDAGNodes.h.

References N.

Referenced by dumpr(), PrepareCall(), and llvm::DAGTypeLegalizer::run().

◆ use_empty()

bool llvm::SDValue::use_empty ( ) const
inline

Return true if there are no nodes using value ResNo of Node.

Definition at line 1080 of file SelectionDAGNodes.h.

References llvm::SDNode::hasAnyUseOfValue().

Referenced by combineADC(), combineMinNumMaxNum(), getContiguousRangeOfSetBits(), isFusableLoadOpStorePattern(), and llvm::DAGTypeLegalizer::run().

Friends And Related Function Documentation

◆ DenseMapInfo< SDValue >

friend struct DenseMapInfo< SDValue >
friend

Definition at line 124 of file SelectionDAGNodes.h.


The documentation for this class was generated from the following files: