62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
110 assert((LocVT == MVT::f32 || LocVT == MVT::f128
112 "Can't handle non-64 bits locations");
115 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
120 if (LocVT == MVT::i64 &&
Offset < 6*8)
123 else if (LocVT == MVT::f64 &&
Offset < 16*8)
126 else if (LocVT == MVT::f32 &&
Offset < 16*8)
129 else if (LocVT == MVT::f128 &&
Offset < 16*8)
147 if (LocVT == MVT::f32)
163 if (LocVT == MVT::f32 &&
Offset < 16*8) {
170 if (LocVT == MVT::i32 &&
Offset < 6*8) {
172 unsigned Reg = SP::I0 +
Offset/8;
222#include "SparcGenCallingConv.inc"
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
230 if (Reg >= SP::I0 && Reg <= SP::I7)
231 return Reg - SP::I0 + SP::O0;
279 for (
unsigned i = 0, realRVLocIdx = 0;
281 ++i, ++realRVLocIdx) {
285 SDValue Arg = OutVals[realRVLocIdx];
313 unsigned RetAddrOffset = 8;
364 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
393 if (i+1 < RVLocs.
size() && RVLocs[i+1].getLocReg() == VA.
getLocReg()) {
449 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
452 if (Ins[InIdx].Flags.isSRet()) {
483 &SP::IntRegsRegClass);
501 else if (VA.
getLocVT() != MVT::i32) {
560 }
else if (VA.
getValVT() == MVT::f128) {
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
588 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
590 if (NumAllocated == 6)
594 ArgOffset = 68+4*NumAllocated;
600 std::vector<SDValue> OutChains;
602 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
616 if (!OutChains.empty()) {
617 OutChains.push_back(Chain);
639 const unsigned ArgArea = 128;
641 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
718 for (; ArgOffset < 6*8; ArgOffset += 8) {
728 if (!OutChains.
empty())
742 return TRI->isReservedReg(MF, r);
746 return TRI->isReservedReg(MF, r);
754 F, (
"SPARC doesn't support"
755 " function calls if any of the argument registers is reserved.")});
769 return Call->hasFnAttr(Attribute::ReturnsTwice);
773 CalleeFn = dyn_cast<Function>(
G->getGlobal());
775 dyn_cast<ExternalSymbolSDNode>(Callee)) {
778 const char *CalleeName =
E->getSymbol();
779 CalleeFn = M->getFunction(CalleeName);
792 auto &Outs = CLI.
Outs;
796 if (Caller.getFnAttribute(
"disable-tail-calls").getValueAsString() ==
"true")
802 unsigned StackSizeLimit = Subtarget->
is64Bit() ? 48 : 0;
808 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
813 for (
auto &Arg : Outs)
814 if (Arg.Flags.isByVal())
849 ArgsSize = (ArgsSize+7) & ~7;
855 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
857 if (!Flags.isByVal())
861 unsigned Size = Flags.getByValSize();
862 Align Alignment = Flags.getNonZeroByValAlign();
869 Chain = DAG.
getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
882 assert(!isTailCall || ArgsSize == 0);
891 bool hasStructRetAttr =
false;
892 unsigned SRetArgSize = 0;
894 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.
size();
898 SDValue Arg = OutVals[realArgIdx];
903 if (Flags.isByVal()) {
904 Arg = ByValArgs[byvalArgIdx++];
928 if (Flags.isSRet()) {
940 hasStructRetAttr =
true;
942 assert(Outs[realArgIdx].OrigArgIndex == 0);
1037 if (!MemOpChains.
empty())
1045 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1046 Register Reg = RegsToPass[i].first;
1049 Chain = DAG.
getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InGlue);
1070 if (hasStructRetAttr)
1072 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1073 Register Reg = RegsToPass[i].first;
1083 ?
TRI->getRTCallPreservedMask(CallConv)
1089 assert(Mask &&
"Missing call preserved mask for calling convention");
1114 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1115 assert(RVLocs[i].isRegLoc() &&
"Can only return in registers!");
1116 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1119 Chain, dl,
toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InGlue);
1120 Chain =
Lo.getValue(1);
1121 InGlue =
Lo.getValue(2);
1125 Chain, dl,
toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InGlue);
1126 Chain =
Hi.getValue(1);
1127 InGlue =
Hi.getValue(2);
1134 RVLocs[i].getValVT(), InGlue)
1149 .
Case(
"i0", SP::I0).
Case(
"i1", SP::I1).
Case(
"i2", SP::I2).
Case(
"i3", SP::I3)
1150 .
Case(
"i4", SP::I4).
Case(
"i5", SP::I5).
Case(
"i6", SP::I6).
Case(
"i7", SP::I7)
1151 .
Case(
"o0", SP::O0).
Case(
"o1", SP::O1).
Case(
"o2", SP::O2).
Case(
"o3", SP::O3)
1152 .
Case(
"o4", SP::O4).
Case(
"o5", SP::O5).
Case(
"o6", SP::O6).
Case(
"o7", SP::O7)
1153 .
Case(
"l0", SP::L0).
Case(
"l1", SP::L1).
Case(
"l2", SP::L2).
Case(
"l3", SP::L3)
1154 .
Case(
"l4", SP::L4).
Case(
"l5", SP::L5).
Case(
"l6", SP::L6).
Case(
"l7", SP::L7)
1155 .
Case(
"g0", SP::G0).
Case(
"g1", SP::G1).
Case(
"g2", SP::G2).
Case(
"g3", SP::G3)
1156 .
Case(
"g4", SP::G4).
Case(
"g5", SP::G5).
Case(
"g6", SP::G6).
Case(
"g7", SP::G7)
1163 if (!
TRI->isReservedReg(MF, Reg))
1182 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1187 if (!VA.
isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1195 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1196 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1198 assert(
Offset < 16*8 &&
"Offset out of range, bad register enum?");
1202 unsigned IReg = SP::I0 +
Offset/8;
1203 if (ValTy == MVT::f64)
1208 assert(ValTy == MVT::f128 &&
"Unexpected type!");
1245 unsigned StackReserved = 6 * 8u;
1246 unsigned ArgsSize = std::max<unsigned>(StackReserved, CCInfo.
getStackSize());
1249 ArgsSize =
alignTo(ArgsSize, 16);
1273 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1329 RegsToPass.
push_back(std::make_pair(HiReg, Hi64));
1330 RegsToPass.
push_back(std::make_pair(LoReg, Lo64));
1342 if (i+1 < ArgLocs.
size() && ArgLocs[i+1].isRegLoc() &&
1343 ArgLocs[i+1].getLocReg() == VA.
getLocReg()) {
1355 RegsToPass.
push_back(std::make_pair(Reg, Arg));
1374 if (!MemOpChains.
empty())
1382 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1384 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1404 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
1406 RegsToPass[i].second.getValueType()));
1411 ((hasReturnsTwice) ?
TRI->getRTCallPreservedMask(CLI.
CallConv)
1418 assert(Mask &&
"Missing call preserved mask for calling convention");
1449 if (CLI.
Ins.size() == 1 && CLI.
Ins[0].VT == MVT::f32 && !CLI.
CB)
1450 CLI.
Ins[0].Flags.setInReg();
1455 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1599 if (!Subtarget->useSoftFloat()) {
1767 if (Subtarget->isV9()) {
1774 }
else if (Subtarget->hasLeonCasa())
1807 if (!Subtarget->isV9()) {
1849 if (Subtarget->useSoftMulDiv()) {
1899 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1907 if (Subtarget->hasHardQuad()) {
1915 if (Subtarget->isV9()) {
1946 if (Subtarget->
is64Bit() && !Subtarget->useSoftFloat()) {
1964 }
else if (!Subtarget->useSoftFloat()) {
1985 if (Subtarget->fixAllFDIVSQRT()) {
1992 if (Subtarget->hasNoFMULS()) {
2000 if (Subtarget->hasLeonCycleCounter())
2011 return Subtarget->useSoftFloat();
2020 return "SPISD::CMPFCC_V9";
2023 return "SPISD::BPICC";
2025 return "SPISD::BPXCC";
2028 return "SPISD::BRFCC_V9";
2030 return "SPISD::BR_REG";
2035 return "SPISD::SELECT_REG";
2068 const APInt &DemandedElts,
2070 unsigned Depth)
const {
2074 switch (
Op.getOpcode()) {
2101 SPCC =
LHS.getConstantOperandVal(2);
2113 GA->getValueType(0),
2114 GA->getOffset(), TF);
2118 CP->getAlign(), CP->getOffset(), TF);
2128 ES->getValueType(0), TF);
2136 unsigned HiTF,
unsigned LoTF,
2139 EVT VT =
Op.getValueType();
2265 assert(Mask &&
"Missing call preserved mask for calling convention");
2347 Args.push_back(Entry);
2353 const char *LibFuncName,
2354 unsigned numArgs)
const {
2367 if (
RetTy->isFP128Ty()) {
2372 Entry.Node = RetPtr;
2375 Entry.IsSRet =
true;
2376 Entry.IndirectType =
RetTy;
2378 Entry.IsReturned =
false;
2379 Args.push_back(Entry);
2384 for (
unsigned i = 0, e = numArgs; i != e; ++i) {
2394 if (RetTyABI ==
RetTy)
2397 assert (
RetTy->isFP128Ty() &&
"Unexpected return type!");
2407 unsigned &SPCC,
const SDLoc &
DL,
2410 const char *
LibCall =
nullptr;
2507 if (
Op.getOperand(0).getValueType() == MVT::f64)
2511 if (
Op.getOperand(0).getValueType() == MVT::f32)
2523 if (
Op.getOperand(0).getValueType() != MVT::f128)
2526 if (
Op.getValueType() == MVT::f64)
2529 if (
Op.getValueType() == MVT::f32)
2541 EVT VT =
Op.getValueType();
2542 assert(VT == MVT::i32 || VT == MVT::i64);
2545 if (
Op.getOperand(0).getValueType() == MVT::f128
2548 ? RTLIB::FPTOSINT_F128_I32
2549 : RTLIB::FPTOSINT_F128_I64);
2570 EVT OpVT =
Op.getOperand(0).getValueType();
2571 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2573 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2576 if (
Op.getValueType() == MVT::f128
2579 ? RTLIB::SINTTOFP_I32_F128
2580 : RTLIB::SINTTOFP_I64_F128);
2591 return DAG.
getNode(opcode, dl,
Op.getValueType(), Tmp);
2598 EVT VT =
Op.getValueType();
2602 if (
Op.getOperand(0).getValueType() != MVT::f128 ||
2606 assert(VT == MVT::i32 || VT == MVT::i64);
2610 ? RTLIB::FPTOUINT_F128_I32
2611 : RTLIB::FPTOUINT_F128_I64),
2619 EVT OpVT =
Op.getOperand(0).getValueType();
2620 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2624 if (
Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.
isTypeLegal(OpVT)))
2629 ? RTLIB::UINTTOFP_I32_F128
2630 : RTLIB::UINTTOFP_I64_F128),
2643 unsigned Opc, SPCC = ~0U;
2652 if (
LHS.getValueType().isInteger()) {
2655 if (
is64Bit && isV9 &&
LHS.getValueType() == MVT::i64 &&
2670 if (!hasHardQuad &&
LHS.getValueType() == MVT::f128) {
2681 return DAG.
getNode(Opc, dl, MVT::Other, Chain, Dest,
2682 DAG.
getConstant(SPCC, dl, MVT::i32), CompareFlag);
2694 unsigned Opc, SPCC = ~0U;
2702 if (
LHS.getValueType().isInteger()) {
2709 EVT ValType = TrueVal.getValueType();
2710 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2711 ValType == MVT::f64 ||
2712 (ValType == MVT::f128 && hasHardQuad);
2713 if (
is64Bit && isV9 &&
LHS.getValueType() == MVT::i64 &&
2720 Opc =
LHS.getValueType() == MVT::i32 ?
2724 if (!hasHardQuad &&
LHS.getValueType() == MVT::f128) {
2735 return DAG.
getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2736 DAG.
getConstant(SPCC, dl, MVT::i32), CompareFlag);
2754 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2761 EVT VT =
Node->getValueType(0);
2765 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2788 cast<ConstantSDNode>(
Op.getOperand(2))->getMaybeAlignValue();
2790 EVT VT =
Size->getValueType(0);
2796 if (Alignment && *Alignment > StackAlign) {
2799 "over-aligned dynamic alloca not supported.");
2804 unsigned regSpillArea;
2834 unsigned SPReg = SP::O6;
2843 SDValue Ops[2] = { NewVal, Chain };
2857 bool AlwaysFlush =
false) {
2861 EVT VT =
Op.getValueType();
2863 unsigned FrameReg = SP::I6;
2874 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2891 uint64_t depth =
Op.getConstantOperandVal(0);
2907 EVT VT =
Op.getValueType();
2909 uint64_t depth =
Op.getConstantOperandVal(0);
2952 Lo32 = DAG.
getNode(opcode, dl, MVT::f32, Lo32);
2954 Hi32 = DAG.
getNode(opcode, dl, MVT::f32, Hi32);
3012 if (MemVT == MVT::f128)
3061 if (MemVT == MVT::f128)
3064 if (MemVT == MVT::i64) {
3080 &&
"invalid opcode");
3084 if (
Op.getValueType() == MVT::f64)
3086 if (
Op.getValueType() != MVT::f128)
3102 Lo64 = DAG.
getNode(
Op.getOpcode(), dl, MVT::f64, Lo64);
3107 Hi64 = DAG.
getNode(
Op.getOpcode(), dl, MVT::f64, Hi64);
3123 if (
Op.getValueType() != MVT::i64)
3140 bool hasChain =
false;
3141 unsigned hiOpc =
Op.getOpcode();
3142 switch (
Op.getOpcode()) {
3152 Lo = DAG.
getNode(
Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
3155 Lo = DAG.
getNode(
Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
3166 SDValue Ops[2] = { Dst, Carry };
3175 unsigned opcode =
Op.getOpcode();
3180 EVT WideVT = MVT::i128;
3184 if (
LHS.getValueType() != VT)
3204 RTLIB::MUL_I128, WideVT,
3205 Args, CallOptions, dl).first;
3207 std::tie(BottomHalf, TopHalf) = DAG.
SplitScalar(MulResult, dl, VT, VT);
3219 assert(MulResult->
use_empty() &&
"Illegally typed node still in use!");
3221 SDValue Ops[2] = { BottomHalf, TopHalf } ;
3237 unsigned IntNo =
Op.getConstantOperandVal(0);
3241 case Intrinsic::thread_pointer: {
3251 bool hasHardQuad = Subtarget->hasHardQuad();
3252 bool isV9 = Subtarget->isV9();
3255 switch (
Op.getOpcode()) {
3314 APInt V =
C->getValueAPF().bitcastToAPInt();
3327 if (isa<ConstantFPSDNode>(Src) &&
N->getSimpleValueType(0) == MVT::v2i32 &&
3328 Src.getSimpleValueType() == MVT::f64)
3336 switch (
N->getOpcode()) {
3348 switch (
MI.getOpcode()) {
3350 case SP::SELECT_CC_Int_ICC:
3351 case SP::SELECT_CC_FP_ICC:
3352 case SP::SELECT_CC_DFP_ICC:
3353 case SP::SELECT_CC_QFP_ICC:
3354 if (Subtarget->isV9())
3357 case SP::SELECT_CC_Int_XCC:
3358 case SP::SELECT_CC_FP_XCC:
3359 case SP::SELECT_CC_DFP_XCC:
3360 case SP::SELECT_CC_QFP_XCC:
3362 case SP::SELECT_CC_Int_FCC:
3363 case SP::SELECT_CC_FP_FCC:
3364 case SP::SELECT_CC_DFP_FCC:
3365 case SP::SELECT_CC_QFP_FCC:
3366 if (Subtarget->isV9())
3374 unsigned BROpcode)
const {
3397 F->insert(It, IfFalseMBB);
3398 F->insert(It, SinkMBB);
3418 MI.getOperand(0).getReg())
3424 MI.eraseFromParent();
3436 if (Constraint.
size() == 1) {
3437 switch (Constraint[0]) {
3453 const char *constraint)
const {
3455 Value *CallOperandVal =
info.CallOperandVal;
3458 if (!CallOperandVal)
3462 switch (*constraint) {
3468 if (isInt<13>(
C->getSExtValue()))
3484 if (Constraint.
size() > 1)
3487 char ConstraintLetter = Constraint[0];
3488 switch (ConstraintLetter) {
3492 if (isInt<13>(
C->getSExtValue())) {
3501 if (Result.getNode()) {
3502 Ops.push_back(Result);
3508std::pair<unsigned, const TargetRegisterClass *>
3512 if (Constraint.
empty())
3513 return std::make_pair(0U,
nullptr);
3515 if (Constraint.
size() == 1) {
3516 switch (Constraint[0]) {
3518 if (VT == MVT::v2i32)
3519 return std::make_pair(0U, &SP::IntPairRegClass);
3520 else if (Subtarget->
is64Bit())
3521 return std::make_pair(0U, &SP::I64RegsRegClass);
3523 return std::make_pair(0U, &SP::IntRegsRegClass);
3525 if (VT == MVT::f32 || VT == MVT::i32)
3526 return std::make_pair(0U, &SP::FPRegsRegClass);
3527 else if (VT == MVT::f64 || VT == MVT::i64)
3528 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3529 else if (VT == MVT::f128)
3530 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3532 return std::make_pair(0U,
nullptr);
3534 if (VT == MVT::f32 || VT == MVT::i32)
3535 return std::make_pair(0U, &SP::FPRegsRegClass);
3536 else if (VT == MVT::f64 || VT == MVT::i64 )
3537 return std::make_pair(0U, &SP::DFPRegsRegClass);
3538 else if (VT == MVT::f128)
3539 return std::make_pair(0U, &SP::QFPRegsRegClass);
3541 return std::make_pair(0U,
nullptr);
3545 if (Constraint.
front() !=
'{')
3546 return std::make_pair(0U,
nullptr);
3548 assert(Constraint.
back() ==
'}' &&
"Not a brace enclosed constraint?");
3551 return std::make_pair(0U,
nullptr);
3553 unsigned long long RegNo;
3562 return std::make_pair(0U,
nullptr);
3563 const char RegTypes[] = {
'g',
'o',
'l',
'i'};
3564 char RegType = RegTypes[RegNo / 8];
3565 char RegIndex =
'0' + (RegNo % 8);
3566 char Tmp[] = {
'{', RegType, RegIndex,
'}', 0};
3571 if (VT != MVT::f32 && VT != MVT::Other &&
RegName[0] ==
'f' &&
3573 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3576 }
else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3580 return std::make_pair(0U,
nullptr);
3586 if (!ResultPair.second)
3587 return std::make_pair(0U,
nullptr);
3590 if (Subtarget->
is64Bit() && VT == MVT::i64) {
3591 assert(ResultPair.second == &SP::IntRegsRegClass &&
3592 "Unexpected register class");
3593 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3613 switch (
N->getOpcode()) {
3615 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
3620 if (
N->getOperand(0).getValueType() != MVT::f128
3621 ||
N->getValueType(0) != MVT::i64)
3624 ? RTLIB::FPTOSINT_F128_I64
3625 : RTLIB::FPTOUINT_F128_I64);
3633 assert(Subtarget->hasLeonCycleCounter());
3639 Results.push_back(
N->getOperand(0));
3645 if (
N->getValueType(0) != MVT::f128
3646 ||
N->getOperand(0).getValueType() != MVT::i64)
3650 ? RTLIB::SINTTOFP_I64_F128
3651 : RTLIB::UINTTOFP_I64_F128);
3695 assert(
MI.getOpcode() == SP::SUBCCrr ||
MI.getOpcode() == SP::SUBCCri);
3697 if (!Node->hasAnyUseOfValue(0))
3698 MI.getOperand(0).setReg(SP::G0);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static bool isSigned(unsigned int Opcode)
const HexagonInstrInfo * TII
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
static unsigned toCallerWindow(unsigned Reg)
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC)
intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC rcond condition.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI, const MachineFunction &MF)
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static void emitReservedArgRegCallError(const MachineFunction &MF)
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool is64Bit(const char *name)
Class for arbitrary precision integers.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
unsigned getValNo() const
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This is the shared class of boolean and integer constants.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Diagnostic information for unsupported feature in backend.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
static auto integer_fixedlen_vector_valuetypes()
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Align getOriginalAlign() const
Returns alignment and volatility of the memory access.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool use_empty() const
Return true if there are no uses of this node.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Register getSRetReturnReg() const
int getVarArgsFrameOffset() const
void setVarArgsFrameOffset(int Offset)
void setSRetReturnReg(Register Reg)
const SparcRegisterInfo * getRegisterInfo() const override
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
const TargetFrameLowering * getFrameLowering() const override
bool isTargetLinux() const
const SparcInstrInfo * getInstrInfo() const override
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
bool useSoftFloat() const override
SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool IsEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
StackOffset holds a fixed and a scalable offset in bytes.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
char back() const
back - Get the last character in the string.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFP128Ty() const
Return true if this is 'fp128'.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt32Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ SMULO
Same for multiplication.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isStrongerThanMonotonic(AtomicOrdering AO)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...
void resetAll()
Resets the known state of all bits.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
This class contains a discriminated union of information about pointers in memory operands,...
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setSExt(bool Value=true)