LLVM  6.0.0svn
LanaiISelLowering.cpp
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1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "LanaiISelLowering.h"
15 #include "Lanai.h"
16 #include "LanaiCondCode.h"
18 #include "LanaiSubtarget.h"
19 #include "LanaiTargetObjectFile.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/KnownBits.h"
50 #include <cassert>
51 #include <cmath>
52 #include <cstdint>
53 #include <cstdlib>
54 #include <utility>
55 
56 #define DEBUG_TYPE "lanai-lower"
57 
58 using namespace llvm;
59 
60 // Limit on number of instructions the lowered multiplication may have before a
61 // call to the library function should be generated instead. The threshold is
62 // currently set to 14 as this was the smallest threshold that resulted in all
63 // constant multiplications being lowered. A threshold of 5 covered all cases
64 // except for one multiplication which required 14. mulsi3 requires 16
65 // instructions (including the prologue and epilogue but excluding instructions
66 // at call site). Until we can inline mulsi3, generating at most 14 instructions
67 // will be faster than invoking mulsi3.
69  "lanai-constant-mul-threshold", cl::Hidden,
70  cl::desc("Maximum number of instruction to generate when lowering constant "
71  "multiplication instead of calling library function [default=14]"),
72  cl::init(14));
73 
75  const LanaiSubtarget &STI)
76  : TargetLowering(TM) {
77  // Set up the register classes.
78  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
79 
80  // Compute derived properties from the register classes
81  TRI = STI.getRegisterInfo();
83 
85 
93 
98 
102 
107 
114 
120 
126 
131 
135 
136  // Extended load operations for i1 types must be promoted
137  for (MVT VT : MVT::integer_valuetypes()) {
141  }
142 
148 
149  // Function alignments (log2)
152 
153  setJumpIsExpensive(true);
154 
155  // TODO: Setting the minimum jump table entries needed before a
156  // switch is transformed to a jump table to 100 to avoid creating jump tables
157  // as this was causing bad performance compared to a large group of if
158  // statements. Re-evaluate this on new benchmarks.
160 
161  // Use fast calling convention for library functions.
162  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
163  setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
164  }
165 
166  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
168  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
170  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
172 
173  // Booleans always contain 0 or 1.
175 }
176 
178  SelectionDAG &DAG) const {
179  switch (Op.getOpcode()) {
180  case ISD::MUL:
181  return LowerMUL(Op, DAG);
182  case ISD::BR_CC:
183  return LowerBR_CC(Op, DAG);
184  case ISD::ConstantPool:
185  return LowerConstantPool(Op, DAG);
186  case ISD::GlobalAddress:
187  return LowerGlobalAddress(Op, DAG);
188  case ISD::BlockAddress:
189  return LowerBlockAddress(Op, DAG);
190  case ISD::JumpTable:
191  return LowerJumpTable(Op, DAG);
192  case ISD::SELECT_CC:
193  return LowerSELECT_CC(Op, DAG);
194  case ISD::SETCC:
195  return LowerSETCC(Op, DAG);
196  case ISD::SETCCE:
197  return LowerSETCCE(Op, DAG);
198  case ISD::SHL_PARTS:
199  return LowerSHL_PARTS(Op, DAG);
200  case ISD::SRL_PARTS:
201  return LowerSRL_PARTS(Op, DAG);
202  case ISD::VASTART:
203  return LowerVASTART(Op, DAG);
205  return LowerDYNAMIC_STACKALLOC(Op, DAG);
206  case ISD::RETURNADDR:
207  return LowerRETURNADDR(Op, DAG);
208  case ISD::FRAMEADDR:
209  return LowerFRAMEADDR(Op, DAG);
210  default:
211  llvm_unreachable("unimplemented operand");
212  }
213 }
214 
215 //===----------------------------------------------------------------------===//
216 // Lanai Inline Assembly Support
217 //===----------------------------------------------------------------------===//
218 
219 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
220  SelectionDAG & /*DAG*/) const {
221  // Only unallocatable registers should be matched here.
222  unsigned Reg = StringSwitch<unsigned>(RegName)
223  .Case("pc", Lanai::PC)
224  .Case("sp", Lanai::SP)
225  .Case("fp", Lanai::FP)
226  .Case("rr1", Lanai::RR1)
227  .Case("r10", Lanai::R10)
228  .Case("rr2", Lanai::RR2)
229  .Case("r11", Lanai::R11)
230  .Case("rca", Lanai::RCA)
231  .Default(0);
232 
233  if (Reg)
234  return Reg;
235  report_fatal_error("Invalid register name global variable");
236 }
237 
238 std::pair<unsigned, const TargetRegisterClass *>
240  StringRef Constraint,
241  MVT VT) const {
242  if (Constraint.size() == 1)
243  // GCC Constraint Letters
244  switch (Constraint[0]) {
245  case 'r': // GENERAL_REGS
246  return std::make_pair(0U, &Lanai::GPRRegClass);
247  default:
248  break;
249  }
250 
251  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
252 }
253 
254 // Examine constraint type and operand type and determine a weight value.
255 // This object must already have been set up with the operand type
256 // and the current alternative constraint selected.
259  AsmOperandInfo &Info, const char *Constraint) const {
260  ConstraintWeight Weight = CW_Invalid;
261  Value *CallOperandVal = Info.CallOperandVal;
262  // If we don't have a value, we can't do a match,
263  // but allow it at the lowest weight.
264  if (CallOperandVal == nullptr)
265  return CW_Default;
266  // Look at the constraint type.
267  switch (*Constraint) {
268  case 'I': // signed 16 bit immediate
269  case 'J': // integer zero
270  case 'K': // unsigned 16 bit immediate
271  case 'L': // immediate in the range 0 to 31
272  case 'M': // signed 32 bit immediate where lower 16 bits are 0
273  case 'N': // signed 26 bit immediate
274  case 'O': // integer zero
275  if (isa<ConstantInt>(CallOperandVal))
276  Weight = CW_Constant;
277  break;
278  default:
279  Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
280  break;
281  }
282  return Weight;
283 }
284 
285 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
286 // vector. If it is invalid, don't add anything to Ops.
288  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
289  SelectionDAG &DAG) const {
290  SDValue Result(nullptr, 0);
291 
292  // Only support length 1 constraints for now.
293  if (Constraint.length() > 1)
294  return;
295 
296  char ConstraintLetter = Constraint[0];
297  switch (ConstraintLetter) {
298  case 'I': // Signed 16 bit constant
299  // If this fails, the parent routine will give an error
300  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
301  if (isInt<16>(C->getSExtValue())) {
302  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
303  Op.getValueType());
304  break;
305  }
306  }
307  return;
308  case 'J': // integer zero
309  case 'O':
310  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
311  if (C->getZExtValue() == 0) {
312  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
313  break;
314  }
315  }
316  return;
317  case 'K': // unsigned 16 bit immediate
318  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
319  if (isUInt<16>(C->getZExtValue())) {
320  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
321  Op.getValueType());
322  break;
323  }
324  }
325  return;
326  case 'L': // immediate in the range 0 to 31
327  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
328  if (C->getZExtValue() <= 31) {
329  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
330  Op.getValueType());
331  break;
332  }
333  }
334  return;
335  case 'M': // signed 32 bit immediate where lower 16 bits are 0
336  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
337  int64_t Val = C->getSExtValue();
338  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
339  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
340  break;
341  }
342  }
343  return;
344  case 'N': // signed 26 bit immediate
345  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
346  int64_t Val = C->getSExtValue();
347  if ((Val >= -33554432) && (Val <= 33554431)) {
348  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
349  break;
350  }
351  }
352  return;
353  default:
354  break; // This will fall through to the generic implementation
355  }
356 
357  if (Result.getNode()) {
358  Ops.push_back(Result);
359  return;
360  }
361 
362  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
363 }
364 
365 //===----------------------------------------------------------------------===//
366 // Calling Convention Implementation
367 //===----------------------------------------------------------------------===//
368 
369 #include "LanaiGenCallingConv.inc"
370 
371 static unsigned NumFixedArgs;
372 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
373  CCValAssign::LocInfo LocInfo,
374  ISD::ArgFlagsTy ArgFlags, CCState &State) {
375  // Handle fixed arguments with default CC.
376  // Note: Both the default and fast CC handle VarArg the same and hence the
377  // calling convention of the function is not considered here.
378  if (ValNo < NumFixedArgs) {
379  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
380  }
381 
382  // Promote i8/i16 args to i32
383  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
384  LocVT = MVT::i32;
385  if (ArgFlags.isSExt())
386  LocInfo = CCValAssign::SExt;
387  else if (ArgFlags.isZExt())
388  LocInfo = CCValAssign::ZExt;
389  else
390  LocInfo = CCValAssign::AExt;
391  }
392 
393  // VarArgs get passed on stack
394  unsigned Offset = State.AllocateStack(4, 4);
395  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
396  return false;
397 }
398 
399 SDValue LanaiTargetLowering::LowerFormalArguments(
400  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
401  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
402  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
403  switch (CallConv) {
404  case CallingConv::C:
405  case CallingConv::Fast:
406  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
407  default:
408  report_fatal_error("Unsupported calling convention");
409  }
410 }
411 
412 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
413  SmallVectorImpl<SDValue> &InVals) const {
414  SelectionDAG &DAG = CLI.DAG;
415  SDLoc &DL = CLI.DL;
417  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
419  SDValue Chain = CLI.Chain;
420  SDValue Callee = CLI.Callee;
421  bool &IsTailCall = CLI.IsTailCall;
422  CallingConv::ID CallConv = CLI.CallConv;
423  bool IsVarArg = CLI.IsVarArg;
424 
425  // Lanai target does not yet support tail call optimization.
426  IsTailCall = false;
427 
428  switch (CallConv) {
429  case CallingConv::Fast:
430  case CallingConv::C:
431  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
432  OutVals, Ins, DL, DAG, InVals);
433  default:
434  report_fatal_error("Unsupported calling convention");
435  }
436 }
437 
438 // LowerCCCArguments - transform physical registers into virtual registers and
439 // generate load operations for arguments places on the stack.
440 SDValue LanaiTargetLowering::LowerCCCArguments(
441  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
442  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
443  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
445  MachineFrameInfo &MFI = MF.getFrameInfo();
446  MachineRegisterInfo &RegInfo = MF.getRegInfo();
448 
449  // Assign locations to all of the incoming arguments.
451  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
452  *DAG.getContext());
453  if (CallConv == CallingConv::Fast) {
454  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
455  } else {
456  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
457  }
458 
459  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
460  CCValAssign &VA = ArgLocs[i];
461  if (VA.isRegLoc()) {
462  // Arguments passed in registers
463  EVT RegVT = VA.getLocVT();
464  switch (RegVT.getSimpleVT().SimpleTy) {
465  case MVT::i32: {
466  unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
467  RegInfo.addLiveIn(VA.getLocReg(), VReg);
468  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
469 
470  // If this is an 8/16-bit value, it is really passed promoted to 32
471  // bits. Insert an assert[sz]ext to capture this, then truncate to the
472  // right size.
473  if (VA.getLocInfo() == CCValAssign::SExt)
474  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
475  DAG.getValueType(VA.getValVT()));
476  else if (VA.getLocInfo() == CCValAssign::ZExt)
477  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
478  DAG.getValueType(VA.getValVT()));
479 
480  if (VA.getLocInfo() != CCValAssign::Full)
481  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
482 
483  InVals.push_back(ArgValue);
484  break;
485  }
486  default:
487  DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
488  << RegVT.getEVTString() << "\n");
489  llvm_unreachable("unhandled argument type");
490  }
491  } else {
492  // Sanity check
493  assert(VA.isMemLoc());
494  // Load the argument to a virtual register
495  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
496  // Check that the argument fits in stack slot
497  if (ObjSize > 4) {
498  errs() << "LowerFormalArguments Unhandled argument type: "
499  << EVT(VA.getLocVT()).getEVTString() << "\n";
500  }
501  // Create the frame index object for this incoming parameter...
502  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
503 
504  // Create the SelectionDAG nodes corresponding to a load
505  // from this parameter
506  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
507  InVals.push_back(DAG.getLoad(
508  VA.getLocVT(), DL, Chain, FIN,
510  }
511  }
512 
513  // The Lanai ABI for returning structs by value requires that we copy
514  // the sret argument into rv for the return. Save the argument into
515  // a virtual register so that we can access it from the return points.
516  if (MF.getFunction()->hasStructRetAttr()) {
517  unsigned Reg = LanaiMFI->getSRetReturnReg();
518  if (!Reg) {
520  LanaiMFI->setSRetReturnReg(Reg);
521  }
522  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
523  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
524  }
525 
526  if (IsVarArg) {
527  // Record the frame index of the first variable argument
528  // which is a value necessary to VASTART.
529  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
530  LanaiMFI->setVarArgsFrameIndex(FI);
531  }
532 
533  return Chain;
534 }
535 
536 SDValue
537 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
538  bool IsVarArg,
540  const SmallVectorImpl<SDValue> &OutVals,
541  const SDLoc &DL, SelectionDAG &DAG) const {
542  // CCValAssign - represent the assignment of the return value to a location
544 
545  // CCState - Info about the registers and stack slot.
546  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
547  *DAG.getContext());
548 
549  // Analize return values.
550  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
551 
552  SDValue Flag;
553  SmallVector<SDValue, 4> RetOps(1, Chain);
554 
555  // Copy the result values into the output registers.
556  for (unsigned i = 0; i != RVLocs.size(); ++i) {
557  CCValAssign &VA = RVLocs[i];
558  assert(VA.isRegLoc() && "Can only return in registers!");
559 
560  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
561 
562  // Guarantee that all emitted copies are stuck together with flags.
563  Flag = Chain.getValue(1);
564  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
565  }
566 
567  // The Lanai ABI for returning structs by value requires that we copy
568  // the sret argument into rv for the return. We saved the argument into
569  // a virtual register in the entry block, so now we copy the value out
570  // and into rv.
574  unsigned Reg = LanaiMFI->getSRetReturnReg();
575  assert(Reg &&
576  "SRetReturnReg should have been set in LowerFormalArguments().");
577  SDValue Val =
578  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
579 
580  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
581  Flag = Chain.getValue(1);
582  RetOps.push_back(
583  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
584  }
585 
586  RetOps[0] = Chain; // Update chain
587 
588  unsigned Opc = LanaiISD::RET_FLAG;
589  if (Flag.getNode())
590  RetOps.push_back(Flag);
591 
592  // Return Void
593  return DAG.getNode(Opc, DL, MVT::Other,
594  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
595 }
596 
597 // LowerCCCCallTo - functions arguments are copied from virtual regs to
598 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
599 SDValue LanaiTargetLowering::LowerCCCCallTo(
600  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
601  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
602  const SmallVectorImpl<SDValue> &OutVals,
603  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
604  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
605  // Analyze operands of the call, assigning locations to each operand.
607  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
608  *DAG.getContext());
611 
612  NumFixedArgs = 0;
613  if (IsVarArg && G) {
614  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
615  if (CalleeFn)
616  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
617  }
618  if (NumFixedArgs)
619  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
620  else {
621  if (CallConv == CallingConv::Fast)
622  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
623  else
624  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
625  }
626 
627  // Get a count of how many bytes are to be pushed on the stack.
628  unsigned NumBytes = CCInfo.getNextStackOffset();
629 
630  // Create local copies for byval args.
631  SmallVector<SDValue, 8> ByValArgs;
632  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
633  ISD::ArgFlagsTy Flags = Outs[I].Flags;
634  if (!Flags.isByVal())
635  continue;
636 
637  SDValue Arg = OutVals[I];
638  unsigned Size = Flags.getByValSize();
639  unsigned Align = Flags.getByValAlign();
640 
641  int FI = MFI.CreateStackObject(Size, Align, false);
642  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
643  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
644 
645  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
646  /*IsVolatile=*/false,
647  /*AlwaysInline=*/false,
648  /*isTailCall=*/false, MachinePointerInfo(),
650  ByValArgs.push_back(FIPtr);
651  }
652 
653  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
654 
656  SmallVector<SDValue, 12> MemOpChains;
657  SDValue StackPtr;
658 
659  // Walk the register/memloc assignments, inserting copies/loads.
660  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
661  CCValAssign &VA = ArgLocs[I];
662  SDValue Arg = OutVals[I];
663  ISD::ArgFlagsTy Flags = Outs[I].Flags;
664 
665  // Promote the value if needed.
666  switch (VA.getLocInfo()) {
667  case CCValAssign::Full:
668  break;
669  case CCValAssign::SExt:
670  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
671  break;
672  case CCValAssign::ZExt:
673  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
674  break;
675  case CCValAssign::AExt:
676  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
677  break;
678  default:
679  llvm_unreachable("Unknown loc info!");
680  }
681 
682  // Use local copy if it is a byval arg.
683  if (Flags.isByVal())
684  Arg = ByValArgs[J++];
685 
686  // Arguments that can be passed on register must be kept at RegsToPass
687  // vector
688  if (VA.isRegLoc()) {
689  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
690  } else {
691  assert(VA.isMemLoc());
692 
693  if (StackPtr.getNode() == nullptr)
694  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
695  getPointerTy(DAG.getDataLayout()));
696 
697  SDValue PtrOff =
698  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
699  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
700 
701  MemOpChains.push_back(
702  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
703  }
704  }
705 
706  // Transform all store nodes into one single node because all store nodes are
707  // independent of each other.
708  if (!MemOpChains.empty())
709  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
710  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
711 
712  SDValue InFlag;
713 
714  // Build a sequence of copy-to-reg nodes chained together with token chain and
715  // flag operands which copy the outgoing args into registers. The InFlag in
716  // necessary since all emitted instructions must be stuck together.
717  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
718  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
719  RegsToPass[I].second, InFlag);
720  InFlag = Chain.getValue(1);
721  }
722 
723  // If the callee is a GlobalAddress node (quite common, every direct call is)
724  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
725  // Likewise ExternalSymbol -> TargetExternalSymbol.
726  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
727  if (G) {
728  Callee = DAG.getTargetGlobalAddress(
729  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
730  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
731  Callee = DAG.getTargetExternalSymbol(
732  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
733  }
734 
735  // Returns a chain & a flag for retval copy to use.
736  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
738  Ops.push_back(Chain);
739  Ops.push_back(Callee);
740 
741  // Add a register mask operand representing the call-preserved registers.
742  // TODO: Should return-twice functions be handled?
743  const uint32_t *Mask =
744  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
745  assert(Mask && "Missing call preserved mask for calling convention");
746  Ops.push_back(DAG.getRegisterMask(Mask));
747 
748  // Add argument registers to the end of the list so that they are
749  // known live into the call.
750  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
751  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
752  RegsToPass[I].second.getValueType()));
753 
754  if (InFlag.getNode())
755  Ops.push_back(InFlag);
756 
757  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
758  ArrayRef<SDValue>(&Ops[0], Ops.size()));
759  InFlag = Chain.getValue(1);
760 
761  // Create the CALLSEQ_END node.
762  Chain = DAG.getCALLSEQ_END(
763  Chain,
764  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
765  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
766  DL);
767  InFlag = Chain.getValue(1);
768 
769  // Handle result values, copying them out of physregs into vregs that we
770  // return.
771  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
772  InVals);
773 }
774 
775 // LowerCallResult - Lower the result values of a call into the
776 // appropriate copies out of appropriate physical registers.
777 SDValue LanaiTargetLowering::LowerCallResult(
778  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
779  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
780  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
781  // Assign locations to each value returned by this call.
783  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
784  *DAG.getContext());
785 
786  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
787 
788  // Copy all of the result registers out of their specified physreg.
789  for (unsigned I = 0; I != RVLocs.size(); ++I) {
790  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
791  RVLocs[I].getValVT(), InFlag)
792  .getValue(1);
793  InFlag = Chain.getValue(2);
794  InVals.push_back(Chain.getValue(0));
795  }
796 
797  return Chain;
798 }
799 
800 //===----------------------------------------------------------------------===//
801 // Custom Lowerings
802 //===----------------------------------------------------------------------===//
803 
805  SDValue &RHS, SelectionDAG &DAG) {
806  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
807 
808  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
809  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
810  // and Lanai only supports integer comparisons, so only provide definitions
811  // for them.
812  switch (SetCCOpcode) {
813  case ISD::SETEQ:
814  return LPCC::ICC_EQ;
815  case ISD::SETGT:
816  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
817  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
818  // X > -1 -> X >= 0 -> is_plus(X)
819  RHS = DAG.getConstant(0, DL, RHS.getValueType());
820  return LPCC::ICC_PL;
821  }
822  return LPCC::ICC_GT;
823  case ISD::SETUGT:
824  return LPCC::ICC_UGT;
825  case ISD::SETLT:
826  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
827  if (RHSC->getZExtValue() == 0)
828  // X < 0 -> is_minus(X)
829  return LPCC::ICC_MI;
830  return LPCC::ICC_LT;
831  case ISD::SETULT:
832  return LPCC::ICC_ULT;
833  case ISD::SETLE:
834  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
835  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
836  // X <= -1 -> X < 0 -> is_minus(X)
837  RHS = DAG.getConstant(0, DL, RHS.getValueType());
838  return LPCC::ICC_MI;
839  }
840  return LPCC::ICC_LE;
841  case ISD::SETULE:
842  return LPCC::ICC_ULE;
843  case ISD::SETGE:
844  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
845  if (RHSC->getZExtValue() == 0)
846  // X >= 0 -> is_plus(X)
847  return LPCC::ICC_PL;
848  return LPCC::ICC_GE;
849  case ISD::SETUGE:
850  return LPCC::ICC_UGE;
851  case ISD::SETNE:
852  return LPCC::ICC_NE;
853  case ISD::SETONE:
854  case ISD::SETUNE:
855  case ISD::SETOGE:
856  case ISD::SETOLE:
857  case ISD::SETOLT:
858  case ISD::SETOGT:
859  case ISD::SETOEQ:
860  case ISD::SETUEQ:
861  case ISD::SETO:
862  case ISD::SETUO:
863  llvm_unreachable("Unsupported comparison.");
864  default:
865  llvm_unreachable("Unknown integer condition code!");
866  }
867 }
868 
870  SDValue Chain = Op.getOperand(0);
871  SDValue Cond = Op.getOperand(1);
872  SDValue LHS = Op.getOperand(2);
873  SDValue RHS = Op.getOperand(3);
874  SDValue Dest = Op.getOperand(4);
875  SDLoc DL(Op);
876 
877  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
878  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
879  SDValue Flag =
880  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
881 
882  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
883  TargetCC, Flag);
884 }
885 
887  EVT VT = Op->getValueType(0);
888  if (VT != MVT::i32)
889  return SDValue();
890 
892  if (!C)
893  return SDValue();
894 
895  int64_t MulAmt = C->getSExtValue();
896  int32_t HighestOne = -1;
897  uint32_t NonzeroEntries = 0;
898  int SignedDigit[32] = {0};
899 
900  // Convert to non-adjacent form (NAF) signed-digit representation.
901  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
902  // minimal Hamming weight representation of a number (on average 1/3 of the
903  // digits will be non-zero vs 1/2 for regular binary representation). And as
904  // the non-zero digits will be the only digits contributing to the instruction
905  // count, this is desirable. The next loop converts it to NAF (following the
906  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
907  // choosing the non-zero coefficients such that the resulting quotient is
908  // divisible by 2 which will cause the next coefficient to be zero.
909  int64_t E = std::abs(MulAmt);
910  int S = (MulAmt < 0 ? -1 : 1);
911  int I = 0;
912  while (E > 0) {
913  int ZI = 0;
914  if (E % 2 == 1) {
915  ZI = 2 - (E % 4);
916  if (ZI != 0)
917  ++NonzeroEntries;
918  }
919  SignedDigit[I] = S * ZI;
920  if (SignedDigit[I] == 1)
921  HighestOne = I;
922  E = (E - ZI) / 2;
923  ++I;
924  }
925 
926  // Compute number of instructions required. Due to differences in lowering
927  // between the different processors this count is not exact.
928  // Start by assuming a shift and a add/sub for every non-zero entry (hence
929  // every non-zero entry requires 1 shift and 1 add/sub except for the first
930  // entry).
931  int32_t InstrRequired = 2 * NonzeroEntries - 1;
932  // Correct possible over-adding due to shift by 0 (which is not emitted).
933  if (std::abs(MulAmt) % 2 == 1)
934  --InstrRequired;
935  // Return if the form generated would exceed the instruction threshold.
936  if (InstrRequired > LanaiLowerConstantMulThreshold)
937  return SDValue();
938 
939  SDValue Res;
940  SDLoc DL(Op);
941  SDValue V = Op->getOperand(0);
942 
943  // Initialize the running sum. Set the running sum to the maximal shifted
944  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
945  // term NAF).
946  if (HighestOne == -1)
947  Res = DAG.getConstant(0, DL, MVT::i32);
948  else {
949  Res = DAG.getNode(ISD::SHL, DL, VT, V,
950  DAG.getConstant(HighestOne, DL, MVT::i32));
951  SignedDigit[HighestOne] = 0;
952  }
953 
954  // Assemble multiplication from shift, add, sub using NAF form and running
955  // sum.
956  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
957  ++I) {
958  if (SignedDigit[I] == 0)
959  continue;
960 
961  // Shifted multiplicand (v<<i).
962  SDValue Op =
963  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
964  if (SignedDigit[I] == 1)
965  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
966  else if (SignedDigit[I] == -1)
967  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
968  }
969  return Res;
970 }
971 
973  SDValue LHS = Op.getOperand(0);
974  SDValue RHS = Op.getOperand(1);
975  SDValue Carry = Op.getOperand(2);
976  SDValue Cond = Op.getOperand(3);
977  SDLoc DL(Op);
978 
979  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
980  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
981  SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
982  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
983 }
984 
986  SDValue LHS = Op.getOperand(0);
987  SDValue RHS = Op.getOperand(1);
988  SDValue Cond = Op.getOperand(2);
989  SDLoc DL(Op);
990 
991  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
992  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
993  SDValue Flag =
994  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
995 
996  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
997 }
998 
1000  SelectionDAG &DAG) const {
1001  SDValue LHS = Op.getOperand(0);
1002  SDValue RHS = Op.getOperand(1);
1003  SDValue TrueV = Op.getOperand(2);
1004  SDValue FalseV = Op.getOperand(3);
1005  SDValue Cond = Op.getOperand(4);
1006  SDLoc DL(Op);
1007 
1008  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
1009  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
1010  SDValue Flag =
1011  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1012 
1013  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1014  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1015  Flag);
1016 }
1017 
1019  MachineFunction &MF = DAG.getMachineFunction();
1021 
1022  SDLoc DL(Op);
1023  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1024  getPointerTy(DAG.getDataLayout()));
1025 
1026  // vastart just stores the address of the VarArgsFrameIndex slot into the
1027  // memory location argument.
1028  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1029  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1030  MachinePointerInfo(SV));
1031 }
1032 
1034  SelectionDAG &DAG) const {
1035  SDValue Chain = Op.getOperand(0);
1036  SDValue Size = Op.getOperand(1);
1037  SDLoc DL(Op);
1038 
1039  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1040 
1041  // Get a reference to the stack pointer.
1042  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1043 
1044  // Subtract the dynamic size from the actual stack size to
1045  // obtain the new stack size.
1046  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1047 
1048  // For Lanai, the outgoing memory arguments area should be on top of the
1049  // alloca area on the stack i.e., the outgoing memory arguments should be
1050  // at a lower address than the alloca area. Move the alloca area down the
1051  // stack by adding back the space reserved for outgoing arguments to SP
1052  // here.
1053  //
1054  // We do not know what the size of the outgoing args is at this point.
1055  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1056  // stack pointer. We replace this instruction with on that has the correct,
1057  // known offset in emitPrologue().
1058  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1059 
1060  // The Sub result contains the new stack start address, so it
1061  // must be placed in the stack pointer register.
1062  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1063 
1064  SDValue Ops[2] = {ArgAdjust, CopyChain};
1065  return DAG.getMergeValues(Ops, DL);
1066 }
1067 
1069  SelectionDAG &DAG) const {
1070  MachineFunction &MF = DAG.getMachineFunction();
1071  MachineFrameInfo &MFI = MF.getFrameInfo();
1072  MFI.setReturnAddressIsTaken(true);
1073 
1074  EVT VT = Op.getValueType();
1075  SDLoc DL(Op);
1076  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1077  if (Depth) {
1078  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1079  const unsigned Offset = -4;
1080  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1081  DAG.getIntPtrConstant(Offset, DL));
1082  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1083  }
1084 
1085  // Return the link register, which contains the return address.
1086  // Mark it an implicit live-in.
1087  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1088  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1089 }
1090 
1092  SelectionDAG &DAG) const {
1094  MFI.setFrameAddressIsTaken(true);
1095 
1096  EVT VT = Op.getValueType();
1097  SDLoc DL(Op);
1098  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1099  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1100  while (Depth--) {
1101  const unsigned Offset = -8;
1102  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1103  DAG.getIntPtrConstant(Offset, DL));
1104  FrameAddr =
1105  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1106  }
1107  return FrameAddr;
1108 }
1109 
1110 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1111  switch (Opcode) {
1112  case LanaiISD::ADJDYNALLOC:
1113  return "LanaiISD::ADJDYNALLOC";
1114  case LanaiISD::RET_FLAG:
1115  return "LanaiISD::RET_FLAG";
1116  case LanaiISD::CALL:
1117  return "LanaiISD::CALL";
1118  case LanaiISD::SELECT_CC:
1119  return "LanaiISD::SELECT_CC";
1120  case LanaiISD::SETCC:
1121  return "LanaiISD::SETCC";
1122  case LanaiISD::SUBBF:
1123  return "LanaiISD::SUBBF";
1124  case LanaiISD::SET_FLAG:
1125  return "LanaiISD::SET_FLAG";
1126  case LanaiISD::BR_CC:
1127  return "LanaiISD::BR_CC";
1128  case LanaiISD::Wrapper:
1129  return "LanaiISD::Wrapper";
1130  case LanaiISD::HI:
1131  return "LanaiISD::HI";
1132  case LanaiISD::LO:
1133  return "LanaiISD::LO";
1134  case LanaiISD::SMALL:
1135  return "LanaiISD::SMALL";
1136  default:
1137  return nullptr;
1138  }
1139 }
1140 
1142  SelectionDAG &DAG) const {
1143  SDLoc DL(Op);
1144  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1145  const Constant *C = N->getConstVal();
1146  const LanaiTargetObjectFile *TLOF =
1147  static_cast<const LanaiTargetObjectFile *>(
1149 
1150  // If the code model is small or constant will be placed in the small section,
1151  // then assume address will fit in 21-bits.
1153  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1156  return DAG.getNode(ISD::OR, DL, MVT::i32,
1157  DAG.getRegister(Lanai::R0, MVT::i32),
1158  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1159  } else {
1160  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1161  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1162 
1164  N->getOffset(), OpFlagHi);
1166  N->getOffset(), OpFlagLo);
1167  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1168  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1169  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1170  return Result;
1171  }
1172 }
1173 
1175  SelectionDAG &DAG) const {
1176  SDLoc DL(Op);
1177  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1178  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1179 
1180  const LanaiTargetObjectFile *TLOF =
1181  static_cast<const LanaiTargetObjectFile *>(
1183 
1184  // If the code model is small or global variable will be placed in the small
1185  // section, then assume address will fit in 21-bits.
1186  const GlobalObject *GO = GV->getBaseObject();
1187  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1189  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1190  return DAG.getNode(ISD::OR, DL, MVT::i32,
1191  DAG.getRegister(Lanai::R0, MVT::i32),
1192  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1193  } else {
1194  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1195  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1196 
1197  // Create the TargetGlobalAddress node, folding in the constant offset.
1199  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1201  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1202  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1203  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1204  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1205  }
1206 }
1207 
1209  SelectionDAG &DAG) const {
1210  SDLoc DL(Op);
1211  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1212 
1213  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1214  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1215 
1216  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1217  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1218  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1219  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1220  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1221  return Result;
1222 }
1223 
1225  SelectionDAG &DAG) const {
1226  SDLoc DL(Op);
1227  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1228 
1229  // If the code model is small assume address will fit in 21-bits.
1233  return DAG.getNode(ISD::OR, DL, MVT::i32,
1234  DAG.getRegister(Lanai::R0, MVT::i32),
1235  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1236  } else {
1237  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1238  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1239 
1241  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1243  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1244  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1245  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1246  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1247  return Result;
1248  }
1249 }
1250 
1252  SelectionDAG &DAG) const {
1253  EVT VT = Op.getValueType();
1254  unsigned VTBits = VT.getSizeInBits();
1255  SDLoc dl(Op);
1256  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1257  SDValue ShOpLo = Op.getOperand(0);
1258  SDValue ShOpHi = Op.getOperand(1);
1259  SDValue ShAmt = Op.getOperand(2);
1260 
1261  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1262  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1263  // HiBitsForHi = ShOpHi << ShAmt
1264  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1265  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1266  // return (Hi << 32) | Lo;
1267 
1268  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1269  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1270  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1271 
1272  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1273  // wanted 0, so CSEL it directly.
1274  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1275  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1276  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1277 
1278  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1279  DAG.getConstant(VTBits, dl, MVT::i32));
1280  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1281  SDValue HiForNormalShift =
1282  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1283 
1284  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1285 
1286  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1287  SDValue Hi =
1288  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1289 
1290  // Lanai shifts of larger than register sizes are wrapped rather than
1291  // clamped, so we can't just emit "lo << b" if b is too big.
1292  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1293  SDValue Lo = DAG.getSelect(
1294  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1295 
1296  SDValue Ops[2] = {Lo, Hi};
1297  return DAG.getMergeValues(Ops, dl);
1298 }
1299 
1301  SelectionDAG &DAG) const {
1302  MVT VT = Op.getSimpleValueType();
1303  unsigned VTBits = VT.getSizeInBits();
1304  SDLoc dl(Op);
1305  SDValue ShOpLo = Op.getOperand(0);
1306  SDValue ShOpHi = Op.getOperand(1);
1307  SDValue ShAmt = Op.getOperand(2);
1308 
1309  // Performs the following for a >> b:
1310  // unsigned r_high = a_high >> b;
1311  // r_high = (32 - b <= 0) ? 0 : r_high;
1312  //
1313  // unsigned r_low = a_low >> b;
1314  // r_low = (32 - b <= 0) ? r_high : r_low;
1315  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1316  // return (unsigned long long)r_high << 32 | r_low;
1317  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1318  // mask the shift amount.
1319 
1320  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1321  SDValue NegatedPlus32 = DAG.getNode(
1322  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1323  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1324 
1325  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1326  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1327 
1328  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1329  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1330  SDValue CarryBits =
1331  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1332  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1333  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1334  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1335 
1336  SDValue Ops[2] = {Lo, Hi};
1337  return DAG.getMergeValues(Ops, dl);
1338 }
1339 
1340 // Helper function that checks if N is a null or all ones constant.
1341 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1342  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1343 }
1344 
1345 // Return true if N is conditionally 0 or all ones.
1346 // Detects these expressions where cc is an i1 value:
1347 //
1348 // (select cc 0, y) [AllOnes=0]
1349 // (select cc y, 0) [AllOnes=0]
1350 // (zext cc) [AllOnes=0]
1351 // (sext cc) [AllOnes=0/1]
1352 // (select cc -1, y) [AllOnes=1]
1353 // (select cc y, -1) [AllOnes=1]
1354 //
1355 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1356 // all ones operand (AllOnes true).
1357 // * Invert is set when N is the all zero/ones constant when CC is false.
1358 // * OtherOp is set to the alternative value of N.
1359 //
1360 // For example, for (select cc X, Y) and AllOnes = 0 if:
1361 // * X = 0, Invert = False and OtherOp = Y
1362 // * Y = 0, Invert = True and OtherOp = X
1363 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1364  bool &Invert, SDValue &OtherOp,
1365  SelectionDAG &DAG) {
1366  switch (N->getOpcode()) {
1367  default:
1368  return false;
1369  case ISD::SELECT: {
1370  CC = N->getOperand(0);
1371  SDValue N1 = N->getOperand(1);
1372  SDValue N2 = N->getOperand(2);
1373  if (isZeroOrAllOnes(N1, AllOnes)) {
1374  Invert = false;
1375  OtherOp = N2;
1376  return true;
1377  }
1378  if (isZeroOrAllOnes(N2, AllOnes)) {
1379  Invert = true;
1380  OtherOp = N1;
1381  return true;
1382  }
1383  return false;
1384  }
1385  case ISD::ZERO_EXTEND: {
1386  // (zext cc) can never be the all ones value.
1387  if (AllOnes)
1388  return false;
1389  CC = N->getOperand(0);
1390  if (CC.getValueType() != MVT::i1)
1391  return false;
1392  SDLoc dl(N);
1393  EVT VT = N->getValueType(0);
1394  OtherOp = DAG.getConstant(1, dl, VT);
1395  Invert = true;
1396  return true;
1397  }
1398  case ISD::SIGN_EXTEND: {
1399  CC = N->getOperand(0);
1400  if (CC.getValueType() != MVT::i1)
1401  return false;
1402  SDLoc dl(N);
1403  EVT VT = N->getValueType(0);
1404  Invert = !AllOnes;
1405  if (AllOnes)
1406  // When looking for an AllOnes constant, N is an sext, and the 'other'
1407  // value is 0.
1408  OtherOp = DAG.getConstant(0, dl, VT);
1409  else
1410  OtherOp =
1412  return true;
1413  }
1414  }
1415 }
1416 
1417 // Combine a constant select operand into its use:
1418 //
1419 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1420 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1421 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1422 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1423 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1424 //
1425 // The transform is rejected if the select doesn't have a constant operand that
1426 // is null, or all ones when AllOnes is set.
1427 //
1428 // Also recognize sext/zext from i1:
1429 //
1430 // (add (zext cc), x) -> (select cc (add x, 1), x)
1431 // (add (sext cc), x) -> (select cc (add x, -1), x)
1432 //
1433 // These transformations eventually create predicated instructions.
1436  bool AllOnes) {
1437  SelectionDAG &DAG = DCI.DAG;
1438  EVT VT = N->getValueType(0);
1439  SDValue NonConstantVal;
1440  SDValue CCOp;
1441  bool SwapSelectOps;
1442  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1443  NonConstantVal, DAG))
1444  return SDValue();
1445 
1446  // Slct is now know to be the desired identity constant when CC is true.
1447  SDValue TrueVal = OtherOp;
1448  SDValue FalseVal =
1449  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1450  // Unless SwapSelectOps says CC should be false.
1451  if (SwapSelectOps)
1452  std::swap(TrueVal, FalseVal);
1453 
1454  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1455 }
1456 
1457 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1458 static SDValue
1460  bool AllOnes) {
1461  SDValue N0 = N->getOperand(0);
1462  SDValue N1 = N->getOperand(1);
1463  if (N0.getNode()->hasOneUse())
1464  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1465  return Result;
1466  if (N1.getNode()->hasOneUse())
1467  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1468  return Result;
1469  return SDValue();
1470 }
1471 
1472 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1475  SDValue N0 = N->getOperand(0);
1476  SDValue N1 = N->getOperand(1);
1477 
1478  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1479  if (N1.getNode()->hasOneUse())
1480  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1481  return Result;
1482 
1483  return SDValue();
1484 }
1485 
1487  DAGCombinerInfo &DCI) const {
1488  switch (N->getOpcode()) {
1489  default:
1490  break;
1491  case ISD::ADD:
1492  case ISD::OR:
1493  case ISD::XOR:
1494  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1495  case ISD::AND:
1496  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1497  case ISD::SUB:
1498  return PerformSUBCombine(N, DCI);
1499  }
1500 
1501  return SDValue();
1502 }
1503 
1505  const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1506  const SelectionDAG &DAG, unsigned Depth) const {
1507  unsigned BitWidth = Known.getBitWidth();
1508  switch (Op.getOpcode()) {
1509  default:
1510  break;
1511  case LanaiISD::SETCC:
1512  Known = KnownBits(BitWidth);
1513  Known.Zero.setBits(1, BitWidth);
1514  break;
1515  case LanaiISD::SELECT_CC:
1516  KnownBits Known2;
1517  DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
1518  DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
1519  Known.Zero &= Known2.Zero;
1520  Known.One &= Known2.One;
1521  break;
1522  }
1523 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:555
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1397
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:898
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:666
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:298
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:911
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
bool isMemLoc() const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:511
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:813
bool hasOneUse() const
Return true if there is exactly one use of this node.
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
Shift and rotation operations.
Definition: ISDOpcodes.h:379
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:446
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:662
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
int64_t getSExtValue() const
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:558
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
amdgpu Simplify well known AMD library false Value * Callee
unsigned getByValSize() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:695
const SDValue & getOperand(unsigned Num) const
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:120
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:686
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
static unsigned NumFixedArgs
Extended Value Type.
Definition: ValueTypes.h:34
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:611
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:301
virtual TargetLoweringObjectFile * getObjFileLowering() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:611
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:382
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:145
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:691
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
void computeKnownBits(SDValue Op, KnownBits &Known, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
unsigned getRARegister() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1213
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
unsigned getOpcode() const
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:338
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, and op #2 is a carry value...
Definition: ISDOpcodes.h:421
const GlobalObject * getBaseObject() const
Definition: Globals.cpp:256
bool isRegLoc() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
LLVM Value Representation.
Definition: Value.h:73
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue getRegister(unsigned Reg, EVT VT)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:118
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:442
const SDValue & getOperand(unsigned i) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const LanaiRegisterInfo * getRegisterInfo() const override
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:600
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:355
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:590