LLVM  8.0.0svn
LanaiISelLowering.cpp
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1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "LanaiISelLowering.h"
15 #include "Lanai.h"
16 #include "LanaiCondCode.h"
18 #include "LanaiSubtarget.h"
19 #include "LanaiTargetObjectFile.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/KnownBits.h"
50 #include <cassert>
51 #include <cmath>
52 #include <cstdint>
53 #include <cstdlib>
54 #include <utility>
55 
56 #define DEBUG_TYPE "lanai-lower"
57 
58 using namespace llvm;
59 
60 // Limit on number of instructions the lowered multiplication may have before a
61 // call to the library function should be generated instead. The threshold is
62 // currently set to 14 as this was the smallest threshold that resulted in all
63 // constant multiplications being lowered. A threshold of 5 covered all cases
64 // except for one multiplication which required 14. mulsi3 requires 16
65 // instructions (including the prologue and epilogue but excluding instructions
66 // at call site). Until we can inline mulsi3, generating at most 14 instructions
67 // will be faster than invoking mulsi3.
69  "lanai-constant-mul-threshold", cl::Hidden,
70  cl::desc("Maximum number of instruction to generate when lowering constant "
71  "multiplication instead of calling library function [default=14]"),
72  cl::init(14));
73 
75  const LanaiSubtarget &STI)
76  : TargetLowering(TM) {
77  // Set up the register classes.
78  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
79 
80  // Compute derived properties from the register classes
81  TRI = STI.getRegisterInfo();
83 
85 
92 
97 
101 
106 
113 
119 
125 
130 
134 
135  // Extended load operations for i1 types must be promoted
136  for (MVT VT : MVT::integer_valuetypes()) {
140  }
141 
147 
148  // Function alignments (log2)
151 
152  setJumpIsExpensive(true);
153 
154  // TODO: Setting the minimum jump table entries needed before a
155  // switch is transformed to a jump table to 100 to avoid creating jump tables
156  // as this was causing bad performance compared to a large group of if
157  // statements. Re-evaluate this on new benchmarks.
159 
160  // Use fast calling convention for library functions.
161  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
162  setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
163  }
164 
165  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
167  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
169  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
171 
172  // Booleans always contain 0 or 1.
174 }
175 
177  SelectionDAG &DAG) const {
178  switch (Op.getOpcode()) {
179  case ISD::MUL:
180  return LowerMUL(Op, DAG);
181  case ISD::BR_CC:
182  return LowerBR_CC(Op, DAG);
183  case ISD::ConstantPool:
184  return LowerConstantPool(Op, DAG);
185  case ISD::GlobalAddress:
186  return LowerGlobalAddress(Op, DAG);
187  case ISD::BlockAddress:
188  return LowerBlockAddress(Op, DAG);
189  case ISD::JumpTable:
190  return LowerJumpTable(Op, DAG);
191  case ISD::SELECT_CC:
192  return LowerSELECT_CC(Op, DAG);
193  case ISD::SETCC:
194  return LowerSETCC(Op, DAG);
195  case ISD::SHL_PARTS:
196  return LowerSHL_PARTS(Op, DAG);
197  case ISD::SRL_PARTS:
198  return LowerSRL_PARTS(Op, DAG);
199  case ISD::VASTART:
200  return LowerVASTART(Op, DAG);
202  return LowerDYNAMIC_STACKALLOC(Op, DAG);
203  case ISD::RETURNADDR:
204  return LowerRETURNADDR(Op, DAG);
205  case ISD::FRAMEADDR:
206  return LowerFRAMEADDR(Op, DAG);
207  default:
208  llvm_unreachable("unimplemented operand");
209  }
210 }
211 
212 //===----------------------------------------------------------------------===//
213 // Lanai Inline Assembly Support
214 //===----------------------------------------------------------------------===//
215 
216 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
217  SelectionDAG & /*DAG*/) const {
218  // Only unallocatable registers should be matched here.
219  unsigned Reg = StringSwitch<unsigned>(RegName)
220  .Case("pc", Lanai::PC)
221  .Case("sp", Lanai::SP)
222  .Case("fp", Lanai::FP)
223  .Case("rr1", Lanai::RR1)
224  .Case("r10", Lanai::R10)
225  .Case("rr2", Lanai::RR2)
226  .Case("r11", Lanai::R11)
227  .Case("rca", Lanai::RCA)
228  .Default(0);
229 
230  if (Reg)
231  return Reg;
232  report_fatal_error("Invalid register name global variable");
233 }
234 
235 std::pair<unsigned, const TargetRegisterClass *>
237  StringRef Constraint,
238  MVT VT) const {
239  if (Constraint.size() == 1)
240  // GCC Constraint Letters
241  switch (Constraint[0]) {
242  case 'r': // GENERAL_REGS
243  return std::make_pair(0U, &Lanai::GPRRegClass);
244  default:
245  break;
246  }
247 
248  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
249 }
250 
251 // Examine constraint type and operand type and determine a weight value.
252 // This object must already have been set up with the operand type
253 // and the current alternative constraint selected.
256  AsmOperandInfo &Info, const char *Constraint) const {
257  ConstraintWeight Weight = CW_Invalid;
258  Value *CallOperandVal = Info.CallOperandVal;
259  // If we don't have a value, we can't do a match,
260  // but allow it at the lowest weight.
261  if (CallOperandVal == nullptr)
262  return CW_Default;
263  // Look at the constraint type.
264  switch (*Constraint) {
265  case 'I': // signed 16 bit immediate
266  case 'J': // integer zero
267  case 'K': // unsigned 16 bit immediate
268  case 'L': // immediate in the range 0 to 31
269  case 'M': // signed 32 bit immediate where lower 16 bits are 0
270  case 'N': // signed 26 bit immediate
271  case 'O': // integer zero
272  if (isa<ConstantInt>(CallOperandVal))
273  Weight = CW_Constant;
274  break;
275  default:
276  Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
277  break;
278  }
279  return Weight;
280 }
281 
282 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
283 // vector. If it is invalid, don't add anything to Ops.
285  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
286  SelectionDAG &DAG) const {
287  SDValue Result(nullptr, 0);
288 
289  // Only support length 1 constraints for now.
290  if (Constraint.length() > 1)
291  return;
292 
293  char ConstraintLetter = Constraint[0];
294  switch (ConstraintLetter) {
295  case 'I': // Signed 16 bit constant
296  // If this fails, the parent routine will give an error
297  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
298  if (isInt<16>(C->getSExtValue())) {
299  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
300  Op.getValueType());
301  break;
302  }
303  }
304  return;
305  case 'J': // integer zero
306  case 'O':
307  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
308  if (C->getZExtValue() == 0) {
309  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
310  break;
311  }
312  }
313  return;
314  case 'K': // unsigned 16 bit immediate
315  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
316  if (isUInt<16>(C->getZExtValue())) {
317  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
318  Op.getValueType());
319  break;
320  }
321  }
322  return;
323  case 'L': // immediate in the range 0 to 31
324  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
325  if (C->getZExtValue() <= 31) {
326  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
327  Op.getValueType());
328  break;
329  }
330  }
331  return;
332  case 'M': // signed 32 bit immediate where lower 16 bits are 0
333  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
334  int64_t Val = C->getSExtValue();
335  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
336  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
337  break;
338  }
339  }
340  return;
341  case 'N': // signed 26 bit immediate
342  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
343  int64_t Val = C->getSExtValue();
344  if ((Val >= -33554432) && (Val <= 33554431)) {
345  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
346  break;
347  }
348  }
349  return;
350  default:
351  break; // This will fall through to the generic implementation
352  }
353 
354  if (Result.getNode()) {
355  Ops.push_back(Result);
356  return;
357  }
358 
359  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
360 }
361 
362 //===----------------------------------------------------------------------===//
363 // Calling Convention Implementation
364 //===----------------------------------------------------------------------===//
365 
366 #include "LanaiGenCallingConv.inc"
367 
368 static unsigned NumFixedArgs;
369 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
370  CCValAssign::LocInfo LocInfo,
371  ISD::ArgFlagsTy ArgFlags, CCState &State) {
372  // Handle fixed arguments with default CC.
373  // Note: Both the default and fast CC handle VarArg the same and hence the
374  // calling convention of the function is not considered here.
375  if (ValNo < NumFixedArgs) {
376  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
377  }
378 
379  // Promote i8/i16 args to i32
380  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
381  LocVT = MVT::i32;
382  if (ArgFlags.isSExt())
383  LocInfo = CCValAssign::SExt;
384  else if (ArgFlags.isZExt())
385  LocInfo = CCValAssign::ZExt;
386  else
387  LocInfo = CCValAssign::AExt;
388  }
389 
390  // VarArgs get passed on stack
391  unsigned Offset = State.AllocateStack(4, 4);
392  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
393  return false;
394 }
395 
396 SDValue LanaiTargetLowering::LowerFormalArguments(
397  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
398  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
399  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
400  switch (CallConv) {
401  case CallingConv::C:
402  case CallingConv::Fast:
403  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
404  default:
405  report_fatal_error("Unsupported calling convention");
406  }
407 }
408 
409 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
410  SmallVectorImpl<SDValue> &InVals) const {
411  SelectionDAG &DAG = CLI.DAG;
412  SDLoc &DL = CLI.DL;
414  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
416  SDValue Chain = CLI.Chain;
417  SDValue Callee = CLI.Callee;
418  bool &IsTailCall = CLI.IsTailCall;
419  CallingConv::ID CallConv = CLI.CallConv;
420  bool IsVarArg = CLI.IsVarArg;
421 
422  // Lanai target does not yet support tail call optimization.
423  IsTailCall = false;
424 
425  switch (CallConv) {
426  case CallingConv::Fast:
427  case CallingConv::C:
428  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
429  OutVals, Ins, DL, DAG, InVals);
430  default:
431  report_fatal_error("Unsupported calling convention");
432  }
433 }
434 
435 // LowerCCCArguments - transform physical registers into virtual registers and
436 // generate load operations for arguments places on the stack.
437 SDValue LanaiTargetLowering::LowerCCCArguments(
438  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
439  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
440  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
442  MachineFrameInfo &MFI = MF.getFrameInfo();
443  MachineRegisterInfo &RegInfo = MF.getRegInfo();
445 
446  // Assign locations to all of the incoming arguments.
448  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
449  *DAG.getContext());
450  if (CallConv == CallingConv::Fast) {
451  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
452  } else {
453  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
454  }
455 
456  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
457  CCValAssign &VA = ArgLocs[i];
458  if (VA.isRegLoc()) {
459  // Arguments passed in registers
460  EVT RegVT = VA.getLocVT();
461  switch (RegVT.getSimpleVT().SimpleTy) {
462  case MVT::i32: {
463  unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
464  RegInfo.addLiveIn(VA.getLocReg(), VReg);
465  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
466 
467  // If this is an 8/16-bit value, it is really passed promoted to 32
468  // bits. Insert an assert[sz]ext to capture this, then truncate to the
469  // right size.
470  if (VA.getLocInfo() == CCValAssign::SExt)
471  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
472  DAG.getValueType(VA.getValVT()));
473  else if (VA.getLocInfo() == CCValAssign::ZExt)
474  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
475  DAG.getValueType(VA.getValVT()));
476 
477  if (VA.getLocInfo() != CCValAssign::Full)
478  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
479 
480  InVals.push_back(ArgValue);
481  break;
482  }
483  default:
484  LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
485  << RegVT.getEVTString() << "\n");
486  llvm_unreachable("unhandled argument type");
487  }
488  } else {
489  // Sanity check
490  assert(VA.isMemLoc());
491  // Load the argument to a virtual register
492  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
493  // Check that the argument fits in stack slot
494  if (ObjSize > 4) {
495  errs() << "LowerFormalArguments Unhandled argument type: "
496  << EVT(VA.getLocVT()).getEVTString() << "\n";
497  }
498  // Create the frame index object for this incoming parameter...
499  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
500 
501  // Create the SelectionDAG nodes corresponding to a load
502  // from this parameter
503  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
504  InVals.push_back(DAG.getLoad(
505  VA.getLocVT(), DL, Chain, FIN,
507  }
508  }
509 
510  // The Lanai ABI for returning structs by value requires that we copy
511  // the sret argument into rv for the return. Save the argument into
512  // a virtual register so that we can access it from the return points.
513  if (MF.getFunction().hasStructRetAttr()) {
514  unsigned Reg = LanaiMFI->getSRetReturnReg();
515  if (!Reg) {
517  LanaiMFI->setSRetReturnReg(Reg);
518  }
519  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
520  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
521  }
522 
523  if (IsVarArg) {
524  // Record the frame index of the first variable argument
525  // which is a value necessary to VASTART.
526  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
527  LanaiMFI->setVarArgsFrameIndex(FI);
528  }
529 
530  return Chain;
531 }
532 
533 SDValue
534 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
535  bool IsVarArg,
537  const SmallVectorImpl<SDValue> &OutVals,
538  const SDLoc &DL, SelectionDAG &DAG) const {
539  // CCValAssign - represent the assignment of the return value to a location
541 
542  // CCState - Info about the registers and stack slot.
543  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
544  *DAG.getContext());
545 
546  // Analize return values.
547  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
548 
549  SDValue Flag;
550  SmallVector<SDValue, 4> RetOps(1, Chain);
551 
552  // Copy the result values into the output registers.
553  for (unsigned i = 0; i != RVLocs.size(); ++i) {
554  CCValAssign &VA = RVLocs[i];
555  assert(VA.isRegLoc() && "Can only return in registers!");
556 
557  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
558 
559  // Guarantee that all emitted copies are stuck together with flags.
560  Flag = Chain.getValue(1);
561  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
562  }
563 
564  // The Lanai ABI for returning structs by value requires that we copy
565  // the sret argument into rv for the return. We saved the argument into
566  // a virtual register in the entry block, so now we copy the value out
567  // and into rv.
571  unsigned Reg = LanaiMFI->getSRetReturnReg();
572  assert(Reg &&
573  "SRetReturnReg should have been set in LowerFormalArguments().");
574  SDValue Val =
575  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
576 
577  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
578  Flag = Chain.getValue(1);
579  RetOps.push_back(
580  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
581  }
582 
583  RetOps[0] = Chain; // Update chain
584 
585  unsigned Opc = LanaiISD::RET_FLAG;
586  if (Flag.getNode())
587  RetOps.push_back(Flag);
588 
589  // Return Void
590  return DAG.getNode(Opc, DL, MVT::Other,
591  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
592 }
593 
594 // LowerCCCCallTo - functions arguments are copied from virtual regs to
595 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
596 SDValue LanaiTargetLowering::LowerCCCCallTo(
597  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
598  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
599  const SmallVectorImpl<SDValue> &OutVals,
600  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
601  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
602  // Analyze operands of the call, assigning locations to each operand.
604  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
605  *DAG.getContext());
608 
609  NumFixedArgs = 0;
610  if (IsVarArg && G) {
611  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
612  if (CalleeFn)
613  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
614  }
615  if (NumFixedArgs)
616  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
617  else {
618  if (CallConv == CallingConv::Fast)
619  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
620  else
621  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
622  }
623 
624  // Get a count of how many bytes are to be pushed on the stack.
625  unsigned NumBytes = CCInfo.getNextStackOffset();
626 
627  // Create local copies for byval args.
628  SmallVector<SDValue, 8> ByValArgs;
629  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
630  ISD::ArgFlagsTy Flags = Outs[I].Flags;
631  if (!Flags.isByVal())
632  continue;
633 
634  SDValue Arg = OutVals[I];
635  unsigned Size = Flags.getByValSize();
636  unsigned Align = Flags.getByValAlign();
637 
638  int FI = MFI.CreateStackObject(Size, Align, false);
639  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
640  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
641 
642  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
643  /*IsVolatile=*/false,
644  /*AlwaysInline=*/false,
645  /*isTailCall=*/false, MachinePointerInfo(),
647  ByValArgs.push_back(FIPtr);
648  }
649 
650  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
651 
653  SmallVector<SDValue, 12> MemOpChains;
654  SDValue StackPtr;
655 
656  // Walk the register/memloc assignments, inserting copies/loads.
657  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
658  CCValAssign &VA = ArgLocs[I];
659  SDValue Arg = OutVals[I];
660  ISD::ArgFlagsTy Flags = Outs[I].Flags;
661 
662  // Promote the value if needed.
663  switch (VA.getLocInfo()) {
664  case CCValAssign::Full:
665  break;
666  case CCValAssign::SExt:
667  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
668  break;
669  case CCValAssign::ZExt:
670  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
671  break;
672  case CCValAssign::AExt:
673  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
674  break;
675  default:
676  llvm_unreachable("Unknown loc info!");
677  }
678 
679  // Use local copy if it is a byval arg.
680  if (Flags.isByVal())
681  Arg = ByValArgs[J++];
682 
683  // Arguments that can be passed on register must be kept at RegsToPass
684  // vector
685  if (VA.isRegLoc()) {
686  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
687  } else {
688  assert(VA.isMemLoc());
689 
690  if (StackPtr.getNode() == nullptr)
691  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
692  getPointerTy(DAG.getDataLayout()));
693 
694  SDValue PtrOff =
695  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
696  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
697 
698  MemOpChains.push_back(
699  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
700  }
701  }
702 
703  // Transform all store nodes into one single node because all store nodes are
704  // independent of each other.
705  if (!MemOpChains.empty())
706  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
707  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
708 
709  SDValue InFlag;
710 
711  // Build a sequence of copy-to-reg nodes chained together with token chain and
712  // flag operands which copy the outgoing args into registers. The InFlag in
713  // necessary since all emitted instructions must be stuck together.
714  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
715  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
716  RegsToPass[I].second, InFlag);
717  InFlag = Chain.getValue(1);
718  }
719 
720  // If the callee is a GlobalAddress node (quite common, every direct call is)
721  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
722  // Likewise ExternalSymbol -> TargetExternalSymbol.
723  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
724  if (G) {
725  Callee = DAG.getTargetGlobalAddress(
726  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
727  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
728  Callee = DAG.getTargetExternalSymbol(
729  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
730  }
731 
732  // Returns a chain & a flag for retval copy to use.
733  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
735  Ops.push_back(Chain);
736  Ops.push_back(Callee);
737 
738  // Add a register mask operand representing the call-preserved registers.
739  // TODO: Should return-twice functions be handled?
740  const uint32_t *Mask =
741  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
742  assert(Mask && "Missing call preserved mask for calling convention");
743  Ops.push_back(DAG.getRegisterMask(Mask));
744 
745  // Add argument registers to the end of the list so that they are
746  // known live into the call.
747  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
748  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
749  RegsToPass[I].second.getValueType()));
750 
751  if (InFlag.getNode())
752  Ops.push_back(InFlag);
753 
754  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
755  ArrayRef<SDValue>(&Ops[0], Ops.size()));
756  InFlag = Chain.getValue(1);
757 
758  // Create the CALLSEQ_END node.
759  Chain = DAG.getCALLSEQ_END(
760  Chain,
761  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
762  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
763  DL);
764  InFlag = Chain.getValue(1);
765 
766  // Handle result values, copying them out of physregs into vregs that we
767  // return.
768  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
769  InVals);
770 }
771 
772 // LowerCallResult - Lower the result values of a call into the
773 // appropriate copies out of appropriate physical registers.
774 SDValue LanaiTargetLowering::LowerCallResult(
775  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
776  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
777  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
778  // Assign locations to each value returned by this call.
780  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
781  *DAG.getContext());
782 
783  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
784 
785  // Copy all of the result registers out of their specified physreg.
786  for (unsigned I = 0; I != RVLocs.size(); ++I) {
787  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
788  RVLocs[I].getValVT(), InFlag)
789  .getValue(1);
790  InFlag = Chain.getValue(2);
791  InVals.push_back(Chain.getValue(0));
792  }
793 
794  return Chain;
795 }
796 
797 //===----------------------------------------------------------------------===//
798 // Custom Lowerings
799 //===----------------------------------------------------------------------===//
800 
802  SDValue &RHS, SelectionDAG &DAG) {
803  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
804 
805  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
806  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
807  // and Lanai only supports integer comparisons, so only provide definitions
808  // for them.
809  switch (SetCCOpcode) {
810  case ISD::SETEQ:
811  return LPCC::ICC_EQ;
812  case ISD::SETGT:
813  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
814  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
815  // X > -1 -> X >= 0 -> is_plus(X)
816  RHS = DAG.getConstant(0, DL, RHS.getValueType());
817  return LPCC::ICC_PL;
818  }
819  return LPCC::ICC_GT;
820  case ISD::SETUGT:
821  return LPCC::ICC_UGT;
822  case ISD::SETLT:
823  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
824  if (RHSC->getZExtValue() == 0)
825  // X < 0 -> is_minus(X)
826  return LPCC::ICC_MI;
827  return LPCC::ICC_LT;
828  case ISD::SETULT:
829  return LPCC::ICC_ULT;
830  case ISD::SETLE:
831  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
832  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
833  // X <= -1 -> X < 0 -> is_minus(X)
834  RHS = DAG.getConstant(0, DL, RHS.getValueType());
835  return LPCC::ICC_MI;
836  }
837  return LPCC::ICC_LE;
838  case ISD::SETULE:
839  return LPCC::ICC_ULE;
840  case ISD::SETGE:
841  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
842  if (RHSC->getZExtValue() == 0)
843  // X >= 0 -> is_plus(X)
844  return LPCC::ICC_PL;
845  return LPCC::ICC_GE;
846  case ISD::SETUGE:
847  return LPCC::ICC_UGE;
848  case ISD::SETNE:
849  return LPCC::ICC_NE;
850  case ISD::SETONE:
851  case ISD::SETUNE:
852  case ISD::SETOGE:
853  case ISD::SETOLE:
854  case ISD::SETOLT:
855  case ISD::SETOGT:
856  case ISD::SETOEQ:
857  case ISD::SETUEQ:
858  case ISD::SETO:
859  case ISD::SETUO:
860  llvm_unreachable("Unsupported comparison.");
861  default:
862  llvm_unreachable("Unknown integer condition code!");
863  }
864 }
865 
867  SDValue Chain = Op.getOperand(0);
868  SDValue Cond = Op.getOperand(1);
869  SDValue LHS = Op.getOperand(2);
870  SDValue RHS = Op.getOperand(3);
871  SDValue Dest = Op.getOperand(4);
872  SDLoc DL(Op);
873 
874  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
875  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
876  SDValue Flag =
877  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
878 
879  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
880  TargetCC, Flag);
881 }
882 
884  EVT VT = Op->getValueType(0);
885  if (VT != MVT::i32)
886  return SDValue();
887 
889  if (!C)
890  return SDValue();
891 
892  int64_t MulAmt = C->getSExtValue();
893  int32_t HighestOne = -1;
894  uint32_t NonzeroEntries = 0;
895  int SignedDigit[32] = {0};
896 
897  // Convert to non-adjacent form (NAF) signed-digit representation.
898  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
899  // minimal Hamming weight representation of a number (on average 1/3 of the
900  // digits will be non-zero vs 1/2 for regular binary representation). And as
901  // the non-zero digits will be the only digits contributing to the instruction
902  // count, this is desirable. The next loop converts it to NAF (following the
903  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
904  // choosing the non-zero coefficients such that the resulting quotient is
905  // divisible by 2 which will cause the next coefficient to be zero.
906  int64_t E = std::abs(MulAmt);
907  int S = (MulAmt < 0 ? -1 : 1);
908  int I = 0;
909  while (E > 0) {
910  int ZI = 0;
911  if (E % 2 == 1) {
912  ZI = 2 - (E % 4);
913  if (ZI != 0)
914  ++NonzeroEntries;
915  }
916  SignedDigit[I] = S * ZI;
917  if (SignedDigit[I] == 1)
918  HighestOne = I;
919  E = (E - ZI) / 2;
920  ++I;
921  }
922 
923  // Compute number of instructions required. Due to differences in lowering
924  // between the different processors this count is not exact.
925  // Start by assuming a shift and a add/sub for every non-zero entry (hence
926  // every non-zero entry requires 1 shift and 1 add/sub except for the first
927  // entry).
928  int32_t InstrRequired = 2 * NonzeroEntries - 1;
929  // Correct possible over-adding due to shift by 0 (which is not emitted).
930  if (std::abs(MulAmt) % 2 == 1)
931  --InstrRequired;
932  // Return if the form generated would exceed the instruction threshold.
933  if (InstrRequired > LanaiLowerConstantMulThreshold)
934  return SDValue();
935 
936  SDValue Res;
937  SDLoc DL(Op);
938  SDValue V = Op->getOperand(0);
939 
940  // Initialize the running sum. Set the running sum to the maximal shifted
941  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
942  // term NAF).
943  if (HighestOne == -1)
944  Res = DAG.getConstant(0, DL, MVT::i32);
945  else {
946  Res = DAG.getNode(ISD::SHL, DL, VT, V,
947  DAG.getConstant(HighestOne, DL, MVT::i32));
948  SignedDigit[HighestOne] = 0;
949  }
950 
951  // Assemble multiplication from shift, add, sub using NAF form and running
952  // sum.
953  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
954  ++I) {
955  if (SignedDigit[I] == 0)
956  continue;
957 
958  // Shifted multiplicand (v<<i).
959  SDValue Op =
960  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
961  if (SignedDigit[I] == 1)
962  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
963  else if (SignedDigit[I] == -1)
964  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
965  }
966  return Res;
967 }
968 
970  SDValue LHS = Op.getOperand(0);
971  SDValue RHS = Op.getOperand(1);
972  SDValue Cond = Op.getOperand(2);
973  SDLoc DL(Op);
974 
975  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
976  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
977  SDValue Flag =
978  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
979 
980  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
981 }
982 
984  SelectionDAG &DAG) const {
985  SDValue LHS = Op.getOperand(0);
986  SDValue RHS = Op.getOperand(1);
987  SDValue TrueV = Op.getOperand(2);
988  SDValue FalseV = Op.getOperand(3);
989  SDValue Cond = Op.getOperand(4);
990  SDLoc DL(Op);
991 
992  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
993  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
994  SDValue Flag =
995  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
996 
997  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
998  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
999  Flag);
1000 }
1001 
1003  MachineFunction &MF = DAG.getMachineFunction();
1005 
1006  SDLoc DL(Op);
1007  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1008  getPointerTy(DAG.getDataLayout()));
1009 
1010  // vastart just stores the address of the VarArgsFrameIndex slot into the
1011  // memory location argument.
1012  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1013  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1014  MachinePointerInfo(SV));
1015 }
1016 
1018  SelectionDAG &DAG) const {
1019  SDValue Chain = Op.getOperand(0);
1020  SDValue Size = Op.getOperand(1);
1021  SDLoc DL(Op);
1022 
1023  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1024 
1025  // Get a reference to the stack pointer.
1026  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1027 
1028  // Subtract the dynamic size from the actual stack size to
1029  // obtain the new stack size.
1030  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1031 
1032  // For Lanai, the outgoing memory arguments area should be on top of the
1033  // alloca area on the stack i.e., the outgoing memory arguments should be
1034  // at a lower address than the alloca area. Move the alloca area down the
1035  // stack by adding back the space reserved for outgoing arguments to SP
1036  // here.
1037  //
1038  // We do not know what the size of the outgoing args is at this point.
1039  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1040  // stack pointer. We replace this instruction with on that has the correct,
1041  // known offset in emitPrologue().
1042  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1043 
1044  // The Sub result contains the new stack start address, so it
1045  // must be placed in the stack pointer register.
1046  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1047 
1048  SDValue Ops[2] = {ArgAdjust, CopyChain};
1049  return DAG.getMergeValues(Ops, DL);
1050 }
1051 
1053  SelectionDAG &DAG) const {
1054  MachineFunction &MF = DAG.getMachineFunction();
1055  MachineFrameInfo &MFI = MF.getFrameInfo();
1056  MFI.setReturnAddressIsTaken(true);
1057 
1058  EVT VT = Op.getValueType();
1059  SDLoc DL(Op);
1060  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1061  if (Depth) {
1062  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1063  const unsigned Offset = -4;
1064  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1065  DAG.getIntPtrConstant(Offset, DL));
1066  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1067  }
1068 
1069  // Return the link register, which contains the return address.
1070  // Mark it an implicit live-in.
1071  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1072  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1073 }
1074 
1076  SelectionDAG &DAG) const {
1078  MFI.setFrameAddressIsTaken(true);
1079 
1080  EVT VT = Op.getValueType();
1081  SDLoc DL(Op);
1082  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1083  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1084  while (Depth--) {
1085  const unsigned Offset = -8;
1086  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1087  DAG.getIntPtrConstant(Offset, DL));
1088  FrameAddr =
1089  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1090  }
1091  return FrameAddr;
1092 }
1093 
1094 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1095  switch (Opcode) {
1096  case LanaiISD::ADJDYNALLOC:
1097  return "LanaiISD::ADJDYNALLOC";
1098  case LanaiISD::RET_FLAG:
1099  return "LanaiISD::RET_FLAG";
1100  case LanaiISD::CALL:
1101  return "LanaiISD::CALL";
1102  case LanaiISD::SELECT_CC:
1103  return "LanaiISD::SELECT_CC";
1104  case LanaiISD::SETCC:
1105  return "LanaiISD::SETCC";
1106  case LanaiISD::SUBBF:
1107  return "LanaiISD::SUBBF";
1108  case LanaiISD::SET_FLAG:
1109  return "LanaiISD::SET_FLAG";
1110  case LanaiISD::BR_CC:
1111  return "LanaiISD::BR_CC";
1112  case LanaiISD::Wrapper:
1113  return "LanaiISD::Wrapper";
1114  case LanaiISD::HI:
1115  return "LanaiISD::HI";
1116  case LanaiISD::LO:
1117  return "LanaiISD::LO";
1118  case LanaiISD::SMALL:
1119  return "LanaiISD::SMALL";
1120  default:
1121  return nullptr;
1122  }
1123 }
1124 
1126  SelectionDAG &DAG) const {
1127  SDLoc DL(Op);
1128  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1129  const Constant *C = N->getConstVal();
1130  const LanaiTargetObjectFile *TLOF =
1131  static_cast<const LanaiTargetObjectFile *>(
1133 
1134  // If the code model is small or constant will be placed in the small section,
1135  // then assume address will fit in 21-bits.
1137  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1140  return DAG.getNode(ISD::OR, DL, MVT::i32,
1141  DAG.getRegister(Lanai::R0, MVT::i32),
1142  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1143  } else {
1144  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1145  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1146 
1148  N->getOffset(), OpFlagHi);
1150  N->getOffset(), OpFlagLo);
1151  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1152  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1153  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1154  return Result;
1155  }
1156 }
1157 
1159  SelectionDAG &DAG) const {
1160  SDLoc DL(Op);
1161  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1162  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1163 
1164  const LanaiTargetObjectFile *TLOF =
1165  static_cast<const LanaiTargetObjectFile *>(
1167 
1168  // If the code model is small or global variable will be placed in the small
1169  // section, then assume address will fit in 21-bits.
1170  const GlobalObject *GO = GV->getBaseObject();
1171  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1173  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1174  return DAG.getNode(ISD::OR, DL, MVT::i32,
1175  DAG.getRegister(Lanai::R0, MVT::i32),
1176  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1177  } else {
1178  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1179  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1180 
1181  // Create the TargetGlobalAddress node, folding in the constant offset.
1183  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1185  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1186  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1187  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1188  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1189  }
1190 }
1191 
1193  SelectionDAG &DAG) const {
1194  SDLoc DL(Op);
1195  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1196 
1197  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1198  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1199 
1200  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1201  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1202  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1203  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1204  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1205  return Result;
1206 }
1207 
1209  SelectionDAG &DAG) const {
1210  SDLoc DL(Op);
1211  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1212 
1213  // If the code model is small assume address will fit in 21-bits.
1217  return DAG.getNode(ISD::OR, DL, MVT::i32,
1218  DAG.getRegister(Lanai::R0, MVT::i32),
1219  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1220  } else {
1221  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1222  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1223 
1225  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1227  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1228  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1229  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1230  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1231  return Result;
1232  }
1233 }
1234 
1236  SelectionDAG &DAG) const {
1237  EVT VT = Op.getValueType();
1238  unsigned VTBits = VT.getSizeInBits();
1239  SDLoc dl(Op);
1240  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1241  SDValue ShOpLo = Op.getOperand(0);
1242  SDValue ShOpHi = Op.getOperand(1);
1243  SDValue ShAmt = Op.getOperand(2);
1244 
1245  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1246  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1247  // HiBitsForHi = ShOpHi << ShAmt
1248  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1249  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1250  // return (Hi << 32) | Lo;
1251 
1252  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1253  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1254  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1255 
1256  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1257  // wanted 0, so CSEL it directly.
1258  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1259  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1260  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1261 
1262  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1263  DAG.getConstant(VTBits, dl, MVT::i32));
1264  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1265  SDValue HiForNormalShift =
1266  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1267 
1268  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1269 
1270  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1271  SDValue Hi =
1272  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1273 
1274  // Lanai shifts of larger than register sizes are wrapped rather than
1275  // clamped, so we can't just emit "lo << b" if b is too big.
1276  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1277  SDValue Lo = DAG.getSelect(
1278  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1279 
1280  SDValue Ops[2] = {Lo, Hi};
1281  return DAG.getMergeValues(Ops, dl);
1282 }
1283 
1285  SelectionDAG &DAG) const {
1286  MVT VT = Op.getSimpleValueType();
1287  unsigned VTBits = VT.getSizeInBits();
1288  SDLoc dl(Op);
1289  SDValue ShOpLo = Op.getOperand(0);
1290  SDValue ShOpHi = Op.getOperand(1);
1291  SDValue ShAmt = Op.getOperand(2);
1292 
1293  // Performs the following for a >> b:
1294  // unsigned r_high = a_high >> b;
1295  // r_high = (32 - b <= 0) ? 0 : r_high;
1296  //
1297  // unsigned r_low = a_low >> b;
1298  // r_low = (32 - b <= 0) ? r_high : r_low;
1299  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1300  // return (unsigned long long)r_high << 32 | r_low;
1301  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1302  // mask the shift amount.
1303 
1304  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1305  SDValue NegatedPlus32 = DAG.getNode(
1306  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1307  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1308 
1309  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1310  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1311 
1312  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1313  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1314  SDValue CarryBits =
1315  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1316  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1317  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1318  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1319 
1320  SDValue Ops[2] = {Lo, Hi};
1321  return DAG.getMergeValues(Ops, dl);
1322 }
1323 
1324 // Helper function that checks if N is a null or all ones constant.
1325 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1326  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1327 }
1328 
1329 // Return true if N is conditionally 0 or all ones.
1330 // Detects these expressions where cc is an i1 value:
1331 //
1332 // (select cc 0, y) [AllOnes=0]
1333 // (select cc y, 0) [AllOnes=0]
1334 // (zext cc) [AllOnes=0]
1335 // (sext cc) [AllOnes=0/1]
1336 // (select cc -1, y) [AllOnes=1]
1337 // (select cc y, -1) [AllOnes=1]
1338 //
1339 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1340 // all ones operand (AllOnes true).
1341 // * Invert is set when N is the all zero/ones constant when CC is false.
1342 // * OtherOp is set to the alternative value of N.
1343 //
1344 // For example, for (select cc X, Y) and AllOnes = 0 if:
1345 // * X = 0, Invert = False and OtherOp = Y
1346 // * Y = 0, Invert = True and OtherOp = X
1347 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1348  bool &Invert, SDValue &OtherOp,
1349  SelectionDAG &DAG) {
1350  switch (N->getOpcode()) {
1351  default:
1352  return false;
1353  case ISD::SELECT: {
1354  CC = N->getOperand(0);
1355  SDValue N1 = N->getOperand(1);
1356  SDValue N2 = N->getOperand(2);
1357  if (isZeroOrAllOnes(N1, AllOnes)) {
1358  Invert = false;
1359  OtherOp = N2;
1360  return true;
1361  }
1362  if (isZeroOrAllOnes(N2, AllOnes)) {
1363  Invert = true;
1364  OtherOp = N1;
1365  return true;
1366  }
1367  return false;
1368  }
1369  case ISD::ZERO_EXTEND: {
1370  // (zext cc) can never be the all ones value.
1371  if (AllOnes)
1372  return false;
1373  CC = N->getOperand(0);
1374  if (CC.getValueType() != MVT::i1)
1375  return false;
1376  SDLoc dl(N);
1377  EVT VT = N->getValueType(0);
1378  OtherOp = DAG.getConstant(1, dl, VT);
1379  Invert = true;
1380  return true;
1381  }
1382  case ISD::SIGN_EXTEND: {
1383  CC = N->getOperand(0);
1384  if (CC.getValueType() != MVT::i1)
1385  return false;
1386  SDLoc dl(N);
1387  EVT VT = N->getValueType(0);
1388  Invert = !AllOnes;
1389  if (AllOnes)
1390  // When looking for an AllOnes constant, N is an sext, and the 'other'
1391  // value is 0.
1392  OtherOp = DAG.getConstant(0, dl, VT);
1393  else
1394  OtherOp =
1396  return true;
1397  }
1398  }
1399 }
1400 
1401 // Combine a constant select operand into its use:
1402 //
1403 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1404 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1405 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1406 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1407 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1408 //
1409 // The transform is rejected if the select doesn't have a constant operand that
1410 // is null, or all ones when AllOnes is set.
1411 //
1412 // Also recognize sext/zext from i1:
1413 //
1414 // (add (zext cc), x) -> (select cc (add x, 1), x)
1415 // (add (sext cc), x) -> (select cc (add x, -1), x)
1416 //
1417 // These transformations eventually create predicated instructions.
1420  bool AllOnes) {
1421  SelectionDAG &DAG = DCI.DAG;
1422  EVT VT = N->getValueType(0);
1423  SDValue NonConstantVal;
1424  SDValue CCOp;
1425  bool SwapSelectOps;
1426  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1427  NonConstantVal, DAG))
1428  return SDValue();
1429 
1430  // Slct is now know to be the desired identity constant when CC is true.
1431  SDValue TrueVal = OtherOp;
1432  SDValue FalseVal =
1433  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1434  // Unless SwapSelectOps says CC should be false.
1435  if (SwapSelectOps)
1436  std::swap(TrueVal, FalseVal);
1437 
1438  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1439 }
1440 
1441 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1442 static SDValue
1444  bool AllOnes) {
1445  SDValue N0 = N->getOperand(0);
1446  SDValue N1 = N->getOperand(1);
1447  if (N0.getNode()->hasOneUse())
1448  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1449  return Result;
1450  if (N1.getNode()->hasOneUse())
1451  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1452  return Result;
1453  return SDValue();
1454 }
1455 
1456 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1459  SDValue N0 = N->getOperand(0);
1460  SDValue N1 = N->getOperand(1);
1461 
1462  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1463  if (N1.getNode()->hasOneUse())
1464  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1465  return Result;
1466 
1467  return SDValue();
1468 }
1469 
1471  DAGCombinerInfo &DCI) const {
1472  switch (N->getOpcode()) {
1473  default:
1474  break;
1475  case ISD::ADD:
1476  case ISD::OR:
1477  case ISD::XOR:
1478  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1479  case ISD::AND:
1480  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1481  case ISD::SUB:
1482  return PerformSUBCombine(N, DCI);
1483  }
1484 
1485  return SDValue();
1486 }
1487 
1489  const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1490  const SelectionDAG &DAG, unsigned Depth) const {
1491  unsigned BitWidth = Known.getBitWidth();
1492  switch (Op.getOpcode()) {
1493  default:
1494  break;
1495  case LanaiISD::SETCC:
1496  Known = KnownBits(BitWidth);
1497  Known.Zero.setBits(1, BitWidth);
1498  break;
1499  case LanaiISD::SELECT_CC:
1500  KnownBits Known2;
1501  DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
1502  DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
1503  Known.Zero &= Known2.Zero;
1504  Known.One &= Known2.One;
1505  break;
1506  }
1507 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:562
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
Definition: APInt.h:1412
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:951
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:610
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:659
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:306
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:964
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:407
bool isMemLoc() const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:579
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:428
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:836
bool hasOneUse() const
Return true if there is exactly one use of this node.
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))
Shift and rotation operations.
Definition: ISDOpcodes.h:382
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void addLoc(const CCValAssign &V)
SimpleValueType SimpleTy
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:398
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(T Value)
Definition: StringSwitch.h:203
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:655
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
int64_t getSExtValue() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:919
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:571
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
amdgpu Simplify well known AMD library false Value * Callee
unsigned getByValSize() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:688
const SDValue & getOperand(unsigned Num) const
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:837
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:679
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
static unsigned NumFixedArgs
Extended Value Type.
Definition: ValueTypes.h:34
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:53
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:634
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:628
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:309
virtual TargetLoweringObjectFile * getObjFileLowering() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:604
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:385
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:674
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:941
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:164
Class for arbitrary precision integers.
Definition: APInt.h:70
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:392
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:440
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:443
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:598
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:684
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:700
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:458
unsigned getRARegister() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1213
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
uint32_t Size
Definition: Profile.cpp:47
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
unsigned getOpcode() const
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:346
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const GlobalObject * getBaseObject() const
Definition: Globals.cpp:261
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
LLVM Value Representation.
Definition: Value.h:73
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue getRegister(unsigned Reg, EVT VT)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:415
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
unsigned getNumOperands() const
Conversion operators.
Definition: ISDOpcodes.h:437
const SDValue & getOperand(unsigned i) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:446
#define LLVM_DEBUG(X)
Definition: Debug.h:123
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const LanaiRegisterInfo * getRegisterInfo() const override
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:583