30 #define GET_REGINFO_TARGET_DESC 31 #include "LanaiGenRegisterInfo.inc" 45 Reserved.
set(Lanai::R0);
46 Reserved.
set(Lanai::R1);
47 Reserved.
set(Lanai::PC);
49 Reserved.
set(Lanai::SP);
52 Reserved.
set(Lanai::R5);
53 Reserved.
set(Lanai::RR1);
54 Reserved.
set(Lanai::R10);
55 Reserved.
set(Lanai::RR2);
56 Reserved.
set(Lanai::R11);
57 Reserved.
set(Lanai::RCA);
58 Reserved.
set(Lanai::R15);
78 case Lanai::ADD_F_I_LO:
79 case Lanai::SUB_F_I_LO:
80 case Lanai::ADDC_I_LO:
81 case Lanai::SUBB_I_LO:
82 case Lanai::ADDC_F_I_LO:
83 case Lanai::SUBB_F_I_LO:
93 return Lanai::SUB_I_LO;
95 return Lanai::ADD_I_LO;
96 case Lanai::ADD_F_I_LO:
97 return Lanai::SUB_F_I_LO;
98 case Lanai::SUB_F_I_LO:
99 return Lanai::ADD_F_I_LO;
100 case Lanai::ADDC_I_LO:
101 return Lanai::SUBB_I_LO;
102 case Lanai::SUBB_I_LO:
103 return Lanai::ADDC_I_LO;
104 case Lanai::ADDC_F_I_LO:
105 return Lanai::SUBB_F_I_LO;
106 case Lanai::SUBB_F_I_LO:
107 return Lanai::ADDC_F_I_LO;
116 return Lanai::LDBs_RR;
118 return Lanai::LDBz_RR;
120 return Lanai::LDHs_RR;
122 return Lanai::LDHz_RR;
124 return Lanai::LDW_RR;
126 return Lanai::STB_RR;
128 return Lanai::STH_RR;
137 int SPAdj,
unsigned FIOperandNum,
139 assert(SPAdj == 0 &&
"Unexpected");
145 bool HasFP = TFI->
hasFP(MF);
155 if (!HasFP || (needsStackRealignment(MF) && FrameIndex >= 0))
159 if (FrameIndex >= 0) {
162 else if (needsStackRealignment(MF))
163 FrameReg = Lanai::SP;
172 assert(RS &&
"Register scavenging must be on");
176 assert(Reg &&
"Register scavenger failed");
178 bool HasNegOffset =
false;
189 .addImm(static_cast<uint32_t>(Offset) >> 16);
192 .
addImm(Offset & 0xffffU);
202 HasNegOffset ? TII->
get(Lanai::SUB_R) : TII->
get(Lanai::ADD_R),
216 "Unexpected ALU op in RRM instruction");
This class represents lattice values for constants.
static unsigned getOppositeALULoOpcode(unsigned Opcode)
static bool isALUArithLoOpcode(unsigned Opcode)
static unsigned getRRMOpcodeVariant(unsigned Opcode)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
constexpr bool isInt< 16 >(int64_t x)
bool hasBasePointer(const MachineFunction &MF) const
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
virtual const TargetInstrInfo * getInstrInfo() const
Register getBaseRegister() const
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
void setImm(int64_t immVal)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
Information about stack frame layout on the target.
BitVector getReservedRegs(const MachineFunction &MF) const override
const MachineBasicBlock * getParent() const
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool isRMOpcode(unsigned Opcode)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
unsigned getRARegister() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
virtual const TargetFrameLowering * getFrameLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSPLSOpcode(unsigned Opcode)
Register getFrameRegister(const MachineFunction &MF) const override
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Wrapper class representing virtual and physical registers.