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LanaiInstrInfo.h
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1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
16 
17 #include "LanaiRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "LanaiGenInstrInfo.inc"
23 
24 namespace llvm {
25 
27  const LanaiRegisterInfo RegisterInfo;
28 
29 public:
31 
32  // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
33  // such, whenever a client has an instance of instruction info, it should
34  // always be able to get register info as well (through this method).
35  virtual const LanaiRegisterInfo &getRegisterInfo() const {
36  return RegisterInfo;
37  }
38 
40  AliasAnalysis *AA) const override;
41 
42  unsigned isLoadFromStackSlot(const MachineInstr &MI,
43  int &FrameIndex) const override;
44 
45  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
46  int &FrameIndex) const override;
47 
48  unsigned isStoreToStackSlot(const MachineInstr &MI,
49  int &FrameIndex) const override;
50 
52  const DebugLoc &DL, unsigned DestinationRegister,
53  unsigned SourceRegister, bool KillSource) const override;
54 
55  void
58  unsigned SourceRegister, bool IsKill, int FrameIndex,
59  const TargetRegisterClass *RegisterClass,
60  const TargetRegisterInfo *RegisterInfo) const override;
61 
62  void
65  unsigned DestinationRegister, int FrameIndex,
66  const TargetRegisterClass *RegisterClass,
67  const TargetRegisterInfo *RegisterInfo) const override;
68 
69  bool expandPostRAPseudo(MachineInstr &MI) const override;
70 
71  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
72  int64_t &Offset,
73  const TargetRegisterInfo *TRI) const override;
74 
75  bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
76  int64_t &Offset, unsigned &Width,
77  const TargetRegisterInfo *TRI) const;
78 
79  std::pair<unsigned, unsigned>
80  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
81 
84 
85  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
86  MachineBasicBlock *&FalseBlock,
88  bool AllowModify) const override;
89 
90  unsigned removeBranch(MachineBasicBlock &MBB,
91  int *BytesRemoved = nullptr) const override;
92 
93  // For a comparison instruction, return the source registers in SrcReg and
94  // SrcReg2 if having two register operands, and the value it compares against
95  // in CmpValue. Return true if the comparison instruction can be analyzed.
96  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
97  unsigned &SrcReg2, int &CmpMask,
98  int &CmpValue) const override;
99 
100  // See if the comparison instruction can be converted into something more
101  // efficient. E.g., on Lanai register-register instructions can set the flag
102  // register, obviating the need for a separate compare.
103  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
104  unsigned SrcReg2, int CmpMask, int CmpValue,
105  const MachineRegisterInfo *MRI) const override;
106 
107  // Analyze the given select instruction, returning true if it cannot be
108  // understood. It is assumed that MI->isSelect() is true.
109  //
110  // When successful, return the controlling condition and the operands that
111  // determine the true and false result values.
112  //
113  // Result = SELECT Cond, TrueOp, FalseOp
114  //
115  // Lanai can optimize certain select instructions, for example by predicating
116  // the instruction defining one of the operands and sets Optimizable to true.
117  bool analyzeSelect(const MachineInstr &MI,
118  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
119  unsigned &FalseOp, bool &Optimizable) const override;
120 
121  // Given a select instruction that was understood by analyzeSelect and
122  // returned Optimizable = true, attempt to optimize MI by merging it with one
123  // of its operands. Returns NULL on failure.
124  //
125  // When successful, returns the new select instruction. The client is
126  // responsible for deleting MI.
127  //
128  // If both sides of the select can be optimized, the TrueOp is modifed.
129  // PreferFalse is not used.
132  bool PreferFalse) const override;
133 
135  SmallVectorImpl<MachineOperand> &Condition) const override;
136 
137  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
138  MachineBasicBlock *FalseBlock,
139  ArrayRef<MachineOperand> Condition,
140  const DebugLoc &DL,
141  int *BytesAdded = nullptr) const override;
142 };
143 
144 static inline bool isSPLSOpcode(unsigned Opcode) {
145  switch (Opcode) {
146  case Lanai::LDBs_RI:
147  case Lanai::LDBz_RI:
148  case Lanai::LDHs_RI:
149  case Lanai::LDHz_RI:
150  case Lanai::STB_RI:
151  case Lanai::STH_RI:
152  return true;
153  default:
154  return false;
155  }
156 }
157 
158 static inline bool isRMOpcode(unsigned Opcode) {
159  switch (Opcode) {
160  case Lanai::LDW_RI:
161  case Lanai::SW_RI:
162  return true;
163  default:
164  return false;
165  }
166 }
167 
168 static inline bool isRRMOpcode(unsigned Opcode) {
169  switch (Opcode) {
170  case Lanai::LDBs_RR:
171  case Lanai::LDBz_RR:
172  case Lanai::LDHs_RR:
173  case Lanai::LDHz_RR:
174  case Lanai::LDWz_RR:
175  case Lanai::LDW_RR:
176  case Lanai::STB_RR:
177  case Lanai::STH_RR:
178  case Lanai::SW_RR:
179  return true;
180  default:
181  return false;
182  }
183 }
184 
185 } // namespace llvm
186 
187 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isRRMOpcode(unsigned Opcode)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool PreferFalse) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned const MachineRegisterInfo * MRI
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:60
static bool isRMOpcode(unsigned Opcode)
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const override
virtual const LanaiRegisterInfo & getRegisterInfo() const
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, unsigned DestinationRegister, unsigned SourceRegister, bool KillSource) const override
static bool isSPLSOpcode(unsigned Opcode)
IRTranslator LLVM IR MI