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LanaiInstrInfo.h
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1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Lanai implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
16 
17 #include "LanaiRegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "LanaiGenInstrInfo.inc"
22 
23 namespace llvm {
24 
26  const LanaiRegisterInfo RegisterInfo;
27 
28 public:
30 
31  // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32  // such, whenever a client has an instance of instruction info, it should
33  // always be able to get register info as well (through this method).
34  virtual const LanaiRegisterInfo &getRegisterInfo() const {
35  return RegisterInfo;
36  }
37 
39  AliasAnalysis *AA) const override;
40 
41  unsigned isLoadFromStackSlot(const MachineInstr &MI,
42  int &FrameIndex) const override;
43 
44  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
45  int &FrameIndex) const override;
46 
47  unsigned isStoreToStackSlot(const MachineInstr &MI,
48  int &FrameIndex) const override;
49 
51  const DebugLoc &DL, unsigned DestinationRegister,
52  unsigned SourceRegister, bool KillSource) const override;
53 
54  void
57  unsigned SourceRegister, bool IsKill, int FrameIndex,
58  const TargetRegisterClass *RegisterClass,
59  const TargetRegisterInfo *RegisterInfo) const override;
60 
61  void
64  unsigned DestinationRegister, int FrameIndex,
65  const TargetRegisterClass *RegisterClass,
66  const TargetRegisterInfo *RegisterInfo) const override;
67 
68  bool expandPostRAPseudo(MachineInstr &MI) const override;
69 
70  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
71  int64_t &Offset,
72  const TargetRegisterInfo *TRI) const override;
73 
74  bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
75  int64_t &Offset, unsigned &Width,
76  const TargetRegisterInfo *TRI) const;
77 
78  std::pair<unsigned, unsigned>
79  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
80 
83 
84  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
85  MachineBasicBlock *&FalseBlock,
87  bool AllowModify) const override;
88 
89  unsigned removeBranch(MachineBasicBlock &MBB,
90  int *BytesRemoved = nullptr) const override;
91 
92  // For a comparison instruction, return the source registers in SrcReg and
93  // SrcReg2 if having two register operands, and the value it compares against
94  // in CmpValue. Return true if the comparison instruction can be analyzed.
95  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
96  unsigned &SrcReg2, int &CmpMask,
97  int &CmpValue) const override;
98 
99  // See if the comparison instruction can be converted into something more
100  // efficient. E.g., on Lanai register-register instructions can set the flag
101  // register, obviating the need for a separate compare.
102  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
103  unsigned SrcReg2, int CmpMask, int CmpValue,
104  const MachineRegisterInfo *MRI) const override;
105 
106  // Analyze the given select instruction, returning true if it cannot be
107  // understood. It is assumed that MI->isSelect() is true.
108  //
109  // When successful, return the controlling condition and the operands that
110  // determine the true and false result values.
111  //
112  // Result = SELECT Cond, TrueOp, FalseOp
113  //
114  // Lanai can optimize certain select instructions, for example by predicating
115  // the instruction defining one of the operands and sets Optimizable to true.
116  bool analyzeSelect(const MachineInstr &MI,
117  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
118  unsigned &FalseOp, bool &Optimizable) const override;
119 
120  // Given a select instruction that was understood by analyzeSelect and
121  // returned Optimizable = true, attempt to optimize MI by merging it with one
122  // of its operands. Returns NULL on failure.
123  //
124  // When successful, returns the new select instruction. The client is
125  // responsible for deleting MI.
126  //
127  // If both sides of the select can be optimized, the TrueOp is modifed.
128  // PreferFalse is not used.
131  bool PreferFalse) const override;
132 
134  SmallVectorImpl<MachineOperand> &Condition) const override;
135 
136  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
137  MachineBasicBlock *FalseBlock,
138  ArrayRef<MachineOperand> Condition,
139  const DebugLoc &DL,
140  int *BytesAdded = nullptr) const override;
141 };
142 
143 static inline bool isSPLSOpcode(unsigned Opcode) {
144  switch (Opcode) {
145  case Lanai::LDBs_RI:
146  case Lanai::LDBz_RI:
147  case Lanai::LDHs_RI:
148  case Lanai::LDHz_RI:
149  case Lanai::STB_RI:
150  case Lanai::STH_RI:
151  return true;
152  default:
153  return false;
154  }
155 }
156 
157 static inline bool isRMOpcode(unsigned Opcode) {
158  switch (Opcode) {
159  case Lanai::LDW_RI:
160  case Lanai::SW_RI:
161  return true;
162  default:
163  return false;
164  }
165 }
166 
167 static inline bool isRRMOpcode(unsigned Opcode) {
168  switch (Opcode) {
169  case Lanai::LDBs_RR:
170  case Lanai::LDBz_RR:
171  case Lanai::LDHs_RR:
172  case Lanai::LDHz_RR:
173  case Lanai::LDWz_RR:
174  case Lanai::LDW_RR:
175  case Lanai::STB_RR:
176  case Lanai::STH_RR:
177  case Lanai::SW_RR:
178  return true;
179  default:
180  return false;
181  }
182 }
183 
184 } // namespace llvm
185 
186 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static bool isRRMOpcode(unsigned Opcode)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool PreferFalse) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned const MachineRegisterInfo * MRI
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
static bool isRMOpcode(unsigned Opcode)
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const override
virtual const LanaiRegisterInfo & getRegisterInfo() const
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, unsigned DestinationRegister, unsigned SourceRegister, bool KillSource) const override
static bool isSPLSOpcode(unsigned Opcode)
IRTranslator LLVM IR MI