LLVM  6.0.0svn
Functions
llvm::BitmaskEnumDetail Namespace Reference

Functions

template<typename E >
std::underlying_type< E >::type Mask ()
 Get a bitmask with 1s in all places up to the high-order bit of E's largest value. More...
 
template<typename E >
std::underlying_type< E >::type Underlying (E Val)
 Check that Val is in range for E, and return Val cast to E's underlying type. More...
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E operator~ (E Val)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E operator| (E LHS, E RHS)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E operator & (E LHS, E RHS)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E operator^ (E LHS, E RHS)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
Eoperator|= (E &LHS, E RHS)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
Eoperator &= (E &LHS, E RHS)
 
template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
Eoperator^= (E &LHS, E RHS)
 

Function Documentation

◆ Mask()

template<typename E >
std::underlying_type<E>::type llvm::BitmaskEnumDetail::Mask ( )

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

Definition at line 81 of file BitmaskEnum.h.

References llvm::NextPowerOf2().

Referenced by llvm::LiveRegUnits::addRegMasked(), AddRuntimeUnrollDisableMetaData(), addSegmentsWithValNo(), AddThumb1SBit(), adjustFixupValue(), adjustForTestUnderMask(), adjustSubwordCmp(), llvm::MachineFunction::allocateRegisterMask(), llvm::analyzeArguments(), llvm::MipsAsmBackend::applyFixup(), ApplyX86MaskOn1BitsVec(), llvm::LivePhysRegs::available(), llvm::lowertypetests::BitSetBuilder::build(), buildFromShuffleMostly(), buildNew(), buildVector(), llvm::HexagonTargetLowering::buildVector64(), llvm::LoopVectorizationPlanner::buildVPlans(), calculateByteProvider(), llvm::canConstantFoldCallTo(), canEvaluateShiftedShift(), CanEvaluateShuffled(), canEvaluateTruncated(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), changeFCMPPredToAArch64CC(), CheckBaseRegAndIndexRegAndScale(), llvm::GlobalObject::classof(), llvm::APInt::clearBit(), llvm::SmallBitVector::clearBitsInMask(), llvm::BitVector::clearBitsInMask(), llvm::SmallBitVector::clearBitsNotInMask(), llvm::BitVector::clearBitsNotInMask(), collectShuffleElements(), combineBasicSADPattern(), combineConcatVectorOfExtracts(), combineExtractWithShuffle(), combineHorizontalMinMaxResult(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineShuffleOfConcatUndef(), combineShuffleOfSplat(), combineShuffleToVectorExtend(), combineTargetShuffle(), combineTruncationShuffle(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::TargetRegisterInfo::composeSubRegIndexLaneMask(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), llvm::slpvectorizer::BoUpSLP::computeMinimumValueSizes(), llvm::SelectionDAG::ComputeNumSignBits(), concatenateTwoVectors(), llvm::ConstantFoldCastOperand(), llvm::MIRPrinter::convert(), llvm::detail::TrailingZerosCounter< T, SizeOfT >::count(), llvm::LiveRangeCalc::createDeadDefs(), llvm::IRBuilder< TargetFolder >::CreateExtractInteger(), llvm::createHexagonHardwareLoops(), llvm::createInterleaveMask(), createMaskedBitTest(), llvm::IRBuilderBase::CreateMaskedGather(), llvm::IRBuilderBase::CreateMaskedLoad(), llvm::IRBuilderBase::CreateMemMove(), llvm::createR600ExpandSpecialInstrsPass(), llvm::MachineOperand::CreateRegLiveOut(), llvm::MachineOperand::CreateRegMask(), llvm::createSequentialMask(), llvm::IRBuilder< TargetFolder >::CreateShuffleVector(), llvm::createStrideMask(), DecodeMSRMask(), decomposeBitTestICmp(), llvm::PPCInstrInfo::decomposeMachineOperandsTargetFlags(), llvm::AArch64InstrInfo::decomposeMachineOperandsTargetFlags(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), doesIgnoreDataTypeSuffix(), llvm::DWARFContext::dump(), eliminateDeadStores(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::X86AsmPrinter::EmitInstruction(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitMaskedTruncSStore(), llvm::UnwindOpcodeAssembler::EmitRegSave(), encodeBitmaskPerm(), llvm::RuntimeDyldCheckerExprEval::evaluate(), expandf64Toi32(), expandV4F32ToV2F64(), extractVector(), llvm::SmallBitVector::find_next_unset(), foldAndOrOfEqualityCmpsWithConstants(), foldConstantInsEltIntoShuffle(), foldICmpShlOne(), foldICmpWithMinMax(), foldLogOpOfMaskedICmps(), foldMaskAndShiftToScale(), foldSelectICmpAndOr(), llvm::InstCombiner::FoldShiftByConstant(), foldShiftedShift(), foreachUnit(), fp16SrcZerosHighBits(), GeneratePerfectShuffle(), getAbsolute(), GetAEABIUnwindPersonalityName(), getARClassRegisterMask(), getAVX2GatherNode(), getBits(), getCompareCC(), GetConstantInt(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::GetDemandedBits(), getDwarfRegNum(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getFauxShuffleMask(), GetFPLibCall(), llvm::DWARFUnitIndex::getFromHash(), llvm::ConstantExpr::getInBoundsGetElementPtr(), llvm::X86TargetLowering::getInlineAsmMemConstraint(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMad64_32(), llvm::SuperRegClassIterator::getMask(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMaskedStore(), getMOVL(), llvm::pdb::PDBFileBuilder::getNamedStreamIndex(), getNextRegister(), llvm::SCEVNAryExpr::getNoWrapFlags(), llvm::MipsTargetLowering::getOpndList(), getParentPad(), getPSHUFShuffleMask(), getRealVLDOpcode(), llvm::TargetLowering::getRecipEstimate(), llvm::RegScavenger::getRegsAvailable(), llvm::ShuffleVectorInst::getShuffleMask(), getStoreTarget(), getTargetConstantBitsFromNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::rdf::PhysicalRegisterInfo::getTRI(), getUniformBase(), getUnpackh(), getUnpackl(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getVCmpInst(), llvm::SimplifyQuery::getWithInstruction(), getX86MaskVec(), group2Shuffle(), llvm::MCCodePadder::handleBasicBlockStart(), llvm::MCCodePadder::handleInstructionBegin(), llvm::LiveIntervals::handleMoveIntoBundle(), hasOnlySelectUsers(), INITIALIZE_PASS(), insert1BitVector(), insertDAGNode(), insertInteger(), insertVector(), isAddSub(), isBoolSGPR(), isBroadcastShuffle(), isBSwapHWordElement(), isCDisp8(), isCopy(), isCrossCopy(), isDefInSubRange(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), isFusableLoadOpStorePattern(), isImplicitOperandIn(), llvm::isKnownNonEqual(), llvm::AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial(), isMemOPCandidate(), isMulPowOf2(), isOpcWithIntImmediate(), llvm::PPCInstrInfo::isProfitableToUnpredicate(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), isStackPtrRelative(), llvm::ShuffleVectorInst::isValidOperands(), LowerAsSplatVectorLoad(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::AArch64TargetLowering::lowerInterleavedStore(), llvm::ARMTargetLowering::lowerInterleavedStore(), llvm::X86TargetLowering::lowerInterleavedStore(), LowerMGATHER(), LowerMLOAD(), lowerMSABitClearImm(), LowerMSCATTER(), LowerMSTORE(), lowerV16I8VectorShuffle(), lowerV8I16GeneralSingleInputVectorShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVectorCTPOPBitmath(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsShift(), lowerVectorShuffleWithPSHUFB(), lowerVSELECTtoVectorShuffle(), llvm::SCEVWrapPredicate::maskFlags(), llvm::ScalarEvolution::maskFlags(), maskIsAllOneOrUndef(), maskIsAllZeroOrUndef(), maskMatters(), llvm::DwarfExpression::maskSubRegister(), matchPair(), matchPairwiseShuffleMask(), matchVectorSplittingReduction(), mayTailCallThisCC(), llvm::MachineInstr::mergeMemRefsWith(), llvm::ShuffleVectorInst::operator new(), llvm::BitVector::operator<<=(), llvm::BitVector::operator>>=(), llvm::BitVector::operator[](), llvm::AArch64InstrInfo::optimizeCondBranch(), optimizeLogicalImm(), parseBitField(), peekThroughBitcast(), performANDCombine(), PerformANDCombine(), performAtomicOp(), PerformBFICombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), performORCombine(), PerformORCombineToBFI(), performSelectCombine(), PerformSHLSimplify(), pickOpcodeForVT(), PrepareCall(), llvm::LiveIntervals::print(), printBitField(), llvm::ARMInstPrinter::printMSRMaskOperand(), printSwizzleBitmask(), llvm::MIPrinter::printTargetFlags(), llvm::ARMInstPrinter::printThumbITMask(), llvm::AArch64_AM::processLogicalImmediate(), profitImm(), llvm::SimpleBitstreamCursor::Read(), readWideAPInt(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo(), llvm::StackMaps::reset(), llvm::SmallBitVector::reset(), llvm::BitVector::reset(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), RunningWindows8OrGreater(), scalarizeMaskedGather(), scalarizeMaskedLoad(), scalarizeMaskedScatter(), scalarizeMaskedStore(), selectI64Imm(), llvm::HexagonDAGToDAGISel::SelectZeroExtend(), llvm::SmallBitVector::set(), llvm::BitVector::set(), llvm::APInt::setBit(), llvm::SmallBitVector::setBitsInMask(), llvm::BitVector::setBitsInMask(), llvm::SmallBitVector::setBitsNotInMask(), llvm::BitVector::setBitsNotInMask(), llvm::MachineInstr::setFlags(), llvm::Function::setIsMaterializable(), setRequiredFeatureString(), llvm::DwarfExpression::setSubRegisterPiece(), setTargetShuffleZeroElements(), shouldReorderOperands(), ShrinkLoadReplaceStoreWithStore(), SimplifyAndInst(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyDivRem(), simplifySelectWithFakeICmpEq(), llvm::TargetLowering::SimplifySetCC(), simplifyX86insertq(), simplifyX86MaskedLoad(), simplifyX86MaskedStore(), stripModuloOnShift(), stripRegisterPrefix(), toString(), tryCombineCRC32(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), tryFormConcatFromShuffle(), trySequenceOfOnes(), TypeSizeToSizeIndex(), llvm::MachineInstr::untieRegOperand(), updateImm(), llvm::UpgradeIntrinsicCall(), upgradeMaskedCompare(), upgradeMaskedMove(), UpgradeMaskToInt(), llvm::InnerLoopVectorizer::vectorizeMemoryInstruction(), llvm::LiveInterval::verify(), llvm::InstCombiner::visitAdd(), llvm::InstCombiner::visitCallInst(), llvm::InstCombiner::visitInsertElementInst(), llvm::InstCombiner::visitInstruction(), llvm::InstCombiner::visitLShr(), llvm::InstCombiner::visitSDiv(), llvm::InstCombiner::visitShl(), llvm::InstCombiner::visitSRem(), and write32AArch64Addr().

◆ operator &()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E llvm::BitmaskEnumDetail::operator& ( E  LHS,
E  RHS 
)

Definition at line 112 of file BitmaskEnum.h.

References E, and Underlying().

◆ operator &=()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E& llvm::BitmaskEnumDetail::operator&= ( E LHS,
E  RHS 
)

Definition at line 134 of file BitmaskEnum.h.

References E.

◆ operator^()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E llvm::BitmaskEnumDetail::operator^ ( E  LHS,
E  RHS 
)

Definition at line 118 of file BitmaskEnum.h.

References E, and Underlying().

◆ operator^=()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E& llvm::BitmaskEnumDetail::operator^= ( E LHS,
E  RHS 
)

Definition at line 141 of file BitmaskEnum.h.

References llvm::LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE().

◆ operator|()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E llvm::BitmaskEnumDetail::operator| ( E  LHS,
E  RHS 
)

Definition at line 106 of file BitmaskEnum.h.

References E, and Underlying().

◆ operator|=()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E& llvm::BitmaskEnumDetail::operator|= ( E LHS,
E  RHS 
)

Definition at line 127 of file BitmaskEnum.h.

References E.

◆ operator~()

template<typename E , typename = typename std::enable_if<is_bitmask_enum<E>::value>::type>
E llvm::BitmaskEnumDetail::operator~ ( E  Val)

Definition at line 100 of file BitmaskEnum.h.

References E, and Underlying().

◆ Underlying()

template<typename E >
std::underlying_type<E>::type llvm::BitmaskEnumDetail::Underlying ( E  Val)

Check that Val is in range for E, and return Val cast to E's underlying type.

Definition at line 91 of file BitmaskEnum.h.

References assert(), and E.

Referenced by eliminateDeadStores(), findInitTrampolineFromAlloca(), operator &(), operator^(), operator|(), and operator~().