LLVM  7.0.0svn
TargetLowering.cpp
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1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCExpr.h"
33 #include "llvm/Support/KnownBits.h"
36 #include <cctype>
37 using namespace llvm;
38 
39 /// NOTE: The TargetMachine owns TLOF.
41  : TargetLoweringBase(tm) {}
42 
43 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
44  return nullptr;
45 }
46 
49 }
50 
51 /// Check whether a given call node is in tail position within its function. If
52 /// so, it sets Chain to the input chain of the tail call.
54  SDValue &Chain) const {
55  const Function &F = DAG.getMachineFunction().getFunction();
56 
57  // Conservatively require the attributes of the call to match those of
58  // the return. Ignore noalias because it doesn't affect the call sequence.
59  AttributeList CallerAttrs = F.getAttributes();
60  if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
61  .removeAttribute(Attribute::NoAlias)
62  .hasAttributes())
63  return false;
64 
65  // It's not safe to eliminate the sign / zero extension of the return value.
66  if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
67  CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
68  return false;
69 
70  // Check if the only use is a function return node.
71  return isUsedByReturnOnly(Node, Chain);
72 }
73 
75  const uint32_t *CallerPreservedMask,
76  const SmallVectorImpl<CCValAssign> &ArgLocs,
77  const SmallVectorImpl<SDValue> &OutVals) const {
78  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
79  const CCValAssign &ArgLoc = ArgLocs[I];
80  if (!ArgLoc.isRegLoc())
81  continue;
82  unsigned Reg = ArgLoc.getLocReg();
83  // Only look at callee saved registers.
84  if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
85  continue;
86  // Check that we pass the value used for the caller.
87  // (We look for a CopyFromReg reading a virtual register that is used
88  // for the function live-in value of register Reg)
89  SDValue Value = OutVals[I];
90  if (Value->getOpcode() != ISD::CopyFromReg)
91  return false;
92  unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
93  if (MRI.getLiveInPhysReg(ArgReg) != Reg)
94  return false;
95  }
96  return true;
97 }
98 
99 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
100 /// and called function attributes.
102  unsigned ArgIdx) {
103  IsSExt = CS->paramHasAttr(ArgIdx, Attribute::SExt);
104  IsZExt = CS->paramHasAttr(ArgIdx, Attribute::ZExt);
105  IsInReg = CS->paramHasAttr(ArgIdx, Attribute::InReg);
106  IsSRet = CS->paramHasAttr(ArgIdx, Attribute::StructRet);
107  IsNest = CS->paramHasAttr(ArgIdx, Attribute::Nest);
108  IsByVal = CS->paramHasAttr(ArgIdx, Attribute::ByVal);
109  IsInAlloca = CS->paramHasAttr(ArgIdx, Attribute::InAlloca);
110  IsReturned = CS->paramHasAttr(ArgIdx, Attribute::Returned);
111  IsSwiftSelf = CS->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
112  IsSwiftError = CS->paramHasAttr(ArgIdx, Attribute::SwiftError);
113  Alignment = CS->getParamAlignment(ArgIdx);
114 }
115 
116 /// Generate a libcall taking the given operands as arguments and returning a
117 /// result of type RetVT.
118 std::pair<SDValue, SDValue>
120  ArrayRef<SDValue> Ops, bool isSigned,
121  const SDLoc &dl, bool doesNotReturn,
122  bool isReturnValueUsed) const {
124  Args.reserve(Ops.size());
125 
127  for (SDValue Op : Ops) {
128  Entry.Node = Op;
129  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
130  Entry.IsSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
131  Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
132  Args.push_back(Entry);
133  }
134 
135  if (LC == RTLIB::UNKNOWN_LIBCALL)
136  report_fatal_error("Unsupported library call operation!");
138  getPointerTy(DAG.getDataLayout()));
139 
140  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
142  bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
143  CLI.setDebugLoc(dl)
144  .setChain(DAG.getEntryNode())
145  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
146  .setNoReturn(doesNotReturn)
147  .setDiscardResult(!isReturnValueUsed)
148  .setSExtResult(signExtend)
149  .setZExtResult(!signExtend);
150  return LowerCallTo(CLI);
151 }
152 
153 /// Soften the operands of a comparison. This code is shared among BR_CC,
154 /// SELECT_CC, and SETCC handlers.
156  SDValue &NewLHS, SDValue &NewRHS,
157  ISD::CondCode &CCCode,
158  const SDLoc &dl) const {
159  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
160  && "Unsupported setcc type!");
161 
162  // Expand into one or more soft-fp libcall(s).
163  RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
164  bool ShouldInvertCC = false;
165  switch (CCCode) {
166  case ISD::SETEQ:
167  case ISD::SETOEQ:
168  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
169  (VT == MVT::f64) ? RTLIB::OEQ_F64 :
170  (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
171  break;
172  case ISD::SETNE:
173  case ISD::SETUNE:
174  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
175  (VT == MVT::f64) ? RTLIB::UNE_F64 :
176  (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
177  break;
178  case ISD::SETGE:
179  case ISD::SETOGE:
180  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181  (VT == MVT::f64) ? RTLIB::OGE_F64 :
182  (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
183  break;
184  case ISD::SETLT:
185  case ISD::SETOLT:
186  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
187  (VT == MVT::f64) ? RTLIB::OLT_F64 :
188  (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
189  break;
190  case ISD::SETLE:
191  case ISD::SETOLE:
192  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
193  (VT == MVT::f64) ? RTLIB::OLE_F64 :
194  (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
195  break;
196  case ISD::SETGT:
197  case ISD::SETOGT:
198  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
199  (VT == MVT::f64) ? RTLIB::OGT_F64 :
200  (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
201  break;
202  case ISD::SETUO:
203  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
204  (VT == MVT::f64) ? RTLIB::UO_F64 :
205  (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
206  break;
207  case ISD::SETO:
208  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
209  (VT == MVT::f64) ? RTLIB::O_F64 :
210  (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
211  break;
212  case ISD::SETONE:
213  // SETONE = SETOLT | SETOGT
214  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
215  (VT == MVT::f64) ? RTLIB::OLT_F64 :
216  (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
217  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
218  (VT == MVT::f64) ? RTLIB::OGT_F64 :
219  (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
220  break;
221  case ISD::SETUEQ:
222  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
223  (VT == MVT::f64) ? RTLIB::UO_F64 :
224  (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
225  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
226  (VT == MVT::f64) ? RTLIB::OEQ_F64 :
227  (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
228  break;
229  default:
230  // Invert CC for unordered comparisons
231  ShouldInvertCC = true;
232  switch (CCCode) {
233  case ISD::SETULT:
234  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
235  (VT == MVT::f64) ? RTLIB::OGE_F64 :
236  (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
237  break;
238  case ISD::SETULE:
239  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
240  (VT == MVT::f64) ? RTLIB::OGT_F64 :
241  (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
242  break;
243  case ISD::SETUGT:
244  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
245  (VT == MVT::f64) ? RTLIB::OLE_F64 :
246  (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
247  break;
248  case ISD::SETUGE:
249  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
250  (VT == MVT::f64) ? RTLIB::OLT_F64 :
251  (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
252  break;
253  default: llvm_unreachable("Do not know how to soften this setcc!");
254  }
255  }
256 
257  // Use the target specific return value for comparions lib calls.
258  EVT RetVT = getCmpLibcallReturnType();
259  SDValue Ops[2] = {NewLHS, NewRHS};
260  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/,
261  dl).first;
262  NewRHS = DAG.getConstant(0, dl, RetVT);
263 
264  CCCode = getCmpLibcallCC(LC1);
265  if (ShouldInvertCC)
266  CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
267 
268  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
269  SDValue Tmp = DAG.getNode(
270  ISD::SETCC, dl,
271  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
272  NewLHS, NewRHS, DAG.getCondCode(CCCode));
273  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/,
274  dl).first;
275  NewLHS = DAG.getNode(
276  ISD::SETCC, dl,
277  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
278  NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
279  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
280  NewRHS = SDValue();
281  }
282 }
283 
284 /// Return the entry encoding for a jump table in the current function. The
285 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
287  // In non-pic modes, just use the address of a block.
288  if (!isPositionIndependent())
290 
291  // In PIC mode, if the target supports a GPRel32 directive, use it.
292  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
294 
295  // Otherwise, use a label difference.
297 }
298 
300  SelectionDAG &DAG) const {
301  // If our PIC model is GP relative, use the global offset table as the base.
302  unsigned JTEncoding = getJumpTableEncoding();
303 
304  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
307 
308  return Table;
309 }
310 
311 /// This returns the relocation base for the given PIC jumptable, the same as
312 /// getPICJumpTableRelocBase, but as an MCExpr.
313 const MCExpr *
315  unsigned JTI,MCContext &Ctx) const{
316  // The normal PIC reloc base is the label at the start of the jump table.
317  return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
318 }
319 
320 bool
322  const TargetMachine &TM = getTargetMachine();
323  const GlobalValue *GV = GA->getGlobal();
324 
325  // If the address is not even local to this DSO we will have to load it from
326  // a got and then add the offset.
327  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
328  return false;
329 
330  // If the code is position independent we will have to add a base register.
331  if (isPositionIndependent())
332  return false;
333 
334  // Otherwise we can do it.
335  return true;
336 }
337 
338 //===----------------------------------------------------------------------===//
339 // Optimization Methods
340 //===----------------------------------------------------------------------===//
341 
342 /// If the specified instruction has a constant integer operand and there are
343 /// bits set in that constant that are not demanded, then clear those bits and
344 /// return true.
346  TargetLoweringOpt &TLO) const {
347  SelectionDAG &DAG = TLO.DAG;
348  SDLoc DL(Op);
349  unsigned Opcode = Op.getOpcode();
350 
351  // Do target-specific constant optimization.
352  if (targetShrinkDemandedConstant(Op, Demanded, TLO))
353  return TLO.New.getNode();
354 
355  // FIXME: ISD::SELECT, ISD::SELECT_CC
356  switch (Opcode) {
357  default:
358  break;
359  case ISD::XOR:
360  case ISD::AND:
361  case ISD::OR: {
362  auto *Op1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
363  if (!Op1C)
364  return false;
365 
366  // If this is a 'not' op, don't touch it because that's a canonical form.
367  const APInt &C = Op1C->getAPIntValue();
368  if (Opcode == ISD::XOR && Demanded.isSubsetOf(C))
369  return false;
370 
371  if (!C.isSubsetOf(Demanded)) {
372  EVT VT = Op.getValueType();
373  SDValue NewC = DAG.getConstant(Demanded & C, DL, VT);
374  SDValue NewOp = DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
375  return TLO.CombineTo(Op, NewOp);
376  }
377 
378  break;
379  }
380  }
381 
382  return false;
383 }
384 
385 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
386 /// This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
387 /// generalized for targets with other types of implicit widening casts.
389  const APInt &Demanded,
390  TargetLoweringOpt &TLO) const {
391  assert(Op.getNumOperands() == 2 &&
392  "ShrinkDemandedOp only supports binary operators!");
393  assert(Op.getNode()->getNumValues() == 1 &&
394  "ShrinkDemandedOp only supports nodes with one result!");
395 
396  SelectionDAG &DAG = TLO.DAG;
397  SDLoc dl(Op);
398 
399  // Early return, as this function cannot handle vector types.
400  if (Op.getValueType().isVector())
401  return false;
402 
403  // Don't do this if the node has another user, which may require the
404  // full value.
405  if (!Op.getNode()->hasOneUse())
406  return false;
407 
408  // Search for the smallest integer type with free casts to and from
409  // Op's type. For expedience, just check power-of-2 integer types.
410  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411  unsigned DemandedSize = Demanded.getActiveBits();
412  unsigned SmallVTBits = DemandedSize;
413  if (!isPowerOf2_32(SmallVTBits))
414  SmallVTBits = NextPowerOf2(SmallVTBits);
415  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
416  EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
417  if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
418  TLI.isZExtFree(SmallVT, Op.getValueType())) {
419  // We found a type with free casts.
420  SDValue X = DAG.getNode(
421  Op.getOpcode(), dl, SmallVT,
422  DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
423  DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
424  assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
425  SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
426  return TLO.CombineTo(Op, Z);
427  }
428  }
429  return false;
430 }
431 
432 bool
434  const APInt &Demanded,
435  DAGCombinerInfo &DCI,
436  TargetLoweringOpt &TLO) const {
437  SDValue Op = User->getOperand(OpIdx);
438  KnownBits Known;
439 
440  if (!SimplifyDemandedBits(Op, Demanded, Known, TLO, 0, true))
441  return false;
442 
443 
444  // Old will not always be the same as Op. For example:
445  //
446  // Demanded = 0xffffff
447  // Op = i64 truncate (i32 and x, 0xffffff)
448  // In this case simplify demand bits will want to replace the 'and' node
449  // with the value 'x', which will give us:
450  // Old = i32 and x, 0xffffff
451  // New = x
452  if (TLO.Old.hasOneUse()) {
453  // For the one use case, we just commit the change.
454  DCI.CommitTargetLoweringOpt(TLO);
455  return true;
456  }
457 
458  // If Old has more than one use then it must be Op, because the
459  // AssumeSingleUse flag is not propogated to recursive calls of
460  // SimplifyDemanded bits, so the only node with multiple use that
461  // it will attempt to combine will be Op.
462  assert(TLO.Old == Op);
463 
465  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
466  if (i == OpIdx) {
467  NewOps.push_back(TLO.New);
468  continue;
469  }
470  NewOps.push_back(User->getOperand(i));
471  }
472  User = TLO.DAG.UpdateNodeOperands(User, NewOps);
473  // Op has less users now, so we may be able to perform additional combines
474  // with it.
475  DCI.AddToWorklist(Op.getNode());
476  // User's operands have been updated, so we may be able to do new combines
477  // with it.
478  DCI.AddToWorklist(User);
479  return true;
480 }
481 
483  DAGCombinerInfo &DCI) const {
484 
485  SelectionDAG &DAG = DCI.DAG;
486  TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
487  !DCI.isBeforeLegalizeOps());
488  KnownBits Known;
489 
490  bool Simplified = SimplifyDemandedBits(Op, DemandedMask, Known, TLO);
491  if (Simplified)
492  DCI.CommitTargetLoweringOpt(TLO);
493  return Simplified;
494 }
495 
496 /// Look at Op. At this point, we know that only the DemandedMask bits of the
497 /// result of Op are ever used downstream. If we can use this information to
498 /// simplify Op, create a new simplified DAG node and return true, returning the
499 /// original and new nodes in Old and New. Otherwise, analyze the expression and
500 /// return a mask of Known bits for the expression (used to simplify the
501 /// caller). The Known bits may only be accurate for those bits in the
502 /// DemandedMask.
504  const APInt &DemandedMask,
505  KnownBits &Known,
506  TargetLoweringOpt &TLO,
507  unsigned Depth,
508  bool AssumeSingleUse) const {
509  unsigned BitWidth = DemandedMask.getBitWidth();
510  assert(Op.getScalarValueSizeInBits() == BitWidth &&
511  "Mask size mismatches value type size!");
512  APInt NewMask = DemandedMask;
513  SDLoc dl(Op);
514  auto &DL = TLO.DAG.getDataLayout();
515 
516  // Don't know anything.
517  Known = KnownBits(BitWidth);
518 
519  if (Op.getOpcode() == ISD::Constant) {
520  // We know all of the bits for a constant!
521  Known.One = cast<ConstantSDNode>(Op)->getAPIntValue();
522  Known.Zero = ~Known.One;
523  return false;
524  }
525 
526  // Other users may use these bits.
527  EVT VT = Op.getValueType();
528  if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
529  if (Depth != 0) {
530  // If not at the root, Just compute the Known bits to
531  // simplify things downstream.
532  TLO.DAG.computeKnownBits(Op, Known, Depth);
533  return false;
534  }
535  // If this is the root being simplified, allow it to have multiple uses,
536  // just set the NewMask to all bits.
537  NewMask = APInt::getAllOnesValue(BitWidth);
538  } else if (DemandedMask == 0) {
539  // Not demanding any bits from Op.
540  if (!Op.isUndef())
541  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
542  return false;
543  } else if (Depth == 6) { // Limit search depth.
544  return false;
545  }
546 
547  KnownBits Known2, KnownOut;
548  switch (Op.getOpcode()) {
549  case ISD::BUILD_VECTOR:
550  // Collect the known bits that are shared by every constant vector element.
551  Known.Zero.setAllBits(); Known.One.setAllBits();
552  for (SDValue SrcOp : Op->ops()) {
553  if (!isa<ConstantSDNode>(SrcOp)) {
554  // We can only handle all constant values - bail out with no known bits.
555  Known = KnownBits(BitWidth);
556  return false;
557  }
558  Known2.One = cast<ConstantSDNode>(SrcOp)->getAPIntValue();
559  Known2.Zero = ~Known2.One;
560 
561  // BUILD_VECTOR can implicitly truncate sources, we must handle this.
562  if (Known2.One.getBitWidth() != BitWidth) {
563  assert(Known2.getBitWidth() > BitWidth &&
564  "Expected BUILD_VECTOR implicit truncation");
565  Known2 = Known2.trunc(BitWidth);
566  }
567 
568  // Known bits are the values that are shared by every element.
569  // TODO: support per-element known bits.
570  Known.One &= Known2.One;
571  Known.Zero &= Known2.Zero;
572  }
573  return false; // Don't fall through, will infinitely loop.
574  case ISD::AND:
575  // If the RHS is a constant, check to see if the LHS would be zero without
576  // using the bits from the RHS. Below, we use knowledge about the RHS to
577  // simplify the LHS, here we're using information from the LHS to simplify
578  // the RHS.
579  if (ConstantSDNode *RHSC = isConstOrConstSplat(Op.getOperand(1))) {
580  SDValue Op0 = Op.getOperand(0);
581  KnownBits LHSKnown;
582  // Do not increment Depth here; that can cause an infinite loop.
583  TLO.DAG.computeKnownBits(Op0, LHSKnown, Depth);
584  // If the LHS already has zeros where RHSC does, this 'and' is dead.
585  if ((LHSKnown.Zero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
586  return TLO.CombineTo(Op, Op0);
587 
588  // If any of the set bits in the RHS are known zero on the LHS, shrink
589  // the constant.
590  if (ShrinkDemandedConstant(Op, ~LHSKnown.Zero & NewMask, TLO))
591  return true;
592 
593  // Bitwise-not (xor X, -1) is a special case: we don't usually shrink its
594  // constant, but if this 'and' is only clearing bits that were just set by
595  // the xor, then this 'and' can be eliminated by shrinking the mask of
596  // the xor. For example, for a 32-bit X:
597  // and (xor (srl X, 31), -1), 1 --> xor (srl X, 31), 1
598  if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
599  LHSKnown.One == ~RHSC->getAPIntValue()) {
600  SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0),
601  Op.getOperand(1));
602  return TLO.CombineTo(Op, Xor);
603  }
604  }
605 
606  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
607  return true;
608  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
609  if (SimplifyDemandedBits(Op.getOperand(0), ~Known.Zero & NewMask,
610  Known2, TLO, Depth+1))
611  return true;
612  assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
613 
614  // If all of the demanded bits are known one on one side, return the other.
615  // These bits cannot contribute to the result of the 'and'.
616  if (NewMask.isSubsetOf(Known2.Zero | Known.One))
617  return TLO.CombineTo(Op, Op.getOperand(0));
618  if (NewMask.isSubsetOf(Known.Zero | Known2.One))
619  return TLO.CombineTo(Op, Op.getOperand(1));
620  // If all of the demanded bits in the inputs are known zeros, return zero.
621  if (NewMask.isSubsetOf(Known.Zero | Known2.Zero))
622  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, VT));
623  // If the RHS is a constant, see if we can simplify it.
624  if (ShrinkDemandedConstant(Op, ~Known2.Zero & NewMask, TLO))
625  return true;
626  // If the operation can be done in a smaller type, do so.
627  if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
628  return true;
629 
630  // Output known-1 bits are only known if set in both the LHS & RHS.
631  Known.One &= Known2.One;
632  // Output known-0 are known to be clear if zero in either the LHS | RHS.
633  Known.Zero |= Known2.Zero;
634  break;
635  case ISD::OR:
636  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
637  return true;
638  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
639  if (SimplifyDemandedBits(Op.getOperand(0), ~Known.One & NewMask,
640  Known2, TLO, Depth+1))
641  return true;
642  assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
643 
644  // If all of the demanded bits are known zero on one side, return the other.
645  // These bits cannot contribute to the result of the 'or'.
646  if (NewMask.isSubsetOf(Known2.One | Known.Zero))
647  return TLO.CombineTo(Op, Op.getOperand(0));
648  if (NewMask.isSubsetOf(Known.One | Known2.Zero))
649  return TLO.CombineTo(Op, Op.getOperand(1));
650  // If the RHS is a constant, see if we can simplify it.
651  if (ShrinkDemandedConstant(Op, NewMask, TLO))
652  return true;
653  // If the operation can be done in a smaller type, do so.
654  if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
655  return true;
656 
657  // Output known-0 bits are only known if clear in both the LHS & RHS.
658  Known.Zero &= Known2.Zero;
659  // Output known-1 are known to be set if set in either the LHS | RHS.
660  Known.One |= Known2.One;
661  break;
662  case ISD::XOR: {
663  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
664  return true;
665  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
666  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, Known2, TLO, Depth+1))
667  return true;
668  assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
669 
670  // If all of the demanded bits are known zero on one side, return the other.
671  // These bits cannot contribute to the result of the 'xor'.
672  if (NewMask.isSubsetOf(Known.Zero))
673  return TLO.CombineTo(Op, Op.getOperand(0));
674  if (NewMask.isSubsetOf(Known2.Zero))
675  return TLO.CombineTo(Op, Op.getOperand(1));
676  // If the operation can be done in a smaller type, do so.
677  if (ShrinkDemandedOp(Op, BitWidth, NewMask, TLO))
678  return true;
679 
680  // If all of the unknown bits are known to be zero on one side or the other
681  // (but not both) turn this into an *inclusive* or.
682  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
683  if ((NewMask & ~Known.Zero & ~Known2.Zero) == 0)
684  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT,
685  Op.getOperand(0),
686  Op.getOperand(1)));
687 
688  // Output known-0 bits are known if clear or set in both the LHS & RHS.
689  KnownOut.Zero = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
690  // Output known-1 are known to be set if set in only one of the LHS, RHS.
691  KnownOut.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
692 
693  // If all of the demanded bits on one side are known, and all of the set
694  // bits on that side are also known to be set on the other side, turn this
695  // into an AND, as we know the bits will be cleared.
696  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
697  // NB: it is okay if more bits are known than are requested
698  if (NewMask.isSubsetOf(Known.Zero|Known.One)) { // all known on one side
699  if (Known.One == Known2.One) { // set bits are the same on both sides
700  SDValue ANDC = TLO.DAG.getConstant(~Known.One & NewMask, dl, VT);
701  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
702  Op.getOperand(0), ANDC));
703  }
704  }
705 
706  // If the RHS is a constant, see if we can change it. Don't alter a -1
707  // constant because that's a 'not' op, and that is better for combining and
708  // codegen.
710  if (C && !C->isAllOnesValue()) {
711  if (NewMask.isSubsetOf(C->getAPIntValue())) {
712  // We're flipping all demanded bits. Flip the undemanded bits too.
713  SDValue New = TLO.DAG.getNOT(dl, Op.getOperand(0), VT);
714  return TLO.CombineTo(Op, New);
715  }
716  // If we can't turn this into a 'not', try to shrink the constant.
717  if (ShrinkDemandedConstant(Op, NewMask, TLO))
718  return true;
719  }
720 
721  Known = std::move(KnownOut);
722  break;
723  }
724  case ISD::SELECT:
725  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known, TLO, Depth+1))
726  return true;
727  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known2, TLO, Depth+1))
728  return true;
729  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
730  assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
731 
732  // If the operands are constants, see if we can simplify them.
733  if (ShrinkDemandedConstant(Op, NewMask, TLO))
734  return true;
735 
736  // Only known if known in both the LHS and RHS.
737  Known.One &= Known2.One;
738  Known.Zero &= Known2.Zero;
739  break;
740  case ISD::SELECT_CC:
741  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, Known, TLO, Depth+1))
742  return true;
743  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known2, TLO, Depth+1))
744  return true;
745  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
746  assert(!Known2.hasConflict() && "Bits known to be one AND zero?");
747 
748  // If the operands are constants, see if we can simplify them.
749  if (ShrinkDemandedConstant(Op, NewMask, TLO))
750  return true;
751 
752  // Only known if known in both the LHS and RHS.
753  Known.One &= Known2.One;
754  Known.Zero &= Known2.Zero;
755  break;
756  case ISD::SETCC: {
757  SDValue Op0 = Op.getOperand(0);
758  SDValue Op1 = Op.getOperand(1);
759  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
760  // If (1) we only need the sign-bit, (2) the setcc operands are the same
761  // width as the setcc result, and (3) the result of a setcc conforms to 0 or
762  // -1, we may be able to bypass the setcc.
763  if (NewMask.isSignMask() && Op0.getScalarValueSizeInBits() == BitWidth &&
764  getBooleanContents(VT) ==
765  BooleanContent::ZeroOrNegativeOneBooleanContent) {
766  // If we're testing X < 0, then this compare isn't needed - just use X!
767  // FIXME: We're limiting to integer types here, but this should also work
768  // if we don't care about FP signed-zero. The use of SETLT with FP means
769  // that we don't care about NaNs.
770  if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
772  return TLO.CombineTo(Op, Op0);
773 
774  // TODO: Should we check for other forms of sign-bit comparisons?
775  // Examples: X <= -1, X >= 0
776  }
777  if (getBooleanContents(Op0.getValueType()) ==
779  BitWidth > 1)
780  Known.Zero.setBitsFrom(1);
781  break;
782  }
783  case ISD::SHL:
784  if (ConstantSDNode *SA = isConstOrConstSplat(Op.getOperand(1))) {
785  SDValue InOp = Op.getOperand(0);
786 
787  // If the shift count is an invalid immediate, don't do anything.
788  if (SA->getAPIntValue().uge(BitWidth))
789  break;
790 
791  unsigned ShAmt = SA->getZExtValue();
792 
793  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
794  // single shift. We can do this if the bottom bits (which are shifted
795  // out) are never demanded.
796  if (InOp.getOpcode() == ISD::SRL) {
797  if (ConstantSDNode *SA2 = isConstOrConstSplat(InOp.getOperand(1))) {
798  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
799  if (SA2->getAPIntValue().ult(BitWidth)) {
800  unsigned C1 = SA2->getZExtValue();
801  unsigned Opc = ISD::SHL;
802  int Diff = ShAmt-C1;
803  if (Diff < 0) {
804  Diff = -Diff;
805  Opc = ISD::SRL;
806  }
807 
808  SDValue NewSA =
809  TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
810  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
811  InOp.getOperand(0),
812  NewSA));
813  }
814  }
815  }
816  }
817 
818  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), Known, TLO, Depth+1))
819  return true;
820 
821  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
822  // are not demanded. This will likely allow the anyext to be folded away.
823  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
824  SDValue InnerOp = InOp.getOperand(0);
825  EVT InnerVT = InnerOp.getValueType();
826  unsigned InnerBits = InnerVT.getScalarSizeInBits();
827  if (ShAmt < InnerBits && NewMask.getActiveBits() <= InnerBits &&
828  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
829  EVT ShTy = getShiftAmountTy(InnerVT, DL);
830  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
831  ShTy = InnerVT;
832  SDValue NarrowShl =
833  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
834  TLO.DAG.getConstant(ShAmt, dl, ShTy));
835  return
836  TLO.CombineTo(Op,
837  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, NarrowShl));
838  }
839  // Repeat the SHL optimization above in cases where an extension
840  // intervenes: (shl (anyext (shr x, c1)), c2) to
841  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
842  // aren't demanded (as above) and that the shifted upper c1 bits of
843  // x aren't demanded.
844  if (InOp.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
845  InnerOp.hasOneUse()) {
846  if (ConstantSDNode *SA2 = isConstOrConstSplat(InnerOp.getOperand(1))) {
847  unsigned InnerShAmt = SA2->getLimitedValue(InnerBits);
848  if (InnerShAmt < ShAmt &&
849  InnerShAmt < InnerBits &&
850  NewMask.getActiveBits() <= (InnerBits - InnerShAmt + ShAmt) &&
851  NewMask.countTrailingZeros() >= ShAmt) {
852  SDValue NewSA =
853  TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
854  Op.getOperand(1).getValueType());
855  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
856  InnerOp.getOperand(0));
857  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
858  NewExt, NewSA));
859  }
860  }
861  }
862  }
863 
864  Known.Zero <<= ShAmt;
865  Known.One <<= ShAmt;
866  // low bits known zero.
867  Known.Zero.setLowBits(ShAmt);
868  }
869  break;
870  case ISD::SRL:
871  if (ConstantSDNode *SA = isConstOrConstSplat(Op.getOperand(1))) {
872  SDValue InOp = Op.getOperand(0);
873 
874  // If the shift count is an invalid immediate, don't do anything.
875  if (SA->getAPIntValue().uge(BitWidth))
876  break;
877 
878  unsigned ShAmt = SA->getZExtValue();
879  APInt InDemandedMask = (NewMask << ShAmt);
880 
881  // If the shift is exact, then it does demand the low bits (and knows that
882  // they are zero).
883  if (Op->getFlags().hasExact())
884  InDemandedMask.setLowBits(ShAmt);
885 
886  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
887  // single shift. We can do this if the top bits (which are shifted out)
888  // are never demanded.
889  if (InOp.getOpcode() == ISD::SHL) {
890  if (ConstantSDNode *SA2 = isConstOrConstSplat(InOp.getOperand(1))) {
891  if (ShAmt &&
892  (NewMask & APInt::getHighBitsSet(BitWidth, ShAmt)) == 0) {
893  if (SA2->getAPIntValue().ult(BitWidth)) {
894  unsigned C1 = SA2->getZExtValue();
895  unsigned Opc = ISD::SRL;
896  int Diff = ShAmt-C1;
897  if (Diff < 0) {
898  Diff = -Diff;
899  Opc = ISD::SHL;
900  }
901 
902  SDValue NewSA =
903  TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
904  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
905  InOp.getOperand(0),
906  NewSA));
907  }
908  }
909  }
910  }
911 
912  // Compute the new bits that are at the top now.
913  if (SimplifyDemandedBits(InOp, InDemandedMask, Known, TLO, Depth+1))
914  return true;
915  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
916  Known.Zero.lshrInPlace(ShAmt);
917  Known.One.lshrInPlace(ShAmt);
918 
919  Known.Zero.setHighBits(ShAmt); // High bits known zero.
920  }
921  break;
922  case ISD::SRA:
923  // If this is an arithmetic shift right and only the low-bit is set, we can
924  // always convert this into a logical shr, even if the shift amount is
925  // variable. The low bit of the shift cannot be an input sign bit unless
926  // the shift amount is >= the size of the datatype, which is undefined.
927  if (NewMask.isOneValue())
928  return TLO.CombineTo(Op,
929  TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
930  Op.getOperand(1)));
931 
932  if (ConstantSDNode *SA = isConstOrConstSplat(Op.getOperand(1))) {
933  // If the shift count is an invalid immediate, don't do anything.
934  if (SA->getAPIntValue().uge(BitWidth))
935  break;
936 
937  unsigned ShAmt = SA->getZExtValue();
938  APInt InDemandedMask = (NewMask << ShAmt);
939 
940  // If the shift is exact, then it does demand the low bits (and knows that
941  // they are zero).
942  if (Op->getFlags().hasExact())
943  InDemandedMask.setLowBits(ShAmt);
944 
945  // If any of the demanded bits are produced by the sign extension, we also
946  // demand the input sign bit.
947  if (NewMask.countLeadingZeros() < ShAmt)
948  InDemandedMask.setSignBit();
949 
950  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, Known, TLO,
951  Depth+1))
952  return true;
953  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
954  Known.Zero.lshrInPlace(ShAmt);
955  Known.One.lshrInPlace(ShAmt);
956 
957  // If the input sign bit is known to be zero, or if none of the top bits
958  // are demanded, turn this into an unsigned shift right.
959  if (Known.Zero[BitWidth - ShAmt - 1] ||
960  NewMask.countLeadingZeros() >= ShAmt) {
961  SDNodeFlags Flags;
962  Flags.setExact(Op->getFlags().hasExact());
963  return TLO.CombineTo(Op,
964  TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
965  Op.getOperand(1), Flags));
966  }
967 
968  int Log2 = NewMask.exactLogBase2();
969  if (Log2 >= 0) {
970  // The bit must come from the sign.
971  SDValue NewSA =
972  TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
973  Op.getOperand(1).getValueType());
974  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
975  Op.getOperand(0), NewSA));
976  }
977 
978  if (Known.One[BitWidth - ShAmt - 1])
979  // New bits are known one.
980  Known.One.setHighBits(ShAmt);
981  }
982  break;
983  case ISD::SIGN_EXTEND_INREG: {
984  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
985  unsigned ExVTBits = ExVT.getScalarSizeInBits();
986 
987  // If we only care about the highest bit, don't bother shifting right.
988  if (NewMask.isSignMask()) {
989  SDValue InOp = Op.getOperand(0);
990  bool AlreadySignExtended =
991  TLO.DAG.ComputeNumSignBits(InOp) >= BitWidth-ExVTBits+1;
992  // However if the input is already sign extended we expect the sign
993  // extension to be dropped altogether later and do not simplify.
994  if (!AlreadySignExtended) {
995  // Compute the correct shift amount type, which must be getShiftAmountTy
996  // for scalar types after legalization.
997  EVT ShiftAmtTy = VT;
998  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
999  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1000 
1001  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ExVTBits, dl,
1002  ShiftAmtTy);
1003  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, InOp,
1004  ShiftAmt));
1005  }
1006  }
1007 
1008  // If none of the extended bits are demanded, eliminate the sextinreg.
1009  if (NewMask.getActiveBits() <= ExVTBits)
1010  return TLO.CombineTo(Op, Op.getOperand(0));
1011 
1012  APInt InputDemandedBits = NewMask.getLoBits(ExVTBits);
1013 
1014  // Since the sign extended bits are demanded, we know that the sign
1015  // bit is demanded.
1016  InputDemandedBits.setBit(ExVTBits - 1);
1017 
1018  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1019  Known, TLO, Depth+1))
1020  return true;
1021  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1022 
1023  // If the sign bit of the input is known set or clear, then we know the
1024  // top bits of the result.
1025 
1026  // If the input sign bit is known zero, convert this into a zero extension.
1027  if (Known.Zero[ExVTBits - 1])
1028  return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(
1029  Op.getOperand(0), dl, ExVT.getScalarType()));
1030 
1031  APInt Mask = APInt::getLowBitsSet(BitWidth, ExVTBits);
1032  if (Known.One[ExVTBits - 1]) { // Input sign bit known set
1033  Known.One.setBitsFrom(ExVTBits);
1034  Known.Zero &= Mask;
1035  } else { // Input sign bit unknown
1036  Known.Zero &= Mask;
1037  Known.One &= Mask;
1038  }
1039  break;
1040  }
1041  case ISD::BUILD_PAIR: {
1042  EVT HalfVT = Op.getOperand(0).getValueType();
1043  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
1044 
1045  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
1046  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
1047 
1048  KnownBits KnownLo, KnownHi;
1049 
1050  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1))
1051  return true;
1052 
1053  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1))
1054  return true;
1055 
1056  Known.Zero = KnownLo.Zero.zext(BitWidth) |
1057  KnownHi.Zero.zext(BitWidth).shl(HalfBitWidth);
1058 
1059  Known.One = KnownLo.One.zext(BitWidth) |
1060  KnownHi.One.zext(BitWidth).shl(HalfBitWidth);
1061  break;
1062  }
1063  case ISD::ZERO_EXTEND: {
1064  unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
1065 
1066  // If none of the top bits are demanded, convert this into an any_extend.
1067  if (NewMask.getActiveBits() <= OperandBitWidth)
1068  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1069  Op.getOperand(0)));
1070 
1071  APInt InMask = NewMask.trunc(OperandBitWidth);
1072  if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
1073  return true;
1074  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1075  Known = Known.zext(BitWidth);
1076  Known.Zero.setBitsFrom(OperandBitWidth);
1077  break;
1078  }
1079  case ISD::SIGN_EXTEND: {
1080  unsigned InBits = Op.getOperand(0).getValueType().getScalarSizeInBits();
1081 
1082  // If none of the top bits are demanded, convert this into an any_extend.
1083  if (NewMask.getActiveBits() <= InBits)
1084  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
1085  Op.getOperand(0)));
1086 
1087  // Since some of the sign extended bits are demanded, we know that the sign
1088  // bit is demanded.
1089  APInt InDemandedBits = NewMask.trunc(InBits);
1090  InDemandedBits.setBit(InBits - 1);
1091 
1092  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, Known, TLO,
1093  Depth+1))
1094  return true;
1095  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1096  // If the sign bit is known one, the top bits match.
1097  Known = Known.sext(BitWidth);
1098 
1099  // If the sign bit is known zero, convert this to a zero extend.
1100  if (Known.isNonNegative())
1101  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT,
1102  Op.getOperand(0)));
1103  break;
1104  }
1105  case ISD::ANY_EXTEND: {
1106  unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
1107  APInt InMask = NewMask.trunc(OperandBitWidth);
1108  if (SimplifyDemandedBits(Op.getOperand(0), InMask, Known, TLO, Depth+1))
1109  return true;
1110  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1111  Known = Known.zext(BitWidth);
1112  break;
1113  }
1114  case ISD::TRUNCATE: {
1115  // Simplify the input, using demanded bit information, and compute the known
1116  // zero/one bits live out.
1117  unsigned OperandBitWidth = Op.getOperand(0).getScalarValueSizeInBits();
1118  APInt TruncMask = NewMask.zext(OperandBitWidth);
1119  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, Known, TLO, Depth+1))
1120  return true;
1121  Known = Known.trunc(BitWidth);
1122 
1123  // If the input is only used by this truncate, see if we can shrink it based
1124  // on the known demanded bits.
1125  if (Op.getOperand(0).getNode()->hasOneUse()) {
1126  SDValue In = Op.getOperand(0);
1127  switch (In.getOpcode()) {
1128  default: break;
1129  case ISD::SRL:
1130  // Shrink SRL by a constant if none of the high bits shifted in are
1131  // demanded.
1132  if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
1133  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1134  // undesirable.
1135  break;
1137  if (!ShAmt)
1138  break;
1139  SDValue Shift = In.getOperand(1);
1140  if (TLO.LegalTypes()) {
1141  uint64_t ShVal = ShAmt->getZExtValue();
1142  Shift = TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(VT, DL));
1143  }
1144 
1145  if (ShAmt->getZExtValue() < BitWidth) {
1146  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1147  OperandBitWidth - BitWidth);
1148  HighBits.lshrInPlace(ShAmt->getZExtValue());
1149  HighBits = HighBits.trunc(BitWidth);
1150 
1151  if (!(HighBits & NewMask)) {
1152  // None of the shifted in bits are needed. Add a truncate of the
1153  // shift input, then shift it.
1154  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, VT,
1155  In.getOperand(0));
1156  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, NewTrunc,
1157  Shift));
1158  }
1159  }
1160  break;
1161  }
1162  }
1163 
1164  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1165  break;
1166  }
1167  case ISD::AssertZext: {
1168  // AssertZext demands all of the high bits, plus any of the low bits
1169  // demanded by its users.
1170  EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1171  APInt InMask = APInt::getLowBitsSet(BitWidth, ZVT.getSizeInBits());
1172  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1173  Known, TLO, Depth+1))
1174  return true;
1175  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
1176 
1177  Known.Zero |= ~InMask;
1178  break;
1179  }
1180  case ISD::BITCAST:
1181  // If this is an FP->Int bitcast and if the sign bit is the only
1182  // thing demanded, turn this into a FGETSIGN.
1183  if (!TLO.LegalOperations() && !VT.isVector() &&
1184  !Op.getOperand(0).getValueType().isVector() &&
1185  NewMask == APInt::getSignMask(Op.getValueSizeInBits()) &&
1187  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
1189  if ((OpVTLegal || i32Legal) && VT.isSimple() &&
1190  Op.getOperand(0).getValueType() != MVT::f128) {
1191  // Cannot eliminate/lower SHL for f128 yet.
1192  EVT Ty = OpVTLegal ? VT : MVT::i32;
1193  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1194  // place. We expect the SHL to be eliminated by other optimizations.
1195  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1196  unsigned OpVTSizeInBits = Op.getValueSizeInBits();
1197  if (!OpVTLegal && OpVTSizeInBits > 32)
1198  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
1199  unsigned ShVal = Op.getValueSizeInBits() - 1;
1200  SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT);
1201  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, Sign, ShAmt));
1202  }
1203  }
1204  // If this is a bitcast, let computeKnownBits handle it. Only do this on a
1205  // recursive call where Known may be useful to the caller.
1206  if (Depth > 0) {
1207  TLO.DAG.computeKnownBits(Op, Known, Depth);
1208  return false;
1209  }
1210  break;
1211  case ISD::ADD:
1212  case ISD::MUL:
1213  case ISD::SUB: {
1214  // Add, Sub, and Mul don't demand any bits in positions beyond that
1215  // of the highest bit demanded of them.
1216  SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
1217  unsigned NewMaskLZ = NewMask.countLeadingZeros();
1218  APInt LoMask = APInt::getLowBitsSet(BitWidth, BitWidth - NewMaskLZ);
1219  if (SimplifyDemandedBits(Op0, LoMask, Known2, TLO, Depth + 1) ||
1220  SimplifyDemandedBits(Op1, LoMask, Known2, TLO, Depth + 1) ||
1221  // See if the operation should be performed at a smaller bit width.
1222  ShrinkDemandedOp(Op, BitWidth, NewMask, TLO)) {
1223  SDNodeFlags Flags = Op.getNode()->getFlags();
1224  if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
1225  // Disable the nsw and nuw flags. We can no longer guarantee that we
1226  // won't wrap after simplification.
1227  Flags.setNoSignedWrap(false);
1228  Flags.setNoUnsignedWrap(false);
1229  SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1,
1230  Flags);
1231  return TLO.CombineTo(Op, NewOp);
1232  }
1233  return true;
1234  }
1235 
1236  // If we have a constant operand, we may be able to turn it into -1 if we
1237  // do not demand the high bits. This can make the constant smaller to
1238  // encode, allow more general folding, or match specialized instruction
1239  // patterns (eg, 'blsr' on x86). Don't bother changing 1 to -1 because that
1240  // is probably not useful (and could be detrimental).
1242  APInt HighMask = APInt::getHighBitsSet(NewMask.getBitWidth(), NewMaskLZ);
1243  if (C && !C->isAllOnesValue() && !C->isOne() &&
1244  (C->getAPIntValue() | HighMask).isAllOnesValue()) {
1245  SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT);
1246  // We can't guarantee that the new math op doesn't wrap, so explicitly
1247  // clear those flags to prevent folding with a potential existing node
1248  // that has those flags set.
1249  SDNodeFlags Flags;
1250  Flags.setNoSignedWrap(false);
1251  Flags.setNoUnsignedWrap(false);
1252  SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
1253  return TLO.CombineTo(Op, NewOp);
1254  }
1255 
1257  }
1258  default:
1259  // Just use computeKnownBits to compute output bits.
1260  TLO.DAG.computeKnownBits(Op, Known, Depth);
1261  break;
1262  }
1263 
1264  // If we know the value of all of the demanded bits, return this as a
1265  // constant.
1266  if (NewMask.isSubsetOf(Known.Zero|Known.One)) {
1267  // Avoid folding to a constant if any OpaqueConstant is involved.
1268  const SDNode *N = Op.getNode();
1270  E = SDNodeIterator::end(N); I != E; ++I) {
1271  SDNode *Op = *I;
1272  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1273  if (C->isOpaque())
1274  return false;
1275  }
1276  return TLO.CombineTo(Op, TLO.DAG.getConstant(Known.One, dl, VT));
1277  }
1278 
1279  return false;
1280 }
1281 
1283  const APInt &DemandedElts,
1284  APInt &KnownUndef,
1285  APInt &KnownZero,
1286  DAGCombinerInfo &DCI) const {
1287  SelectionDAG &DAG = DCI.DAG;
1288  TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1289  !DCI.isBeforeLegalizeOps());
1290 
1291  bool Simplified =
1292  SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
1293  if (Simplified)
1294  DCI.CommitTargetLoweringOpt(TLO);
1295  return Simplified;
1296 }
1297 
1299  SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef,
1300  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth,
1301  bool AssumeSingleUse) const {
1302  EVT VT = Op.getValueType();
1303  APInt DemandedElts = DemandedEltMask;
1304  unsigned NumElts = DemandedElts.getBitWidth();
1305  assert(VT.isVector() && "Expected vector op");
1306  assert(VT.getVectorNumElements() == NumElts &&
1307  "Mask size mismatches value type element count!");
1308 
1309  KnownUndef = KnownZero = APInt::getNullValue(NumElts);
1310 
1311  // Undef operand.
1312  if (Op.isUndef()) {
1313  KnownUndef.setAllBits();
1314  return false;
1315  }
1316 
1317  // If Op has other users, assume that all elements are needed.
1318  if (!Op.getNode()->hasOneUse() && !AssumeSingleUse)
1319  DemandedElts.setAllBits();
1320 
1321  // Not demanding any elements from Op.
1322  if (DemandedElts == 0) {
1323  KnownUndef.setAllBits();
1324  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1325  }
1326 
1327  // Limit search depth.
1328  if (Depth >= 6)
1329  return false;
1330 
1331  SDLoc DL(Op);
1332  unsigned EltSizeInBits = VT.getScalarSizeInBits();
1333 
1334  switch (Op.getOpcode()) {
1335  case ISD::SCALAR_TO_VECTOR: {
1336  if (!DemandedElts[0]) {
1337  KnownUndef.setAllBits();
1338  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT));
1339  }
1340  KnownUndef.setHighBits(NumElts - 1);
1341  break;
1342  }
1343  case ISD::BUILD_VECTOR: {
1344  // Check all elements and simplify any unused elements with UNDEF.
1345  if (!DemandedElts.isAllOnesValue()) {
1346  // Don't simplify BROADCASTS.
1347  if (llvm::any_of(Op->op_values(),
1348  [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
1349  SmallVector<SDValue, 32> Ops(Op->op_begin(), Op->op_end());
1350  bool Updated = false;
1351  for (unsigned i = 0; i != NumElts; ++i) {
1352  if (!DemandedElts[i] && !Ops[i].isUndef()) {
1353  Ops[i] = TLO.DAG.getUNDEF(Ops[0].getValueType());
1354  KnownUndef.setBit(i);
1355  Updated = true;
1356  }
1357  }
1358  if (Updated)
1359  return TLO.CombineTo(Op, TLO.DAG.getBuildVector(VT, DL, Ops));
1360  }
1361  }
1362  for (unsigned i = 0; i != NumElts; ++i) {
1363  SDValue SrcOp = Op.getOperand(i);
1364  if (SrcOp.isUndef()) {
1365  KnownUndef.setBit(i);
1366  } else if (EltSizeInBits == SrcOp.getScalarValueSizeInBits() &&
1367  (isNullConstant(SrcOp) || isNullFPConstant(SrcOp))) {
1368  KnownZero.setBit(i);
1369  }
1370  }
1371  break;
1372  }
1373  case ISD::CONCAT_VECTORS: {
1374  EVT SubVT = Op.getOperand(0).getValueType();
1375  unsigned NumSubVecs = Op.getNumOperands();
1376  unsigned NumSubElts = SubVT.getVectorNumElements();
1377  for (unsigned i = 0; i != NumSubVecs; ++i) {
1378  SDValue SubOp = Op.getOperand(i);
1379  APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1380  APInt SubUndef, SubZero;
1381  if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
1382  Depth + 1))
1383  return true;
1384  KnownUndef.insertBits(SubUndef, i * NumSubElts);
1385  KnownZero.insertBits(SubZero, i * NumSubElts);
1386  }
1387  break;
1388  }
1389  case ISD::INSERT_SUBVECTOR: {
1390  if (!isa<ConstantSDNode>(Op.getOperand(2)))
1391  break;
1392  SDValue Base = Op.getOperand(0);
1393  SDValue Sub = Op.getOperand(1);
1394  EVT SubVT = Sub.getValueType();
1395  unsigned NumSubElts = SubVT.getVectorNumElements();
1396  APInt Idx = cast<ConstantSDNode>(Op.getOperand(2))->getAPIntValue();
1397  if (Idx.uge(NumElts - NumSubElts))
1398  break;
1399  unsigned SubIdx = Idx.getZExtValue();
1400  APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
1401  APInt SubUndef, SubZero;
1402  if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
1403  Depth + 1))
1404  return true;
1405  APInt BaseElts = DemandedElts;
1406  BaseElts.insertBits(APInt::getNullValue(NumSubElts), SubIdx);
1407  if (SimplifyDemandedVectorElts(Base, BaseElts, KnownUndef, KnownZero, TLO,
1408  Depth + 1))
1409  return true;
1410  KnownUndef.insertBits(SubUndef, SubIdx);
1411  KnownZero.insertBits(SubZero, SubIdx);
1412  break;
1413  }
1414  case ISD::VSELECT: {
1415  APInt DemandedLHS(DemandedElts);
1416  APInt DemandedRHS(DemandedElts);
1417 
1418  // TODO - add support for constant vselect masks.
1419 
1420  // See if we can simplify either vselect operand.
1421  APInt UndefLHS, ZeroLHS;
1422  APInt UndefRHS, ZeroRHS;
1423  if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedLHS, UndefLHS,
1424  ZeroLHS, TLO, Depth + 1))
1425  return true;
1426  if (SimplifyDemandedVectorElts(Op.getOperand(2), DemandedRHS, UndefRHS,
1427  ZeroRHS, TLO, Depth + 1))
1428  return true;
1429 
1430  KnownUndef = UndefLHS & UndefRHS;
1431  KnownZero = ZeroLHS & ZeroRHS;
1432  break;
1433  }
1434  case ISD::VECTOR_SHUFFLE: {
1435  ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
1436 
1437  // Collect demanded elements from shuffle operands..
1438  APInt DemandedLHS(NumElts, 0);
1439  APInt DemandedRHS(NumElts, 0);
1440  for (unsigned i = 0; i != NumElts; ++i) {
1441  int M = ShuffleMask[i];
1442  if (M < 0 || !DemandedElts[i])
1443  continue;
1444  assert(0 <= M && M < (int)(2 * NumElts) && "Shuffle index out of range");
1445  if (M < (int)NumElts)
1446  DemandedLHS.setBit(M);
1447  else
1448  DemandedRHS.setBit(M - NumElts);
1449  }
1450 
1451  // See if we can simplify either shuffle operand.
1452  APInt UndefLHS, ZeroLHS;
1453  APInt UndefRHS, ZeroRHS;
1454  if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedLHS, UndefLHS,
1455  ZeroLHS, TLO, Depth + 1))
1456  return true;
1457  if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedRHS, UndefRHS,
1458  ZeroRHS, TLO, Depth + 1))
1459  return true;
1460 
1461  // Simplify mask using undef elements from LHS/RHS.
1462  bool Updated = false;
1463  bool IdentityLHS = true, IdentityRHS = true;
1464  SmallVector<int, 32> NewMask(ShuffleMask.begin(), ShuffleMask.end());
1465  for (unsigned i = 0; i != NumElts; ++i) {
1466  int &M = NewMask[i];
1467  if (M < 0)
1468  continue;
1469  if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
1470  (M >= (int)NumElts && UndefRHS[M - NumElts])) {
1471  Updated = true;
1472  M = -1;
1473  }
1474  IdentityLHS &= (M < 0) || (M == (int)i);
1475  IdentityRHS &= (M < 0) || ((M - NumElts) == i);
1476  }
1477 
1478  // Update legal shuffle masks based on demanded elements if it won't reduce
1479  // to Identity which can cause premature removal of the shuffle mask.
1480  if (Updated && !IdentityLHS && !IdentityRHS && !TLO.LegalOps &&
1481  isShuffleMaskLegal(NewMask, VT))
1482  return TLO.CombineTo(Op,
1483  TLO.DAG.getVectorShuffle(VT, DL, Op.getOperand(0),
1484  Op.getOperand(1), NewMask));
1485 
1486  // Propagate undef/zero elements from LHS/RHS.
1487  for (unsigned i = 0; i != NumElts; ++i) {
1488  int M = ShuffleMask[i];
1489  if (M < 0) {
1490  KnownUndef.setBit(i);
1491  } else if (M < (int)NumElts) {
1492  if (UndefLHS[M])
1493  KnownUndef.setBit(i);
1494  if (ZeroLHS[M])
1495  KnownZero.setBit(i);
1496  } else {
1497  if (UndefRHS[M - NumElts])
1498  KnownUndef.setBit(i);
1499  if (ZeroRHS[M - NumElts])
1500  KnownZero.setBit(i);
1501  }
1502  }
1503  break;
1504  }
1505  default: {
1506  if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
1507  if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
1508  KnownZero, TLO, Depth))
1509  return true;
1510  break;
1511  }
1512  }
1513 
1514  assert((KnownUndef & KnownZero) == 0 && "Elements flagged as undef AND zero");
1515  return false;
1516 }
1517 
1518 /// Determine which of the bits specified in Mask are known to be either zero or
1519 /// one and return them in the Known.
1521  KnownBits &Known,
1522  const APInt &DemandedElts,
1523  const SelectionDAG &DAG,
1524  unsigned Depth) const {
1528  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1529  "Should use MaskedValueIsZero if you don't know whether Op"
1530  " is a target node!");
1531  Known.resetAll();
1532 }
1533 
1535  KnownBits &Known,
1536  const APInt &DemandedElts,
1537  const SelectionDAG &DAG,
1538  unsigned Depth) const {
1539  assert(isa<FrameIndexSDNode>(Op) && "expected FrameIndex");
1540 
1541  if (unsigned Align = DAG.InferPtrAlignment(Op)) {
1542  // The low bits are known zero if the pointer is aligned.
1543  Known.Zero.setLowBits(Log2_32(Align));
1544  }
1545 }
1546 
1547 /// This method can be implemented by targets that want to expose additional
1548 /// information about sign bits to the DAG Combiner.
1550  const APInt &,
1551  const SelectionDAG &,
1552  unsigned Depth) const {
1556  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1557  "Should use ComputeNumSignBits if you don't know whether Op"
1558  " is a target node!");
1559  return 1;
1560 }
1561 
1563  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
1564  TargetLoweringOpt &TLO, unsigned Depth) const {
1568  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1569  "Should use SimplifyDemandedVectorElts if you don't know whether Op"
1570  " is a target node!");
1571  return false;
1572 }
1573 
1574 // FIXME: Ideally, this would use ISD::isConstantSplatVector(), but that must
1575 // work with truncating build vectors and vectors with elements of less than
1576 // 8 bits.
1578  if (!N)
1579  return false;
1580 
1581  APInt CVal;
1582  if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
1583  CVal = CN->getAPIntValue();
1584  } else if (auto *BV = dyn_cast<BuildVectorSDNode>(N)) {
1585  auto *CN = BV->getConstantSplatNode();
1586  if (!CN)
1587  return false;
1588 
1589  // If this is a truncating build vector, truncate the splat value.
1590  // Otherwise, we may fail to match the expected values below.
1591  unsigned BVEltWidth = BV->getValueType(0).getScalarSizeInBits();
1592  CVal = CN->getAPIntValue();
1593  if (BVEltWidth < CVal.getBitWidth())
1594  CVal = CVal.trunc(BVEltWidth);
1595  } else {
1596  return false;
1597  }
1598 
1599  switch (getBooleanContents(N->getValueType(0))) {
1601  return CVal[0];
1603  return CVal.isOneValue();
1605  return CVal.isAllOnesValue();
1606  }
1607 
1608  llvm_unreachable("Invalid boolean contents");
1609 }
1610 
1612  if (!N)
1613  return false;
1614 
1615  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1616  if (!CN) {
1618  if (!BV)
1619  return false;
1620 
1621  // Only interested in constant splats, we don't care about undef
1622  // elements in identifying boolean constants and getConstantSplatNode
1623  // returns NULL if all ops are undef;
1624  CN = BV->getConstantSplatNode();
1625  if (!CN)
1626  return false;
1627  }
1628 
1630  return !CN->getAPIntValue()[0];
1631 
1632  return CN->isNullValue();
1633 }
1634 
1636  bool SExt) const {
1637  if (VT == MVT::i1)
1638  return N->isOne();
1639 
1641  switch (Cnt) {
1643  // An extended value of 1 is always true, unless its original type is i1,
1644  // in which case it will be sign extended to -1.
1645  return (N->isOne() && !SExt) || (SExt && (N->getValueType(0) != MVT::i1));
1648  return N->isAllOnesValue() && SExt;
1649  }
1650  llvm_unreachable("Unexpected enumeration.");
1651 }
1652 
1653 /// This helper function of SimplifySetCC tries to optimize the comparison when
1654 /// either operand of the SetCC node is a bitwise-and instruction.
1655 SDValue TargetLowering::simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
1656  ISD::CondCode Cond,
1657  DAGCombinerInfo &DCI,
1658  const SDLoc &DL) const {
1659  // Match these patterns in any of their permutations:
1660  // (X & Y) == Y
1661  // (X & Y) != Y
1662  if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
1663  std::swap(N0, N1);
1664 
1665  EVT OpVT = N0.getValueType();
1666  if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
1667  (Cond != ISD::SETEQ && Cond != ISD::SETNE))
1668  return SDValue();
1669 
1670  SDValue X, Y;
1671  if (N0.getOperand(0) == N1) {
1672  X = N0.getOperand(1);
1673  Y = N0.getOperand(0);
1674  } else if (N0.getOperand(1) == N1) {
1675  X = N0.getOperand(0);
1676  Y = N0.getOperand(1);
1677  } else {
1678  return SDValue();
1679  }
1680 
1681  SelectionDAG &DAG = DCI.DAG;
1682  SDValue Zero = DAG.getConstant(0, DL, OpVT);
1683  if (DAG.isKnownToBeAPowerOfTwo(Y)) {
1684  // Simplify X & Y == Y to X & Y != 0 if Y has exactly one bit set.
1685  // Note that where Y is variable and is known to have at most one bit set
1686  // (for example, if it is Z & 1) we cannot do this; the expressions are not
1687  // equivalent when Y == 0.
1688  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1689  if (DCI.isBeforeLegalizeOps() ||
1690  isCondCodeLegal(Cond, N0.getSimpleValueType()))
1691  return DAG.getSetCC(DL, VT, N0, Zero, Cond);
1692  } else if (N0.hasOneUse() && hasAndNotCompare(Y)) {
1693  // If the target supports an 'and-not' or 'and-complement' logic operation,
1694  // try to use that to make a comparison operation more efficient.
1695  // But don't do this transform if the mask is a single bit because there are
1696  // more efficient ways to deal with that case (for example, 'bt' on x86 or
1697  // 'rlwinm' on PPC).
1698 
1699  // Bail out if the compare operand that we want to turn into a zero is
1700  // already a zero (otherwise, infinite loop).
1701  auto *YConst = dyn_cast<ConstantSDNode>(Y);
1702  if (YConst && YConst->isNullValue())
1703  return SDValue();
1704 
1705  // Transform this into: ~X & Y == 0.
1706  SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT);
1707  SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, NotX, Y);
1708  return DAG.getSetCC(DL, VT, NewAnd, Zero, Cond);
1709  }
1710 
1711  return SDValue();
1712 }
1713 
1714 /// Try to simplify a setcc built with the specified operands and cc. If it is
1715 /// unable to simplify it, return a null SDValue.
1717  ISD::CondCode Cond, bool foldBooleans,
1718  DAGCombinerInfo &DCI,
1719  const SDLoc &dl) const {
1720  SelectionDAG &DAG = DCI.DAG;
1721  EVT OpVT = N0.getValueType();
1722 
1723  // These setcc operations always fold.
1724  switch (Cond) {
1725  default: break;
1726  case ISD::SETFALSE:
1727  case ISD::SETFALSE2: return DAG.getBoolConstant(false, dl, VT, OpVT);
1728  case ISD::SETTRUE:
1729  case ISD::SETTRUE2: return DAG.getBoolConstant(true, dl, VT, OpVT);
1730  }
1731 
1732  // Ensure that the constant occurs on the RHS and fold constant comparisons.
1733  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1734  if (isa<ConstantSDNode>(N0.getNode()) &&
1735  (DCI.isBeforeLegalizeOps() ||
1736  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1737  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1738 
1739  if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1740  const APInt &C1 = N1C->getAPIntValue();
1741 
1742  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1743  // equality comparison, then we're just comparing whether X itself is
1744  // zero.
1745  if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
1746  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1747  N0.getOperand(1).getOpcode() == ISD::Constant) {
1748  const APInt &ShAmt
1749  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1750  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1751  ShAmt == Log2_32(N0.getValueSizeInBits())) {
1752  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1753  // (srl (ctlz x), 5) == 0 -> X != 0
1754  // (srl (ctlz x), 5) != 1 -> X != 0
1755  Cond = ISD::SETNE;
1756  } else {
1757  // (srl (ctlz x), 5) != 0 -> X == 0
1758  // (srl (ctlz x), 5) == 1 -> X == 0
1759  Cond = ISD::SETEQ;
1760  }
1761  SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1762  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1763  Zero, Cond);
1764  }
1765  }
1766 
1767  SDValue CTPOP = N0;
1768  // Look through truncs that don't change the value of a ctpop.
1769  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1770  CTPOP = N0.getOperand(0);
1771 
1772  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1773  (N0 == CTPOP ||
1775  EVT CTVT = CTPOP.getValueType();
1776  SDValue CTOp = CTPOP.getOperand(0);
1777 
1778  // (ctpop x) u< 2 -> (x & x-1) == 0
1779  // (ctpop x) u> 1 -> (x & x-1) != 0
1780  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1781  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1782  DAG.getConstant(1, dl, CTVT));
1783  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1785  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1786  }
1787 
1788  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1789  }
1790 
1791  // (zext x) == C --> x == (trunc C)
1792  // (sext x) == C --> x == (trunc C)
1793  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1794  DCI.isBeforeLegalize() && N0->hasOneUse()) {
1795  unsigned MinBits = N0.getValueSizeInBits();
1796  SDValue PreExt;
1797  bool Signed = false;
1798  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1799  // ZExt
1800  MinBits = N0->getOperand(0).getValueSizeInBits();
1801  PreExt = N0->getOperand(0);
1802  } else if (N0->getOpcode() == ISD::AND) {
1803  // DAGCombine turns costly ZExts into ANDs
1804  if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1805  if ((C->getAPIntValue()+1).isPowerOf2()) {
1806  MinBits = C->getAPIntValue().countTrailingOnes();
1807  PreExt = N0->getOperand(0);
1808  }
1809  } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1810  // SExt
1811  MinBits = N0->getOperand(0).getValueSizeInBits();
1812  PreExt = N0->getOperand(0);
1813  Signed = true;
1814  } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
1815  // ZEXTLOAD / SEXTLOAD
1816  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1817  MinBits = LN0->getMemoryVT().getSizeInBits();
1818  PreExt = N0;
1819  } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1820  Signed = true;
1821  MinBits = LN0->getMemoryVT().getSizeInBits();
1822  PreExt = N0;
1823  }
1824  }
1825 
1826  // Figure out how many bits we need to preserve this constant.
1827  unsigned ReqdBits = Signed ?
1828  C1.getBitWidth() - C1.getNumSignBits() + 1 :
1829  C1.getActiveBits();
1830 
1831  // Make sure we're not losing bits from the constant.
1832  if (MinBits > 0 &&
1833  MinBits < C1.getBitWidth() &&
1834  MinBits >= ReqdBits) {
1835  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1836  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1837  // Will get folded away.
1838  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1839  if (MinBits == 1 && C1 == 1)
1840  // Invert the condition.
1841  return DAG.getSetCC(dl, VT, Trunc, DAG.getConstant(0, dl, MVT::i1),
1842  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1843  SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1844  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1845  }
1846 
1847  // If truncating the setcc operands is not desirable, we can still
1848  // simplify the expression in some cases:
1849  // setcc ([sz]ext (setcc x, y, cc)), 0, setne) -> setcc (x, y, cc)
1850  // setcc ([sz]ext (setcc x, y, cc)), 0, seteq) -> setcc (x, y, inv(cc))
1851  // setcc (zext (setcc x, y, cc)), 1, setne) -> setcc (x, y, inv(cc))
1852  // setcc (zext (setcc x, y, cc)), 1, seteq) -> setcc (x, y, cc)
1853  // setcc (sext (setcc x, y, cc)), -1, setne) -> setcc (x, y, inv(cc))
1854  // setcc (sext (setcc x, y, cc)), -1, seteq) -> setcc (x, y, cc)
1855  SDValue TopSetCC = N0->getOperand(0);
1856  unsigned N0Opc = N0->getOpcode();
1857  bool SExt = (N0Opc == ISD::SIGN_EXTEND);
1858  if (TopSetCC.getValueType() == MVT::i1 && VT == MVT::i1 &&
1859  TopSetCC.getOpcode() == ISD::SETCC &&
1860  (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
1861  (isConstFalseVal(N1C) ||
1862  isExtendedTrueVal(N1C, N0->getValueType(0), SExt))) {
1863 
1864  bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) ||
1865  (!N1C->isNullValue() && Cond == ISD::SETNE);
1866 
1867  if (!Inverse)
1868  return TopSetCC;
1869 
1871  cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
1872  TopSetCC.getOperand(0).getValueType().isInteger());
1873  return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
1874  TopSetCC.getOperand(1),
1875  InvCond);
1876  }
1877  }
1878  }
1879 
1880  // If the LHS is '(and load, const)', the RHS is 0, the test is for
1881  // equality or unsigned, and all 1 bits of the const are in the same
1882  // partial word, see if we can shorten the load.
1883  if (DCI.isBeforeLegalize() &&
1884  !ISD::isSignedIntSetCC(Cond) &&
1885  N0.getOpcode() == ISD::AND && C1 == 0 &&
1886  N0.getNode()->hasOneUse() &&
1887  isa<LoadSDNode>(N0.getOperand(0)) &&
1888  N0.getOperand(0).getNode()->hasOneUse() &&
1889  isa<ConstantSDNode>(N0.getOperand(1))) {
1890  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1891  APInt bestMask;
1892  unsigned bestWidth = 0, bestOffset = 0;
1893  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1894  unsigned origWidth = N0.getValueSizeInBits();
1895  unsigned maskWidth = origWidth;
1896  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1897  // 8 bits, but have to be careful...
1898  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1899  origWidth = Lod->getMemoryVT().getSizeInBits();
1900  const APInt &Mask =
1901  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1902  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1903  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1904  for (unsigned offset=0; offset<origWidth/width; offset++) {
1905  if (Mask.isSubsetOf(newMask)) {
1906  if (DAG.getDataLayout().isLittleEndian())
1907  bestOffset = (uint64_t)offset * (width/8);
1908  else
1909  bestOffset = (origWidth/width - offset - 1) * (width/8);
1910  bestMask = Mask.lshr(offset * (width/8) * 8);
1911  bestWidth = width;
1912  break;
1913  }
1914  newMask <<= width;
1915  }
1916  }
1917  }
1918  if (bestWidth) {
1919  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1920  if (newVT.isRound()) {
1921  EVT PtrType = Lod->getOperand(1).getValueType();
1922  SDValue Ptr = Lod->getBasePtr();
1923  if (bestOffset != 0)
1924  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1925  DAG.getConstant(bestOffset, dl, PtrType));
1926  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1927  SDValue NewLoad = DAG.getLoad(
1928  newVT, dl, Lod->getChain(), Ptr,
1929  Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign);
1930  return DAG.getSetCC(dl, VT,
1931  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1932  DAG.getConstant(bestMask.trunc(bestWidth),
1933  dl, newVT)),
1934  DAG.getConstant(0LL, dl, newVT), Cond);
1935  }
1936  }
1937  }
1938 
1939  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1940  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1941  unsigned InSize = N0.getOperand(0).getValueSizeInBits();
1942 
1943  // If the comparison constant has bits in the upper part, the
1944  // zero-extended value could never match.
1945  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1946  C1.getBitWidth() - InSize))) {
1947  switch (Cond) {
1948  case ISD::SETUGT:
1949  case ISD::SETUGE:
1950  case ISD::SETEQ:
1951  return DAG.getConstant(0, dl, VT);
1952  case ISD::SETULT:
1953  case ISD::SETULE:
1954  case ISD::SETNE:
1955  return DAG.getConstant(1, dl, VT);
1956  case ISD::SETGT:
1957  case ISD::SETGE:
1958  // True if the sign bit of C1 is set.
1959  return DAG.getConstant(C1.isNegative(), dl, VT);
1960  case ISD::SETLT:
1961  case ISD::SETLE:
1962  // True if the sign bit of C1 isn't set.
1963  return DAG.getConstant(C1.isNonNegative(), dl, VT);
1964  default:
1965  break;
1966  }
1967  }
1968 
1969  // Otherwise, we can perform the comparison with the low bits.
1970  switch (Cond) {
1971  case ISD::SETEQ:
1972  case ISD::SETNE:
1973  case ISD::SETUGT:
1974  case ISD::SETUGE:
1975  case ISD::SETULT:
1976  case ISD::SETULE: {
1977  EVT newVT = N0.getOperand(0).getValueType();
1978  if (DCI.isBeforeLegalizeOps() ||
1979  (isOperationLegal(ISD::SETCC, newVT) &&
1980  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1981  EVT NewSetCCVT =
1982  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
1983  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1984 
1985  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1986  NewConst, Cond);
1987  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1988  }
1989  break;
1990  }
1991  default:
1992  break; // todo, be more careful with signed comparisons
1993  }
1994  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1995  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1996  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1997  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1998  EVT ExtDstTy = N0.getValueType();
1999  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2000 
2001  // If the constant doesn't fit into the number of bits for the source of
2002  // the sign extension, it is impossible for both sides to be equal.
2003  if (C1.getMinSignedBits() > ExtSrcTyBits)
2004  return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
2005 
2006  SDValue ZextOp;
2007  EVT Op0Ty = N0.getOperand(0).getValueType();
2008  if (Op0Ty == ExtSrcTy) {
2009  ZextOp = N0.getOperand(0);
2010  } else {
2011  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2012  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2013  DAG.getConstant(Imm, dl, Op0Ty));
2014  }
2015  if (!DCI.isCalledByLegalizer())
2016  DCI.AddToWorklist(ZextOp.getNode());
2017  // Otherwise, make this a use of a zext.
2018  return DAG.getSetCC(dl, VT, ZextOp,
2020  ExtDstTyBits,
2021  ExtSrcTyBits),
2022  dl, ExtDstTy),
2023  Cond);
2024  } else if ((N1C->isNullValue() || N1C->isOne()) &&
2025  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2026  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2027  if (N0.getOpcode() == ISD::SETCC &&
2028  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2029  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne());
2030  if (TrueWhenTrue)
2031  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2032  // Invert the condition.
2033  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2034  CC = ISD::getSetCCInverse(CC,
2035  N0.getOperand(0).getValueType().isInteger());
2036  if (DCI.isBeforeLegalizeOps() ||
2037  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
2038  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2039  }
2040 
2041  if ((N0.getOpcode() == ISD::XOR ||
2042  (N0.getOpcode() == ISD::AND &&
2043  N0.getOperand(0).getOpcode() == ISD::XOR &&
2044  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2045  isa<ConstantSDNode>(N0.getOperand(1)) &&
2046  cast<ConstantSDNode>(N0.getOperand(1))->isOne()) {
2047  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2048  // can only do this if the top bits are known zero.
2049  unsigned BitWidth = N0.getValueSizeInBits();
2050  if (DAG.MaskedValueIsZero(N0,
2051  APInt::getHighBitsSet(BitWidth,
2052  BitWidth-1))) {
2053  // Okay, get the un-inverted input value.
2054  SDValue Val;
2055  if (N0.getOpcode() == ISD::XOR) {
2056  Val = N0.getOperand(0);
2057  } else {
2058  assert(N0.getOpcode() == ISD::AND &&
2059  N0.getOperand(0).getOpcode() == ISD::XOR);
2060  // ((X^1)&1)^1 -> X & 1
2061  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2062  N0.getOperand(0).getOperand(0),
2063  N0.getOperand(1));
2064  }
2065 
2066  return DAG.getSetCC(dl, VT, Val, N1,
2067  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2068  }
2069  } else if (N1C->isOne() &&
2070  (VT == MVT::i1 ||
2071  getBooleanContents(N0->getValueType(0)) ==
2073  SDValue Op0 = N0;
2074  if (Op0.getOpcode() == ISD::TRUNCATE)
2075  Op0 = Op0.getOperand(0);
2076 
2077  if ((Op0.getOpcode() == ISD::XOR) &&
2078  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2079  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2080  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2081  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2082  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2083  Cond);
2084  }
2085  if (Op0.getOpcode() == ISD::AND &&
2086  isa<ConstantSDNode>(Op0.getOperand(1)) &&
2087  cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
2088  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2089  if (Op0.getValueType().bitsGT(VT))
2090  Op0 = DAG.getNode(ISD::AND, dl, VT,
2091  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2092  DAG.getConstant(1, dl, VT));
2093  else if (Op0.getValueType().bitsLT(VT))
2094  Op0 = DAG.getNode(ISD::AND, dl, VT,
2095  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2096  DAG.getConstant(1, dl, VT));
2097 
2098  return DAG.getSetCC(dl, VT, Op0,
2099  DAG.getConstant(0, dl, Op0.getValueType()),
2100  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2101  }
2102  if (Op0.getOpcode() == ISD::AssertZext &&
2103  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
2104  return DAG.getSetCC(dl, VT, Op0,
2105  DAG.getConstant(0, dl, Op0.getValueType()),
2106  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2107  }
2108  }
2109 
2110  APInt MinVal, MaxVal;
2111  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2112  if (ISD::isSignedIntSetCC(Cond)) {
2113  MinVal = APInt::getSignedMinValue(OperandBitSize);
2114  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2115  } else {
2116  MinVal = APInt::getMinValue(OperandBitSize);
2117  MaxVal = APInt::getMaxValue(OperandBitSize);
2118  }
2119 
2120  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2121  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2122  // X >= MIN --> true
2123  if (C1 == MinVal)
2124  return DAG.getBoolConstant(true, dl, VT, OpVT);
2125 
2126  // X >= C0 --> X > (C0 - 1)
2127  APInt C = C1 - 1;
2128  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
2129  if ((DCI.isBeforeLegalizeOps() ||
2130  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
2131  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
2133  return DAG.getSetCC(dl, VT, N0,
2134  DAG.getConstant(C, dl, N1.getValueType()),
2135  NewCC);
2136  }
2137  }
2138 
2139  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2140  // X <= MAX --> true
2141  if (C1 == MaxVal)
2142  return DAG.getBoolConstant(true, dl, VT, OpVT);
2143 
2144  // X <= C0 --> X < (C0 + 1)
2145  APInt C = C1 + 1;
2146  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
2147  if ((DCI.isBeforeLegalizeOps() ||
2148  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
2149  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
2151  return DAG.getSetCC(dl, VT, N0,
2152  DAG.getConstant(C, dl, N1.getValueType()),
2153  NewCC);
2154  }
2155  }
2156 
2157  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2158  return DAG.getBoolConstant(false, dl, VT, OpVT); // X < MIN --> false
2159  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2160  return DAG.getBoolConstant(false, dl, VT, OpVT); // X > MAX --> false
2161 
2162  // Canonicalize setgt X, Min --> setne X, Min
2163  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2164  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2165  // Canonicalize setlt X, Max --> setne X, Max
2166  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2167  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2168 
2169  // If we have setult X, 1, turn it into seteq X, 0
2170  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2171  return DAG.getSetCC(dl, VT, N0,
2172  DAG.getConstant(MinVal, dl, N0.getValueType()),
2173  ISD::SETEQ);
2174  // If we have setugt X, Max-1, turn it into seteq X, Max
2175  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2176  return DAG.getSetCC(dl, VT, N0,
2177  DAG.getConstant(MaxVal, dl, N0.getValueType()),
2178  ISD::SETEQ);
2179 
2180  // If we have "setcc X, C0", check to see if we can shrink the immediate
2181  // by changing cc.
2182 
2183  // SETUGT X, SINTMAX -> SETLT X, 0
2184  if (Cond == ISD::SETUGT &&
2185  C1 == APInt::getSignedMaxValue(OperandBitSize))
2186  return DAG.getSetCC(dl, VT, N0,
2187  DAG.getConstant(0, dl, N1.getValueType()),
2188  ISD::SETLT);
2189 
2190  // SETULT X, SINTMIN -> SETGT X, -1
2191  if (Cond == ISD::SETULT &&
2192  C1 == APInt::getSignedMinValue(OperandBitSize)) {
2193  SDValue ConstMinusOne =
2194  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
2195  N1.getValueType());
2196  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2197  }
2198 
2199  // Fold bit comparisons when we can.
2200  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2201  (VT == N0.getValueType() ||
2202  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2203  N0.getOpcode() == ISD::AND) {
2204  auto &DL = DAG.getDataLayout();
2205  if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2206  EVT ShiftTy = DCI.isBeforeLegalize()
2207  ? getPointerTy(DL)
2208  : getShiftAmountTy(N0.getValueType(), DL);
2209  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2210  // Perform the xform if the AND RHS is a single bit.
2211  if (AndRHS->getAPIntValue().isPowerOf2()) {
2212  return DAG.getNode(ISD::TRUNCATE, dl, VT,
2213  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2214  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
2215  ShiftTy)));
2216  }
2217  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2218  // (X & 8) == 8 --> (X & 8) >> 3
2219  // Perform the xform if C1 is a single bit.
2220  if (C1.isPowerOf2()) {
2221  return DAG.getNode(ISD::TRUNCATE, dl, VT,
2222  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2223  DAG.getConstant(C1.logBase2(), dl,
2224  ShiftTy)));
2225  }
2226  }
2227  }
2228  }
2229 
2230  if (C1.getMinSignedBits() <= 64 &&
2231  !isLegalICmpImmediate(C1.getSExtValue())) {
2232  // (X & -256) == 256 -> (X >> 8) == 1
2233  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2234  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2235  if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2236  const APInt &AndRHSC = AndRHS->getAPIntValue();
2237  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2238  unsigned ShiftBits = AndRHSC.countTrailingZeros();
2239  auto &DL = DAG.getDataLayout();
2240  EVT ShiftTy = DCI.isBeforeLegalize()
2241  ? getPointerTy(DL)
2242  : getShiftAmountTy(N0.getValueType(), DL);
2243  EVT CmpTy = N0.getValueType();
2244  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2245  DAG.getConstant(ShiftBits, dl,
2246  ShiftTy));
2247  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
2248  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2249  }
2250  }
2251  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2252  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2253  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2254  // X < 0x100000000 -> (X >> 32) < 1
2255  // X >= 0x100000000 -> (X >> 32) >= 1
2256  // X <= 0x0ffffffff -> (X >> 32) < 1
2257  // X > 0x0ffffffff -> (X >> 32) >= 1
2258  unsigned ShiftBits;
2259  APInt NewC = C1;
2260  ISD::CondCode NewCond = Cond;
2261  if (AdjOne) {
2262  ShiftBits = C1.countTrailingOnes();
2263  NewC = NewC + 1;
2264  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2265  } else {
2266  ShiftBits = C1.countTrailingZeros();
2267  }
2268  NewC.lshrInPlace(ShiftBits);
2269  if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
2271  auto &DL = DAG.getDataLayout();
2272  EVT ShiftTy = DCI.isBeforeLegalize()
2273  ? getPointerTy(DL)
2274  : getShiftAmountTy(N0.getValueType(), DL);
2275  EVT CmpTy = N0.getValueType();
2276  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2277  DAG.getConstant(ShiftBits, dl, ShiftTy));
2278  SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
2279  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2280  }
2281  }
2282  }
2283  }
2284 
2285  if (isa<ConstantFPSDNode>(N0.getNode())) {
2286  // Constant fold or commute setcc.
2287  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2288  if (O.getNode()) return O;
2289  } else if (auto *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2290  // If the RHS of an FP comparison is a constant, simplify it away in
2291  // some cases.
2292  if (CFP->getValueAPF().isNaN()) {
2293  // If an operand is known to be a nan, we can fold it.
2294  switch (ISD::getUnorderedFlavor(Cond)) {
2295  default: llvm_unreachable("Unknown flavor!");
2296  case 0: // Known false.
2297  return DAG.getBoolConstant(false, dl, VT, OpVT);
2298  case 1: // Known true.
2299  return DAG.getBoolConstant(true, dl, VT, OpVT);
2300  case 2: // Undefined.
2301  return DAG.getUNDEF(VT);
2302  }
2303  }
2304 
2305  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2306  // constant if knowing that the operand is non-nan is enough. We prefer to
2307  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2308  // materialize 0.0.
2309  if (Cond == ISD::SETO || Cond == ISD::SETUO)
2310  return DAG.getSetCC(dl, VT, N0, N0, Cond);
2311 
2312  // setcc (fneg x), C -> setcc swap(pred) x, -C
2313  if (N0.getOpcode() == ISD::FNEG) {
2315  if (DCI.isBeforeLegalizeOps() ||
2316  isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
2317  SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
2318  return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
2319  }
2320  }
2321 
2322  // If the condition is not legal, see if we can find an equivalent one
2323  // which is legal.
2324  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2325  // If the comparison was an awkward floating-point == or != and one of
2326  // the comparison operands is infinity or negative infinity, convert the
2327  // condition to a less-awkward <= or >=.
2328  if (CFP->getValueAPF().isInfinity()) {
2329  if (CFP->getValueAPF().isNegative()) {
2330  if (Cond == ISD::SETOEQ &&
2332  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2333  if (Cond == ISD::SETUEQ &&
2335  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2336  if (Cond == ISD::SETUNE &&
2338  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2339  if (Cond == ISD::SETONE &&
2341  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2342  } else {
2343  if (Cond == ISD::SETOEQ &&
2345  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2346  if (Cond == ISD::SETUEQ &&
2348  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2349  if (Cond == ISD::SETUNE &&
2351  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2352  if (Cond == ISD::SETONE &&
2354  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2355  }
2356  }
2357  }
2358  }
2359 
2360  if (N0 == N1) {
2361  // The sext(setcc()) => setcc() optimization relies on the appropriate
2362  // constant being emitted.
2363 
2364  bool EqTrue = ISD::isTrueWhenEqual(Cond);
2365 
2366  // We can always fold X == X for integer setcc's.
2367  if (N0.getValueType().isInteger())
2368  return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2369 
2370  unsigned UOF = ISD::getUnorderedFlavor(Cond);
2371  if (UOF == 2) // FP operators that are undefined on NaNs.
2372  return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2373  if (UOF == unsigned(EqTrue))
2374  return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
2375  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2376  // if it is not already.
2377  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2378  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2379  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
2380  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2381  }
2382 
2383  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2384  N0.getValueType().isInteger()) {
2385  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2386  N0.getOpcode() == ISD::XOR) {
2387  // Simplify (X+Y) == (X+Z) --> Y == Z
2388  if (N0.getOpcode() == N1.getOpcode()) {
2389  if (N0.getOperand(0) == N1.getOperand(0))
2390  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2391  if (N0.getOperand(1) == N1.getOperand(1))
2392  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2393  if (isCommutativeBinOp(N0.getOpcode())) {
2394  // If X op Y == Y op X, try other combinations.
2395  if (N0.getOperand(0) == N1.getOperand(1))
2396  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2397  Cond);
2398  if (N0.getOperand(1) == N1.getOperand(0))
2399  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2400  Cond);
2401  }
2402  }
2403 
2404  // If RHS is a legal immediate value for a compare instruction, we need
2405  // to be careful about increasing register pressure needlessly.
2406  bool LegalRHSImm = false;
2407 
2408  if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2409  if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2410  // Turn (X+C1) == C2 --> X == C2-C1
2411  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2412  return DAG.getSetCC(dl, VT, N0.getOperand(0),
2413  DAG.getConstant(RHSC->getAPIntValue()-
2414  LHSR->getAPIntValue(),
2415  dl, N0.getValueType()), Cond);
2416  }
2417 
2418  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2419  if (N0.getOpcode() == ISD::XOR)
2420  // If we know that all of the inverted bits are zero, don't bother
2421  // performing the inversion.
2422  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2423  return
2424  DAG.getSetCC(dl, VT, N0.getOperand(0),
2425  DAG.getConstant(LHSR->getAPIntValue() ^
2426  RHSC->getAPIntValue(),
2427  dl, N0.getValueType()),
2428  Cond);
2429  }
2430 
2431  // Turn (C1-X) == C2 --> X == C1-C2
2432  if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2433  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2434  return
2435  DAG.getSetCC(dl, VT, N0.getOperand(1),
2436  DAG.getConstant(SUBC->getAPIntValue() -
2437  RHSC->getAPIntValue(),
2438  dl, N0.getValueType()),
2439  Cond);
2440  }
2441  }
2442 
2443  // Could RHSC fold directly into a compare?
2444  if (RHSC->getValueType(0).getSizeInBits() <= 64)
2445  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2446  }
2447 
2448  // Simplify (X+Z) == X --> Z == 0
2449  // Don't do this if X is an immediate that can fold into a cmp
2450  // instruction and X+Z has other uses. It could be an induction variable
2451  // chain, and the transform would increase register pressure.
2452  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2453  if (N0.getOperand(0) == N1)
2454  return DAG.getSetCC(dl, VT, N0.getOperand(1),
2455  DAG.getConstant(0, dl, N0.getValueType()), Cond);
2456  if (N0.getOperand(1) == N1) {
2457  if (isCommutativeBinOp(N0.getOpcode()))
2458  return DAG.getSetCC(dl, VT, N0.getOperand(0),
2459  DAG.getConstant(0, dl, N0.getValueType()),
2460  Cond);
2461  if (N0.getNode()->hasOneUse()) {
2462  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2463  auto &DL = DAG.getDataLayout();
2464  // (Z-X) == X --> Z == X<<1
2465  SDValue SH = DAG.getNode(
2466  ISD::SHL, dl, N1.getValueType(), N1,
2467  DAG.getConstant(1, dl,
2468  getShiftAmountTy(N1.getValueType(), DL)));
2469  if (!DCI.isCalledByLegalizer())
2470  DCI.AddToWorklist(SH.getNode());
2471  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2472  }
2473  }
2474  }
2475  }
2476 
2477  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2478  N1.getOpcode() == ISD::XOR) {
2479  // Simplify X == (X+Z) --> Z == 0
2480  if (N1.getOperand(0) == N0)
2481  return DAG.getSetCC(dl, VT, N1.getOperand(1),
2482  DAG.getConstant(0, dl, N1.getValueType()), Cond);
2483  if (N1.getOperand(1) == N0) {
2484  if (isCommutativeBinOp(N1.getOpcode()))
2485  return DAG.getSetCC(dl, VT, N1.getOperand(0),
2486  DAG.getConstant(0, dl, N1.getValueType()), Cond);
2487  if (N1.getNode()->hasOneUse()) {
2488  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2489  auto &DL = DAG.getDataLayout();
2490  // X == (Z-X) --> X<<1 == Z
2491  SDValue SH = DAG.getNode(
2492  ISD::SHL, dl, N1.getValueType(), N0,
2493  DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL)));
2494  if (!DCI.isCalledByLegalizer())
2495  DCI.AddToWorklist(SH.getNode());
2496  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2497  }
2498  }
2499  }
2500 
2501  if (SDValue V = simplifySetCCWithAnd(VT, N0, N1, Cond, DCI, dl))
2502  return V;
2503  }
2504 
2505  // Fold away ALL boolean setcc's.
2506  SDValue Temp;
2507  if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
2508  EVT OpVT = N0.getValueType();
2509  switch (Cond) {
2510  default: llvm_unreachable("Unknown integer setcc!");
2511  case ISD::SETEQ: // X == Y -> ~(X^Y)
2512  Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
2513  N0 = DAG.getNOT(dl, Temp, OpVT);
2514  if (!DCI.isCalledByLegalizer())
2515  DCI.AddToWorklist(Temp.getNode());
2516  break;
2517  case ISD::SETNE: // X != Y --> (X^Y)
2518  N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
2519  break;
2520  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2521  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2522  Temp = DAG.getNOT(dl, N0, OpVT);
2523  N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
2524  if (!DCI.isCalledByLegalizer())
2525  DCI.AddToWorklist(Temp.getNode());
2526  break;
2527  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2528  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2529  Temp = DAG.getNOT(dl, N1, OpVT);
2530  N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
2531  if (!DCI.isCalledByLegalizer())
2532  DCI.AddToWorklist(Temp.getNode());
2533  break;
2534  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2535  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2536  Temp = DAG.getNOT(dl, N0, OpVT);
2537  N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
2538  if (!DCI.isCalledByLegalizer())
2539  DCI.AddToWorklist(Temp.getNode());
2540  break;
2541  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2542  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2543  Temp = DAG.getNOT(dl, N1, OpVT);
2544  N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
2545  break;
2546  }
2547  if (VT.getScalarType() != MVT::i1) {
2548  if (!DCI.isCalledByLegalizer())
2549  DCI.AddToWorklist(N0.getNode());
2550  // FIXME: If running after legalize, we probably can't do this.
2552  N0 = DAG.getNode(ExtendCode, dl, VT, N0);
2553  }
2554  return N0;
2555  }
2556 
2557  // Could not fold it.
2558  return SDValue();
2559 }
2560 
2561 /// Returns true (and the GlobalValue and the offset) if the node is a
2562 /// GlobalAddress + offset.
2564  int64_t &Offset) const {
2565  if (auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
2566  GA = GASD->getGlobal();
2567  Offset += GASD->getOffset();
2568  return true;
2569  }
2570 
2571  if (N->getOpcode() == ISD::ADD) {
2572  SDValue N1 = N->getOperand(0);
2573  SDValue N2 = N->getOperand(1);
2574  if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2575  if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
2576  Offset += V->getSExtValue();
2577  return true;
2578  }
2579  } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2580  if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
2581  Offset += V->getSExtValue();
2582  return true;
2583  }
2584  }
2585  }
2586 
2587  return false;
2588 }
2589 
2591  DAGCombinerInfo &DCI) const {
2592  // Default implementation: no optimization.
2593  return SDValue();
2594 }
2595 
2596 //===----------------------------------------------------------------------===//
2597 // Inline Assembler Implementation Methods
2598 //===----------------------------------------------------------------------===//
2599 
2602  unsigned S = Constraint.size();
2603 
2604  if (S == 1) {
2605  switch (Constraint[0]) {
2606  default: break;
2607  case 'r': return C_RegisterClass;
2608  case 'm': // memory
2609  case 'o': // offsetable
2610  case 'V': // not offsetable
2611  return C_Memory;
2612  case 'i': // Simple Integer or Relocatable Constant
2613  case 'n': // Simple Integer
2614  case 'E': // Floating Point Constant
2615  case 'F': // Floating Point Constant
2616  case 's': // Relocatable Constant
2617  case 'p': // Address.
2618  case 'X': // Allow ANY value.
2619  case 'I': // Target registers.
2620  case 'J':
2621  case 'K':
2622  case 'L':
2623  case 'M':
2624  case 'N':
2625  case 'O':
2626  case 'P':
2627  case '<':
2628  case '>':
2629  return C_Other;
2630  }
2631  }
2632 
2633  if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2634  if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
2635  return C_Memory;
2636  return C_Register;
2637  }
2638  return C_Unknown;
2639 }
2640 
2641 /// Try to replace an X constraint, which matches anything, with another that
2642 /// has more specific requirements based on the type of the corresponding
2643 /// operand.
2644 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2645  if (ConstraintVT.isInteger())
2646  return "r";
2647  if (ConstraintVT.isFloatingPoint())
2648  return "f"; // works for many targets
2649  return nullptr;
2650 }
2651 
2652 /// Lower the specified operand into the Ops vector.
2653 /// If it is invalid, don't add anything to Ops.
2655  std::string &Constraint,
2656  std::vector<SDValue> &Ops,
2657  SelectionDAG &DAG) const {
2658 
2659  if (Constraint.length() > 1) return;
2660 
2661  char ConstraintLetter = Constraint[0];
2662  switch (ConstraintLetter) {
2663  default: break;
2664  case 'X': // Allows any operand; labels (basic block) use this.
2665  if (Op.getOpcode() == ISD::BasicBlock) {
2666  Ops.push_back(Op);
2667  return;
2668  }
2670  case 'i': // Simple Integer or Relocatable Constant
2671  case 'n': // Simple Integer
2672  case 's': { // Relocatable Constant
2673  // These operands are interested in values of the form (GV+C), where C may
2674  // be folded in as an offset of GV, or it may be explicitly added. Also, it
2675  // is possible and fine if either GV or C are missing.
2678 
2679  // If we have "(add GV, C)", pull out GV/C
2680  if (Op.getOpcode() == ISD::ADD) {
2681  C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2683  if (!C || !GA) {
2684  C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2686  }
2687  if (!C || !GA) {
2688  C = nullptr;
2689  GA = nullptr;
2690  }
2691  }
2692 
2693  // If we find a valid operand, map to the TargetXXX version so that the
2694  // value itself doesn't get selected.
2695  if (GA) { // Either &GV or &GV+C
2696  if (ConstraintLetter != 'n') {
2697  int64_t Offs = GA->getOffset();
2698  if (C) Offs += C->getZExtValue();
2699  Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2700  C ? SDLoc(C) : SDLoc(),
2701  Op.getValueType(), Offs));
2702  }
2703  return;
2704  }
2705  if (C) { // just C, no GV.
2706  // Simple constants are not allowed for 's'.
2707  if (ConstraintLetter != 's') {
2708  // gcc prints these as sign extended. Sign extend value to 64 bits
2709  // now; without this it would get ZExt'd later in
2710  // ScheduleDAGSDNodes::EmitNode, which is very generic.
2711  Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
2712  SDLoc(C), MVT::i64));
2713  }
2714  return;
2715  }
2716  break;
2717  }
2718  }
2719 }
2720 
2721 std::pair<unsigned, const TargetRegisterClass *>
2723  StringRef Constraint,
2724  MVT VT) const {
2725  if (Constraint.empty() || Constraint[0] != '{')
2726  return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2727  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2728 
2729  // Remove the braces from around the name.
2730  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2731 
2732  std::pair<unsigned, const TargetRegisterClass*> R =
2733  std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2734 
2735  // Figure out which register class contains this reg.
2736  for (const TargetRegisterClass *RC : RI->regclasses()) {
2737  // If none of the value types for this register class are valid, we
2738  // can't use it. For example, 64-bit reg classes on 32-bit targets.
2739  if (!isLegalRC(*RI, *RC))
2740  continue;
2741 
2742  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2743  I != E; ++I) {
2744  if (RegName.equals_lower(RI->getRegAsmName(*I))) {
2745  std::pair<unsigned, const TargetRegisterClass*> S =
2746  std::make_pair(*I, RC);
2747 
2748  // If this register class has the requested value type, return it,
2749  // otherwise keep searching and return the first class found
2750  // if no other is found which explicitly has the requested type.
2751  if (RI->isTypeLegalForClass(*RC, VT))
2752  return S;
2753  if (!R.second)
2754  R = S;
2755  }
2756  }
2757  }
2758 
2759  return R;
2760 }
2761 
2762 //===----------------------------------------------------------------------===//
2763 // Constraint Selection.
2764 
2765 /// Return true of this is an input operand that is a matching constraint like
2766 /// "4".
2768  assert(!ConstraintCode.empty() && "No known constraint!");
2769  return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2770 }
2771 
2772 /// If this is an input matching constraint, this method returns the output
2773 /// operand it matches.
2775  assert(!ConstraintCode.empty() && "No known constraint!");
2776  return atoi(ConstraintCode.c_str());
2777 }
2778 
2779 /// Split up the constraint string from the inline assembly value into the
2780 /// specific constraints and their prefixes, and also tie in the associated
2781 /// operand values.
2782 /// If this returns an empty vector, and if the constraint string itself
2783 /// isn't empty, there was an error parsing.
2786  const TargetRegisterInfo *TRI,
2787  ImmutableCallSite CS) const {
2788  /// Information about all of the constraints.
2789  AsmOperandInfoVector ConstraintOperands;
2790  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2791  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2792 
2793  // Do a prepass over the constraints, canonicalizing them, and building up the
2794  // ConstraintOperands list.
2795  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2796  unsigned ResNo = 0; // ResNo - The result number of the next output.
2797 
2798  for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2799  ConstraintOperands.emplace_back(std::move(CI));
2800  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2801 
2802  // Update multiple alternative constraint count.
2803  if (OpInfo.multipleAlternatives.size() > maCount)
2804  maCount = OpInfo.multipleAlternatives.size();
2805 
2806  OpInfo.ConstraintVT = MVT::Other;
2807 
2808  // Compute the value type for each operand.
2809  switch (OpInfo.Type) {
2810  case InlineAsm::isOutput:
2811  // Indirect outputs just consume an argument.
2812  if (OpInfo.isIndirect) {
2813  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2814  break;
2815  }
2816 
2817  // The return value of the call is this value. As such, there is no
2818  // corresponding argument.
2819  assert(!CS.getType()->isVoidTy() &&
2820  "Bad inline asm!");
2821  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2822  OpInfo.ConstraintVT =
2823  getSimpleValueType(DL, STy->getElementType(ResNo));
2824  } else {
2825  assert(ResNo == 0 && "Asm only has one result!");
2826  OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
2827  }
2828  ++ResNo;
2829  break;
2830  case InlineAsm::isInput:
2831  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2832  break;
2833  case InlineAsm::isClobber:
2834  // Nothing to do.
2835  break;
2836  }
2837 
2838  if (OpInfo.CallOperandVal) {
2839  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2840  if (OpInfo.isIndirect) {
2841  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2842  if (!PtrTy)
2843  report_fatal_error("Indirect operand for inline asm not a pointer!");
2844  OpTy = PtrTy->getElementType();
2845  }
2846 
2847  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2848  if (StructType *STy = dyn_cast<StructType>(OpTy))
2849  if (STy->getNumElements() == 1)
2850  OpTy = STy->getElementType(0);
2851 
2852  // If OpTy is not a single value, it may be a struct/union that we
2853  // can tile with integers.
2854  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2855  unsigned BitSize = DL.getTypeSizeInBits(OpTy);
2856  switch (BitSize) {
2857  default: break;
2858  case 1:
2859  case 8:
2860  case 16:
2861  case 32:
2862  case 64:
2863  case 128:
2864  OpInfo.ConstraintVT =
2865  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2866  break;
2867  }
2868  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2869  unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
2870  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2871  } else {
2872  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2873  }
2874  }
2875  }
2876 
2877  // If we have multiple alternative constraints, select the best alternative.
2878  if (!ConstraintOperands.empty()) {
2879  if (maCount) {
2880  unsigned bestMAIndex = 0;
2881  int bestWeight = -1;
2882  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2883  int weight = -1;
2884  unsigned maIndex;
2885  // Compute the sums of the weights for each alternative, keeping track
2886  // of the best (highest weight) one so far.
2887  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2888  int weightSum = 0;
2889  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2890  cIndex != eIndex; ++cIndex) {
2891  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2892  if (OpInfo.Type == InlineAsm::isClobber)
2893  continue;
2894 
2895  // If this is an output operand with a matching input operand,
2896  // look up the matching input. If their types mismatch, e.g. one
2897  // is an integer, the other is floating point, or their sizes are
2898  // different, flag it as an maCantMatch.
2899  if (OpInfo.hasMatchingInput()) {
2900  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2901  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2902  if ((OpInfo.ConstraintVT.isInteger() !=
2903  Input.ConstraintVT.isInteger()) ||
2904  (OpInfo.ConstraintVT.getSizeInBits() !=
2905  Input.ConstraintVT.getSizeInBits())) {
2906  weightSum = -1; // Can't match.
2907  break;
2908  }
2909  }
2910  }
2911  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2912  if (weight == -1) {
2913  weightSum = -1;
2914  break;
2915  }
2916  weightSum += weight;
2917  }
2918  // Update best.
2919  if (weightSum > bestWeight) {
2920  bestWeight = weightSum;
2921  bestMAIndex = maIndex;
2922  }
2923  }
2924 
2925  // Now select chosen alternative in each constraint.
2926  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2927  cIndex != eIndex; ++cIndex) {
2928  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2929  if (cInfo.Type == InlineAsm::isClobber)
2930  continue;
2931  cInfo.selectAlternative(bestMAIndex);
2932  }
2933  }
2934  }
2935 
2936  // Check and hook up tied operands, choose constraint code to use.
2937  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2938  cIndex != eIndex; ++cIndex) {
2939  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2940 
2941  // If this is an output operand with a matching input operand, look up the
2942  // matching input. If their types mismatch, e.g. one is an integer, the
2943  // other is floating point, or their sizes are different, flag it as an
2944  // error.
2945  if (OpInfo.hasMatchingInput()) {
2946  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2947 
2948  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2949  std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2951  OpInfo.ConstraintVT);
2952  std::pair<unsigned, const TargetRegisterClass *> InputRC =
2954  Input.ConstraintVT);
2955  if ((OpInfo.ConstraintVT.isInteger() !=
2956  Input.ConstraintVT.isInteger()) ||
2957  (MatchRC.second != InputRC.second)) {
2958  report_fatal_error("Unsupported asm: input constraint"
2959  " with a matching output constraint of"
2960  " incompatible type!");
2961  }
2962  }
2963  }
2964  }
2965 
2966  return ConstraintOperands;
2967 }
2968 
2969 /// Return an integer indicating how general CT is.
2971  switch (CT) {
2974  return 0;
2976  return 1;
2978  return 2;
2980  return 3;
2981  }
2982  llvm_unreachable("Invalid constraint type");
2983 }
2984 
2985 /// Examine constraint type and operand type and determine a weight value.
2986 /// This object must already have been set up with the operand type
2987 /// and the current alternative constraint selected.
2990  AsmOperandInfo &info, int maIndex) const {
2992  if (maIndex >= (int)info.multipleAlternatives.size())
2993  rCodes = &info.Codes;
2994  else
2995  rCodes = &info.multipleAlternatives[maIndex].Codes;
2996  ConstraintWeight BestWeight = CW_Invalid;
2997 
2998  // Loop over the options, keeping track of the most general one.
2999  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3000  ConstraintWeight weight =
3001  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3002  if (weight > BestWeight)
3003  BestWeight = weight;
3004  }
3005 
3006  return BestWeight;
3007 }
3008 
3009 /// Examine constraint type and operand type and determine a weight value.
3010 /// This object must already have been set up with the operand type
3011 /// and the current alternative constraint selected.
3014  AsmOperandInfo &info, const char *constraint) const {
3015  ConstraintWeight weight = CW_Invalid;
3016  Value *CallOperandVal = info.CallOperandVal;
3017  // If we don't have a value, we can't do a match,
3018  // but allow it at the lowest weight.
3019  if (!CallOperandVal)
3020  return CW_Default;
3021  // Look at the constraint type.
3022  switch (*constraint) {
3023  case 'i': // immediate integer.
3024  case 'n': // immediate integer with a known value.
3025  if (isa<ConstantInt>(CallOperandVal))
3026  weight = CW_Constant;
3027  break;
3028  case 's': // non-explicit intregal immediate.
3029  if (isa<GlobalValue>(CallOperandVal))
3030  weight = CW_Constant;
3031  break;
3032  case 'E': // immediate float if host format.
3033  case 'F': // immediate float.
3034  if (isa<ConstantFP>(CallOperandVal))
3035  weight = CW_Constant;
3036  break;
3037  case '<': // memory operand with autodecrement.
3038  case '>': // memory operand with autoincrement.
3039  case 'm': // memory operand.
3040  case 'o': // offsettable memory operand
3041  case 'V': // non-offsettable memory operand
3042  weight = CW_Memory;
3043  break;
3044  case 'r': // general register.
3045  case 'g': // general register, memory operand or immediate integer.
3046  // note: Clang converts "g" to "imr".
3047  if (CallOperandVal->getType()->isIntegerTy())
3048  weight = CW_Register;
3049  break;
3050  case 'X': // any operand.
3051  default:
3052  weight = CW_Default;
3053  break;
3054  }
3055  return weight;
3056 }
3057 
3058 /// If there are multiple different constraints that we could pick for this
3059 /// operand (e.g. "imr") try to pick the 'best' one.
3060 /// This is somewhat tricky: constraints fall into four classes:
3061 /// Other -> immediates and magic values
3062 /// Register -> one specific register
3063 /// RegisterClass -> a group of regs
3064 /// Memory -> memory
3065 /// Ideally, we would pick the most specific constraint possible: if we have
3066 /// something that fits into a register, we would pick it. The problem here
3067 /// is that if we have something that could either be in a register or in
3068 /// memory that use of the register could cause selection of *other*
3069 /// operands to fail: they might only succeed if we pick memory. Because of
3070 /// this the heuristic we use is:
3071 ///
3072 /// 1) If there is an 'other' constraint, and if the operand is valid for
3073 /// that constraint, use it. This makes us take advantage of 'i'
3074 /// constraints when available.
3075 /// 2) Otherwise, pick the most general constraint present. This prefers
3076 /// 'm' over 'r', for example.
3077 ///
3079  const TargetLowering &TLI,
3080  SDValue Op, SelectionDAG *DAG) {
3081  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3082  unsigned BestIdx = 0;
3084  int BestGenerality = -1;
3085 
3086  // Loop over the options, keeping track of the most general one.
3087  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3089  TLI.getConstraintType(OpInfo.Codes[i]);
3090 
3091  // If this is an 'other' constraint, see if the operand is valid for it.
3092  // For example, on X86 we might have an 'rI' constraint. If the operand
3093  // is an integer in the range [0..31] we want to use I (saving a load
3094  // of a register), otherwise we must use 'r'.
3095  if (CType == TargetLowering::C_Other && Op.getNode()) {
3096  assert(OpInfo.Codes[i].size() == 1 &&
3097  "Unhandled multi-letter 'other' constraint");
3098  std::vector<SDValue> ResultOps;
3099  TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3100  ResultOps, *DAG);
3101  if (!ResultOps.empty()) {
3102  BestType = CType;
3103  BestIdx = i;
3104  break;
3105  }
3106  }
3107 
3108  // Things with matching constraints can only be registers, per gcc
3109  // documentation. This mainly affects "g" constraints.
3110  if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3111  continue;
3112 
3113  // This constraint letter is more general than the previous one, use it.
3114  int Generality = getConstraintGenerality(CType);
3115  if (Generality > BestGenerality) {
3116  BestType = CType;
3117  BestIdx = i;
3118  BestGenerality = Generality;
3119  }
3120  }
3121 
3122  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3123  OpInfo.ConstraintType = BestType;
3124 }
3125 
3126 /// Determines the constraint code and constraint type to use for the specific
3127 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3129  SDValue Op,
3130  SelectionDAG *DAG) const {
3131  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3132 
3133  // Single-letter constraints ('r') are very common.
3134  if (OpInfo.Codes.size() == 1) {
3135  OpInfo.ConstraintCode = OpInfo.Codes[0];
3137  } else {
3138  ChooseConstraint(OpInfo, *this, Op, DAG);
3139  }
3140 
3141  // 'X' matches anything.
3142  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3143  // Labels and constants are handled elsewhere ('X' is the only thing
3144  // that matches labels). For Functions, the type here is the type of
3145  // the result, which is not what we want to look at; leave them alone.
3146  Value *v = OpInfo.CallOperandVal;
3147  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3148  OpInfo.CallOperandVal = v;
3149  return;
3150  }
3151 
3152  // Otherwise, try to resolve it to something we know about by looking at
3153  // the actual operand type.
3154  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3155  OpInfo.ConstraintCode = Repl;
3157  }
3158  }
3159 }
3160 
3161 /// \brief Given an exact SDIV by a constant, create a multiplication
3162 /// with the multiplicative inverse of the constant.
3164  const SDLoc &dl, SelectionDAG &DAG,
3165  std::vector<SDNode *> &Created) {
3166  assert(d != 0 && "Division by zero!");
3167 
3168  // Shift the value upfront if it is even, so the LSB is one.
3169  unsigned ShAmt = d.countTrailingZeros();
3170  if (ShAmt) {
3171  // TODO: For UDIV use SRL instead of SRA.
3172  SDValue Amt =
3173  DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType(),
3174  DAG.getDataLayout()));
3175  SDNodeFlags Flags;
3176  Flags.setExact(true);
3177  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, Flags);
3178  Created.push_back(Op1.getNode());
3179  d.ashrInPlace(ShAmt);
3180  }
3181 
3182  // Calculate the multiplicative inverse, using Newton's method.
3183  APInt t, xn = d;
3184  while ((t = d*xn) != 1)
3185  xn *= APInt(d.getBitWidth(), 2) - t;
3186 
3187  SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
3188  SDValue Mul = DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3189  Created.push_back(Mul.getNode());
3190  return Mul;
3191 }
3192 
3194  SelectionDAG &DAG,
3195  std::vector<SDNode *> *Created) const {
3197  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3198  if (TLI.isIntDivCheap(N->getValueType(0), Attr))
3199  return SDValue(N,0); // Lower SDIV as SDIV
3200  return SDValue();
3201 }
3202 
3203 /// \brief Given an ISD::SDIV node expressing a divide by constant,
3204 /// return a DAG expression to select that will generate the same value by
3205 /// multiplying by a magic number.
3206 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
3208  SelectionDAG &DAG, bool IsAfterLegalization,
3209  std::vector<SDNode *> *Created) const {
3210  assert(Created && "No vector to hold sdiv ops.");
3211 
3212  EVT VT = N->getValueType(0);
3213  SDLoc dl(N);
3214 
3215  // Check to see if we can do this.
3216  // FIXME: We should be more aggressive here.
3217  if (!isTypeLegal(VT))
3218  return SDValue();
3219 
3220  // If the sdiv has an 'exact' bit we can use a simpler lowering.
3221  if (N->getFlags().hasExact())
3222  return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
3223 
3224  APInt::ms magics = Divisor.magic();
3225 
3226  // Multiply the numerator (operand 0) by the magic value
3227  // FIXME: We should support doing a MUL in a wider type
3228  SDValue Q;
3229  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3231  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3232  DAG.getConstant(magics.m, dl, VT));
3233  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3235  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3236  N->getOperand(0),
3237  DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
3238  else
3239  return SDValue(); // No mulhs or equvialent
3240  // If d > 0 and m < 0, add the numerator
3241  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
3242  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3243  Created->push_back(Q.getNode());
3244  }
3245  // If d < 0 and m > 0, subtract the numerator.
3246  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
3247  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3248  Created->push_back(Q.getNode());
3249  }
3250  auto &DL = DAG.getDataLayout();
3251  // Shift right algebraic if shift value is nonzero
3252  if (magics.s > 0) {
3253  Q = DAG.getNode(
3254  ISD::SRA, dl, VT, Q,
3255  DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
3256  Created->push_back(Q.getNode());
3257  }
3258  // Extract the sign bit and add it to the quotient
3259  SDValue T =
3260  DAG.getNode(ISD::SRL, dl, VT, Q,
3261  DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
3262  getShiftAmountTy(Q.getValueType(), DL)));
3263  Created->push_back(T.getNode());
3264  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3265 }
3266 
3267 /// \brief Given an ISD::UDIV node expressing a divide by constant,
3268 /// return a DAG expression to select that will generate the same value by
3269 /// multiplying by a magic number.
3270 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
3272  SelectionDAG &DAG, bool IsAfterLegalization,
3273  std::vector<SDNode *> *Created) const {
3274  assert(Created && "No vector to hold udiv ops.");
3275 
3276  EVT VT = N->getValueType(0);
3277  SDLoc dl(N);
3278  auto &DL = DAG.getDataLayout();
3279 
3280  // Check to see if we can do this.
3281  // FIXME: We should be more aggressive here.
3282  if (!isTypeLegal(VT))
3283  return SDValue();
3284 
3285  // FIXME: We should use a narrower constant when the upper
3286  // bits are known to be zero.
3287  APInt::mu magics = Divisor.magicu();
3288 
3289  SDValue Q = N->getOperand(0);
3290 
3291  // If the divisor is even, we can avoid using the expensive fixup by shifting
3292  // the divided value upfront.
3293  if (magics.a != 0 && !Divisor[0]) {
3294  unsigned Shift = Divisor.countTrailingZeros();
3295  Q = DAG.getNode(
3296  ISD::SRL, dl, VT, Q,
3297  DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL)));
3298  Created->push_back(Q.getNode());
3299 
3300  // Get magic number for the shifted divisor.
3301  magics = Divisor.lshr(Shift).magicu(Shift);
3302  assert(magics.a == 0 && "Should use cheap fixup now");
3303  }
3304 
3305  // Multiply the numerator (operand 0) by the magic value
3306  // FIXME: We should support doing a MUL in a wider type
3307  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3309  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
3310  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3312  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3313  DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
3314  else
3315  return SDValue(); // No mulhu or equivalent
3316 
3317  Created->push_back(Q.getNode());
3318 
3319  if (magics.a == 0) {
3320  assert(magics.s < Divisor.getBitWidth() &&
3321  "We shouldn't generate an undefined shift!");
3322  return DAG.getNode(
3323  ISD::SRL, dl, VT, Q,
3324  DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
3325  } else {
3326  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3327  Created->push_back(NPQ.getNode());
3328  NPQ = DAG.getNode(
3329  ISD::SRL, dl, VT, NPQ,
3330  DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
3331  Created->push_back(NPQ.getNode());
3332  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3333  Created->push_back(NPQ.getNode());
3334  return DAG.getNode(
3335  ISD::SRL, dl, VT, NPQ,
3336  DAG.getConstant(magics.s - 1, dl,
3337  getShiftAmountTy(NPQ.getValueType(), DL)));
3338  }
3339 }
3340 
3341 bool TargetLowering::
3343  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
3344  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
3345  "be a constant integer");
3346  return true;
3347  }
3348 
3349  return false;
3350 }
3351 
3352 //===----------------------------------------------------------------------===//
3353 // Legalization Utilities
3354 //===----------------------------------------------------------------------===//
3355 
3356 bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl,
3357  SDValue LHS, SDValue RHS,
3358  SmallVectorImpl<SDValue> &Result,
3359  EVT HiLoVT, SelectionDAG &DAG,
3361  SDValue LH, SDValue RL, SDValue RH) const {
3362  assert(Opcode == ISD::MUL || Opcode == ISD::UMUL_LOHI ||
3363  Opcode == ISD::SMUL_LOHI);
3364 
3365  bool HasMULHS = (Kind == MulExpansionKind::Always) ||
3367  bool HasMULHU = (Kind == MulExpansionKind::Always) ||
3369  bool HasSMUL_LOHI = (Kind == MulExpansionKind::Always) ||
3371  bool HasUMUL_LOHI = (Kind == MulExpansionKind::Always) ||
3373 
3374  if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
3375  return false;
3376 
3377  unsigned OuterBitSize = VT.getScalarSizeInBits();
3378  unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
3379  unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
3380  unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
3381 
3382  // LL, LH, RL, and RH must be either all NULL or all set to a value.
3383  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
3384  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
3385 
3386  SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
3387  auto MakeMUL_LOHI = [&](SDValue L, SDValue R, SDValue &Lo, SDValue &Hi,
3388  bool Signed) -> bool {
3389  if ((Signed && HasSMUL_LOHI) || (!Signed && HasUMUL_LOHI)) {
3390  Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
3391  Hi = SDValue(Lo.getNode(), 1);
3392  return true;
3393  }
3394  if ((Signed && HasMULHS) || (!Signed && HasMULHU)) {
3395  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
3396  Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
3397  return true;
3398  }
3399  return false;
3400  };
3401 
3402  SDValue Lo, Hi;
3403 
3404  if (!LL.getNode() && !RL.getNode() &&
3406  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
3407  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
3408  }
3409 
3410  if (!LL.getNode())
3411  return false;
3412 
3413  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
3414  if (DAG.MaskedValueIsZero(LHS, HighMask) &&
3415  DAG.MaskedValueIsZero(RHS, HighMask)) {
3416  // The inputs are both zero-extended.
3417  if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
3418  Result.push_back(Lo);
3419  Result.push_back(Hi);
3420  if (Opcode != ISD::MUL) {
3421  SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
3422  Result.push_back(Zero);
3423  Result.push_back(Zero);
3424  }
3425  return true;
3426  }
3427  }
3428 
3429  if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
3430  RHSSB > InnerBitSize) {
3431  // The input values are both sign-extended.
3432  // TODO non-MUL case?
3433  if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
3434  Result.push_back(Lo);
3435  Result.push_back(Hi);
3436  return true;
3437  }
3438  }
3439 
3440  unsigned ShiftAmount = OuterBitSize - InnerBitSize;
3441  EVT ShiftAmountTy = getShiftAmountTy(VT, DAG.getDataLayout());
3442  if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
3443  // FIXME getShiftAmountTy does not always return a sensible result when VT
3444  // is an illegal type, and so the type may be too small to fit the shift
3445  // amount. Override it with i32. The shift will have to be legalized.
3446  ShiftAmountTy = MVT::i32;
3447  }
3448  SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
3449 
3450  if (!LH.getNode() && !RH.getNode() &&
3453  LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
3454  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
3455  RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift);
3456  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
3457  }
3458 
3459  if (!LH.getNode())
3460  return false;
3461 
3462  if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
3463  return false;
3464 
3465  Result.push_back(Lo);
3466 
3467  if (Opcode == ISD::MUL) {
3468  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
3469  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
3470  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
3471  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
3472  Result.push_back(Hi);
3473  return true;
3474  }
3475 
3476  // Compute the full width result.
3477  auto Merge = [&](SDValue Lo, SDValue Hi) -> SDValue {
3478  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3479  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
3480  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3481  return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
3482  };
3483 
3484  SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
3485  if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
3486  return false;
3487 
3488  // This is effectively the add part of a multiply-add of half-sized operands,
3489  // so it cannot overflow.
3490  Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
3491 
3492  if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
3493  return false;
3494 
3495  Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
3496  Merge(Lo, Hi));
3497 
3498  SDValue Carry = Next.getValue(1);
3499  Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
3500  Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
3501 
3502  if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
3503  return false;
3504 
3505  SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
3506  Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
3507  Carry);
3508  Next = DAG.getNode(ISD::ADD, dl, VT, Next, Merge(Lo, Hi));
3509 
3510  if (Opcode == ISD::SMUL_LOHI) {
3511  SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
3512  DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
3513  Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
3514 
3515  NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
3516  DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
3517  Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
3518  }
3519 
3520  Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
3521  Next = DAG.getNode(ISD::SRL, dl, VT, Next, Shift);
3522  Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
3523  return true;
3524 }
3525 
3528  SDValue LL, SDValue LH, SDValue RL,
3529  SDValue RH) const {
3530  SmallVector<SDValue, 2> Result;
3531  bool Ok = expandMUL_LOHI(N->getOpcode(), N->getValueType(0), N,
3532  N->getOperand(0), N->getOperand(1), Result, HiLoVT,
3533  DAG, Kind, LL, LH, RL, RH);
3534  if (Ok) {
3535  assert(Result.size() == 2);
3536  Lo = Result[0];
3537  Hi = Result[1];
3538  }
3539  return Ok;
3540 }
3541 
3543  SelectionDAG &DAG) const {
3544  EVT VT = Node->getOperand(0).getValueType();
3545  EVT NVT = Node->getValueType(0);
3546  SDLoc dl(SDValue(Node, 0));
3547 
3548  // FIXME: Only f32 to i64 conversions are supported.
3549  if (VT != MVT::f32 || NVT != MVT::i64)
3550  return false;
3551 
3552  // Expand f32 -> i64 conversion
3553  // This algorithm comes from compiler-rt's implementation of fixsfdi:
3554  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
3555  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
3556  VT.getSizeInBits());
3557  SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
3558  SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
3559  SDValue Bias = DAG.getConstant(127, dl, IntVT);
3560  SDValue SignMask = DAG.getConstant(APInt::getSignMask(VT.getSizeInBits()), dl,
3561  IntVT);
3562  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
3563  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
3564 
3565  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3566 
3567  auto &DL = DAG.getDataLayout();
3568  SDValue ExponentBits = DAG.getNode(
3569  ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3570  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL)));
3571  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3572 
3573  SDValue Sign = DAG.getNode(
3574  ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3575  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT, DL)));
3576  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
3577 
3578  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3579  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3580  DAG.getConstant(0x00800000, dl, IntVT));
3581 
3582  R = DAG.getZExtOrTrunc(R, dl, NVT);
3583 
3584  R = DAG.getSelectCC(
3585  dl, Exponent, ExponentLoBit,
3586  DAG.getNode(ISD::SHL, dl, NVT, R,
3587  DAG.getZExtOrTrunc(
3588  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3589  dl, getShiftAmountTy(IntVT, DL))),
3590  DAG.getNode(ISD::SRL, dl, NVT, R,
3591  DAG.getZExtOrTrunc(
3592  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3593  dl, getShiftAmountTy(IntVT, DL))),
3594  ISD::SETGT);
3595 
3596  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3597  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3598  Sign);
3599 
3600  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3601  DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);
3602  return true;
3603 }
3604 
3606  SelectionDAG &DAG) const {
3607  SDLoc SL(LD);
3608  SDValue Chain = LD->getChain();
3609  SDValue BasePTR = LD->getBasePtr();
3610  EVT SrcVT = LD->getMemoryVT();
3611  ISD::LoadExtType ExtType = LD->getExtensionType();
3612 
3613  unsigned NumElem = SrcVT.getVectorNumElements();
3614 
3615  EVT SrcEltVT = SrcVT.getScalarType();
3616  EVT DstEltVT = LD->getValueType(0).getScalarType();
3617 
3618  unsigned Stride = SrcEltVT.getSizeInBits() / 8;
3619  assert(SrcEltVT.isByteSized());
3620 
3621  EVT PtrVT = BasePTR.getValueType();
3622 
3624  SmallVector<SDValue, 8> LoadChains;
3625 
3626  for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
3627  SDValue ScalarLoad =
3628  DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
3629  LD->getPointerInfo().getWithOffset(Idx * Stride),
3630  SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride),
3631  LD->getMemOperand()->getFlags(), LD->getAAInfo());
3632 
3633  BasePTR = DAG.getNode(ISD::ADD, SL, PtrVT, BasePTR,
3634  DAG.getConstant(Stride, SL, PtrVT));
3635 
3636  Vals.push_back(ScalarLoad.getValue(0));
3637  LoadChains.push_back(ScalarLoad.getValue(1));
3638  }
3639 
3640  SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains);
3641  SDValue Value = DAG.getBuildVector(LD->getValueType(0), SL, Vals);
3642 
3643  return DAG.getMergeValues({ Value, NewChain }, SL);
3644 }
3645 
3647  SelectionDAG &DAG) const {
3648  SDLoc SL(ST);
3649 
3650  SDValue Chain = ST->getChain();
3651  SDValue BasePtr = ST->getBasePtr();
3652  SDValue Value = ST->getValue();
3653  EVT StVT = ST->getMemoryVT();
3654 
3655  // The type of the data we want to save
3656  EVT RegVT = Value.getValueType();
3657  EVT RegSclVT = RegVT.getScalarType();
3658 
3659  // The type of data as saved in memory.
3660  EVT MemSclVT = StVT.getScalarType();
3661 
3662  EVT IdxVT = getVectorIdxTy(DAG.getDataLayout());
3663  unsigned NumElem = StVT.getVectorNumElements();
3664 
3665  // A vector must always be stored in memory as-is, i.e. without any padding
3666  // between the elements, since various code depend on it, e.g. in the
3667  // handling of a bitcast of a vector type to int, which may be done with a
3668  // vector store followed by an integer load. A vector that does not have
3669  // elements that are byte-sized must therefore be stored as an integer
3670  // built out of the extracted vector elements.
3671  if (!MemSclVT.isByteSized()) {
3672  unsigned NumBits = StVT.getSizeInBits();
3673  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
3674 
3675  SDValue CurrVal = DAG.getConstant(0, SL, IntVT);
3676 
3677  for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
3678  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
3679  DAG.getConstant(Idx, SL, IdxVT));
3680  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MemSclVT, Elt);
3681  SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
3682  unsigned ShiftIntoIdx =
3683  (DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
3684  SDValue ShiftAmount =
3685  DAG.getConstant(ShiftIntoIdx * MemSclVT.getSizeInBits(), SL, IntVT);
3686  SDValue ShiftedElt =
3687  DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
3688  CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
3689  }
3690 
3691  return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
3692  ST->getAlignment(), ST->getMemOperand()->getFlags(),
3693  ST->getAAInfo());
3694  }
3695 
3696  // Store Stride in bytes
3697  unsigned Stride = MemSclVT.getSizeInBits() / 8;
3698  assert (Stride && "Zero stride!");
3699  // Extract each of the elements from the original vector and save them into
3700  // memory individually.
3701  SmallVector<SDValue, 8> Stores;
3702  for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
3703  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, RegSclVT, Value,
3704  DAG.getConstant(Idx, SL, IdxVT));
3705 
3706  SDValue Ptr = DAG.getObjectPtrOffset(SL, BasePtr, Idx * Stride);
3707 
3708  // This scalar TruncStore may be illegal, but we legalize it later.
3709  SDValue Store = DAG.getTruncStore(
3710  Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
3711  MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride),
3712  ST->getMemOperand()->getFlags(), ST->getAAInfo());
3713 
3714  Stores.push_back(Store);
3715  }
3716 
3717  return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Stores);
3718 }
3719 
3720 std::pair<SDValue, SDValue>
3723  "unaligned indexed loads not implemented!");
3724  SDValue Chain = LD->getChain();
3725  SDValue Ptr = LD->getBasePtr();
3726  EVT VT = LD->getValueType(0);
3727  EVT LoadedVT = LD->getMemoryVT();
3728  SDLoc dl(LD);
3729  auto &MF = DAG.getMachineFunction();
3730 
3731  if (VT.isFloatingPoint() || VT.isVector()) {
3732  EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
3733  if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) {
3734  if (!isOperationLegalOrCustom(ISD::LOAD, intVT)) {
3735  // Scalarize the load and let the individual components be handled.
3736  SDValue Scalarized = scalarizeVectorLoad(LD, DAG);
3737  return std::make_pair(Scalarized.getValue(0), Scalarized.getValue(1));
3738  }
3739 
3740  // Expand to a (misaligned) integer load of the same size,
3741  // then bitconvert to floating point or vector.
3742  SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
3743  LD->getMemOperand());
3744  SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
3745  if (LoadedVT != VT)
3746  Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
3747  ISD::ANY_EXTEND, dl, VT, Result);
3748 
3749  return std::make_pair(Result, newLoad.getValue(1));
3750  }
3751 
3752  // Copy the value to a (aligned) stack slot using (unaligned) integer
3753  // loads and stores, then do a (aligned) load from the stack slot.
3754  MVT RegVT = getRegisterType(*DAG.getContext(), intVT);
3755  unsigned LoadedBytes = LoadedVT.getStoreSize();
3756  unsigned RegBytes = RegVT.getSizeInBits() / 8;
3757  unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
3758 
3759  // Make sure the stack slot is also aligned for the register type.
3760  SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
3761  auto FrameIndex = cast<FrameIndexSDNode>(StackBase.getNode())->getIndex();
3762  SmallVector<SDValue, 8> Stores;
3763  SDValue StackPtr = StackBase;
3764  unsigned Offset = 0;
3765 
3766  EVT PtrVT = Ptr.getValueType();
3767  EVT StackPtrVT = StackPtr.getValueType();
3768 
3769  SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
3770  SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
3771 
3772  // Do all but one copies using the full register width.
3773  for (unsigned i = 1; i < NumRegs; i++) {
3774  // Load one integer register's worth from the original location.
3775  SDValue Load = DAG.getLoad(
3776  RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
3778  LD->getAAInfo());
3779  // Follow the load with a store to the stack slot. Remember the store.
3780  Stores.push_back(DAG.getStore(
3781  Load.getValue(1), dl, Load, StackPtr,
3783  // Increment the pointers.
3784  Offset += RegBytes;
3785 
3786  Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
3787  StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
3788  }
3789 
3790  // The last copy may be partial. Do an extending load.
3791  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
3792  8 * (LoadedBytes - Offset));
3793  SDValue Load =
3794  DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
3795  LD->getPointerInfo().getWithOffset(Offset), MemVT,
3796  MinAlign(LD->getAlignment(), Offset),
3797  LD->getMemOperand()->getFlags(), LD->getAAInfo());
3798  // Follow the load with a store to the stack slot. Remember the store.
3799  // On big-endian machines this requires a truncating store to ensure
3800  // that the bits end up in the right place.
3801  Stores.push_back(DAG.getTruncStore(
3802  Load.getValue(1), dl, Load, StackPtr,
3803  MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT));
3804 
3805  // The order of the stores doesn't matter - say it with a TokenFactor.
3806  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
3807 
3808  // Finally, perform the original load only redirected to the stack slot.
3809  Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
3811  LoadedVT);
3812 
3813  // Callers expect a MERGE_VALUES node.
3814  return std::make_pair(Load, TF);
3815  }
3816 
3817  assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
3818  "Unaligned load of unsupported type.");
3819 
3820  // Compute the new VT that is half the size of the old one. This is an
3821  // integer MVT.
3822  unsigned NumBits = LoadedVT.getSizeInBits();
3823  EVT NewLoadedVT;
3824  NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
3825  NumBits >>= 1;
3826 
3827  unsigned Alignment = LD->getAlignment();
3828  unsigned IncrementSize = NumBits / 8;
3829  ISD::LoadExtType HiExtType = LD->getExtensionType();
3830 
3831  // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
3832  if (HiExtType == ISD::NON_EXTLOAD)
3833  HiExtType = ISD::ZEXTLOAD;
3834 
3835  // Load the value in two parts
3836  SDValue Lo, Hi;
3837  if (DAG.getDataLayout().isLittleEndian()) {
3838  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
3839  NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
3840  LD->getAAInfo());
3841 
3842  Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3843  Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
3844  LD->getPointerInfo().getWithOffset(IncrementSize),
3845  NewLoadedVT, MinAlign(Alignment, IncrementSize),
3846  LD->getMemOperand()->getFlags(), LD->getAAInfo());
3847  } else {
3848  Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
3849  NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
3850  LD->getAAInfo());
3851 
3852  Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3853  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
3854  LD->getPointerInfo().getWithOffset(IncrementSize),
3855  NewLoadedVT, MinAlign(Alignment, IncrementSize),
3856  LD->getMemOperand()->getFlags(), LD->getAAInfo());
3857  }
3858 
3859  // aggregate the two parts
3860  SDValue ShiftAmount =
3861  DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(),
3862  DAG.getDataLayout()));
3863  SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
3864  Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
3865 
3866  SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3867  Hi.getValue(1));
3868 
3869  return std::make_pair(Result, TF);
3870 }
3871 
3873  SelectionDAG &DAG) const {
3875  "unaligned indexed stores not implemented!");
3876  SDValue Chain = ST->getChain();
3877  SDValue Ptr = ST->getBasePtr();
3878  SDValue Val = ST->getValue();
3879  EVT VT = Val.getValueType();
3880  int Alignment = ST->getAlignment();
3881  auto &MF = DAG.getMachineFunction();
3882 
3883  SDLoc dl(ST);
3884  if (ST->getMemoryVT().isFloatingPoint() ||
3885  ST->getMemoryVT().isVector()) {
3886  EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
3887  if (isTypeLegal(intVT)) {
3888  if (!isOperationLegalOrCustom(ISD::STORE, intVT)) {
3889  // Scalarize the store and let the individual components be handled.
3890  SDValue Result = scalarizeVectorStore(ST, DAG);
3891 
3892  return Result;
3893  }
3894  // Expand to a bitconvert of the value to the integer type of the
3895  // same size, then a (misaligned) int store.
3896  // FIXME: Does not handle truncating floating point stores!
3897  SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
3898  Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
3899  Alignment, ST->getMemOperand()->getFlags());
3900  return Result;
3901  }
3902  // Do a (aligned) store to a stack slot, then copy from the stack slot
3903  // to the final destination using (unaligned) integer loads and stores.
3904  EVT StoredVT = ST->getMemoryVT();
3905  MVT RegVT =
3906  getRegisterType(*DAG.getContext(),
3908  StoredVT.getSizeInBits()));
3909  EVT PtrVT = Ptr.getValueType();
3910  unsigned StoredBytes = StoredVT.getStoreSize();
3911  unsigned RegBytes = RegVT.getSizeInBits() / 8;
3912  unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
3913 
3914  // Make sure the stack slot is also aligned for the register type.
3915  SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
3916  auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
3917 
3918  // Perform the original store, only redirected to the stack slot.
3919  SDValue Store = DAG.getTruncStore(
3920  Chain, dl, Val, StackPtr,
3921  MachinePointerInfo::getFixedStack(MF, FrameIndex, 0), StoredVT);
3922 
3923  EVT StackPtrVT = StackPtr.getValueType();
3924 
3925  SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
3926  SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
3927  SmallVector<SDValue, 8> Stores;
3928  unsigned Offset = 0;
3929 
3930  // Do all but one copies using the full register width.
3931  for (unsigned i = 1; i < NumRegs; i++) {
3932  // Load one integer register's worth from the stack slot.
3933  SDValue Load = DAG.getLoad(
3934  RegVT, dl, Store, StackPtr,
3936  // Store it to the final location. Remember the store.
3937  Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
3938  ST->getPointerInfo().getWithOffset(Offset),
3939  MinAlign(ST->getAlignment(), Offset),
3940  ST->getMemOperand()->getFlags()));
3941  // Increment the pointers.
3942  Offset += RegBytes;
3943  StackPtr = DAG.getObjectPtrOffset(dl, StackPtr, StackPtrIncrement);
3944  Ptr = DAG.getObjectPtrOffset(dl, Ptr, PtrIncrement);
3945  }
3946 
3947  // The last store may be partial. Do a truncating store. On big-endian
3948  // machines this requires an extending load from the stack slot to ensure
3949  // that the bits are in the right place.
3950  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
3951  8 * (StoredBytes - Offset));
3952 
3953  // Load from the stack slot.
3954  SDValue Load = DAG.getExtLoad(
3955  ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
3956  MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), MemVT);
3957 
3958  Stores.push_back(
3959  DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
3960  ST->getPointerInfo().getWithOffset(Offset), MemVT,
3961  MinAlign(ST->getAlignment(), Offset),
3962  ST->getMemOperand()->getFlags(), ST->getAAInfo()));
3963  // The order of the stores doesn't matter - say it with a TokenFactor.
3964  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
3965  return Result;
3966  }
3967 
3968  assert(ST->getMemoryVT().isInteger() &&
3969  !ST->getMemoryVT().isVector() &&
3970  "Unaligned store of unknown type.");
3971  // Get the half-size VT
3972  EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
3973  int NumBits = NewStoredVT.getSizeInBits();
3974  int IncrementSize = NumBits / 8;
3975 
3976  // Divide the stored value in two parts.
3977  SDValue ShiftAmount =
3978  DAG.getConstant(NumBits, dl, getShiftAmountTy(Val.getValueType(),
3979  DAG.getDataLayout()));
3980  SDValue Lo = Val;
3981  SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
3982 
3983  // Store the two parts
3984  SDValue Store1, Store2;
3985  Store1 = DAG.getTruncStore(Chain, dl,
3986  DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
3987  Ptr, ST->getPointerInfo(), NewStoredVT, Alignment,
3988  ST->getMemOperand()->getFlags());
3989 
3990  Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3991  Alignment = MinAlign(Alignment, IncrementSize);
3992  Store2 = DAG.getTruncStore(
3993  Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
3994  ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment,
3995  ST->getMemOperand()->getFlags(), ST->getAAInfo());
3996 
3997  SDValue Result =
3998  DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
3999  return Result;
4000 }
4001 
4002 SDValue
4004  const SDLoc &DL, EVT DataVT,
4005  SelectionDAG &DAG,
4006  bool IsCompressedMemory) const {
4007  SDValue Increment;
4008  EVT AddrVT = Addr.getValueType();
4009  EVT MaskVT = Mask.getValueType();
4010  assert(DataVT.getVectorNumElements() == MaskVT.getVectorNumElements() &&
4011  "Incompatible types of Data and Mask");
4012  if (IsCompressedMemory) {
4013  // Incrementing the pointer according to number of '1's in the mask.
4014  EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits());
4015  SDValue MaskInIntReg = DAG.getBitcast(MaskIntVT, Mask);
4016  if (MaskIntVT.getSizeInBits() < 32) {
4017  MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg);
4018  MaskIntVT = MVT::i32;
4019  }
4020 
4021  // Count '1's with POPCNT.
4022  Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg);
4023  Increment = DAG.getZExtOrTrunc(Increment, DL, AddrVT);
4024  // Scale is an element size in bytes.
4025  SDValue Scale = DAG.getConstant(DataVT.getScalarSizeInBits() / 8, DL,
4026  AddrVT);
4027  Increment = DAG.getNode(ISD::MUL, DL, AddrVT, Increment, Scale);
4028  } else
4029  Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT);
4030 
4031  return DAG.getNode(ISD::ADD, DL, AddrVT, Addr, Increment);
4032 }
4033 
4035  SDValue Idx,
4036  EVT VecVT,
4037  const SDLoc &dl) {
4038  if (isa<ConstantSDNode>(Idx))
4039  return Idx;
4040 
4041  EVT IdxVT = Idx.getValueType();
4042  unsigned NElts = VecVT.getVectorNumElements();
4043  if (isPowerOf2_32(NElts)) {
4045  Log2_32(NElts));
4046  return DAG.getNode(ISD::AND, dl, IdxVT, Idx,
4047  DAG.getConstant(Imm, dl, IdxVT));
4048  }
4049 
4050  return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx,
4051  DAG.getConstant(NElts - 1, dl, IdxVT));
4052 }
4053 
4055  SDValue VecPtr, EVT VecVT,
4056  SDValue Index) const {
4057  SDLoc dl(Index);
4058  // Make sure the index type is big enough to compute in.
4059  Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType());
4060 
4061  EVT EltVT = VecVT.getVectorElementType();
4062 
4063  // Calculate the element offset and add it to the pointer.
4064  unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
4065  assert(EltSize * 8 == EltVT.getSizeInBits() &&
4066  "Converting bits to bytes lost precision");
4067 
4068  Index = clampDynamicVectorIndex(DAG, Index, VecVT, dl);
4069 
4070  EVT IdxVT = Index.getValueType();
4071 
4072  Index = DAG.getNode(ISD::MUL, dl, IdxVT, Index,
4073  DAG.getConstant(EltSize, dl, IdxVT));
4074  return DAG.getNode(ISD::ADD, dl, IdxVT, VecPtr, Index);
4075 }
4076 
4077 //===----------------------------------------------------------------------===//
4078 // Implementation of Emulated TLS Model
4079 //===----------------------------------------------------------------------===//
4080 
4082  SelectionDAG &DAG) const {
4083  // Access to address of TLS varialbe xyz is lowered to a function call:
4084  // __emutls_get_address( address of global variable named "__emutls_v.xyz" )
4085  EVT PtrVT = getPointerTy(DAG.getDataLayout());
4086  PointerType *VoidPtrType = Type::getInt8PtrTy(*DAG.getContext());
4087  SDLoc dl(GA);
4088 
4089  ArgListTy Args;
4090  ArgListEntry Entry;
4091  std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str();
4092  Module *VariableModule = const_cast<Module*>(GA->getGlobal()->getParent());
4093  StringRef EmuTlsVarName(NameString);
4094  GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName);
4095  assert(EmuTlsVar && "Cannot find EmuTlsVar ");
4096  Entry.Node = DAG.getGlobalAddress(EmuTlsVar, dl, PtrVT);
4097  Entry.Ty = VoidPtrType;
4098  Args.push_back(Entry);
4099 
4100  SDValue EmuTlsGetAddr = DAG.getExternalSymbol("__emutls_get_address", PtrVT);
4101 
4103  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode());
4104  CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args));
4105  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
4106 
4107  // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
4108  // At last for X86 targets, maybe good for other targets too?
4110  MFI.setAdjustsStack(true); // Is this only for X86 target?
4111  MFI.setHasCalls(true);
4112 
4113  assert((GA->getOffset() == 0) &&
4114  "Emulated TLS must have zero offset in GlobalAddressSDNode");
4115  return CallResult.first;
4116 }
4117 
4119  SelectionDAG &DAG) const {
4120  assert((Op->getOpcode() == ISD::SETCC) && "Input has to be a SETCC node.");
4121  if (!isCtlzFast())
4122  return SDValue();
4123  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
4124  SDLoc dl(Op);
4125  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4126  if (C->isNullValue() && CC == ISD::SETEQ) {
4127  EVT VT = Op.getOperand(0).getValueType();
4128  SDValue Zext = Op.getOperand(0);
4129  if (VT.bitsLT(MVT::i32)) {
4130  VT = MVT::i32;
4131  Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
4132  }
4133  unsigned Log2b = Log2_32(VT.getSizeInBits());
4134  SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
4135  SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
4136  DAG.getConstant(Log2b, dl, MVT::i32));
4137  return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
4138  }
4139  }
4140  return SDValue();
4141 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:546
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned char TargetFlags=0)
static MVT getIntegerVT(unsigned BitWidth)
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:544
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setSignBit()
Set the sign bit to 1.
Definition: APInt.h:1392
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
bool isUndef() const
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:555
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:923
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:313
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned getParamAlignment(unsigned ArgNo) const
Extract the alignment for a call or parameter (0=unknown).
Definition: CallSite.h:406
Various leaf nodes.
Definition: ISDOpcodes.h:60
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:343
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:262
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
const SDValue & getBasePtr() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
unsigned s
shift amount
Definition: APInt.h:1936
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:866
const SDValue & getValue() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:641
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
int MatchingInput
MatchingInput - If this is not -1, this is an output constraint where an input constraint is required...
Definition: InlineAsm.h:131
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
Definition: APInt.h:1308
static ISD::NodeType getExtendForContent(BooleanContent Content)
const GlobalVariable * getNamedGlobal(StringRef Name) const
Return the global variable in the module with the specified name, of arbitrary type.
Definition: Module.h:383
const SDValue & getChain() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
unsigned getAlignment() const
bool isBitwiseNot(SDValue V)
Returns true if V is a bitwise not operation.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:819
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
void setAllBits()
Set every bit to 1.
Definition: APInt.h:1369
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:350
The two locations do not alias at all.
Definition: AliasAnalysis.h:85
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
const SDNodeFlags getFlags() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:212
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal...
Definition: ISDOpcodes.h:964
bool isConstTrueVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:329
CallLoweringInfo & setDiscardResult(bool Value=true)
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1940
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:528
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:292
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1488
SDValue getExternalSymbol(const char *Sym, EVT VT)
bool hasMatchingInput() const
hasMatchingInput - Return true if this is an output constraint that has a matching input constraint...
Definition: InlineAsm.h:135
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
ConstraintCodeVector Codes
Code - The constraint code, either the register name (in braces) or the constraint letter/number...
Definition: InlineAsm.h:149
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.h:1611
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
void setNoSignedWrap(bool b)
ms magic() const
Calculate the magic numbers required to implement a signed integer division by a constant as a sequen...
Definition: APInt.cpp:1153
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:97
bool hasOneUse() const
Return true if there is exactly one use of this node.
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:516
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1382
static SDValue clampDynamicVectorIndex(SelectionDAG &DAG, SDValue Idx, EVT VecVT, const SDLoc &dl)
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
Try to simplify a setcc built with the specified operands and cc.
APInt shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:981
Shift and rotation operations.
Definition: ISDOpcodes.h:380
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
Class to represent struct types.
Definition: DerivedTypes.h:201
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef...
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:191
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDNode *> &Created)
Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the con...
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
op_iterator op_end() const
unsigned getScalarValueSizeInBits() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Reg
All possible values of the reg field in the ModR/M byte.
iterator_range< regclass_iterator > regclasses() const
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:304
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:449
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:390
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:511
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
Definition: APInt.h:966
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
zlib-gnu style compression
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
Context object for machine code objects.
Definition: MCContext.h:61
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
ValTy * getCalledValue() const
Return the pointer to function that is being called.
Definition: CallSite.h:100
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1512
int64_t getSExtValue() const
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
Definition: APInt.h:942
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1554
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:387
static SDNodeIterator begin(const SDNode *N)
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:399
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
Definition: APInt.cpp:405
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const
Return if N is a True value when extended to VT.
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Return true if the call or the callee has the given attribute.
Definition: CallSite.h:377
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
EK_BlockAddress - Each entry is a plain address of block, e.g.
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:219
CallLoweringInfo & setZExtResult(bool Value=true)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:855
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
virtual bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Vector Op.
op_iterator op_begin() const
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:561
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber.
Definition: InlineAsm.h:121
ArrayRef< SDUse > ops() const
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:951
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
amdgpu Simplify well known AMD library false Value * Callee
Class to represent pointers.
Definition: DerivedTypes.h:467
virtual StringRef getRegAsmName(unsigned Reg) const
Return the assembly name for Reg.
This class is used to represent ISD::STORE nodes.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:303
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:629
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:229
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:602
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
Check to see if the specified operand of the specified instruction is a constant integer.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
Definition: APInt.cpp:346
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:357
const SDValue & getBasePtr() const
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
std::vector< AsmOperandInfo > AsmOperandInfoVector
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:389
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:384
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool isIndirect
isIndirect - True if this operand is an indirect operand.
Definition: InlineAsm.h:145
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void resetAll()
Resets the known state of all bits.
Definition: KnownBits.h:66
iterator_range< value_op_iterator > op_values() const
bool isRound() const
Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:217
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:893