LLVM  6.0.0svn
NVPTXISelLowering.cpp
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1 //===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "NVPTXISelLowering.h"
17 #include "NVPTX.h"
18 #include "NVPTXSection.h"
19 #include "NVPTXSubtarget.h"
20 #include "NVPTXTargetMachine.h"
21 #include "NVPTXTargetObjectFile.h"
22 #include "NVPTXUtilities.h"
23 #include "llvm/ADT/APInt.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/IR/Argument.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/IR/Value.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CodeGen.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstdint>
59 #include <iterator>
60 #include <sstream>
61 #include <string>
62 #include <utility>
63 #include <vector>
64 
65 #define DEBUG_TYPE "nvptx-lower"
66 
67 using namespace llvm;
68 
69 static unsigned int uniqueCallSite = 0;
70 
72  "nvptx-sched4reg",
73  cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
74 
75 static cl::opt<unsigned>
77  cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
78  " 1: do it 2: do it aggressively"),
79  cl::init(2));
80 
82  "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
83  cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
84  " IEEE Compliant F32 div.rnd if available."),
85  cl::init(2));
86 
88  "nvptx-prec-sqrtf32", cl::Hidden,
89  cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
90  cl::init(true));
91 
93  "nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
94  cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
95  cl::init(false));
96 
98  if (UsePrecDivF32.getNumOccurrences() > 0) {
99  // If nvptx-prec-div32=N is used on the command-line, always honor it
100  return UsePrecDivF32;
101  } else {
102  // Otherwise, use div.approx if fast math is enabled
104  return 0;
105  else
106  return 2;
107  }
108 }
109 
111  if (UsePrecSqrtF32.getNumOccurrences() > 0) {
112  // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
113  return UsePrecSqrtF32;
114  } else {
115  // Otherwise, use sqrt.approx if fast math is enabled
117  }
118 }
119 
121  // TODO: Get rid of this flag; there can be only one way to do this.
122  if (FtzEnabled.getNumOccurrences() > 0) {
123  // If nvptx-f32ftz is used on the command-line, always honor it
124  return FtzEnabled;
125  } else {
126  const Function *F = MF.getFunction();
127  // Otherwise, check for an nvptx-f32ftz attribute on the function
128  if (F->hasFnAttribute("nvptx-f32ftz"))
129  return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
130  else
131  return false;
132  }
133 }
134 
135 static bool IsPTXVectorType(MVT VT) {
136  switch (VT.SimpleTy) {
137  default:
138  return false;
139  case MVT::v2i1:
140  case MVT::v4i1:
141  case MVT::v2i8:
142  case MVT::v4i8:
143  case MVT::v2i16:
144  case MVT::v4i16:
145  case MVT::v2i32:
146  case MVT::v4i32:
147  case MVT::v2i64:
148  case MVT::v2f16:
149  case MVT::v4f16:
150  case MVT::v8f16: // <4 x f16x2>
151  case MVT::v2f32:
152  case MVT::v4f32:
153  case MVT::v2f64:
154  return true;
155  }
156 }
157 
158 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
159 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
160 /// into their primitive components.
161 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
162 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
163 /// LowerCall, and LowerReturn.
164 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
165  Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
167  uint64_t StartingOffset = 0) {
168  SmallVector<EVT, 16> TempVTs;
169  SmallVector<uint64_t, 16> TempOffsets;
170 
171  // Special case for i128 - decompose to (i64, i64)
172  if (Ty->isIntegerTy(128)) {
173  ValueVTs.push_back(EVT(MVT::i64));
174  ValueVTs.push_back(EVT(MVT::i64));
175 
176  if (Offsets) {
177  Offsets->push_back(StartingOffset + 0);
178  Offsets->push_back(StartingOffset + 8);
179  }
180 
181  return;
182  }
183 
184  ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
185  for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
186  EVT VT = TempVTs[i];
187  uint64_t Off = TempOffsets[i];
188  // Split vectors into individual elements, except for v2f16, which
189  // we will pass as a single scalar.
190  if (VT.isVector()) {
191  unsigned NumElts = VT.getVectorNumElements();
192  EVT EltVT = VT.getVectorElementType();
193  // Vectors with an even number of f16 elements will be passed to
194  // us as an array of v2f16 elements. We must match this so we
195  // stay in sync with Ins/Outs.
196  if (EltVT == MVT::f16 && NumElts % 2 == 0) {
197  EltVT = MVT::v2f16;
198  NumElts /= 2;
199  }
200  for (unsigned j = 0; j != NumElts; ++j) {
201  ValueVTs.push_back(EltVT);
202  if (Offsets)
203  Offsets->push_back(Off + j * EltVT.getStoreSize());
204  }
205  } else {
206  ValueVTs.push_back(VT);
207  if (Offsets)
208  Offsets->push_back(Off);
209  }
210  }
211 }
212 
213 // Check whether we can merge loads/stores of some of the pieces of a
214 // flattened function parameter or return value into a single vector
215 // load/store.
216 //
217 // The flattened parameter is represented as a list of EVTs and
218 // offsets, and the whole structure is aligned to ParamAlignment. This
219 // function determines whether we can load/store pieces of the
220 // parameter starting at index Idx using a single vectorized op of
221 // size AccessSize. If so, it returns the number of param pieces
222 // covered by the vector op. Otherwise, it returns 1.
224  unsigned Idx, uint32_t AccessSize, const SmallVectorImpl<EVT> &ValueVTs,
225  const SmallVectorImpl<uint64_t> &Offsets, unsigned ParamAlignment) {
226  assert(isPowerOf2_32(AccessSize) && "must be a power of 2!");
227 
228  // Can't vectorize if param alignment is not sufficient.
229  if (AccessSize > ParamAlignment)
230  return 1;
231  // Can't vectorize if offset is not aligned.
232  if (Offsets[Idx] & (AccessSize - 1))
233  return 1;
234 
235  EVT EltVT = ValueVTs[Idx];
236  unsigned EltSize = EltVT.getStoreSize();
237 
238  // Element is too large to vectorize.
239  if (EltSize >= AccessSize)
240  return 1;
241 
242  unsigned NumElts = AccessSize / EltSize;
243  // Can't vectorize if AccessBytes if not a multiple of EltSize.
244  if (AccessSize != EltSize * NumElts)
245  return 1;
246 
247  // We don't have enough elements to vectorize.
248  if (Idx + NumElts > ValueVTs.size())
249  return 1;
250 
251  // PTX ISA can only deal with 2- and 4-element vector ops.
252  if (NumElts != 4 && NumElts != 2)
253  return 1;
254 
255  for (unsigned j = Idx + 1; j < Idx + NumElts; ++j) {
256  // Types do not match.
257  if (ValueVTs[j] != EltVT)
258  return 1;
259 
260  // Elements are not contiguous.
261  if (Offsets[j] - Offsets[j - 1] != EltSize)
262  return 1;
263  }
264  // OK. We can vectorize ValueVTs[i..i+NumElts)
265  return NumElts;
266 }
267 
268 // Flags for tracking per-element vectorization state of loads/stores
269 // of a flattened function parameter or return value.
271  PVF_INNER = 0x0, // Middle elements of a vector.
272  PVF_FIRST = 0x1, // First element of the vector.
273  PVF_LAST = 0x2, // Last element of the vector.
274  // Scalar is effectively a 1-element vector.
276 };
277 
278 // Computes whether and how we can vectorize the loads/stores of a
279 // flattened function parameter or return value.
280 //
281 // The flattened parameter is represented as the list of ValueVTs and
282 // Offsets, and is aligned to ParamAlignment bytes. We return a vector
283 // of the same size as ValueVTs indicating how each piece should be
284 // loaded/stored (i.e. as a scalar, or as part of a vector
285 // load/store).
289  unsigned ParamAlignment) {
290  // Set vector size to match ValueVTs and mark all elements as
291  // scalars by default.
293  VectorInfo.assign(ValueVTs.size(), PVF_SCALAR);
294 
295  // Check what we can vectorize using 128/64/32-bit accesses.
296  for (int I = 0, E = ValueVTs.size(); I != E; ++I) {
297  // Skip elements we've already processed.
298  assert(VectorInfo[I] == PVF_SCALAR && "Unexpected vector info state.");
299  for (unsigned AccessSize : {16, 8, 4, 2}) {
300  unsigned NumElts = CanMergeParamLoadStoresStartingAt(
301  I, AccessSize, ValueVTs, Offsets, ParamAlignment);
302  // Mark vectorized elements.
303  switch (NumElts) {
304  default:
305  llvm_unreachable("Unexpected return value");
306  case 1:
307  // Can't vectorize using this size, try next smaller size.
308  continue;
309  case 2:
310  assert(I + 1 < E && "Not enough elements.");
311  VectorInfo[I] = PVF_FIRST;
312  VectorInfo[I + 1] = PVF_LAST;
313  I += 1;
314  break;
315  case 4:
316  assert(I + 3 < E && "Not enough elements.");
317  VectorInfo[I] = PVF_FIRST;
318  VectorInfo[I + 1] = PVF_INNER;
319  VectorInfo[I + 2] = PVF_INNER;
320  VectorInfo[I + 3] = PVF_LAST;
321  I += 3;
322  break;
323  }
324  // Break out of the inner loop because we've already succeeded
325  // using largest possible AccessSize.
326  break;
327  }
328  }
329  return VectorInfo;
330 }
331 
332 // NVPTXTargetLowering Constructor.
334  const NVPTXSubtarget &STI)
335  : TargetLowering(TM), nvTM(&TM), STI(STI) {
336  // always lower memset, memcpy, and memmove intrinsics to load/store
337  // instructions, rather
338  // then generating calls to memset, mempcy or memmove.
339  MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
340  MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
341  MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
342 
345 
346  // Jump is Expensive. Don't create extra control flow for 'and', 'or'
347  // condition branches.
348  setJumpIsExpensive(true);
349 
350  // Wide divides are _very_ slow. Try to reduce the width of the divide if
351  // possible.
352  addBypassSlowDiv(64, 32);
353 
354  // By default, use the Source scheduling
355  if (sched4reg)
357  else
359 
360  auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
361  LegalizeAction NoF16Action) {
362  setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
363  };
364 
365  addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
366  addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
367  addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
368  addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
369  addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
370  addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
371  addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
372  addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass);
373 
374  // Conversion to/from FP16/FP16x2 is always legal.
379 
380  setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
381  setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
382 
383  // Operations not directly supported by NVPTX.
402  // Some SIGN_EXTEND_INREG can be done using cvt instruction.
403  // For others we will expand to a SHL/SRA pair.
409 
416 
419 
420  if (STI.hasROT64()) {
423  } else {
426  }
427  if (STI.hasROT32()) {
430  } else {
433  }
434 
442 
443  // Indirect branch is not supported.
444  // This also disables Jump Table creation.
447 
450 
451  // We want to legalize constant related memmove and memcopy
452  // intrinsics.
454 
455  // Turn FP extload into load/fpextend
465  // Turn FP truncstore into trunc + store.
466  // FIXME: vector types should also be expanded
470 
471  // PTX does not support load / store predicate registers
474 
475  for (MVT VT : MVT::integer_valuetypes()) {
479  }
480 
481  // This is legal in NVPTX
485 
486  // TRAP can be lowered to PTX trap
488 
491 
492  // Register custom handling for vector loads/stores
493  for (MVT VT : MVT::vector_valuetypes()) {
494  if (IsPTXVectorType(VT)) {
498  }
499  }
500 
501  // Custom handling for i8 intrinsics
503 
504  for (const auto& Ty : {MVT::i16, MVT::i32, MVT::i64}) {
510 
513  }
514 
518 
519  // PTX does not directly support SELP of i1, so promote to i32 first
521 
522  // PTX cannot multiply two i64s in a single instruction.
525 
526  // We have some custom DAG combine patterns for these nodes
534 
535  // setcc for f16x2 needs special handling to prevent legalizer's
536  // attempt to scalarize it due to v2i1 not being legal.
537  if (STI.allowFP16Math())
539 
540  // Promote fp16 arithmetic if fp16 hardware isn't available or the
541  // user passed --nvptx-no-fp16-math. The flag is useful because,
542  // although sm_53+ GPUs have some sort of FP16 support in
543  // hardware, only sm_53 and sm_60 have full implementation. Others
544  // only have token amount of hardware and are likely to run faster
545  // by using fp32 units instead.
546  for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
547  setFP16OperationAction(Op, MVT::f16, Legal, Promote);
548  setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
549  }
550 
551  // There's no neg.f16 instruction. Expand to (0-x).
554 
555  // (would be) Library functions.
556 
557  // These map to conversion instructions for scalar FP types.
558  for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
564  }
565 
566  // 'Expand' implements FCOPYSIGN without calling an external library.
571 
572  // These map to corresponding instructions for f32/f64. f16 must be
573  // promoted to f32. v2f16 is expanded to f16, which is then promoted
574  // to f32.
575  for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
581  }
586 
587  // No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate.
588  // No FPOW or FREM in PTX.
589 
590  // Now deduce the information based on the above mentioned
591  // actions
593 }
594 
595 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
596  switch ((NVPTXISD::NodeType)Opcode) {
598  break;
599  case NVPTXISD::CALL:
600  return "NVPTXISD::CALL";
601  case NVPTXISD::RET_FLAG:
602  return "NVPTXISD::RET_FLAG";
604  return "NVPTXISD::LOAD_PARAM";
605  case NVPTXISD::Wrapper:
606  return "NVPTXISD::Wrapper";
608  return "NVPTXISD::DeclareParam";
610  return "NVPTXISD::DeclareScalarParam";
612  return "NVPTXISD::DeclareRet";
614  return "NVPTXISD::DeclareScalarRet";
616  return "NVPTXISD::DeclareRetParam";
617  case NVPTXISD::PrintCall:
618  return "NVPTXISD::PrintCall";
620  return "NVPTXISD::PrintConvergentCall";
622  return "NVPTXISD::PrintCallUni";
624  return "NVPTXISD::PrintConvergentCallUni";
625  case NVPTXISD::LoadParam:
626  return "NVPTXISD::LoadParam";
628  return "NVPTXISD::LoadParamV2";
630  return "NVPTXISD::LoadParamV4";
632  return "NVPTXISD::StoreParam";
634  return "NVPTXISD::StoreParamV2";
636  return "NVPTXISD::StoreParamV4";
638  return "NVPTXISD::StoreParamS32";
640  return "NVPTXISD::StoreParamU32";
642  return "NVPTXISD::CallArgBegin";
643  case NVPTXISD::CallArg:
644  return "NVPTXISD::CallArg";
646  return "NVPTXISD::LastCallArg";
648  return "NVPTXISD::CallArgEnd";
649  case NVPTXISD::CallVoid:
650  return "NVPTXISD::CallVoid";
651  case NVPTXISD::CallVal:
652  return "NVPTXISD::CallVal";
654  return "NVPTXISD::CallSymbol";
655  case NVPTXISD::Prototype:
656  return "NVPTXISD::Prototype";
657  case NVPTXISD::MoveParam:
658  return "NVPTXISD::MoveParam";
660  return "NVPTXISD::StoreRetval";
662  return "NVPTXISD::StoreRetvalV2";
664  return "NVPTXISD::StoreRetvalV4";
666  return "NVPTXISD::PseudoUseParam";
667  case NVPTXISD::RETURN:
668  return "NVPTXISD::RETURN";
670  return "NVPTXISD::CallSeqBegin";
672  return "NVPTXISD::CallSeqEnd";
674  return "NVPTXISD::CallPrototype";
675  case NVPTXISD::LoadV2:
676  return "NVPTXISD::LoadV2";
677  case NVPTXISD::LoadV4:
678  return "NVPTXISD::LoadV4";
679  case NVPTXISD::LDGV2:
680  return "NVPTXISD::LDGV2";
681  case NVPTXISD::LDGV4:
682  return "NVPTXISD::LDGV4";
683  case NVPTXISD::LDUV2:
684  return "NVPTXISD::LDUV2";
685  case NVPTXISD::LDUV4:
686  return "NVPTXISD::LDUV4";
687  case NVPTXISD::StoreV2:
688  return "NVPTXISD::StoreV2";
689  case NVPTXISD::StoreV4:
690  return "NVPTXISD::StoreV4";
692  return "NVPTXISD::FUN_SHFL_CLAMP";
694  return "NVPTXISD::FUN_SHFR_CLAMP";
695  case NVPTXISD::IMAD:
696  return "NVPTXISD::IMAD";
698  return "NVPTXISD::SETP_F16X2";
699  case NVPTXISD::Dummy:
700  return "NVPTXISD::Dummy";
702  return "NVPTXISD::MUL_WIDE_SIGNED";
704  return "NVPTXISD::MUL_WIDE_UNSIGNED";
705  case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
706  case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
708  return "NVPTXISD::Tex1DFloatFloatLevel";
710  return "NVPTXISD::Tex1DFloatFloatGrad";
711  case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
712  case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
714  return "NVPTXISD::Tex1DS32FloatLevel";
716  return "NVPTXISD::Tex1DS32FloatGrad";
717  case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
718  case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
720  return "NVPTXISD::Tex1DU32FloatLevel";
722  return "NVPTXISD::Tex1DU32FloatGrad";
723  case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
724  case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
726  return "NVPTXISD::Tex1DArrayFloatFloatLevel";
728  return "NVPTXISD::Tex1DArrayFloatFloatGrad";
729  case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
730  case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
732  return "NVPTXISD::Tex1DArrayS32FloatLevel";
734  return "NVPTXISD::Tex1DArrayS32FloatGrad";
735  case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
736  case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
738  return "NVPTXISD::Tex1DArrayU32FloatLevel";
740  return "NVPTXISD::Tex1DArrayU32FloatGrad";
741  case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
742  case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
744  return "NVPTXISD::Tex2DFloatFloatLevel";
746  return "NVPTXISD::Tex2DFloatFloatGrad";
747  case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
748  case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
750  return "NVPTXISD::Tex2DS32FloatLevel";
752  return "NVPTXISD::Tex2DS32FloatGrad";
753  case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
754  case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
756  return "NVPTXISD::Tex2DU32FloatLevel";
758  return "NVPTXISD::Tex2DU32FloatGrad";
759  case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
760  case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
762  return "NVPTXISD::Tex2DArrayFloatFloatLevel";
764  return "NVPTXISD::Tex2DArrayFloatFloatGrad";
765  case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
766  case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
768  return "NVPTXISD::Tex2DArrayS32FloatLevel";
770  return "NVPTXISD::Tex2DArrayS32FloatGrad";
771  case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
772  case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
774  return "NVPTXISD::Tex2DArrayU32FloatLevel";
776  return "NVPTXISD::Tex2DArrayU32FloatGrad";
777  case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
778  case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
780  return "NVPTXISD::Tex3DFloatFloatLevel";
782  return "NVPTXISD::Tex3DFloatFloatGrad";
783  case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
784  case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
786  return "NVPTXISD::Tex3DS32FloatLevel";
788  return "NVPTXISD::Tex3DS32FloatGrad";
789  case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
790  case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
792  return "NVPTXISD::Tex3DU32FloatLevel";
794  return "NVPTXISD::Tex3DU32FloatGrad";
795  case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
797  return "NVPTXISD::TexCubeFloatFloatLevel";
798  case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
800  return "NVPTXISD::TexCubeS32FloatLevel";
801  case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
803  return "NVPTXISD::TexCubeU32FloatLevel";
805  return "NVPTXISD::TexCubeArrayFloatFloat";
807  return "NVPTXISD::TexCubeArrayFloatFloatLevel";
809  return "NVPTXISD::TexCubeArrayS32Float";
811  return "NVPTXISD::TexCubeArrayS32FloatLevel";
813  return "NVPTXISD::TexCubeArrayU32Float";
815  return "NVPTXISD::TexCubeArrayU32FloatLevel";
817  return "NVPTXISD::Tld4R2DFloatFloat";
819  return "NVPTXISD::Tld4G2DFloatFloat";
821  return "NVPTXISD::Tld4B2DFloatFloat";
823  return "NVPTXISD::Tld4A2DFloatFloat";
825  return "NVPTXISD::Tld4R2DS64Float";
827  return "NVPTXISD::Tld4G2DS64Float";
829  return "NVPTXISD::Tld4B2DS64Float";
831  return "NVPTXISD::Tld4A2DS64Float";
833  return "NVPTXISD::Tld4R2DU64Float";
835  return "NVPTXISD::Tld4G2DU64Float";
837  return "NVPTXISD::Tld4B2DU64Float";
839  return "NVPTXISD::Tld4A2DU64Float";
840 
842  return "NVPTXISD::TexUnified1DFloatS32";
844  return "NVPTXISD::TexUnified1DFloatFloat";
846  return "NVPTXISD::TexUnified1DFloatFloatLevel";
848  return "NVPTXISD::TexUnified1DFloatFloatGrad";
850  return "NVPTXISD::TexUnified1DS32S32";
852  return "NVPTXISD::TexUnified1DS32Float";
854  return "NVPTXISD::TexUnified1DS32FloatLevel";
856  return "NVPTXISD::TexUnified1DS32FloatGrad";
858  return "NVPTXISD::TexUnified1DU32S32";
860  return "NVPTXISD::TexUnified1DU32Float";
862  return "NVPTXISD::TexUnified1DU32FloatLevel";
864  return "NVPTXISD::TexUnified1DU32FloatGrad";
866  return "NVPTXISD::TexUnified1DArrayFloatS32";
868  return "NVPTXISD::TexUnified1DArrayFloatFloat";
870  return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
872  return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
874  return "NVPTXISD::TexUnified1DArrayS32S32";
876  return "NVPTXISD::TexUnified1DArrayS32Float";
878  return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
880  return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
882  return "NVPTXISD::TexUnified1DArrayU32S32";
884  return "NVPTXISD::TexUnified1DArrayU32Float";
886  return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
888  return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
890  return "NVPTXISD::TexUnified2DFloatS32";
892  return "NVPTXISD::TexUnified2DFloatFloat";
894  return "NVPTXISD::TexUnified2DFloatFloatLevel";
896  return "NVPTXISD::TexUnified2DFloatFloatGrad";
898  return "NVPTXISD::TexUnified2DS32S32";
900  return "NVPTXISD::TexUnified2DS32Float";
902  return "NVPTXISD::TexUnified2DS32FloatLevel";
904  return "NVPTXISD::TexUnified2DS32FloatGrad";
906  return "NVPTXISD::TexUnified2DU32S32";
908  return "NVPTXISD::TexUnified2DU32Float";
910  return "NVPTXISD::TexUnified2DU32FloatLevel";
912  return "NVPTXISD::TexUnified2DU32FloatGrad";
914  return "NVPTXISD::TexUnified2DArrayFloatS32";
916  return "NVPTXISD::TexUnified2DArrayFloatFloat";
918  return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
920  return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
922  return "NVPTXISD::TexUnified2DArrayS32S32";
924  return "NVPTXISD::TexUnified2DArrayS32Float";
926  return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
928  return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
930  return "NVPTXISD::TexUnified2DArrayU32S32";
932  return "NVPTXISD::TexUnified2DArrayU32Float";
934  return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
936  return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
938  return "NVPTXISD::TexUnified3DFloatS32";
940  return "NVPTXISD::TexUnified3DFloatFloat";
942  return "NVPTXISD::TexUnified3DFloatFloatLevel";
944  return "NVPTXISD::TexUnified3DFloatFloatGrad";
946  return "NVPTXISD::TexUnified3DS32S32";
948  return "NVPTXISD::TexUnified3DS32Float";
950  return "NVPTXISD::TexUnified3DS32FloatLevel";
952  return "NVPTXISD::TexUnified3DS32FloatGrad";
954  return "NVPTXISD::TexUnified3DU32S32";
956  return "NVPTXISD::TexUnified3DU32Float";
958  return "NVPTXISD::TexUnified3DU32FloatLevel";
960  return "NVPTXISD::TexUnified3DU32FloatGrad";
962  return "NVPTXISD::TexUnifiedCubeFloatFloat";
964  return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
966  return "NVPTXISD::TexUnifiedCubeS32Float";
968  return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
970  return "NVPTXISD::TexUnifiedCubeU32Float";
972  return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
974  return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
976  return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
978  return "NVPTXISD::TexUnifiedCubeArrayS32Float";
980  return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
982  return "NVPTXISD::TexUnifiedCubeArrayU32Float";
984  return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
986  return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
988  return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
990  return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
992  return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
994  return "NVPTXISD::Tld4UnifiedR2DS64Float";
996  return "NVPTXISD::Tld4UnifiedG2DS64Float";
998  return "NVPTXISD::Tld4UnifiedB2DS64Float";
1000  return "NVPTXISD::Tld4UnifiedA2DS64Float";
1002  return "NVPTXISD::Tld4UnifiedR2DU64Float";
1004  return "NVPTXISD::Tld4UnifiedG2DU64Float";
1006  return "NVPTXISD::Tld4UnifiedB2DU64Float";
1008  return "NVPTXISD::Tld4UnifiedA2DU64Float";
1009 
1010  case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
1011  case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
1012  case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
1013  case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
1014  case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
1015  case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
1016  case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
1017  case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
1018  case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
1019  case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
1020  case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
1021 
1022  case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
1023  case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
1024  case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
1025  case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
1026  case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
1027  case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
1028  case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
1029  case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
1030  case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
1031  case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
1032  case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
1033 
1034  case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
1035  case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
1036  case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
1037  case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
1038  case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
1039  case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
1040  case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
1041  case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
1042  case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
1043  case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
1044  case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
1045 
1046  case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
1047  case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
1048  case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
1049  case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
1050  case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
1051  case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
1052  case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
1053  case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
1054  case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
1055  case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
1056  case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
1057 
1058  case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
1059  case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
1060  case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
1061  case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
1062  case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
1063  case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
1064  case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
1065  case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
1066  case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
1067  case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
1068  case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
1069 
1070  case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
1071  case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
1072  case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
1073  case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
1074  case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
1075  case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
1076  case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
1077  case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
1078  case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
1079  case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
1080  case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
1081 
1082  case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
1083  case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
1084  case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
1085  case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
1086  case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
1087  case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
1088  case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
1089  case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
1090  case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
1091  case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
1092  case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
1093 
1094  case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
1095  case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
1096  case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
1097  case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
1098  case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
1099  case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
1100  case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
1101  case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
1102  case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
1103  case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
1104  case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
1105 
1106  case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
1107  case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
1108  case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
1109  case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
1110  case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
1111  case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
1112  case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
1113  case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
1114  case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
1115  case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
1116  case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
1117 
1118  case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
1119  case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
1120  case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
1121  case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
1122  case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
1123  case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
1124  case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
1125  case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
1126  case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
1127  case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
1128  case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
1129 
1130  case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
1131  case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
1132  case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
1133  case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
1134  case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
1135  case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
1136  case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
1137  case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
1138  case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
1139  case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
1140  case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
1141 
1142  case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
1143  case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
1144  case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
1145  case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
1146  case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
1147  case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
1148  case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
1149  case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
1150  case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
1151  case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
1152  case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
1153 
1154  case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
1155  case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
1156  case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
1157  case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
1158  case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
1159  case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
1160  case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
1161  case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
1162  case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
1163  case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
1164  case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
1165 
1166  case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
1167  case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
1168  case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
1169  case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
1170  case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
1171  case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
1172  case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
1173  case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
1174  case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
1175  case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
1176  case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
1177 
1178  case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
1179  case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
1180  case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
1181  case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
1182  case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
1183  case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
1184  case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
1185  case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
1186  case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
1187  case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
1188  case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
1189  }
1190  return nullptr;
1191 }
1192 
1195  if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
1196  return TypeSplitVector;
1197  if (VT == MVT::v2f16)
1198  return TypeLegal;
1200 }
1201 
1203  int Enabled, int &ExtraSteps,
1204  bool &UseOneConst,
1205  bool Reciprocal) const {
1206  if (!(Enabled == ReciprocalEstimate::Enabled ||
1207  (Enabled == ReciprocalEstimate::Unspecified && !usePrecSqrtF32())))
1208  return SDValue();
1209 
1210  if (ExtraSteps == ReciprocalEstimate::Unspecified)
1211  ExtraSteps = 0;
1212 
1213  SDLoc DL(Operand);
1214  EVT VT = Operand.getValueType();
1215  bool Ftz = useF32FTZ(DAG.getMachineFunction());
1216 
1217  auto MakeIntrinsicCall = [&](Intrinsic::ID IID) {
1218  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
1219  DAG.getConstant(IID, DL, MVT::i32), Operand);
1220  };
1221 
1222  // The sqrt and rsqrt refinement processes assume we always start out with an
1223  // approximation of the rsqrt. Therefore, if we're going to do any refinement
1224  // (i.e. ExtraSteps > 0), we must return an rsqrt. But if we're *not* doing
1225  // any refinement, we must return a regular sqrt.
1226  if (Reciprocal || ExtraSteps > 0) {
1227  if (VT == MVT::f32)
1228  return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_rsqrt_approx_ftz_f
1229  : Intrinsic::nvvm_rsqrt_approx_f);
1230  else if (VT == MVT::f64)
1231  return MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d);
1232  else
1233  return SDValue();
1234  } else {
1235  if (VT == MVT::f32)
1236  return MakeIntrinsicCall(Ftz ? Intrinsic::nvvm_sqrt_approx_ftz_f
1237  : Intrinsic::nvvm_sqrt_approx_f);
1238  else {
1239  // There's no sqrt.approx.f64 instruction, so we emit
1240  // reciprocal(rsqrt(x)). This is faster than
1241  // select(x == 0, 0, x * rsqrt(x)). (In fact, it's faster than plain
1242  // x * rsqrt(x).)
1243  return DAG.getNode(
1244  ISD::INTRINSIC_WO_CHAIN, DL, VT,
1245  DAG.getConstant(Intrinsic::nvvm_rcp_approx_ftz_d, DL, MVT::i32),
1246  MakeIntrinsicCall(Intrinsic::nvvm_rsqrt_approx_d));
1247  }
1248  }
1249 }
1250 
1251 SDValue
1253  SDLoc dl(Op);
1254  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1255  auto PtrVT = getPointerTy(DAG.getDataLayout());
1256  Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
1257  return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
1258 }
1259 
1261  const DataLayout &DL, Type *retTy, const ArgListTy &Args,
1262  const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
1263  ImmutableCallSite CS) const {
1264  auto PtrVT = getPointerTy(DL);
1265 
1266  bool isABI = (STI.getSmVersion() >= 20);
1267  assert(isABI && "Non-ABI compilation is not supported");
1268  if (!isABI)
1269  return "";
1270 
1271  std::stringstream O;
1272  O << "prototype_" << uniqueCallSite << " : .callprototype ";
1273 
1274  if (retTy->getTypeID() == Type::VoidTyID) {
1275  O << "()";
1276  } else {
1277  O << "(";
1278  if (retTy->isFloatingPointTy() || (retTy->isIntegerTy() && !retTy->isIntegerTy(128))) {
1279  unsigned size = 0;
1280  if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
1281  size = ITy->getBitWidth();
1282  } else {
1283  assert(retTy->isFloatingPointTy() &&
1284  "Floating point type expected here");
1285  size = retTy->getPrimitiveSizeInBits();
1286  }
1287  // PTX ABI requires all scalar return values to be at least 32
1288  // bits in size. fp16 normally uses .b16 as its storage type in
1289  // PTX, so its size must be adjusted here, too.
1290  if (size < 32)
1291  size = 32;
1292 
1293  O << ".param .b" << size << " _";
1294  } else if (isa<PointerType>(retTy)) {
1295  O << ".param .b" << PtrVT.getSizeInBits() << " _";
1296  } else if (retTy->isAggregateType() || retTy->isVectorTy() || retTy->isIntegerTy(128)) {
1297  auto &DL = CS.getCalledFunction()->getParent()->getDataLayout();
1298  O << ".param .align " << retAlignment << " .b8 _["
1299  << DL.getTypeAllocSize(retTy) << "]";
1300  } else {
1301  llvm_unreachable("Unknown return type");
1302  }
1303  O << ") ";
1304  }
1305  O << "_ (";
1306 
1307  bool first = true;
1308 
1309  unsigned OIdx = 0;
1310  for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1311  Type *Ty = Args[i].Ty;
1312  if (!first) {
1313  O << ", ";
1314  }
1315  first = false;
1316 
1317  if (!Outs[OIdx].Flags.isByVal()) {
1318  if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1319  unsigned align = 0;
1320  const CallInst *CallI = cast<CallInst>(CS.getInstruction());
1321  // +1 because index 0 is reserved for return type alignment
1322  if (!getAlign(*CallI, i + 1, align))
1323  align = DL.getABITypeAlignment(Ty);
1324  unsigned sz = DL.getTypeAllocSize(Ty);
1325  O << ".param .align " << align << " .b8 ";
1326  O << "_";
1327  O << "[" << sz << "]";
1328  // update the index for Outs
1329  SmallVector<EVT, 16> vtparts;
1330  ComputeValueVTs(*this, DL, Ty, vtparts);
1331  if (unsigned len = vtparts.size())
1332  OIdx += len - 1;
1333  continue;
1334  }
1335  // i8 types in IR will be i16 types in SDAG
1336  assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
1337  (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1338  "type mismatch between callee prototype and arguments");
1339  // scalar type
1340  unsigned sz = 0;
1341  if (isa<IntegerType>(Ty)) {
1342  sz = cast<IntegerType>(Ty)->getBitWidth();
1343  if (sz < 32)
1344  sz = 32;
1345  } else if (isa<PointerType>(Ty)) {
1346  sz = PtrVT.getSizeInBits();
1347  } else if (Ty->isHalfTy())
1348  // PTX ABI requires all scalar parameters to be at least 32
1349  // bits in size. fp16 normally uses .b16 as its storage type
1350  // in PTX, so its size must be adjusted here, too.
1351  sz = 32;
1352  else
1353  sz = Ty->getPrimitiveSizeInBits();
1354  O << ".param .b" << sz << " ";
1355  O << "_";
1356  continue;
1357  }
1358  auto *PTy = dyn_cast<PointerType>(Ty);
1359  assert(PTy && "Param with byval attribute should be a pointer type");
1360  Type *ETy = PTy->getElementType();
1361 
1362  unsigned align = Outs[OIdx].Flags.getByValAlign();
1363  unsigned sz = DL.getTypeAllocSize(ETy);
1364  O << ".param .align " << align << " .b8 ";
1365  O << "_";
1366  O << "[" << sz << "]";
1367  }
1368  O << ");";
1369  return O.str();
1370 }
1371 
1372 unsigned NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1373  ImmutableCallSite CS,
1374  Type *Ty, unsigned Idx,
1375  const DataLayout &DL) const {
1376  if (!CS) {
1377  // CallSite is zero, fallback to ABI type alignment
1378  return DL.getABITypeAlignment(Ty);
1379  }
1380 
1381  unsigned Align = 0;
1382  const Value *DirectCallee = CS.getCalledFunction();
1383 
1384  if (!DirectCallee) {
1385  // We don't have a direct function symbol, but that may be because of
1386  // constant cast instructions in the call.
1387  const Instruction *CalleeI = CS.getInstruction();
1388  assert(CalleeI && "Call target is not a function or derived value?");
1389 
1390  // With bitcast'd call targets, the instruction will be the call
1391  if (isa<CallInst>(CalleeI)) {
1392  // Check if we have call alignment metadata
1393  if (getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1394  return Align;
1395 
1396  const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1397  // Ignore any bitcast instructions
1398  while (isa<ConstantExpr>(CalleeV)) {
1399  const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1400  if (!CE->isCast())
1401  break;
1402  // Look through the bitcast
1403  CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1404  }
1405 
1406  // We have now looked past all of the bitcasts. Do we finally have a
1407  // Function?
1408  if (isa<Function>(CalleeV))
1409  DirectCallee = CalleeV;
1410  }
1411  }
1412 
1413  // Check for function alignment information if we found that the
1414  // ultimate target is a Function
1415  if (DirectCallee)
1416  if (getAlign(*cast<Function>(DirectCallee), Idx, Align))
1417  return Align;
1418 
1419  // Call is indirect or alignment information is not available, fall back to
1420  // the ABI type alignment
1421  return DL.getABITypeAlignment(Ty);
1422 }
1423 
1425  SmallVectorImpl<SDValue> &InVals) const {
1426  SelectionDAG &DAG = CLI.DAG;
1427  SDLoc dl = CLI.DL;
1429  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1431  SDValue Chain = CLI.Chain;
1432  SDValue Callee = CLI.Callee;
1433  bool &isTailCall = CLI.IsTailCall;
1434  ArgListTy &Args = CLI.getArgs();
1435  Type *RetTy = CLI.RetTy;
1436  ImmutableCallSite CS = CLI.CS;
1437  const DataLayout &DL = DAG.getDataLayout();
1438 
1439  bool isABI = (STI.getSmVersion() >= 20);
1440  assert(isABI && "Non-ABI compilation is not supported");
1441  if (!isABI)
1442  return Chain;
1443 
1444  SDValue tempChain = Chain;
1445  Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
1446  SDValue InFlag = Chain.getValue(1);
1447 
1448  unsigned paramCount = 0;
1449  // Args.size() and Outs.size() need not match.
1450  // Outs.size() will be larger
1451  // * if there is an aggregate argument with multiple fields (each field
1452  // showing up separately in Outs)
1453  // * if there is a vector argument with more than typical vector-length
1454  // elements (generally if more than 4) where each vector element is
1455  // individually present in Outs.
1456  // So a different index should be used for indexing into Outs/OutVals.
1457  // See similar issue in LowerFormalArguments.
1458  unsigned OIdx = 0;
1459  // Declare the .params or .reg need to pass values
1460  // to the function
1461  for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1462  EVT VT = Outs[OIdx].VT;
1463  Type *Ty = Args[i].Ty;
1464 
1465  if (!Outs[OIdx].Flags.isByVal()) {
1468  ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets);
1469  unsigned ArgAlign =
1470  getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1471  unsigned AllocSize = DL.getTypeAllocSize(Ty);
1472  SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1473  bool NeedAlign; // Does argument declaration specify alignment?
1474  if (Ty->isAggregateType() || Ty->isVectorTy() || Ty->isIntegerTy(128)) {
1475  // declare .param .align <align> .b8 .param<n>[<size>];
1476  SDValue DeclareParamOps[] = {
1477  Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1478  DAG.getConstant(paramCount, dl, MVT::i32),
1479  DAG.getConstant(AllocSize, dl, MVT::i32), InFlag};
1480  Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1481  DeclareParamOps);
1482  NeedAlign = true;
1483  } else {
1484  // declare .param .b<size> .param<n>;
1485  if ((VT.isInteger() || VT.isFloatingPoint()) && AllocSize < 4) {
1486  // PTX ABI requires integral types to be at least 32 bits in
1487  // size. FP16 is loaded/stored using i16, so it's handled
1488  // here as well.
1489  AllocSize = 4;
1490  }
1491  SDValue DeclareScalarParamOps[] = {
1492  Chain, DAG.getConstant(paramCount, dl, MVT::i32),
1493  DAG.getConstant(AllocSize * 8, dl, MVT::i32),
1494  DAG.getConstant(0, dl, MVT::i32), InFlag};
1495  Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1496  DeclareScalarParamOps);
1497  NeedAlign = false;
1498  }
1499  InFlag = Chain.getValue(1);
1500 
1501  // PTX Interoperability Guide 3.3(A): [Integer] Values shorter
1502  // than 32-bits are sign extended or zero extended, depending on
1503  // whether they are signed or unsigned types. This case applies
1504  // only to scalar parameters and not to aggregate values.
1505  bool ExtendIntegerParam =
1506  Ty->isIntegerTy() && DL.getTypeAllocSizeInBits(Ty) < 32;
1507 
1508  auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, ArgAlign);
1509  SmallVector<SDValue, 6> StoreOperands;
1510  for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1511  // New store.
1512  if (VectorInfo[j] & PVF_FIRST) {
1513  assert(StoreOperands.empty() && "Unfinished preceeding store.");
1514  StoreOperands.push_back(Chain);
1515  StoreOperands.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1516  StoreOperands.push_back(DAG.getConstant(Offsets[j], dl, MVT::i32));
1517  }
1518 
1519  EVT EltVT = VTs[j];
1520  SDValue StVal = OutVals[OIdx];
1521  if (ExtendIntegerParam) {
1522  assert(VTs.size() == 1 && "Scalar can't have multiple parts.");
1523  // zext/sext to i32
1524  StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
1525  : ISD::ZERO_EXTEND,
1526  dl, MVT::i32, StVal);
1527  } else if (EltVT.getSizeInBits() < 16) {
1528  // Use 16-bit registers for small stores as it's the
1529  // smallest general purpose register size supported by NVPTX.
1530  StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1531  }
1532 
1533  // Record the value to store.
1534  StoreOperands.push_back(StVal);
1535 
1536  if (VectorInfo[j] & PVF_LAST) {
1537  unsigned NumElts = StoreOperands.size() - 3;
1539  switch (NumElts) {
1540  case 1:
1541  Op = NVPTXISD::StoreParam;
1542  break;
1543  case 2:
1545  break;
1546  case 4:
1548  break;
1549  default:
1550  llvm_unreachable("Invalid vector info.");
1551  }
1552 
1553  StoreOperands.push_back(InFlag);
1554 
1555  // Adjust type of the store op if we've extended the scalar
1556  // return value.
1557  EVT TheStoreType = ExtendIntegerParam ? MVT::i32 : VTs[j];
1558  unsigned EltAlign =
1559  NeedAlign ? GreatestCommonDivisor64(ArgAlign, Offsets[j]) : 0;
1560 
1561  Chain = DAG.getMemIntrinsicNode(
1562  Op, dl, DAG.getVTList(MVT::Other, MVT::Glue), StoreOperands,
1563  TheStoreType, MachinePointerInfo(), EltAlign,
1564  /* Volatile */ false, /* ReadMem */ false,
1565  /* WriteMem */ true, /* Size */ 0);
1566  InFlag = Chain.getValue(1);
1567 
1568  // Cleanup.
1569  StoreOperands.clear();
1570  }
1571  ++OIdx;
1572  }
1573  assert(StoreOperands.empty() && "Unfinished parameter store.");
1574  if (VTs.size() > 0)
1575  --OIdx;
1576  ++paramCount;
1577  continue;
1578  }
1579 
1580  // ByVal arguments
1583  auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1584  assert(PTy && "Type of a byval parameter should be pointer");
1585  ComputePTXValueVTs(*this, DL, PTy->getElementType(), VTs, &Offsets, 0);
1586 
1587  // declare .param .align <align> .b8 .param<n>[<size>];
1588  unsigned sz = Outs[OIdx].Flags.getByValSize();
1589  SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1590  unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1591  // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1592  // so we don't need to worry about natural alignment or not.
1593  // See TargetLowering::LowerCallTo().
1594 
1595  // Enforce minumum alignment of 4 to work around ptxas miscompile
1596  // for sm_50+. See corresponding alignment adjustment in
1597  // emitFunctionParamList() for details.
1598  if (ArgAlign < 4)
1599  ArgAlign = 4;
1600  SDValue DeclareParamOps[] = {Chain, DAG.getConstant(ArgAlign, dl, MVT::i32),
1601  DAG.getConstant(paramCount, dl, MVT::i32),
1602  DAG.getConstant(sz, dl, MVT::i32), InFlag};
1603  Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1604  DeclareParamOps);
1605  InFlag = Chain.getValue(1);
1606  for (unsigned j = 0, je = VTs.size(); j != je; ++j) {
1607  EVT elemtype = VTs[j];
1608  int curOffset = Offsets[j];
1609  unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1610  auto PtrVT = getPointerTy(DL);
1611  SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1612  DAG.getConstant(curOffset, dl, PtrVT));
1613  SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1614  MachinePointerInfo(), PartAlign);
1615  if (elemtype.getSizeInBits() < 16) {
1616  theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1617  }
1618  SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1619  SDValue CopyParamOps[] = { Chain,
1620  DAG.getConstant(paramCount, dl, MVT::i32),
1621  DAG.getConstant(curOffset, dl, MVT::i32),
1622  theVal, InFlag };
1623  Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1624  CopyParamOps, elemtype,
1625  MachinePointerInfo(), /* Align */ 0,
1626  /* Volatile */ false, /* ReadMem */ false,
1627  /* WriteMem */ true, /* Size */ 0);
1628 
1629  InFlag = Chain.getValue(1);
1630  }
1631  ++paramCount;
1632  }
1633 
1635  unsigned retAlignment = 0;
1636 
1637  // Handle Result
1638  if (Ins.size() > 0) {
1639  SmallVector<EVT, 16> resvtparts;
1640  ComputeValueVTs(*this, DL, RetTy, resvtparts);
1641 
1642  // Declare
1643  // .param .align 16 .b8 retval0[<size-in-bytes>], or
1644  // .param .b<size-in-bits> retval0
1645  unsigned resultsz = DL.getTypeAllocSizeInBits(RetTy);
1646  // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1647  // these three types to match the logic in
1648  // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1649  // Plus, this behavior is consistent with nvcc's.
1650  if (RetTy->isFloatingPointTy() || RetTy->isPointerTy() ||
1651  (RetTy->isIntegerTy() && !RetTy->isIntegerTy(128))) {
1652  // Scalar needs to be at least 32bit wide
1653  if (resultsz < 32)
1654  resultsz = 32;
1655  SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1656  SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1657  DAG.getConstant(resultsz, dl, MVT::i32),
1658  DAG.getConstant(0, dl, MVT::i32), InFlag };
1659  Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1660  DeclareRetOps);
1661  InFlag = Chain.getValue(1);
1662  } else {
1663  retAlignment = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1664  SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1665  SDValue DeclareRetOps[] = { Chain,
1666  DAG.getConstant(retAlignment, dl, MVT::i32),
1667  DAG.getConstant(resultsz / 8, dl, MVT::i32),
1668  DAG.getConstant(0, dl, MVT::i32), InFlag };
1669  Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1670  DeclareRetOps);
1671  InFlag = Chain.getValue(1);
1672  }
1673  }
1674 
1675  if (!Func) {
1676  // This is indirect function call case : PTX requires a prototype of the
1677  // form
1678  // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1679  // to be emitted, and the label has to used as the last arg of call
1680  // instruction.
1681  // The prototype is embedded in a string and put as the operand for a
1682  // CallPrototype SDNode which will print out to the value of the string.
1683  SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1684  std::string Proto = getPrototype(DL, RetTy, Args, Outs, retAlignment, CS);
1685  const char *ProtoStr =
1686  nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1687  SDValue ProtoOps[] = {
1688  Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1689  };
1690  Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1691  InFlag = Chain.getValue(1);
1692  }
1693  // Op to just print "call"
1694  SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1695  SDValue PrintCallOps[] = {
1696  Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1697  };
1698  // We model convergent calls as separate opcodes.
1699  unsigned Opcode = Func ? NVPTXISD::PrintCallUni : NVPTXISD::PrintCall;
1700  if (CLI.IsConvergent)
1703  Chain = DAG.getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
1704  InFlag = Chain.getValue(1);
1705 
1706  // Ops to print out the function name
1707  SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1708  SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1709  Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1710  InFlag = Chain.getValue(1);
1711 
1712  // Ops to print out the param list
1713  SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1714  SDValue CallArgBeginOps[] = { Chain, InFlag };
1715  Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1716  CallArgBeginOps);
1717  InFlag = Chain.getValue(1);
1718 
1719  for (unsigned i = 0, e = paramCount; i != e; ++i) {
1720  unsigned opcode;
1721  if (i == (e - 1))
1722  opcode = NVPTXISD::LastCallArg;
1723  else
1724  opcode = NVPTXISD::CallArg;
1725  SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1726  SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1727  DAG.getConstant(i, dl, MVT::i32), InFlag };
1728  Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1729  InFlag = Chain.getValue(1);
1730  }
1731  SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1732  SDValue CallArgEndOps[] = { Chain,
1733  DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1734  InFlag };
1735  Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1736  InFlag = Chain.getValue(1);
1737 
1738  if (!Func) {
1739  SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1740  SDValue PrototypeOps[] = { Chain,
1742  InFlag };
1743  Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1744  InFlag = Chain.getValue(1);
1745  }
1746 
1747  // Generate loads from param memory/moves from registers for result
1748  if (Ins.size() > 0) {
1751  ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0);
1752  assert(VTs.size() == Ins.size() && "Bad value decomposition");
1753 
1754  unsigned RetAlign = getArgumentAlignment(Callee, CS, RetTy, 0, DL);
1755  auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign);
1756 
1757  SmallVector<EVT, 6> LoadVTs;
1758  int VecIdx = -1; // Index of the first element of the vector.
1759 
1760  // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
1761  // 32-bits are sign extended or zero extended, depending on whether
1762  // they are signed or unsigned types.
1763  bool ExtendIntegerRetVal =
1764  RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
1765 
1766  for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
1767  bool needTruncate = false;
1768  EVT TheLoadType = VTs[i];
1769  EVT EltType = Ins[i].VT;
1770  unsigned EltAlign = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1771  if (ExtendIntegerRetVal) {
1772  TheLoadType = MVT::i32;
1773  EltType = MVT::i32;
1774  needTruncate = true;
1775  } else if (TheLoadType.getSizeInBits() < 16) {
1776  if (VTs[i].isInteger())
1777  needTruncate = true;
1778  EltType = MVT::i16;
1779  }
1780 
1781  // Record index of the very first element of the vector.
1782  if (VectorInfo[i] & PVF_FIRST) {
1783  assert(VecIdx == -1 && LoadVTs.empty() && "Orphaned operand list.");
1784  VecIdx = i;
1785  }
1786 
1787  LoadVTs.push_back(EltType);
1788 
1789  if (VectorInfo[i] & PVF_LAST) {
1790  unsigned NumElts = LoadVTs.size();
1791  LoadVTs.push_back(MVT::Other);
1792  LoadVTs.push_back(MVT::Glue);
1794  switch (NumElts) {
1795  case 1:
1796  Op = NVPTXISD::LoadParam;
1797  break;
1798  case 2:
1799  Op = NVPTXISD::LoadParamV2;
1800  break;
1801  case 4:
1802  Op = NVPTXISD::LoadParamV4;
1803  break;
1804  default:
1805  llvm_unreachable("Invalid vector info.");
1806  }
1807 
1808  SDValue LoadOperands[] = {
1809  Chain, DAG.getConstant(1, dl, MVT::i32),
1810  DAG.getConstant(Offsets[VecIdx], dl, MVT::i32), InFlag};
1811  SDValue RetVal = DAG.getMemIntrinsicNode(
1812  Op, dl, DAG.getVTList(LoadVTs), LoadOperands, TheLoadType,
1813  MachinePointerInfo(), EltAlign, /* Volatile */ false,
1814  /* ReadMem */ true, /* WriteMem */ false, /* Size */ 0);
1815 
1816  for (unsigned j = 0; j < NumElts; ++j) {
1817  SDValue Ret = RetVal.getValue(j);
1818  if (needTruncate)
1819  Ret = DAG.getNode(ISD::TRUNCATE, dl, Ins[VecIdx + j].VT, Ret);
1820  InVals.push_back(Ret);
1821  }
1822  Chain = RetVal.getValue(NumElts);
1823  InFlag = RetVal.getValue(NumElts + 1);
1824 
1825  // Cleanup
1826  VecIdx = -1;
1827  LoadVTs.clear();
1828  }
1829  }
1830  }
1831 
1832  Chain = DAG.getCALLSEQ_END(Chain,
1833  DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1834  DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1835  true),
1836  InFlag, dl);
1837  uniqueCallSite++;
1838 
1839  // set isTailCall to false for now, until we figure out how to express
1840  // tail call optimization in PTX
1841  isTailCall = false;
1842  return Chain;
1843 }
1844 
1845 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1846 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1847 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1848 SDValue
1849 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1850  SDNode *Node = Op.getNode();
1851  SDLoc dl(Node);
1853  unsigned NumOperands = Node->getNumOperands();
1854  for (unsigned i = 0; i < NumOperands; ++i) {
1855  SDValue SubOp = Node->getOperand(i);
1856  EVT VVT = SubOp.getNode()->getValueType(0);
1857  EVT EltVT = VVT.getVectorElementType();
1858  unsigned NumSubElem = VVT.getVectorNumElements();
1859  for (unsigned j = 0; j < NumSubElem; ++j) {
1860  Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1861  DAG.getIntPtrConstant(j, dl)));
1862  }
1863  }
1864  return DAG.getBuildVector(Node->getValueType(0), dl, Ops);
1865 }
1866 
1867 // We can init constant f16x2 with a single .b32 move. Normally it
1868 // would get lowered as two constant loads and vector-packing move.
1869 // mov.b16 %h1, 0x4000;
1870 // mov.b16 %h2, 0x3C00;
1871 // mov.b32 %hh2, {%h2, %h1};
1872 // Instead we want just a constant move:
1873 // mov.b32 %hh2, 0x40003C00
1874 //
1875 // This results in better SASS code with CUDA 7.x. Ptxas in CUDA 8.0
1876 // generates good SASS in both cases.
1877 SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
1878  SelectionDAG &DAG) const {
1879  //return Op;
1880  if (!(Op->getValueType(0) == MVT::v2f16 &&
1881  isa<ConstantFPSDNode>(Op->getOperand(0)) &&
1882  isa<ConstantFPSDNode>(Op->getOperand(1))))
1883  return Op;
1884 
1885  APInt E0 =
1886  cast<ConstantFPSDNode>(Op->getOperand(0))->getValueAPF().bitcastToAPInt();
1887  APInt E1 =
1888  cast<ConstantFPSDNode>(Op->getOperand(1))->getValueAPF().bitcastToAPInt();
1889  SDValue Const =
1890  DAG.getConstant(E1.zext(32).shl(16) | E0.zext(32), SDLoc(Op), MVT::i32);
1891  return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::v2f16, Const);
1892 }
1893 
1894 SDValue NVPTXTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
1895  SelectionDAG &DAG) const {
1896  SDValue Index = Op->getOperand(1);
1897  // Constant index will be matched by tablegen.
1898  if (isa<ConstantSDNode>(Index.getNode()))
1899  return Op;
1900 
1901  // Extract individual elements and select one of them.
1902  SDValue Vector = Op->getOperand(0);
1903  EVT VectorVT = Vector.getValueType();
1904  assert(VectorVT == MVT::v2f16 && "Unexpected vector type.");
1905  EVT EltVT = VectorVT.getVectorElementType();
1906 
1907  SDLoc dl(Op.getNode());
1908  SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1909  DAG.getIntPtrConstant(0, dl));
1910  SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1911  DAG.getIntPtrConstant(1, dl));
1912  return DAG.getSelectCC(dl, Index, DAG.getIntPtrConstant(0, dl), E0, E1,
1914 }
1915 
1916 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1917 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1918 /// amount, or
1919 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1920 /// amount.
1921 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1922  SelectionDAG &DAG) const {
1923  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1925 
1926  EVT VT = Op.getValueType();
1927  unsigned VTBits = VT.getSizeInBits();
1928  SDLoc dl(Op);
1929  SDValue ShOpLo = Op.getOperand(0);
1930  SDValue ShOpHi = Op.getOperand(1);
1931  SDValue ShAmt = Op.getOperand(2);
1932  unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1933 
1934  if (VTBits == 32 && STI.getSmVersion() >= 35) {
1935  // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1936  // {dHi, dLo} = {aHi, aLo} >> Amt
1937  // dHi = aHi >> Amt
1938  // dLo = shf.r.clamp aLo, aHi, Amt
1939 
1940  SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1941  SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1942  ShAmt);
1943 
1944  SDValue Ops[2] = { Lo, Hi };
1945  return DAG.getMergeValues(Ops, dl);
1946  }
1947  else {
1948  // {dHi, dLo} = {aHi, aLo} >> Amt
1949  // - if (Amt>=size) then
1950  // dLo = aHi >> (Amt-size)
1951  // dHi = aHi >> Amt (this is either all 0 or all 1)
1952  // else
1953  // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1954  // dHi = aHi >> Amt
1955 
1956  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1957  DAG.getConstant(VTBits, dl, MVT::i32),
1958  ShAmt);
1959  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1960  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1961  DAG.getConstant(VTBits, dl, MVT::i32));
1962  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1963  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1964  SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1965 
1966  SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1967  DAG.getConstant(VTBits, dl, MVT::i32),
1968  ISD::SETGE);
1969  SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1970  SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1971 
1972  SDValue Ops[2] = { Lo, Hi };
1973  return DAG.getMergeValues(Ops, dl);
1974  }
1975 }
1976 
1977 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1978 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1979 /// amount, or
1980 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1981 /// amount.
1982 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1983  SelectionDAG &DAG) const {
1984  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1985  assert(Op.getOpcode() == ISD::SHL_PARTS);
1986 
1987  EVT VT = Op.getValueType();
1988  unsigned VTBits = VT.getSizeInBits();
1989  SDLoc dl(Op);
1990  SDValue ShOpLo = Op.getOperand(0);
1991  SDValue ShOpHi = Op.getOperand(1);
1992  SDValue ShAmt = Op.getOperand(2);
1993 
1994  if (VTBits == 32 && STI.getSmVersion() >= 35) {
1995  // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1996  // {dHi, dLo} = {aHi, aLo} << Amt
1997  // dHi = shf.l.clamp aLo, aHi, Amt
1998  // dLo = aLo << Amt
1999 
2000  SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
2001  ShAmt);
2002  SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2003 
2004  SDValue Ops[2] = { Lo, Hi };
2005  return DAG.getMergeValues(Ops, dl);
2006  }
2007  else {
2008  // {dHi, dLo} = {aHi, aLo} << Amt
2009  // - if (Amt>=size) then
2010  // dLo = aLo << Amt (all 0)
2011  // dLo = aLo << (Amt-size)
2012  // else
2013  // dLo = aLo << Amt
2014  // dHi = (aHi << Amt) | (aLo >> (size-Amt))
2015 
2016  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2017  DAG.getConstant(VTBits, dl, MVT::i32),
2018  ShAmt);
2019  SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2020  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2021  DAG.getConstant(VTBits, dl, MVT::i32));
2022  SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2023  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2024  SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2025 
2026  SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
2027  DAG.getConstant(VTBits, dl, MVT::i32),
2028  ISD::SETGE);
2029  SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2030  SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2031 
2032  SDValue Ops[2] = { Lo, Hi };
2033  return DAG.getMergeValues(Ops, dl);
2034  }
2035 }
2036 
2037 SDValue
2039  switch (Op.getOpcode()) {
2040  case ISD::RETURNADDR:
2041  return SDValue();
2042  case ISD::FRAMEADDR:
2043  return SDValue();
2044  case ISD::GlobalAddress:
2045  return LowerGlobalAddress(Op, DAG);
2047  return Op;
2048  case ISD::BUILD_VECTOR:
2049  return LowerBUILD_VECTOR(Op, DAG);
2051  return Op;
2053  return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2054  case ISD::CONCAT_VECTORS:
2055  return LowerCONCAT_VECTORS(Op, DAG);
2056  case ISD::STORE:
2057  return LowerSTORE(Op, DAG);
2058  case ISD::LOAD:
2059  return LowerLOAD(Op, DAG);
2060  case ISD::SHL_PARTS:
2061  return LowerShiftLeftParts(Op, DAG);
2062  case ISD::SRA_PARTS:
2063  case ISD::SRL_PARTS:
2064  return LowerShiftRightParts(Op, DAG);
2065  case ISD::SELECT:
2066  return LowerSelect(Op, DAG);
2067  default:
2068  llvm_unreachable("Custom lowering not defined for operation");
2069  }
2070 }
2071 
2072 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
2073  SDValue Op0 = Op->getOperand(0);
2074  SDValue Op1 = Op->getOperand(1);
2075  SDValue Op2 = Op->getOperand(2);
2076  SDLoc DL(Op.getNode());
2077 
2078  assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
2079 
2080  Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
2081  Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
2082  SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
2083  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
2084 
2085  return Trunc;
2086 }
2087 
2088 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2089  if (Op.getValueType() == MVT::i1)
2090  return LowerLOADi1(Op, DAG);
2091 
2092  // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2093  // loads and have to handle it here.
2094  if (Op.getValueType() == MVT::v2f16) {
2095  LoadSDNode *Load = cast<LoadSDNode>(Op);
2096  EVT MemVT = Load->getMemoryVT();
2097  if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
2098  Load->getAddressSpace(), Load->getAlignment())) {
2099  SDValue Ops[2];
2100  std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
2101  return DAG.getMergeValues(Ops, SDLoc(Op));
2102  }
2103  }
2104 
2105  return SDValue();
2106 }
2107 
2108 // v = ld i1* addr
2109 // =>
2110 // v1 = ld i8* addr (-> i16)
2111 // v = trunc i16 to i1
2112 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
2113  SDNode *Node = Op.getNode();
2114  LoadSDNode *LD = cast<LoadSDNode>(Node);
2115  SDLoc dl(Node);
2117  assert(Node->getValueType(0) == MVT::i1 &&
2118  "Custom lowering for i1 load only");
2119  SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
2120  LD->getPointerInfo(), LD->getAlignment(),
2121  LD->getMemOperand()->getFlags());
2122  SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
2123  // The legalizer (the caller) is expecting two values from the legalized
2124  // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
2125  // in LegalizeDAG.cpp which also uses MergeValues.
2126  SDValue Ops[] = { result, LD->getChain() };
2127  return DAG.getMergeValues(Ops, dl);
2128 }
2129 
2130 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2131  StoreSDNode *Store = cast<StoreSDNode>(Op);
2132  EVT VT = Store->getMemoryVT();
2133 
2134  if (VT == MVT::i1)
2135  return LowerSTOREi1(Op, DAG);
2136 
2137  // v2f16 is legal, so we can't rely on legalizer to handle unaligned
2138  // stores and have to handle it here.
2139  if (VT == MVT::v2f16 &&
2140  !allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
2141  Store->getAddressSpace(), Store->getAlignment()))
2142  return expandUnalignedStore(Store, DAG);
2143 
2144  if (VT.isVector())
2145  return LowerSTOREVector(Op, DAG);
2146 
2147  return SDValue();
2148 }
2149 
2150 SDValue
2151 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
2152  SDNode *N = Op.getNode();
2153  SDValue Val = N->getOperand(1);
2154  SDLoc DL(N);
2155  EVT ValVT = Val.getValueType();
2156 
2157  if (ValVT.isVector()) {
2158  // We only handle "native" vector sizes for now, e.g. <4 x double> is not
2159  // legal. We can (and should) split that into 2 stores of <2 x double> here
2160  // but I'm leaving that as a TODO for now.
2161  if (!ValVT.isSimple())
2162  return SDValue();
2163  switch (ValVT.getSimpleVT().SimpleTy) {
2164  default:
2165  return SDValue();
2166  case MVT::v2i8:
2167  case MVT::v2i16:
2168  case MVT::v2i32:
2169  case MVT::v2i64:
2170  case MVT::v2f16:
2171  case MVT::v2f32:
2172  case MVT::v2f64:
2173  case MVT::v4i8:
2174  case MVT::v4i16:
2175  case MVT::v4i32:
2176  case MVT::v4f16:
2177  case MVT::v4f32:
2178  case MVT::v8f16: // <4 x f16x2>
2179  // This is a "native" vector type
2180  break;
2181  }
2182 
2183  MemSDNode *MemSD = cast<MemSDNode>(N);
2184  const DataLayout &TD = DAG.getDataLayout();
2185 
2186  unsigned Align = MemSD->getAlignment();
2187  unsigned PrefAlign =
2188  TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
2189  if (Align < PrefAlign) {
2190  // This store is not sufficiently aligned, so bail out and let this vector
2191  // store be scalarized. Note that we may still be able to emit smaller
2192  // vector stores. For example, if we are storing a <4 x float> with an
2193  // alignment of 8, this check will fail but the legalizer will try again
2194  // with 2 x <2 x float>, which will succeed with an alignment of 8.
2195  return SDValue();
2196  }
2197 
2198  unsigned Opcode = 0;
2199  EVT EltVT = ValVT.getVectorElementType();
2200  unsigned NumElts = ValVT.getVectorNumElements();
2201 
2202  // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
2203  // Therefore, we must ensure the type is legal. For i1 and i8, we set the
2204  // stored type to i16 and propagate the "real" type as the memory type.
2205  bool NeedExt = false;
2206  if (EltVT.getSizeInBits() < 16)
2207  NeedExt = true;
2208 
2209  bool StoreF16x2 = false;
2210  switch (NumElts) {
2211  default:
2212  return SDValue();
2213  case 2:
2214  Opcode = NVPTXISD::StoreV2;
2215  break;
2216  case 4:
2217  Opcode = NVPTXISD::StoreV4;
2218  break;
2219  case 8:
2220  // v8f16 is a special case. PTX doesn't have st.v8.f16
2221  // instruction. Instead, we split the vector into v2f16 chunks and
2222  // store them with st.v4.b32.
2223  assert(EltVT == MVT::f16 && "Wrong type for the vector.");
2224  Opcode = NVPTXISD::StoreV4;
2225  StoreF16x2 = true;
2226  break;
2227  }
2228 
2230 
2231  // First is the chain
2232  Ops.push_back(N->getOperand(0));
2233 
2234  if (StoreF16x2) {
2235  // Combine f16,f16 -> v2f16
2236  NumElts /= 2;
2237  for (unsigned i = 0; i < NumElts; ++i) {
2238  SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2239  DAG.getIntPtrConstant(i * 2, DL));
2240  SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2241  DAG.getIntPtrConstant(i * 2 + 1, DL));
2242  SDValue V2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f16, E0, E1);
2243  Ops.push_back(V2);
2244  }
2245  } else {
2246  // Then the split values
2247  for (unsigned i = 0; i < NumElts; ++i) {
2248  SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
2249  DAG.getIntPtrConstant(i, DL));
2250  if (NeedExt)
2251  ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2252  Ops.push_back(ExtVal);
2253  }
2254  }
2255 
2256  // Then any remaining arguments
2257  Ops.append(N->op_begin() + 2, N->op_end());
2258 
2259  SDValue NewSt =
2260  DAG.getMemIntrinsicNode(Opcode, DL, DAG.getVTList(MVT::Other), Ops,
2261  MemSD->getMemoryVT(), MemSD->getMemOperand());
2262 
2263  // return DCI.CombineTo(N, NewSt, true);
2264  return NewSt;
2265  }
2266 
2267  return SDValue();
2268 }
2269 
2270 // st i1 v, addr
2271 // =>
2272 // v1 = zxt v to i16
2273 // st.u8 i16, addr
2274 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2275  SDNode *Node = Op.getNode();
2276  SDLoc dl(Node);
2277  StoreSDNode *ST = cast<StoreSDNode>(Node);
2278  SDValue Tmp1 = ST->getChain();
2279  SDValue Tmp2 = ST->getBasePtr();
2280  SDValue Tmp3 = ST->getValue();
2281  assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2282  Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2283  SDValue Result =
2284  DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
2285  ST->getAlignment(), ST->getMemOperand()->getFlags());
2286  return Result;
2287 }
2288 
2289 SDValue
2290 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2291  std::string ParamSym;
2292  raw_string_ostream ParamStr(ParamSym);
2293 
2294  ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2295  ParamStr.flush();
2296 
2297  std::string *SavedStr =
2298  nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2299  return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2300 }
2301 
2302 // Check to see if the kernel argument is image*_t or sampler_t
2303 
2304 static bool isImageOrSamplerVal(const Value *arg, const Module *context) {
2305  static const char *const specialTypes[] = { "struct._image2d_t",
2306  "struct._image3d_t",
2307  "struct._sampler_t" };
2308 
2309  Type *Ty = arg->getType();
2310  auto *PTy = dyn_cast<PointerType>(Ty);
2311 
2312  if (!PTy)
2313  return false;
2314 
2315  if (!context)
2316  return false;
2317 
2318  auto *STy = dyn_cast<StructType>(PTy->getElementType());
2319  if (!STy || STy->isLiteral())
2320  return false;
2321 
2322  return std::find(std::begin(specialTypes), std::end(specialTypes),
2323  STy->getName()) != std::end(specialTypes);
2324 }
2325 
2327  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2328  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2329  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2330  MachineFunction &MF = DAG.getMachineFunction();
2331  const DataLayout &DL = DAG.getDataLayout();
2332  auto PtrVT = getPointerTy(DAG.getDataLayout());
2333 
2334  const Function *F = MF.getFunction();
2335  const AttributeList &PAL = F->getAttributes();
2336  const TargetLowering *TLI = STI.getTargetLowering();
2337 
2338  SDValue Root = DAG.getRoot();
2339  std::vector<SDValue> OutChains;
2340 
2341  bool isABI = (STI.getSmVersion() >= 20);
2342  assert(isABI && "Non-ABI compilation is not supported");
2343  if (!isABI)
2344  return Chain;
2345 
2346  std::vector<Type *> argTypes;
2347  std::vector<const Argument *> theArgs;
2348  for (const Argument &I : F->args()) {
2349  theArgs.push_back(&I);
2350  argTypes.push_back(I.getType());
2351  }
2352  // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2353  // Ins.size() will be larger
2354  // * if there is an aggregate argument with multiple fields (each field
2355  // showing up separately in Ins)
2356  // * if there is a vector argument with more than typical vector-length
2357  // elements (generally if more than 4) where each vector element is
2358  // individually present in Ins.
2359  // So a different index should be used for indexing into Ins.
2360  // See similar issue in LowerCall.
2361  unsigned InsIdx = 0;
2362 
2363  int idx = 0;
2364  for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2365  Type *Ty = argTypes[i];
2366 
2367  // If the kernel argument is image*_t or sampler_t, convert it to
2368  // a i32 constant holding the parameter position. This can later
2369  // matched in the AsmPrinter to output the correct mangled name.
2370  if (isImageOrSamplerVal(
2371  theArgs[i],
2372  (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2373  : nullptr))) {
2374  assert(isKernelFunction(*F) &&
2375  "Only kernels can have image/sampler params");
2376  InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2377  continue;
2378  }
2379 
2380  if (theArgs[i]->use_empty()) {
2381  // argument is dead
2382  if (Ty->isAggregateType() || Ty->isIntegerTy(128)) {
2383  SmallVector<EVT, 16> vtparts;
2384 
2385  ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2386  assert(vtparts.size() > 0 && "empty aggregate type not expected");
2387  for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2388  ++parti) {
2389  InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2390  ++InsIdx;
2391  }
2392  if (vtparts.size() > 0)
2393  --InsIdx;
2394  continue;
2395  }
2396  if (Ty->isVectorTy()) {
2397  EVT ObjectVT = getValueType(DL, Ty);
2398  unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2399  for (unsigned parti = 0; parti < NumRegs; ++parti) {
2400  InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2401  ++InsIdx;
2402  }
2403  if (NumRegs > 0)
2404  --InsIdx;
2405  continue;
2406  }
2407  InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2408  continue;
2409  }
2410 
2411  // In the following cases, assign a node order of "idx+1"
2412  // to newly created nodes. The SDNodes for params have to
2413  // appear in the same order as their order of appearance
2414  // in the original function. "idx+1" holds that order.
2415  if (!PAL.hasParamAttribute(i, Attribute::ByVal)) {
2416  bool aggregateIsPacked = false;
2417  if (StructType *STy = dyn_cast<StructType>(Ty))
2418  aggregateIsPacked = STy->isPacked();
2419 
2422  ComputePTXValueVTs(*this, DL, Ty, VTs, &Offsets, 0);
2423  assert(VTs.size() > 0 && "Unexpected empty type.");
2424  auto VectorInfo =
2425  VectorizePTXValueVTs(VTs, Offsets, DL.getABITypeAlignment(Ty));
2426 
2427  SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2428  int VecIdx = -1; // Index of the first element of the current vector.
2429  for (unsigned parti = 0, parte = VTs.size(); parti != parte; ++parti) {
2430  if (VectorInfo[parti] & PVF_FIRST) {
2431  assert(VecIdx == -1 && "Orphaned vector.");
2432  VecIdx = parti;
2433  }
2434 
2435  // That's the last element of this store op.
2436  if (VectorInfo[parti] & PVF_LAST) {
2437  unsigned NumElts = parti - VecIdx + 1;
2438  EVT EltVT = VTs[parti];
2439  // i1 is loaded/stored as i8.
2440  EVT LoadVT = EltVT;
2441  if (EltVT == MVT::i1)
2442  LoadVT = MVT::i8;
2443  else if (EltVT == MVT::v2f16)
2444  // getLoad needs a vector type, but it can't handle
2445  // vectors which contain v2f16 elements. So we must load
2446  // using i32 here and then bitcast back.
2447  LoadVT = MVT::i32;
2448 
2449  EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts);
2450  SDValue VecAddr =
2451  DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2452  DAG.getConstant(Offsets[VecIdx], dl, PtrVT));
2454  EltVT.getTypeForEVT(F->getContext()), ADDRESS_SPACE_PARAM));
2455  SDValue P =
2456  DAG.getLoad(VecVT, dl, Root, VecAddr,
2457  MachinePointerInfo(srcValue), aggregateIsPacked,
2460  if (P.getNode())
2461  P.getNode()->setIROrder(idx + 1);
2462  for (unsigned j = 0; j < NumElts; ++j) {
2463  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P,
2464  DAG.getIntPtrConstant(j, dl));
2465  // We've loaded i1 as an i8 and now must truncate it back to i1
2466  if (EltVT == MVT::i1)
2467  Elt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Elt);
2468  // v2f16 was loaded as an i32. Now we must bitcast it back.
2469  else if (EltVT == MVT::v2f16)
2470  Elt = DAG.getNode(ISD::BITCAST, dl, MVT::v2f16, Elt);
2471  // Extend the element if necessary (e.g. an i8 is loaded
2472  // into an i16 register)
2473  if (Ins[InsIdx].VT.isInteger() &&
2474  Ins[InsIdx].VT.getSizeInBits() > LoadVT.getSizeInBits()) {
2475  unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
2476  : ISD::ZERO_EXTEND;
2477  Elt = DAG.getNode(Extend, dl, Ins[InsIdx].VT, Elt);
2478  }
2479  InVals.push_back(Elt);
2480  }
2481 
2482  // Reset vector tracking state.
2483  VecIdx = -1;
2484  }
2485  ++InsIdx;
2486  }
2487  if (VTs.size() > 0)
2488  --InsIdx;
2489  continue;
2490  }
2491 
2492  // Param has ByVal attribute
2493  // Return MoveParam(param symbol).
2494  // Ideally, the param symbol can be returned directly,
2495  // but when SDNode builder decides to use it in a CopyToReg(),
2496  // machine instruction fails because TargetExternalSymbol
2497  // (not lowered) is target dependent, and CopyToReg assumes
2498  // the source is lowered.
2499  EVT ObjectVT = getValueType(DL, Ty);
2500  assert(ObjectVT == Ins[InsIdx].VT &&
2501  "Ins type did not match function type");
2502  SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2503  SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2504  if (p.getNode())
2505  p.getNode()->setIROrder(idx + 1);
2506  InVals.push_back(p);
2507  }
2508 
2509  // Clang will check explicit VarArg and issue error if any. However, Clang
2510  // will let code with
2511  // implicit var arg like f() pass. See bug 617733.
2512  // We treat this case as if the arg list is empty.
2513  // if (F.isVarArg()) {
2514  // assert(0 && "VarArg not supported yet!");
2515  //}
2516 
2517  if (!OutChains.empty())
2518  DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2519 
2520  return Chain;
2521 }
2522 
2523 SDValue
2525  bool isVarArg,
2526  const SmallVectorImpl<ISD::OutputArg> &Outs,
2527  const SmallVectorImpl<SDValue> &OutVals,
2528  const SDLoc &dl, SelectionDAG &DAG) const {
2529  MachineFunction &MF = DAG.getMachineFunction();
2530  Type *RetTy = MF.getFunction()->getReturnType();
2531 
2532  bool isABI = (STI.getSmVersion() >= 20);
2533  assert(isABI && "Non-ABI compilation is not supported");
2534  if (!isABI)
2535  return Chain;
2536 
2537  const DataLayout DL = DAG.getDataLayout();
2540  ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets);
2541  assert(VTs.size() == OutVals.size() && "Bad return value decomposition");
2542 
2543  auto VectorInfo = VectorizePTXValueVTs(
2544  VTs, Offsets, RetTy->isSized() ? DL.getABITypeAlignment(RetTy) : 1);
2545 
2546  // PTX Interoperability Guide 3.3(A): [Integer] Values shorter than
2547  // 32-bits are sign extended or zero extended, depending on whether
2548  // they are signed or unsigned types.
2549  bool ExtendIntegerRetVal =
2550  RetTy->isIntegerTy() && DL.getTypeAllocSizeInBits(RetTy) < 32;
2551 
2552  SmallVector<SDValue, 6> StoreOperands;
2553  for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2554  // New load/store. Record chain and offset operands.
2555  if (VectorInfo[i] & PVF_FIRST) {
2556  assert(StoreOperands.empty() && "Orphaned operand list.");
2557  StoreOperands.push_back(Chain);
2558  StoreOperands.push_back(DAG.getConstant(Offsets[i], dl, MVT::i32));
2559  }
2560 
2561  SDValue RetVal = OutVals[i];
2562  if (ExtendIntegerRetVal) {
2563  RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND
2564  : ISD::ZERO_EXTEND,
2565  dl, MVT::i32, RetVal);
2566  } else if (RetVal.getValueSizeInBits() < 16) {
2567  // Use 16-bit registers for small load-stores as it's the
2568  // smallest general purpose register size supported by NVPTX.
2569  RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal);
2570  }
2571 
2572  // Record the value to return.
2573  StoreOperands.push_back(RetVal);
2574 
2575  // That's the last element of this store op.
2576  if (VectorInfo[i] & PVF_LAST) {
2578  unsigned NumElts = StoreOperands.size() - 2;
2579  switch (NumElts) {
2580  case 1:
2581  Op = NVPTXISD::StoreRetval;
2582  break;
2583  case 2:
2585  break;
2586  case 4:
2588  break;
2589  default:
2590  llvm_unreachable("Invalid vector info.");
2591  }
2592 
2593  // Adjust type of load/store op if we've extended the scalar
2594  // return value.
2595  EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
2596  Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
2597  StoreOperands, TheStoreType,
2598  MachinePointerInfo(), /* Align */ 1,
2599  /* Volatile */ false, /* ReadMem */ false,
2600  /* WriteMem */ true, /* Size */ 0);
2601  // Cleanup vector state.
2602  StoreOperands.clear();
2603  }
2604  }
2605 
2606  return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2607 }
2608 
2610  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2611  SelectionDAG &DAG) const {
2612  if (Constraint.length() > 1)
2613  return;
2614  else
2615  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2616 }
2617 
2618 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2619  switch (Intrinsic) {
2620  default:
2621  return 0;
2622 
2623  case Intrinsic::nvvm_tex_1d_v4f32_s32:
2624  return NVPTXISD::Tex1DFloatS32;
2625  case Intrinsic::nvvm_tex_1d_v4f32_f32:
2627  case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2629  case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2631  case Intrinsic::nvvm_tex_1d_v4s32_s32:
2632  return NVPTXISD::Tex1DS32S32;
2633  case Intrinsic::nvvm_tex_1d_v4s32_f32:
2634  return NVPTXISD::Tex1DS32Float;
2635  case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2637  case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2639  case Intrinsic::nvvm_tex_1d_v4u32_s32:
2640  return NVPTXISD::Tex1DU32S32;
2641  case Intrinsic::nvvm_tex_1d_v4u32_f32:
2642  return NVPTXISD::Tex1DU32Float;
2643  case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2645  case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2647 
2648  case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2650  case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2652  case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2654  case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2656  case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2658  case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2660  case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2662  case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2664  case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2666  case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2668  case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2670  case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2672 
2673  case Intrinsic::nvvm_tex_2d_v4f32_s32:
2674  return NVPTXISD::Tex2DFloatS32;
2675  case Intrinsic::nvvm_tex_2d_v4f32_f32:
2677  case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2679  case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2681  case Intrinsic::nvvm_tex_2d_v4s32_s32:
2682  return NVPTXISD::Tex2DS32S32;
2683  case Intrinsic::nvvm_tex_2d_v4s32_f32:
2684  return NVPTXISD::Tex2DS32Float;
2685  case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2687  case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2689  case Intrinsic::nvvm_tex_2d_v4u32_s32:
2690  return NVPTXISD::Tex2DU32S32;
2691  case Intrinsic::nvvm_tex_2d_v4u32_f32:
2692  return NVPTXISD::Tex2DU32Float;
2693  case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2695  case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2697 
2698  case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2700  case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2702  case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2704  case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2706  case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2708  case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2710  case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2712  case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2714  case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2716  case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2718  case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2720  case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2722 
2723  case Intrinsic::nvvm_tex_3d_v4f32_s32:
2724  return NVPTXISD::Tex3DFloatS32;
2725  case Intrinsic::nvvm_tex_3d_v4f32_f32:
2727  case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2729  case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2731  case Intrinsic::nvvm_tex_3d_v4s32_s32:
2732  return NVPTXISD::Tex3DS32S32;
2733  case Intrinsic::nvvm_tex_3d_v4s32_f32:
2734  return NVPTXISD::Tex3DS32Float;
2735  case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2737  case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2739  case Intrinsic::nvvm_tex_3d_v4u32_s32:
2740  return NVPTXISD::Tex3DU32S32;
2741  case Intrinsic::nvvm_tex_3d_v4u32_f32:
2742  return NVPTXISD::Tex3DU32Float;
2743  case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2745  case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2747 
2748  case Intrinsic::nvvm_tex_cube_v4f32_f32:
2750  case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2752  case Intrinsic::nvvm_tex_cube_v4s32_f32:
2754  case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2756  case Intrinsic::nvvm_tex_cube_v4u32_f32:
2758  case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2760 
2761  case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2763  case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2765  case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2767  case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2769  case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2771  case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2773 
2774  case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2776  case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2778  case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2780  case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2782  case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2784  case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2786  case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2788  case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2790  case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2792  case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2794  case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2796  case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2798 
2799  case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2801  case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2803  case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2805  case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2807  case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2809  case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2811  case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2813  case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2815  case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2817  case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2819  case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2821  case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2823 
2824  case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2826  case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2828  case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2830  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2832  case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2834  case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2836  case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2838  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2840  case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2842  case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2844  case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2846  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2848 
2849  case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2851  case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2853  case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2855  case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2857  case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2859  case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2861  case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2863  case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2865  case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2867  case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2869  case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2871  case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2873 
2874  case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2876  case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2878  case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2880  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2882  case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2884  case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2886  case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2888  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2890  case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2892  case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2894  case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2896  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2898 
2899  case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2901  case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2903  case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2905  case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2907  case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2909  case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2911  case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2913  case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2915  case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2917  case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2919  case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2921  case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2923 
2924  case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2926  case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2928  case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2930  case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2932  case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2934  case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2936 
2937  case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2939  case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2941  case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2943  case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2945  case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2947  case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2949 
2950  case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2952  case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2954  case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2956  case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2958  case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2960  case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2962  case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2964  case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2966  case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2968  case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2970  case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2972  case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2974  }
2975 }
2976 
2977 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2978  switch (Intrinsic) {
2979  default:
2980  return 0;
2981  case Intrinsic::nvvm_suld_1d_i8_clamp:
2982  return NVPTXISD::Suld1DI8Clamp;
2983  case Intrinsic::nvvm_suld_1d_i16_clamp:
2984  return NVPTXISD::Suld1DI16Clamp;
2985  case Intrinsic::nvvm_suld_1d_i32_clamp:
2986  return NVPTXISD::Suld1DI32Clamp;
2987  case Intrinsic::nvvm_suld_1d_i64_clamp:
2988  return NVPTXISD::Suld1DI64Clamp;
2989  case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2991  case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2993  case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2995  case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2997  case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2999  case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3001  case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3003  case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3005  case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3007  case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3009  case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3011  case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3013  case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3015  case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3017  case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3019  case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3021  case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3023  case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3025  case Intrinsic::nvvm_suld_2d_i8_clamp:
3026  return NVPTXISD::Suld2DI8Clamp;
3027  case Intrinsic::nvvm_suld_2d_i16_clamp:
3028  return NVPTXISD::Suld2DI16Clamp;
3029  case Intrinsic::nvvm_suld_2d_i32_clamp:
3030  return NVPTXISD::Suld2DI32Clamp;
3031  case Intrinsic::nvvm_suld_2d_i64_clamp:
3032  return NVPTXISD::Suld2DI64Clamp;
3033  case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3035  case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3037  case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3039  case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3041  case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3043  case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3045  case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3047  case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3049  case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3051  case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3053  case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3055  case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3057  case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3059  case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3061  case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3063  case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3065  case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3067  case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3069  case Intrinsic::nvvm_suld_3d_i8_clamp:
3070  return NVPTXISD::Suld3DI8Clamp;
3071  case Intrinsic::nvvm_suld_3d_i16_clamp:
3072  return NVPTXISD::Suld3DI16Clamp;
3073  case Intrinsic::nvvm_suld_3d_i32_clamp:
3074  return NVPTXISD::Suld3DI32Clamp;
3075  case Intrinsic::nvvm_suld_3d_i64_clamp:
3076  return NVPTXISD::Suld3DI64Clamp;
3077  case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3079  case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3081  case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3083  case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3085  case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3087  case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3089  case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3091  case Intrinsic::nvvm_suld_1d_i8_trap:
3092  return NVPTXISD::Suld1DI8Trap;
3093  case Intrinsic::nvvm_suld_1d_i16_trap:
3094  return NVPTXISD::Suld1DI16Trap;
3095  case Intrinsic::nvvm_suld_1d_i32_trap:
3096  return NVPTXISD::Suld1DI32Trap;
3097  case Intrinsic::nvvm_suld_1d_i64_trap:
3098  return NVPTXISD::Suld1DI64Trap;
3099  case Intrinsic::nvvm_suld_1d_v2i8_trap:
3100  return NVPTXISD::Suld1DV2I8Trap;
3101  case Intrinsic::nvvm_suld_1d_v2i16_trap:
3103  case Intrinsic::nvvm_suld_1d_v2i32_trap:
3105  case Intrinsic::nvvm_suld_1d_v2i64_trap:
3107  case Intrinsic::nvvm_suld_1d_v4i8_trap:
3108  return NVPTXISD::Suld1DV4I8Trap;
3109  case Intrinsic::nvvm_suld_1d_v4i16_trap:
3111  case Intrinsic::nvvm_suld_1d_v4i32_trap:
3113  case Intrinsic::nvvm_suld_1d_array_i8_trap:
3115  case Intrinsic::nvvm_suld_1d_array_i16_trap:
3117  case Intrinsic::nvvm_suld_1d_array_i32_trap:
3119  case Intrinsic::nvvm_suld_1d_array_i64_trap:
3121  case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3123  case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3125  case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3127  case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3129  case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3131  case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3133  case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3135  case Intrinsic::nvvm_suld_2d_i8_trap:
3136  return NVPTXISD::Suld2DI8Trap;
3137  case Intrinsic::nvvm_suld_2d_i16_trap:
3138  return NVPTXISD::Suld2DI16Trap;
3139  case Intrinsic::nvvm_suld_2d_i32_trap:
3140  return NVPTXISD::Suld2DI32Trap;
3141  case Intrinsic::nvvm_suld_2d_i64_trap:
3142  return NVPTXISD::Suld2DI64Trap;
3143  case Intrinsic::nvvm_suld_2d_v2i8_trap:
3144  return NVPTXISD::Suld2DV2I8Trap;
3145  case Intrinsic::nvvm_suld_2d_v2i16_trap:
3147  case Intrinsic::nvvm_suld_2d_v2i32_trap:
3149  case Intrinsic::nvvm_suld_2d_v2i64_trap:
3151  case Intrinsic::nvvm_suld_2d_v4i8_trap:
3152  return NVPTXISD::Suld2DV4I8Trap;
3153  case Intrinsic::nvvm_suld_2d_v4i16_trap:
3155  case Intrinsic::nvvm_suld_2d_v4i32_trap:
3157  case Intrinsic::nvvm_suld_2d_array_i8_trap:
3159  case Intrinsic::nvvm_suld_2d_array_i16_trap:
3161  case Intrinsic::nvvm_suld_2d_array_i32_trap:
3163  case Intrinsic::nvvm_suld_2d_array_i64_trap:
3165  case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3167  case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3169  case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3171  case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3173  case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3175  case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3177  case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3179  case Intrinsic::nvvm_suld_3d_i8_trap:
3180  return NVPTXISD::Suld3DI8Trap;
3181  case Intrinsic::nvvm_suld_3d_i16_trap:
3182  return NVPTXISD::Suld3DI16Trap;
3183  case Intrinsic::nvvm_suld_3d_i32_trap:
3184  return NVPTXISD::Suld3DI32Trap;
3185  case Intrinsic::nvvm_suld_3d_i64_trap:
3186  return NVPTXISD::Suld3DI64Trap;
3187  case Intrinsic::nvvm_suld_3d_v2i8_trap:
3188  return NVPTXISD::Suld3DV2I8Trap;
3189  case Intrinsic::nvvm_suld_3d_v2i16_trap:
3191  case Intrinsic::nvvm_suld_3d_v2i32_trap:
3193  case Intrinsic::nvvm_suld_3d_v2i64_trap:
3195  case Intrinsic::nvvm_suld_3d_v4i8_trap:
3196  return NVPTXISD::Suld3DV4I8Trap;
3197  case Intrinsic::nvvm_suld_3d_v4i16_trap:
3199  case Intrinsic::nvvm_suld_3d_v4i32_trap:
3201  case Intrinsic::nvvm_suld_1d_i8_zero:
3202  return NVPTXISD::Suld1DI8Zero;
3203  case Intrinsic::nvvm_suld_1d_i16_zero:
3204  return NVPTXISD::Suld1DI16Zero;
3205  case Intrinsic::nvvm_suld_1d_i32_zero:
3206  return NVPTXISD::Suld1DI32Zero;
3207  case Intrinsic::nvvm_suld_1d_i64_zero:
3208  return NVPTXISD::Suld1DI64Zero;
3209  case Intrinsic::nvvm_suld_1d_v2i8_zero:
3210  return NVPTXISD::Suld1DV2I8Zero;
3211  case Intrinsic::nvvm_suld_1d_v2i16_zero:
3213  case Intrinsic::nvvm_suld_1d_v2i32_zero:
3215  case Intrinsic::nvvm_suld_1d_v2i64_zero:
3217  case Intrinsic::nvvm_suld_1d_v4i8_zero:
3218  return NVPTXISD::Suld1DV4I8Zero;
3219  case Intrinsic::nvvm_suld_1d_v4i16_zero:
3221  case Intrinsic::nvvm_suld_1d_v4i32_zero:
3223  case Intrinsic::nvvm_suld_1d_array_i8_zero:
3225  case Intrinsic::nvvm_suld_1d_array_i16_zero:
3227  case Intrinsic::nvvm_suld_1d_array_i32_zero:
3229  case Intrinsic::nvvm_suld_1d_array_i64_zero:
3231  case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3233  case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3235  case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3237  case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3239  case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3241  case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3243  case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3245  case Intrinsic::nvvm_suld_2d_i8_zero:
3246  return NVPTXISD::Suld2DI8Zero;
3247  case Intrinsic::nvvm_suld_2d_i16_zero:
3248  return NVPTXISD::Suld2DI16Zero;
3249  case Intrinsic::nvvm_suld_2d_i32_zero:
3250  return NVPTXISD::Suld2DI32Zero;
3251  case Intrinsic::nvvm_suld_2d_i64_zero:
3252  return NVPTXISD::Suld2DI64Zero;
3253  case Intrinsic::nvvm_suld_2d_v2i8_zero:
3254  return NVPTXISD::Suld2DV2I8Zero;
3255  case Intrinsic::nvvm_suld_2d_v2i16_zero:
3257  case Intrinsic::nvvm_suld_2d_v2i32_zero:
3259  case Intrinsic::nvvm_suld_2d_v2i64_zero:
3261  case Intrinsic::nvvm_suld_2d_v4i8_zero:
3262  return NVPTXISD::Suld2DV4I8Zero;
3263  case Intrinsic::nvvm_suld_2d_v4i16_zero:
3265  case Intrinsic::nvvm_suld_2d_v4i32_zero:
3267  case Intrinsic::nvvm_suld_2d_array_i8_zero:
3269  case Intrinsic::nvvm_suld_2d_array_i16_zero:
3271  case Intrinsic::nvvm_suld_2d_array_i32_zero:
3273  case Intrinsic::nvvm_suld_2d_array_i64_zero:
3275  case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3277  case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3279  case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3281  case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3283  case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3285  case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3287  case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3289  case Intrinsic::nvvm_suld_3d_i8_zero:
3290  return NVPTXISD::Suld3DI8Zero;
3291  case Intrinsic::nvvm_suld_3d_i16_zero:
3292  return NVPTXISD::Suld3DI16Zero;
3293  case Intrinsic::nvvm_suld_3d_i32_zero:
3294  return NVPTXISD::Suld3DI32Zero;
3295  case Intrinsic::nvvm_suld_3d_i64_zero:
3296  return NVPTXISD::Suld3DI64Zero;
3297  case Intrinsic::nvvm_suld_3d_v2i8_zero:
3298  return NVPTXISD::Suld3DV2I8Zero;
3299  case Intrinsic::nvvm_suld_3d_v2i16_zero:
3301  case Intrinsic::nvvm_suld_3d_v2i32_zero:
3303  case Intrinsic::nvvm_suld_3d_v2i64_zero:
3305  case Intrinsic::nvvm_suld_3d_v4i8_zero:
3306  return NVPTXISD::Suld3DV4I8Zero;
3307  case Intrinsic::nvvm_suld_3d_v4i16_zero:
3309  case Intrinsic::nvvm_suld_3d_v4i32_zero:
3311  }
3312 }
3313 
3314 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3315 // TgtMemIntrinsic
3316 // because we need the information that is only available in the "Value" type
3317 // of destination
3318 // pointer. In particular, the address space information.
3320  IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3321  switch (Intrinsic) {
3322  default:
3323  return false;
3324 
3325  case Intrinsic::nvvm_atomic_load_add_f32:
3326  case Intrinsic::nvvm_atomic_load_inc_32:
3327  case Intrinsic::nvvm_atomic_load_dec_32:
3328 
3329  case Intrinsic::nvvm_atomic_add_gen_f_cta:
3330  case Intrinsic::nvvm_atomic_add_gen_f_sys:
3331  case Intrinsic::nvvm_atomic_add_gen_i_cta:
3332  case Intrinsic::nvvm_atomic_add_gen_i_sys:
3333  case Intrinsic::nvvm_atomic_and_gen_i_cta:
3334  case Intrinsic::nvvm_atomic_and_gen_i_sys:
3335  case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3336  case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3337  case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3338  case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3339  case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3340  case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3341  case Intrinsic::nvvm_atomic_max_gen_i_cta:
3342  case Intrinsic::nvvm_atomic_max_gen_i_sys:
3343  case Intrinsic::nvvm_atomic_min_gen_i_cta:
3344  case Intrinsic::nvvm_atomic_min_gen_i_sys:
3345  case Intrinsic::nvvm_atomic_or_gen_i_cta:
3346  case Intrinsic::nvvm_atomic_or_gen_i_sys:
3347  case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3348  case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3349  case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3350  case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3351  auto &DL = I.getModule()->getDataLayout();
3352  Info.opc = ISD::INTRINSIC_W_CHAIN;
3353  Info.memVT = getValueType(DL, I.getType());
3354  Info.ptrVal = I.getArgOperand(0);
3355  Info.offset = 0;
3356  Info.vol = false;
3357  Info.readMem = true;
3358  Info.writeMem = true;
3359  Info.align = 0;
3360  return true;
3361  }
3362 
3363  case Intrinsic::nvvm_ldu_global_i:
3364  case Intrinsic::nvvm_ldu_global_f:
3365  case Intrinsic::nvvm_ldu_global_p: {
3366  auto &DL = I.getModule()->getDataLayout();
3367  Info.opc = ISD::INTRINSIC_W_CHAIN;
3368  if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3369  Info.memVT = getValueType(DL, I.getType());
3370  else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3371  Info.memVT = getPointerTy(DL);
3372  else
3373  Info.memVT = getValueType(DL, I.getType());
3374  Info.ptrVal = I.getArgOperand(0);
3375  Info.offset = 0;
3376  Info.vol = false;
3377  Info.readMem = true;
3378  Info.writeMem = false;
3379  Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3380 
3381  return true;
3382  }
3383  case Intrinsic::nvvm_ldg_global_i:
3384  case Intrinsic::nvvm_ldg_global_f:
3385  case Intrinsic::nvvm_ldg_global_p: {
3386  auto &DL = I.getModule()->getDataLayout();
3387 
3388  Info.opc = ISD::INTRINSIC_W_CHAIN;
3389  if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3390  Info.memVT = getValueType(DL, I.getType());
3391  else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3392  Info.memVT = getPointerTy(DL);
3393  else
3394  Info.memVT = getValueType(DL, I.getType());
3395  Info.ptrVal = I.getArgOperand(0);
3396  Info.offset = 0;
3397  Info.vol = false;
3398  Info.readMem = true;
3399  Info.writeMem = false;
3400  Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3401 
3402  return true;
3403  }
3404 
3405  case Intrinsic::nvvm_tex_1d_v4f32_s32:
3406  case Intrinsic::nvvm_tex_1d_v4f32_f32:
3407  case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3408  case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3409  case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3410  case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3411  case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3412  case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3413  case Intrinsic::nvvm_tex_2d_v4f32_s32:
3414  case Intrinsic::nvvm_tex_2d_v4f32_f32:
3415  case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3416  case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3417  case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3418  case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3419  case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3420  case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3421  case Intrinsic::nvvm_tex_3d_v4f32_s32:
3422  case Intrinsic::nvvm_tex_3d_v4f32_f32:
3423  case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3424  case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3425  case Intrinsic::nvvm_tex_cube_v4f32_f32:
3426  case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3427  case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3428  case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3429  case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3430  case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3431  case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3432  case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3433  case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3434  case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3435  case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3436  case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3437  case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3438  case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3439  case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3440  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3441  case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3442  case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3443  case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3444  case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3445  case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3446  case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3447  case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3448  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3449  case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3450  case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3451  case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3452  case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3453  case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3454  case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3455  case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3456  case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3457  case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3458  case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3459  case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3460  case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3461  Info.opc = getOpcForTextureInstr(Intrinsic);
3462  Info.memVT = MVT::v4f32;
3463  Info.ptrVal = nullptr;
3464  Info.offset = 0;
3465  Info.vol = false;
3466  Info.readMem = true;
3467  Info.writeMem = false;
3468  Info.align = 16;
3469  return true;
3470 
3471  case Intrinsic::nvvm_tex_1d_v4s32_s32:
3472  case Intrinsic::nvvm_tex_1d_v4s32_f32:
3473  case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3474  case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3475  case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3476  case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3477  case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3478  case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3479  case Intrinsic::nvvm_tex_2d_v4s32_s32:
3480  case Intrinsic::nvvm_tex_2d_v4s32_f32:
3481  case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3482  case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3483  case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3484  case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3485  case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3486  case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3487  case Intrinsic::nvvm_tex_3d_v4s32_s32:
3488  case Intrinsic::nvvm_tex_3d_v4s32_f32:
3489  case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3490  case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3491  case Intrinsic::nvvm_tex_cube_v4s32_f32:
3492  case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3493  case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3494  case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3495  case Intrinsic::nvvm_tex_cube_v4u32_f32:
3496  case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3497  case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3498  case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3499  case Intrinsic::nvvm_tex_1d_v4u32_s32:
3500  case Intrinsic::nvvm_tex_1d_v4u32_f32:
3501  case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3502  case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3503  case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3504  case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3505  case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3506  case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3507  case Intrinsic::nvvm_tex_2d_v4u32_s32:
3508  case Intrinsic::nvvm_tex_2d_v4u32_f32:
3509  case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3510  case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3511  case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3512  case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3513  case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3514  case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3515  case Intrinsic::nvvm_tex_3d_v4u32_s32:
3516  case Intrinsic::nvvm_tex_3d_v4u32_f32:
3517  case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3518  case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3519  case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3520  case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3521  case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3522  case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3523  case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3524  case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3525  case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3526  case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3527  case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3528  case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3529  case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3530  case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3531  case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3532  case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3533  case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3534  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3535  case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3536  case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3537  case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3538  case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3539  case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3540  case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3541  case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3542  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3543  case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3544  case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3545  case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3546  case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3547  case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3548  case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3549  case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3550  case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3551  case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3552  case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3553  case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3554  case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3555  case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3556  case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3557  case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3558  case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3559  case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3560  case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3561  case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3562  case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3563  case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3564  case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3565  case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3566  case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3567  case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3568  case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3569  case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3570  case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3571  case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3572  case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3573  case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3574  case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3575  case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3576  case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3577  case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3578  case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3579  case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3580  case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3581  case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3582  case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3583  Info.opc = getOpcForTextureInstr(Intrinsic);
3584  Info.memVT = MVT::v4i32;
3585  Info.ptrVal = nullptr;
3586  Info.offset = 0;
3587  Info.vol = false;
3588  Info.readMem = true;
3589  Info.writeMem = false;
3590  Info.align = 16;
3591  return true;
3592 
3593  case Intrinsic::nvvm_suld_1d_i8_clamp:
3594  case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3595  case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3596  case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3597  case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3598  case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3599  case Intrinsic::nvvm_suld_2d_i8_clamp:
3600  case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3601  case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3602  case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3603  case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3604  case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3605  case Intrinsic::nvvm_suld_3d_i8_clamp:
3606  case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3607  case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3608  case Intrinsic::nvvm_suld_1d_i8_trap:
3609  case Intrinsic::nvvm_suld_1d_v2i8_trap:
3610  case Intrinsic::nvvm_suld_1d_v4i8_trap:
3611  case Intrinsic::nvvm_suld_1d_array_i8_trap:
3612  case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3613  case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3614  case Intrinsic::nvvm_suld_2d_i8_trap:
3615  case Intrinsic::nvvm_suld_2d_v2i8_trap:
3616  case Intrinsic::nvvm_suld_2d_v4i8_trap:
3617  case Intrinsic::nvvm_suld_2d_array_i8_trap:
3618  case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3619  case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3620  case Intrinsic::nvvm_suld_3d_i8_trap:
3621  case Intrinsic::nvvm_suld_3d_v2i8_trap:
3622  case Intrinsic::nvvm_suld_3d_v4i8_trap:
3623  case Intrinsic::nvvm_suld_1d_i8_zero:
3624  case Intrinsic::nvvm_suld_1d_v2i8_zero:
3625  case Intrinsic::nvvm_suld_1d_v4i8_zero:
3626  case Intrinsic::nvvm_suld_1d_array_i8_zero:
3627  case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3628  case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3629  case Intrinsic::nvvm_suld_2d_i8_zero:
3630  case Intrinsic::nvvm_suld_2d_v2i8_zero:
3631  case Intrinsic::nvvm_suld_2d_v4i8_zero:
3632  case Intrinsic::nvvm_suld_2d_array_i8_zero:
3633  case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3634  case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3635  case Intrinsic::nvvm_suld_3d_i8_zero:
3636  case Intrinsic::nvvm_suld_3d_v2i8_zero:
3637  case Intrinsic::nvvm_suld_3d_v4i8_zero:
3638  Info.opc = getOpcForSurfaceInstr(Intrinsic);
3639  Info.memVT = MVT::i8;
3640  Info.ptrVal = nullptr;
3641  Info.offset = 0;
3642  Info.vol = false;
3643  Info.readMem = true;
3644  Info.writeMem = false;
3645  Info.align = 16;
3646  return true;
3647 
3648  case Intrinsic::nvvm_suld_1d_i16_clamp:
3649  case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3650  case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3651  case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3652  case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3653  case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3654  case Intrinsic::nvvm_suld_2d_i16_clamp:
3655  case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3656  case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3657  case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3658  case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3659  case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3660  case Intrinsic::nvvm_suld_3d_i16_clamp:
3661  case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3662  case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3663  case Intrinsic::nvvm_suld_1d_i16_trap:
3664  case Intrinsic::nvvm_suld_1d_v2i16_trap:
3665  case Intrinsic::nvvm_suld_1d_v4i16_trap:
3666  case Intrinsic::nvvm_suld_1d_array_i16_trap:
3667  case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3668  case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3669  case Intrinsic::nvvm_suld_2d_i16_trap:
3670  case Intrinsic::nvvm_suld_2d_v2i16_trap:
3671  case Intrinsic::nvvm_suld_2d_v4i16_trap:
3672  case Intrinsic::nvvm_suld_2d_array_i16_trap:
3673  case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3674  case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3675  case Intrinsic::nvvm_suld_3d_i16_trap:
3676  case Intrinsic::nvvm_suld_3d_v2i16_trap:
3677  case Intrinsic::nvvm_suld_3d_v4i16_trap:
3678  case Intrinsic::nvvm_suld_1d_i16_zero:
3679  case Intrinsic::nvvm_suld_1d_v2i16_zero:
3680  case Intrinsic::nvvm_suld_1d_v4i16_zero:
3681  case Intrinsic::nvvm_suld_1d_array_i16_zero:
3682  case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3683  case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3684  case Intrinsic::nvvm_suld_2d_i16_zero:
3685  case Intrinsic::nvvm_suld_2d_v2i16_zero:
3686  case Intrinsic::nvvm_suld_2d_v4i16_zero:
3687  case Intrinsic::nvvm_suld_2d_array_i16_zero:
3688  case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3689  case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3690  case Intrinsic::nvvm_suld_3d_i16_zero:
3691  case Intrinsic::nvvm_suld_3d_v2i16_zero:
3692  case Intrinsic::nvvm_suld_3d_v4i16_zero:
3693  Info.opc = getOpcForSurfaceInstr(Intrinsic);
3694  Info.memVT = MVT::i16;
3695  Info.ptrVal = nullptr;
3696  Info.offset = 0;
3697  Info.vol = false;
3698  Info.readMem = true;
3699  Info.writeMem = false;
3700  Info.align = 16;
3701  return true;
3702 
3703  case Intrinsic::nvvm_suld_1d_i32_clamp:
3704  case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3705  case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3706  case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3707  case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3708  case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3709  case Intrinsic::nvvm_suld_2d_i32_clamp:
3710  case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3711  case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3712  case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3713  case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3714  case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3715  case Intrinsic::nvvm_suld_3d_i32_clamp:
3716  case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3717  case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3718  case Intrinsic::nvvm_suld_1d_i32_trap:
3719  case Intrinsic::nvvm_suld_1d_v2i32_trap:
3720  case Intrinsic::nvvm_suld_1d_v4i32_trap:
3721  case Intrinsic::nvvm_suld_1d_array_i32_trap:
3722  case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3723  case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3724  case Intrinsic::nvvm_suld_2d_i32_trap:
3725  case Intrinsic::nvvm_suld_2d_v2i32_trap:
3726  case Intrinsic::nvvm_suld_2d_v4i32_trap:
3727  case Intrinsic::nvvm_suld_2d_array_i32_trap:
3728  case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3729  case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3730  case Intrinsic::nvvm_suld_3d_i32_trap:
3731  case Intrinsic::nvvm_suld_3d_v2i32_trap:
3732  case Intrinsic::nvvm_suld_3d_v4i32_trap:
3733  case Intrinsic::nvvm_suld_1d_i32_zero:
3734  case Intrinsic::nvvm_suld_1d_v2i32_zero:
3735  case Intrinsic::nvvm_suld_1d_v4i32_zero:
3736  case Intrinsic::nvvm_suld_1d_array_i32_zero:
3737  case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3738  case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3739  case Intrinsic::nvvm_suld_2d_i32_zero:
3740  case Intrinsic::nvvm_suld_2d_v2i32_zero:
3741  case Intrinsic::nvvm_suld_2d_v4i32_zero:
3742  case Intrinsic::nvvm_suld_2d_array_i32_zero:
3743  case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3744  case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3745  case Intrinsic::nvvm_suld_3d_i32_zero:
3746  case Intrinsic::nvvm_suld_3d_v2i32_zero:
3747  case Intrinsic::nvvm_suld_3d_v4i32_zero:
3748  Info.opc = getOpcForSurfaceInstr(Intrinsic);
3749  Info.memVT = MVT::i32;
3750  Info.ptrVal = nullptr;
3751  Info.offset = 0;
3752  Info.vol = false;
3753  Info.readMem = true;
3754  Info.writeMem = false;
3755  Info.align = 16;
3756  return true;
3757 
3758  case Intrinsic::nvvm_suld_1d_i64_clamp:
3759  case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3760  case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3761  case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3762  case Intrinsic::nvvm_suld_2d_i64_clamp:
3763  case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3764  case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3765  case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3766  case Intrinsic::nvvm_suld_3d_i64_clamp:
3767  case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3768  case Intrinsic::nvvm_suld_1d_i64_trap:
3769  case Intrinsic::nvvm_suld_1d_v2i64_trap:
3770  case Intrinsic::nvvm_suld_1d_array_i64_trap:
3771  case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3772  case Intrinsic::nvvm_suld_2d_i64_trap:
3773  case Intrinsic::nvvm_suld_2d_v2i64_trap:
3774  case Intrinsic::nvvm_suld_2d_array_i64_trap:
3775  case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3776  case Intrinsic::nvvm_suld_3d_i64_trap:
3777  case Intrinsic::nvvm_suld_3d_v2i64_trap:
3778  case Intrinsic::nvvm_suld_1d_i64_zero:
3779  case Intrinsic::nvvm_suld_1d_v2i64_zero:
3780  case Intrinsic::nvvm_suld_1d_array_i64_zero:
3781  case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3782  case Intrinsic::nvvm_suld_2d_i64_zero:
3783  case Intrinsic::nvvm_suld_2d_v2i64_zero:
3784  case Intrinsic::nvvm_suld_2d_array_i64_zero:
3785  case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3786  case Intrinsic::nvvm_suld_3d_i64_zero:
3787  case Intrinsic::nvvm_suld_3d_v2i64_zero:
3788  Info.opc = getOpcForSurfaceInstr(Intrinsic);
3789  Info.memVT = MVT::i64;
3790  Info.ptrVal = nullptr;
3791  Info.offset = 0;
3792  Info.vol = false;
3793  Info.readMem = true;
3794  Info.writeMem = false;
3795  Info.align = 16;
3796  return true;
3797  }
3798  return false;
3799 }
3800 
3801 /// isLegalAddressingMode - Return true if the addressing mode represented
3802 /// by AM is legal for this target, for a load/store of the specified type.
3803 /// Used to guide target specific optimizations, like loop strength reduction
3804 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3805 /// (CodeGenPrepare.cpp)
3807  const AddrMode &AM, Type *Ty,
3808  unsigned AS, Instruction *I) const {
3809  // AddrMode - This represents an addressing mode of:
3810  // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3811  //
3812  // The legal address modes are
3813  // - [avar]
3814  // - [areg]
3815  // - [areg+immoff]
3816  // - [immAddr]
3817 
3818  if (AM.BaseGV) {
3819  return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3820  }
3821 
3822  switch (AM.Scale) {
3823  case 0: // "r", "r+i" or "i" is allowed
3824  break;
3825  case 1:
3826  if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3827  return false;
3828  // Otherwise we have r+i.
3829  break;
3830  default:
3831  // No scale > 1 is allowed
3832  return false;
3833  }
3834  return true;
3835 }
3836 
3837 //===----------------------------------------------------------------------===//
3838 // NVPTX Inline Assembly Support
3839 //===----------------------------------------------------------------------===//
3840 
3841 /// getConstraintType - Given a constraint letter, return the type of
3842 /// constraint it is for this target.
3845  if (Constraint.size() == 1) {
3846  switch (Constraint[0]) {
3847  default:
3848  break;
3849  case 'b':
3850  case 'r':
3851  case 'h':
3852  case 'c':
3853  case 'l':
3854  case 'f':
3855  case 'd':
3856  case '0':
3857  case 'N':
3858  return C_RegisterClass;
3859  }
3860  }
3861  return TargetLowering::getConstraintType(Constraint);
3862 }
3863 
3864 std::pair<unsigned, const TargetRegisterClass *>
3866  StringRef Constraint,
3867  MVT VT) const {
3868  if (Constraint.size() == 1) {
3869  switch (Constraint[0]) {
3870  case 'b':
3871  return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3872  case 'c':
3873  return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3874  case 'h':
3875  return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3876  case 'r':
3877  return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3878  case 'l':
3879  case 'N':
3880  return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3881  case 'f':
3882  return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3883  case 'd':
3884  return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3885  }
3886  }
3887  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3888 }
3889 
3890 //===----------------------------------------------------------------------===//
3891 // NVPTX DAG Combining
3892 //===----------------------------------------------------------------------===//
3893 
3895  CodeGenOpt::Level OptLevel) const {
3896  // Always honor command-line argument
3897  if (FMAContractLevelOpt.getNumOccurrences() > 0)
3898  return FMAContractLevelOpt > 0;
3899 
3900  // Do not contract if we're not optimizing the code.
3901  if (OptLevel == 0)
3902  return false;
3903 
3904  // Honor TargetOptions flags that explicitly say fusion is okay.
3906  return true;
3907 
3908  return allowUnsafeFPMath(MF);
3909 }
3910 
3912  // Honor TargetOptions flags that explicitly say unsafe math is okay.
3913  if (MF.getTarget().Options.UnsafeFPMath)
3914  return true;
3915 
3916  // Allow unsafe math if unsafe-fp-math attribute explicitly says so.
3917  const Function *F = MF.getFunction();
3918  if (F->hasFnAttribute("unsafe-fp-math")) {
3919  Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3920  StringRef Val = Attr.getValueAsString();
3921  if (Val == "true")
3922  return true;
3923  }
3924 
3925  return false;
3926 }
3927 
3928 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3929 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3930 /// called with the default operands, and if that fails, with commuted
3931 /// operands.
3934  const NVPTXSubtarget &Subtarget,
3935  CodeGenOpt::Level OptLevel) {
3936  SelectionDAG &DAG = DCI.DAG;
3937  // Skip non-integer, non-scalar case
3938  EVT VT=N0.getValueType();
3939  if (VT.isVector())
3940  return SDValue();
3941 
3942  // fold (add (mul a, b), c) -> (mad a, b, c)
3943  //
3944  if (N0.getOpcode() == ISD::MUL) {
3945  assert (VT.isInteger());
3946  // For integer:
3947  // Since integer multiply-add costs the same as integer multiply
3948  // but is more costly than integer add, do the fusion only when
3949  // the mul is only used in the add.
3950  if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3951  !N0.getNode()->hasOneUse())
3952  return SDValue();
3953 
3954  // Do the folding
3955  return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3956  N0.getOperand(0), N0.getOperand(1), N1);
3957  }
3958  else if (N0.getOpcode() == ISD::FMUL) {
3959  if (VT == MVT::f32 || VT == MVT::f64) {
3960  const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3961  &DAG.getTargetLoweringInfo());
3962  if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3963  return SDValue();
3964 
3965  // For floating point:
3966  // Do the fusion only when the mul has less than 5 uses and all
3967  // are add.
3968  // The heuristic is that if a use is not an add, then that use
3969  // cannot be fused into fma, therefore mul is still needed anyway.
3970  // If there are more than 4 uses, even if they are all add, fusing
3971  // them will increase register pressue.
3972  //
3973  int numUses = 0;
3974  int nonAddCount = 0;
3975  for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3976  UE = N0.getNode()->use_end();
3977  UI != UE; ++UI) {
3978  numUses++;
3979  SDNode *User = *UI;
3980  if (User->getOpcode() != ISD::FADD)
3981  ++nonAddCount;
3982  }
3983  if (numUses >= 5)
3984  return SDValue();
3985  if (nonAddCount) {
3986  int orderNo = N->getIROrder();
3987  int orderNo2 = N0.getNode()->getIROrder();
3988  // simple heuristics here for considering potential register
3989  // pressure, the logics here is that the differnce are used
3990  // to measure the distance between def and use, the longer distance
3991  // more likely cause register pressure.
3992  if (orderNo - orderNo2 < 500)
3993  return SDValue();
3994 
3995  // Now, check if at least one of the FMUL's operands is live beyond the node N,
3996  // which guarantees that the FMA will not increase register pressure at node N.
3997  bool opIsLive = false;
3998  const SDNode *left = N0.getOperand(0).getNode();
3999  const SDNode *right = N0.getOperand(1).getNode();
4000 
4001  if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
4002  opIsLive = true;
4003 
4004  if (!opIsLive)
4005  for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
4006  SDNode *User = *UI;
4007  int orderNo3 = User->getIROrder();
4008  if (orderNo3 > orderNo) {
4009  opIsLive = true;
4010  break;
4011  }
4012  }
4013 
4014  if (!opIsLive)
4015  for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
4016  SDNode *User = *UI;
4017  int orderNo3 = User->getIROrder();
4018  if (orderNo3 > orderNo) {
4019  opIsLive = true;
4020  break;
4021  }
4022  }
4023 
4024  if (!opIsLive)
4025  return SDValue();
4026  }
4027 
4028  return DAG.getNode(ISD::FMA, SDLoc(N), VT,
4029  N0.getOperand(0), N0.getOperand(1), N1);
4030  }
4031  }
4032 
4033  return SDValue();
4034 }
4035 
4036 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4037 ///
4040  const NVPTXSubtarget &Subtarget,
4041  CodeGenOpt::Level OptLevel) {
4042  SDValue N0 = N->getOperand(0);
4043  SDValue N1 = N->getOperand(1);
4044 
4045  // First try with the default operand order.
4046  if (SDValue Result =
4047  PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel))
4048  return Result;
4049 
4050  // If that didn't work, try again with the operands commuted.
4051  return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
4052 }
4053 
4056  // The type legalizer turns a vector load of i8 values into a zextload to i16
4057  // registers, optionally ANY_EXTENDs it (if target type is integer),
4058  // and ANDs off the high 8 bits. Since we turn this load into a
4059  // target-specific DAG node, the DAG combiner fails to eliminate these AND
4060  // nodes. Do that here.
4061  SDValue Val = N->getOperand(0);
4062  SDValue Mask = N->getOperand(1);
4063 
4064  if (isa<ConstantSDNode>(Val)) {
4065  std::swap(Val, Mask);
4066  }
4067 
4068  SDValue AExt;
4069  // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4070  if (Val.getOpcode() == ISD::ANY_EXTEND) {
4071  AExt = Val;
4072  Val = Val->getOperand(0);
4073  }
4074 
4075  if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4076  Val = Val->getOperand(0);
4077  }
4078 
4079  if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4080  Val->getOpcode() == NVPTXISD::LoadV4) {
4082  if (!MaskCnst) {
4083  // Not an AND with a constant
4084  return SDValue();
4085  }
4086 
4087  uint64_t MaskVal = MaskCnst->getZExtValue();
4088  if (MaskVal != 0xff) {
4089  // Not an AND that chops off top 8 bits
4090  return SDValue();
4091  }
4092 
4093  MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4094  if (!Mem) {
4095  // Not a MemSDNode?!?
4096  return SDValue();
4097  }
4098 
4099  EVT MemVT = Mem->getMemoryVT();
4100  if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4101  // We only handle the i8 case
4102  return SDValue();
4103  }
4104 
4105  unsigned ExtType =
4106  cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4107  getZExtValue();
4108  if (ExtType == ISD::SEXTLOAD) {
4109  // If for some reason the load is a sextload, the and is needed to zero
4110  // out the high 8 bits
4111  return SDValue();
4112  }
4113 
4114  bool AddTo = false;
4115  if (AExt.getNode() != nullptr) {
4116  // Re-insert the ext as a zext.
4117  Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4118  AExt.getValueType(), Val);
4119  AddTo = true;
4120  }
4121 
4122  // If we get here, the AND is unnecessary. Just replace it with the load
4123  DCI.CombineTo(N, Val, AddTo);
4124  }
4125 
4126  return SDValue();
4127 }
4128 
4131  CodeGenOpt::Level OptLevel) {
4132  assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4133 
4134  // Don't do anything at less than -O2.
4135  if (OptLevel < CodeGenOpt::Default)
4136  return SDValue();
4137 
4138  SelectionDAG &DAG = DCI.DAG;
4139  SDLoc DL(N);
4140  EVT VT = N->getValueType(0);
4141  bool IsSigned = N->getOpcode() == ISD::SREM;
4142  unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
4143 
4144  const SDValue &Num = N->getOperand(0);
4145  const SDValue &Den = N->getOperand(1);
4146 
4147  for (const SDNode *U : Num->uses()) {
4148  if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4149  U->getOperand(1) == Den) {
4150  // Num % Den -> Num - (Num / Den) * Den
4151  return DAG.getNode(ISD::SUB, DL, VT, Num,
4152  DAG.getNode(ISD::MUL, DL, VT,
4153  DAG.getNode(DivOpc, DL, VT, Num, Den),
4154  Den));
4155  }
4156  }
4157  return SDValue();
4158 }
4159 
4161  Signed = 0,
4164 };
4165 
4166 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4167 /// that can be demoted to \p OptSize bits without loss of information. The
4168 /// signedness of the operand, if determinable, is placed in \p S.
4170  unsigned OptSize,
4171  OperandSignedness &S) {
4172  S = Unknown;
4173 
4174  if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4176  EVT OrigVT = Op.getOperand(0).getValueType();
4177  if (OrigVT.getSizeInBits() <= OptSize) {
4178  S = Signed;
4179  return true;
4180  }
4181  } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4182  EVT OrigVT = Op.getOperand(0).getValueType();
4183  if (OrigVT.getSizeInBits() <= OptSize) {
4184  S = Unsigned;
4185  return true;
4186  }
4187  }
4188 
4189  return false;
4190 }
4191 
4192 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4193 /// be demoted to \p OptSize bits without loss of information. If the operands
4194 /// contain a constant, it should appear as the RHS operand. The signedness of
4195 /// the operands is placed in \p IsSigned.
4197  unsigned OptSize,
4198  bool &IsSigned) {
4199  OperandSignedness LHSSign;
4200 
4201  // The LHS operand must be a demotable op
4202  if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4203  return false;
4204 
4205  // We should have been able to determine the signedness from the LHS
4206  if (LHSSign == Unknown)
4207  return false;
4208 
4209  IsSigned = (LHSSign == Signed);
4210 
4211  // The RHS can be a demotable op or a constant
4212  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4213  const APInt &Val = CI->getAPIntValue();
4214  if (LHSSign == Unsigned) {
4215  return Val.isIntN(OptSize);
4216  } else {
4217  return Val.isSignedIntN(OptSize);
4218  }
4219  } else {
4220  OperandSignedness RHSSign;
4221  if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4222  return false;
4223 
4224  return LHSSign == RHSSign;
4225  }
4226 }
4227 
4228 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4229 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4230 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4231 /// amount.
4234  EVT MulType = N->getValueType(0);
4235  if (MulType != MVT::i32 && MulType != MVT::i64) {
4236  return SDValue();
4237  }
4238 
4239  SDLoc DL(N);
4240  unsigned OptSize = MulType.getSizeInBits() >> 1;
4241  SDValue LHS = N->getOperand(0);
4242  SDValue RHS = N->getOperand(1);
4243 
4244  // Canonicalize the multiply so the constant (if any) is on the right
4245  if (N->getOpcode() == ISD::MUL) {
4246  if (isa<ConstantSDNode>(LHS)) {
4247  std::swap(LHS, RHS);
4248  }
4249  }
4250 
4251  // If we have a SHL, determine the actual multiply amount
4252  if (N->getOpcode() == ISD::SHL) {
4253  ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4254  if (!ShlRHS) {
4255  return SDValue();
4256  }
4257 
4258  APInt ShiftAmt = ShlRHS->getAPIntValue();
4259  unsigned BitWidth = MulType.getSizeInBits();
4260  if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4261  APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4262  RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4263  } else {
4264  return SDValue();
4265  }
4266  }
4267 
4268  bool Signed;
4269  // Verify that our operands are demotable
4270  if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4271  return SDValue();
4272  }
4273 
4274  EVT DemotedVT;
4275  if (MulType == MVT::i32) {
4276  DemotedVT = MVT::i16;
4277  } else {
4278  DemotedVT = MVT::i32;
4279  }
4280 
4281  // Truncate the operands to the correct size. Note that these are just for
4282  // type consistency and will (likely) be eliminated in later phases.
4283  SDValue TruncLHS =
4284  DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4285  SDValue TruncRHS =
4286  DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4287 
4288  unsigned Opc;
4289  if (Signed) {
4291  } else {
4293  }
4294 
4295  return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4296 }
4297 
4298 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4301  CodeGenOpt::Level OptLevel) {
4302  if (OptLevel > 0) {
4303  // Try mul.wide combining at OptLevel > 0
4304  if (SDValue Ret = TryMULWIDECombine(N, DCI))
4305  return Ret;
4306  }
4307 
4308  return SDValue();
4309 }
4310 
4311 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4314  CodeGenOpt::Level OptLevel) {
4315  if (OptLevel > 0) {
4316  // Try mul.wide combining at OptLevel > 0
4317  if (SDValue Ret = TryMULWIDECombine(N, DCI))
4318  return Ret;
4319  }
4320 
4321  return SDValue();
4322 }
4323 
4326  EVT CCType = N->getValueType(0);
4327  SDValue A = N->getOperand(0);
4328  SDValue B = N->getOperand(1);
4329 
4330  if (CCType != MVT::v2i1 || A.getValueType() != MVT::v2f16)
4331  return SDValue();
4332 
4333  SDLoc DL(N);
4334  // setp.f16x2 returns two scalar predicates, which we need to
4335  // convert back to v2i1. The returned result will be scalarized by
4336  // the legalizer, but the comparison will remain a single vector
4337  // instruction.
4338  SDValue CCNode = DCI.DAG.getNode(NVPTXISD::SETP_F16X2, DL,
4339  DCI.DAG.getVTList(MVT::i1, MVT::i1),
4340  {A, B, N->getOperand(2)});
4341  return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
4342  CCNode.getValue(1));
4343 }
4344 
4345 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4346  DAGCombinerInfo &DCI) const {
4348  switch (N->getOpcode()) {
4349  default: break;
4350  case ISD::ADD:
4351  case ISD::FADD:
4352  return PerformADDCombine(N, DCI, STI, OptLevel);
4353  case ISD::MUL:
4354  return PerformMULCombine(N, DCI, OptLevel);
4355  case ISD::SHL:
4356  return PerformSHLCombine(N, DCI, OptLevel);
4357  case ISD::AND:
4358  return PerformANDCombine(N, DCI);
4359  case ISD::UREM:
4360  case ISD::SREM:
4361  return PerformREMCombine(N, DCI, OptLevel);
4362  case ISD::SETCC:
4363  return PerformSETCCCombine(N, DCI);
4364  }
4365  return SDValue();
4366 }
4367 
4368 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4371  EVT ResVT = N->getValueType(0);
4372  SDLoc DL(N);
4373 
4374  assert(ResVT.isVector() && "Vector load must have vector type");
4375 
4376  // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4377  // legal. We can (and should) split that into 2 loads of <2 x double> here
4378  // but I'm leaving that as a TODO for now.
4379  assert(ResVT.isSimple() && "Can only handle simple types");
4380  switch (ResVT.getSimpleVT().SimpleTy) {
4381  default:
4382  return;
4383  case MVT::v2i8:
4384  case MVT::v2i16:
4385  case MVT::v2i32:
4386  case MVT::v2i64:
4387  case MVT::v2f16:
4388  case MVT::v2f32:
4389  case MVT::v2f64:
4390  case MVT::v4i8:
4391  case MVT::v4i16:
4392  case MVT::v4i32:
4393  case MVT::v4f16:
4394  case MVT::v4f32:
4395  case MVT::v8f16: // <4 x f16x2>
4396  // This is a "native" vector type
4397  break;
4398  }
4399 
4400  LoadSDNode *LD = cast<LoadSDNode>(N);
4401 
4402  unsigned Align = LD->getAlignment();
4403  auto &TD = DAG.getDataLayout();
4404  unsigned PrefAlign =
4405  TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4406  if (Align < PrefAlign) {
4407  // This load is not sufficiently aligned, so bail out and let this vector
4408  // load be scalarized. Note that we may still be able to emit smaller
4409  // vector loads. For example, if we are loading a <4 x float> with an
4410  // alignment of 8, this check will fail but the legalizer will try again
4411  // with 2 x <2 x float>, which will succeed with an alignment of 8.
4412  return;
4413  }
4414 
4415  EVT EltVT = ResVT.getVectorElementType();
4416  unsigned NumElts = ResVT.getVectorNumElements();
4417 
4418  // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4419  // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4420  // loaded type to i16 and propagate the "real" type as the memory type.
4421  bool NeedTrunc = false;
4422  if (EltVT.getSizeInBits() < 16) {
4423  EltVT = MVT::i16;
4424  NeedTrunc = true;
4425  }
4426 
4427  unsigned Opcode = 0;
4428  SDVTList LdResVTs;
4429  bool LoadF16x2 = false;
4430 
4431  switch (NumElts) {
4432  default:
4433  return;
4434  case 2:
4435  Opcode = NVPTXISD::LoadV2;
4436  LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4437  break;
4438  case 4: {
4439  Opcode = NVPTXISD::LoadV4;
4440  EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4441  LdResVTs = DAG.getVTList(ListVTs);
4442  break;
4443  }
4444  case 8: {
4445  // v8f16 is a special case. PTX doesn't have ld.v8.f16
4446  // instruction. Instead, we split the vector into v2f16 chunks and
4447  // load them with ld.v4.b32.
4448  assert(EltVT == MVT::f16 && "Unsupported v8 vector type.");
4449  LoadF16x2 = true;
4450  Opcode = NVPTXISD::LoadV4;
4451  EVT ListVTs[] = {MVT::v2f16, MVT::v2f16, MVT::v2f16, MVT::v2f16,
4452  MVT::Other};
4453  LdResVTs = DAG.getVTList(ListVTs);
4454  break;
4455  }
4456  }
4457 
4458  // Copy regular operands
4459  SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4460 
4461  // The select routine does not have access to the LoadSDNode instance, so
4462  // pass along the extension information
4463  OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4464 
4465  SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4466  LD->getMemoryVT(),
4467  LD->getMemOperand());
4468 
4469  SmallVector<SDValue, 8> ScalarRes;
4470  if (LoadF16x2) {
4471  // Split v2f16 subvectors back into individual elements.
4472  NumElts /= 2;
4473  for (unsigned i = 0; i < NumElts; ++i) {
4474  SDValue SubVector = NewLD.getValue(i);
4475  SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4476  DAG.getIntPtrConstant(0, DL));
4477  SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector,
4478  DAG.getIntPtrConstant(1, DL));
4479  ScalarRes.push_back(E0);
4480  ScalarRes.push_back(E1);
4481  }
4482  } else {
4483  for (unsigned i = 0; i < NumElts; ++i) {
4484  SDValue Res = NewLD.getValue(i);
4485  if (NeedTrunc)
4486  Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4487  ScalarRes.push_back(Res);
4488  }
4489  }
4490 
4491  SDValue LoadChain = NewLD.getValue(NumElts);
4492 
4493  SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes);
4494 
4495  Results.push_back(BuildVec);
4496  Results.push_back(LoadChain);
4497 }
4498 
4501  SDValue Chain = N->getOperand(0);
4502  SDValue Intrin = N->getOperand(1);
4503  SDLoc DL(N);
4504 
4505  // Get the intrinsic ID
4506  unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4507  switch (IntrinNo) {
4508  default:
4509  return;
4510  case Intrinsic::nvvm_ldg_global_i:
4511  case Intrinsic::nvvm_ldg_global_f:
4512  case Intrinsic::nvvm_ldg_global_p:
4513  case Intrinsic::nvvm_ldu_global_i:
4514  case Intrinsic::nvvm_ldu_global_f:
4515  case Intrinsic::nvvm_ldu_global_p: {
4516  EVT ResVT = N->getValueType(0);
4517 
4518  if (ResVT.isVector()) {
4519  // Vector LDG/LDU
4520 
4521  unsigned NumElts = ResVT.getVectorNumElements();
4522  EVT EltVT = ResVT.getVectorElementType();
4523 
4524  // Since LDU/LDG are target nodes, we cannot rely on DAG type
4525  // legalization.
4526  // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4527  // loaded type to i16 and propagate the "real" type as the memory type.
4528  bool NeedTrunc = false;
4529  if (EltVT.getSizeInBits() < 16) {
4530  EltVT = MVT::i16;
4531  NeedTrunc = true;
4532  }
4533 
4534  unsigned Opcode = 0;
4535  SDVTList LdResVTs;
4536 
4537  switch (NumElts) {
4538  default:
4539  return;
4540  case 2:
4541  switch (IntrinNo) {
4542  default:
4543  return;
4544  case Intrinsic::nvvm_ldg_global_i:
4545  case Intrinsic::nvvm_ldg_global_f:
4546  case Intrinsic::nvvm_ldg_global_p:
4547  Opcode = NVPTXISD::LDGV2;
4548  break;
4549  case Intrinsic::nvvm_ldu_global_i:
4550  case Intrinsic::nvvm_ldu_global_f:
4551  case Intrinsic::nvvm_ldu_global_p:
4552  Opcode = NVPTXISD::LDUV2;
4553  break;
4554  }
4555  LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4556  break;
4557  case 4: {
4558  switch (IntrinNo) {
4559  default:
4560  return;
4561  case Intrinsic::nvvm_ldg_global_i:
4562  case Intrinsic::nvvm_ldg_global_f:
4563  case Intrinsic::nvvm_ldg_global_p:
4564  Opcode = NVPTXISD::LDGV4;
4565  break;
4566  case Intrinsic::nvvm_ldu_global_i:
4567  case Intrinsic::nvvm_ldu_global_f:
4568  case Intrinsic::nvvm_ldu_global_p:
4569  Opcode = NVPTXISD::LDUV4;
4570  break;
4571  }
4572  EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4573  LdResVTs = DAG.getVTList(ListVTs);
4574  break;
4575  }
4576  }
4577 
4578  SmallVector<SDValue, 8> OtherOps;
4579 
4580  // Copy regular operands
4581 
4582  OtherOps.push_back(Chain); // Chain
4583  // Skip operand 1 (intrinsic ID)
4584  // Others
4585  OtherOps.append(N->op_begin() + 2, N->op_end());
4586 
4587  MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4588 
4589  SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4590  MemSD->getMemoryVT(),
4591  MemSD->getMemOperand());
4592 
4593  SmallVector<SDValue, 4> ScalarRes;
4594 
4595  for (unsigned i = 0; i < NumElts; ++i) {
4596  SDValue Res = NewLD.getValue(i);
4597  if (NeedTrunc)
4598  Res =
4599  DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4600  ScalarRes.push_back(Res);
4601  }
4602 
4603  SDValue LoadChain = NewLD.getValue(NumElts);
4604 
4605  SDValue BuildVec =
4606  DAG.getBuildVector(ResVT, DL, ScalarRes);
4607 
4608  Results.push_back(BuildVec);
4609  Results.push_back(LoadChain);
4610  } else {
4611  // i8 LDG/LDU
4612  assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4613  "Custom handling of non-i8 ldu/ldg?");
4614 
4615  // Just copy all operands as-is
4616  SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4617 
4618  // Force output to i16
4619  SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4620 
4621  MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4622 
4623  // We make sure the memory type is i8, which will be used during isel
4624  // to select the proper instruction.
4625  SDValue NewLD =
4626  DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4627  MVT::i8, MemSD->getMemOperand());
4628 
4629  Results.