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AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
30 private:
31  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32  /// legalized from a smaller type VT. Need to match pre-legalized type because
33  /// the generic legalization inserts the add/sub between the select and
34  /// compare.
35  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
39  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
40 
41 protected:
44 
47  /// \brief Split a vector store into multiple scalar stores.
48  /// \returns The resulting chain.
49 
50  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
55 
57  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
58  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
59  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
61  double Log2BaseInverted) const;
62 
64 
65  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69 
70  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
74 
76 
77 protected:
78  bool shouldCombineMemoryType(EVT VT) const;
83 
85  unsigned Opc, SDValue LHS,
86  uint32_t ValLo, uint32_t ValHi) const;
95  SDValue RHS, DAGCombinerInfo &DCI) const;
99 
101 
103  SelectionDAG &DAG) const;
104 
105  /// Return 64-bit value Op as two 32-bit integers.
106  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
107  SelectionDAG &DAG) const;
108  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
109  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
110 
111  /// \brief Split a vector load into 2 loads of half the vector.
113 
114  /// \brief Split a vector store into 2 stores of half the vector.
116 
117  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
118  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
119  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
120  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
121  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
124  const SmallVectorImpl<ISD::InputArg> &Ins) const;
125 public:
126  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
127 
128  bool mayIgnoreSignedZero(SDValue Op) const {
129  if (getTargetMachine().Options.NoSignedZerosFPMath)
130  return true;
131 
132  const auto Flags = Op.getNode()->getFlags();
133  if (Flags.isDefined())
134  return Flags.hasNoSignedZeros();
135 
136  return false;
137  }
138 
139  static bool allUsesHaveSourceMods(const SDNode *N,
140  unsigned CostThreshold = 4);
141  bool isFAbsFree(EVT VT) const override;
142  bool isFNegFree(EVT VT) const override;
143  bool isTruncateFree(EVT Src, EVT Dest) const override;
144  bool isTruncateFree(Type *Src, Type *Dest) const override;
145 
146  bool isZExtFree(Type *Src, Type *Dest) const override;
147  bool isZExtFree(EVT Src, EVT Dest) const override;
148  bool isZExtFree(SDValue Val, EVT VT2) const override;
149  bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
150 
151  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
152 
153  MVT getVectorIdxTy(const DataLayout &) const override;
154  bool isSelectSupported(SelectSupportKind) const override;
155 
156  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
157  bool ShouldShrinkFPConstant(EVT VT) const override;
159  ISD::LoadExtType ExtType,
160  EVT ExtVT) const override;
161 
162  bool isLoadBitCastBeneficial(EVT, EVT) const final;
163 
165  unsigned NumElem,
166  unsigned AS) const override;
167  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
168  bool isCheapToSpeculateCttz() const override;
169  bool isCheapToSpeculateCtlz() const override;
170 
171  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
172  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
173 
174  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
176  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
177  SelectionDAG &DAG) const override;
178 
180  SelectionDAG &DAG,
181  MachineFrameInfo &MFI,
182  int ClobberedFI) const;
183 
185  SmallVectorImpl<SDValue> &InVals,
186  StringRef Reason) const;
188  SmallVectorImpl<SDValue> &InVals) const override;
189 
191  SelectionDAG &DAG) const;
192 
193  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
194  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
195  void ReplaceNodeResults(SDNode * N,
197  SelectionDAG &DAG) const override;
198 
199  SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
200  SDValue RHS, SDValue True, SDValue False,
201  SDValue CC, DAGCombinerInfo &DCI) const;
202 
203  const char* getTargetNodeName(unsigned Opcode) const override;
204 
205  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
206  // for AMDGPU.
207  // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
208  // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
209  // MergeConsecutiveStores() before Instruction Selection for all targets.
210  // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
211  // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
212  // re-merges, etc. ) to warrant turning it off for now.
213  bool mergeStoresAfterLegalization() const override { return false; }
214 
215  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
216  return true;
217  }
219  int &RefinementSteps, bool &UseOneConstNR,
220  bool Reciprocal) const override;
221  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
222  int &RefinementSteps) const override;
223 
225  SelectionDAG &DAG) const = 0;
226 
227  /// \brief Determine which of the bits specified in \p Mask are known to be
228  /// either zero or one and return them in the \p KnownZero and \p KnownOne
229  /// bitsets.
231  KnownBits &Known,
232  const APInt &DemandedElts,
233  const SelectionDAG &DAG,
234  unsigned Depth = 0) const override;
235 
236  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
237  const SelectionDAG &DAG,
238  unsigned Depth = 0) const override;
239 
240  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
241  /// MachineFunction.
242  ///
243  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
244  /// a copy from the register.
246  const TargetRegisterClass *RC,
247  unsigned Reg, EVT VT,
248  const SDLoc &SL,
249  bool RawReg = false) const;
251  const TargetRegisterClass *RC,
252  unsigned Reg, EVT VT) const {
253  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
254  }
255 
256  // Returns the raw live in register rather than a copy from it.
258  const TargetRegisterClass *RC,
259  unsigned Reg, EVT VT) const {
260  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
261  }
262 
263  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
264  /// slot rather than passed in a register.
266  EVT VT,
267  const SDLoc &SL,
268  int64_t Offset) const;
269 
271  const SDLoc &SL,
272  SDValue Chain,
273  SDValue StackPtr,
274  SDValue ArgVal,
275  int64_t Offset) const;
276 
278  const TargetRegisterClass *RC,
279  EVT VT, const SDLoc &SL,
280  const ArgDescriptor &Arg) const;
281 
286  };
287 
288  /// \brief Helper function that returns the byte offset of the given
289  /// type of implicit parameter.
291  const ImplicitParameter Param) const;
292 
294  return AMDGPUASI;
295  }
296 
297  MVT getFenceOperandTy(const DataLayout &DL) const override {
298  return MVT::i32;
299  }
300 };
301 
302 namespace AMDGPUISD {
303 
304 enum NodeType : unsigned {
305  // AMDIL ISD Opcodes
307  UMUL, // 32bit unsigned multiplication
309  // End AMDIL ISD Opcodes
310 
311  // Function call.
315 
316  // Masked control flow nodes.
317  IF,
320 
321  // A uniform kernel return that terminates the wavefront.
323 
324  // Return to a shader part's epilog code.
326 
327  // Return with values from a non-entry function.
329 
332 
333  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
334  /// modifier behavior with dx10_enable.
336 
337  // This is SETCC with the full mask result which is used for a compare with a
338  // result bit per item in the wavefront.
341  // FP ops with input and output chain.
344 
345  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
346  // Denormals handled on some parts.
364  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
365  // treated as an illegal operation.
367  TRIG_PREOP, // 1 ULP max error for f64
368 
369  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
370  // For f64, max error 2^29 ULP, handles denormals.
382  BFE_U32, // Extract range of bits with zero extension to 32-bits.
383  BFE_I32, // Extract range of bits with sign extension to 32-bits.
384  BFI, // (src0 & src1) | (~src0 & src2)
385  BFM, // Insert a range of bits into a 32-bit word.
386  FFBH_U32, // ctlz with -1 if input is zero.
388  FFBL_B32, // cttz with -1 if input is zero.
400  EXPORT, // exp on SI+
401  EXPORT_DONE, // exp on SI+ with done bit set
410 
411  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
416 
417  // Convert two float 32 numbers into a single register holding two packed f16
418  // with round to zero.
424 
425  // Same as the standard node, except the high bits of the resulting integer
426  // are known 0.
428 
429  // Wrapper around fp16 results that are known to zero the high bits.
431 
432  /// This node is for VLIW targets and it is used to represent a vector
433  /// that is stored in consecutive registers with the same channel.
434  /// For example:
435  /// |X |Y|Z|W|
436  /// T0|v.x| | | |
437  /// T1|v.y| | | |
438  /// T2|v.z| | | |
439  /// T3|v.w| | | |
441  /// Pointer to the start of the shader's constant data.
488 
489  // Basic sample.
500 
501  // Sample with comparison.
512 
513  // Sample with offsets.
524 
525  // Sample with comparison and offsets.
536 
537  // Basic gather4.
544 
545  // Gather4 with comparison.
552 
553  // Gather4 with offsets.
560 
561  // Gather4 with comparison and offsets.
568 
570 };
571 
572 
573 } // End namespace AMDGPUISD
574 
575 } // End namespace llvm
576 
577 #endif
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
bool hasNoSignedZeros() const
bool shouldCombineMemoryType(EVT VT) const
LLVMContext & Context
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG&#39;s MachineFunction.
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag, double Log2BaseInverted) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
CLAMP value between 0.0 and 1.0.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool mayIgnoreSignedZero(SDValue Op) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
Pointer to the start of the shader&#39;s constant data.
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:214
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:449
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const AMDGPUSubtarget * Subtarget
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:893
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Extended Value Type.
Definition: ValueTypes.h:34
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
const AMDGPUAS & AS
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:843
SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const
Represents one node in the SelectionDAG.
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
amdgpu Simplify well known AMD library false Value Value * Arg
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue StackPtr, SDValue ArgVal, int64_t Offset) const
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This file describes how to lower LLVM code to machine code.
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isSelectSupported(SelectSupportKind) const override