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AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition of the TargetLowering class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 
18 #include "AMDGPU.h"
21 
22 namespace llvm {
23 
24 class AMDGPUMachineFunction;
25 class AMDGPUSubtarget;
26 struct ArgDescriptor;
27 
29 private:
30  const AMDGPUSubtarget *Subtarget;
31 
32  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
33  /// legalized from a smaller type VT. Need to match pre-legalized type because
34  /// the generic legalization inserts the add/sub between the select and
35  /// compare.
36  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
37 
38 public:
39  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
41 
42 protected:
45  /// Split a vector store into multiple scalar stores.
46  /// \returns The resulting chain.
47 
48  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 
55  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
56  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
57  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
59  double Log2BaseInverted) const;
60  SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
61 
63 
64  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
68 
69  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
73 
75 
76 protected:
77  bool shouldCombineMemoryType(EVT VT) const;
81 
83  unsigned Opc, SDValue LHS,
84  uint32_t ValLo, uint32_t ValHi) const;
94  SDValue RHS, DAGCombinerInfo &DCI) const;
96 
97  bool isConstantCostlierToNegate(SDValue N) const;
101 
103 
105  SelectionDAG &DAG) const;
106 
107  /// Return 64-bit value Op as two 32-bit integers.
108  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
109  SelectionDAG &DAG) const;
110  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
111  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
112 
113  /// Split a vector load into 2 loads of half the vector.
115 
116  /// Split a vector store into 2 stores of half the vector.
118 
119  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
120  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
121  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
122  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
123  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
125 
127  CCState &State,
128  const SmallVectorImpl<ISD::InputArg> &Ins) const;
129 
130 public:
131  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
132 
133  bool mayIgnoreSignedZero(SDValue Op) const {
134  if (getTargetMachine().Options.NoSignedZerosFPMath)
135  return true;
136 
137  const auto Flags = Op.getNode()->getFlags();
138  if (Flags.isDefined())
139  return Flags.hasNoSignedZeros();
140 
141  return false;
142  }
143 
144  static inline SDValue stripBitcast(SDValue Val) {
145  return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
146  }
147 
148  static bool allUsesHaveSourceMods(const SDNode *N,
149  unsigned CostThreshold = 4);
150  bool isFAbsFree(EVT VT) const override;
151  bool isFNegFree(EVT VT) const override;
152  bool isTruncateFree(EVT Src, EVT Dest) const override;
153  bool isTruncateFree(Type *Src, Type *Dest) const override;
154 
155  bool isZExtFree(Type *Src, Type *Dest) const override;
156  bool isZExtFree(EVT Src, EVT Dest) const override;
157  bool isZExtFree(SDValue Val, EVT VT2) const override;
158 
159  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
160 
161  MVT getVectorIdxTy(const DataLayout &) const override;
162  bool isSelectSupported(SelectSupportKind) const override;
163 
164  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
165  bool ShouldShrinkFPConstant(EVT VT) const override;
168  EVT ExtVT) const override;
169 
170  bool isLoadBitCastBeneficial(EVT, EVT) const final;
171 
173  unsigned NumElem,
174  unsigned AS) const override;
175  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
176  bool isCheapToSpeculateCttz() const override;
177  bool isCheapToSpeculateCtlz() const override;
178 
179  bool isSDNodeAlwaysUniform(const SDNode *N) const override;
180  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
181  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
182 
183  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
185  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
186  SelectionDAG &DAG) const override;
187 
189  SelectionDAG &DAG,
190  MachineFrameInfo &MFI,
191  int ClobberedFI) const;
192 
194  SmallVectorImpl<SDValue> &InVals,
195  StringRef Reason) const;
197  SmallVectorImpl<SDValue> &InVals) const override;
198 
200  SelectionDAG &DAG) const;
201 
202  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
203  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
204  void ReplaceNodeResults(SDNode * N,
205  SmallVectorImpl<SDValue> &Results,
206  SelectionDAG &DAG) const override;
207 
208  SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
209  SDValue RHS, SDValue True, SDValue False,
210  SDValue CC, DAGCombinerInfo &DCI) const;
211 
212  const char* getTargetNodeName(unsigned Opcode) const override;
213 
214  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
215  // AMDGPU. Commit r319036,
216  // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
217  // turned on MergeConsecutiveStores() before Instruction Selection for all
218  // targets. Enough AMDGPU compiles go into an infinite loop (
219  // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
220  // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
221  // now.
222  bool mergeStoresAfterLegalization() const override { return false; }
223 
224  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
225  return true;
226  }
228  int &RefinementSteps, bool &UseOneConstNR,
229  bool Reciprocal) const override;
230  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
231  int &RefinementSteps) const override;
232 
234  SelectionDAG &DAG) const = 0;
235 
236  /// Determine which of the bits specified in \p Mask are known to be
237  /// either zero or one and return them in the \p KnownZero and \p KnownOne
238  /// bitsets.
240  KnownBits &Known,
241  const APInt &DemandedElts,
242  const SelectionDAG &DAG,
243  unsigned Depth = 0) const override;
244 
245  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
246  const SelectionDAG &DAG,
247  unsigned Depth = 0) const override;
248 
250  const SelectionDAG &DAG,
251  bool SNaN = false,
252  unsigned Depth = 0) const override;
253 
254  /// Helper function that adds Reg to the LiveIn list of the DAG's
255  /// MachineFunction.
256  ///
257  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
258  /// a copy from the register.
260  const TargetRegisterClass *RC,
261  unsigned Reg, EVT VT,
262  const SDLoc &SL,
263  bool RawReg = false) const;
265  const TargetRegisterClass *RC,
266  unsigned Reg, EVT VT) const {
267  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
268  }
269 
270  // Returns the raw live in register rather than a copy from it.
272  const TargetRegisterClass *RC,
273  unsigned Reg, EVT VT) const {
274  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
275  }
276 
277  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
278  /// slot rather than passed in a register.
280  EVT VT,
281  const SDLoc &SL,
282  int64_t Offset) const;
283 
285  const SDLoc &SL,
286  SDValue Chain,
287  SDValue ArgVal,
288  int64_t Offset) const;
289 
291  const TargetRegisterClass *RC,
292  EVT VT, const SDLoc &SL,
293  const ArgDescriptor &Arg) const;
294 
299  };
300 
301  /// Helper function that returns the byte offset of the given
302  /// type of implicit parameter.
304  const ImplicitParameter Param) const;
305 
306  MVT getFenceOperandTy(const DataLayout &DL) const override {
307  return MVT::i32;
308  }
309 
311 };
312 
313 namespace AMDGPUISD {
314 
315 enum NodeType : unsigned {
316  // AMDIL ISD Opcodes
318  UMUL, // 32bit unsigned multiplication
320  // End AMDIL ISD Opcodes
321 
322  // Function call.
326 
327  // Masked control flow nodes.
328  IF,
331 
332  // A uniform kernel return that terminates the wavefront.
334 
335  // Return to a shader part's epilog code.
337 
338  // Return with values from a non-entry function.
340 
343 
344  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
345  /// modifier behavior with dx10_enable.
347 
348  // This is SETCC with the full mask result which is used for a compare with a
349  // result bit per item in the wavefront.
352  // FP ops with input and output chain.
355 
356  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
357  // Denormals handled on some parts.
362 
377  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
378  // treated as an illegal operation.
380  TRIG_PREOP, // 1 ULP max error for f64
381 
382  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
383  // For f64, max error 2^29 ULP, handles denormals.
396  BFE_U32, // Extract range of bits with zero extension to 32-bits.
397  BFE_I32, // Extract range of bits with sign extension to 32-bits.
398  BFI, // (src0 & src1) | (~src0 & src2)
399  BFM, // Insert a range of bits into a 32-bit word.
400  FFBH_U32, // ctlz with -1 if input is zero.
402  FFBL_B32, // cttz with -1 if input is zero.
415  EXPORT, // exp on SI+
416  EXPORT_DONE, // exp on SI+ with done bit set
425 
426  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
431 
432  // Convert two float 32 numbers into a single register holding two packed f16
433  // with round to zero.
439 
440  // Same as the standard node, except the high bits of the resulting integer
441  // are known 0.
443 
444  // Wrapper around fp16 results that are known to zero the high bits.
446 
447  /// This node is for VLIW targets and it is used to represent a vector
448  /// that is stored in consecutive registers with the same channel.
449  /// For example:
450  /// |X |Y|Z|W|
451  /// T0|v.x| | | |
452  /// T1|v.y| | | |
453  /// T2|v.z| | | |
454  /// T3|v.w| | | |
456  /// Pointer to the start of the shader's constant data.
503 
505 };
506 
507 
508 } // End namespace AMDGPUISD
509 
510 } // End namespace llvm
511 
512 #endif
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:883
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
bool hasNoSignedZeros() const
bool shouldCombineMemoryType(EVT VT) const
LLVMContext & Context
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG&#39;s MachineFunction.
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Return true if it is profitable to reduce a load to a smaller type.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
unsigned Reg
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDNodeFlags getFlags() const
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
CLAMP value between 0.0 and 1.0.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool mayIgnoreSignedZero(SDValue Op) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
Pointer to the start of the shader&#39;s constant data.
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:459
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:940
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Extended Value Type.
Definition: ValueTypes.h:33
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
bool isConstantCostlierToNegate(SDValue N) const
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:890
Represents one node in the SelectionDAG.
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
static SDValue stripBitcast(SDValue Val)
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
#define AMDGPUSubtarget
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
const SDValue & getOperand(unsigned i) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This file describes how to lower LLVM code to machine code.
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isSelectSupported(SelectSupportKind) const override