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AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition of the TargetLowering class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 
18 #include "AMDGPU.h"
21 
22 namespace llvm {
23 
24 class AMDGPUMachineFunction;
25 class AMDGPUSubtarget;
26 struct ArgDescriptor;
27 
29 private:
30  const AMDGPUSubtarget *Subtarget;
31 
32  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
33  /// legalized from a smaller type VT. Need to match pre-legalized type because
34  /// the generic legalization inserts the add/sub between the select and
35  /// compare.
36  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
37 
38 public:
39  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
41 
42 protected:
45  /// Split a vector store into multiple scalar stores.
46  /// \returns The resulting chain.
47 
48  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 
55  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
56  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
57  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
59  double Log2BaseInverted) const;
60  SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
61 
63 
64  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
68 
69  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
73 
75 
76 protected:
77  bool shouldCombineMemoryType(EVT VT) const;
81 
83  unsigned Opc, SDValue LHS,
84  uint32_t ValLo, uint32_t ValHi) const;
94  SDValue RHS, DAGCombinerInfo &DCI) const;
96 
97  bool isConstantCostlierToNegate(SDValue N) const;
101 
103 
105  SelectionDAG &DAG) const;
106 
107  /// Return 64-bit value Op as two 32-bit integers.
108  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
109  SelectionDAG &DAG) const;
110  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
111  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
112 
113  /// Split a vector type into two parts. The first part is a power of two
114  /// vector. The second part is whatever is left over, and is a scalar if it
115  /// would otherwise be a 1-vector.
116  std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
117 
118  /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
119  /// scalar.
120  std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
121  const EVT &LoVT, const EVT &HighVT,
122  SelectionDAG &DAG) const;
123 
124  /// Split a vector load into 2 loads of half the vector.
126 
127  /// Widen a vector load from vec3 to vec4.
129 
130  /// Split a vector store into 2 stores of half the vector.
132 
133  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
134  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
135  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
136  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
137  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
139 
141  CCState &State,
142  const SmallVectorImpl<ISD::InputArg> &Ins) const;
143 
144 public:
145  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
146 
147  bool mayIgnoreSignedZero(SDValue Op) const {
148  if (getTargetMachine().Options.NoSignedZerosFPMath)
149  return true;
150 
151  const auto Flags = Op.getNode()->getFlags();
152  if (Flags.isDefined())
153  return Flags.hasNoSignedZeros();
154 
155  return false;
156  }
157 
158  static inline SDValue stripBitcast(SDValue Val) {
159  return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
160  }
161 
162  static bool allUsesHaveSourceMods(const SDNode *N,
163  unsigned CostThreshold = 4);
164  bool isFAbsFree(EVT VT) const override;
165  bool isFNegFree(EVT VT) const override;
166  bool isTruncateFree(EVT Src, EVT Dest) const override;
167  bool isTruncateFree(Type *Src, Type *Dest) const override;
168 
169  bool isZExtFree(Type *Src, Type *Dest) const override;
170  bool isZExtFree(EVT Src, EVT Dest) const override;
171  bool isZExtFree(SDValue Val, EVT VT2) const override;
172 
173  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
174 
175  MVT getVectorIdxTy(const DataLayout &) const override;
176  bool isSelectSupported(SelectSupportKind) const override;
177 
178  bool isFPImmLegal(const APFloat &Imm, EVT VT,
179  bool ForCodeSize) const override;
180  bool ShouldShrinkFPConstant(EVT VT) const override;
183  EVT ExtVT) const override;
184 
185  bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
186  const MachineMemOperand &MMO) const final;
187 
189  unsigned NumElem,
190  unsigned AS) const override;
191  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
192  bool isCheapToSpeculateCttz() const override;
193  bool isCheapToSpeculateCtlz() const override;
194 
195  bool isSDNodeAlwaysUniform(const SDNode *N) const override;
196  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
197  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
198 
199  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
201  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
202  SelectionDAG &DAG) const override;
203 
205  SelectionDAG &DAG,
206  MachineFrameInfo &MFI,
207  int ClobberedFI) const;
208 
210  SmallVectorImpl<SDValue> &InVals,
211  StringRef Reason) const;
213  SmallVectorImpl<SDValue> &InVals) const override;
214 
216  SelectionDAG &DAG) const;
217 
218  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
219  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
220  void ReplaceNodeResults(SDNode * N,
221  SmallVectorImpl<SDValue> &Results,
222  SelectionDAG &DAG) const override;
223 
224  SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
225  SDValue RHS, SDValue True, SDValue False,
226  SDValue CC, DAGCombinerInfo &DCI) const;
227 
228  const char* getTargetNodeName(unsigned Opcode) const override;
229 
230  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
231  // AMDGPU. Commit r319036,
232  // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
233  // turned on MergeConsecutiveStores() before Instruction Selection for all
234  // targets. Enough AMDGPU compiles go into an infinite loop (
235  // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
236  // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
237  // now.
238  bool mergeStoresAfterLegalization(EVT) const override { return false; }
239 
240  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
241  return true;
242  }
244  int &RefinementSteps, bool &UseOneConstNR,
245  bool Reciprocal) const override;
246  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
247  int &RefinementSteps) const override;
248 
250  SelectionDAG &DAG) const = 0;
251 
252  /// Determine which of the bits specified in \p Mask are known to be
253  /// either zero or one and return them in the \p KnownZero and \p KnownOne
254  /// bitsets.
256  KnownBits &Known,
257  const APInt &DemandedElts,
258  const SelectionDAG &DAG,
259  unsigned Depth = 0) const override;
260 
261  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
262  const SelectionDAG &DAG,
263  unsigned Depth = 0) const override;
264 
266  const SelectionDAG &DAG,
267  bool SNaN = false,
268  unsigned Depth = 0) const override;
269 
270  /// Helper function that adds Reg to the LiveIn list of the DAG's
271  /// MachineFunction.
272  ///
273  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
274  /// a copy from the register.
276  const TargetRegisterClass *RC,
277  unsigned Reg, EVT VT,
278  const SDLoc &SL,
279  bool RawReg = false) const;
281  const TargetRegisterClass *RC,
282  unsigned Reg, EVT VT) const {
283  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
284  }
285 
286  // Returns the raw live in register rather than a copy from it.
288  const TargetRegisterClass *RC,
289  unsigned Reg, EVT VT) const {
290  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
291  }
292 
293  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
294  /// slot rather than passed in a register.
296  EVT VT,
297  const SDLoc &SL,
298  int64_t Offset) const;
299 
301  const SDLoc &SL,
302  SDValue Chain,
303  SDValue ArgVal,
304  int64_t Offset) const;
305 
307  const TargetRegisterClass *RC,
308  EVT VT, const SDLoc &SL,
309  const ArgDescriptor &Arg) const;
310 
315  };
316 
317  /// Helper function that returns the byte offset of the given
318  /// type of implicit parameter.
320  const ImplicitParameter Param) const;
321 
322  MVT getFenceOperandTy(const DataLayout &DL) const override {
323  return MVT::i32;
324  }
325 
327 
328  bool SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N,
329  SDValue Addr, SDValue &VAddr, SDValue &Offset,
330  SDValue &SLC) const;
331 };
332 
333 namespace AMDGPUISD {
334 
335 enum NodeType : unsigned {
336  // AMDIL ISD Opcodes
338  UMUL, // 32bit unsigned multiplication
340  // End AMDIL ISD Opcodes
341 
342  // Function call.
346 
347  // Masked control flow nodes.
348  IF,
351 
352  // A uniform kernel return that terminates the wavefront.
354 
355  // Return to a shader part's epilog code.
357 
358  // Return with values from a non-entry function.
360 
363 
364  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
365  /// modifier behavior with dx10_enable.
367 
368  // This is SETCC with the full mask result which is used for a compare with a
369  // result bit per item in the wavefront.
372 
374 
375  // FP ops with input and output chain.
378 
379  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
380  // Denormals handled on some parts.
385 
400  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
401  // treated as an illegal operation.
403  TRIG_PREOP, // 1 ULP max error for f64
404 
405  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
406  // For f64, max error 2^29 ULP, handles denormals.
419  BFE_U32, // Extract range of bits with zero extension to 32-bits.
420  BFE_I32, // Extract range of bits with sign extension to 32-bits.
421  BFI, // (src0 & src1) | (~src0 & src2)
422  BFM, // Insert a range of bits into a 32-bit word.
423  FFBH_U32, // ctlz with -1 if input is zero.
425  FFBL_B32, // cttz with -1 if input is zero.
438  EXPORT, // exp on SI+
439  EXPORT_DONE, // exp on SI+ with done bit set
448 
449  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
454 
455  // Convert two float 32 numbers into a single register holding two packed f16
456  // with round to zero.
462 
463  // Same as the standard node, except the high bits of the resulting integer
464  // are known 0.
466 
467  // Wrapper around fp16 results that are known to zero the high bits.
469 
470  /// This node is for VLIW targets and it is used to represent a vector
471  /// that is stored in consecutive registers with the same channel.
472  /// For example:
473  /// |X |Y|Z|W|
474  /// T0|v.x| | | |
475  /// T1|v.y| | | |
476  /// T2|v.z| | | |
477  /// T3|v.w| | | |
479  /// Pointer to the start of the shader's constant data.
502 
545 
547 };
548 
549 
550 } // End namespace AMDGPUISD
551 
552 } // End namespace llvm
553 
554 #endif
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
bool hasNoSignedZeros() const
bool shouldCombineMemoryType(EVT VT) const
LLVMContext & Context
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG&#39;s MachineFunction.
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Return true if it is profitable to reduce a load to a smaller type.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
unsigned Reg
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDNodeFlags getFlags() const
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:693
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
CLAMP value between 0.0 and 1.0.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
std::pair< EVT, EVT > getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const
Split a vector type into two parts.
bool mayIgnoreSignedZero(SDValue Op) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
std::pair< SDValue, SDValue > splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const
Split a vector value into two parts of types LoVT and HiVT.
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
A description of a memory reference used in the backend.
Pointer to the start of the shader&#39;s constant data.
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:473
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:987
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
Extended Value Type.
Definition: ValueTypes.h:33
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
bool isConstantCostlierToNegate(SDValue N) const
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
SDValue WidenVectorLoad(SDValue Op, SelectionDAG &DAG) const
Widen a vector load from vec3 to vec4.
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:920
Represents one node in the SelectionDAG.
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:69
bool SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset, SDValue &SLC) const
bool mergeStoresAfterLegalization(EVT) const override
Allow store merging for the specified type after legalization in addition to before legalization...
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
static SDValue stripBitcast(SDValue Val)
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
#define AMDGPUSubtarget
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
const SDValue & getOperand(unsigned i) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This file describes how to lower LLVM code to machine code.
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isSelectSupported(SelectSupportKind) const override