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AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
30 private:
31  const AMDGPUSubtarget *Subtarget;
32 
33  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
34  /// legalized from a smaller type VT. Need to match pre-legalized type because
35  /// the generic legalization inserts the add/sub between the select and
36  /// compare.
37  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
38 
39 public:
40  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
41  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
42 
43 protected:
46  /// Split a vector store into multiple scalar stores.
47  /// \returns The resulting chain.
48 
49  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
54 
56  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
57  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
58  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
60  double Log2BaseInverted) const;
61  SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
62 
64 
65  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69 
70  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
74 
76 
77 protected:
78  bool shouldCombineMemoryType(EVT VT) const;
82 
84  unsigned Opc, SDValue LHS,
85  uint32_t ValLo, uint32_t ValHi) const;
95  SDValue RHS, DAGCombinerInfo &DCI) const;
97 
98  bool isConstantCostlierToNegate(SDValue N) const;
102 
104 
106  SelectionDAG &DAG) const;
107 
108  /// Return 64-bit value Op as two 32-bit integers.
109  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
110  SelectionDAG &DAG) const;
111  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
112  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
113 
114  /// Split a vector load into 2 loads of half the vector.
116 
117  /// Split a vector store into 2 stores of half the vector.
119 
120  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
121  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
122  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
123  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
124  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
126 
128  CCState &State,
129  const SmallVectorImpl<ISD::InputArg> &Ins) const;
130 
131 public:
132  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
133 
134  bool mayIgnoreSignedZero(SDValue Op) const {
135  if (getTargetMachine().Options.NoSignedZerosFPMath)
136  return true;
137 
138  const auto Flags = Op.getNode()->getFlags();
139  if (Flags.isDefined())
140  return Flags.hasNoSignedZeros();
141 
142  return false;
143  }
144 
145  static inline SDValue stripBitcast(SDValue Val) {
146  return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
147  }
148 
149  static bool allUsesHaveSourceMods(const SDNode *N,
150  unsigned CostThreshold = 4);
151  bool isFAbsFree(EVT VT) const override;
152  bool isFNegFree(EVT VT) const override;
153  bool isTruncateFree(EVT Src, EVT Dest) const override;
154  bool isTruncateFree(Type *Src, Type *Dest) const override;
155 
156  bool isZExtFree(Type *Src, Type *Dest) const override;
157  bool isZExtFree(EVT Src, EVT Dest) const override;
158  bool isZExtFree(SDValue Val, EVT VT2) const override;
159 
160  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
161 
162  MVT getVectorIdxTy(const DataLayout &) const override;
163  bool isSelectSupported(SelectSupportKind) const override;
164 
165  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
166  bool ShouldShrinkFPConstant(EVT VT) const override;
169  EVT ExtVT) const override;
170 
171  bool isLoadBitCastBeneficial(EVT, EVT) const final;
172 
174  unsigned NumElem,
175  unsigned AS) const override;
176  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
177  bool isCheapToSpeculateCttz() const override;
178  bool isCheapToSpeculateCtlz() const override;
179 
180  bool isSDNodeAlwaysUniform(const SDNode *N) const override;
181  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
182  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
183 
184  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
186  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
187  SelectionDAG &DAG) const override;
188 
190  SelectionDAG &DAG,
191  MachineFrameInfo &MFI,
192  int ClobberedFI) const;
193 
195  SmallVectorImpl<SDValue> &InVals,
196  StringRef Reason) const;
198  SmallVectorImpl<SDValue> &InVals) const override;
199 
201  SelectionDAG &DAG) const;
202 
203  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
204  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
205  void ReplaceNodeResults(SDNode * N,
206  SmallVectorImpl<SDValue> &Results,
207  SelectionDAG &DAG) const override;
208 
209  SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
210  SDValue RHS, SDValue True, SDValue False,
211  SDValue CC, DAGCombinerInfo &DCI) const;
212 
213  const char* getTargetNodeName(unsigned Opcode) const override;
214 
215  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
216  // for AMDGPU.
217  // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
218  // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
219  // MergeConsecutiveStores() before Instruction Selection for all targets.
220  // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
221  // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
222  // re-merges, etc. ) to warrant turning it off for now.
223  bool mergeStoresAfterLegalization() const override { return false; }
224 
225  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
226  return true;
227  }
229  int &RefinementSteps, bool &UseOneConstNR,
230  bool Reciprocal) const override;
231  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
232  int &RefinementSteps) const override;
233 
235  SelectionDAG &DAG) const = 0;
236 
237  /// Determine which of the bits specified in \p Mask are known to be
238  /// either zero or one and return them in the \p KnownZero and \p KnownOne
239  /// bitsets.
241  KnownBits &Known,
242  const APInt &DemandedElts,
243  const SelectionDAG &DAG,
244  unsigned Depth = 0) const override;
245 
246  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
247  const SelectionDAG &DAG,
248  unsigned Depth = 0) const override;
249 
251  const SelectionDAG &DAG,
252  bool SNaN = false,
253  unsigned Depth = 0) const override;
254 
255  /// Helper function that adds Reg to the LiveIn list of the DAG's
256  /// MachineFunction.
257  ///
258  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
259  /// a copy from the register.
261  const TargetRegisterClass *RC,
262  unsigned Reg, EVT VT,
263  const SDLoc &SL,
264  bool RawReg = false) const;
266  const TargetRegisterClass *RC,
267  unsigned Reg, EVT VT) const {
268  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
269  }
270 
271  // Returns the raw live in register rather than a copy from it.
273  const TargetRegisterClass *RC,
274  unsigned Reg, EVT VT) const {
275  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
276  }
277 
278  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
279  /// slot rather than passed in a register.
281  EVT VT,
282  const SDLoc &SL,
283  int64_t Offset) const;
284 
286  const SDLoc &SL,
287  SDValue Chain,
288  SDValue ArgVal,
289  int64_t Offset) const;
290 
292  const TargetRegisterClass *RC,
293  EVT VT, const SDLoc &SL,
294  const ArgDescriptor &Arg) const;
295 
300  };
301 
302  /// Helper function that returns the byte offset of the given
303  /// type of implicit parameter.
305  const ImplicitParameter Param) const;
306 
307  MVT getFenceOperandTy(const DataLayout &DL) const override {
308  return MVT::i32;
309  }
310 };
311 
312 namespace AMDGPUISD {
313 
314 enum NodeType : unsigned {
315  // AMDIL ISD Opcodes
317  UMUL, // 32bit unsigned multiplication
319  // End AMDIL ISD Opcodes
320 
321  // Function call.
325 
326  // Masked control flow nodes.
327  IF,
330 
331  // A uniform kernel return that terminates the wavefront.
333 
334  // Return to a shader part's epilog code.
336 
337  // Return with values from a non-entry function.
339 
342 
343  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
344  /// modifier behavior with dx10_enable.
346 
347  // This is SETCC with the full mask result which is used for a compare with a
348  // result bit per item in the wavefront.
351  // FP ops with input and output chain.
354 
355  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
356  // Denormals handled on some parts.
375  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
376  // treated as an illegal operation.
378  TRIG_PREOP, // 1 ULP max error for f64
379 
380  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
381  // For f64, max error 2^29 ULP, handles denormals.
394  BFE_U32, // Extract range of bits with zero extension to 32-bits.
395  BFE_I32, // Extract range of bits with sign extension to 32-bits.
396  BFI, // (src0 & src1) | (~src0 & src2)
397  BFM, // Insert a range of bits into a 32-bit word.
398  FFBH_U32, // ctlz with -1 if input is zero.
400  FFBL_B32, // cttz with -1 if input is zero.
413  EXPORT, // exp on SI+
414  EXPORT_DONE, // exp on SI+ with done bit set
423 
424  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
429 
430  // Convert two float 32 numbers into a single register holding two packed f16
431  // with round to zero.
437 
438  // Same as the standard node, except the high bits of the resulting integer
439  // are known 0.
441 
442  // Wrapper around fp16 results that are known to zero the high bits.
444 
445  /// This node is for VLIW targets and it is used to represent a vector
446  /// that is stored in consecutive registers with the same channel.
447  /// For example:
448  /// |X |Y|Z|W|
449  /// T0|v.x| | | |
450  /// T1|v.y| | | |
451  /// T2|v.z| | | |
452  /// T3|v.w| | | |
454  /// Pointer to the start of the shader's constant data.
498 
500 };
501 
502 
503 } // End namespace AMDGPUISD
504 
505 } // End namespace llvm
506 
507 #endif
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:541
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:837
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
bool hasNoSignedZeros() const
bool shouldCombineMemoryType(EVT VT) const
LLVMContext & Context
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG&#39;s MachineFunction.
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
unsigned Reg
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
CLAMP value between 0.0 and 1.0.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool mayIgnoreSignedZero(SDValue Op) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
Pointer to the start of the shader&#39;s constant data.
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:894
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Extended Value Type.
Definition: ValueTypes.h:34
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
bool isConstantCostlierToNegate(SDValue N) const
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:844
Represents one node in the SelectionDAG.
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:70
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
amdgpu Simplify well known AMD library false Value Value * Arg
static SDValue stripBitcast(SDValue Val)
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
#define AMDGPUSubtarget
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
const SDValue & getOperand(unsigned i) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This file describes how to lower LLVM code to machine code.
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isSelectSupported(SelectSupportKind) const override