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AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
30 private:
31  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32  /// legalized from a smaller type VT. Need to match pre-legalized type because
33  /// the generic legalization inserts the add/sub between the select and
34  /// compare.
35  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
39  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
40 
41 protected:
44 
47  /// Split a vector store into multiple scalar stores.
48  /// \returns The resulting chain.
49 
50  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
55 
57  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
58  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
59  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
61  double Log2BaseInverted) const;
62 
64 
65  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69 
70  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
74 
76 
77 protected:
78  bool shouldCombineMemoryType(EVT VT) const;
82 
84  unsigned Opc, SDValue LHS,
85  uint32_t ValLo, uint32_t ValHi) const;
95  SDValue RHS, DAGCombinerInfo &DCI) const;
99 
101 
103  SelectionDAG &DAG) const;
104 
105  /// Return 64-bit value Op as two 32-bit integers.
106  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
107  SelectionDAG &DAG) const;
108  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
109  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
110 
111  /// Split a vector load into 2 loads of half the vector.
113 
114  /// Split a vector store into 2 stores of half the vector.
116 
117  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
118  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
119  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
120  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
121  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
124  const SmallVectorImpl<ISD::InputArg> &Ins) const;
125 public:
126  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
127 
128  bool mayIgnoreSignedZero(SDValue Op) const {
129  if (getTargetMachine().Options.NoSignedZerosFPMath)
130  return true;
131 
132  const auto Flags = Op.getNode()->getFlags();
133  if (Flags.isDefined())
134  return Flags.hasNoSignedZeros();
135 
136  return false;
137  }
138 
139  static inline SDValue stripBitcast(SDValue Val) {
140  return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
141  }
142 
143  static bool allUsesHaveSourceMods(const SDNode *N,
144  unsigned CostThreshold = 4);
145  bool isFAbsFree(EVT VT) const override;
146  bool isFNegFree(EVT VT) const override;
147  bool isTruncateFree(EVT Src, EVT Dest) const override;
148  bool isTruncateFree(Type *Src, Type *Dest) const override;
149 
150  bool isZExtFree(Type *Src, Type *Dest) const override;
151  bool isZExtFree(EVT Src, EVT Dest) const override;
152  bool isZExtFree(SDValue Val, EVT VT2) const override;
153 
154  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
155 
156  MVT getVectorIdxTy(const DataLayout &) const override;
157  bool isSelectSupported(SelectSupportKind) const override;
158 
159  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
160  bool ShouldShrinkFPConstant(EVT VT) const override;
162  ISD::LoadExtType ExtType,
163  EVT ExtVT) const override;
164 
165  bool isLoadBitCastBeneficial(EVT, EVT) const final;
166 
168  unsigned NumElem,
169  unsigned AS) const override;
170  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
171  bool isCheapToSpeculateCttz() const override;
172  bool isCheapToSpeculateCtlz() const override;
173 
174  bool isSDNodeAlwaysUniform(const SDNode *N) const override;
175  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
176  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
177 
178  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
180  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
181  SelectionDAG &DAG) const override;
182 
184  SelectionDAG &DAG,
185  MachineFrameInfo &MFI,
186  int ClobberedFI) const;
187 
189  SmallVectorImpl<SDValue> &InVals,
190  StringRef Reason) const;
192  SmallVectorImpl<SDValue> &InVals) const override;
193 
195  SelectionDAG &DAG) const;
196 
197  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
198  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
199  void ReplaceNodeResults(SDNode * N,
201  SelectionDAG &DAG) const override;
202 
203  SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
204  SDValue RHS, SDValue True, SDValue False,
205  SDValue CC, DAGCombinerInfo &DCI) const;
206 
207  const char* getTargetNodeName(unsigned Opcode) const override;
208 
209  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
210  // for AMDGPU.
211  // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
212  // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
213  // MergeConsecutiveStores() before Instruction Selection for all targets.
214  // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
215  // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
216  // re-merges, etc. ) to warrant turning it off for now.
217  bool mergeStoresAfterLegalization() const override { return false; }
218 
219  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
220  return true;
221  }
223  int &RefinementSteps, bool &UseOneConstNR,
224  bool Reciprocal) const override;
225  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
226  int &RefinementSteps) const override;
227 
229  SelectionDAG &DAG) const = 0;
230 
231  /// Determine which of the bits specified in \p Mask are known to be
232  /// either zero or one and return them in the \p KnownZero and \p KnownOne
233  /// bitsets.
235  KnownBits &Known,
236  const APInt &DemandedElts,
237  const SelectionDAG &DAG,
238  unsigned Depth = 0) const override;
239 
240  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
241  const SelectionDAG &DAG,
242  unsigned Depth = 0) const override;
243 
244  /// Helper function that adds Reg to the LiveIn list of the DAG's
245  /// MachineFunction.
246  ///
247  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
248  /// a copy from the register.
250  const TargetRegisterClass *RC,
251  unsigned Reg, EVT VT,
252  const SDLoc &SL,
253  bool RawReg = false) const;
255  const TargetRegisterClass *RC,
256  unsigned Reg, EVT VT) const {
257  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
258  }
259 
260  // Returns the raw live in register rather than a copy from it.
262  const TargetRegisterClass *RC,
263  unsigned Reg, EVT VT) const {
264  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
265  }
266 
267  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
268  /// slot rather than passed in a register.
270  EVT VT,
271  const SDLoc &SL,
272  int64_t Offset) const;
273 
275  const SDLoc &SL,
276  SDValue Chain,
277  SDValue StackPtr,
278  SDValue ArgVal,
279  int64_t Offset) const;
280 
282  const TargetRegisterClass *RC,
283  EVT VT, const SDLoc &SL,
284  const ArgDescriptor &Arg) const;
285 
290  };
291 
292  /// Helper function that returns the byte offset of the given
293  /// type of implicit parameter.
295  const ImplicitParameter Param) const;
296 
298  return AMDGPUASI;
299  }
300 
301  MVT getFenceOperandTy(const DataLayout &DL) const override {
302  return MVT::i32;
303  }
304 };
305 
306 namespace AMDGPUISD {
307 
308 enum NodeType : unsigned {
309  // AMDIL ISD Opcodes
311  UMUL, // 32bit unsigned multiplication
313  // End AMDIL ISD Opcodes
314 
315  // Function call.
319 
320  // Masked control flow nodes.
321  IF,
324 
325  // A uniform kernel return that terminates the wavefront.
327 
328  // Return to a shader part's epilog code.
330 
331  // Return with values from a non-entry function.
333 
336 
337  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
338  /// modifier behavior with dx10_enable.
340 
341  // This is SETCC with the full mask result which is used for a compare with a
342  // result bit per item in the wavefront.
345  // FP ops with input and output chain.
348 
349  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
350  // Denormals handled on some parts.
368  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
369  // treated as an illegal operation.
371  TRIG_PREOP, // 1 ULP max error for f64
372 
373  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
374  // For f64, max error 2^29 ULP, handles denormals.
386  BFE_U32, // Extract range of bits with zero extension to 32-bits.
387  BFE_I32, // Extract range of bits with sign extension to 32-bits.
388  BFI, // (src0 & src1) | (~src0 & src2)
389  BFM, // Insert a range of bits into a 32-bit word.
390  FFBH_U32, // ctlz with -1 if input is zero.
392  FFBL_B32, // cttz with -1 if input is zero.
405  EXPORT, // exp on SI+
406  EXPORT_DONE, // exp on SI+ with done bit set
415 
416  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
421 
422  // Convert two float 32 numbers into a single register holding two packed f16
423  // with round to zero.
429 
430  // Same as the standard node, except the high bits of the resulting integer
431  // are known 0.
433 
434  // Wrapper around fp16 results that are known to zero the high bits.
436 
437  /// This node is for VLIW targets and it is used to represent a vector
438  /// that is stored in consecutive registers with the same channel.
439  /// For example:
440  /// |X |Y|Z|W|
441  /// T0|v.x| | | |
442  /// T1|v.y| | | |
443  /// T2|v.z| | | |
444  /// T3|v.w| | | |
446  /// Pointer to the start of the shader's constant data.
493 
494  // Basic sample.
505 
506  // Sample with comparison.
517 
518  // Sample with offsets.
529 
530  // Sample with comparison and offsets.
541 
542  // Basic gather4.
549 
550  // Gather4 with comparison.
557 
558  // Gather4 with offsets.
565 
566  // Gather4 with comparison and offsets.
573 
575 };
576 
577 
578 } // End namespace AMDGPUISD
579 
580 } // End namespace llvm
581 
582 #endif
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:539
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:829
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
bool hasNoSignedZeros() const
bool shouldCombineMemoryType(EVT VT) const
LLVMContext & Context
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG&#39;s MachineFunction.
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag, double Log2BaseInverted) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
bool mergeStoresAfterLegalization() const override
Allow store merging after legalization in addition to before legalization.
unsigned Reg
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
CLAMP value between 0.0 and 1.0.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool mayIgnoreSignedZero(SDValue Op) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
Pointer to the start of the shader&#39;s constant data.
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:220
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn&#39;t be replaced with X*RSQRT(X).
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const AMDGPUSubtarget * Subtarget
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:886
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Extended Value Type.
Definition: ValueTypes.h:34
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
const AMDGPUAS & AS
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:836
Represents one node in the SelectionDAG.
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
amdgpu Simplify well known AMD library false Value Value * Arg
static SDValue stripBitcast(SDValue Val)
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it&#39;s profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue StackPtr, SDValue ArgVal, int64_t Offset) const
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
const SDValue & getOperand(unsigned i) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This file describes how to lower LLVM code to machine code.
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isSelectSupported(SelectSupportKind) const override