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AMDGPUISelLowering.cpp
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1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This is the parent TargetLowering class for hardware code gen
12 /// targets.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
17 #define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
18 #define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
19 
20 #include "AMDGPUISelLowering.h"
21 #include "AMDGPU.h"
22 #include "AMDGPUCallLowering.h"
23 #include "AMDGPUFrameLowering.h"
24 #include "AMDGPUIntrinsicInfo.h"
25 #include "AMDGPURegisterInfo.h"
26 #include "AMDGPUSubtarget.h"
27 #include "AMDGPUTargetMachine.h"
28 #include "Utils/AMDGPUBaseInfo.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
33 #include "llvm/CodeGen/Analysis.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DiagnosticInfo.h"
41 #include "llvm/Support/KnownBits.h"
42 using namespace llvm;
43 
44 static bool allocateCCRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
45  CCValAssign::LocInfo LocInfo,
46  ISD::ArgFlagsTy ArgFlags, CCState &State,
47  const TargetRegisterClass *RC,
48  unsigned NumRegs) {
49  ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs);
50  unsigned RegResult = State.AllocateReg(RegList);
51  if (RegResult == AMDGPU::NoRegister)
52  return false;
53 
54  State.addLoc(CCValAssign::getReg(ValNo, ValVT, RegResult, LocVT, LocInfo));
55  return true;
56 }
57 
58 static bool allocateSGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
59  CCValAssign::LocInfo LocInfo,
60  ISD::ArgFlagsTy ArgFlags, CCState &State) {
61  switch (LocVT.SimpleTy) {
62  case MVT::i64:
63  case MVT::f64:
64  case MVT::v2i32:
65  case MVT::v2f32:
66  case MVT::v4i16:
67  case MVT::v4f16: {
68  // Up to SGPR0-SGPR39
69  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
70  &AMDGPU::SGPR_64RegClass, 20);
71  }
72  default:
73  return false;
74  }
75 }
76 
77 // Allocate up to VGPR31.
78 //
79 // TODO: Since there are no VGPR alignent requirements would it be better to
80 // split into individual scalar registers?
81 static bool allocateVGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
82  CCValAssign::LocInfo LocInfo,
83  ISD::ArgFlagsTy ArgFlags, CCState &State) {
84  switch (LocVT.SimpleTy) {
85  case MVT::i64:
86  case MVT::f64:
87  case MVT::v2i32:
88  case MVT::v2f32:
89  case MVT::v4i16:
90  case MVT::v4f16: {
91  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
92  &AMDGPU::VReg_64RegClass, 31);
93  }
94  case MVT::v4i32:
95  case MVT::v4f32:
96  case MVT::v2i64:
97  case MVT::v2f64: {
98  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
99  &AMDGPU::VReg_128RegClass, 29);
100  }
101  case MVT::v8i32:
102  case MVT::v8f32: {
103  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
104  &AMDGPU::VReg_256RegClass, 25);
105 
106  }
107  case MVT::v16i32:
108  case MVT::v16f32: {
109  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
110  &AMDGPU::VReg_512RegClass, 17);
111 
112  }
113  default:
114  return false;
115  }
116 }
117 
118 #include "AMDGPUGenCallingConv.inc"
119 
120 // Find a larger type to do a load / store of a vector with.
122  unsigned StoreSize = VT.getStoreSizeInBits();
123  if (StoreSize <= 32)
124  return EVT::getIntegerVT(Ctx, StoreSize);
125 
126  assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
127  return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
128 }
129 
131  KnownBits Known;
132  EVT VT = Op.getValueType();
133  DAG.computeKnownBits(Op, Known);
134 
135  return VT.getSizeInBits() - Known.countMinLeadingZeros();
136 }
137 
139  EVT VT = Op.getValueType();
140 
141  // In order for this to be a signed 24-bit value, bit 23, must
142  // be a sign bit.
143  return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
144 }
145 
147  const AMDGPUSubtarget &STI)
148  : TargetLowering(TM), Subtarget(&STI) {
149  // Lower floating point store/load to integer store/load to reduce the number
150  // of patterns in tablegen.
153 
156 
159 
162 
165 
168 
171 
174 
177 
178  // There are no 64-bit extloads. These should be done as a 32-bit extload and
179  // an extension to 64-bit.
180  for (MVT VT : MVT::integer_valuetypes()) {
184  }
185 
186  for (MVT VT : MVT::integer_valuetypes()) {
187  if (VT == MVT::i64)
188  continue;
189 
194 
199 
204  }
205 
206  for (MVT VT : MVT::integer_vector_valuetypes()) {
219  }
220 
225 
230 
235 
238 
241 
244 
247 
250 
253 
256 
259 
262 
267 
272 
277 
280 
283 
286 
289 
290 
295 
298 
299  // This is totally unsupported, just custom lower to produce an error.
301 
302  // Library functions. These default to Expand, but we have instructions
303  // for them.
314 
317 
321 
322 
325 
328 
329  // Expand to fneg + fadd.
331 
342 
346 
347  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
348  for (MVT VT : ScalarIntVTs) {
349  // These should use [SU]DIVREM, so set them to expand
354 
355  // GPU does not have divrem function for signed or unsigned.
358 
359  // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
362 
366 
367  // AMDGPU uses ADDC/SUBC/ADDE/SUBE
372  }
373 
374  // The hardware supports 32-bit ROTR, but not ROTL.
376  setOperationAction(ISD::ROTL, MVT::i64, Expand);
377  setOperationAction(ISD::ROTR, MVT::i64, Expand);
378 
379  setOperationAction(ISD::MUL, MVT::i64, Expand);
387 
392 
393  setOperationAction(ISD::CTTZ, MVT::i64, Custom);
395  setOperationAction(ISD::CTLZ, MVT::i64, Custom);
397 
398  static const MVT::SimpleValueType VectorIntTypes[] = {
400  };
401 
402  for (MVT VT : VectorIntTypes) {
403  // Expand the following operations for the current type by default.
438  }
439 
440  static const MVT::SimpleValueType FloatVectorTypes[] = {
442  };
443 
444  for (MVT VT : FloatVectorTypes) {
475  }
476 
477  // This causes using an unrolled select operation rather than expansion with
478  // bit operations. This is in general better, but the alternative using BFI
479  // instructions may be better if the select sources are SGPRs.
482 
483  setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
484  AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
485 
486  // There are no libcalls of any kind.
487  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
488  setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
489 
492 
494  setJumpIsExpensive(true);
495 
496  // FIXME: This is only partially true. If we have to do vector compares, any
497  // SGPR pair can be a condition register. If we have a uniform condition, we
498  // are better off doing SALU operations, where there is only one SCC. For now,
499  // we don't have a way of knowing during instruction selection if a condition
500  // will be uniform and we always use vector compares. Assume we are using
501  // vector compares until that is fixed.
503 
505 
506  // We want to find all load dependencies for long chains of stores to enable
507  // merging into very wide vectors. The problem is with vectors with > 4
508  // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
509  // vectors are a legal type, even though we have to split the loads
510  // usually. When we can more precisely specify load legality per address
511  // space, we should be able to make FindBetterChain/MergeConsecutiveStores
512  // smarter so that they can figure out what to do in 2 iterations without all
513  // N > 4 stores on the same chain.
515 
516  // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
517  // about these during lowering.
518  MaxStoresPerMemcpy = 0xffffffff;
519  MaxStoresPerMemmove = 0xffffffff;
520  MaxStoresPerMemset = 0xffffffff;
521 
539 }
540 
541 //===----------------------------------------------------------------------===//
542 // Target Information
543 //===----------------------------------------------------------------------===//
544 
546 static bool fnegFoldsIntoOp(unsigned Opc) {
547  switch (Opc) {
548  case ISD::FADD:
549  case ISD::FSUB:
550  case ISD::FMUL:
551  case ISD::FMA:
552  case ISD::FMAD:
553  case ISD::FMINNUM:
554  case ISD::FMAXNUM:
555  case ISD::FMINNUM_IEEE:
556  case ISD::FMAXNUM_IEEE:
557  case ISD::FSIN:
558  case ISD::FTRUNC:
559  case ISD::FRINT:
560  case ISD::FNEARBYINT:
561  case ISD::FCANONICALIZE:
562  case AMDGPUISD::RCP:
565  case AMDGPUISD::SIN_HW:
569  case AMDGPUISD::FMED3:
570  return true;
571  default:
572  return false;
573  }
574 }
575 
576 /// \p returns true if the operation will definitely need to use a 64-bit
577 /// encoding, and thus will use a VOP3 encoding regardless of the source
578 /// modifiers.
580 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
581  return N->getNumOperands() > 2 || VT == MVT::f64;
582 }
583 
584 // Most FP instructions support source modifiers, but this could be refined
585 // slightly.
587 static bool hasSourceMods(const SDNode *N) {
588  if (isa<MemSDNode>(N))
589  return false;
590 
591  switch (N->getOpcode()) {
592  case ISD::CopyToReg:
593  case ISD::SELECT:
594  case ISD::FDIV:
595  case ISD::FREM:
596  case ISD::INLINEASM:
600 
601  // TODO: Should really be looking at the users of the bitcast. These are
602  // problematic because bitcasts are used to legalize all stores to integer
603  // types.
604  case ISD::BITCAST:
605  return false;
606  default:
607  return true;
608  }
609 }
610 
612  unsigned CostThreshold) {
613  // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
614  // it is truly free to use a source modifier in all cases. If there are
615  // multiple users but for each one will necessitate using VOP3, there will be
616  // a code size increase. Try to avoid increasing code size unless we know it
617  // will save on the instruction count.
618  unsigned NumMayIncreaseSize = 0;
619  MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
620 
621  // XXX - Should this limit number of uses to check?
622  for (const SDNode *U : N->uses()) {
623  if (!hasSourceMods(U))
624  return false;
625 
626  if (!opMustUseVOP3Encoding(U, VT)) {
627  if (++NumMayIncreaseSize > CostThreshold)
628  return false;
629  }
630  }
631 
632  return true;
633 }
634 
636  return MVT::i32;
637 }
638 
640  return true;
641 }
642 
643 // The backend supports 32 and 64 bit floating point immediates.
644 // FIXME: Why are we reporting vectors of FP immediates as legal?
645 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
646  EVT ScalarVT = VT.getScalarType();
647  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
648  (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
649 }
650 
651 // We don't want to shrink f64 / f32 constants.
653  EVT ScalarVT = VT.getScalarType();
654  return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
655 }
656 
658  ISD::LoadExtType ExtTy,
659  EVT NewVT) const {
660  // TODO: This may be worth removing. Check regression tests for diffs.
661  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
662  return false;
663 
664  unsigned NewSize = NewVT.getStoreSizeInBits();
665 
666  // If we are reducing to a 32-bit load, this is always better.
667  if (NewSize == 32)
668  return true;
669 
670  EVT OldVT = N->getValueType(0);
671  unsigned OldSize = OldVT.getStoreSizeInBits();
672 
673  MemSDNode *MN = cast<MemSDNode>(N);
674  unsigned AS = MN->getAddressSpace();
675  // Do not shrink an aligned scalar load to sub-dword.
676  // Scalar engine cannot do sub-dword loads.
677  if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
680  (isa<LoadSDNode>(N) &&
681  AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
683  return false;
684 
685  // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
686  // extloads, so doing one requires using a buffer_load. In cases where we
687  // still couldn't use a scalar load, using the wider load shouldn't really
688  // hurt anything.
689 
690  // If the old size already had to be an extload, there's no harm in continuing
691  // to reduce the width.
692  return (OldSize < 32);
693 }
694 
696  EVT CastTy) const {
697 
698  assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
699 
700  if (LoadTy.getScalarType() == MVT::i32)
701  return false;
702 
703  unsigned LScalarSize = LoadTy.getScalarSizeInBits();
704  unsigned CastScalarSize = CastTy.getScalarSizeInBits();
705 
706  return (LScalarSize < CastScalarSize) ||
707  (CastScalarSize >= 32);
708 }
709 
710 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
711 // profitable with the expansion for 64-bit since it's generally good to
712 // speculate things.
713 // FIXME: These should really have the size as a parameter.
715  return true;
716 }
717 
719  return true;
720 }
721 
723  switch (N->getOpcode()) {
724  default:
725  return false;
726  case ISD::EntryToken:
727  case ISD::TokenFactor:
728  return true;
730  {
731  unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
732  switch (IntrID) {
733  default:
734  return false;
735  case Intrinsic::amdgcn_readfirstlane:
736  case Intrinsic::amdgcn_readlane:
737  return true;
738  }
739  }
740  break;
741  case ISD::LOAD:
742  {
743  const LoadSDNode * L = dyn_cast<LoadSDNode>(N);
744  if (L->getMemOperand()->getAddrSpace()
746  return true;
747  return false;
748  }
749  break;
750  }
751 }
752 
753 //===---------------------------------------------------------------------===//
754 // Target Properties
755 //===---------------------------------------------------------------------===//
756 
758  assert(VT.isFloatingPoint());
759 
760  // Packed operations do not have a fabs modifier.
761  return VT == MVT::f32 || VT == MVT::f64 ||
762  (Subtarget->has16BitInsts() && VT == MVT::f16);
763 }
764 
766  assert(VT.isFloatingPoint());
767  return VT == MVT::f32 || VT == MVT::f64 ||
768  (Subtarget->has16BitInsts() && VT == MVT::f16) ||
769  (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
770 }
771 
773  unsigned NumElem,
774  unsigned AS) const {
775  return true;
776 }
777 
779  // There are few operations which truly have vector input operands. Any vector
780  // operation is going to involve operations on each component, and a
781  // build_vector will be a copy per element, so it always makes sense to use a
782  // build_vector input in place of the extracted element to avoid a copy into a
783  // super register.
784  //
785  // We should probably only do this if all users are extracts only, but this
786  // should be the common case.
787  return true;
788 }
789 
791  // Truncate is just accessing a subregister.
792 
793  unsigned SrcSize = Source.getSizeInBits();
794  unsigned DestSize = Dest.getSizeInBits();
795 
796  return DestSize < SrcSize && DestSize % 32 == 0 ;
797 }
798 
800  // Truncate is just accessing a subregister.
801 
802  unsigned SrcSize = Source->getScalarSizeInBits();
803  unsigned DestSize = Dest->getScalarSizeInBits();
804 
805  if (DestSize== 16 && Subtarget->has16BitInsts())
806  return SrcSize >= 32;
807 
808  return DestSize < SrcSize && DestSize % 32 == 0;
809 }
810 
811 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
812  unsigned SrcSize = Src->getScalarSizeInBits();
813  unsigned DestSize = Dest->getScalarSizeInBits();
814 
815  if (SrcSize == 16 && Subtarget->has16BitInsts())
816  return DestSize >= 32;
817 
818  return SrcSize == 32 && DestSize == 64;
819 }
820 
821 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
822  // Any register load of a 64-bit value really requires 2 32-bit moves. For all
823  // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
824  // this will enable reducing 64-bit operations the 32-bit, which is always
825  // good.
826 
827  if (Src == MVT::i16)
828  return Dest == MVT::i32 ||Dest == MVT::i64 ;
829 
830  return Src == MVT::i32 && Dest == MVT::i64;
831 }
832 
834  return isZExtFree(Val.getValueType(), VT2);
835 }
836 
838  // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
839  // limited number of native 64-bit operations. Shrinking an operation to fit
840  // in a single 32-bit register should always be helpful. As currently used,
841  // this is much less general than the name suggests, and is only used in
842  // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
843  // not profitable, and may actually be harmful.
844  return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
845 }
846 
847 //===---------------------------------------------------------------------===//
848 // TargetLowering Callbacks
849 //===---------------------------------------------------------------------===//
850 
852  bool IsVarArg) {
853  switch (CC) {
856  llvm_unreachable("kernels should not be handled here");
864  return CC_AMDGPU;
865  case CallingConv::C:
866  case CallingConv::Fast:
867  case CallingConv::Cold:
868  return CC_AMDGPU_Func;
869  default:
870  report_fatal_error("Unsupported calling convention.");
871  }
872 }
873 
875  bool IsVarArg) {
876  switch (CC) {
879  llvm_unreachable("kernels should not be handled here");
887  return RetCC_SI_Shader;
888  case CallingConv::C:
889  case CallingConv::Fast:
890  case CallingConv::Cold:
891  return RetCC_AMDGPU_Func;
892  default:
893  report_fatal_error("Unsupported calling convention.");
894  }
895 }
896 
897 /// The SelectionDAGBuilder will automatically promote function arguments
898 /// with illegal types. However, this does not work for the AMDGPU targets
899 /// since the function arguments are stored in memory as these illegal types.
900 /// In order to handle this properly we need to get the original types sizes
901 /// from the LLVM IR Function and fixup the ISD:InputArg values before
902 /// passing them to AnalyzeFormalArguments()
903 
904 /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
905 /// input values across multiple registers. Each item in the Ins array
906 /// represents a single value that will be stored in registers. Ins[x].VT is
907 /// the value type of the value that will be stored in the register, so
908 /// whatever SDNode we lower the argument to needs to be this type.
909 ///
910 /// In order to correctly lower the arguments we need to know the size of each
911 /// argument. Since Ins[x].VT gives us the size of the register that will
912 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
913 /// for the orignal function argument so that we can deduce the correct memory
914 /// type to use for Ins[x]. In most cases the correct memory type will be
915 /// Ins[x].ArgVT. However, this will not always be the case. If, for example,
916 /// we have a kernel argument of type v8i8, this argument will be split into
917 /// 8 parts and each part will be represented by its own item in the Ins array.
918 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
919 /// the argument before it was split. From this, we deduce that the memory type
920 /// for each individual part is i8. We pass the memory type as LocVT to the
921 /// calling convention analysis function and the register type (Ins[x].VT) as
922 /// the ValVT.
924  CCState &State,
925  const SmallVectorImpl<ISD::InputArg> &Ins) const {
926  const MachineFunction &MF = State.getMachineFunction();
927  const Function &Fn = MF.getFunction();
928  LLVMContext &Ctx = Fn.getParent()->getContext();
930  const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
932 
933  unsigned MaxAlign = 1;
934  uint64_t ExplicitArgOffset = 0;
935  const DataLayout &DL = Fn.getParent()->getDataLayout();
936 
937  unsigned InIndex = 0;
938 
939  for (const Argument &Arg : Fn.args()) {
940  Type *BaseArgTy = Arg.getType();
941  unsigned Align = DL.getABITypeAlignment(BaseArgTy);
942  MaxAlign = std::max(Align, MaxAlign);
943  unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
944 
945  uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
946  ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
947 
948  // We're basically throwing away everything passed into us and starting over
949  // to get accurate in-memory offsets. The "PartOffset" is completely useless
950  // to us as computed in Ins.
951  //
952  // We also need to figure out what type legalization is trying to do to get
953  // the correct memory offsets.
954 
955  SmallVector<EVT, 16> ValueVTs;
957  ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
958 
959  for (unsigned Value = 0, NumValues = ValueVTs.size();
960  Value != NumValues; ++Value) {
961  uint64_t BasePartOffset = Offsets[Value];
962 
963  EVT ArgVT = ValueVTs[Value];
964  EVT MemVT = ArgVT;
965  MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
966  unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
967 
968  if (NumRegs == 1) {
969  // This argument is not split, so the IR type is the memory type.
970  if (ArgVT.isExtended()) {
971  // We have an extended type, like i24, so we should just use the
972  // register type.
973  MemVT = RegisterVT;
974  } else {
975  MemVT = ArgVT;
976  }
977  } else if (ArgVT.isVector() && RegisterVT.isVector() &&
978  ArgVT.getScalarType() == RegisterVT.getScalarType()) {
979  assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
980  // We have a vector value which has been split into a vector with
981  // the same scalar type, but fewer elements. This should handle
982  // all the floating-point vector types.
983  MemVT = RegisterVT;
984  } else if (ArgVT.isVector() &&
985  ArgVT.getVectorNumElements() == NumRegs) {
986  // This arg has been split so that each element is stored in a separate
987  // register.
988  MemVT = ArgVT.getScalarType();
989  } else if (ArgVT.isExtended()) {
990  // We have an extended type, like i65.
991  MemVT = RegisterVT;
992  } else {
993  unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
994  assert(ArgVT.getStoreSizeInBits() % NumRegs == 0);
995  if (RegisterVT.isInteger()) {
996  MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
997  } else if (RegisterVT.isVector()) {
998  assert(!RegisterVT.getScalarType().isFloatingPoint());
999  unsigned NumElements = RegisterVT.getVectorNumElements();
1000  assert(MemoryBits % NumElements == 0);
1001  // This vector type has been split into another vector type with
1002  // a different elements size.
1003  EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
1004  MemoryBits / NumElements);
1005  MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
1006  } else {
1007  llvm_unreachable("cannot deduce memory type.");
1008  }
1009  }
1010 
1011  // Convert one element vectors to scalar.
1012  if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
1013  MemVT = MemVT.getScalarType();
1014 
1015  if (MemVT.isExtended()) {
1016  // This should really only happen if we have vec3 arguments
1017  assert(MemVT.isVector() && MemVT.getVectorNumElements() == 3);
1018  MemVT = MemVT.getPow2VectorType(State.getContext());
1019  }
1020 
1021  unsigned PartOffset = 0;
1022  for (unsigned i = 0; i != NumRegs; ++i) {
1023  State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1024  BasePartOffset + PartOffset,
1025  MemVT.getSimpleVT(),
1027  PartOffset += MemVT.getStoreSize();
1028  }
1029  }
1030  }
1031 }
1032 
1034  SDValue Chain, CallingConv::ID CallConv,
1035  bool isVarArg,
1036  const SmallVectorImpl<ISD::OutputArg> &Outs,
1037  const SmallVectorImpl<SDValue> &OutVals,
1038  const SDLoc &DL, SelectionDAG &DAG) const {
1039  // FIXME: Fails for r600 tests
1040  //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1041  // "wave terminate should not have return values");
1042  return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1043 }
1044 
1045 //===---------------------------------------------------------------------===//
1046 // Target specific lowering
1047 //===---------------------------------------------------------------------===//
1048 
1049 /// Selects the correct CCAssignFn for a given CallingConvention value.
1051  bool IsVarArg) {
1052  return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1053 }
1054 
1056  bool IsVarArg) {
1057  return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1058 }
1059 
1061  SelectionDAG &DAG,
1062  MachineFrameInfo &MFI,
1063  int ClobberedFI) const {
1064  SmallVector<SDValue, 8> ArgChains;
1065  int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1066  int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1067 
1068  // Include the original chain at the beginning of the list. When this is
1069  // used by target LowerCall hooks, this helps legalize find the
1070  // CALLSEQ_BEGIN node.
1071  ArgChains.push_back(Chain);
1072 
1073  // Add a chain value for each stack argument corresponding
1074  for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1075  UE = DAG.getEntryNode().getNode()->use_end();
1076  U != UE; ++U) {
1077  if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1078  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1079  if (FI->getIndex() < 0) {
1080  int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1081  int64_t InLastByte = InFirstByte;
1082  InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1083 
1084  if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1085  (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1086  ArgChains.push_back(SDValue(L, 1));
1087  }
1088  }
1089  }
1090  }
1091 
1092  // Build a tokenfactor for all the chains.
1093  return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1094 }
1095 
1097  SmallVectorImpl<SDValue> &InVals,
1098  StringRef Reason) const {
1099  SDValue Callee = CLI.Callee;
1100  SelectionDAG &DAG = CLI.DAG;
1101 
1102  const Function &Fn = DAG.getMachineFunction().getFunction();
1103 
1104  StringRef FuncName("<unknown>");
1105 
1106  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1107  FuncName = G->getSymbol();
1108  else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1109  FuncName = G->getGlobal()->getName();
1110 
1111  DiagnosticInfoUnsupported NoCalls(
1112  Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1113  DAG.getContext()->diagnose(NoCalls);
1114 
1115  if (!CLI.IsTailCall) {
1116  for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1117  InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1118  }
1119 
1120  return DAG.getEntryNode();
1121 }
1122 
1124  SmallVectorImpl<SDValue> &InVals) const {
1125  return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1126 }
1127 
1129  SelectionDAG &DAG) const {
1130  const Function &Fn = DAG.getMachineFunction().getFunction();
1131 
1132  DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1133  SDLoc(Op).getDebugLoc());
1134  DAG.getContext()->diagnose(NoDynamicAlloca);
1135  auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1136  return DAG.getMergeValues(Ops, SDLoc());
1137 }
1138 
1140  SelectionDAG &DAG) const {
1141  switch (Op.getOpcode()) {
1142  default:
1143  Op->print(errs(), &DAG);
1144  llvm_unreachable("Custom lowering code for this"
1145  "instruction is not implemented yet!");
1146  break;
1147  case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1148  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1149  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1150  case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1151  case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1152  case ISD::FREM: return LowerFREM(Op, DAG);
1153  case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1154  case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1155  case ISD::FRINT: return LowerFRINT(Op, DAG);
1156  case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1157  case ISD::FROUND: return LowerFROUND(Op, DAG);
1158  case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1159  case ISD::FLOG:
1160  return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1161  case ISD::FLOG10:
1162  return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
1163  case ISD::FEXP:
1164  return lowerFEXP(Op, DAG);
1165  case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1166  case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1167  case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1168  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1169  case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1170  case ISD::CTTZ:
1171  case ISD::CTTZ_ZERO_UNDEF:
1172  case ISD::CTLZ:
1173  case ISD::CTLZ_ZERO_UNDEF:
1174  return LowerCTLZ_CTTZ(Op, DAG);
1175  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1176  }
1177  return Op;
1178 }
1179 
1182  SelectionDAG &DAG) const {
1183  switch (N->getOpcode()) {
1185  // Different parts of legalization seem to interpret which type of
1186  // sign_extend_inreg is the one to check for custom lowering. The extended
1187  // from type is what really matters, but some places check for custom
1188  // lowering of the result type. This results in trying to use
1189  // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1190  // nothing here and let the illegal result integer be handled normally.
1191  return;
1192  default:
1193  return;
1194  }
1195 }
1196 
1197 static bool hasDefinedInitializer(const GlobalValue *GV) {
1198  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1199  if (!GVar || !GVar->hasInitializer())
1200  return false;
1201 
1202  return !isa<UndefValue>(GVar->getInitializer());
1203 }
1204 
1206  SDValue Op,
1207  SelectionDAG &DAG) const {
1208 
1209  const DataLayout &DL = DAG.getDataLayout();
1210  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1211  const GlobalValue *GV = G->getGlobal();
1212 
1215  if (!MFI->isEntryFunction()) {
1216  const Function &Fn = DAG.getMachineFunction().getFunction();
1217  DiagnosticInfoUnsupported BadLDSDecl(
1218  Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1219  DAG.getContext()->diagnose(BadLDSDecl);
1220  }
1221 
1222  // XXX: What does the value of G->getOffset() mean?
1223  assert(G->getOffset() == 0 &&
1224  "Do not know what to do with an non-zero offset");
1225 
1226  // TODO: We could emit code to handle the initialization somewhere.
1227  if (!hasDefinedInitializer(GV)) {
1228  unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1229  return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1230  }
1231  }
1232 
1233  const Function &Fn = DAG.getMachineFunction().getFunction();
1234  DiagnosticInfoUnsupported BadInit(
1235  Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1236  DAG.getContext()->diagnose(BadInit);
1237  return SDValue();
1238 }
1239 
1241  SelectionDAG &DAG) const {
1243 
1244  EVT VT = Op.getValueType();
1245  if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1246  SDLoc SL(Op);
1247  SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1248  SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1249 
1250  SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1251  return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1252  }
1253 
1254  for (const SDUse &U : Op->ops())
1255  DAG.ExtractVectorElements(U.get(), Args);
1256 
1257  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1258 }
1259 
1261  SelectionDAG &DAG) const {
1262 
1264  unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1265  EVT VT = Op.getValueType();
1266  DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1267  VT.getVectorNumElements());
1268 
1269  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1270 }
1271 
1272 /// Generate Min/Max node
1274  SDValue LHS, SDValue RHS,
1275  SDValue True, SDValue False,
1276  SDValue CC,
1277  DAGCombinerInfo &DCI) const {
1278  if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1279  return SDValue();
1280 
1281  SelectionDAG &DAG = DCI.DAG;
1282  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1283  switch (CCOpcode) {
1284  case ISD::SETOEQ:
1285  case ISD::SETONE:
1286  case ISD::SETUNE:
1287  case ISD::SETNE:
1288  case ISD::SETUEQ:
1289  case ISD::SETEQ:
1290  case ISD::SETFALSE:
1291  case ISD::SETFALSE2:
1292  case ISD::SETTRUE:
1293  case ISD::SETTRUE2:
1294  case ISD::SETUO:
1295  case ISD::SETO:
1296  break;
1297  case ISD::SETULE:
1298  case ISD::SETULT: {
1299  if (LHS == True)
1300  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1301  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1302  }
1303  case ISD::SETOLE:
1304  case ISD::SETOLT:
1305  case ISD::SETLE:
1306  case ISD::SETLT: {
1307  // Ordered. Assume ordered for undefined.
1308 
1309  // Only do this after legalization to avoid interfering with other combines
1310  // which might occur.
1311  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1312  !DCI.isCalledByLegalizer())
1313  return SDValue();
1314 
1315  // We need to permute the operands to get the correct NaN behavior. The
1316  // selected operand is the second one based on the failing compare with NaN,
1317  // so permute it based on the compare type the hardware uses.
1318  if (LHS == True)
1319  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1320  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1321  }
1322  case ISD::SETUGE:
1323  case ISD::SETUGT: {
1324  if (LHS == True)
1325  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1326  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1327  }
1328  case ISD::SETGT:
1329  case ISD::SETGE:
1330  case ISD::SETOGE:
1331  case ISD::SETOGT: {
1332  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1333  !DCI.isCalledByLegalizer())
1334  return SDValue();
1335 
1336  if (LHS == True)
1337  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1338  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1339  }
1340  case ISD::SETCC_INVALID:
1341  llvm_unreachable("Invalid setcc condcode!");
1342  }
1343  return SDValue();
1344 }
1345 
1346 std::pair<SDValue, SDValue>
1348  SDLoc SL(Op);
1349 
1350  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1351 
1352  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1353  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1354 
1355  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1356  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1357 
1358  return std::make_pair(Lo, Hi);
1359 }
1360 
1362  SDLoc SL(Op);
1363 
1364  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1365  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1366  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1367 }
1368 
1370  SDLoc SL(Op);
1371 
1372  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1373  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1374  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1375 }
1376 
1378  SelectionDAG &DAG) const {
1379  LoadSDNode *Load = cast<LoadSDNode>(Op);
1380  EVT VT = Op.getValueType();
1381 
1382 
1383  // If this is a 2 element vector, we really want to scalarize and not create
1384  // weird 1 element vectors.
1385  if (VT.getVectorNumElements() == 2)
1386  return scalarizeVectorLoad(Load, DAG);
1387 
1388  SDValue BasePtr = Load->getBasePtr();
1389  EVT MemVT = Load->getMemoryVT();
1390  SDLoc SL(Op);
1391 
1392  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1393 
1394  EVT LoVT, HiVT;
1395  EVT LoMemVT, HiMemVT;
1396  SDValue Lo, Hi;
1397 
1398  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1399  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1400  std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1401 
1402  unsigned Size = LoMemVT.getStoreSize();
1403  unsigned BaseAlign = Load->getAlignment();
1404  unsigned HiAlign = MinAlign(BaseAlign, Size);
1405 
1406  SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1407  Load->getChain(), BasePtr, SrcValue, LoMemVT,
1408  BaseAlign, Load->getMemOperand()->getFlags());
1409  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1410  SDValue HiLoad =
1411  DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1412  HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1413  HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1414 
1415  SDValue Ops[] = {
1416  DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1418  LoLoad.getValue(1), HiLoad.getValue(1))
1419  };
1420 
1421  return DAG.getMergeValues(Ops, SL);
1422 }
1423 
1425  SelectionDAG &DAG) const {
1426  StoreSDNode *Store = cast<StoreSDNode>(Op);
1427  SDValue Val = Store->getValue();
1428  EVT VT = Val.getValueType();
1429 
1430  // If this is a 2 element vector, we really want to scalarize and not create
1431  // weird 1 element vectors.
1432  if (VT.getVectorNumElements() == 2)
1433  return scalarizeVectorStore(Store, DAG);
1434 
1435  EVT MemVT = Store->getMemoryVT();
1436  SDValue Chain = Store->getChain();
1437  SDValue BasePtr = Store->getBasePtr();
1438  SDLoc SL(Op);
1439 
1440  EVT LoVT, HiVT;
1441  EVT LoMemVT, HiMemVT;
1442  SDValue Lo, Hi;
1443 
1444  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1445  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1446  std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1447 
1448  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1449 
1450  const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1451  unsigned BaseAlign = Store->getAlignment();
1452  unsigned Size = LoMemVT.getStoreSize();
1453  unsigned HiAlign = MinAlign(BaseAlign, Size);
1454 
1455  SDValue LoStore =
1456  DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1457  Store->getMemOperand()->getFlags());
1458  SDValue HiStore =
1459  DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1460  HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1461 
1462  return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1463 }
1464 
1465 // This is a shortcut for integer division because we have fast i32<->f32
1466 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1467 // float is enough to accurately represent up to a 24-bit signed integer.
1469  bool Sign) const {
1470  SDLoc DL(Op);
1471  EVT VT = Op.getValueType();
1472  SDValue LHS = Op.getOperand(0);
1473  SDValue RHS = Op.getOperand(1);
1474  MVT IntVT = MVT::i32;
1475  MVT FltVT = MVT::f32;
1476 
1477  unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1478  if (LHSSignBits < 9)
1479  return SDValue();
1480 
1481  unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1482  if (RHSSignBits < 9)
1483  return SDValue();
1484 
1485  unsigned BitSize = VT.getSizeInBits();
1486  unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1487  unsigned DivBits = BitSize - SignBits;
1488  if (Sign)
1489  ++DivBits;
1490 
1493 
1494  SDValue jq = DAG.getConstant(1, DL, IntVT);
1495 
1496  if (Sign) {
1497  // char|short jq = ia ^ ib;
1498  jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1499 
1500  // jq = jq >> (bitsize - 2)
1501  jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1502  DAG.getConstant(BitSize - 2, DL, VT));
1503 
1504  // jq = jq | 0x1
1505  jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1506  }
1507 
1508  // int ia = (int)LHS;
1509  SDValue ia = LHS;
1510 
1511  // int ib, (int)RHS;
1512  SDValue ib = RHS;
1513 
1514  // float fa = (float)ia;
1515  SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1516 
1517  // float fb = (float)ib;
1518  SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1519 
1520  SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1521  fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1522 
1523  // fq = trunc(fq);
1524  fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1525 
1526  // float fqneg = -fq;
1527  SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1528 
1529  // float fr = mad(fqneg, fb, fa);
1530  unsigned OpCode = Subtarget->hasFP32Denormals() ?
1532  (unsigned)ISD::FMAD;
1533  SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1534 
1535  // int iq = (int)fq;
1536  SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1537 
1538  // fr = fabs(fr);
1539  fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1540 
1541  // fb = fabs(fb);
1542  fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1543 
1544  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1545 
1546  // int cv = fr >= fb;
1547  SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1548 
1549  // jq = (cv ? jq : 0);
1550  jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1551 
1552  // dst = iq + jq;
1553  SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1554 
1555  // Rem needs compensation, it's easier to recompute it
1556  SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1557  Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1558 
1559  // Truncate to number of bits this divide really is.
1560  if (Sign) {
1561  SDValue InRegSize
1562  = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1563  Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1564  Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1565  } else {
1566  SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1567  Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1568  Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1569  }
1570 
1571  return DAG.getMergeValues({ Div, Rem }, DL);
1572 }
1573 
1575  SelectionDAG &DAG,
1577  SDLoc DL(Op);
1578  EVT VT = Op.getValueType();
1579 
1580  assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1581 
1582  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1583 
1584  SDValue One = DAG.getConstant(1, DL, HalfVT);
1585  SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1586 
1587  //HiLo split
1588  SDValue LHS = Op.getOperand(0);
1589  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1590  SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1591 
1592  SDValue RHS = Op.getOperand(1);
1593  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1594  SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1595 
1596  if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1597  DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1598 
1599  SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1600  LHS_Lo, RHS_Lo);
1601 
1602  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1603  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1604 
1605  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1606  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1607  return;
1608  }
1609 
1610  if (isTypeLegal(MVT::i64)) {
1611  // Compute denominator reciprocal.
1612  unsigned FMAD = Subtarget->hasFP32Denormals() ?
1614  (unsigned)ISD::FMAD;
1615 
1616  SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1617  SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1618  SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1619  DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1620  Cvt_Lo);
1621  SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1622  SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1623  DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1624  SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1625  DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1626  SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1627  SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1628  DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1629  Mul1);
1630  SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1631  SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1632  SDValue Rcp64 = DAG.getBitcast(VT,
1633  DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1634 
1635  SDValue Zero64 = DAG.getConstant(0, DL, VT);
1636  SDValue One64 = DAG.getConstant(1, DL, VT);
1637  SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1638  SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1639 
1640  SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1641  SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1642  SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1643  SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1644  Zero);
1645  SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1646  One);
1647 
1648  SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1649  Mulhi1_Lo, Zero1);
1650  SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1651  Mulhi1_Hi, Add1_Lo.getValue(1));
1652  SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1653  SDValue Add1 = DAG.getBitcast(VT,
1654  DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1655 
1656  SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1657  SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1658  SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1659  Zero);
1660  SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1661  One);
1662 
1663  SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1664  Mulhi2_Lo, Zero1);
1665  SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1666  Mulhi2_Hi, Add1_Lo.getValue(1));
1667  SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1668  Zero, Add2_Lo.getValue(1));
1669  SDValue Add2 = DAG.getBitcast(VT,
1670  DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1671  SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1672 
1673  SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1674 
1675  SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1676  SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1677  SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1678  Mul3_Lo, Zero1);
1679  SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1680  Mul3_Hi, Sub1_Lo.getValue(1));
1681  SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1682  SDValue Sub1 = DAG.getBitcast(VT,
1683  DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1684 
1685  SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1686  SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1687  ISD::SETUGE);
1688  SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1689  ISD::SETUGE);
1690  SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1691 
1692  // TODO: Here and below portions of the code can be enclosed into if/endif.
1693  // Currently control flow is unconditional and we have 4 selects after
1694  // potential endif to substitute PHIs.
1695 
1696  // if C3 != 0 ...
1697  SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1698  RHS_Lo, Zero1);
1699  SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1700  RHS_Hi, Sub1_Lo.getValue(1));
1701  SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1702  Zero, Sub2_Lo.getValue(1));
1703  SDValue Sub2 = DAG.getBitcast(VT,
1704  DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1705 
1706  SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1707 
1708  SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1709  ISD::SETUGE);
1710  SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1711  ISD::SETUGE);
1712  SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1713 
1714  // if (C6 != 0)
1715  SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1716 
1717  SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1718  RHS_Lo, Zero1);
1719  SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1720  RHS_Hi, Sub2_Lo.getValue(1));
1721  SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1722  Zero, Sub3_Lo.getValue(1));
1723  SDValue Sub3 = DAG.getBitcast(VT,
1724  DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1725 
1726  // endif C6
1727  // endif C3
1728 
1729  SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1730  SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1731 
1732  SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1733  SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1734 
1735  Results.push_back(Div);
1736  Results.push_back(Rem);
1737 
1738  return;
1739  }
1740 
1741  // r600 expandion.
1742  // Get Speculative values
1743  SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1744  SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1745 
1746  SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1747  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1748  REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1749 
1750  SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1751  SDValue DIV_Lo = Zero;
1752 
1753  const unsigned halfBitWidth = HalfVT.getSizeInBits();
1754 
1755  for (unsigned i = 0; i < halfBitWidth; ++i) {
1756  const unsigned bitPos = halfBitWidth - i - 1;
1757  SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1758  // Get value of high bit
1759  SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1760  HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1761  HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1762 
1763  // Shift
1764  REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1765  // Add LHS high bit
1766  REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1767 
1768  SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1769  SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1770 
1771  DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1772 
1773  // Update REM
1774  SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1775  REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1776  }
1777 
1778  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1779  DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1780  Results.push_back(DIV);
1781  Results.push_back(REM);
1782 }
1783 
1785  SelectionDAG &DAG) const {
1786  SDLoc DL(Op);
1787  EVT VT = Op.getValueType();
1788 
1789  if (VT == MVT::i64) {
1791  LowerUDIVREM64(Op, DAG, Results);
1792  return DAG.getMergeValues(Results, DL);
1793  }
1794 
1795  if (VT == MVT::i32) {
1796  if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1797  return Res;
1798  }
1799 
1800  SDValue Num = Op.getOperand(0);
1801  SDValue Den = Op.getOperand(1);
1802 
1803  // RCP = URECIP(Den) = 2^32 / Den + e
1804  // e is rounding error.
1805  SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1806 
1807  // RCP_LO = mul(RCP, Den) */
1808  SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1809 
1810  // RCP_HI = mulhu (RCP, Den) */
1811  SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1812 
1813  // NEG_RCP_LO = -RCP_LO
1814  SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1815  RCP_LO);
1816 
1817  // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1818  SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1819  NEG_RCP_LO, RCP_LO,
1820  ISD::SETEQ);
1821  // Calculate the rounding error from the URECIP instruction
1822  // E = mulhu(ABS_RCP_LO, RCP)
1823  SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1824 
1825  // RCP_A_E = RCP + E
1826  SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1827 
1828  // RCP_S_E = RCP - E
1829  SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1830 
1831  // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1832  SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1833  RCP_A_E, RCP_S_E,
1834  ISD::SETEQ);
1835  // Quotient = mulhu(Tmp0, Num)
1836  SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1837 
1838  // Num_S_Remainder = Quotient * Den
1839  SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1840 
1841  // Remainder = Num - Num_S_Remainder
1842  SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1843 
1844  // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1845  SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1846  DAG.getConstant(-1, DL, VT),
1847  DAG.getConstant(0, DL, VT),
1848  ISD::SETUGE);
1849  // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1850  SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1851  Num_S_Remainder,
1852  DAG.getConstant(-1, DL, VT),
1853  DAG.getConstant(0, DL, VT),
1854  ISD::SETUGE);
1855  // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1856  SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1857  Remainder_GE_Zero);
1858 
1859  // Calculate Division result:
1860 
1861  // Quotient_A_One = Quotient + 1
1862  SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1863  DAG.getConstant(1, DL, VT));
1864 
1865  // Quotient_S_One = Quotient - 1
1866  SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1867  DAG.getConstant(1, DL, VT));
1868 
1869  // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1870  SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1871  Quotient, Quotient_A_One, ISD::SETEQ);
1872 
1873  // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1874  Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1875  Quotient_S_One, Div, ISD::SETEQ);
1876 
1877  // Calculate Rem result:
1878 
1879  // Remainder_S_Den = Remainder - Den
1880  SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1881 
1882  // Remainder_A_Den = Remainder + Den
1883  SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1884 
1885  // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1886  SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1887  Remainder, Remainder_S_Den, ISD::SETEQ);
1888 
1889  // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1890  Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1891  Remainder_A_Den, Rem, ISD::SETEQ);
1892  SDValue Ops[2] = {
1893  Div,
1894  Rem
1895  };
1896  return DAG.getMergeValues(Ops, DL);
1897 }
1898 
1900  SelectionDAG &DAG) const {
1901  SDLoc DL(Op);
1902  EVT VT = Op.getValueType();
1903 
1904  SDValue LHS = Op.getOperand(0);
1905  SDValue RHS = Op.getOperand(1);
1906 
1907  SDValue Zero = DAG.getConstant(0, DL, VT);
1908  SDValue NegOne = DAG.getConstant(-1, DL, VT);
1909 
1910  if (VT == MVT::i32) {
1911  if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1912  return Res;
1913  }
1914 
1915  if (VT == MVT::i64 &&
1916  DAG.ComputeNumSignBits(LHS) > 32 &&
1917  DAG.ComputeNumSignBits(RHS) > 32) {
1918  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1919 
1920  //HiLo split
1921  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1922  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1923  SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1924  LHS_Lo, RHS_Lo);
1925  SDValue Res[2] = {
1926  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1927  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1928  };
1929  return DAG.getMergeValues(Res, DL);
1930  }
1931 
1932  SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1933  SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1934  SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1935  SDValue RSign = LHSign; // Remainder sign is the same as LHS
1936 
1937  LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1938  RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1939 
1940  LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1941  RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1942 
1943  SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1944  SDValue Rem = Div.getValue(1);
1945 
1946  Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1947  Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1948 
1949  Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1950  Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1951 
1952  SDValue Res[2] = {
1953  Div,
1954  Rem
1955  };
1956  return DAG.getMergeValues(Res, DL);
1957 }
1958 
1959 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1961  SDLoc SL(Op);
1962  EVT VT = Op.getValueType();
1963  SDValue X = Op.getOperand(0);
1964  SDValue Y = Op.getOperand(1);
1965 
1966  // TODO: Should this propagate fast-math-flags?
1967 
1968  SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1969  SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1970  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1971 
1972  return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1973 }
1974 
1976  SDLoc SL(Op);
1977  SDValue Src = Op.getOperand(0);
1978 
1979  // result = trunc(src)
1980  // if (src > 0.0 && src != result)
1981  // result += 1.0
1982 
1983  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1984 
1985  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1986  const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1987 
1988  EVT SetCCVT =
1990 
1991  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1992  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1993  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1994 
1995  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1996  // TODO: Should this propagate fast-math-flags?
1997  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1998 }
1999 
2001  SelectionDAG &DAG) {
2002  const unsigned FractBits = 52;
2003  const unsigned ExpBits = 11;
2004 
2005  SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2006  Hi,
2007  DAG.getConstant(FractBits - 32, SL, MVT::i32),
2008  DAG.getConstant(ExpBits, SL, MVT::i32));
2009  SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2010  DAG.getConstant(1023, SL, MVT::i32));
2011 
2012  return Exp;
2013 }
2014 
2016  SDLoc SL(Op);
2017  SDValue Src = Op.getOperand(0);
2018 
2019  assert(Op.getValueType() == MVT::f64);
2020 
2021  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2022  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2023 
2024  SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2025 
2026  // Extract the upper half, since this is where we will find the sign and
2027  // exponent.
2028  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2029 
2030  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2031 
2032  const unsigned FractBits = 52;
2033 
2034  // Extract the sign bit.
2035  const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2036  SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2037 
2038  // Extend back to 64-bits.
2039  SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2040  SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2041 
2042  SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2043  const SDValue FractMask
2044  = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2045 
2046  SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2047  SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2048  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2049 
2050  EVT SetCCVT =
2052 
2053  const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2054 
2055  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2056  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2057 
2058  SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2059  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2060 
2061  return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2062 }
2063 
2065  SDLoc SL(Op);
2066  SDValue Src = Op.getOperand(0);
2067 
2068  assert(Op.getValueType() == MVT::f64);
2069 
2070  APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2071  SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2072  SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2073 
2074  // TODO: Should this propagate fast-math-flags?
2075 
2076  SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2077  SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2078 
2079  SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2080 
2081  APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2082  SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2083 
2084  EVT SetCCVT =
2086  SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2087 
2088  return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2089 }
2090 
2092  // FNEARBYINT and FRINT are the same, except in their handling of FP
2093  // exceptions. Those aren't really meaningful for us, and OpenCL only has
2094  // rint, so just treat them as equivalent.
2095  return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2096 }
2097 
2098 // XXX - May require not supporting f32 denormals?
2099 
2100 // Don't handle v2f16. The extra instructions to scalarize and repack around the
2101 // compare and vselect end up producing worse code than scalarizing the whole
2102 // operation.
2104  SDLoc SL(Op);
2105  SDValue X = Op.getOperand(0);
2106  EVT VT = Op.getValueType();
2107 
2108  SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2109 
2110  // TODO: Should this propagate fast-math-flags?
2111 
2112  SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2113 
2114  SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2115 
2116  const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2117  const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2118  const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2119 
2120  SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2121 
2122  EVT SetCCVT =
2123  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2124 
2125  SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2126 
2127  SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2128 
2129  return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2130 }
2131 
2133  SDLoc SL(Op);
2134  SDValue X = Op.getOperand(0);
2135 
2136  SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2137 
2138  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2139  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2140  const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2141  const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2142  EVT SetCCVT =
2144 
2145  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2146 
2147  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2148 
2149  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2150 
2151  const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2152  MVT::i64);
2153 
2154  SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2155  SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2156  DAG.getConstant(INT64_C(0x0008000000000000), SL,
2157  MVT::i64),
2158  Exp);
2159 
2160  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2161  SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2162  DAG.getConstant(0, SL, MVT::i64), Tmp0,
2163  ISD::SETNE);
2164 
2165  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2166  D, DAG.getConstant(0, SL, MVT::i64));
2167  SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2168 
2169  K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2170  K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2171 
2172  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2173  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2174  SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2175 
2176  SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2177  ExpEqNegOne,
2178  DAG.getConstantFP(1.0, SL, MVT::f64),
2179  DAG.getConstantFP(0.0, SL, MVT::f64));
2180 
2181  SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2182 
2183  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2184  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2185 
2186  return K;
2187 }
2188 
2190  EVT VT = Op.getValueType();
2191 
2192  if (VT == MVT::f32 || VT == MVT::f16)
2193  return LowerFROUND32_16(Op, DAG);
2194 
2195  if (VT == MVT::f64)
2196  return LowerFROUND64(Op, DAG);
2197 
2198  llvm_unreachable("unhandled type");
2199 }
2200 
2202  SDLoc SL(Op);
2203  SDValue Src = Op.getOperand(0);
2204 
2205  // result = trunc(src);
2206  // if (src < 0.0 && src != result)
2207  // result += -1.0.
2208 
2209  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2210 
2211  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2212  const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2213 
2214  EVT SetCCVT =
2216 
2217  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2218  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2219  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2220 
2221  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2222  // TODO: Should this propagate fast-math-flags?
2223  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2224 }
2225 
2227  double Log2BaseInverted) const {
2228  EVT VT = Op.getValueType();
2229 
2230  SDLoc SL(Op);
2231  SDValue Operand = Op.getOperand(0);
2232  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2233  SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2234 
2235  return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2236 }
2237 
2238 // Return M_LOG2E of appropriate type
2239 static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) {
2240  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
2241  case MVT::f32:
2242  return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT);
2243  case MVT::f16:
2244  return DAG.getConstantFP(
2245  APFloat(APFloat::IEEEhalf(), "1.44269504088896340735992468100189214"),
2246  SL, VT);
2247  case MVT::f64:
2248  return DAG.getConstantFP(
2249  APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT);
2250  default:
2251  llvm_unreachable("unsupported fp type");
2252  }
2253 }
2254 
2255 // exp2(M_LOG2E_F * f);
2257  EVT VT = Op.getValueType();
2258  SDLoc SL(Op);
2259  SDValue Src = Op.getOperand(0);
2260 
2261  const SDValue K = getLog2EVal(DAG, SL, VT);
2262  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2263  return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2264 }
2265 
2266 static bool isCtlzOpc(unsigned Opc) {
2267  return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2268 }
2269 
2270 static bool isCttzOpc(unsigned Opc) {
2271  return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2272 }
2273 
2275  SDLoc SL(Op);
2276  SDValue Src = Op.getOperand(0);
2277  bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2279 
2280  unsigned ISDOpc, NewOpc;
2281  if (isCtlzOpc(Op.getOpcode())) {
2282  ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2283  NewOpc = AMDGPUISD::FFBH_U32;
2284  } else if (isCttzOpc(Op.getOpcode())) {
2285  ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2286  NewOpc = AMDGPUISD::FFBL_B32;
2287  } else
2288  llvm_unreachable("Unexpected OPCode!!!");
2289 
2290 
2291  if (ZeroUndef && Src.getValueType() == MVT::i32)
2292  return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2293 
2294  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2295 
2296  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2297  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2298 
2299  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2300  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2301 
2302  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2303  *DAG.getContext(), MVT::i32);
2304 
2305  SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2306  SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2307 
2308  SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2309  SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2310 
2311  const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2312  SDValue Add, NewOpr;
2313  if (isCtlzOpc(Op.getOpcode())) {
2314  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2315  // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2316  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2317  } else {
2318  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2319  // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2320  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2321  }
2322 
2323  if (!ZeroUndef) {
2324  // Test if the full 64-bit input is zero.
2325 
2326  // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2327  // which we probably don't want.
2328  SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2329  SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2330  SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2331 
2332  // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2333  // with the same cycles, otherwise it is slower.
2334  // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2335  // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2336 
2337  const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2338 
2339  // The instruction returns -1 for 0 input, but the defined intrinsic
2340  // behavior is to return the number of bits.
2341  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2342  SrcIsZero, Bits32, NewOpr);
2343  }
2344 
2345  return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2346 }
2347 
2349  bool Signed) const {
2350  // Unsigned
2351  // cul2f(ulong u)
2352  //{
2353  // uint lz = clz(u);
2354  // uint e = (u != 0) ? 127U + 63U - lz : 0;
2355  // u = (u << lz) & 0x7fffffffffffffffUL;
2356  // ulong t = u & 0xffffffffffUL;
2357  // uint v = (e << 23) | (uint)(u >> 40);
2358  // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2359  // return as_float(v + r);
2360  //}
2361  // Signed
2362  // cl2f(long l)
2363  //{
2364  // long s = l >> 63;
2365  // float r = cul2f((l + s) ^ s);
2366  // return s ? -r : r;
2367  //}
2368 
2369  SDLoc SL(Op);
2370  SDValue Src = Op.getOperand(0);
2371  SDValue L = Src;
2372 
2373  SDValue S;
2374  if (Signed) {
2375  const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2376  S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2377 
2378  SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2379  L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2380  }
2381 
2382  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2383  *DAG.getContext(), MVT::f32);
2384 
2385 
2386  SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2387  SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2388  SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2389  LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2390 
2391  SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2392  SDValue E = DAG.getSelect(SL, MVT::i32,
2393  DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2394  DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2395  ZeroI32);
2396 
2397  SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2398  DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2399  DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2400 
2401  SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2402  DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2403 
2404  SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2405  U, DAG.getConstant(40, SL, MVT::i64));
2406 
2407  SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2408  DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2409  DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2410 
2411  SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2412  SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2413  SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2414 
2415  SDValue One = DAG.getConstant(1, SL, MVT::i32);
2416 
2417  SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2418 
2419  SDValue R = DAG.getSelect(SL, MVT::i32,
2420  RCmp,
2421  One,
2422  DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2423  R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2424  R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2425 
2426  if (!Signed)
2427  return R;
2428 
2429  SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2430  return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2431 }
2432 
2434  bool Signed) const {
2435  SDLoc SL(Op);
2436  SDValue Src = Op.getOperand(0);
2437 
2438  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2439 
2441  DAG.getConstant(0, SL, MVT::i32));
2443  DAG.getConstant(1, SL, MVT::i32));
2444 
2445  SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2446  SL, MVT::f64, Hi);
2447 
2448  SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2449 
2450  SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2451  DAG.getConstant(32, SL, MVT::i32));
2452  // TODO: Should this propagate fast-math-flags?
2453  return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2454 }
2455 
2457  SelectionDAG &DAG) const {
2458  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2459  "operation should be legal");
2460 
2461  // TODO: Factor out code common with LowerSINT_TO_FP.
2462 
2463  EVT DestVT = Op.getValueType();
2464  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2465  SDLoc DL(Op);
2466  SDValue Src = Op.getOperand(0);
2467 
2468  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2469  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2470  SDValue FPRound =
2471  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2472 
2473  return FPRound;
2474  }
2475 
2476  if (DestVT == MVT::f32)
2477  return LowerINT_TO_FP32(Op, DAG, false);
2478 
2479  assert(DestVT == MVT::f64);
2480  return LowerINT_TO_FP64(Op, DAG, false);
2481 }
2482 
2484  SelectionDAG &DAG) const {
2485  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2486  "operation should be legal");
2487 
2488  // TODO: Factor out code common with LowerUINT_TO_FP.
2489 
2490  EVT DestVT = Op.getValueType();
2491  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2492  SDLoc DL(Op);
2493  SDValue Src = Op.getOperand(0);
2494 
2495  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2496  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2497  SDValue FPRound =
2498  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2499 
2500  return FPRound;
2501  }
2502 
2503  if (DestVT == MVT::f32)
2504  return LowerINT_TO_FP32(Op, DAG, true);
2505 
2506  assert(DestVT == MVT::f64);
2507  return LowerINT_TO_FP64(Op, DAG, true);
2508 }
2509 
2511  bool Signed) const {
2512  SDLoc SL(Op);
2513 
2514  SDValue Src = Op.getOperand(0);
2515 
2516  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2517 
2518  SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2519  MVT::f64);
2520  SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2521  MVT::f64);
2522  // TODO: Should this propagate fast-math-flags?
2523  SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2524 
2525  SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2526 
2527 
2528  SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2529 
2530  SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2531  MVT::i32, FloorMul);
2532  SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2533 
2534  SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2535 
2536  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2537 }
2538 
2540  SDLoc DL(Op);
2541  SDValue N0 = Op.getOperand(0);
2542 
2543  // Convert to target node to get known bits
2544  if (N0.getValueType() == MVT::f32)
2545  return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2546 
2548  // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2549  return SDValue();
2550  }
2551 
2553 
2554  // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2555  const unsigned ExpMask = 0x7ff;
2556  const unsigned ExpBiasf64 = 1023;
2557  const unsigned ExpBiasf16 = 15;
2558  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2559  SDValue One = DAG.getConstant(1, DL, MVT::i32);
2560  SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2561  SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2562  DAG.getConstant(32, DL, MVT::i64));
2563  UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2564  U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2565  SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2566  DAG.getConstant(20, DL, MVT::i64));
2567  E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2568  DAG.getConstant(ExpMask, DL, MVT::i32));
2569  // Subtract the fp64 exponent bias (1023) to get the real exponent and
2570  // add the f16 bias (15) to get the biased exponent for the f16 format.
2571  E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2572  DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2573 
2574  SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2575  DAG.getConstant(8, DL, MVT::i32));
2576  M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2577  DAG.getConstant(0xffe, DL, MVT::i32));
2578 
2579  SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2580  DAG.getConstant(0x1ff, DL, MVT::i32));
2581  MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2582 
2583  SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2584  M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2585 
2586  // (M != 0 ? 0x0200 : 0) | 0x7c00;
2587  SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2588  DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2589  Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2590 
2591  // N = M | (E << 12);
2592  SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2593  DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2594  DAG.getConstant(12, DL, MVT::i32)));
2595 
2596  // B = clamp(1-E, 0, 13);
2597  SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2598  One, E);
2599  SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2600  B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2601  DAG.getConstant(13, DL, MVT::i32));
2602 
2603  SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2604  DAG.getConstant(0x1000, DL, MVT::i32));
2605 
2606  SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2607  SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2608  SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2609  D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2610 
2611  SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2612  SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2613  DAG.getConstant(0x7, DL, MVT::i32));
2614  V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2615  DAG.getConstant(2, DL, MVT::i32));
2616  SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2617  One, Zero, ISD::SETEQ);
2618  SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2619  One, Zero, ISD::SETGT);
2620  V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2621  V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2622 
2623  V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2624  DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2625  V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2626  I, V, ISD::SETEQ);
2627 
2628  // Extract the sign bit.
2629  SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2630  DAG.getConstant(16, DL, MVT::i32));
2631  Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2632  DAG.getConstant(0x8000, DL, MVT::i32));
2633 
2634  V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2635  return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2636 }
2637 
2639  SelectionDAG &DAG) const {
2640  SDValue Src = Op.getOperand(0);
2641 
2642  // TODO: Factor out code common with LowerFP_TO_UINT.
2643 
2644  EVT SrcVT = Src.getValueType();
2645  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2646  SDLoc DL(Op);
2647 
2648  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2649  SDValue FpToInt32 =
2650  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2651 
2652  return FpToInt32;
2653  }
2654 
2655  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2656  return LowerFP64_TO_INT(Op, DAG, true);
2657 
2658  return SDValue();
2659 }
2660 
2662  SelectionDAG &DAG) const {
2663  SDValue Src = Op.getOperand(0);
2664 
2665  // TODO: Factor out code common with LowerFP_TO_SINT.
2666 
2667  EVT SrcVT = Src.getValueType();
2668  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2669  SDLoc DL(Op);
2670 
2671  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2672  SDValue FpToInt32 =
2673  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2674 
2675  return FpToInt32;
2676  }
2677 
2678  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2679  return LowerFP64_TO_INT(Op, DAG, false);
2680 
2681  return SDValue();
2682 }
2683 
2685  SelectionDAG &DAG) const {
2686  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2687  MVT VT = Op.getSimpleValueType();
2688  MVT ScalarVT = VT.getScalarType();
2689 
2690  assert(VT.isVector());
2691 
2692  SDValue Src = Op.getOperand(0);
2693  SDLoc DL(Op);
2694 
2695  // TODO: Don't scalarize on Evergreen?
2696  unsigned NElts = VT.getVectorNumElements();
2698  DAG.ExtractVectorElements(Src, Args, 0, NElts);
2699 
2700  SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2701  for (unsigned I = 0; I < NElts; ++I)
2702  Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2703 
2704  return DAG.getBuildVector(VT, DL, Args);
2705 }
2706 
2707 //===----------------------------------------------------------------------===//
2708 // Custom DAG optimizations
2709 //===----------------------------------------------------------------------===//
2710 
2711 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2712  return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2713 }
2714 
2715 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2716  EVT VT = Op.getValueType();
2717  return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2718  // as unsigned 24-bit values.
2720 }
2721 
2722 static bool simplifyI24(SDNode *Node24, unsigned OpIdx,
2724 
2725  SelectionDAG &DAG = DCI.DAG;
2726  SDValue Op = Node24->getOperand(OpIdx);
2727  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2728  EVT VT = Op.getValueType();
2729 
2730  APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2731  APInt KnownZero, KnownOne;
2732  TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2733  if (TLI.SimplifyDemandedBits(Node24, OpIdx, Demanded, DCI, TLO))
2734  return true;
2735 
2736  return false;
2737 }
2738 
2739 template <typename IntTy>
2741  uint32_t Width, const SDLoc &DL) {
2742  if (Width + Offset < 32) {
2743  uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2744  IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2745  return DAG.getConstant(Result, DL, MVT::i32);
2746  }
2747 
2748  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2749 }
2750 
2751 static bool hasVolatileUser(SDNode *Val) {
2752  for (SDNode *U : Val->uses()) {
2753  if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2754  if (M->isVolatile())
2755  return true;
2756  }
2757  }
2758 
2759  return false;
2760 }
2761 
2763  // i32 vectors are the canonical memory type.
2764  if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2765  return false;
2766 
2767  if (!VT.isByteSized())
2768  return false;
2769 
2770  unsigned Size = VT.getStoreSize();
2771 
2772  if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2773  return false;
2774 
2775  if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2776  return false;
2777 
2778  return true;
2779 }
2780 
2781 // Replace load of an illegal type with a store of a bitcast to a friendlier
2782 // type.
2784  DAGCombinerInfo &DCI) const {
2785  if (!DCI.isBeforeLegalize())
2786  return SDValue();
2787 
2788  LoadSDNode *LN = cast<LoadSDNode>(N);
2789  if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2790  return SDValue();
2791 
2792  SDLoc SL(N);
2793  SelectionDAG &DAG = DCI.DAG;
2794  EVT VT = LN->getMemoryVT();
2795 
2796  unsigned Size = VT.getStoreSize();
2797  unsigned Align = LN->getAlignment();
2798  if (Align < Size && isTypeLegal(VT)) {
2799  bool IsFast;
2800  unsigned AS = LN->getAddressSpace();
2801 
2802  // Expand unaligned loads earlier than legalization. Due to visitation order
2803  // problems during legalization, the emitted instructions to pack and unpack
2804  // the bytes again are not eliminated in the case of an unaligned copy.
2805  if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2806  if (VT.isVector())
2807  return scalarizeVectorLoad(LN, DAG);
2808 
2809  SDValue Ops[2];
2810  std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2811  return DAG.getMergeValues(Ops, SDLoc(N));
2812  }
2813 
2814  if (!IsFast)
2815  return SDValue();
2816  }
2817 
2818  if (!shouldCombineMemoryType(VT))
2819  return SDValue();
2820 
2821  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2822 
2823  SDValue NewLoad
2824  = DAG.getLoad(NewVT, SL, LN->getChain(),
2825  LN->getBasePtr(), LN->getMemOperand());
2826 
2827  SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2828  DCI.CombineTo(N, BC, NewLoad.getValue(1));
2829  return SDValue(N, 0);
2830 }
2831 
2832 // Replace store of an illegal type with a store of a bitcast to a friendlier
2833 // type.
2835  DAGCombinerInfo &DCI) const {
2836  if (!DCI.isBeforeLegalize())
2837  return SDValue();
2838 
2839  StoreSDNode *SN = cast<StoreSDNode>(N);
2840  if (SN->isVolatile() || !ISD::isNormalStore(SN))
2841  return SDValue();
2842 
2843  EVT VT = SN->getMemoryVT();
2844  unsigned Size = VT.getStoreSize();
2845 
2846  SDLoc SL(N);
2847  SelectionDAG &DAG = DCI.DAG;
2848  unsigned Align = SN->getAlignment();
2849  if (Align < Size && isTypeLegal(VT)) {
2850  bool IsFast;
2851  unsigned AS = SN->getAddressSpace();
2852 
2853  // Expand unaligned stores earlier than legalization. Due to visitation
2854  // order problems during legalization, the emitted instructions to pack and
2855  // unpack the bytes again are not eliminated in the case of an unaligned
2856  // copy.
2857  if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2858  if (VT.isVector())
2859  return scalarizeVectorStore(SN, DAG);
2860 
2861  return expandUnalignedStore(SN, DAG);
2862  }
2863 
2864  if (!IsFast)
2865  return SDValue();
2866  }
2867 
2868  if (!shouldCombineMemoryType(VT))
2869  return SDValue();
2870 
2871  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2872  SDValue Val = SN->getValue();
2873 
2874  //DCI.AddToWorklist(Val.getNode());
2875 
2876  bool OtherUses = !Val.hasOneUse();
2877  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2878  if (OtherUses) {
2879  SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2880  DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2881  }
2882 
2883  return DAG.getStore(SN->getChain(), SL, CastVal,
2884  SN->getBasePtr(), SN->getMemOperand());
2885 }
2886 
2887 // FIXME: This should go in generic DAG combiner with an isTruncateFree check,
2888 // but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
2889 // issues.
2891  DAGCombinerInfo &DCI) const {
2892  SelectionDAG &DAG = DCI.DAG;
2893  SDValue N0 = N->getOperand(0);
2894 
2895  // (vt2 (assertzext (truncate vt0:x), vt1)) ->
2896  // (vt2 (truncate (assertzext vt0:x, vt1)))
2897  if (N0.getOpcode() == ISD::TRUNCATE) {
2898  SDValue N1 = N->getOperand(1);
2899  EVT ExtVT = cast<VTSDNode>(N1)->getVT();
2900  SDLoc SL(N);
2901 
2902  SDValue Src = N0.getOperand(0);
2903  EVT SrcVT = Src.getValueType();
2904  if (SrcVT.bitsGE(ExtVT)) {
2905  SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
2906  return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
2907  }
2908  }
2909 
2910  return SDValue();
2911 }
2912 /// Split the 64-bit value \p LHS into two 32-bit components, and perform the
2913 /// binary operation \p Opc to it with the corresponding constant operands.
2915  DAGCombinerInfo &DCI, const SDLoc &SL,
2916  unsigned Opc, SDValue LHS,
2917  uint32_t ValLo, uint32_t ValHi) const {
2918  SelectionDAG &DAG = DCI.DAG;
2919  SDValue Lo, Hi;
2920  std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
2921 
2922  SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
2923  SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
2924 
2925  SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
2926  SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
2927 
2928  // Re-visit the ands. It's possible we eliminated one of them and it could
2929  // simplify the vector.
2930  DCI.AddToWorklist(Lo.getNode());
2931  DCI.AddToWorklist(Hi.getNode());
2932 
2933  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
2934  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2935 }
2936 
2938  DAGCombinerInfo &DCI) const {
2939  EVT VT = N->getValueType(0);
2940 
2942  if (!RHS)
2943  return SDValue();
2944 
2945  SDValue LHS = N->getOperand(0);
2946  unsigned RHSVal = RHS->getZExtValue();
2947  if (!RHSVal)
2948  return LHS;
2949 
2950  SDLoc SL(N);
2951  SelectionDAG &DAG = DCI.DAG;
2952 
2953  switch (LHS->getOpcode()) {
2954  default:
2955  break;
2956  case ISD::ZERO_EXTEND:
2957  case ISD::SIGN_EXTEND:
2958  case ISD::ANY_EXTEND: {
2959  SDValue X = LHS->getOperand(0);
2960 
2961  if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
2963  // Prefer build_vector as the canonical form if packed types are legal.
2964  // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
2965  SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
2966  { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
2967  return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
2968  }
2969 
2970  // shl (ext x) => zext (shl x), if shift does not overflow int
2971  if (VT != MVT::i64)
2972  break;
2973  KnownBits Known;
2974  DAG.computeKnownBits(X, Known);
2975  unsigned LZ = Known.countMinLeadingZeros();
2976  if (LZ < RHSVal)
2977  break;
2978  EVT XVT = X.getValueType();
2979  SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
2980  return DAG.getZExtOrTrunc(Shl, SL, VT);
2981  }
2982  }
2983 
2984  if (VT != MVT::i64)
2985  return SDValue();
2986 
2987  // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
2988 
2989  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
2990  // common case, splitting this into a move and a 32-bit shift is faster and
2991  // the same code size.
2992  if (RHSVal < 32)
2993  return SDValue();
2994 
2995  SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
2996 
2997  SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2998  SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
2999 
3000  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3001 
3002  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3003  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3004 }
3005 
3007  DAGCombinerInfo &DCI) const {
3008  if (N->getValueType(0) != MVT::i64)
3009  return SDValue();
3010 
3011  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3012  if (!RHS)
3013  return SDValue();
3014 
3015  SelectionDAG &DAG = DCI.DAG;
3016  SDLoc SL(N);
3017  unsigned RHSVal = RHS->getZExtValue();
3018 
3019  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3020  if (RHSVal == 32) {
3021  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3022  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3023  DAG.getConstant(31, SL, MVT::i32));
3024 
3025  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3026  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3027  }
3028 
3029  // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3030  if (RHSVal == 63) {
3031  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3032  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3033  DAG.getConstant(31, SL, MVT::i32));
3034  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3035  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3036  }
3037 
3038  return SDValue();
3039 }
3040 
3042  DAGCombinerInfo &DCI) const {
3043  if (N->getValueType(0) != MVT::i64)
3044  return SDValue();
3045 
3046  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3047  if (!RHS)
3048  return SDValue();
3049 
3050  unsigned ShiftAmt = RHS->getZExtValue();
3051  if (ShiftAmt < 32)
3052  return SDValue();
3053 
3054  // srl i64:x, C for C >= 32
3055  // =>
3056  // build_pair (srl hi_32(x), C - 32), 0
3057 
3058  SelectionDAG &DAG = DCI.DAG;
3059  SDLoc SL(N);
3060 
3061  SDValue One = DAG.getConstant(1, SL, MVT::i32);
3062  SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3063 
3064  SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
3066  VecOp, One);
3067 
3068  SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3069  SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3070 
3071  SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3072 
3073  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3074 }
3075 
3077  SDNode *N, DAGCombinerInfo &DCI) const {
3078  SDLoc SL(N);
3079  SelectionDAG &DAG = DCI.DAG;
3080  EVT VT = N->getValueType(0);
3081  SDValue Src = N->getOperand(0);
3082 
3083  // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3084  if (Src.getOpcode() == ISD::BITCAST) {
3085  SDValue Vec = Src.getOperand(0);
3086  if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3087  SDValue Elt0 = Vec.getOperand(0);
3088  EVT EltVT = Elt0.getValueType();
3089  if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3090  if (EltVT.isFloatingPoint()) {
3091  Elt0 = DAG.getNode(ISD::BITCAST, SL,
3092  EltVT.changeTypeToInteger(), Elt0);
3093  }
3094 
3095  return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3096  }
3097  }
3098  }
3099 
3100  // Equivalent of above for accessing the high element of a vector as an
3101  // integer operation.
3102  // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3103  if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3104  if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3105  if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3106  SDValue BV = stripBitcast(Src.getOperand(0));
3107  if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3108  BV.getValueType().getVectorNumElements() == 2) {
3109  SDValue SrcElt = BV.getOperand(1);
3110  EVT SrcEltVT = SrcElt.getValueType();
3111  if (SrcEltVT.isFloatingPoint()) {
3112  SrcElt = DAG.getNode(ISD::BITCAST, SL,
3113  SrcEltVT.changeTypeToInteger(), SrcElt);
3114  }
3115 
3116  return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3117  }
3118  }
3119  }
3120  }
3121 
3122  // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3123  //
3124  // i16 (trunc (srl i64:x, K)), K <= 16 ->
3125  // i16 (trunc (srl (i32 (trunc x), K)))
3126  if (VT.getScalarSizeInBits() < 32) {
3127  EVT SrcVT = Src.getValueType();
3128  if (SrcVT.getScalarSizeInBits() > 32 &&
3129  (Src.getOpcode() == ISD::SRL ||
3130  Src.getOpcode() == ISD::SRA ||
3131  Src.getOpcode() == ISD::SHL)) {
3132  SDValue Amt = Src.getOperand(1);
3133  KnownBits Known;
3134  DAG.computeKnownBits(Amt, Known);
3135  unsigned Size = VT.getScalarSizeInBits();
3136  if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3137  (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3138  EVT MidVT = VT.isVector() ?
3141 
3142  EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3143  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3144  Src.getOperand(0));
3145  DCI.AddToWorklist(Trunc.getNode());
3146 
3147  if (Amt.getValueType() != NewShiftVT) {
3148  Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3149  DCI.AddToWorklist(Amt.getNode());
3150  }
3151 
3152  SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3153  Trunc, Amt);
3154  return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3155  }
3156  }
3157  }
3158 
3159  return SDValue();
3160 }
3161 
3162 // We need to specifically handle i64 mul here to avoid unnecessary conversion
3163 // instructions. If we only match on the legalized i64 mul expansion,
3164 // SimplifyDemandedBits will be unable to remove them because there will be
3165 // multiple uses due to the separate mul + mulh[su].
3166 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3167  SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3168  if (Size <= 32) {
3169  unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3170  return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3171  }
3172 
3173  // Because we want to eliminate extension instructions before the
3174  // operation, we need to create a single user here (i.e. not the separate
3175  // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3176 
3177  unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
3178 
3179  SDValue Mul = DAG.getNode(MulOpc, SL,
3180  DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3181 
3182  return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3183  Mul.getValue(0), Mul.getValue(1));
3184 }
3185 
3187  DAGCombinerInfo &DCI) const {
3188  EVT VT = N->getValueType(0);
3189 
3190  unsigned Size = VT.getSizeInBits();
3191  if (VT.isVector() || Size > 64)
3192  return SDValue();
3193 
3194  // There are i16 integer mul/mad.
3195  if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3196  return SDValue();
3197 
3198  SelectionDAG &DAG = DCI.DAG;
3199  SDLoc DL(N);
3200 
3201  SDValue N0 = N->getOperand(0);
3202  SDValue N1 = N->getOperand(1);
3203 
3204  // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3205  // in the source into any_extends if the result of the mul is truncated. Since
3206  // we can assume the high bits are whatever we want, use the underlying value
3207  // to avoid the unknown high bits from interfering.
3208  if (N0.getOpcode() == ISD::ANY_EXTEND)
3209  N0 = N0.getOperand(0);
3210 
3211  if (N1.getOpcode() == ISD::ANY_EXTEND)
3212  N1 = N1.getOperand(0);
3213 
3214  SDValue Mul;
3215 
3216  if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3217  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3218  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3219  Mul = getMul24(DAG, DL, N0, N1, Size, false);
3220  } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3221  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3222  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3223  Mul = getMul24(DAG, DL, N0, N1, Size, true);
3224  } else {
3225  return SDValue();
3226  }
3227 
3228  // We need to use sext even for MUL_U24, because MUL_U24 is used
3229  // for signed multiply of 8 and 16-bit types.
3230  return DAG.getSExtOrTrunc(Mul, DL, VT);
3231 }
3232 
3234  DAGCombinerInfo &DCI) const {
3235  EVT VT = N->getValueType(0);
3236 
3237  if (!Subtarget->hasMulI24() || VT.isVector())
3238  return SDValue();
3239 
3240  SelectionDAG &DAG = DCI.DAG;
3241  SDLoc DL(N);
3242 
3243  SDValue N0 = N->getOperand(0);
3244  SDValue N1 = N->getOperand(1);
3245 
3246  if (!isI24(N0, DAG) || !isI24(N1, DAG))
3247  return SDValue();
3248 
3249  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3250  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3251 
3252  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3253  DCI.AddToWorklist(Mulhi.getNode());
3254  return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3255 }
3256 
3258  DAGCombinerInfo &DCI) const {
3259  EVT VT = N->getValueType(0);
3260 
3261  if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3262  return SDValue();
3263 
3264  SelectionDAG &DAG = DCI.DAG;
3265  SDLoc DL(N);
3266 
3267  SDValue N0 = N->getOperand(0);
3268  SDValue N1 = N->getOperand(1);
3269 
3270  if (!isU24(N0, DAG) || !isU24(N1, DAG))
3271  return SDValue();
3272 
3273  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3274  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3275 
3276  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3277  DCI.AddToWorklist(Mulhi.getNode());
3278  return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3279 }
3280 
3282  SDNode *N, DAGCombinerInfo &DCI) const {
3283  SelectionDAG &DAG = DCI.DAG;
3284 
3285  // Simplify demanded bits before splitting into multiple users.
3286  if (simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI))
3287  return SDValue();
3288 
3289  SDValue N0 = N->getOperand(0);
3290  SDValue N1 = N->getOperand(1);
3291 
3292  bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3293 
3294  unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3295  unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3296 
3297  SDLoc SL(N);
3298 
3299  SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3300  SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3301  return DAG.getMergeValues({ MulLo, MulHi }, SL);
3302 }
3303 
3304 static bool isNegativeOne(SDValue Val) {
3305  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3306  return C->isAllOnesValue();
3307  return false;
3308 }
3309 
3310 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3311  SDValue Op,
3312  const SDLoc &DL,
3313  unsigned Opc) const {
3314  EVT VT = Op.getValueType();
3315  EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3316  if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3317  LegalVT != MVT::i16))
3318  return SDValue();
3319 
3320  if (VT != MVT::i32)
3321  Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3322 
3323  SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3324  if (VT != MVT::i32)
3325  FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3326 
3327  return FFBX;
3328 }
3329 
3330 // The native instructions return -1 on 0 input. Optimize out a select that
3331 // produces -1 on 0.
3332 //
3333 // TODO: If zero is not undef, we could also do this if the output is compared
3334 // against the bitwidth.
3335 //
3336 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3338  SDValue LHS, SDValue RHS,
3339  DAGCombinerInfo &DCI) const {
3340  ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3341  if (!CmpRhs || !CmpRhs->isNullValue())
3342  return SDValue();
3343 
3344  SelectionDAG &DAG = DCI.DAG;
3345  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3346  SDValue CmpLHS = Cond.getOperand(0);
3347 
3348  unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3350 
3351  // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3352  // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3353  if (CCOpcode == ISD::SETEQ &&
3354  (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3355  RHS.getOperand(0) == CmpLHS &&
3356  isNegativeOne(LHS)) {
3357  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3358  }
3359 
3360  // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3361  // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3362  if (CCOpcode == ISD::SETNE &&
3363  (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3364  LHS.getOperand(0) == CmpLHS &&
3365  isNegativeOne(RHS)) {
3366  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3367  }
3368 
3369  return SDValue();
3370 }
3371 
3373  unsigned Op,
3374  const SDLoc &SL,
3375  SDValue Cond,
3376  SDValue N1,
3377  SDValue N2) {
3378  SelectionDAG &DAG = DCI.DAG;
3379  EVT VT = N1.getValueType();
3380 
3381  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3382  N1.getOperand(0), N2.getOperand(0));
3383  DCI.AddToWorklist(NewSelect.getNode());
3384  return DAG.getNode(Op, SL, VT, NewSelect);
3385 }
3386 
3387 // Pull a free FP operation out of a select so it may fold into uses.
3388 //
3389 // select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3390 // select c, (fneg x), k -> fneg (select c, x, (fneg k))
3391 //
3392 // select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3393 // select c, (fabs x), +k -> fabs (select c, x, k)
3395  SDValue N) {
3396  SelectionDAG &DAG = DCI.DAG;
3397  SDValue Cond = N.getOperand(0);
3398  SDValue LHS = N.getOperand(1);
3399  SDValue RHS = N.getOperand(2);
3400 
3401  EVT VT = N.getValueType();
3402  if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3403  (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3404  return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3405  SDLoc(N), Cond, LHS, RHS);
3406  }
3407 
3408  bool Inv = false;
3409  if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3410  std::swap(LHS, RHS);
3411  Inv = true;
3412  }
3413 
3414  // TODO: Support vector constants.
3416  if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3417  SDLoc SL(N);
3418  // If one side is an fneg/fabs and the other is a constant, we can push the
3419  // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3420  SDValue NewLHS = LHS.getOperand(0);
3421  SDValue NewRHS = RHS;
3422 
3423  // Careful: if the neg can be folded up, don't try to pull it back down.
3424  bool ShouldFoldNeg = true;
3425 
3426  if (NewLHS.hasOneUse()) {
3427  unsigned Opc = NewLHS.getOpcode();
3428  if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3429  ShouldFoldNeg = false;
3430  if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3431  ShouldFoldNeg = false;
3432  }
3433 
3434  if (ShouldFoldNeg) {
3435  if (LHS.getOpcode() == ISD::FNEG)
3436  NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3437  else if (CRHS->isNegative())
3438  return SDValue();
3439 
3440  if (Inv)
3441  std::swap(NewLHS, NewRHS);
3442 
3443  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3444  Cond, NewLHS, NewRHS);
3445  DCI.AddToWorklist(NewSelect.getNode());
3446  return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3447  }
3448  }
3449 
3450  return SDValue();
3451 }
3452 
3453 
3455  DAGCombinerInfo &DCI) const {
3456  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3457  return Folded;
3458 
3459  SDValue Cond = N->getOperand(0);
3460  if (Cond.getOpcode() != ISD::SETCC)
3461  return SDValue();
3462 
3463  EVT VT = N->getValueType(0);
3464  SDValue LHS = Cond.getOperand(0);
3465  SDValue RHS = Cond.getOperand(1);
3466  SDValue CC = Cond.getOperand(2);
3467 
3468  SDValue True = N->getOperand(1);
3469  SDValue False = N->getOperand(2);
3470 
3471  if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3472  SelectionDAG &DAG = DCI.DAG;
3473  if ((DAG.isConstantValueOfAnyType(True) ||
3474  DAG.isConstantValueOfAnyType(True)) &&
3475  (!DAG.isConstantValueOfAnyType(False) &&
3476  !DAG.isConstantValueOfAnyType(False))) {
3477  // Swap cmp + select pair to move constant to false input.
3478  // This will allow using VOPC cndmasks more often.
3479  // select (setcc x, y), k, x -> select (setcc y, x) x, x
3480 
3481  SDLoc SL(N);
3482  ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3483  LHS.getValueType().isInteger());
3484 
3485  SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3486  return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3487  }
3488 
3489  if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3490  SDValue MinMax
3491  = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3492  // Revisit this node so we can catch min3/max3/med3 patterns.
3493  //DCI.AddToWorklist(MinMax.getNode());
3494  return MinMax;
3495  }
3496  }
3497 
3498  // There's no reason to not do this if the condition has other uses.
3499  return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3500 }
3501 
3502 static bool isInv2Pi(const APFloat &APF) {
3503  static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3504  static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3505  static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3506 
3507  return APF.bitwiseIsEqual(KF16) ||
3508  APF.bitwiseIsEqual(KF32) ||
3509  APF.bitwiseIsEqual(KF64);
3510 }
3511 
3512 // 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3513 // additional cost to negate them.
3515  if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3516  if (C->isZero() && !C->isNegative())
3517  return true;
3518 
3519  if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3520  return true;
3521  }
3522 
3523  return false;
3524 }
3525 
3526 static unsigned inverseMinMax(unsigned Opc) {
3527  switch (Opc) {
3528  case ISD::FMAXNUM:
3529  return ISD::FMINNUM;
3530  case ISD::FMINNUM:
3531  return ISD::FMAXNUM;
3532  case ISD::FMAXNUM_IEEE:
3533  return ISD::FMINNUM_IEEE;
3534  case ISD::FMINNUM_IEEE:
3535  return ISD::FMAXNUM_IEEE;
3537  return AMDGPUISD::FMIN_LEGACY;
3539  return AMDGPUISD::FMAX_LEGACY;
3540  default:
3541  llvm_unreachable("invalid min/max opcode");
3542  }
3543 }
3544 
3546  DAGCombinerInfo &DCI) const {
3547  SelectionDAG &DAG = DCI.DAG;
3548  SDValue N0 = N->getOperand(0);
3549  EVT VT = N->getValueType(0);
3550 
3551  unsigned Opc = N0.getOpcode();
3552 
3553  // If the input has multiple uses and we can either fold the negate down, or
3554  // the other uses cannot, give up. This both prevents unprofitable
3555  // transformations and infinite loops: we won't repeatedly try to fold around
3556  // a negate that has no 'good' form.
3557  if (N0.hasOneUse()) {
3558  // This may be able to fold into the source, but at a code size cost. Don't
3559  // fold if the fold into the user is free.
3560  if (allUsesHaveSourceMods(N, 0))
3561  return SDValue();
3562  } else {
3563  if (fnegFoldsIntoOp(Opc) &&
3565  return SDValue();
3566  }
3567 
3568  SDLoc SL(N);
3569  switch (Opc) {
3570  case ISD::FADD: {
3571  if (!mayIgnoreSignedZero(N0))
3572  return SDValue();
3573 
3574  // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3575  SDValue LHS = N0.getOperand(0);
3576  SDValue RHS = N0.getOperand(1);
3577 
3578  if (LHS.getOpcode() != ISD::FNEG)
3579  LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3580  else
3581  LHS = LHS.getOperand(0);
3582 
3583  if (RHS.getOpcode() != ISD::FNEG)
3584  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3585  else
3586  RHS = RHS.getOperand(0);
3587 
3588  SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3589  if (!N0.hasOneUse())
3590  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3591  return Res;
3592  }
3593  case ISD::FMUL:
3594  case AMDGPUISD::FMUL_LEGACY: {
3595  // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3596  // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3597  SDValue LHS = N0.getOperand(0);
3598  SDValue RHS = N0.getOperand(1);
3599 
3600  if (LHS.getOpcode() == ISD::FNEG)
3601  LHS = LHS.getOperand(0);
3602  else if (RHS.getOpcode() == ISD::FNEG)
3603  RHS = RHS.getOperand(0);
3604  else
3605  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3606 
3607  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3608  if (!N0.hasOneUse())
3609  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3610  return Res;
3611  }
3612  case ISD::FMA:
3613  case ISD::FMAD: {
3614  if (!mayIgnoreSignedZero(N0))
3615  return SDValue();
3616 
3617  // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3618  SDValue LHS = N0.getOperand(0);
3619  SDValue MHS = N0.getOperand(1);
3620  SDValue RHS = N0.getOperand(2);
3621 
3622  if (LHS.getOpcode() == ISD::FNEG)
3623  LHS = LHS.getOperand(0);
3624  else if (MHS.getOpcode() == ISD::FNEG)
3625  MHS = MHS.getOperand(0);
3626  else
3627  MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3628 
3629  if (RHS.getOpcode() != ISD::FNEG)
3630  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3631  else
3632  RHS = RHS.getOperand(0);
3633 
3634  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3635  if (!N0.hasOneUse())
3636  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3637  return Res;
3638  }
3639  case ISD::FMAXNUM:
3640  case ISD::FMINNUM:
3641  case ISD::FMAXNUM_IEEE:
3642  case ISD::FMINNUM_IEEE:
3644  case AMDGPUISD::FMIN_LEGACY: {
3645  // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3646  // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3647  // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3648  // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3649 
3650  SDValue LHS = N0.getOperand(0);
3651  SDValue RHS = N0.getOperand(1);
3652 
3653  // 0 doesn't have a negated inline immediate.
3654  // TODO: This constant check should be generalized to other operations.
3655  if (isConstantCostlierToNegate(RHS))
3656  return SDValue();
3657 
3658  SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3659  SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3660  unsigned Opposite = inverseMinMax(Opc);
3661 
3662  SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3663  if (!N0.hasOneUse())
3664  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3665  return Res;
3666  }
3667  case AMDGPUISD::FMED3: {
3668  SDValue Ops[3];
3669  for (unsigned I = 0; I < 3; ++I)
3670  Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3671 
3672  SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3673  if (!N0.hasOneUse())
3674  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3675  return Res;
3676  }
3677  case ISD::FP_EXTEND:
3678  case ISD::FTRUNC:
3679  case ISD::FRINT:
3680  case ISD::FNEARBYINT: // XXX - Should fround be handled?
3681  case ISD::FSIN:
3682  case ISD::FCANONICALIZE:
3683  case AMDGPUISD::RCP:
3684  case AMDGPUISD::RCP_LEGACY:
3685  case AMDGPUISD::RCP_IFLAG:
3686  case AMDGPUISD::SIN_HW: {
3687  SDValue CvtSrc = N0.getOperand(0);
3688  if (CvtSrc.getOpcode() == ISD::FNEG) {
3689  // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3690  // (fneg (rcp (fneg x))) -> (rcp x)
3691  return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3692  }
3693 
3694  if (!N0.hasOneUse())
3695  return SDValue();
3696 
3697  // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3698  // (fneg (rcp x)) -> (rcp (fneg x))
3699  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3700  return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3701  }
3702  case ISD::FP_ROUND: {
3703  SDValue CvtSrc = N0.getOperand(0);
3704 
3705  if (CvtSrc.getOpcode() == ISD::FNEG) {
3706  // (fneg (fp_round (fneg x))) -> (fp_round x)
3707  return DAG.getNode(ISD::FP_ROUND, SL, VT,
3708  CvtSrc.getOperand(0), N0.getOperand(1));
3709  }
3710 
3711  if (!N0.hasOneUse())
3712  return SDValue();
3713 
3714  // (fneg (fp_round x)) -> (fp_round (fneg x))
3715  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3716  return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3717  }
3718  case ISD::FP16_TO_FP: {
3719  // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3720  // f16, but legalization of f16 fneg ends up pulling it out of the source.
3721  // Put the fneg back as a legal source operation that can be matched later.
3722  SDLoc SL(N);
3723 
3724  SDValue Src = N0.getOperand(0);
3725  EVT SrcVT = Src.getValueType();
3726 
3727  // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3728  SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3729  DAG.getConstant(0x8000, SL, SrcVT));
3730  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3731  }
3732  default:
3733  return SDValue();
3734  }
3735 }
3736 
3738  DAGCombinerInfo &DCI) const {
3739  SelectionDAG &DAG = DCI.DAG;
3740  SDValue N0 = N->getOperand(0);
3741 
3742  if (!N0.hasOneUse())
3743  return SDValue();
3744 
3745  switch (N0.getOpcode()) {
3746  case ISD::FP16_TO_FP: {
3747  assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3748  SDLoc SL(N);
3749  SDValue Src = N0.getOperand(0);
3750  EVT SrcVT = Src.getValueType();
3751 
3752  // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3753  SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3754  DAG.getConstant(0x7fff, SL, SrcVT));
3755  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3756  }
3757  default:
3758  return SDValue();
3759  }
3760 }
3761 
3763  DAGCombinerInfo &DCI) const {
3764  const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3765  if (!CFP)
3766  return SDValue();
3767 
3768  // XXX - Should this flush denormals?
3769  const APFloat &Val = CFP->getValueAPF();
3770  APFloat One(Val.getSemantics(), "1.0");
3771  return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3772 }
3773 
3775  DAGCombinerInfo &DCI) const {
3776  SelectionDAG &DAG = DCI.DAG;
3777  SDLoc DL(N);
3778 
3779  switch(N->getOpcode()) {
3780  default:
3781  break;
3782  case ISD::BITCAST: {
3783  EVT DestVT = N->getValueType(0);
3784 
3785  // Push casts through vector builds. This helps avoid emitting a large
3786  // number of copies when materializing floating point vector constants.
3787  //
3788  // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3789  // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3790  if (DestVT.isVector()) {
3791  SDValue Src = N->getOperand(0);
3792  if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3793  EVT SrcVT = Src.getValueType();
3794  unsigned NElts = DestVT.getVectorNumElements();
3795 
3796  if (SrcVT.getVectorNumElements() == NElts) {
3797  EVT DestEltVT = DestVT.getVectorElementType();
3798 
3799  SmallVector<SDValue, 8> CastedElts;
3800  SDLoc SL(N);
3801  for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3802  SDValue Elt = Src.getOperand(I);
3803  CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3804  }
3805 
3806  return DAG.getBuildVector(DestVT, SL, CastedElts);
3807  }
3808  }
3809  }
3810 
3811  if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
3812  break;
3813 
3814  // Fold bitcasts of constants.
3815  //
3816  // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3817  // TODO: Generalize and move to DAGCombiner
3818  SDValue Src = N->getOperand(0);
3819  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3820  if (Src.getValueType() == MVT::i64) {
3821  SDLoc SL(N);
3822  uint64_t CVal = C->getZExtValue();
3824  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3825  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3826  return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
3827  }
3828  }
3829 
3830  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3831  const APInt &Val = C->getValueAPF().bitcastToAPInt();
3832  SDLoc SL(N);
3833  uint64_t CVal = Val.getZExtValue();
3835  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3836  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3837 
3838  return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3839  }
3840 
3841  break;
3842  }
3843  case ISD::SHL: {
3845  break;
3846 
3847  return performShlCombine(N, DCI);
3848  }
3849  case ISD::SRL: {
3851  break;
3852 
3853  return performSrlCombine(N, DCI);
3854  }
3855  case ISD::SRA: {
3857  break;
3858 
3859  return performSraCombine(N, DCI);
3860  }
3861  case ISD::TRUNCATE:
3862  return performTruncateCombine(N, DCI);
3863  case ISD::MUL:
3864  return performMulCombine(N, DCI);
3865  case ISD::MULHS:
3866  return performMulhsCombine(N, DCI);
3867  case ISD::MULHU:
3868  return performMulhuCombine(N, DCI);
3869  case AMDGPUISD::MUL_I24:
3870  case AMDGPUISD::MUL_U24:
3871  case AMDGPUISD::MULHI_I24:
3872  case AMDGPUISD::MULHI_U24: {
3873  // If the first call to simplify is successfull, then N may end up being
3874  // deleted, so we shouldn't call simplifyI24 again.
3875  simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI);
3876  return SDValue();
3877  }
3880  return performMulLoHi24Combine(N, DCI);
3881  case ISD::SELECT:
3882  return performSelectCombine(N, DCI);
3883  case ISD::FNEG:
3884  return performFNegCombine(N, DCI);
3885  case ISD::FABS:
3886  return performFAbsCombine(N, DCI);
3887  case AMDGPUISD::BFE_I32:
3888  case AMDGPUISD::BFE_U32: {
3889  assert(!N->getValueType(0).isVector() &&
3890  "Vector handling of BFE not implemented");
3892  if (!Width)
3893  break;
3894 
3895  uint32_t WidthVal = Width->getZExtValue() & 0x1f;
3896  if (WidthVal == 0)
3897  return DAG.getConstant(0, DL, MVT::i32);
3898 
3900  if (!Offset)
3901  break;
3902 
3903  SDValue BitsFrom = N->getOperand(0);
3904  uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
3905 
3906  bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
3907 
3908  if (OffsetVal == 0) {
3909  // This is already sign / zero extended, so try to fold away extra BFEs.
3910  unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
3911 
3912  unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
3913  if (OpSignBits >= SignBits)
3914  return BitsFrom;
3915 
3916  EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
3917  if (Signed) {
3918  // This is a sign_extend_inreg. Replace it to take advantage of existing
3919  // DAG Combines. If not eliminated, we will match back to BFE during
3920  // selection.
3921 
3922  // TODO: The sext_inreg of extended types ends, although we can could
3923  // handle them in a single BFE.
3924  return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
3925  DAG.getValueType(SmallVT));
3926  }
3927 
3928  return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
3929  }
3930 
3931  if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
3932  if (Signed) {
3933  return constantFoldBFE<int32_t>(DAG,
3934  CVal->getSExtValue(),
3935  OffsetVal,
3936  WidthVal,
3937  DL);
3938  }
3939 
3940  return constantFoldBFE<uint32_t>(DAG,
3941  CVal->getZExtValue(),
3942  OffsetVal,
3943  WidthVal,
3944  DL);
3945  }
3946 
3947  if ((OffsetVal + WidthVal) >= 32 &&
3948  !(Subtarget->hasSDWA() && OffsetVal == 16 && WidthVal == 16)) {
3949  SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
3950  return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
3951  BitsFrom, ShiftVal);
3952  }
3953 
3954  if (BitsFrom.hasOneUse()) {
3955  APInt Demanded = APInt::getBitsSet(32,
3956  OffsetVal,
3957  OffsetVal + WidthVal);
3958 
3959  KnownBits Known;
3961  !DCI.isBeforeLegalizeOps());
3962  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3963  if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
3964  TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
3965  DCI.CommitTargetLoweringOpt(TLO);
3966  }
3967  }
3968 
3969  break;
3970  }
3971  case ISD::LOAD:
3972  return performLoadCombine(N, DCI);
3973  case ISD::STORE:
3974  return performStoreCombine(N, DCI);
3975  case AMDGPUISD::RCP:
3976  case AMDGPUISD::RCP_IFLAG:
3977  return performRcpCombine(N, DCI);
3978  case ISD::AssertZext:
3979  case ISD::AssertSext:
3980  return performAssertSZExtCombine(N, DCI);
3981  }
3982  return SDValue();
3983 }
3984 
3985 //===----------------------------------------------------------------------===//
3986 // Helper functions
3987 //===----------------------------------------------------------------------===//
3988 
3990  const TargetRegisterClass *RC,
3991  unsigned Reg, EVT VT,
3992  const SDLoc &SL,
3993  bool RawReg) const {
3994  MachineFunction &MF = DAG.getMachineFunction();
3996  unsigned VReg;
3997 
3998  if (!MRI.isLiveIn(Reg)) {
3999  VReg = MRI.createVirtualRegister(RC);
4000  MRI.addLiveIn(Reg, VReg);
4001  } else {
4002  VReg = MRI.getLiveInVirtReg(Reg);
4003  }
4004 
4005  if (RawReg)
4006  return DAG.getRegister(VReg, VT);
4007 
4008  return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4009 }
4010 
4012  EVT VT,
4013  const SDLoc &SL,
4014  int64_t Offset) const {
4015  MachineFunction &MF = DAG.getMachineFunction();
4016  MachineFrameInfo &MFI = MF.getFrameInfo();
4017 
4018  int FI = MFI.CreateFixedObject(VT.getStoreSize(), Offset, true);
4019  auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4020  SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4021 
4022  return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4,
4025 }
4026 
4028  const SDLoc &SL,
4029  SDValue Chain,
4030  SDValue ArgVal,
4031  int64_t Offset) const {
4032  MachineFunction &MF = DAG.getMachineFunction();
4033  MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4034 
4035  SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4036  SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
4038  return Store;
4039 }
4040 
4042  const TargetRegisterClass *RC,
4043  EVT VT, const SDLoc &SL,
4044  const ArgDescriptor &Arg) const {
4045  assert(Arg && "Attempting to load missing argument");
4046 
4047  if (Arg.isRegister())
4048  return CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL);
4049  return loadStackInputValue(DAG, VT, SL, Arg.getStackOffset());
4050 }
4051 
4053  const MachineFunction &MF, const ImplicitParameter Param) const {
4055  const AMDGPUSubtarget &ST =
4057  unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4058  unsigned Alignment = ST.getAlignmentForImplicitArgPtr();
4059  uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4060  ExplicitArgOffset;
4061  switch (Param) {
4062  case GRID_DIM:
4063  return ArgOffset;
4064  case GRID_OFFSET:
4065  return ArgOffset + 4;
4066  }
4067  llvm_unreachable("unexpected implicit parameter type");
4068 }
4069 
4070 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
4071 
4072 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4073  switch ((AMDGPUISD::NodeType)Opcode) {
4074  case AMDGPUISD::FIRST_NUMBER: break;
4075  // AMDIL DAG nodes
4078 
4079  // AMDGPU DAG nodes