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AMDGPUISelLowering.cpp
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1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This is the parent TargetLowering class for hardware code gen
11 /// targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
16 #define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
17 #define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
18 
19 #include "AMDGPUISelLowering.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUCallLowering.h"
22 #include "AMDGPUFrameLowering.h"
23 #include "AMDGPURegisterInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "AMDGPUTargetMachine.h"
26 #include "Utils/AMDGPUBaseInfo.h"
28 #include "SIInstrInfo.h"
29 #include "SIMachineFunctionInfo.h"
31 #include "llvm/CodeGen/Analysis.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DiagnosticInfo.h"
39 #include "llvm/Support/KnownBits.h"
40 using namespace llvm;
41 
42 static bool allocateCCRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
43  CCValAssign::LocInfo LocInfo,
44  ISD::ArgFlagsTy ArgFlags, CCState &State,
45  const TargetRegisterClass *RC,
46  unsigned NumRegs) {
47  ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs);
48  unsigned RegResult = State.AllocateReg(RegList);
49  if (RegResult == AMDGPU::NoRegister)
50  return false;
51 
52  State.addLoc(CCValAssign::getReg(ValNo, ValVT, RegResult, LocVT, LocInfo));
53  return true;
54 }
55 
56 static bool allocateSGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
57  CCValAssign::LocInfo LocInfo,
58  ISD::ArgFlagsTy ArgFlags, CCState &State) {
59  switch (LocVT.SimpleTy) {
60  case MVT::i64:
61  case MVT::f64:
62  case MVT::v2i32:
63  case MVT::v2f32:
64  case MVT::v4i16:
65  case MVT::v4f16: {
66  // Up to SGPR0-SGPR39
67  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
68  &AMDGPU::SGPR_64RegClass, 20);
69  }
70  default:
71  return false;
72  }
73 }
74 
75 // Allocate up to VGPR31.
76 //
77 // TODO: Since there are no VGPR alignent requirements would it be better to
78 // split into individual scalar registers?
79 static bool allocateVGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
80  CCValAssign::LocInfo LocInfo,
81  ISD::ArgFlagsTy ArgFlags, CCState &State) {
82  switch (LocVT.SimpleTy) {
83  case MVT::i64:
84  case MVT::f64:
85  case MVT::v2i32:
86  case MVT::v2f32:
87  case MVT::v4i16:
88  case MVT::v4f16: {
89  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
90  &AMDGPU::VReg_64RegClass, 31);
91  }
92  case MVT::v4i32:
93  case MVT::v4f32:
94  case MVT::v2i64:
95  case MVT::v2f64: {
96  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
97  &AMDGPU::VReg_128RegClass, 29);
98  }
99  case MVT::v8i32:
100  case MVT::v8f32: {
101  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
102  &AMDGPU::VReg_256RegClass, 25);
103 
104  }
105  case MVT::v16i32:
106  case MVT::v16f32: {
107  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
108  &AMDGPU::VReg_512RegClass, 17);
109 
110  }
111  default:
112  return false;
113  }
114 }
115 
116 #include "AMDGPUGenCallingConv.inc"
117 
118 // Find a larger type to do a load / store of a vector with.
120  unsigned StoreSize = VT.getStoreSizeInBits();
121  if (StoreSize <= 32)
122  return EVT::getIntegerVT(Ctx, StoreSize);
123 
124  assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
125  return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
126 }
127 
129  EVT VT = Op.getValueType();
130  KnownBits Known = DAG.computeKnownBits(Op);
131  return VT.getSizeInBits() - Known.countMinLeadingZeros();
132 }
133 
135  EVT VT = Op.getValueType();
136 
137  // In order for this to be a signed 24-bit value, bit 23, must
138  // be a sign bit.
139  return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
140 }
141 
143  const AMDGPUSubtarget &STI)
144  : TargetLowering(TM), Subtarget(&STI) {
145  // Lower floating point store/load to integer store/load to reduce the number
146  // of patterns in tablegen.
149 
152 
155 
158 
161 
164 
167 
170 
173 
174  // There are no 64-bit extloads. These should be done as a 32-bit extload and
175  // an extension to 64-bit.
176  for (MVT VT : MVT::integer_valuetypes()) {
180  }
181 
182  for (MVT VT : MVT::integer_valuetypes()) {
183  if (VT == MVT::i64)
184  continue;
185 
190 
195 
200  }
201 
202  for (MVT VT : MVT::integer_vector_valuetypes()) {
215  }
216 
221 
226 
231 
234 
237 
240 
243 
246 
249 
252 
255 
258 
263 
268 
273 
276 
279 
282 
285 
286 
291 
294 
295  // This is totally unsupported, just custom lower to produce an error.
297 
298  // Library functions. These default to Expand, but we have instructions
299  // for them.
310 
313 
317 
318 
321 
324 
325  // Expand to fneg + fadd.
327 
338 
342 
343  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
344  for (MVT VT : ScalarIntVTs) {
345  // These should use [SU]DIVREM, so set them to expand
350 
351  // GPU does not have divrem function for signed or unsigned.
354 
355  // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
358 
362 
363  // AMDGPU uses ADDC/SUBC/ADDE/SUBE
368  }
369 
370  // The hardware supports 32-bit ROTR, but not ROTL.
372  setOperationAction(ISD::ROTL, MVT::i64, Expand);
373  setOperationAction(ISD::ROTR, MVT::i64, Expand);
374 
375  setOperationAction(ISD::MUL, MVT::i64, Expand);
383 
388 
389  setOperationAction(ISD::CTTZ, MVT::i64, Custom);
391  setOperationAction(ISD::CTLZ, MVT::i64, Custom);
393 
394  static const MVT::SimpleValueType VectorIntTypes[] = {
396  };
397 
398  for (MVT VT : VectorIntTypes) {
399  // Expand the following operations for the current type by default.
434  }
435 
436  static const MVT::SimpleValueType FloatVectorTypes[] = {
438  };
439 
440  for (MVT VT : FloatVectorTypes) {
471  }
472 
473  // This causes using an unrolled select operation rather than expansion with
474  // bit operations. This is in general better, but the alternative using BFI
475  // instructions may be better if the select sources are SGPRs.
478 
479  setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
480  AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
481 
482  // There are no libcalls of any kind.
483  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
484  setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
485 
488 
490  setJumpIsExpensive(true);
491 
492  // FIXME: This is only partially true. If we have to do vector compares, any
493  // SGPR pair can be a condition register. If we have a uniform condition, we
494  // are better off doing SALU operations, where there is only one SCC. For now,
495  // we don't have a way of knowing during instruction selection if a condition
496  // will be uniform and we always use vector compares. Assume we are using
497  // vector compares until that is fixed.
499 
501 
502  // We want to find all load dependencies for long chains of stores to enable
503  // merging into very wide vectors. The problem is with vectors with > 4
504  // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
505  // vectors are a legal type, even though we have to split the loads
506  // usually. When we can more precisely specify load legality per address
507  // space, we should be able to make FindBetterChain/MergeConsecutiveStores
508  // smarter so that they can figure out what to do in 2 iterations without all
509  // N > 4 stores on the same chain.
511 
512  // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
513  // about these during lowering.
514  MaxStoresPerMemcpy = 0xffffffff;
515  MaxStoresPerMemmove = 0xffffffff;
516  MaxStoresPerMemset = 0xffffffff;
517 
535 }
536 
537 //===----------------------------------------------------------------------===//
538 // Target Information
539 //===----------------------------------------------------------------------===//
540 
542 static bool fnegFoldsIntoOp(unsigned Opc) {
543  switch (Opc) {
544  case ISD::FADD:
545  case ISD::FSUB:
546  case ISD::FMUL:
547  case ISD::FMA:
548  case ISD::FMAD:
549  case ISD::FMINNUM:
550  case ISD::FMAXNUM:
551  case ISD::FMINNUM_IEEE:
552  case ISD::FMAXNUM_IEEE:
553  case ISD::FSIN:
554  case ISD::FTRUNC:
555  case ISD::FRINT:
556  case ISD::FNEARBYINT:
557  case ISD::FCANONICALIZE:
558  case AMDGPUISD::RCP:
561  case AMDGPUISD::SIN_HW:
565  case AMDGPUISD::FMED3:
566  return true;
567  default:
568  return false;
569  }
570 }
571 
572 /// \p returns true if the operation will definitely need to use a 64-bit
573 /// encoding, and thus will use a VOP3 encoding regardless of the source
574 /// modifiers.
576 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
577  return N->getNumOperands() > 2 || VT == MVT::f64;
578 }
579 
580 // Most FP instructions support source modifiers, but this could be refined
581 // slightly.
583 static bool hasSourceMods(const SDNode *N) {
584  if (isa<MemSDNode>(N))
585  return false;
586 
587  switch (N->getOpcode()) {
588  case ISD::CopyToReg:
589  case ISD::SELECT:
590  case ISD::FDIV:
591  case ISD::FREM:
592  case ISD::INLINEASM:
593  case ISD::INLINEASM_BR:
597 
598  // TODO: Should really be looking at the users of the bitcast. These are
599  // problematic because bitcasts are used to legalize all stores to integer
600  // types.
601  case ISD::BITCAST:
602  return false;
603  default:
604  return true;
605  }
606 }
607 
609  unsigned CostThreshold) {
610  // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
611  // it is truly free to use a source modifier in all cases. If there are
612  // multiple users but for each one will necessitate using VOP3, there will be
613  // a code size increase. Try to avoid increasing code size unless we know it
614  // will save on the instruction count.
615  unsigned NumMayIncreaseSize = 0;
616  MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
617 
618  // XXX - Should this limit number of uses to check?
619  for (const SDNode *U : N->uses()) {
620  if (!hasSourceMods(U))
621  return false;
622 
623  if (!opMustUseVOP3Encoding(U, VT)) {
624  if (++NumMayIncreaseSize > CostThreshold)
625  return false;
626  }
627  }
628 
629  return true;
630 }
631 
633  return MVT::i32;
634 }
635 
637  return true;
638 }
639 
640 // The backend supports 32 and 64 bit floating point immediates.
641 // FIXME: Why are we reporting vectors of FP immediates as legal?
642 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
643  EVT ScalarVT = VT.getScalarType();
644  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
645  (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
646 }
647 
648 // We don't want to shrink f64 / f32 constants.
650  EVT ScalarVT = VT.getScalarType();
651  return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
652 }
653 
655  ISD::LoadExtType ExtTy,
656  EVT NewVT) const {
657  // TODO: This may be worth removing. Check regression tests for diffs.
658  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
659  return false;
660 
661  unsigned NewSize = NewVT.getStoreSizeInBits();
662 
663  // If we are reducing to a 32-bit load, this is always better.
664  if (NewSize == 32)
665  return true;
666 
667  EVT OldVT = N->getValueType(0);
668  unsigned OldSize = OldVT.getStoreSizeInBits();
669 
670  MemSDNode *MN = cast<MemSDNode>(N);
671  unsigned AS = MN->getAddressSpace();
672  // Do not shrink an aligned scalar load to sub-dword.
673  // Scalar engine cannot do sub-dword loads.
674  if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
677  (isa<LoadSDNode>(N) &&
678  AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
680  return false;
681 
682  // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
683  // extloads, so doing one requires using a buffer_load. In cases where we
684  // still couldn't use a scalar load, using the wider load shouldn't really
685  // hurt anything.
686 
687  // If the old size already had to be an extload, there's no harm in continuing
688  // to reduce the width.
689  return (OldSize < 32);
690 }
691 
693  EVT CastTy) const {
694 
695  assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
696 
697  if (LoadTy.getScalarType() == MVT::i32)
698  return false;
699 
700  unsigned LScalarSize = LoadTy.getScalarSizeInBits();
701  unsigned CastScalarSize = CastTy.getScalarSizeInBits();
702 
703  return (LScalarSize < CastScalarSize) ||
704  (CastScalarSize >= 32);
705 }
706 
707 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
708 // profitable with the expansion for 64-bit since it's generally good to
709 // speculate things.
710 // FIXME: These should really have the size as a parameter.
712  return true;
713 }
714 
716  return true;
717 }
718 
720  switch (N->getOpcode()) {
721  default:
722  return false;
723  case ISD::EntryToken:
724  case ISD::TokenFactor:
725  return true;
727  {
728  unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
729  switch (IntrID) {
730  default:
731  return false;
732  case Intrinsic::amdgcn_readfirstlane:
733  case Intrinsic::amdgcn_readlane:
734  return true;
735  }
736  }
737  break;
738  case ISD::LOAD:
739  {
740  const LoadSDNode * L = dyn_cast<LoadSDNode>(N);
741  if (L->getMemOperand()->getAddrSpace()
743  return true;
744  return false;
745  }
746  break;
747  }
748 }
749 
750 //===---------------------------------------------------------------------===//
751 // Target Properties
752 //===---------------------------------------------------------------------===//
753 
755  assert(VT.isFloatingPoint());
756 
757  // Packed operations do not have a fabs modifier.
758  return VT == MVT::f32 || VT == MVT::f64 ||
759  (Subtarget->has16BitInsts() && VT == MVT::f16);
760 }
761 
763  assert(VT.isFloatingPoint());
764  return VT == MVT::f32 || VT == MVT::f64 ||
765  (Subtarget->has16BitInsts() && VT == MVT::f16) ||
766  (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
767 }
768 
770  unsigned NumElem,
771  unsigned AS) const {
772  return true;
773 }
774 
776  // There are few operations which truly have vector input operands. Any vector
777  // operation is going to involve operations on each component, and a
778  // build_vector will be a copy per element, so it always makes sense to use a
779  // build_vector input in place of the extracted element to avoid a copy into a
780  // super register.
781  //
782  // We should probably only do this if all users are extracts only, but this
783  // should be the common case.
784  return true;
785 }
786 
788  // Truncate is just accessing a subregister.
789 
790  unsigned SrcSize = Source.getSizeInBits();
791  unsigned DestSize = Dest.getSizeInBits();
792 
793  return DestSize < SrcSize && DestSize % 32 == 0 ;
794 }
795 
797  // Truncate is just accessing a subregister.
798 
799  unsigned SrcSize = Source->getScalarSizeInBits();
800  unsigned DestSize = Dest->getScalarSizeInBits();
801 
802  if (DestSize== 16 && Subtarget->has16BitInsts())
803  return SrcSize >= 32;
804 
805  return DestSize < SrcSize && DestSize % 32 == 0;
806 }
807 
808 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
809  unsigned SrcSize = Src->getScalarSizeInBits();
810  unsigned DestSize = Dest->getScalarSizeInBits();
811 
812  if (SrcSize == 16 && Subtarget->has16BitInsts())
813  return DestSize >= 32;
814 
815  return SrcSize == 32 && DestSize == 64;
816 }
817 
818 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
819  // Any register load of a 64-bit value really requires 2 32-bit moves. For all
820  // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
821  // this will enable reducing 64-bit operations the 32-bit, which is always
822  // good.
823 
824  if (Src == MVT::i16)
825  return Dest == MVT::i32 ||Dest == MVT::i64 ;
826 
827  return Src == MVT::i32 && Dest == MVT::i64;
828 }
829 
831  return isZExtFree(Val.getValueType(), VT2);
832 }
833 
835  // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
836  // limited number of native 64-bit operations. Shrinking an operation to fit
837  // in a single 32-bit register should always be helpful. As currently used,
838  // this is much less general than the name suggests, and is only used in
839  // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
840  // not profitable, and may actually be harmful.
841  return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
842 }
843 
844 //===---------------------------------------------------------------------===//
845 // TargetLowering Callbacks
846 //===---------------------------------------------------------------------===//
847 
849  bool IsVarArg) {
850  switch (CC) {
853  llvm_unreachable("kernels should not be handled here");
861  return CC_AMDGPU;
862  case CallingConv::C:
863  case CallingConv::Fast:
864  case CallingConv::Cold:
865  return CC_AMDGPU_Func;
866  default:
867  report_fatal_error("Unsupported calling convention.");
868  }
869 }
870 
872  bool IsVarArg) {
873  switch (CC) {
876  llvm_unreachable("kernels should not be handled here");
884  return RetCC_SI_Shader;
885  case CallingConv::C:
886  case CallingConv::Fast:
887  case CallingConv::Cold:
888  return RetCC_AMDGPU_Func;
889  default:
890  report_fatal_error("Unsupported calling convention.");
891  }
892 }
893 
894 /// The SelectionDAGBuilder will automatically promote function arguments
895 /// with illegal types. However, this does not work for the AMDGPU targets
896 /// since the function arguments are stored in memory as these illegal types.
897 /// In order to handle this properly we need to get the original types sizes
898 /// from the LLVM IR Function and fixup the ISD:InputArg values before
899 /// passing them to AnalyzeFormalArguments()
900 
901 /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
902 /// input values across multiple registers. Each item in the Ins array
903 /// represents a single value that will be stored in registers. Ins[x].VT is
904 /// the value type of the value that will be stored in the register, so
905 /// whatever SDNode we lower the argument to needs to be this type.
906 ///
907 /// In order to correctly lower the arguments we need to know the size of each
908 /// argument. Since Ins[x].VT gives us the size of the register that will
909 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
910 /// for the orignal function argument so that we can deduce the correct memory
911 /// type to use for Ins[x]. In most cases the correct memory type will be
912 /// Ins[x].ArgVT. However, this will not always be the case. If, for example,
913 /// we have a kernel argument of type v8i8, this argument will be split into
914 /// 8 parts and each part will be represented by its own item in the Ins array.
915 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
916 /// the argument before it was split. From this, we deduce that the memory type
917 /// for each individual part is i8. We pass the memory type as LocVT to the
918 /// calling convention analysis function and the register type (Ins[x].VT) as
919 /// the ValVT.
921  CCState &State,
922  const SmallVectorImpl<ISD::InputArg> &Ins) const {
923  const MachineFunction &MF = State.getMachineFunction();
924  const Function &Fn = MF.getFunction();
925  LLVMContext &Ctx = Fn.getParent()->getContext();
927  const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
929 
930  unsigned MaxAlign = 1;
931  uint64_t ExplicitArgOffset = 0;
932  const DataLayout &DL = Fn.getParent()->getDataLayout();
933 
934  unsigned InIndex = 0;
935 
936  for (const Argument &Arg : Fn.args()) {
937  Type *BaseArgTy = Arg.getType();
938  unsigned Align = DL.getABITypeAlignment(BaseArgTy);
939  MaxAlign = std::max(Align, MaxAlign);
940  unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
941 
942  uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
943  ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
944 
945  // We're basically throwing away everything passed into us and starting over
946  // to get accurate in-memory offsets. The "PartOffset" is completely useless
947  // to us as computed in Ins.
948  //
949  // We also need to figure out what type legalization is trying to do to get
950  // the correct memory offsets.
951 
952  SmallVector<EVT, 16> ValueVTs;
954  ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
955 
956  for (unsigned Value = 0, NumValues = ValueVTs.size();
957  Value != NumValues; ++Value) {
958  uint64_t BasePartOffset = Offsets[Value];
959 
960  EVT ArgVT = ValueVTs[Value];
961  EVT MemVT = ArgVT;
962  MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
963  unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
964 
965  if (NumRegs == 1) {
966  // This argument is not split, so the IR type is the memory type.
967  if (ArgVT.isExtended()) {
968  // We have an extended type, like i24, so we should just use the
969  // register type.
970  MemVT = RegisterVT;
971  } else {
972  MemVT = ArgVT;
973  }
974  } else if (ArgVT.isVector() && RegisterVT.isVector() &&
975  ArgVT.getScalarType() == RegisterVT.getScalarType()) {
976  assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
977  // We have a vector value which has been split into a vector with
978  // the same scalar type, but fewer elements. This should handle
979  // all the floating-point vector types.
980  MemVT = RegisterVT;
981  } else if (ArgVT.isVector() &&
982  ArgVT.getVectorNumElements() == NumRegs) {
983  // This arg has been split so that each element is stored in a separate
984  // register.
985  MemVT = ArgVT.getScalarType();
986  } else if (ArgVT.isExtended()) {
987  // We have an extended type, like i65.
988  MemVT = RegisterVT;
989  } else {
990  unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
991  assert(ArgVT.getStoreSizeInBits() % NumRegs == 0);
992  if (RegisterVT.isInteger()) {
993  MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
994  } else if (RegisterVT.isVector()) {
995  assert(!RegisterVT.getScalarType().isFloatingPoint());
996  unsigned NumElements = RegisterVT.getVectorNumElements();
997  assert(MemoryBits % NumElements == 0);
998  // This vector type has been split into another vector type with
999  // a different elements size.
1000  EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
1001  MemoryBits / NumElements);
1002  MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
1003  } else {
1004  llvm_unreachable("cannot deduce memory type.");
1005  }
1006  }
1007 
1008  // Convert one element vectors to scalar.
1009  if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
1010  MemVT = MemVT.getScalarType();
1011 
1012  if (MemVT.isExtended()) {
1013  // This should really only happen if we have vec3 arguments
1014  assert(MemVT.isVector() && MemVT.getVectorNumElements() == 3);
1015  MemVT = MemVT.getPow2VectorType(State.getContext());
1016  }
1017 
1018  unsigned PartOffset = 0;
1019  for (unsigned i = 0; i != NumRegs; ++i) {
1020  State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1021  BasePartOffset + PartOffset,
1022  MemVT.getSimpleVT(),
1024  PartOffset += MemVT.getStoreSize();
1025  }
1026  }
1027  }
1028 }
1029 
1031  SDValue Chain, CallingConv::ID CallConv,
1032  bool isVarArg,
1033  const SmallVectorImpl<ISD::OutputArg> &Outs,
1034  const SmallVectorImpl<SDValue> &OutVals,
1035  const SDLoc &DL, SelectionDAG &DAG) const {
1036  // FIXME: Fails for r600 tests
1037  //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1038  // "wave terminate should not have return values");
1039  return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1040 }
1041 
1042 //===---------------------------------------------------------------------===//
1043 // Target specific lowering
1044 //===---------------------------------------------------------------------===//
1045 
1046 /// Selects the correct CCAssignFn for a given CallingConvention value.
1048  bool IsVarArg) {
1049  return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1050 }
1051 
1053  bool IsVarArg) {
1054  return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1055 }
1056 
1058  SelectionDAG &DAG,
1059  MachineFrameInfo &MFI,
1060  int ClobberedFI) const {
1061  SmallVector<SDValue, 8> ArgChains;
1062  int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1063  int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1064 
1065  // Include the original chain at the beginning of the list. When this is
1066  // used by target LowerCall hooks, this helps legalize find the
1067  // CALLSEQ_BEGIN node.
1068  ArgChains.push_back(Chain);
1069 
1070  // Add a chain value for each stack argument corresponding
1071  for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1072  UE = DAG.getEntryNode().getNode()->use_end();
1073  U != UE; ++U) {
1074  if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1075  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1076  if (FI->getIndex() < 0) {
1077  int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1078  int64_t InLastByte = InFirstByte;
1079  InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1080 
1081  if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1082  (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1083  ArgChains.push_back(SDValue(L, 1));
1084  }
1085  }
1086  }
1087  }
1088 
1089  // Build a tokenfactor for all the chains.
1090  return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1091 }
1092 
1094  SmallVectorImpl<SDValue> &InVals,
1095  StringRef Reason) const {
1096  SDValue Callee = CLI.Callee;
1097  SelectionDAG &DAG = CLI.DAG;
1098 
1099  const Function &Fn = DAG.getMachineFunction().getFunction();
1100 
1101  StringRef FuncName("<unknown>");
1102 
1103  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1104  FuncName = G->getSymbol();
1105  else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1106  FuncName = G->getGlobal()->getName();
1107 
1108  DiagnosticInfoUnsupported NoCalls(
1109  Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1110  DAG.getContext()->diagnose(NoCalls);
1111 
1112  if (!CLI.IsTailCall) {
1113  for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1114  InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1115  }
1116 
1117  return DAG.getEntryNode();
1118 }
1119 
1121  SmallVectorImpl<SDValue> &InVals) const {
1122  return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1123 }
1124 
1126  SelectionDAG &DAG) const {
1127  const Function &Fn = DAG.getMachineFunction().getFunction();
1128 
1129  DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1130  SDLoc(Op).getDebugLoc());
1131  DAG.getContext()->diagnose(NoDynamicAlloca);
1132  auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1133  return DAG.getMergeValues(Ops, SDLoc());
1134 }
1135 
1137  SelectionDAG &DAG) const {
1138  switch (Op.getOpcode()) {
1139  default:
1140  Op->print(errs(), &DAG);
1141  llvm_unreachable("Custom lowering code for this"
1142  "instruction is not implemented yet!");
1143  break;
1144  case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1145  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1146  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1147  case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1148  case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1149  case ISD::FREM: return LowerFREM(Op, DAG);
1150  case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1151  case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1152  case ISD::FRINT: return LowerFRINT(Op, DAG);
1153  case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1154  case ISD::FROUND: return LowerFROUND(Op, DAG);
1155  case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1156  case ISD::FLOG:
1157  return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1158  case ISD::FLOG10:
1159  return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
1160  case ISD::FEXP:
1161  return lowerFEXP(Op, DAG);
1162  case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1163  case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1164  case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1165  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1166  case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1167  case ISD::CTTZ:
1168  case ISD::CTTZ_ZERO_UNDEF:
1169  case ISD::CTLZ:
1170  case ISD::CTLZ_ZERO_UNDEF:
1171  return LowerCTLZ_CTTZ(Op, DAG);
1172  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1173  }
1174  return Op;
1175 }
1176 
1179  SelectionDAG &DAG) const {
1180  switch (N->getOpcode()) {
1182  // Different parts of legalization seem to interpret which type of
1183  // sign_extend_inreg is the one to check for custom lowering. The extended
1184  // from type is what really matters, but some places check for custom
1185  // lowering of the result type. This results in trying to use
1186  // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1187  // nothing here and let the illegal result integer be handled normally.
1188  return;
1189  default:
1190  return;
1191  }
1192 }
1193 
1194 static bool hasDefinedInitializer(const GlobalValue *GV) {
1195  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1196  if (!GVar || !GVar->hasInitializer())
1197  return false;
1198 
1199  return !isa<UndefValue>(GVar->getInitializer());
1200 }
1201 
1203  SDValue Op,
1204  SelectionDAG &DAG) const {
1205 
1206  const DataLayout &DL = DAG.getDataLayout();
1207  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1208  const GlobalValue *GV = G->getGlobal();
1209 
1212  if (!MFI->isEntryFunction()) {
1213  const Function &Fn = DAG.getMachineFunction().getFunction();
1214  DiagnosticInfoUnsupported BadLDSDecl(
1215  Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1216  DAG.getContext()->diagnose(BadLDSDecl);
1217  }
1218 
1219  // XXX: What does the value of G->getOffset() mean?
1220  assert(G->getOffset() == 0 &&
1221  "Do not know what to do with an non-zero offset");
1222 
1223  // TODO: We could emit code to handle the initialization somewhere.
1224  if (!hasDefinedInitializer(GV)) {
1225  unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1226  return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1227  }
1228  }
1229 
1230  const Function &Fn = DAG.getMachineFunction().getFunction();
1231  DiagnosticInfoUnsupported BadInit(
1232  Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1233  DAG.getContext()->diagnose(BadInit);
1234  return SDValue();
1235 }
1236 
1238  SelectionDAG &DAG) const {
1240 
1241  EVT VT = Op.getValueType();
1242  if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1243  SDLoc SL(Op);
1244  SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1245  SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1246 
1247  SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1248  return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1249  }
1250 
1251  for (const SDUse &U : Op->ops())
1252  DAG.ExtractVectorElements(U.get(), Args);
1253 
1254  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1255 }
1256 
1258  SelectionDAG &DAG) const {
1259 
1261  unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1262  EVT VT = Op.getValueType();
1263  DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1264  VT.getVectorNumElements());
1265 
1266  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1267 }
1268 
1269 /// Generate Min/Max node
1271  SDValue LHS, SDValue RHS,
1272  SDValue True, SDValue False,
1273  SDValue CC,
1274  DAGCombinerInfo &DCI) const {
1275  if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1276  return SDValue();
1277 
1278  SelectionDAG &DAG = DCI.DAG;
1279  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1280  switch (CCOpcode) {
1281  case ISD::SETOEQ:
1282  case ISD::SETONE:
1283  case ISD::SETUNE:
1284  case ISD::SETNE:
1285  case ISD::SETUEQ:
1286  case ISD::SETEQ:
1287  case ISD::SETFALSE:
1288  case ISD::SETFALSE2:
1289  case ISD::SETTRUE:
1290  case ISD::SETTRUE2:
1291  case ISD::SETUO:
1292  case ISD::SETO:
1293  break;
1294  case ISD::SETULE:
1295  case ISD::SETULT: {
1296  if (LHS == True)
1297  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1298  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1299  }
1300  case ISD::SETOLE:
1301  case ISD::SETOLT:
1302  case ISD::SETLE:
1303  case ISD::SETLT: {
1304  // Ordered. Assume ordered for undefined.
1305 
1306  // Only do this after legalization to avoid interfering with other combines
1307  // which might occur.
1308  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1309  !DCI.isCalledByLegalizer())
1310  return SDValue();
1311 
1312  // We need to permute the operands to get the correct NaN behavior. The
1313  // selected operand is the second one based on the failing compare with NaN,
1314  // so permute it based on the compare type the hardware uses.
1315  if (LHS == True)
1316  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1317  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1318  }
1319  case ISD::SETUGE:
1320  case ISD::SETUGT: {
1321  if (LHS == True)
1322  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1323  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1324  }
1325  case ISD::SETGT:
1326  case ISD::SETGE:
1327  case ISD::SETOGE:
1328  case ISD::SETOGT: {
1329  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1330  !DCI.isCalledByLegalizer())
1331  return SDValue();
1332 
1333  if (LHS == True)
1334  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1335  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1336  }
1337  case ISD::SETCC_INVALID:
1338  llvm_unreachable("Invalid setcc condcode!");
1339  }
1340  return SDValue();
1341 }
1342 
1343 std::pair<SDValue, SDValue>
1345  SDLoc SL(Op);
1346 
1347  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1348 
1349  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1350  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1351 
1352  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1353  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1354 
1355  return std::make_pair(Lo, Hi);
1356 }
1357 
1359  SDLoc SL(Op);
1360 
1361  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1362  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1363  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1364 }
1365 
1367  SDLoc SL(Op);
1368 
1369  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1370  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1371  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1372 }
1373 
1375  SelectionDAG &DAG) const {
1376  LoadSDNode *Load = cast<LoadSDNode>(Op);
1377  EVT VT = Op.getValueType();
1378 
1379 
1380  // If this is a 2 element vector, we really want to scalarize and not create
1381  // weird 1 element vectors.
1382  if (VT.getVectorNumElements() == 2)
1383  return scalarizeVectorLoad(Load, DAG);
1384 
1385  SDValue BasePtr = Load->getBasePtr();
1386  EVT MemVT = Load->getMemoryVT();
1387  SDLoc SL(Op);
1388 
1389  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1390 
1391  EVT LoVT, HiVT;
1392  EVT LoMemVT, HiMemVT;
1393  SDValue Lo, Hi;
1394 
1395  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1396  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1397  std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1398 
1399  unsigned Size = LoMemVT.getStoreSize();
1400  unsigned BaseAlign = Load->getAlignment();
1401  unsigned HiAlign = MinAlign(BaseAlign, Size);
1402 
1403  SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1404  Load->getChain(), BasePtr, SrcValue, LoMemVT,
1405  BaseAlign, Load->getMemOperand()->getFlags());
1406  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1407  SDValue HiLoad =
1408  DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1409  HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1410  HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1411 
1412  SDValue Ops[] = {
1413  DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1415  LoLoad.getValue(1), HiLoad.getValue(1))
1416  };
1417 
1418  return DAG.getMergeValues(Ops, SL);
1419 }
1420 
1422  SelectionDAG &DAG) const {
1423  StoreSDNode *Store = cast<StoreSDNode>(Op);
1424  SDValue Val = Store->getValue();
1425  EVT VT = Val.getValueType();
1426 
1427  // If this is a 2 element vector, we really want to scalarize and not create
1428  // weird 1 element vectors.
1429  if (VT.getVectorNumElements() == 2)
1430  return scalarizeVectorStore(Store, DAG);
1431 
1432  EVT MemVT = Store->getMemoryVT();
1433  SDValue Chain = Store->getChain();
1434  SDValue BasePtr = Store->getBasePtr();
1435  SDLoc SL(Op);
1436 
1437  EVT LoVT, HiVT;
1438  EVT LoMemVT, HiMemVT;
1439  SDValue Lo, Hi;
1440 
1441  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1442  std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1443  std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1444 
1445  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1446 
1447  const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1448  unsigned BaseAlign = Store->getAlignment();
1449  unsigned Size = LoMemVT.getStoreSize();
1450  unsigned HiAlign = MinAlign(BaseAlign, Size);
1451 
1452  SDValue LoStore =
1453  DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1454  Store->getMemOperand()->getFlags());
1455  SDValue HiStore =
1456  DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1457  HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1458 
1459  return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1460 }
1461 
1462 // This is a shortcut for integer division because we have fast i32<->f32
1463 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1464 // float is enough to accurately represent up to a 24-bit signed integer.
1466  bool Sign) const {
1467  SDLoc DL(Op);
1468  EVT VT = Op.getValueType();
1469  SDValue LHS = Op.getOperand(0);
1470  SDValue RHS = Op.getOperand(1);
1471  MVT IntVT = MVT::i32;
1472  MVT FltVT = MVT::f32;
1473 
1474  unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1475  if (LHSSignBits < 9)
1476  return SDValue();
1477 
1478  unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1479  if (RHSSignBits < 9)
1480  return SDValue();
1481 
1482  unsigned BitSize = VT.getSizeInBits();
1483  unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1484  unsigned DivBits = BitSize - SignBits;
1485  if (Sign)
1486  ++DivBits;
1487 
1490 
1491  SDValue jq = DAG.getConstant(1, DL, IntVT);
1492 
1493  if (Sign) {
1494  // char|short jq = ia ^ ib;
1495  jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1496 
1497  // jq = jq >> (bitsize - 2)
1498  jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1499  DAG.getConstant(BitSize - 2, DL, VT));
1500 
1501  // jq = jq | 0x1
1502  jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1503  }
1504 
1505  // int ia = (int)LHS;
1506  SDValue ia = LHS;
1507 
1508  // int ib, (int)RHS;
1509  SDValue ib = RHS;
1510 
1511  // float fa = (float)ia;
1512  SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1513 
1514  // float fb = (float)ib;
1515  SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1516 
1517  SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1518  fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1519 
1520  // fq = trunc(fq);
1521  fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1522 
1523  // float fqneg = -fq;
1524  SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1525 
1526  // float fr = mad(fqneg, fb, fa);
1527  unsigned OpCode = Subtarget->hasFP32Denormals() ?
1529  (unsigned)ISD::FMAD;
1530  SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1531 
1532  // int iq = (int)fq;
1533  SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1534 
1535  // fr = fabs(fr);
1536  fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1537 
1538  // fb = fabs(fb);
1539  fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1540 
1541  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1542 
1543  // int cv = fr >= fb;
1544  SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1545 
1546  // jq = (cv ? jq : 0);
1547  jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1548 
1549  // dst = iq + jq;
1550  SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1551 
1552  // Rem needs compensation, it's easier to recompute it
1553  SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1554  Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1555 
1556  // Truncate to number of bits this divide really is.
1557  if (Sign) {
1558  SDValue InRegSize
1559  = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1560  Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1561  Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1562  } else {
1563  SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1564  Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1565  Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1566  }
1567 
1568  return DAG.getMergeValues({ Div, Rem }, DL);
1569 }
1570 
1572  SelectionDAG &DAG,
1574  SDLoc DL(Op);
1575  EVT VT = Op.getValueType();
1576 
1577  assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1578 
1579  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1580 
1581  SDValue One = DAG.getConstant(1, DL, HalfVT);
1582  SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1583 
1584  //HiLo split
1585  SDValue LHS = Op.getOperand(0);
1586  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1587  SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1588 
1589  SDValue RHS = Op.getOperand(1);
1590  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1591  SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1592 
1593  if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1594  DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1595 
1596  SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1597  LHS_Lo, RHS_Lo);
1598 
1599  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1600  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1601 
1602  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1603  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1604  return;
1605  }
1606 
1607  if (isTypeLegal(MVT::i64)) {
1608  // Compute denominator reciprocal.
1609  unsigned FMAD = Subtarget->hasFP32Denormals() ?
1611  (unsigned)ISD::FMAD;
1612 
1613  SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1614  SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1615  SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1616  DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1617  Cvt_Lo);
1618  SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1619  SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1620  DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1621  SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1622  DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1623  SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1624  SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1625  DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1626  Mul1);
1627  SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1628  SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1629  SDValue Rcp64 = DAG.getBitcast(VT,
1630  DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1631 
1632  SDValue Zero64 = DAG.getConstant(0, DL, VT);
1633  SDValue One64 = DAG.getConstant(1, DL, VT);
1634  SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1635  SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1636 
1637  SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1638  SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1639  SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1640  SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1641  Zero);
1642  SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1643  One);
1644 
1645  SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1646  Mulhi1_Lo, Zero1);
1647  SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1648  Mulhi1_Hi, Add1_Lo.getValue(1));
1649  SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1650  SDValue Add1 = DAG.getBitcast(VT,
1651  DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1652 
1653  SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1654  SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1655  SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1656  Zero);
1657  SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1658  One);
1659 
1660  SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1661  Mulhi2_Lo, Zero1);
1662  SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1663  Mulhi2_Hi, Add1_Lo.getValue(1));
1664  SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1665  Zero, Add2_Lo.getValue(1));
1666  SDValue Add2 = DAG.getBitcast(VT,
1667  DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1668  SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1669 
1670  SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1671 
1672  SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1673  SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1674  SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1675  Mul3_Lo, Zero1);
1676  SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1677  Mul3_Hi, Sub1_Lo.getValue(1));
1678  SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1679  SDValue Sub1 = DAG.getBitcast(VT,
1680  DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1681 
1682  SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1683  SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1684  ISD::SETUGE);
1685  SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1686  ISD::SETUGE);
1687  SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1688 
1689  // TODO: Here and below portions of the code can be enclosed into if/endif.
1690  // Currently control flow is unconditional and we have 4 selects after
1691  // potential endif to substitute PHIs.
1692 
1693  // if C3 != 0 ...
1694  SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1695  RHS_Lo, Zero1);
1696  SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1697  RHS_Hi, Sub1_Lo.getValue(1));
1698  SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1699  Zero, Sub2_Lo.getValue(1));
1700  SDValue Sub2 = DAG.getBitcast(VT,
1701  DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1702 
1703  SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1704 
1705  SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1706  ISD::SETUGE);
1707  SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1708  ISD::SETUGE);
1709  SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1710 
1711  // if (C6 != 0)
1712  SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1713 
1714  SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1715  RHS_Lo, Zero1);
1716  SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1717  RHS_Hi, Sub2_Lo.getValue(1));
1718  SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1719  Zero, Sub3_Lo.getValue(1));
1720  SDValue Sub3 = DAG.getBitcast(VT,
1721  DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1722 
1723  // endif C6
1724  // endif C3
1725 
1726  SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1727  SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1728 
1729  SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1730  SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1731 
1732  Results.push_back(Div);
1733  Results.push_back(Rem);
1734 
1735  return;
1736  }
1737 
1738  // r600 expandion.
1739  // Get Speculative values
1740  SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1741  SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1742 
1743  SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1744  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1745  REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1746 
1747  SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1748  SDValue DIV_Lo = Zero;
1749 
1750  const unsigned halfBitWidth = HalfVT.getSizeInBits();
1751 
1752  for (unsigned i = 0; i < halfBitWidth; ++i) {
1753  const unsigned bitPos = halfBitWidth - i - 1;
1754  SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1755  // Get value of high bit
1756  SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1757  HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1758  HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1759 
1760  // Shift
1761  REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1762  // Add LHS high bit
1763  REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1764 
1765  SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1766  SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1767 
1768  DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1769 
1770  // Update REM
1771  SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1772  REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1773  }
1774 
1775  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1776  DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1777  Results.push_back(DIV);
1778  Results.push_back(REM);
1779 }
1780 
1782  SelectionDAG &DAG) const {
1783  SDLoc DL(Op);
1784  EVT VT = Op.getValueType();
1785 
1786  if (VT == MVT::i64) {
1788  LowerUDIVREM64(Op, DAG, Results);
1789  return DAG.getMergeValues(Results, DL);
1790  }
1791 
1792  if (VT == MVT::i32) {
1793  if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1794  return Res;
1795  }
1796 
1797  SDValue Num = Op.getOperand(0);
1798  SDValue Den = Op.getOperand(1);
1799 
1800  // RCP = URECIP(Den) = 2^32 / Den + e
1801  // e is rounding error.
1802  SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1803 
1804  // RCP_LO = mul(RCP, Den) */
1805  SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1806 
1807  // RCP_HI = mulhu (RCP, Den) */
1808  SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1809 
1810  // NEG_RCP_LO = -RCP_LO
1811  SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1812  RCP_LO);
1813 
1814  // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1815  SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1816  NEG_RCP_LO, RCP_LO,
1817  ISD::SETEQ);
1818  // Calculate the rounding error from the URECIP instruction
1819  // E = mulhu(ABS_RCP_LO, RCP)
1820  SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1821 
1822  // RCP_A_E = RCP + E
1823  SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1824 
1825  // RCP_S_E = RCP - E
1826  SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1827 
1828  // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1829  SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1830  RCP_A_E, RCP_S_E,
1831  ISD::SETEQ);
1832  // Quotient = mulhu(Tmp0, Num)
1833  SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1834 
1835  // Num_S_Remainder = Quotient * Den
1836  SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1837 
1838  // Remainder = Num - Num_S_Remainder
1839  SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1840 
1841  // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1842  SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1843  DAG.getConstant(-1, DL, VT),
1844  DAG.getConstant(0, DL, VT),
1845  ISD::SETUGE);
1846  // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1847  SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1848  Num_S_Remainder,
1849  DAG.getConstant(-1, DL, VT),
1850  DAG.getConstant(0, DL, VT),
1851  ISD::SETUGE);
1852  // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1853  SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1854  Remainder_GE_Zero);
1855 
1856  // Calculate Division result:
1857 
1858  // Quotient_A_One = Quotient + 1
1859  SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1860  DAG.getConstant(1, DL, VT));
1861 
1862  // Quotient_S_One = Quotient - 1
1863  SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1864  DAG.getConstant(1, DL, VT));
1865 
1866  // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1867  SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1868  Quotient, Quotient_A_One, ISD::SETEQ);
1869 
1870  // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1871  Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1872  Quotient_S_One, Div, ISD::SETEQ);
1873 
1874  // Calculate Rem result:
1875 
1876  // Remainder_S_Den = Remainder - Den
1877  SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1878 
1879  // Remainder_A_Den = Remainder + Den
1880  SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1881 
1882  // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1883  SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1884  Remainder, Remainder_S_Den, ISD::SETEQ);
1885 
1886  // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1887  Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1888  Remainder_A_Den, Rem, ISD::SETEQ);
1889  SDValue Ops[2] = {
1890  Div,
1891  Rem
1892  };
1893  return DAG.getMergeValues(Ops, DL);
1894 }
1895 
1897  SelectionDAG &DAG) const {
1898  SDLoc DL(Op);
1899  EVT VT = Op.getValueType();
1900 
1901  SDValue LHS = Op.getOperand(0);
1902  SDValue RHS = Op.getOperand(1);
1903 
1904  SDValue Zero = DAG.getConstant(0, DL, VT);
1905  SDValue NegOne = DAG.getConstant(-1, DL, VT);
1906 
1907  if (VT == MVT::i32) {
1908  if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1909  return Res;
1910  }
1911 
1912  if (VT == MVT::i64 &&
1913  DAG.ComputeNumSignBits(LHS) > 32 &&
1914  DAG.ComputeNumSignBits(RHS) > 32) {
1915  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1916 
1917  //HiLo split
1918  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1919  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1920  SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1921  LHS_Lo, RHS_Lo);
1922  SDValue Res[2] = {
1923  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1924  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1925  };
1926  return DAG.getMergeValues(Res, DL);
1927  }
1928 
1929  SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1930  SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1931  SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1932  SDValue RSign = LHSign; // Remainder sign is the same as LHS
1933 
1934  LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1935  RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1936 
1937  LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1938  RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1939 
1940  SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1941  SDValue Rem = Div.getValue(1);
1942 
1943  Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1944  Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1945 
1946  Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1947  Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1948 
1949  SDValue Res[2] = {
1950  Div,
1951  Rem
1952  };
1953  return DAG.getMergeValues(Res, DL);
1954 }
1955 
1956 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1958  SDLoc SL(Op);
1959  EVT VT = Op.getValueType();
1960  SDValue X = Op.getOperand(0);
1961  SDValue Y = Op.getOperand(1);
1962 
1963  // TODO: Should this propagate fast-math-flags?
1964 
1965  SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1966  SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1967  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1968 
1969  return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1970 }
1971 
1973  SDLoc SL(Op);
1974  SDValue Src = Op.getOperand(0);
1975 
1976  // result = trunc(src)
1977  // if (src > 0.0 && src != result)
1978  // result += 1.0
1979 
1980  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1981 
1982  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1983  const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1984 
1985  EVT SetCCVT =
1987 
1988  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1989  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1990  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1991 
1992  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1993  // TODO: Should this propagate fast-math-flags?
1994  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1995 }
1996 
1998  SelectionDAG &DAG) {
1999  const unsigned FractBits = 52;
2000  const unsigned ExpBits = 11;
2001 
2002  SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2003  Hi,
2004  DAG.getConstant(FractBits - 32, SL, MVT::i32),
2005  DAG.getConstant(ExpBits, SL, MVT::i32));
2006  SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2007  DAG.getConstant(1023, SL, MVT::i32));
2008 
2009  return Exp;
2010 }
2011 
2013  SDLoc SL(Op);
2014  SDValue Src = Op.getOperand(0);
2015 
2016  assert(Op.getValueType() == MVT::f64);
2017 
2018  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2019  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2020 
2021  SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2022 
2023  // Extract the upper half, since this is where we will find the sign and
2024  // exponent.
2025  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2026 
2027  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2028 
2029  const unsigned FractBits = 52;
2030 
2031  // Extract the sign bit.
2032  const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2033  SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2034 
2035  // Extend back to 64-bits.
2036  SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2037  SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2038 
2039  SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2040  const SDValue FractMask
2041  = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2042 
2043  SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2044  SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2045  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2046 
2047  EVT SetCCVT =
2049 
2050  const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2051 
2052  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2053  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2054 
2055  SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2056  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2057 
2058  return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2059 }
2060 
2062  SDLoc SL(Op);
2063  SDValue Src = Op.getOperand(0);
2064 
2065  assert(Op.getValueType() == MVT::f64);
2066 
2067  APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2068  SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2069  SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2070 
2071  // TODO: Should this propagate fast-math-flags?
2072 
2073  SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2074  SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2075 
2076  SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2077 
2078  APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2079  SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2080 
2081  EVT SetCCVT =
2083  SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2084 
2085  return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2086 }
2087 
2089  // FNEARBYINT and FRINT are the same, except in their handling of FP
2090  // exceptions. Those aren't really meaningful for us, and OpenCL only has
2091  // rint, so just treat them as equivalent.
2092  return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2093 }
2094 
2095 // XXX - May require not supporting f32 denormals?
2096 
2097 // Don't handle v2f16. The extra instructions to scalarize and repack around the
2098 // compare and vselect end up producing worse code than scalarizing the whole
2099 // operation.
2101  SDLoc SL(Op);
2102  SDValue X = Op.getOperand(0);
2103  EVT VT = Op.getValueType();
2104 
2105  SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2106 
2107  // TODO: Should this propagate fast-math-flags?
2108 
2109  SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2110 
2111  SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2112 
2113  const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2114  const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2115  const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2116 
2117  SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2118 
2119  EVT SetCCVT =
2120  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2121 
2122  SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2123 
2124  SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2125 
2126  return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2127 }
2128 
2130  SDLoc SL(Op);
2131  SDValue X = Op.getOperand(0);
2132 
2133  SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2134 
2135  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2136  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2137  const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2138  const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2139  EVT SetCCVT =
2141 
2142  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2143 
2144  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2145 
2146  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2147 
2148  const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2149  MVT::i64);
2150 
2151  SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2152  SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2153  DAG.getConstant(INT64_C(0x0008000000000000), SL,
2154  MVT::i64),
2155  Exp);
2156 
2157  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2158  SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2159  DAG.getConstant(0, SL, MVT::i64), Tmp0,
2160  ISD::SETNE);
2161 
2162  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2163  D, DAG.getConstant(0, SL, MVT::i64));
2164  SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2165 
2166  K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2167  K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2168 
2169  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2170  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2171  SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2172 
2173  SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2174  ExpEqNegOne,
2175  DAG.getConstantFP(1.0, SL, MVT::f64),
2176  DAG.getConstantFP(0.0, SL, MVT::f64));
2177 
2178  SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2179 
2180  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2181  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2182 
2183  return K;
2184 }
2185 
2187  EVT VT = Op.getValueType();
2188 
2189  if (VT == MVT::f32 || VT == MVT::f16)
2190  return LowerFROUND32_16(Op, DAG);
2191 
2192  if (VT == MVT::f64)
2193  return LowerFROUND64(Op, DAG);
2194 
2195  llvm_unreachable("unhandled type");
2196 }
2197 
2199  SDLoc SL(Op);
2200  SDValue Src = Op.getOperand(0);
2201 
2202  // result = trunc(src);
2203  // if (src < 0.0 && src != result)
2204  // result += -1.0.
2205 
2206  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2207 
2208  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2209  const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2210 
2211  EVT SetCCVT =
2213 
2214  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2215  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2216  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2217 
2218  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2219  // TODO: Should this propagate fast-math-flags?
2220  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2221 }
2222 
2224  double Log2BaseInverted) const {
2225  EVT VT = Op.getValueType();
2226 
2227  SDLoc SL(Op);
2228  SDValue Operand = Op.getOperand(0);
2229  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2230  SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2231 
2232  return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2233 }
2234 
2235 // Return M_LOG2E of appropriate type
2236 static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) {
2237  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
2238  case MVT::f32:
2239  return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT);
2240  case MVT::f16:
2241  return DAG.getConstantFP(
2242  APFloat(APFloat::IEEEhalf(), "1.44269504088896340735992468100189214"),
2243  SL, VT);
2244  case MVT::f64:
2245  return DAG.getConstantFP(
2246  APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT);
2247  default:
2248  llvm_unreachable("unsupported fp type");
2249  }
2250 }
2251 
2252 // exp2(M_LOG2E_F * f);
2254  EVT VT = Op.getValueType();
2255  SDLoc SL(Op);
2256  SDValue Src = Op.getOperand(0);
2257 
2258  const SDValue K = getLog2EVal(DAG, SL, VT);
2259  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2260  return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2261 }
2262 
2263 static bool isCtlzOpc(unsigned Opc) {
2264  return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2265 }
2266 
2267 static bool isCttzOpc(unsigned Opc) {
2268  return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2269 }
2270 
2272  SDLoc SL(Op);
2273  SDValue Src = Op.getOperand(0);
2274  bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2276 
2277  unsigned ISDOpc, NewOpc;
2278  if (isCtlzOpc(Op.getOpcode())) {
2279  ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2280  NewOpc = AMDGPUISD::FFBH_U32;
2281  } else if (isCttzOpc(Op.getOpcode())) {
2282  ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2283  NewOpc = AMDGPUISD::FFBL_B32;
2284  } else
2285  llvm_unreachable("Unexpected OPCode!!!");
2286 
2287 
2288  if (ZeroUndef && Src.getValueType() == MVT::i32)
2289  return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2290 
2291  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2292 
2293  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2294  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2295 
2296  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2297  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2298 
2299  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2300  *DAG.getContext(), MVT::i32);
2301 
2302  SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2303  SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2304 
2305  SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2306  SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2307 
2308  const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2309  SDValue Add, NewOpr;
2310  if (isCtlzOpc(Op.getOpcode())) {
2311  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2312  // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2313  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2314  } else {
2315  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2316  // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2317  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2318  }
2319 
2320  if (!ZeroUndef) {
2321  // Test if the full 64-bit input is zero.
2322 
2323  // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2324  // which we probably don't want.
2325  SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2326  SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2327  SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2328 
2329  // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2330  // with the same cycles, otherwise it is slower.
2331  // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2332  // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2333 
2334  const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2335 
2336  // The instruction returns -1 for 0 input, but the defined intrinsic
2337  // behavior is to return the number of bits.
2338  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2339  SrcIsZero, Bits32, NewOpr);
2340  }
2341 
2342  return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2343 }
2344 
2346  bool Signed) const {
2347  // Unsigned
2348  // cul2f(ulong u)
2349  //{
2350  // uint lz = clz(u);
2351  // uint e = (u != 0) ? 127U + 63U - lz : 0;
2352  // u = (u << lz) & 0x7fffffffffffffffUL;
2353  // ulong t = u & 0xffffffffffUL;
2354  // uint v = (e << 23) | (uint)(u >> 40);
2355  // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2356  // return as_float(v + r);
2357  //}
2358  // Signed
2359  // cl2f(long l)
2360  //{
2361  // long s = l >> 63;
2362  // float r = cul2f((l + s) ^ s);
2363  // return s ? -r : r;
2364  //}
2365 
2366  SDLoc SL(Op);
2367  SDValue Src = Op.getOperand(0);
2368  SDValue L = Src;
2369 
2370  SDValue S;
2371  if (Signed) {
2372  const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2373  S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2374 
2375  SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2376  L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2377  }
2378 
2379  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2380  *DAG.getContext(), MVT::f32);
2381 
2382 
2383  SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2384  SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2385  SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2386  LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2387 
2388  SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2389  SDValue E = DAG.getSelect(SL, MVT::i32,
2390  DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2391  DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2392  ZeroI32);
2393 
2394  SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2395  DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2396  DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2397 
2398  SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2399  DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2400 
2401  SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2402  U, DAG.getConstant(40, SL, MVT::i64));
2403 
2404  SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2405  DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2406  DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2407 
2408  SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2409  SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2410  SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2411 
2412  SDValue One = DAG.getConstant(1, SL, MVT::i32);
2413 
2414  SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2415 
2416  SDValue R = DAG.getSelect(SL, MVT::i32,
2417  RCmp,
2418  One,
2419  DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2420  R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2421  R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2422 
2423  if (!Signed)
2424  return R;
2425 
2426  SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2427  return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2428 }
2429 
2431  bool Signed) const {
2432  SDLoc SL(Op);
2433  SDValue Src = Op.getOperand(0);
2434 
2435  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2436 
2438  DAG.getConstant(0, SL, MVT::i32));
2440  DAG.getConstant(1, SL, MVT::i32));
2441 
2442  SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2443  SL, MVT::f64, Hi);
2444 
2445  SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2446 
2447  SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2448  DAG.getConstant(32, SL, MVT::i32));
2449  // TODO: Should this propagate fast-math-flags?
2450  return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2451 }
2452 
2454  SelectionDAG &DAG) const {
2455  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2456  "operation should be legal");
2457 
2458  // TODO: Factor out code common with LowerSINT_TO_FP.
2459 
2460  EVT DestVT = Op.getValueType();
2461  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2462  SDLoc DL(Op);
2463  SDValue Src = Op.getOperand(0);
2464 
2465  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2466  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2467  SDValue FPRound =
2468  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2469 
2470  return FPRound;
2471  }
2472 
2473  if (DestVT == MVT::f32)
2474  return LowerINT_TO_FP32(Op, DAG, false);
2475 
2476  assert(DestVT == MVT::f64);
2477  return LowerINT_TO_FP64(Op, DAG, false);
2478 }
2479 
2481  SelectionDAG &DAG) const {
2482  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2483  "operation should be legal");
2484 
2485  // TODO: Factor out code common with LowerUINT_TO_FP.
2486 
2487  EVT DestVT = Op.getValueType();
2488  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2489  SDLoc DL(Op);
2490  SDValue Src = Op.getOperand(0);
2491 
2492  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2493  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2494  SDValue FPRound =
2495  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2496 
2497  return FPRound;
2498  }
2499 
2500  if (DestVT == MVT::f32)
2501  return LowerINT_TO_FP32(Op, DAG, true);
2502 
2503  assert(DestVT == MVT::f64);
2504  return LowerINT_TO_FP64(Op, DAG, true);
2505 }
2506 
2508  bool Signed) const {
2509  SDLoc SL(Op);
2510 
2511  SDValue Src = Op.getOperand(0);
2512 
2513  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2514 
2515  SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2516  MVT::f64);
2517  SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2518  MVT::f64);
2519  // TODO: Should this propagate fast-math-flags?
2520  SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2521 
2522  SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2523 
2524 
2525  SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2526 
2527  SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2528  MVT::i32, FloorMul);
2529  SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2530 
2531  SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2532 
2533  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2534 }
2535 
2537  SDLoc DL(Op);
2538  SDValue N0 = Op.getOperand(0);
2539 
2540  // Convert to target node to get known bits
2541  if (N0.getValueType() == MVT::f32)
2542  return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2543 
2545  // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2546  return SDValue();
2547  }
2548 
2550 
2551  // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2552  const unsigned ExpMask = 0x7ff;
2553  const unsigned ExpBiasf64 = 1023;
2554  const unsigned ExpBiasf16 = 15;
2555  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2556  SDValue One = DAG.getConstant(1, DL, MVT::i32);
2557  SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2558  SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2559  DAG.getConstant(32, DL, MVT::i64));
2560  UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2561  U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2562  SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2563  DAG.getConstant(20, DL, MVT::i64));
2564  E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2565  DAG.getConstant(ExpMask, DL, MVT::i32));
2566  // Subtract the fp64 exponent bias (1023) to get the real exponent and
2567  // add the f16 bias (15) to get the biased exponent for the f16 format.
2568  E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2569  DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2570 
2571  SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2572  DAG.getConstant(8, DL, MVT::i32));
2573  M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2574  DAG.getConstant(0xffe, DL, MVT::i32));
2575 
2576  SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2577  DAG.getConstant(0x1ff, DL, MVT::i32));
2578  MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2579 
2580  SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2581  M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2582 
2583  // (M != 0 ? 0x0200 : 0) | 0x7c00;
2584  SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2585  DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2586  Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2587 
2588  // N = M | (E << 12);
2589  SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2590  DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2591  DAG.getConstant(12, DL, MVT::i32)));
2592 
2593  // B = clamp(1-E, 0, 13);
2594  SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2595  One, E);
2596  SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2597  B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2598  DAG.getConstant(13, DL, MVT::i32));
2599 
2600  SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2601  DAG.getConstant(0x1000, DL, MVT::i32));
2602 
2603  SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2604  SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2605  SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2606  D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2607 
2608  SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2609  SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2610  DAG.getConstant(0x7, DL, MVT::i32));
2611  V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2612  DAG.getConstant(2, DL, MVT::i32));
2613  SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2614  One, Zero, ISD::SETEQ);
2615  SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2616  One, Zero, ISD::SETGT);
2617  V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2618  V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2619 
2620  V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2621  DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2622  V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2623  I, V, ISD::SETEQ);
2624 
2625  // Extract the sign bit.
2626  SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2627  DAG.getConstant(16, DL, MVT::i32));
2628  Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2629  DAG.getConstant(0x8000, DL, MVT::i32));
2630 
2631  V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2632  return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2633 }
2634 
2636  SelectionDAG &DAG) const {
2637  SDValue Src = Op.getOperand(0);
2638 
2639  // TODO: Factor out code common with LowerFP_TO_UINT.
2640 
2641  EVT SrcVT = Src.getValueType();
2642  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2643  SDLoc DL(Op);
2644 
2645  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2646  SDValue FpToInt32 =
2647  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2648 
2649  return FpToInt32;
2650  }
2651 
2652  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2653  return LowerFP64_TO_INT(Op, DAG, true);
2654 
2655  return SDValue();
2656 }
2657 
2659  SelectionDAG &DAG) const {
2660  SDValue Src = Op.getOperand(0);
2661 
2662  // TODO: Factor out code common with LowerFP_TO_SINT.
2663 
2664  EVT SrcVT = Src.getValueType();
2665  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2666  SDLoc DL(Op);
2667 
2668  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2669  SDValue FpToInt32 =
2670  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2671 
2672  return FpToInt32;
2673  }
2674 
2675  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2676  return LowerFP64_TO_INT(Op, DAG, false);
2677 
2678  return SDValue();
2679 }
2680 
2682  SelectionDAG &DAG) const {
2683  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2684  MVT VT = Op.getSimpleValueType();
2685  MVT ScalarVT = VT.getScalarType();
2686 
2687  assert(VT.isVector());
2688 
2689  SDValue Src = Op.getOperand(0);
2690  SDLoc DL(Op);
2691 
2692  // TODO: Don't scalarize on Evergreen?
2693  unsigned NElts = VT.getVectorNumElements();
2695  DAG.ExtractVectorElements(Src, Args, 0, NElts);
2696 
2697  SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2698  for (unsigned I = 0; I < NElts; ++I)
2699  Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2700 
2701  return DAG.getBuildVector(VT, DL, Args);
2702 }
2703 
2704 //===----------------------------------------------------------------------===//
2705 // Custom DAG optimizations
2706 //===----------------------------------------------------------------------===//
2707 
2708 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2709  return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2710 }
2711 
2712 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2713  EVT VT = Op.getValueType();
2714  return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2715  // as unsigned 24-bit values.
2717 }
2718 
2719 static SDValue simplifyI24(SDNode *Node24,
2721  SelectionDAG &DAG = DCI.DAG;
2722  SDValue LHS = Node24->getOperand(0);
2723  SDValue RHS = Node24->getOperand(1);
2724 
2725  APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2726 
2727  // First try to simplify using GetDemandedBits which allows the operands to
2728  // have other uses, but will only perform simplifications that involve
2729  // bypassing some nodes for this user.
2730  SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
2731  SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
2732  if (DemandedLHS || DemandedRHS)
2733  return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),
2734  DemandedLHS ? DemandedLHS : LHS,
2735  DemandedRHS ? DemandedRHS : RHS);
2736 
2737  // Now try SimplifyDemandedBits which can simplify the nodes used by our
2738  // operands if this node is the only user.
2739  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2740  if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2741  return SDValue(Node24, 0);
2742  if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2743  return SDValue(Node24, 0);
2744 
2745  return SDValue();
2746 }
2747 
2748 template <typename IntTy>
2750  uint32_t Width, const SDLoc &DL) {
2751  if (Width + Offset < 32) {
2752  uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2753  IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2754  return DAG.getConstant(Result, DL, MVT::i32);
2755  }
2756 
2757  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2758 }
2759 
2760 static bool hasVolatileUser(SDNode *Val) {
2761  for (SDNode *U : Val->uses()) {
2762  if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2763  if (M->isVolatile())
2764  return true;
2765  }
2766  }
2767 
2768  return false;
2769 }
2770 
2772  // i32 vectors are the canonical memory type.
2773  if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2774  return false;
2775 
2776  if (!VT.isByteSized())
2777  return false;
2778 
2779  unsigned Size = VT.getStoreSize();
2780 
2781  if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2782  return false;
2783 
2784  if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2785  return false;
2786 
2787  return true;
2788 }
2789 
2790 // Replace load of an illegal type with a store of a bitcast to a friendlier
2791 // type.
2793  DAGCombinerInfo &DCI) const {
2794  if (!DCI.isBeforeLegalize())
2795  return SDValue();
2796 
2797  LoadSDNode *LN = cast<LoadSDNode>(N);
2798  if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2799  return SDValue();
2800 
2801  SDLoc SL(N);
2802  SelectionDAG &DAG = DCI.DAG;
2803  EVT VT = LN->getMemoryVT();
2804 
2805  unsigned Size = VT.getStoreSize();
2806  unsigned Align = LN->getAlignment();
2807  if (Align < Size && isTypeLegal(VT)) {
2808  bool IsFast;
2809  unsigned AS = LN->getAddressSpace();
2810 
2811  // Expand unaligned loads earlier than legalization. Due to visitation order
2812  // problems during legalization, the emitted instructions to pack and unpack
2813  // the bytes again are not eliminated in the case of an unaligned copy.
2814  if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2815  if (VT.isVector())
2816  return scalarizeVectorLoad(LN, DAG);
2817 
2818  SDValue Ops[2];
2819  std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2820  return DAG.getMergeValues(Ops, SDLoc(N));
2821  }
2822 
2823  if (!IsFast)
2824  return SDValue();
2825  }
2826 
2827  if (!shouldCombineMemoryType(VT))
2828  return SDValue();
2829 
2830  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2831 
2832  SDValue NewLoad
2833  = DAG.getLoad(NewVT, SL, LN->getChain(),
2834  LN->getBasePtr(), LN->getMemOperand());
2835 
2836  SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2837  DCI.CombineTo(N, BC, NewLoad.getValue(1));
2838  return SDValue(N, 0);
2839 }
2840 
2841 // Replace store of an illegal type with a store of a bitcast to a friendlier
2842 // type.
2844  DAGCombinerInfo &DCI) const {
2845  if (!DCI.isBeforeLegalize())
2846  return SDValue();
2847 
2848  StoreSDNode *SN = cast<StoreSDNode>(N);
2849  if (SN->isVolatile() || !ISD::isNormalStore(SN))
2850  return SDValue();
2851 
2852  EVT VT = SN->getMemoryVT();
2853  unsigned Size = VT.getStoreSize();
2854 
2855  SDLoc SL(N);
2856  SelectionDAG &DAG = DCI.DAG;
2857  unsigned Align = SN->getAlignment();
2858  if (Align < Size && isTypeLegal(VT)) {
2859  bool IsFast;
2860  unsigned AS = SN->getAddressSpace();
2861 
2862  // Expand unaligned stores earlier than legalization. Due to visitation
2863  // order problems during legalization, the emitted instructions to pack and
2864  // unpack the bytes again are not eliminated in the case of an unaligned
2865  // copy.
2866  if (!allowsMisalignedMemoryAccesses(VT, AS, Align, &IsFast)) {
2867  if (VT.isVector())
2868  return scalarizeVectorStore(SN, DAG);
2869 
2870  return expandUnalignedStore(SN, DAG);
2871  }
2872 
2873  if (!IsFast)
2874  return SDValue();
2875  }
2876 
2877  if (!shouldCombineMemoryType(VT))
2878  return SDValue();
2879 
2880  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2881  SDValue Val = SN->getValue();
2882 
2883  //DCI.AddToWorklist(Val.getNode());
2884 
2885  bool OtherUses = !Val.hasOneUse();
2886  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2887  if (OtherUses) {
2888  SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2889  DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2890  }
2891 
2892  return DAG.getStore(SN->getChain(), SL, CastVal,
2893  SN->getBasePtr(), SN->getMemOperand());
2894 }
2895 
2896 // FIXME: This should go in generic DAG combiner with an isTruncateFree check,
2897 // but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
2898 // issues.
2900  DAGCombinerInfo &DCI) const {
2901  SelectionDAG &DAG = DCI.DAG;
2902  SDValue N0 = N->getOperand(0);
2903 
2904  // (vt2 (assertzext (truncate vt0:x), vt1)) ->
2905  // (vt2 (truncate (assertzext vt0:x, vt1)))
2906  if (N0.getOpcode() == ISD::TRUNCATE) {
2907  SDValue N1 = N->getOperand(1);
2908  EVT ExtVT = cast<VTSDNode>(N1)->getVT();
2909  SDLoc SL(N);
2910 
2911  SDValue Src = N0.getOperand(0);
2912  EVT SrcVT = Src.getValueType();
2913  if (SrcVT.bitsGE(ExtVT)) {
2914  SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
2915  return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
2916  }
2917  }
2918 
2919  return SDValue();
2920 }
2921 /// Split the 64-bit value \p LHS into two 32-bit components, and perform the
2922 /// binary operation \p Opc to it with the corresponding constant operands.
2924  DAGCombinerInfo &DCI, const SDLoc &SL,
2925  unsigned Opc, SDValue LHS,
2926  uint32_t ValLo, uint32_t ValHi) const {
2927  SelectionDAG &DAG = DCI.DAG;
2928  SDValue Lo, Hi;
2929  std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
2930 
2931  SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
2932  SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
2933 
2934  SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
2935  SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
2936 
2937  // Re-visit the ands. It's possible we eliminated one of them and it could
2938  // simplify the vector.
2939  DCI.AddToWorklist(Lo.getNode());
2940  DCI.AddToWorklist(Hi.getNode());
2941 
2942  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
2943  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2944 }
2945 
2947  DAGCombinerInfo &DCI) const {
2948  EVT VT = N->getValueType(0);
2949 
2951  if (!RHS)
2952  return SDValue();
2953 
2954  SDValue LHS = N->getOperand(0);
2955  unsigned RHSVal = RHS->getZExtValue();
2956  if (!RHSVal)
2957  return LHS;
2958 
2959  SDLoc SL(N);
2960  SelectionDAG &DAG = DCI.DAG;
2961 
2962  switch (LHS->getOpcode()) {
2963  default:
2964  break;
2965  case ISD::ZERO_EXTEND:
2966  case ISD::SIGN_EXTEND:
2967  case ISD::ANY_EXTEND: {
2968  SDValue X = LHS->getOperand(0);
2969 
2970  if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
2972  // Prefer build_vector as the canonical form if packed types are legal.
2973  // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
2974  SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
2975  { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
2976  return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
2977  }
2978 
2979  // shl (ext x) => zext (shl x), if shift does not overflow int
2980  if (VT != MVT::i64)
2981  break;
2982  KnownBits Known = DAG.computeKnownBits(X);
2983  unsigned LZ = Known.countMinLeadingZeros();
2984  if (LZ < RHSVal)
2985  break;
2986  EVT XVT = X.getValueType();
2987  SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
2988  return DAG.getZExtOrTrunc(Shl, SL, VT);
2989  }
2990  }
2991 
2992  if (VT != MVT::i64)
2993  return SDValue();
2994 
2995  // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
2996 
2997  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
2998  // common case, splitting this into a move and a 32-bit shift is faster and
2999  // the same code size.
3000  if (RHSVal < 32)
3001  return SDValue();
3002 
3003  SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3004 
3005  SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3006  SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3007 
3008  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3009 
3010  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3011  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3012 }
3013 
3015  DAGCombinerInfo &DCI) const {
3016  if (N->getValueType(0) != MVT::i64)
3017  return SDValue();
3018 
3019  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3020  if (!RHS)
3021  return SDValue();
3022 
3023  SelectionDAG &DAG = DCI.DAG;
3024  SDLoc SL(N);
3025  unsigned RHSVal = RHS->getZExtValue();
3026 
3027  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3028  if (RHSVal == 32) {
3029  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3030  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3031  DAG.getConstant(31, SL, MVT::i32));
3032 
3033  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3034  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3035  }
3036 
3037  // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3038  if (RHSVal == 63) {
3039  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3040  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3041  DAG.getConstant(31, SL, MVT::i32));
3042  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3043  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3044  }
3045 
3046  return SDValue();
3047 }
3048 
3050  DAGCombinerInfo &DCI) const {
3051  if (N->getValueType(0) != MVT::i64)
3052  return SDValue();
3053 
3054  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3055  if (!RHS)
3056  return SDValue();
3057 
3058  unsigned ShiftAmt = RHS->getZExtValue();
3059  if (ShiftAmt < 32)
3060  return SDValue();
3061 
3062  // srl i64:x, C for C >= 32
3063  // =>
3064  // build_pair (srl hi_32(x), C - 32), 0
3065 
3066  SelectionDAG &DAG = DCI.DAG;
3067  SDLoc SL(N);
3068 
3069  SDValue One = DAG.getConstant(1, SL, MVT::i32);
3070  SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3071 
3072  SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
3074  VecOp, One);
3075 
3076  SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3077  SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3078 
3079  SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3080 
3081  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3082 }
3083 
3085  SDNode *N, DAGCombinerInfo &DCI) const {
3086  SDLoc SL(N);
3087  SelectionDAG &DAG = DCI.DAG;
3088  EVT VT = N->getValueType(0);
3089  SDValue Src = N->getOperand(0);
3090 
3091  // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3092  if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3093  SDValue Vec = Src.getOperand(0);
3094  if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3095  SDValue Elt0 = Vec.getOperand(0);
3096  EVT EltVT = Elt0.getValueType();
3097  if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3098  if (EltVT.isFloatingPoint()) {
3099  Elt0 = DAG.getNode(ISD::BITCAST, SL,
3100  EltVT.changeTypeToInteger(), Elt0);
3101  }
3102 
3103  return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3104  }
3105  }
3106  }
3107 
3108  // Equivalent of above for accessing the high element of a vector as an
3109  // integer operation.
3110  // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3111  if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3112  if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3113  if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3114  SDValue BV = stripBitcast(Src.getOperand(0));
3115  if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3116  BV.getValueType().getVectorNumElements() == 2) {
3117  SDValue SrcElt = BV.getOperand(1);
3118  EVT SrcEltVT = SrcElt.getValueType();
3119  if (SrcEltVT.isFloatingPoint()) {
3120  SrcElt = DAG.getNode(ISD::BITCAST, SL,
3121  SrcEltVT.changeTypeToInteger(), SrcElt);
3122  }
3123 
3124  return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3125  }
3126  }
3127  }
3128  }
3129 
3130  // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3131  //
3132  // i16 (trunc (srl i64:x, K)), K <= 16 ->
3133  // i16 (trunc (srl (i32 (trunc x), K)))
3134  if (VT.getScalarSizeInBits() < 32) {
3135  EVT SrcVT = Src.getValueType();
3136  if (SrcVT.getScalarSizeInBits() > 32 &&
3137  (Src.getOpcode() == ISD::SRL ||
3138  Src.getOpcode() == ISD::SRA ||
3139  Src.getOpcode() == ISD::SHL)) {
3140  SDValue Amt = Src.getOperand(1);
3141  KnownBits Known = DAG.computeKnownBits(Amt);
3142  unsigned Size = VT.getScalarSizeInBits();
3143  if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3144  (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3145  EVT MidVT = VT.isVector() ?
3148 
3149  EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3150  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3151  Src.getOperand(0));
3152  DCI.AddToWorklist(Trunc.getNode());
3153 
3154  if (Amt.getValueType() != NewShiftVT) {
3155  Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3156  DCI.AddToWorklist(Amt.getNode());
3157  }
3158 
3159  SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3160  Trunc, Amt);
3161  return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3162  }
3163  }
3164  }
3165 
3166  return SDValue();
3167 }
3168 
3169 // We need to specifically handle i64 mul here to avoid unnecessary conversion
3170 // instructions. If we only match on the legalized i64 mul expansion,
3171 // SimplifyDemandedBits will be unable to remove them because there will be
3172 // multiple uses due to the separate mul + mulh[su].
3173 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3174  SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3175  if (Size <= 32) {
3176  unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3177  return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3178  }
3179 
3180  // Because we want to eliminate extension instructions before the
3181  // operation, we need to create a single user here (i.e. not the separate
3182  // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3183 
3184  unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
3185 
3186  SDValue Mul = DAG.getNode(MulOpc, SL,
3187  DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3188 
3189  return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3190  Mul.getValue(0), Mul.getValue(1));
3191 }
3192 
3194  DAGCombinerInfo &DCI) const {
3195  EVT VT = N->getValueType(0);
3196 
3197  unsigned Size = VT.getSizeInBits();
3198  if (VT.isVector() || Size > 64)
3199  return SDValue();
3200 
3201  // There are i16 integer mul/mad.
3202  if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3203  return SDValue();
3204 
3205  SelectionDAG &DAG = DCI.DAG;
3206  SDLoc DL(N);
3207 
3208  SDValue N0 = N->getOperand(0);
3209  SDValue N1 = N->getOperand(1);
3210 
3211  // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3212  // in the source into any_extends if the result of the mul is truncated. Since
3213  // we can assume the high bits are whatever we want, use the underlying value
3214  // to avoid the unknown high bits from interfering.
3215  if (N0.getOpcode() == ISD::ANY_EXTEND)
3216  N0 = N0.getOperand(0);
3217 
3218  if (N1.getOpcode() == ISD::ANY_EXTEND)
3219  N1 = N1.getOperand(0);
3220 
3221  SDValue Mul;
3222 
3223  if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3224  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3225  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3226  Mul = getMul24(DAG, DL, N0, N1, Size, false);
3227  } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3228  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3229  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3230  Mul = getMul24(DAG, DL, N0, N1, Size, true);
3231  } else {
3232  return SDValue();
3233  }
3234 
3235  // We need to use sext even for MUL_U24, because MUL_U24 is used
3236  // for signed multiply of 8 and 16-bit types.
3237  return DAG.getSExtOrTrunc(Mul, DL, VT);
3238 }
3239 
3241  DAGCombinerInfo &DCI) const {
3242  EVT VT = N->getValueType(0);
3243 
3244  if (!Subtarget->hasMulI24() || VT.isVector())
3245  return SDValue();
3246 
3247  SelectionDAG &DAG = DCI.DAG;
3248  SDLoc DL(N);
3249 
3250  SDValue N0 = N->getOperand(0);
3251  SDValue N1 = N->getOperand(1);
3252 
3253  if (!isI24(N0, DAG) || !isI24(N1, DAG))
3254  return SDValue();
3255 
3256  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3257  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3258 
3259  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3260  DCI.AddToWorklist(Mulhi.getNode());
3261  return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3262 }
3263 
3265  DAGCombinerInfo &DCI) const {
3266  EVT VT = N->getValueType(0);
3267 
3268  if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3269  return SDValue();
3270 
3271  SelectionDAG &DAG = DCI.DAG;
3272  SDLoc DL(N);
3273 
3274  SDValue N0 = N->getOperand(0);
3275  SDValue N1 = N->getOperand(1);
3276 
3277  if (!isU24(N0, DAG) || !isU24(N1, DAG))
3278  return SDValue();
3279 
3280  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3281  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3282 
3283  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3284  DCI.AddToWorklist(Mulhi.getNode());
3285  return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3286 }
3287 
3289  SDNode *N, DAGCombinerInfo &DCI) const {
3290  SelectionDAG &DAG = DCI.DAG;
3291 
3292  // Simplify demanded bits before splitting into multiple users.
3293  if (SDValue V = simplifyI24(N, DCI))
3294  return V;
3295 
3296  SDValue N0 = N->getOperand(0);
3297  SDValue N1 = N->getOperand(1);
3298 
3299  bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3300 
3301  unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3302  unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3303 
3304  SDLoc SL(N);
3305 
3306  SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3307  SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3308  return DAG.getMergeValues({ MulLo, MulHi }, SL);
3309 }
3310 
3311 static bool isNegativeOne(SDValue Val) {
3312  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3313  return C->isAllOnesValue();
3314  return false;
3315 }
3316 
3317 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3318  SDValue Op,
3319  const SDLoc &DL,
3320  unsigned Opc) const {
3321  EVT VT = Op.getValueType();
3322  EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3323  if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3324  LegalVT != MVT::i16))
3325  return SDValue();
3326 
3327  if (VT != MVT::i32)
3328  Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3329 
3330  SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3331  if (VT != MVT::i32)
3332  FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3333 
3334  return FFBX;
3335 }
3336 
3337 // The native instructions return -1 on 0 input. Optimize out a select that
3338 // produces -1 on 0.
3339 //
3340 // TODO: If zero is not undef, we could also do this if the output is compared
3341 // against the bitwidth.
3342 //
3343 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3345  SDValue LHS, SDValue RHS,
3346  DAGCombinerInfo &DCI) const {
3347  ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3348  if (!CmpRhs || !CmpRhs->isNullValue())
3349  return SDValue();
3350 
3351  SelectionDAG &DAG = DCI.DAG;
3352  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3353  SDValue CmpLHS = Cond.getOperand(0);
3354 
3355  unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3357 
3358  // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3359  // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3360  if (CCOpcode == ISD::SETEQ &&
3361  (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3362  RHS.getOperand(0) == CmpLHS &&
3363  isNegativeOne(LHS)) {
3364  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3365  }
3366 
3367  // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3368  // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3369  if (CCOpcode == ISD::SETNE &&
3370  (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3371  LHS.getOperand(0) == CmpLHS &&
3372  isNegativeOne(RHS)) {
3373  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3374  }
3375 
3376  return SDValue();
3377 }
3378 
3380  unsigned Op,
3381  const SDLoc &SL,
3382  SDValue Cond,
3383  SDValue N1,
3384  SDValue N2) {
3385  SelectionDAG &DAG = DCI.DAG;
3386  EVT VT = N1.getValueType();
3387 
3388  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3389  N1.getOperand(0), N2.getOperand(0));
3390  DCI.AddToWorklist(NewSelect.getNode());
3391  return DAG.getNode(Op, SL, VT, NewSelect);
3392 }
3393 
3394 // Pull a free FP operation out of a select so it may fold into uses.
3395 //
3396 // select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3397 // select c, (fneg x), k -> fneg (select c, x, (fneg k))
3398 //
3399 // select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3400 // select c, (fabs x), +k -> fabs (select c, x, k)
3402  SDValue N) {
3403  SelectionDAG &DAG = DCI.DAG;
3404  SDValue Cond = N.getOperand(0);
3405  SDValue LHS = N.getOperand(1);
3406  SDValue RHS = N.getOperand(2);
3407 
3408  EVT VT = N.getValueType();
3409  if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3410  (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3411  return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3412  SDLoc(N), Cond, LHS, RHS);
3413  }
3414 
3415  bool Inv = false;
3416  if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3417  std::swap(LHS, RHS);
3418  Inv = true;
3419  }
3420 
3421  // TODO: Support vector constants.
3423  if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3424  SDLoc SL(N);
3425  // If one side is an fneg/fabs and the other is a constant, we can push the
3426  // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3427  SDValue NewLHS = LHS.getOperand(0);
3428  SDValue NewRHS = RHS;
3429 
3430  // Careful: if the neg can be folded up, don't try to pull it back down.
3431  bool ShouldFoldNeg = true;
3432 
3433  if (NewLHS.hasOneUse()) {
3434  unsigned Opc = NewLHS.getOpcode();
3435  if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3436  ShouldFoldNeg = false;
3437  if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3438  ShouldFoldNeg = false;
3439  }
3440 
3441  if (ShouldFoldNeg) {
3442  if (LHS.getOpcode() == ISD::FNEG)
3443  NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3444  else if (CRHS->isNegative())
3445  return SDValue();
3446 
3447  if (Inv)
3448  std::swap(NewLHS, NewRHS);
3449 
3450  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3451  Cond, NewLHS, NewRHS);
3452  DCI.AddToWorklist(NewSelect.getNode());
3453  return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3454  }
3455  }
3456 
3457  return SDValue();
3458 }
3459 
3460 
3462  DAGCombinerInfo &DCI) const {
3463  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3464  return Folded;
3465 
3466  SDValue Cond = N->getOperand(0);
3467  if (Cond.getOpcode() != ISD::SETCC)
3468  return SDValue();
3469 
3470  EVT VT = N->getValueType(0);
3471  SDValue LHS = Cond.getOperand(0);
3472  SDValue RHS = Cond.getOperand(1);
3473  SDValue CC = Cond.getOperand(2);
3474 
3475  SDValue True = N->getOperand(1);
3476  SDValue False = N->getOperand(2);
3477 
3478  if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3479  SelectionDAG &DAG = DCI.DAG;
3480  if ((DAG.isConstantValueOfAnyType(True) ||
3481  DAG.isConstantValueOfAnyType(True)) &&
3482  (!DAG.isConstantValueOfAnyType(False) &&
3483  !DAG.isConstantValueOfAnyType(False))) {
3484  // Swap cmp + select pair to move constant to false input.
3485  // This will allow using VOPC cndmasks more often.
3486  // select (setcc x, y), k, x -> select (setcc y, x) x, x
3487 
3488  SDLoc SL(N);
3489  ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3490  LHS.getValueType().isInteger());
3491 
3492  SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3493  return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3494  }
3495 
3496  if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3497  SDValue MinMax
3498  = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3499  // Revisit this node so we can catch min3/max3/med3 patterns.
3500  //DCI.AddToWorklist(MinMax.getNode());
3501  return MinMax;
3502  }
3503  }
3504 
3505  // There's no reason to not do this if the condition has other uses.
3506  return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3507 }
3508 
3509 static bool isInv2Pi(const APFloat &APF) {
3510  static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3511  static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3512  static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3513 
3514  return APF.bitwiseIsEqual(KF16) ||
3515  APF.bitwiseIsEqual(KF32) ||
3516  APF.bitwiseIsEqual(KF64);
3517 }
3518 
3519 // 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3520 // additional cost to negate them.
3522  if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3523  if (C->isZero() && !C->isNegative())
3524  return true;
3525 
3526  if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3527  return true;
3528  }
3529 
3530  return false;
3531 }
3532 
3533 static unsigned inverseMinMax(unsigned Opc) {
3534  switch (Opc) {
3535  case ISD::FMAXNUM:
3536  return ISD::FMINNUM;
3537  case ISD::FMINNUM:
3538  return ISD::FMAXNUM;
3539  case ISD::FMAXNUM_IEEE:
3540  return ISD::FMINNUM_IEEE;
3541  case ISD::FMINNUM_IEEE:
3542  return ISD::FMAXNUM_IEEE;
3544  return AMDGPUISD::FMIN_LEGACY;
3546  return AMDGPUISD::FMAX_LEGACY;
3547  default:
3548  llvm_unreachable("invalid min/max opcode");
3549  }
3550 }
3551 
3553  DAGCombinerInfo &DCI) const {
3554  SelectionDAG &DAG = DCI.DAG;
3555  SDValue N0 = N->getOperand(0);
3556  EVT VT = N->getValueType(0);
3557 
3558  unsigned Opc = N0.getOpcode();
3559 
3560  // If the input has multiple uses and we can either fold the negate down, or
3561  // the other uses cannot, give up. This both prevents unprofitable
3562  // transformations and infinite loops: we won't repeatedly try to fold around
3563  // a negate that has no 'good' form.
3564  if (N0.hasOneUse()) {
3565  // This may be able to fold into the source, but at a code size cost. Don't
3566  // fold if the fold into the user is free.
3567  if (allUsesHaveSourceMods(N, 0))
3568  return SDValue();
3569  } else {
3570  if (fnegFoldsIntoOp(Opc) &&
3572  return SDValue();
3573  }
3574 
3575  SDLoc SL(N);
3576  switch (Opc) {
3577  case ISD::FADD: {
3578  if (!mayIgnoreSignedZero(N0))
3579  return SDValue();
3580 
3581  // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3582  SDValue LHS = N0.getOperand(0);
3583  SDValue RHS = N0.getOperand(1);
3584 
3585  if (LHS.getOpcode() != ISD::FNEG)
3586  LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3587  else
3588  LHS = LHS.getOperand(0);
3589 
3590  if (RHS.getOpcode() != ISD::FNEG)
3591  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3592  else
3593  RHS = RHS.getOperand(0);
3594 
3595  SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3596  if (!N0.hasOneUse())
3597  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3598  return Res;
3599  }
3600  case ISD::FMUL:
3601  case AMDGPUISD::FMUL_LEGACY: {
3602  // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3603  // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3604  SDValue LHS = N0.getOperand(0);
3605  SDValue RHS = N0.getOperand(1);
3606 
3607  if (LHS.getOpcode() == ISD::FNEG)
3608  LHS = LHS.getOperand(0);
3609  else if (RHS.getOpcode() == ISD::FNEG)
3610  RHS = RHS.getOperand(0);
3611  else
3612  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3613 
3614  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3615  if (!N0.hasOneUse())
3616  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3617  return Res;
3618  }
3619  case ISD::FMA:
3620  case ISD::FMAD: {
3621  if (!mayIgnoreSignedZero(N0))
3622  return SDValue();
3623 
3624  // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3625  SDValue LHS = N0.getOperand(0);
3626  SDValue MHS = N0.getOperand(1);
3627  SDValue RHS = N0.getOperand(2);
3628 
3629  if (LHS.getOpcode() == ISD::FNEG)
3630  LHS = LHS.getOperand(0);
3631  else if (MHS.getOpcode() == ISD::FNEG)
3632  MHS = MHS.getOperand(0);
3633  else
3634  MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3635 
3636  if (RHS.getOpcode() != ISD::FNEG)
3637  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3638  else
3639  RHS = RHS.getOperand(0);
3640 
3641  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3642  if (!N0.hasOneUse())
3643  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3644  return Res;
3645  }
3646  case ISD::FMAXNUM:
3647  case ISD::FMINNUM:
3648  case ISD::FMAXNUM_IEEE:
3649  case ISD::FMINNUM_IEEE:
3651  case AMDGPUISD::FMIN_LEGACY: {
3652  // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3653  // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3654  // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3655  // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3656 
3657  SDValue LHS = N0.getOperand(0);
3658  SDValue RHS = N0.getOperand(1);
3659 
3660  // 0 doesn't have a negated inline immediate.
3661  // TODO: This constant check should be generalized to other operations.
3662  if (isConstantCostlierToNegate(RHS))
3663  return SDValue();
3664 
3665  SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3666  SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3667  unsigned Opposite = inverseMinMax(Opc);
3668 
3669  SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3670  if (!N0.hasOneUse())
3671  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3672  return Res;
3673  }
3674  case AMDGPUISD::FMED3: {
3675  SDValue Ops[3];
3676  for (unsigned I = 0; I < 3; ++I)
3677  Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3678 
3679  SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3680  if (!N0.hasOneUse())
3681  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3682  return Res;
3683  }
3684  case ISD::FP_EXTEND:
3685  case ISD::FTRUNC:
3686  case ISD::FRINT:
3687  case ISD::FNEARBYINT: // XXX - Should fround be handled?
3688  case ISD::FSIN:
3689  case ISD::FCANONICALIZE:
3690  case AMDGPUISD::RCP:
3691  case AMDGPUISD::RCP_LEGACY:
3692  case AMDGPUISD::RCP_IFLAG:
3693  case AMDGPUISD::SIN_HW: {
3694  SDValue CvtSrc = N0.getOperand(0);
3695  if (CvtSrc.getOpcode() == ISD::FNEG) {
3696  // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3697  // (fneg (rcp (fneg x))) -> (rcp x)
3698  return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3699  }
3700 
3701  if (!N0.hasOneUse())
3702  return SDValue();
3703 
3704  // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3705  // (fneg (rcp x)) -> (rcp (fneg x))
3706  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3707  return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3708  }
3709  case ISD::FP_ROUND: {
3710  SDValue CvtSrc = N0.getOperand(0);
3711 
3712  if (CvtSrc.getOpcode() == ISD::FNEG) {
3713  // (fneg (fp_round (fneg x))) -> (fp_round x)
3714  return DAG.getNode(ISD::FP_ROUND, SL, VT,
3715  CvtSrc.getOperand(0), N0.getOperand(1));
3716  }
3717 
3718  if (!N0.hasOneUse())
3719  return SDValue();
3720 
3721  // (fneg (fp_round x)) -> (fp_round (fneg x))
3722  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3723  return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3724  }
3725  case ISD::FP16_TO_FP: {
3726  // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3727  // f16, but legalization of f16 fneg ends up pulling it out of the source.
3728  // Put the fneg back as a legal source operation that can be matched later.
3729  SDLoc SL(N);
3730 
3731  SDValue Src = N0.getOperand(0);
3732  EVT SrcVT = Src.getValueType();
3733 
3734  // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3735  SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3736  DAG.getConstant(0x8000, SL, SrcVT));
3737  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3738  }
3739  default:
3740  return SDValue();
3741  }
3742 }
3743 
3745  DAGCombinerInfo &DCI) const {
3746  SelectionDAG &DAG = DCI.DAG;
3747  SDValue N0 = N->getOperand(0);
3748 
3749  if (!N0.hasOneUse())
3750  return SDValue();
3751 
3752  switch (N0.getOpcode()) {
3753  case ISD::FP16_TO_FP: {
3754  assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3755  SDLoc SL(N);
3756  SDValue Src = N0.getOperand(0);
3757  EVT SrcVT = Src.getValueType();
3758 
3759  // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3760  SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3761  DAG.getConstant(0x7fff, SL, SrcVT));
3762  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3763  }
3764  default:
3765  return SDValue();
3766  }
3767 }
3768 
3770  DAGCombinerInfo &DCI) const {
3771  const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3772  if (!CFP)
3773  return SDValue();
3774 
3775  // XXX - Should this flush denormals?
3776  const APFloat &Val = CFP->getValueAPF();
3777  APFloat One(Val.getSemantics(), "1.0");
3778  return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3779 }
3780 
3782  DAGCombinerInfo &DCI) const {
3783  SelectionDAG &DAG = DCI.DAG;
3784  SDLoc DL(N);
3785 
3786  switch(N->getOpcode()) {
3787  default:
3788  break;
3789  case ISD::BITCAST: {
3790  EVT DestVT = N->getValueType(0);
3791 
3792  // Push casts through vector builds. This helps avoid emitting a large
3793  // number of copies when materializing floating point vector constants.
3794  //
3795  // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3796  // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3797  if (DestVT.isVector()) {
3798  SDValue Src = N->getOperand(0);
3799  if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3800  EVT SrcVT = Src.getValueType();
3801  unsigned NElts = DestVT.getVectorNumElements();
3802 
3803  if (SrcVT.getVectorNumElements() == NElts) {
3804  EVT DestEltVT = DestVT.getVectorElementType();
3805 
3806  SmallVector<SDValue, 8> CastedElts;
3807  SDLoc SL(N);
3808  for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3809  SDValue Elt = Src.getOperand(I);
3810  CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3811  }
3812 
3813  return DAG.getBuildVector(DestVT, SL, CastedElts);
3814  }
3815  }
3816  }
3817 
3818  if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
3819  break;
3820 
3821  // Fold bitcasts of constants.
3822  //
3823  // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3824  // TODO: Generalize and move to DAGCombiner
3825  SDValue Src = N->getOperand(0);
3826  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3827  if (Src.getValueType() == MVT::i64) {
3828  SDLoc SL(N);
3829  uint64_t CVal = C->getZExtValue();
3831  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3832  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3833  return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
3834  }
3835  }
3836 
3837  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3838  const APInt &Val = C->getValueAPF().bitcastToAPInt();
3839  SDLoc SL(N);
3840  uint64_t CVal = Val.getZExtValue();
3842  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3843  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3844 
3845  return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3846  }
3847 
3848  break;
3849  }
3850  case ISD::SHL: {
3852  break;
3853 
3854  return performShlCombine(N, DCI);
3855  }
3856  case ISD::SRL: {
3858  break;
3859 
3860  return performSrlCombine(N, DCI);
3861  }
3862  case ISD::SRA: {
3864  break;
3865 
3866  return performSraCombine(N, DCI);
3867  }
3868  case ISD::TRUNCATE:
3869  return performTruncateCombine(N, DCI);
3870  case ISD::MUL:
3871  return performMulCombine(N, DCI);
3872  case ISD::MULHS:
3873  return performMulhsCombine(N, DCI);
3874  case ISD::MULHU:
3875  return performMulhuCombine(N, DCI);
3876  case AMDGPUISD::MUL_I24:
3877  case AMDGPUISD::MUL_U24:
3878  case AMDGPUISD::MULHI_I24:
3879  case AMDGPUISD::MULHI_U24: {
3880  if (SDValue V = simplifyI24(N, DCI))
3881  return V;
3882  return SDValue();
3883  }
3886  return performMulLoHi24Combine(N, DCI);
3887  case ISD::SELECT:
3888  return performSelectCombine(N, DCI);
3889  case ISD::FNEG:
3890  return performFNegCombine(N, DCI);
3891  case ISD::FABS:
3892  return performFAbsCombine(N, DCI);
3893  case AMDGPUISD::BFE_I32:
3894  case AMDGPUISD::BFE_U32: {
3895  assert(!N->getValueType(0).isVector() &&
3896  "Vector handling of BFE not implemented");
3898  if (!Width)
3899  break;
3900 
3901  uint32_t WidthVal = Width->getZExtValue() & 0x1f;
3902  if (WidthVal == 0)
3903  return DAG.getConstant(0, DL, MVT::i32);
3904 
3906  if (!Offset)
3907  break;
3908 
3909  SDValue BitsFrom = N->getOperand(0);
3910  uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
3911 
3912  bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
3913 
3914  if (OffsetVal == 0) {
3915  // This is already sign / zero extended, so try to fold away extra BFEs.
3916  unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
3917 
3918  unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
3919  if (OpSignBits >= SignBits)
3920  return BitsFrom;
3921 
3922  EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
3923  if (Signed) {
3924  // This is a sign_extend_inreg. Replace it to take advantage of existing
3925  // DAG Combines. If not eliminated, we will match back to BFE during
3926  // selection.
3927 
3928  // TODO: The sext_inreg of extended types ends, although we can could
3929  // handle them in a single BFE.
3930  return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
3931  DAG.getValueType(SmallVT));
3932  }
3933 
3934  return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
3935  }
3936 
3937  if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
3938  if (Signed) {
3939  return constantFoldBFE<int32_t>(DAG,
3940  CVal->getSExtValue(),
3941  OffsetVal,
3942  WidthVal,
3943  DL);
3944  }
3945 
3946  return constantFoldBFE<uint32_t>(DAG,
3947  CVal->getZExtValue(),
3948  OffsetVal,
3949  WidthVal,
3950  DL);
3951  }
3952 
3953  if ((OffsetVal + WidthVal) >= 32 &&
3954  !(Subtarget->hasSDWA() && OffsetVal == 16 && WidthVal == 16)) {
3955  SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
3956  return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
3957  BitsFrom, ShiftVal);
3958  }
3959 
3960  if (BitsFrom.hasOneUse()) {
3961  APInt Demanded = APInt::getBitsSet(32,
3962  OffsetVal,
3963  OffsetVal + WidthVal);
3964 
3965  KnownBits Known;
3967  !DCI.isBeforeLegalizeOps());
3968  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3969  if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
3970  TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
3971  DCI.CommitTargetLoweringOpt(TLO);
3972  }
3973  }
3974 
3975  break;
3976  }
3977  case ISD::LOAD:
3978  return performLoadCombine(N, DCI);
3979  case ISD::STORE:
3980  return performStoreCombine(N, DCI);
3981  case AMDGPUISD::RCP:
3982  case AMDGPUISD::RCP_IFLAG:
3983  return performRcpCombine(N, DCI);
3984  case ISD::AssertZext:
3985  case ISD::AssertSext:
3986  return performAssertSZExtCombine(N, DCI);
3987  }
3988  return SDValue();
3989 }
3990 
3991 //===----------------------------------------------------------------------===//
3992 // Helper functions
3993 //===----------------------------------------------------------------------===//
3994 
3996  const TargetRegisterClass *RC,
3997  unsigned Reg, EVT VT,
3998  const SDLoc &SL,
3999  bool RawReg) const {
4000  MachineFunction &MF = DAG.getMachineFunction();
4002  unsigned VReg;
4003 
4004  if (!MRI.isLiveIn(Reg)) {
4005  VReg = MRI.createVirtualRegister(RC);
4006  MRI.addLiveIn(Reg, VReg);
4007  } else {
4008  VReg = MRI.getLiveInVirtReg(Reg);
4009  }
4010 
4011  if (RawReg)
4012  return DAG.getRegister(VReg, VT);
4013 
4014  return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4015 }
4016 
4018  EVT VT,
4019  const SDLoc &SL,
4020  int64_t Offset) const {
4021  MachineFunction &MF = DAG.getMachineFunction();
4022  MachineFrameInfo &MFI = MF.getFrameInfo();
4023 
4024  int FI = MFI.CreateFixedObject(VT.getStoreSize(), Offset, true);
4025  auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4026  SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4027 
4028  return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4,
4031 }
4032 
4034  const SDLoc &SL,
4035  SDValue Chain,
4036  SDValue ArgVal,
4037  int64_t Offset) const {
4038  MachineFunction &MF = DAG.getMachineFunction();
4039  MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4040 
4041  SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4042  SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
4044  return Store;
4045 }
4046 
4048  const TargetRegisterClass *RC,
4049  EVT VT, const SDLoc &SL,
4050  const ArgDescriptor &Arg) const {
4051  assert(Arg && "Attempting to load missing argument");
4052 
4053  if (Arg.isRegister())
4054  return CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL);
4055  return loadStackInputValue(DAG, VT, SL, Arg.getStackOffset());
4056 }
4057 
4059  const MachineFunction &MF, const ImplicitParameter Param) const {
4061  const AMDGPUSubtarget &ST =
4063  unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4064  unsigned Alignment = ST.getAlignmentForImplicitArgPtr();
4065  uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4066  ExplicitArgOffset;
4067  switch (Param) {
4068  case GRID_DIM:
4069  return ArgOffset;
4070  case GRID_OFFSET:
4071  return ArgOffset + 4;
4072  }
4073  llvm_unreachable("unexpected implicit parameter type");
4074 }
4075 
4076 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
4077 
4078 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4079  switch ((AMDGPUISD::NodeType)Opcode) {
4080  case AMDGPUISD::FIRST_NUMBER: break;
4081  // AMDIL DAG nodes
4084 
4085  // AMDGPU DAG nodes
4131