LLVM  12.0.0git
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llvm::SIMachineFunctionInfo Class Referencefinal

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load. More...

#include "Target/AMDGPU/SIMachineFunctionInfo.h"

Inheritance diagram for llvm::SIMachineFunctionInfo:
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Collaboration diagram for llvm::SIMachineFunctionInfo:
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Classes

struct  SGPRSpillVGPRCSR
 
struct  SpilledReg
 
struct  VGPRSpillToAGPR
 

Public Member Functions

void ReserveWWMRegister (Register Reg)
 
bool isCalleeSavedReg (const MCPhysReg *CSRegs, MCPhysReg Reg)
 
 SIMachineFunctionInfo (const MachineFunction &MF)
 
bool initializeBaseYamlFields (const yaml::SIMachineFunctionInfo &YamlMFI)
 
ArrayRef< SpilledReggetSGPRToVGPRSpills (int FrameIndex) const
 
ArrayRef< SGPRSpillVGPRCSRgetSGPRSpillVGPRs () const
 
void setSGPRSpillVGPRs (Register NewVGPR, Optional< int > newFI, int Index)
 
bool removeVGPRForSGPRSpill (Register ReservedVGPR, MachineFunction &MF)
 
ArrayRef< MCPhysReggetAGPRSpillVGPRs () const
 
ArrayRef< MCPhysReggetVGPRSpillAGPRs () const
 
MCPhysReg getVGPRToAGPRSpill (int FrameIndex, unsigned Lane) const
 
bool haveFreeLanesForSGPRSpill (const MachineFunction &MF, unsigned NumLane) const
 returns true if NumLanes slots are available in VGPRs already used for SGPR spilling. More...
 
bool allocateSGPRSpillToVGPR (MachineFunction &MF, int FI)
 Reserve a slice of a VGPR to support spilling for FrameIndex FI. More...
 
bool reserveVGPRforSGPRSpills (MachineFunction &MF)
 Reserve a VGPR for spilling of SGPRs. More...
 
bool allocateVGPRSpillToAGPR (MachineFunction &MF, int FI, bool isAGPRtoVGPR)
 Reserve AGPRs or VGPRs to support spilling for FrameIndex FI. More...
 
void removeDeadFrameIndices (MachineFrameInfo &MFI)
 
bool hasCalculatedTID () const
 
Register getTIDReg () const
 
void setTIDReg (Register Reg)
 
unsigned getBytesInStackArgArea () const
 
void setBytesInStackArgArea (unsigned Bytes)
 
Register addPrivateSegmentBuffer (const SIRegisterInfo &TRI)
 
Register addDispatchPtr (const SIRegisterInfo &TRI)
 
Register addQueuePtr (const SIRegisterInfo &TRI)
 
Register addKernargSegmentPtr (const SIRegisterInfo &TRI)
 
Register addDispatchID (const SIRegisterInfo &TRI)
 
Register addFlatScratchInit (const SIRegisterInfo &TRI)
 
Register addImplicitBufferPtr (const SIRegisterInfo &TRI)
 
Register addWorkGroupIDX ()
 
Register addWorkGroupIDY ()
 
Register addWorkGroupIDZ ()
 
Register addWorkGroupInfo ()
 
void setWorkItemIDX (ArgDescriptor Arg)
 
void setWorkItemIDY (ArgDescriptor Arg)
 
void setWorkItemIDZ (ArgDescriptor Arg)
 
Register addPrivateSegmentWaveByteOffset ()
 
void setPrivateSegmentWaveByteOffset (Register Reg)
 
bool hasPrivateSegmentBuffer () const
 
bool hasDispatchPtr () const
 
bool hasQueuePtr () const
 
bool hasKernargSegmentPtr () const
 
bool hasDispatchID () const
 
bool hasFlatScratchInit () const
 
bool hasWorkGroupIDX () const
 
bool hasWorkGroupIDY () const
 
bool hasWorkGroupIDZ () const
 
bool hasWorkGroupInfo () const
 
bool hasPrivateSegmentWaveByteOffset () const
 
bool hasWorkItemIDX () const
 
bool hasWorkItemIDY () const
 
bool hasWorkItemIDZ () const
 
bool hasImplicitArgPtr () const
 
bool hasImplicitBufferPtr () const
 
AMDGPUFunctionArgInfogetArgInfo ()
 
const AMDGPUFunctionArgInfogetArgInfo () const
 
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLTgetPreloadedValue (AMDGPUFunctionArgInfo::PreloadedValue Value) const
 
Register getPreloadedReg (AMDGPUFunctionArgInfo::PreloadedValue Value) const
 
unsigned getGITPtrHigh () const
 
Register getGITPtrLoReg (const MachineFunction &MF) const
 
uint32_t get32BitAddressHighBits () const
 
unsigned getGDSSize () const
 
unsigned getNumUserSGPRs () const
 
unsigned getNumPreloadedSGPRs () const
 
Register getPrivateSegmentWaveByteOffsetSystemSGPR () const
 
Register getScratchRSrcReg () const
 Returns the physical register reserved for use as the resource descriptor for scratch accesses. More...
 
void setScratchRSrcReg (Register Reg)
 
Register getFrameOffsetReg () const
 
void setFrameOffsetReg (Register Reg)
 
void setStackPtrOffsetReg (Register Reg)
 
Register getStackPtrOffsetReg () const
 
Register getQueuePtrUserSGPR () const
 
Register getImplicitBufferPtrUserSGPR () const
 
bool hasSpilledSGPRs () const
 
void setHasSpilledSGPRs (bool Spill=true)
 
bool hasSpilledVGPRs () const
 
void setHasSpilledVGPRs (bool Spill=true)
 
bool hasNonSpillStackObjects () const
 
void setHasNonSpillStackObjects (bool StackObject=true)
 
bool isStackRealigned () const
 
void setIsStackRealigned (bool Realigned=true)
 
unsigned getNumSpilledSGPRs () const
 
unsigned getNumSpilledVGPRs () const
 
void addToSpilledSGPRs (unsigned num)
 
void addToSpilledVGPRs (unsigned num)
 
unsigned getPSInputAddr () const
 
unsigned getPSInputEnable () const
 
bool isPSInputAllocated (unsigned Index) const
 
void markPSInputAllocated (unsigned Index)
 
void markPSInputEnabled (unsigned Index)
 
bool returnsVoid () const
 
void setIfReturnsVoid (bool Value)
 
std::pair< unsigned, unsignedgetFlatWorkGroupSizes () const
 
unsigned getMinFlatWorkGroupSize () const
 
unsigned getMaxFlatWorkGroupSize () const
 
std::pair< unsigned, unsignedgetWavesPerEU () const
 
unsigned getMinWavesPerEU () const
 
unsigned getMaxWavesPerEU () const
 
Register getWorkGroupIDSGPR (unsigned Dim) const
 
unsigned getLDSWaveSpillSize () const
 
const AMDGPUBufferPseudoSourceValuegetBufferPSV (const SIInstrInfo &TII, const Value *BufferRsrc)
 
const AMDGPUImagePseudoSourceValuegetImagePSV (const SIInstrInfo &TII, const Value *ImgRsrc)
 
const AMDGPUGWSResourcePseudoSourceValuegetGWSPSV (const SIInstrInfo &TII)
 
unsigned getOccupancy () const
 
unsigned getMinAllowedOccupancy () const
 
void limitOccupancy (const MachineFunction &MF)
 
void limitOccupancy (unsigned Limit)
 
void increaseOccupancy (const MachineFunction &MF, unsigned Limit)
 
- Public Member Functions inherited from llvm::AMDGPUMachineFunction
 AMDGPUMachineFunction (const MachineFunction &MF)
 
uint64_t getExplicitKernArgSize () const
 
unsigned getMaxKernArgAlign () const
 
unsigned getLDSSize () const
 
AMDGPU::SIModeRegisterDefaults getMode () const
 
bool isEntryFunction () const
 
bool hasNoSignedZerosFPMath () const
 
bool isMemoryBound () const
 
bool needsWaveLimiter () const
 
unsigned allocateLDSGlobal (const DataLayout &DL, const GlobalVariable &GV)
 
- Public Member Functions inherited from llvm::MachineFunctionInfo
virtual ~MachineFunctionInfo ()
 

Public Attributes

SparseBitVector WWMReservedRegs
 
Register SGPRForFPSaveRestoreCopy
 If this is set, an SGPR used for save/restore of the register used for the frame pointer. More...
 
Optional< int > FramePointerSaveIndex
 
Register SGPRForBPSaveRestoreCopy
 If this is set, an SGPR used for save/restore of the register used for the base pointer. More...
 
Optional< int > BasePointerSaveIndex
 
Register VGPRReservedForSGPRSpill
 

Friends

class GCNTargetMachine
 

Additional Inherited Members

- Static Public Member Functions inherited from llvm::MachineFunctionInfo
template<typename Ty >
static Ty * create (BumpPtrAllocator &Allocator, MachineFunction &MF)
 Factory function: default behavior is to call new using the supplied allocator. More...
 
- Protected Attributes inherited from llvm::AMDGPUMachineFunction
uint64_t ExplicitKernArgSize = 0
 
Align MaxKernArgAlign
 
unsigned LDSSize = 0
 Number of bytes in the LDS that are being used. More...
 
AMDGPU::SIModeRegisterDefaults Mode
 
bool IsEntryFunction = false
 
bool NoSignedZerosFPMath = false
 
bool MemoryBound = false
 
bool WaveLimiter = false
 

Detailed Description

This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which interpolation parameters to load.

Definition at line 328 of file SIMachineFunctionInfo.h.

Constructor & Destructor Documentation

◆ SIMachineFunctionInfo()

SIMachineFunctionInfo::SIMachineFunctionInfo ( const MachineFunction MF)

Member Function Documentation

◆ addDispatchID()

Register SIMachineFunctionInfo::addDispatchID ( const SIRegisterInfo TRI)

◆ addDispatchPtr()

Register SIMachineFunctionInfo::addDispatchPtr ( const SIRegisterInfo TRI)

◆ addFlatScratchInit()

Register SIMachineFunctionInfo::addFlatScratchInit ( const SIRegisterInfo TRI)

◆ addImplicitBufferPtr()

Register SIMachineFunctionInfo::addImplicitBufferPtr ( const SIRegisterInfo TRI)

◆ addKernargSegmentPtr()

Register SIMachineFunctionInfo::addKernargSegmentPtr ( const SIRegisterInfo TRI)

◆ addPrivateSegmentBuffer()

Register SIMachineFunctionInfo::addPrivateSegmentBuffer ( const SIRegisterInfo TRI)

◆ addPrivateSegmentWaveByteOffset()

Register llvm::SIMachineFunctionInfo::addPrivateSegmentWaveByteOffset ( )
inline

◆ addQueuePtr()

Register SIMachineFunctionInfo::addQueuePtr ( const SIRegisterInfo TRI)

◆ addToSpilledSGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledSGPRs ( unsigned  num)
inline

Definition at line 799 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::spillSGPR().

◆ addToSpilledVGPRs()

void llvm::SIMachineFunctionInfo::addToSpilledVGPRs ( unsigned  num)
inline

◆ addWorkGroupIDX()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDX ( )
inline

◆ addWorkGroupIDY()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDY ( )
inline

◆ addWorkGroupIDZ()

Register llvm::SIMachineFunctionInfo::addWorkGroupIDZ ( )
inline

◆ addWorkGroupInfo()

Register llvm::SIMachineFunctionInfo::addWorkGroupInfo ( )
inline

◆ allocateSGPRSpillToVGPR()

bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR ( MachineFunction MF,
int  FI 
)

◆ allocateVGPRSpillToAGPR()

bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR ( MachineFunction MF,
int  FI,
bool  isAGPRtoVGPR 
)

◆ get32BitAddressHighBits()

uint32_t llvm::SIMachineFunctionInfo::get32BitAddressHighBits ( ) const
inline

◆ getAGPRSpillVGPRs()

ArrayRef<MCPhysReg> llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs ( ) const
inline

◆ getArgInfo() [1/2]

AMDGPUFunctionArgInfo& llvm::SIMachineFunctionInfo::getArgInfo ( )
inline

◆ getArgInfo() [2/2]

const AMDGPUFunctionArgInfo& llvm::SIMachineFunctionInfo::getArgInfo ( ) const
inline

Definition at line 678 of file SIMachineFunctionInfo.h.

◆ getBufferPSV()

const AMDGPUBufferPseudoSourceValue* llvm::SIMachineFunctionInfo::getBufferPSV ( const SIInstrInfo TII,
const Value BufferRsrc 
)
inline

Definition at line 887 of file SIMachineFunctionInfo.h.

References assert().

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic().

◆ getBytesInStackArgArea()

unsigned llvm::SIMachineFunctionInfo::getBytesInStackArgArea ( ) const
inline

◆ getFlatWorkGroupSizes()

std::pair<unsigned, unsigned> llvm::SIMachineFunctionInfo::getFlatWorkGroupSizes ( ) const
inline
Returns
A pair of default/requested minimum/maximum flat work group sizes for this function.

Definition at line 837 of file SIMachineFunctionInfo.h.

◆ getFrameOffsetReg()

Register llvm::SIMachineFunctionInfo::getFrameOffsetReg ( ) const
inline

◆ getGDSSize()

unsigned llvm::SIMachineFunctionInfo::getGDSSize ( ) const
inline

Definition at line 702 of file SIMachineFunctionInfo.h.

◆ getGITPtrHigh()

unsigned llvm::SIMachineFunctionInfo::getGITPtrHigh ( ) const
inline

◆ getGITPtrLoReg()

Register SIMachineFunctionInfo::getGITPtrLoReg ( const MachineFunction MF) const

◆ getGWSPSV()

const AMDGPUGWSResourcePseudoSourceValue* llvm::SIMachineFunctionInfo::getGWSPSV ( const SIInstrInfo TII)
inline

Definition at line 905 of file SIMachineFunctionInfo.h.

References TII.

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic().

◆ getImagePSV()

const AMDGPUImagePseudoSourceValue* llvm::SIMachineFunctionInfo::getImagePSV ( const SIInstrInfo TII,
const Value ImgRsrc 
)
inline

Definition at line 896 of file SIMachineFunctionInfo.h.

References assert().

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic().

◆ getImplicitBufferPtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getImplicitBufferPtrUserSGPR ( ) const
inline

◆ getLDSWaveSpillSize()

unsigned llvm::SIMachineFunctionInfo::getLDSWaveSpillSize ( ) const
inline

Definition at line 883 of file SIMachineFunctionInfo.h.

Referenced by getCalleeFunction().

◆ getMaxFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMaxFlatWorkGroupSize ( ) const
inline
Returns
Default/requested maximum flat work group size for this function.

Definition at line 847 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), and getCalleeFunction().

◆ getMaxWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMaxWavesPerEU ( ) const
inline
Returns
Default/requested maximum number of waves per execution unit.

Definition at line 863 of file SIMachineFunctionInfo.h.

Referenced by getCalleeFunction(), and limitOccupancy().

◆ getMinAllowedOccupancy()

unsigned llvm::SIMachineFunctionInfo::getMinAllowedOccupancy ( ) const
inline

◆ getMinFlatWorkGroupSize()

unsigned llvm::SIMachineFunctionInfo::getMinFlatWorkGroupSize ( ) const
inline
Returns
Default/requested minimum flat work group size for this function.

Definition at line 842 of file SIMachineFunctionInfo.h.

◆ getMinWavesPerEU()

unsigned llvm::SIMachineFunctionInfo::getMinWavesPerEU ( ) const
inline
Returns
Default/requested minimum number of waves per execution unit.

Definition at line 858 of file SIMachineFunctionInfo.h.

Referenced by llvm::GCNScheduleDAGMILive::schedule().

◆ getNumPreloadedSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumPreloadedSGPRs ( ) const
inline

◆ getNumSpilledSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledSGPRs ( ) const
inline

◆ getNumSpilledVGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumSpilledVGPRs ( ) const
inline

◆ getNumUserSGPRs()

unsigned llvm::SIMachineFunctionInfo::getNumUserSGPRs ( ) const
inline

Definition at line 706 of file SIMachineFunctionInfo.h.

Referenced by getCalleeFunction().

◆ getOccupancy()

unsigned llvm::SIMachineFunctionInfo::getOccupancy ( ) const
inline

◆ getPreloadedReg()

Register llvm::SIMachineFunctionInfo::getPreloadedReg ( AMDGPUFunctionArgInfo::PreloadedValue  Value) const
inline

◆ getPreloadedValue()

std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT> llvm::SIMachineFunctionInfo::getPreloadedValue ( AMDGPUFunctionArgInfo::PreloadedValue  Value) const
inline

◆ getPrivateSegmentWaveByteOffsetSystemSGPR()

Register llvm::SIMachineFunctionInfo::getPrivateSegmentWaveByteOffsetSystemSGPR ( ) const
inline

◆ getPSInputAddr()

unsigned llvm::SIMachineFunctionInfo::getPSInputAddr ( ) const
inline

◆ getPSInputEnable()

unsigned llvm::SIMachineFunctionInfo::getPSInputEnable ( ) const
inline

◆ getQueuePtrUserSGPR()

Register llvm::SIMachineFunctionInfo::getQueuePtrUserSGPR ( ) const
inline

◆ getScratchRSrcReg()

Register llvm::SIMachineFunctionInfo::getScratchRSrcReg ( ) const
inline

◆ getSGPRSpillVGPRs()

ArrayRef<SGPRSpillVGPRCSR> llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs ( ) const
inline

◆ getSGPRToVGPRSpills()

ArrayRef<SpilledReg> llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills ( int  FrameIndex) const
inline

◆ getStackPtrOffsetReg()

Register llvm::SIMachineFunctionInfo::getStackPtrOffsetReg ( ) const
inline

◆ getTIDReg()

Register llvm::SIMachineFunctionInfo::getTIDReg ( ) const
inline

◆ getVGPRSpillAGPRs()

ArrayRef<MCPhysReg> llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs ( ) const
inline

◆ getVGPRToAGPRSpill()

MCPhysReg llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill ( int  FrameIndex,
unsigned  Lane 
) const
inline

◆ getWavesPerEU()

std::pair<unsigned, unsigned> llvm::SIMachineFunctionInfo::getWavesPerEU ( ) const
inline
Returns
A pair of default/requested minimum/maximum number of waves per execution unit.

Definition at line 853 of file SIMachineFunctionInfo.h.

Referenced by llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::GCNSubtarget::getMaxNumVGPRs().

◆ getWorkGroupIDSGPR()

Register llvm::SIMachineFunctionInfo::getWorkGroupIDSGPR ( unsigned  Dim) const
inline

◆ hasCalculatedTID()

bool llvm::SIMachineFunctionInfo::hasCalculatedTID ( ) const
inline

◆ hasDispatchID()

bool llvm::SIMachineFunctionInfo::hasDispatchID ( ) const
inline

◆ hasDispatchPtr()

bool llvm::SIMachineFunctionInfo::hasDispatchPtr ( ) const
inline

◆ hasFlatScratchInit()

bool llvm::SIMachineFunctionInfo::hasFlatScratchInit ( ) const
inline

◆ hasImplicitArgPtr()

bool llvm::SIMachineFunctionInfo::hasImplicitArgPtr ( ) const
inline

◆ hasImplicitBufferPtr()

bool llvm::SIMachineFunctionInfo::hasImplicitBufferPtr ( ) const
inline

◆ hasKernargSegmentPtr()

bool llvm::SIMachineFunctionInfo::hasKernargSegmentPtr ( ) const
inline

◆ hasNonSpillStackObjects()

bool llvm::SIMachineFunctionInfo::hasNonSpillStackObjects ( ) const
inline

Definition at line 775 of file SIMachineFunctionInfo.h.

◆ hasPrivateSegmentBuffer()

bool llvm::SIMachineFunctionInfo::hasPrivateSegmentBuffer ( ) const
inline

◆ hasPrivateSegmentWaveByteOffset()

bool llvm::SIMachineFunctionInfo::hasPrivateSegmentWaveByteOffset ( ) const
inline

◆ hasQueuePtr()

bool llvm::SIMachineFunctionInfo::hasQueuePtr ( ) const
inline

◆ hasSpilledSGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledSGPRs ( ) const
inline

Definition at line 759 of file SIMachineFunctionInfo.h.

Referenced by lowerShiftReservedVGPR().

◆ hasSpilledVGPRs()

bool llvm::SIMachineFunctionInfo::hasSpilledVGPRs ( ) const
inline

Definition at line 767 of file SIMachineFunctionInfo.h.

Referenced by lowerShiftReservedVGPR().

◆ hasWorkGroupIDX()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDX ( ) const
inline

◆ hasWorkGroupIDY()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDY ( ) const
inline

◆ hasWorkGroupIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkGroupIDZ ( ) const
inline

◆ hasWorkGroupInfo()

bool llvm::SIMachineFunctionInfo::hasWorkGroupInfo ( ) const
inline

◆ hasWorkItemIDX()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDX ( ) const
inline

◆ hasWorkItemIDY()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDY ( ) const
inline

◆ hasWorkItemIDZ()

bool llvm::SIMachineFunctionInfo::hasWorkItemIDZ ( ) const
inline

◆ haveFreeLanesForSGPRSpill()

bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill ( const MachineFunction MF,
unsigned  NumNeed 
) const

returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.

Definition at line 266 of file SIMachineFunctionInfo.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::AMDGPUSubtarget::getWavefrontSize(), and llvm::ARM_MB::ST.

Referenced by getVGPRSpillLaneOrTempRegister().

◆ increaseOccupancy()

void llvm::SIMachineFunctionInfo::increaseOccupancy ( const MachineFunction MF,
unsigned  Limit 
)
inline

◆ initializeBaseYamlFields()

bool SIMachineFunctionInfo::initializeBaseYamlFields ( const yaml::SIMachineFunctionInfo YamlMFI)

◆ isCalleeSavedReg()

bool SIMachineFunctionInfo::isCalleeSavedReg ( const MCPhysReg CSRegs,
MCPhysReg  Reg 
)

Definition at line 252 of file SIMachineFunctionInfo.cpp.

References I.

Referenced by allocateSGPRSpillToVGPR(), and lowerShiftReservedVGPR().

◆ isPSInputAllocated()

bool llvm::SIMachineFunctionInfo::isPSInputAllocated ( unsigned  Index) const
inline

◆ isStackRealigned()

bool llvm::SIMachineFunctionInfo::isStackRealigned ( ) const
inline

◆ limitOccupancy() [1/2]

void SIMachineFunctionInfo::limitOccupancy ( const MachineFunction MF)

◆ limitOccupancy() [2/2]

void llvm::SIMachineFunctionInfo::limitOccupancy ( unsigned  Limit)
inline

Definition at line 926 of file SIMachineFunctionInfo.h.

◆ markPSInputAllocated()

void llvm::SIMachineFunctionInfo::markPSInputAllocated ( unsigned  Index)
inline

◆ markPSInputEnabled()

void llvm::SIMachineFunctionInfo::markPSInputEnabled ( unsigned  Index)
inline

◆ removeDeadFrameIndices()

void SIMachineFunctionInfo::removeDeadFrameIndices ( MachineFrameInfo MFI)

◆ removeVGPRForSGPRSpill()

bool SIMachineFunctionInfo::removeVGPRForSGPRSpill ( Register  ReservedVGPR,
MachineFunction MF 
)

◆ reserveVGPRforSGPRSpills()

bool SIMachineFunctionInfo::reserveVGPRforSGPRSpills ( MachineFunction MF)

◆ ReserveWWMRegister()

void llvm::SIMachineFunctionInfo::ReserveWWMRegister ( Register  Reg)
inline

◆ returnsVoid()

bool llvm::SIMachineFunctionInfo::returnsVoid ( ) const
inline

◆ setBytesInStackArgArea()

void llvm::SIMachineFunctionInfo::setBytesInStackArgArea ( unsigned  Bytes)
inline

Definition at line 548 of file SIMachineFunctionInfo.h.

References TRI.

Referenced by llvm::SITargetLowering::LowerFormalArguments().

◆ setFrameOffsetReg()

void llvm::SIMachineFunctionInfo::setFrameOffsetReg ( Register  Reg)
inline

Definition at line 733 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

Referenced by reservePrivateMemoryRegs().

◆ setHasNonSpillStackObjects()

void llvm::SIMachineFunctionInfo::setHasNonSpillStackObjects ( bool  StackObject = true)
inline

Definition at line 779 of file SIMachineFunctionInfo.h.

Referenced by reservePrivateMemoryRegs().

◆ setHasSpilledSGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledSGPRs ( bool  Spill = true)
inline

◆ setHasSpilledVGPRs()

void llvm::SIMachineFunctionInfo::setHasSpilledVGPRs ( bool  Spill = true)
inline

Definition at line 771 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ setIfReturnsVoid()

void llvm::SIMachineFunctionInfo::setIfReturnsVoid ( bool  Value)
inline

◆ setIsStackRealigned()

void llvm::SIMachineFunctionInfo::setIsStackRealigned ( bool  Realigned = true)
inline

Definition at line 787 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::emitPrologue().

◆ setPrivateSegmentWaveByteOffset()

void llvm::SIMachineFunctionInfo::setPrivateSegmentWaveByteOffset ( Register  Reg)
inline

◆ setScratchRSrcReg()

void llvm::SIMachineFunctionInfo::setScratchRSrcReg ( Register  Reg)
inline

Definition at line 724 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

Referenced by buildEpilogReload(), and reservePrivateMemoryRegs().

◆ setSGPRSpillVGPRs()

void llvm::SIMachineFunctionInfo::setSGPRSpillVGPRs ( Register  NewVGPR,
Optional< int >  newFI,
int  Index 
)
inline

Definition at line 511 of file SIMachineFunctionInfo.h.

Referenced by lowerShiftReservedVGPR().

◆ setStackPtrOffsetReg()

void llvm::SIMachineFunctionInfo::setStackPtrOffsetReg ( Register  Reg)
inline

Definition at line 738 of file SIMachineFunctionInfo.h.

References assert(), and Reg.

Referenced by reservePrivateMemoryRegs().

◆ setTIDReg()

void llvm::SIMachineFunctionInfo::setTIDReg ( Register  Reg)
inline

Definition at line 542 of file SIMachineFunctionInfo.h.

References Reg.

◆ setWorkItemIDX()

void llvm::SIMachineFunctionInfo::setWorkItemIDX ( ArgDescriptor  Arg)
inline

◆ setWorkItemIDY()

void llvm::SIMachineFunctionInfo::setWorkItemIDY ( ArgDescriptor  Arg)
inline

◆ setWorkItemIDZ()

void llvm::SIMachineFunctionInfo::setWorkItemIDZ ( ArgDescriptor  Arg)
inline

Friends And Related Function Documentation

◆ GCNTargetMachine

friend class GCNTargetMachine
friend

Definition at line 329 of file SIMachineFunctionInfo.h.

Member Data Documentation

◆ BasePointerSaveIndex

Optional<int> llvm::SIMachineFunctionInfo::BasePointerSaveIndex

◆ FramePointerSaveIndex

Optional<int> llvm::SIMachineFunctionInfo::FramePointerSaveIndex

◆ SGPRForBPSaveRestoreCopy

Register llvm::SIMachineFunctionInfo::SGPRForBPSaveRestoreCopy

If this is set, an SGPR used for save/restore of the register used for the base pointer.

Definition at line 490 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), buildScratchExecCopy(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ SGPRForFPSaveRestoreCopy

Register llvm::SIMachineFunctionInfo::SGPRForFPSaveRestoreCopy

If this is set, an SGPR used for save/restore of the register used for the frame pointer.

Definition at line 485 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots(), buildScratchExecCopy(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ VGPRReservedForSGPRSpill

Register llvm::SIMachineFunctionInfo::VGPRReservedForSGPRSpill

◆ WWMReservedRegs

SparseBitVector llvm::SIMachineFunctionInfo::WWMReservedRegs

Definition at line 463 of file SIMachineFunctionInfo.h.

Referenced by llvm::SIRegisterInfo::getReservedRegs().


The documentation for this class was generated from the following files: