LLVM  9.0.0svn
AMDGPUCallLowering.cpp
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1 //===-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp - Call lowering -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUCallLowering.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIISelLowering.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 struct OutgoingArgHandler : public CallLowering::ValueHandler {
34  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
35  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
36  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
37 
39 
40  unsigned getStackAddress(uint64_t Size, int64_t Offset,
41  MachinePointerInfo &MPO) override {
42  llvm_unreachable("not implemented");
43  }
44 
45  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
46  MachinePointerInfo &MPO, CCValAssign &VA) override {
47  llvm_unreachable("not implemented");
48  }
49 
50  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
51  CCValAssign &VA) override {
52  MIB.addUse(PhysReg);
53  MIRBuilder.buildCopy(PhysReg, ValVReg);
54  }
55 
56  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
57  CCValAssign::LocInfo LocInfo,
59  CCState &State) override {
60  return AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
61  }
62 };
63 
64 }
65 
67  : CallLowering(&TLI) {
68 }
69 
71  const Value *Val,
72  ArrayRef<unsigned> VRegs) const {
73 
74  MachineFunction &MF = MIRBuilder.getMF();
77  MFI->setIfReturnsVoid(!Val);
78 
79  if (!Val) {
80  MIRBuilder.buildInstr(AMDGPU::S_ENDPGM).addImm(0);
81  return true;
82  }
83 
84  unsigned VReg = VRegs[0];
85 
86  const Function &F = MF.getFunction();
87  auto &DL = F.getParent()->getDataLayout();
89  return false;
90 
91 
92  const AMDGPUTargetLowering &TLI = *getTLI<AMDGPUTargetLowering>();
93  SmallVector<EVT, 4> SplitVTs;
95  ArgInfo OrigArg{VReg, Val->getType()};
96  setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
97  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
98 
99  SmallVector<ArgInfo, 8> SplitArgs;
100  CCAssignFn *AssignFn = CCAssignFnForReturn(F.getCallingConv(), false);
101  for (unsigned i = 0, e = Offsets.size(); i != e; ++i) {
102  Type *SplitTy = SplitVTs[i].getTypeForEVT(F.getContext());
103  SplitArgs.push_back({VRegs[i], SplitTy, OrigArg.Flags, OrigArg.IsFixed});
104  }
105  auto RetInstr = MIRBuilder.buildInstrNoInsert(AMDGPU::SI_RETURN_TO_EPILOG);
106  OutgoingArgHandler Handler(MIRBuilder, MRI, RetInstr, AssignFn);
107  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
108  return false;
109  MIRBuilder.insertInstr(RetInstr);
110 
111  return true;
112 }
113 
114 unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
115  Type *ParamTy,
116  uint64_t Offset) const {
117 
118  MachineFunction &MF = MIRBuilder.getMF();
121  const Function &F = MF.getFunction();
122  const DataLayout &DL = F.getParent()->getDataLayout();
124  LLT PtrType = getLLTForType(*PtrTy, DL);
125  unsigned DstReg = MRI.createGenericVirtualRegister(PtrType);
126  unsigned KernArgSegmentPtr =
128  unsigned KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
129 
130  unsigned OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
131  MIRBuilder.buildConstant(OffsetReg, Offset);
132 
133  MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
134 
135  return DstReg;
136 }
137 
138 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
139  Type *ParamTy, uint64_t Offset,
140  unsigned Align,
141  unsigned DstReg) const {
142  MachineFunction &MF = MIRBuilder.getMF();
143  const Function &F = MF.getFunction();
144  const DataLayout &DL = F.getParent()->getDataLayout();
146  MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
147  unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
148  unsigned PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);
149 
150  MachineMemOperand *MMO =
154  TypeSize, Align);
155 
156  MIRBuilder.buildLoad(DstReg, PtrReg, *MMO);
157 }
158 
159 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
160  unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
161  for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
162  if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
163  return AMDGPU::SGPR0 + Reg;
164  }
165  }
166  llvm_unreachable("Cannot allocate sgpr");
167 }
168 
169 static void allocateSystemSGPRs(CCState &CCInfo,
170  MachineFunction &MF,
172  CallingConv::ID CallConv,
173  bool IsShader) {
174  if (Info.hasPrivateSegmentWaveByteOffset()) {
175  // Scratch wave offset passed in system SGPR.
176  unsigned PrivateSegmentWaveByteOffsetReg;
177 
178  if (IsShader) {
179  PrivateSegmentWaveByteOffsetReg =
181 
182  // This is true if the scratch wave byte offset doesn't have a fixed
183  // location.
184  if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
185  PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
186  Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
187  }
188  } else
189  PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
190 
191  MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
192  CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
193  }
194 }
195 
197  const Function &F,
198  ArrayRef<unsigned> VRegs) const {
199  // AMDGPU_GS and AMDGP_HS are not supported yet.
202  return false;
203 
204  MachineFunction &MF = MIRBuilder.getMF();
205  const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
208  const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
209  const DataLayout &DL = F.getParent()->getDataLayout();
210 
211  bool IsShader = AMDGPU::isShader(F.getCallingConv());
212 
214  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
215 
216  // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
217  if (Info->hasPrivateSegmentBuffer()) {
218  unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
219  MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
220  CCInfo.AllocateReg(PrivateSegmentBufferReg);
221  }
222 
223  if (Info->hasDispatchPtr()) {
224  unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
225  // FIXME: Need to add reg as live-in
226  CCInfo.AllocateReg(DispatchPtrReg);
227  }
228 
229  if (Info->hasQueuePtr()) {
230  unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
231  // FIXME: Need to add reg as live-in
232  CCInfo.AllocateReg(QueuePtrReg);
233  }
234 
235  if (Info->hasKernargSegmentPtr()) {
236  unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
238  unsigned VReg = MRI.createGenericVirtualRegister(P2);
239  MRI.addLiveIn(InputPtrReg, VReg);
240  MIRBuilder.getMBB().addLiveIn(InputPtrReg);
241  MIRBuilder.buildCopy(VReg, InputPtrReg);
242  CCInfo.AllocateReg(InputPtrReg);
243  }
244 
245  if (Info->hasDispatchID()) {
246  unsigned DispatchIDReg = Info->addDispatchID(*TRI);
247  // FIXME: Need to add reg as live-in
248  CCInfo.AllocateReg(DispatchIDReg);
249  }
250 
251  if (Info->hasFlatScratchInit()) {
252  unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);
253  // FIXME: Need to add reg as live-in
254  CCInfo.AllocateReg(FlatScratchInitReg);
255  }
256 
257  // The infrastructure for normal calling convention lowering is essentially
258  // useless for kernels. We want to avoid any kind of legalization or argument
259  // splitting.
261  unsigned i = 0;
262  const unsigned KernArgBaseAlign = 16;
263  const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
264  uint64_t ExplicitArgOffset = 0;
265 
266  // TODO: Align down to dword alignment and extract bits for extending loads.
267  for (auto &Arg : F.args()) {
268  Type *ArgTy = Arg.getType();
269  unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
270  if (AllocSize == 0)
271  continue;
272 
273  unsigned ABIAlign = DL.getABITypeAlignment(ArgTy);
274 
275  uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
276  ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
277 
278  unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
279  ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
280  lowerParameter(MIRBuilder, ArgTy, ArgOffset, Align, VRegs[i]);
281  ++i;
282  }
283 
284  allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), IsShader);
285  return true;
286  }
287 
288  unsigned NumArgs = F.arg_size();
289  Function::const_arg_iterator CurOrigArg = F.arg_begin();
290  const AMDGPUTargetLowering &TLI = *getTLI<AMDGPUTargetLowering>();
291  unsigned PSInputNum = 0;
292  BitVector Skipped(NumArgs);
293  for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) {
294  EVT ValEVT = TLI.getValueType(DL, CurOrigArg->getType());
295 
296  // We can only hanlde simple value types at the moment.
297  ISD::ArgFlagsTy Flags;
298  ArgInfo OrigArg{VRegs[i], CurOrigArg->getType()};
299  setArgFlags(OrigArg, i + 1, DL, F);
300  Flags.setOrigAlign(DL.getABITypeAlignment(CurOrigArg->getType()));
301 
303  !OrigArg.Flags.isInReg() && !OrigArg.Flags.isByVal() &&
304  PSInputNum <= 15) {
305  if (CurOrigArg->use_empty() && !Info->isPSInputAllocated(PSInputNum)) {
306  Skipped.set(i);
307  ++PSInputNum;
308  continue;
309  }
310 
311  Info->markPSInputAllocated(PSInputNum);
312  if (!CurOrigArg->use_empty())
313  Info->markPSInputEnabled(PSInputNum);
314 
315  ++PSInputNum;
316  }
317 
319  /*IsVarArg=*/false);
320 
321  if (ValEVT.isVector()) {
322  EVT ElemVT = ValEVT.getVectorElementType();
323  if (!ValEVT.isSimple())
324  return false;
325  MVT ValVT = ElemVT.getSimpleVT();
326  bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full,
327  OrigArg.Flags, CCInfo);
328  if (!Res)
329  return false;
330  } else {
331  MVT ValVT = ValEVT.getSimpleVT();
332  if (!ValEVT.isSimple())
333  return false;
334  bool Res =
335  AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo);
336 
337  // Fail if we don't know how to handle this type.
338  if (Res)
339  return false;
340  }
341  }
342 
344 
347  for (unsigned i = 0, OrigArgIdx = 0;
348  OrigArgIdx != NumArgs && i != ArgLocs.size(); ++Arg, ++OrigArgIdx) {
349  if (Skipped.test(OrigArgIdx))
350  continue;
351  CCValAssign &VA = ArgLocs[i++];
352  MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]);
353  MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
354  MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg());
355  }
356 
357  allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), IsShader);
358  return true;
359  }
360 
361  return false;
362 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
BitVector & set()
Definition: BitVector.h:397
Interface definition for SIRegisterInfo.
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
AMDGPU specific subclass of TargetSubtarget.
bool isPSInputAllocated(unsigned Index) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isAllocated(unsigned Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
static void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader)
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
This file describes how to lower LLVM calls to machine code calls.
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI)
unsigned Reg
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space...
Definition: Type.cpp:629
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
bool test(unsigned Idx) const
Definition: BitVector.h:501
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1042
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
unsigned const TargetRegisterInfo * TRI
F(f)
void markPSInputEnabled(unsigned Index)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
void setPrivateSegmentWaveByteOffset(unsigned Reg)
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
unsigned addDispatchID(const SIRegisterInfo &TRI)
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
void setOrigAlign(unsigned A)
void markPSInputAllocated(unsigned Index)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:498
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
Helper class to build MachineInstr.
SI DAG Lowering interface definition.
unsigned addQueuePtr(const SIRegisterInfo &TRI)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
size_t arg_size() const
Definition: Function.h:714
arg_iterator arg_begin()
Definition: Function.h:687
The memory access is non-temporal.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
static UndefValue * get(Type *T)
Static factory methods - Return an &#39;undef&#39; object of the specified type.
Definition: Constants.cpp:1424
size_t size() const
Definition: SmallVector.h:52
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:64
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Address space for constant memory (VTX2).
Definition: AMDGPU.h:257
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
unsigned addDispatchPtr(const SIRegisterInfo &TRI)
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
Definition: CallingConv.h:188
CCState - This class holds information needed while lowering arguments and return values...
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
Interface definition of the TargetLowering class that is common to all AMD GPUs.
unsigned getExplicitKernelArgOffset(const Function &F) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:749
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const
bool isShader(CallingConv::ID cc)
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:200
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
unsigned addFlatScratchInit(const SIRegisterInfo &TRI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:469
Provides AMDGPU specific target descriptions.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
The memory access always returns the same value (or traps).
uint32_t Size
Definition: Profile.cpp:46
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
static unsigned findFirstFreeSGPR(CCState &CCInfo)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:444
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
unsigned getLocReg() const
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
bool use_empty() const
Definition: Value.h:322
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
iterator_range< arg_iterator > args()
Definition: Function.h:705