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AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDGPU.h"
14 #include "AMDKernelCodeT.h"
15 #include "SIDefines.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/IR/CallingConv.h"
18 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/Compiler.h"
23 #include <cstdint>
24 #include <string>
25 #include <utility>
26 
27 namespace llvm {
28 
29 class Argument;
30 class AMDGPUSubtarget;
31 class FeatureBitset;
32 class Function;
33 class GCNSubtarget;
34 class GlobalValue;
35 class MCContext;
36 class MCRegisterClass;
37 class MCRegisterInfo;
38 class MCSection;
39 class MCSubtargetInfo;
40 class MachineMemOperand;
41 class Triple;
42 
43 namespace AMDGPU {
44 
45 #define GET_MIMGBaseOpcode_DECL
46 #define GET_MIMGDim_DECL
47 #define GET_MIMGEncoding_DECL
48 #define GET_MIMGLZMapping_DECL
49 #include "AMDGPUGenSearchableTables.inc"
50 
51 namespace IsaInfo {
52 
53 enum {
54  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
55  // doesn't spill SGPRs as much as when 80 is set.
58 };
59 
60 /// Streams isa version string for given subtarget \p STI into \p Stream.
61 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
62 
63 /// \returns True if given subtarget \p STI supports code object version 3,
64 /// false otherwise.
65 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
66 
67 /// \returns Wavefront size for given subtarget \p STI.
68 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
69 
70 /// \returns Local memory size in bytes for given subtarget \p STI.
71 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
72 
73 /// \returns Number of execution units per compute unit for given subtarget \p
74 /// STI.
75 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
76 
77 /// \returns Maximum number of work groups per compute unit for given subtarget
78 /// \p STI and limited by given \p FlatWorkGroupSize.
79 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
80  unsigned FlatWorkGroupSize);
81 
82 /// \returns Maximum number of waves per compute unit for given subtarget \p
83 /// STI without any kind of limitation.
84 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI);
85 
86 /// \returns Maximum number of waves per compute unit for given subtarget \p
87 /// STI and limited by given \p FlatWorkGroupSize.
88 unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
89  unsigned FlatWorkGroupSize);
90 
91 /// \returns Minimum number of waves per execution unit for given subtarget \p
92 /// STI.
93 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
94 
95 /// \returns Maximum number of waves per execution unit for given subtarget \p
96 /// STI without any kind of limitation.
97 unsigned getMaxWavesPerEU();
98 
99 /// \returns Maximum number of waves per execution unit for given subtarget \p
100 /// STI and limited by given \p FlatWorkGroupSize.
101 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
102  unsigned FlatWorkGroupSize);
103 
104 /// \returns Minimum flat work group size for given subtarget \p STI.
105 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
106 
107 /// \returns Maximum flat work group size for given subtarget \p STI.
108 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
109 
110 /// \returns Number of waves per work group for given subtarget \p STI and
111 /// limited by given \p FlatWorkGroupSize.
112 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
113  unsigned FlatWorkGroupSize);
114 
115 /// \returns SGPR allocation granularity for given subtarget \p STI.
116 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
117 
118 /// \returns SGPR encoding granularity for given subtarget \p STI.
119 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
120 
121 /// \returns Total number of SGPRs for given subtarget \p STI.
122 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
123 
124 /// \returns Addressable number of SGPRs for given subtarget \p STI.
125 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
126 
127 /// \returns Minimum number of SGPRs that meets the given number of waves per
128 /// execution unit requirement for given subtarget \p STI.
129 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
130 
131 /// \returns Maximum number of SGPRs that meets the given number of waves per
132 /// execution unit requirement for given subtarget \p STI.
133 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
134  bool Addressable);
135 
136 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
137 /// STI when the given special registers are used.
138 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
139  bool FlatScrUsed, bool XNACKUsed);
140 
141 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
142 /// STI when the given special registers are used. XNACK is inferred from
143 /// \p STI.
144 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
145  bool FlatScrUsed);
146 
147 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
148 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
149 /// register counts.
150 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
151 
152 /// \returns VGPR allocation granularity for given subtarget \p STI.
153 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI);
154 
155 /// \returns VGPR encoding granularity for given subtarget \p STI.
156 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI);
157 
158 /// \returns Total number of VGPRs for given subtarget \p STI.
159 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
160 
161 /// \returns Addressable number of VGPRs for given subtarget \p STI.
162 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
163 
164 /// \returns Minimum number of VGPRs that meets given number of waves per
165 /// execution unit requirement for given subtarget \p STI.
166 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
167 
168 /// \returns Maximum number of VGPRs that meets given number of waves per
169 /// execution unit requirement for given subtarget \p STI.
170 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
171 
172 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
173 /// \p NumVGPRs are used.
174 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
175 
176 } // end namespace IsaInfo
177 
179 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
180 
182  MIMGBaseOpcode BaseOpcode;
183  bool Store;
184  bool Atomic;
185  bool AtomicX2;
186  bool Sampler;
187 
188  uint8_t NumExtraArgs;
189  bool Gradients;
192  bool HasD16;
193 };
194 
196 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
197 
198 struct MIMGDimInfo {
199  MIMGDim Dim;
200  uint8_t NumCoords;
201  uint8_t NumGradients;
202  bool DA;
203 };
204 
206 const MIMGDimInfo *getMIMGDimInfo(unsigned Dim);
207 
209  MIMGBaseOpcode L;
210  MIMGBaseOpcode LZ;
211 };
212 
214 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
215 
217 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
218  unsigned VDataDwords, unsigned VAddrDwords);
219 
221 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
222 
224 int getMUBUFBaseOpcode(unsigned Opc);
225 
227 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords);
228 
230 int getMUBUFDwords(unsigned Opc);
231 
233 bool getMUBUFHasVAddr(unsigned Opc);
234 
236 bool getMUBUFHasSrsrc(unsigned Opc);
237 
239 bool getMUBUFHasSoffset(unsigned Opc);
240 
242 int getMCOpcode(uint16_t Opcode, unsigned Gen);
243 
245  const MCSubtargetInfo *STI);
246 
248 
249 bool isGroupSegment(const GlobalValue *GV);
250 bool isGlobalSegment(const GlobalValue *GV);
251 bool isReadOnlySegment(const GlobalValue *GV);
252 
253 /// \returns True if constants should be emitted to .text section for given
254 /// target triple \p TT, false otherwise.
256 
257 /// \returns Integer value requested using \p F's \p Name attribute.
258 ///
259 /// \returns \p Default if attribute is not present.
260 ///
261 /// \returns \p Default and emits error if requested value cannot be converted
262 /// to integer.
263 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
264 
265 /// \returns A pair of integer values requested using \p F's \p Name attribute
266 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
267 /// is false).
268 ///
269 /// \returns \p Default if attribute is not present.
270 ///
271 /// \returns \p Default and emits error if one of the requested values cannot be
272 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
273 /// not present.
274 std::pair<int, int> getIntegerPairAttribute(const Function &F,
275  StringRef Name,
276  std::pair<int, int> Default,
277  bool OnlyFirstRequired = false);
278 
279 /// Represents the counter values to wait for in an s_waitcnt instruction.
280 ///
281 /// Large values (including the maximum possible integer) can be used to
282 /// represent "don't care" waits.
283 struct Waitcnt {
284  unsigned VmCnt = ~0u;
285  unsigned ExpCnt = ~0u;
286  unsigned LgkmCnt = ~0u;
287 
288  Waitcnt() {}
289  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt)
290  : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt) {}
291 
292  static Waitcnt allZero() { return Waitcnt(0, 0, 0); }
293 
294  bool dominates(const Waitcnt &Other) const {
295  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
296  LgkmCnt <= Other.LgkmCnt;
297  }
298 
299  Waitcnt combined(const Waitcnt &Other) const {
300  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
301  std::min(LgkmCnt, Other.LgkmCnt));
302  }
303 };
304 
305 /// \returns Vmcnt bit mask for given isa \p Version.
306 unsigned getVmcntBitMask(const IsaVersion &Version);
307 
308 /// \returns Expcnt bit mask for given isa \p Version.
309 unsigned getExpcntBitMask(const IsaVersion &Version);
310 
311 /// \returns Lgkmcnt bit mask for given isa \p Version.
312 unsigned getLgkmcntBitMask(const IsaVersion &Version);
313 
314 /// \returns Waitcnt bit mask for given isa \p Version.
315 unsigned getWaitcntBitMask(const IsaVersion &Version);
316 
317 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
318 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
319 
320 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
321 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
322 
323 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
324 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
325 
326 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
327 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
328 /// \p Lgkmcnt respectively.
329 ///
330 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
331 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
332 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
333 /// \p Expcnt = \p Waitcnt[6:4]
334 /// \p Lgkmcnt = \p Waitcnt[11:8]
335 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
336  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
337 
338 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
339 
340 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
341 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
342  unsigned Vmcnt);
343 
344 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
345 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
346  unsigned Expcnt);
347 
348 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
349 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
350  unsigned Lgkmcnt);
351 
352 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
353 /// \p Version.
354 ///
355 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
356 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
357 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
358 /// Waitcnt[6:4] = \p Expcnt
359 /// Waitcnt[11:8] = \p Lgkmcnt
360 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
361 ///
362 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
363 /// isa \p Version.
364 unsigned encodeWaitcnt(const IsaVersion &Version,
365  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
366 
367 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
368 
369 unsigned getInitialPSInputAddr(const Function &F);
370 
372 bool isShader(CallingConv::ID CC);
373 
375 bool isCompute(CallingConv::ID CC);
376 
379 
380 // FIXME: Remove this when calling conventions cleaned up
382 inline bool isKernel(CallingConv::ID CC) {
383  switch (CC) {
386  return true;
387  default:
388  return false;
389  }
390 }
391 
392 bool hasXNACK(const MCSubtargetInfo &STI);
393 bool hasSRAMECC(const MCSubtargetInfo &STI);
394 bool hasMIMG_R128(const MCSubtargetInfo &STI);
395 bool hasPackedD16(const MCSubtargetInfo &STI);
396 
397 bool isSI(const MCSubtargetInfo &STI);
398 bool isCI(const MCSubtargetInfo &STI);
399 bool isVI(const MCSubtargetInfo &STI);
400 bool isGFX9(const MCSubtargetInfo &STI);
401 
402 /// Is Reg - scalar register
403 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
404 
405 /// Is there any intersection between registers
406 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
407 
408 /// If \p Reg is a pseudo reg, return the correct hardware register given
409 /// \p STI otherwise return \p Reg.
410 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
411 
412 /// Convert hardware register \p Reg to a pseudo register
414 unsigned mc2PseudoReg(unsigned Reg);
415 
416 /// Can this operand also contain immediate values?
417 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
418 
419 /// Is this floating-point operand?
420 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
421 
422 /// Does this opearnd support only inlinable literals?
423 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
424 
425 /// Get the size in bits of a register from the register class \p RC.
426 unsigned getRegBitWidth(unsigned RCID);
427 
428 /// Get the size in bits of a register from the register class \p RC.
429 unsigned getRegBitWidth(const MCRegisterClass &RC);
430 
431 /// Get size of register operand
432 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
433  unsigned OpNo);
434 
436 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
437  switch (OpInfo.OperandType) {
442  return 4;
443 
448  return 8;
449 
456  return 2;
457 
458  default:
459  llvm_unreachable("unhandled operand type");
460  }
461 }
462 
464 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
465  return getOperandSize(Desc.OpInfo[OpNo]);
466 }
467 
468 /// Is this literal inlinable
470 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
471 
473 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
474 
476 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
477 
479 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
480 
481 bool isArgPassedInSGPR(const Argument *Arg);
482 
483 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
484 /// offset field.
485 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
486 
487 /// \returns true if this offset is small enough to fit in the SMRD
488 /// offset field. \p ByteOffset should be the offset in bytes and
489 /// not the encoded offset.
490 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
491 
492 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
493  const GCNSubtarget *Subtarget, uint32_t Align = 4);
494 
495 /// \returns true if the intrinsic is divergent
496 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
497 
498 } // end namespace AMDGPU
499 } // end namespace llvm
500 
501 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords)
static Waitcnt allZero()
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasPackedD16(const MCSubtargetInfo &STI)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
bool getMUBUFHasSrsrc(unsigned Opc)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getExpcntBitMask(const IsaVersion &Version)
Represents the counter values to wait for in an s_waitcnt instruction.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Instruction set architecture version.
Definition: TargetParser.h:132
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned Dim)
unsigned const TargetRegisterInfo * TRI
F(f)
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
int getMUBUFDwords(unsigned Opc)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor()
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
#define LLVM_READNONE
Definition: Compiler.h:177
amdgpu Simplify well known AMD library false Value Value const Twine & Name
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:137
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:79
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, uint32_t Align)
bool isGroupSegment(const GlobalValue *GV)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
bool isReadOnlySegment(const GlobalValue *GV)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt)
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool hasSRAMECC(const MCSubtargetInfo &STI)
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCompute(CallingConv::ID cc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned const MachineRegisterInfo * MRI
bool getMUBUFHasSoffset(unsigned Opc)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
int getMUBUFBaseOpcode(unsigned Opc)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Operands with register or inline constant.
Definition: SIDefines.h:124
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
AMDHSA kernel descriptor definitions.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isArgPassedInSGPR(const Argument *A)
bool dominates(const Waitcnt &Other) const
bool isShader(CallingConv::ID cc)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool isCI(const MCSubtargetInfo &STI)
amdgpu Simplify well known AMD library false Value Value * Arg
unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isGFX9(const MCSubtargetInfo &STI)
bool isVI(const MCSubtargetInfo &STI)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
bool hasXNACK(const MCSubtargetInfo &STI)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
#define LLVM_READONLY
Definition: Compiler.h:184
Generic base class for all target subtargets.
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool shouldEmitConstantsToTextSection(const Triple &TT)
Operands with register or 32-bit immediate.
Definition: SIDefines.h:116
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
#define AMDGPUSubtarget
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFHasVAddr(unsigned Opc)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Waitcnt combined(const Waitcnt &Other) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:67
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
const uint64_t Version
Definition: InstrProf.h:895
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:201
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
unsigned getVmcntBitMask(const IsaVersion &Version)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...