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AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDGPU.h"
14 #include "AMDKernelCodeT.h"
15 #include "SIDefines.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/IR/CallingConv.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/Support/Compiler.h"
21 #include <cstdint>
22 #include <string>
23 #include <utility>
24 
25 namespace llvm {
26 
27 class Argument;
28 class FeatureBitset;
29 class Function;
30 class GlobalValue;
31 class MachineMemOperand;
32 class MCContext;
33 class MCRegisterClass;
34 class MCRegisterInfo;
35 class MCSection;
36 class MCSubtargetInfo;
37 class Triple;
38 
39 namespace AMDGPU {
40 namespace IsaInfo {
41 
42 enum {
43  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
44  // doesn't spill SGPRs as much as when 80 is set.
46 };
47 
48 /// \brief Instruction set architecture version.
49 struct IsaVersion {
50  unsigned Major;
51  unsigned Minor;
52  unsigned Stepping;
53 };
54 
55 /// \returns Isa version for given subtarget \p Features.
57 
58 /// \brief Streams isa version string for given subtarget \p STI into \p Stream.
59 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
60 
61 /// \returns True if given subtarget \p Features support code object version 3,
62 /// false otherwise.
64 
65 /// \returns Wavefront size for given subtarget \p Features.
66 unsigned getWavefrontSize(const FeatureBitset &Features);
67 
68 /// \returns Local memory size in bytes for given subtarget \p Features.
70 
71 /// \returns Number of execution units per compute unit for given subtarget \p
72 /// Features.
73 unsigned getEUsPerCU(const FeatureBitset &Features);
74 
75 /// \returns Maximum number of work groups per compute unit for given subtarget
76 /// \p Features and limited by given \p FlatWorkGroupSize.
78  unsigned FlatWorkGroupSize);
79 
80 /// \returns Maximum number of waves per compute unit for given subtarget \p
81 /// Features without any kind of limitation.
82 unsigned getMaxWavesPerCU(const FeatureBitset &Features);
83 
84 /// \returns Maximum number of waves per compute unit for given subtarget \p
85 /// Features and limited by given \p FlatWorkGroupSize.
87  unsigned FlatWorkGroupSize);
88 
89 /// \returns Minimum number of waves per execution unit for given subtarget \p
90 /// Features.
91 unsigned getMinWavesPerEU(const FeatureBitset &Features);
92 
93 /// \returns Maximum number of waves per execution unit for given subtarget \p
94 /// Features without any kind of limitation.
95 unsigned getMaxWavesPerEU(const FeatureBitset &Features);
96 
97 /// \returns Maximum number of waves per execution unit for given subtarget \p
98 /// Features and limited by given \p FlatWorkGroupSize.
100  unsigned FlatWorkGroupSize);
101 
102 /// \returns Minimum flat work group size for given subtarget \p Features.
104 
105 /// \returns Maximum flat work group size for given subtarget \p Features.
107 
108 /// \returns Number of waves per work group for given subtarget \p Features and
109 /// limited by given \p FlatWorkGroupSize.
111  unsigned FlatWorkGroupSize);
112 
113 /// \returns SGPR allocation granularity for given subtarget \p Features.
115 
116 /// \returns SGPR encoding granularity for given subtarget \p Features.
118 
119 /// \returns Total number of SGPRs for given subtarget \p Features.
120 unsigned getTotalNumSGPRs(const FeatureBitset &Features);
121 
122 /// \returns Addressable number of SGPRs for given subtarget \p Features.
124 
125 /// \returns Minimum number of SGPRs that meets the given number of waves per
126 /// execution unit requirement for given subtarget \p Features.
127 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
128 
129 /// \returns Maximum number of SGPRs that meets the given number of waves per
130 /// execution unit requirement for given subtarget \p Features.
131 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
132  bool Addressable);
133 
134 /// \returns VGPR allocation granularity for given subtarget \p Features.
136 
137 /// \returns VGPR encoding granularity for given subtarget \p Features.
139 
140 /// \returns Total number of VGPRs for given subtarget \p Features.
141 unsigned getTotalNumVGPRs(const FeatureBitset &Features);
142 
143 /// \returns Addressable number of VGPRs for given subtarget \p Features.
145 
146 /// \returns Minimum number of VGPRs that meets given number of waves per
147 /// execution unit requirement for given subtarget \p Features.
148 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
149 
150 /// \returns Maximum number of VGPRs that meets given number of waves per
151 /// execution unit requirement for given subtarget \p Features.
152 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
153 
154 } // end namespace IsaInfo
155 
157 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
158 
160 int getMaskedMIMGOp(const MCInstrInfo &MII,
161  unsigned Opc, unsigned NewChannels);
162 
164 int getMaskedMIMGAtomicOp(const MCInstrInfo &MII,
165  unsigned Opc, unsigned NewChannels);
166 
168 int getMCOpcode(uint16_t Opcode, unsigned Gen);
169 
171  const FeatureBitset &Features);
172 
173 bool isGroupSegment(const GlobalValue *GV);
174 bool isGlobalSegment(const GlobalValue *GV);
175 bool isReadOnlySegment(const GlobalValue *GV);
176 
177 /// \returns True if constants should be emitted to .text section for given
178 /// target triple \p TT, false otherwise.
180 
181 /// \returns Integer value requested using \p F's \p Name attribute.
182 ///
183 /// \returns \p Default if attribute is not present.
184 ///
185 /// \returns \p Default and emits error if requested value cannot be converted
186 /// to integer.
187 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
188 
189 /// \returns A pair of integer values requested using \p F's \p Name attribute
190 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
191 /// is false).
192 ///
193 /// \returns \p Default if attribute is not present.
194 ///
195 /// \returns \p Default and emits error if one of the requested values cannot be
196 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
197 /// not present.
198 std::pair<int, int> getIntegerPairAttribute(const Function &F,
199  StringRef Name,
200  std::pair<int, int> Default,
201  bool OnlyFirstRequired = false);
202 
203 /// \returns Vmcnt bit mask for given isa \p Version.
205 
206 /// \returns Expcnt bit mask for given isa \p Version.
208 
209 /// \returns Lgkmcnt bit mask for given isa \p Version.
211 
212 /// \returns Waitcnt bit mask for given isa \p Version.
214 
215 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
216 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
217 
218 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
219 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
220 
221 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
222 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
223 
224 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
225 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
226 /// \p Lgkmcnt respectively.
227 ///
228 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
229 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
230 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
231 /// \p Expcnt = \p Waitcnt[6:4]
232 /// \p Lgkmcnt = \p Waitcnt[11:8]
233 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
234  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
235 
236 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
237 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
238  unsigned Vmcnt);
239 
240 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
241 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
242  unsigned Expcnt);
243 
244 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
245 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
246  unsigned Lgkmcnt);
247 
248 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
249 /// \p Version.
250 ///
251 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
252 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
253 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
254 /// Waitcnt[6:4] = \p Expcnt
255 /// Waitcnt[11:8] = \p Lgkmcnt
256 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
257 ///
258 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
259 /// isa \p Version.
261  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
262 
263 unsigned getInitialPSInputAddr(const Function &F);
264 
266 bool isShader(CallingConv::ID CC);
267 
269 bool isCompute(CallingConv::ID CC);
270 
273 
274 // FIXME: Remove this when calling conventions cleaned up
276 inline bool isKernel(CallingConv::ID CC) {
277  switch (CC) {
280  return true;
281  default:
282  return false;
283  }
284 }
285 
286 bool hasXNACK(const MCSubtargetInfo &STI);
287 bool hasMIMG_R128(const MCSubtargetInfo &STI);
288 bool hasPackedD16(const MCSubtargetInfo &STI);
289 
290 bool isSI(const MCSubtargetInfo &STI);
291 bool isCI(const MCSubtargetInfo &STI);
292 bool isVI(const MCSubtargetInfo &STI);
293 bool isGFX9(const MCSubtargetInfo &STI);
294 
295 /// \brief Is Reg - scalar register
296 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
297 
298 /// \brief Is there any intersection between registers
299 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
300 
301 /// If \p Reg is a pseudo reg, return the correct hardware register given
302 /// \p STI otherwise return \p Reg.
303 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
304 
305 /// \brief Convert hardware register \p Reg to a pseudo register
307 unsigned mc2PseudoReg(unsigned Reg);
308 
309 /// \brief Can this operand also contain immediate values?
310 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
311 
312 /// \brief Is this floating-point operand?
313 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
314 
315 /// \brief Does this opearnd support only inlinable literals?
316 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
317 
318 /// \brief Get the size in bits of a register from the register class \p RC.
319 unsigned getRegBitWidth(unsigned RCID);
320 
321 /// \brief Get the size in bits of a register from the register class \p RC.
322 unsigned getRegBitWidth(const MCRegisterClass &RC);
323 
324 /// \brief Get size of register operand
325 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
326  unsigned OpNo);
327 
329 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
330  switch (OpInfo.OperandType) {
335  return 4;
336 
341  return 8;
342 
349  return 2;
350 
351  default:
352  llvm_unreachable("unhandled operand type");
353  }
354 }
355 
357 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
358  return getOperandSize(Desc.OpInfo[OpNo]);
359 }
360 
361 /// \brief Is this literal inlinable
363 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
364 
366 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
367 
369 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
370 
372 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
373 
374 bool isArgPassedInSGPR(const Argument *Arg);
375 
376 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
377 /// offset field.
378 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
379 
380 /// \returns true if this offset is small enough to fit in the SMRD
381 /// offset field. \p ByteOffset should be the offset in bytes and
382 /// not the encoded offset.
383 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
384 
385 } // end namespace AMDGPU
386 } // end namespace llvm
387 
388 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getAddressableNumVGPRs(const FeatureBitset &Features)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features, unsigned FlatWorkGroupSize)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
F(f)
unsigned getTotalNumVGPRs(const FeatureBitset &Features)
unsigned getMinWavesPerEU(const FeatureBitset &Features)
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:137
unsigned getWavesPerWorkGroup(const FeatureBitset &Features, unsigned FlatWorkGroupSize)
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
unsigned getVGPREncodingGranule(const FeatureBitset &Features)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getEUsPerCU(const FeatureBitset &Features)
unsigned getWavefrontSize(const FeatureBitset &Features)
unsigned getVGPRAllocGranule(const FeatureBitset &Features)
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features)
bool hasCodeObjectV3(const FeatureBitset &Features)
unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
unsigned getMaxWavesPerCU(const FeatureBitset &Features)
unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU, bool Addressable)
unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
bool isGroupSegment(const GlobalValue *GV)
unsigned getMaxWavesPerEU(const FeatureBitset &Features)
bool isReadOnlySegment(const GlobalValue *GV)
unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features)
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isCompute(CallingConv::ID cc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
unsigned getTotalNumSGPRs(const FeatureBitset &Features)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
Instruction set architecture version.
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Operands with register or inline constant.
Definition: SIDefines.h:121
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version)
bool isArgPassedInSGPR(const Argument *A)
unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
int getMaskedMIMGAtomicOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
bool isShader(CallingConv::ID cc)
bool isCI(const MCSubtargetInfo &STI)
amdgpu Simplify well known AMD library false Value Value * Arg
unsigned getInitialPSInputAddr(const Function &F)
bool isGFX9(const MCSubtargetInfo &STI)
bool isVI(const MCSubtargetInfo &STI)
unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt)
bool hasXNACK(const MCSubtargetInfo &STI)
unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
#define LLVM_READNONE
Definition: Compiler.h:161
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
MCSubtargetInfo - Generic base class for all target subtargets.
bool shouldEmitConstantsToTextSection(const Triple &TT)
unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version)
#define LLVM_READONLY
Definition: Compiler.h:168
unsigned getAddressableNumSGPRs(const FeatureBitset &Features)
Operands with register or 32-bit immediate.
Definition: SIDefines.h:113
unsigned getSGPREncodingGranule(const FeatureBitset &Features)
int getMaskedMIMGOp(const MCInstrInfo &MII, unsigned Opc, unsigned NewChannels)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const FeatureBitset Features
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
unsigned getSGPRAllocGranule(const FeatureBitset &Features)
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:201
unsigned getLocalMemorySize(const FeatureBitset &Features)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU)
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
const uint64_t Version
Definition: InstrProf.h:867
IsaVersion getIsaVersion(const FeatureBitset &Features)
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.