LLVM 19.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
17#include <array>
18#include <functional>
19#include <utility>
20
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45/// Generic target versions emitted by this version of LLVM.
46///
47/// These numbers are incremented every time a codegen breaking change occurs
48/// within a generic family.
49namespace GenericVersion {
50static constexpr unsigned GFX9 = 1;
51static constexpr unsigned GFX10_1 = 1;
52static constexpr unsigned GFX10_3 = 1;
53static constexpr unsigned GFX11 = 1;
54} // namespace GenericVersion
55
56enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
57
58/// \returns True if \p STI is AMDHSA.
59bool isHsaAbi(const MCSubtargetInfo &STI);
60
61/// \returns Code object version from the IR module flag.
62unsigned getAMDHSACodeObjectVersion(const Module &M);
63
64/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].
65unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);
66
67/// \returns The default HSA code object version. This should only be used when
68/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
69/// flag or a .amdhsa_code_object_version directive)
71
72/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param
73/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
74uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
75
76/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
77unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
78
79/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
80unsigned getHostcallImplicitArgPosition(unsigned COV);
81
82unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
83unsigned getCompletionActionImplicitArgPosition(unsigned COV);
84
86 unsigned Format;
87 unsigned BitsPerComp;
88 unsigned NumComponents;
89 unsigned NumFormat;
90 unsigned DataFormat;
91};
92
97};
98
99#define GET_MIMGBaseOpcode_DECL
100#define GET_MIMGDim_DECL
101#define GET_MIMGEncoding_DECL
102#define GET_MIMGLZMapping_DECL
103#define GET_MIMGMIPMapping_DECL
104#define GET_MIMGBiASMapping_DECL
105#define GET_MAIInstInfoTable_DECL
106#include "AMDGPUGenSearchableTables.inc"
107
108namespace IsaInfo {
109
110enum {
111 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
112 // doesn't spill SGPRs as much as when 80 is set.
114 TRAP_NUM_SGPRS = 16
116
117enum class TargetIDSetting {
119 Any,
120 Off,
121 On
122};
123
125private:
126 const MCSubtargetInfo &STI;
127 TargetIDSetting XnackSetting;
128 TargetIDSetting SramEccSetting;
129
130public:
131 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
132 ~AMDGPUTargetID() = default;
133
134 /// \return True if the current xnack setting is not "Unsupported".
135 bool isXnackSupported() const {
136 return XnackSetting != TargetIDSetting::Unsupported;
137 }
138
139 /// \returns True if the current xnack setting is "On" or "Any".
140 bool isXnackOnOrAny() const {
141 return XnackSetting == TargetIDSetting::On ||
142 XnackSetting == TargetIDSetting::Any;
143 }
144
145 /// \returns True if current xnack setting is "On" or "Off",
146 /// false otherwise.
147 bool isXnackOnOrOff() const {
150 }
151
152 /// \returns The current xnack TargetIDSetting, possible options are
153 /// "Unsupported", "Any", "Off", and "On".
155 return XnackSetting;
156 }
157
158 /// Sets xnack setting to \p NewXnackSetting.
159 void setXnackSetting(TargetIDSetting NewXnackSetting) {
160 XnackSetting = NewXnackSetting;
161 }
162
163 /// \return True if the current sramecc setting is not "Unsupported".
164 bool isSramEccSupported() const {
165 return SramEccSetting != TargetIDSetting::Unsupported;
166 }
167
168 /// \returns True if the current sramecc setting is "On" or "Any".
169 bool isSramEccOnOrAny() const {
170 return SramEccSetting == TargetIDSetting::On ||
171 SramEccSetting == TargetIDSetting::Any;
172 }
173
174 /// \returns True if current sramecc setting is "On" or "Off",
175 /// false otherwise.
176 bool isSramEccOnOrOff() const {
179 }
180
181 /// \returns The current sramecc TargetIDSetting, possible options are
182 /// "Unsupported", "Any", "Off", and "On".
184 return SramEccSetting;
185 }
186
187 /// Sets sramecc setting to \p NewSramEccSetting.
188 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
189 SramEccSetting = NewSramEccSetting;
190 }
191
194
195 /// \returns String representation of an object.
196 std::string toString() const;
197};
198
199/// \returns Wavefront size for given subtarget \p STI.
200unsigned getWavefrontSize(const MCSubtargetInfo *STI);
201
202/// \returns Local memory size in bytes for given subtarget \p STI.
203unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
204
205/// \returns Maximum addressable local memory size in bytes for given subtarget
206/// \p STI.
208
209/// \returns Number of execution units per compute unit for given subtarget \p
210/// STI.
211unsigned getEUsPerCU(const MCSubtargetInfo *STI);
212
213/// \returns Maximum number of work groups per compute unit for given subtarget
214/// \p STI and limited by given \p FlatWorkGroupSize.
215unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
216 unsigned FlatWorkGroupSize);
217
218/// \returns Minimum number of waves per execution unit for given subtarget \p
219/// STI.
220unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
221
222/// \returns Maximum number of waves per execution unit for given subtarget \p
223/// STI without any kind of limitation.
224unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
225
226/// \returns Number of waves per execution unit required to support the given \p
227/// FlatWorkGroupSize.
229 unsigned FlatWorkGroupSize);
230
231/// \returns Minimum flat work group size for given subtarget \p STI.
232unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
233
234/// \returns Maximum flat work group size for given subtarget \p STI.
235unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
236
237/// \returns Number of waves per work group for given subtarget \p STI and
238/// \p FlatWorkGroupSize.
239unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
240 unsigned FlatWorkGroupSize);
241
242/// \returns SGPR allocation granularity for given subtarget \p STI.
243unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
244
245/// \returns SGPR encoding granularity for given subtarget \p STI.
246unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
247
248/// \returns Total number of SGPRs for given subtarget \p STI.
249unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
250
251/// \returns Addressable number of SGPRs for given subtarget \p STI.
252unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
253
254/// \returns Minimum number of SGPRs that meets the given number of waves per
255/// execution unit requirement for given subtarget \p STI.
256unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
257
258/// \returns Maximum number of SGPRs that meets the given number of waves per
259/// execution unit requirement for given subtarget \p STI.
260unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
261 bool Addressable);
262
263/// \returns Number of extra SGPRs implicitly required by given subtarget \p
264/// STI when the given special registers are used.
265unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
266 bool FlatScrUsed, bool XNACKUsed);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used. XNACK is inferred from
270/// \p STI.
271unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
272 bool FlatScrUsed);
273
274/// \returns Number of SGPR blocks needed for given subtarget \p STI when
275/// \p NumSGPRs are used. \p NumSGPRs should already include any special
276/// register counts.
277unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
278
279/// \returns VGPR allocation granularity for given subtarget \p STI.
280///
281/// For subtargets which support it, \p EnableWavefrontSize32 should match
282/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
283unsigned
285 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
286
287/// \returns VGPR encoding granularity for given subtarget \p STI.
288///
289/// For subtargets which support it, \p EnableWavefrontSize32 should match
290/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
292 const MCSubtargetInfo *STI,
293 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
294
295/// \returns Total number of VGPRs for given subtarget \p STI.
296unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
297
298/// \returns Addressable number of architectural VGPRs for a given subtarget \p
299/// STI.
301
302/// \returns Addressable number of VGPRs for given subtarget \p STI.
303unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
304
305/// \returns Minimum number of VGPRs that meets given number of waves per
306/// execution unit requirement for given subtarget \p STI.
307unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
308
309/// \returns Maximum number of VGPRs that meets given number of waves per
310/// execution unit requirement for given subtarget \p STI.
311unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
312
313/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
314/// subtarget \p STI.
316 unsigned NumVGPRs);
317
318/// \returns Number of VGPR blocks needed for given subtarget \p STI when
319/// \p NumVGPRs are used. We actually return the number of blocks -1, since
320/// that's what we encode.
321///
322/// For subtargets which support it, \p EnableWavefrontSize32 should match the
323/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
325 const MCSubtargetInfo *STI, unsigned NumVGPRs,
326 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
327
328/// \returns Number of VGPR blocks that need to be allocated for the given
329/// subtarget \p STI when \p NumVGPRs are used.
331 const MCSubtargetInfo *STI, unsigned NumVGPRs,
332 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
333
334} // end namespace IsaInfo
335
336// Represents a field in an encoded value.
337template <unsigned HighBit, unsigned LowBit, unsigned D = 0>
339 static_assert(HighBit >= LowBit, "Invalid bit range!");
340 static constexpr unsigned Offset = LowBit;
341 static constexpr unsigned Width = HighBit - LowBit + 1;
342
344 static constexpr ValueType Default = D;
345
348
349 constexpr uint64_t encode() const { return Value; }
350 static ValueType decode(uint64_t Encoded) { return Encoded; }
351};
352
353// A helper for encoding and decoding multiple fields.
354template <typename... Fields> struct EncodingFields {
355 static constexpr uint64_t encode(Fields... Values) {
356 return ((Values.encode() << Values.Offset) | ...);
357 }
358
359 static std::tuple<typename Fields::ValueType...> decode(uint64_t Encoded) {
360 return {Fields::decode((Encoded >> Fields::Offset) &
361 maxUIntN(Fields::Width))...};
362 }
363};
364
366int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
367
369inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
370 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
371}
372
375
377 MIMGBaseOpcode BaseOpcode;
378 bool Store;
379 bool Atomic;
383
386 bool G16;
389 bool HasD16;
390 bool MSAA;
391 bool BVH;
392 bool A16;
393};
394
396const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
397
399const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
400
402 MIMGDim Dim;
403 uint8_t NumCoords;
405 bool MSAA;
406 bool DA;
407 uint8_t Encoding;
408 const char *AsmSuffix;
409};
410
412const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
413
416
419
421 MIMGBaseOpcode L;
422 MIMGBaseOpcode LZ;
423};
424
426 MIMGBaseOpcode MIP;
427 MIMGBaseOpcode NONMIP;
428};
429
431 MIMGBaseOpcode Bias;
432 MIMGBaseOpcode NoBias;
433};
434
436 MIMGBaseOpcode Offset;
437 MIMGBaseOpcode NoOffset;
438};
439
441 MIMGBaseOpcode G;
442 MIMGBaseOpcode G16;
443};
444
447
449 unsigned Opcode2Addr;
450 unsigned Opcode3Addr;
451};
452
455
458
461
464
466int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
467 unsigned VDataDwords, unsigned VAddrDwords);
468
470int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
471
473unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
474 const MIMGDimInfo *Dim, bool IsA16,
475 bool IsG16Supported);
476
477struct MIMGInfo {
481 uint8_t VDataDwords;
482 uint8_t VAddrDwords;
484};
485
487const MIMGInfo *getMIMGInfo(unsigned Opc);
488
490int getMTBUFBaseOpcode(unsigned Opc);
491
493int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
494
496int getMTBUFElements(unsigned Opc);
497
499bool getMTBUFHasVAddr(unsigned Opc);
500
502bool getMTBUFHasSrsrc(unsigned Opc);
503
505bool getMTBUFHasSoffset(unsigned Opc);
506
508int getMUBUFBaseOpcode(unsigned Opc);
509
511int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
512
514int getMUBUFElements(unsigned Opc);
515
517bool getMUBUFHasVAddr(unsigned Opc);
518
520bool getMUBUFHasSrsrc(unsigned Opc);
521
523bool getMUBUFHasSoffset(unsigned Opc);
524
526bool getMUBUFIsBufferInv(unsigned Opc);
527
529bool getSMEMIsBuffer(unsigned Opc);
530
532bool getVOP1IsSingle(unsigned Opc);
533
535bool getVOP2IsSingle(unsigned Opc);
536
538bool getVOP3IsSingle(unsigned Opc);
539
541bool isVOPC64DPP(unsigned Opc);
542
544bool isVOPCAsmOnly(unsigned Opc);
545
546/// Returns true if MAI operation is a double precision GEMM.
548bool getMAIIsDGEMM(unsigned Opc);
549
551bool getMAIIsGFX940XDL(unsigned Opc);
552
553struct CanBeVOPD {
554 bool X;
555 bool Y;
556};
557
558/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
560unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
561
563CanBeVOPD getCanBeVOPD(unsigned Opc);
564
566const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
567 uint8_t NumComponents,
568 uint8_t NumFormat,
569 const MCSubtargetInfo &STI);
572 const MCSubtargetInfo &STI);
573
575int getMCOpcode(uint16_t Opcode, unsigned Gen);
576
578unsigned getVOPDOpcode(unsigned Opc);
579
581int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily);
582
584bool isVOPD(unsigned Opc);
585
587bool isMAC(unsigned Opc);
588
590bool isPermlane16(unsigned Opc);
591
593bool isGenericAtomic(unsigned Opc);
594
596bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);
597
598namespace VOPD {
599
600enum Component : unsigned {
601 DST = 0,
605
610
611// LSB mask for VGPR banks per VOPD component operand.
612// 4 banks result in a mask 3, setting 2 lower bits.
613constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
614
615enum ComponentIndex : unsigned { X = 0, Y = 1 };
617constexpr unsigned COMPONENTS_NUM = 2;
618
619// Properties of VOPD components.
621private:
622 unsigned SrcOperandsNum = 0;
623 unsigned MandatoryLiteralIdx = ~0u;
624 bool HasSrc2Acc = false;
625
626public:
627 ComponentProps() = default;
628 ComponentProps(const MCInstrDesc &OpDesc);
629
630 // Return the total number of src operands this component has.
631 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
632
633 // Return the number of src operands of this component visible to the parser.
635 return SrcOperandsNum - HasSrc2Acc;
636 }
637
638 // Return true iif this component has a mandatory literal.
639 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
640
641 // If this component has a mandatory literal, return component operand
642 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
645 return MandatoryLiteralIdx;
646 }
647
648 // Return true iif this component has operand
649 // with component index CompSrcIdx and this operand may be a register.
650 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
651 assert(CompSrcIdx < Component::MAX_SRC_NUM);
652 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
653 }
654
655 // Return true iif this component has tied src2.
656 bool hasSrc2Acc() const { return HasSrc2Acc; }
657
658private:
659 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
660 assert(CompSrcIdx < Component::MAX_SRC_NUM);
661 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
662 }
663};
664
665enum ComponentKind : unsigned {
666 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
667 COMPONENT_X, // A VOPD instruction, X component.
668 COMPONENT_Y, // A VOPD instruction, Y component.
671
672// Interface functions of this class map VOPD component operand indices
673// to indices of operands in MachineInstr/MCInst or parsed operands array.
674//
675// Note that this class operates with 3 kinds of indices:
676// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
677// - MC operand indices (they refer operands in a MachineInstr/MCInst);
678// - parsed operand indices (they refer operands in parsed operands array).
679//
680// For SINGLE components mapping between these indices is trivial.
681// But things get more complicated for COMPONENT_X and
682// COMPONENT_Y because these components share the same
683// MachineInstr/MCInst and the same parsed operands array.
684// Below is an example of component operand to parsed operand
685// mapping for the following instruction:
686//
687// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
688//
689// PARSED COMPONENT PARSED
690// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
691// -------------------------------------------------------------------
692// "v_dual_add_f32" 0
693// v_dual_add_f32 v255 0 (DST) --> 1
694// v4 1 (SRC0) --> 2
695// v5 2 (SRC1) --> 3
696// "::" 4
697// "v_dual_mov_b32" 5
698// v_dual_mov_b32 v6 0 (DST) --> 6
699// v1 1 (SRC0) --> 7
700// -------------------------------------------------------------------
701//
703private:
704 // Regular MachineInstr/MCInst operands are ordered as follows:
705 // dst, src0 [, other src operands]
706 // VOPD MachineInstr/MCInst operands are ordered as follows:
707 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
708 // Each ComponentKind has operand indices defined below.
709 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
710 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
711
712 // Parsed operands of regular instructions are ordered as follows:
713 // Mnemo dst src0 [vsrc1 ...]
714 // Parsed VOPD operands are ordered as follows:
715 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
716 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
717 // Each ComponentKind has operand indices defined below.
718 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
719 4 /* + OpX.ParsedSrcNum */};
720 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
721 2, 2, 5 /* + OpX.ParsedSrcNum */};
722
723private:
724 const ComponentKind Kind;
725 const ComponentProps PrevComp;
726
727public:
728 // Create layout for COMPONENT_X or SINGLE component.
729 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
731 }
732
733 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
735 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
736
737public:
738 // Return the index of dst operand in MCInst operands.
739 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
740
741 // Return the index of the specified src operand in MCInst operands.
742 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
743 assert(CompSrcIdx < Component::MAX_SRC_NUM);
744 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
745 }
746
747 // Return the index of dst operand in the parsed operands array.
749 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
750 }
751
752 // Return the index of the specified src operand in the parsed operands array.
753 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
754 assert(CompSrcIdx < Component::MAX_SRC_NUM);
755 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
756 }
757
758private:
759 unsigned getPrevCompSrcNum() const {
760 return PrevComp.getCompSrcOperandsNum();
761 }
762 unsigned getPrevCompParsedSrcNum() const {
763 return PrevComp.getCompParsedSrcOperandsNum();
764 }
765};
766
767// Layout and properties of VOPD components.
769public:
770 // Create ComponentInfo for COMPONENT_X or SINGLE component.
773 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
774
775 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
776 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
777 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
778
779 // Map component operand index to parsed operand index.
780 // Return 0 if the specified operand does not exist.
781 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
782};
783
784// Properties of VOPD instructions.
785class InstInfo {
786private:
787 const ComponentInfo CompInfo[COMPONENTS_NUM];
788
789public:
790 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
791
792 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
793 : CompInfo{OpX, OpY} {}
794
795 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
796 : CompInfo{OprInfoX, OprInfoY} {}
797
798 const ComponentInfo &operator[](size_t ComponentIdx) const {
799 assert(ComponentIdx < COMPONENTS_NUM);
800 return CompInfo[ComponentIdx];
801 }
802
803 // Check VOPD operands constraints.
804 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
805 // for the specified component and MC operand. The callback must return 0
806 // if the operand is not a register or not a VGPR.
807 // If \p SkipSrc is set to true then constraints for source operands are not
808 // checked.
809 bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
810 bool SkipSrc = false) const {
811 return getInvalidCompOperandIndex(GetRegIdx, SkipSrc).has_value();
812 }
813
814 // Check VOPD operands constraints.
815 // Return the index of an invalid component operand, if any.
816 // If \p SkipSrc is set to true then constraints for source operands are not
817 // checked.
818 std::optional<unsigned> getInvalidCompOperandIndex(
819 std::function<unsigned(unsigned, unsigned)> GetRegIdx,
820 bool SkipSrc = false) const;
821
822private:
824 getRegIndices(unsigned ComponentIdx,
825 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
826};
827
828} // namespace VOPD
829
831std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
832
834// Get properties of 2 single VOP1/VOP2 instructions
835// used as components to create a VOPD instruction.
836VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
837
839// Get properties of VOPD X and Y components.
840VOPD::InstInfo
841getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
842
844bool isTrue16Inst(unsigned Opc);
845
847unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
848
850unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
851
853 const MCSubtargetInfo *STI);
854
856 const MCSubtargetInfo *STI);
857
858bool isGroupSegment(const GlobalValue *GV);
859bool isGlobalSegment(const GlobalValue *GV);
860bool isReadOnlySegment(const GlobalValue *GV);
861
862/// \returns True if constants should be emitted to .text section for given
863/// target triple \p TT, false otherwise.
865
866/// \returns Integer value requested using \p F's \p Name attribute.
867///
868/// \returns \p Default if attribute is not present.
869///
870/// \returns \p Default and emits error if requested value cannot be converted
871/// to integer.
873
874/// \returns A pair of integer values requested using \p F's \p Name attribute
875/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
876/// is false).
877///
878/// \returns \p Default if attribute is not present.
879///
880/// \returns \p Default and emits error if one of the requested values cannot be
881/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
882/// not present.
883std::pair<unsigned, unsigned>
885 std::pair<unsigned, unsigned> Default,
886 bool OnlyFirstRequired = false);
887
888/// \returns Generate a vector of integer values requested using \p F's \p Name
889/// attribute.
890///
891/// \returns true if exactly Size (>2) number of integers are found in the
892/// attribute.
893///
894/// \returns false if any error occurs.
896 unsigned Size);
897
898/// Represents the counter values to wait for in an s_waitcnt instruction.
899///
900/// Large values (including the maximum possible integer) can be used to
901/// represent "don't care" waits.
902struct Waitcnt {
903 unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12.
904 unsigned ExpCnt = ~0u;
905 unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12.
906 unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11.
907 unsigned SampleCnt = ~0u; // gfx12+ only.
908 unsigned BvhCnt = ~0u; // gfx12+ only.
909 unsigned KmCnt = ~0u; // gfx12+ only.
910
911 Waitcnt() = default;
912 // Pre-gfx12 constructor.
913 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
914 : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt),
915 SampleCnt(~0u), BvhCnt(~0u), KmCnt(~0u) {}
916
917 // gfx12+ constructor.
918 Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt,
919 unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
922
923 bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); }
924
926 return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u ||
927 SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u;
928 }
929
930 bool hasWaitStoreCnt() const { return StoreCnt != ~0u; }
931
933 // Does the right thing provided self and Other are either both pre-gfx12
934 // or both gfx12+.
935 return Waitcnt(
936 std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt),
937 std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt),
938 std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),
939 std::min(KmCnt, Other.KmCnt));
940 }
941};
942
943// The following methods are only meaningful on targets that support
944// S_WAITCNT.
945
946/// \returns Vmcnt bit mask for given isa \p Version.
947unsigned getVmcntBitMask(const IsaVersion &Version);
948
949/// \returns Expcnt bit mask for given isa \p Version.
950unsigned getExpcntBitMask(const IsaVersion &Version);
951
952/// \returns Lgkmcnt bit mask for given isa \p Version.
953unsigned getLgkmcntBitMask(const IsaVersion &Version);
954
955/// \returns Waitcnt bit mask for given isa \p Version.
956unsigned getWaitcntBitMask(const IsaVersion &Version);
957
958/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
959unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
960
961/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
962unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
963
964/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
965unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
966
967/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
968/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
969/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction
970/// which needs it is deprecated
971///
972/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
973/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
974/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
975/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)
976/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
977/// \p Expcnt = \p Waitcnt[2:0] (gfx11)
978/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
979/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
980/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)
981///
982void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
983 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
984
985Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
986
987/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
988unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
989 unsigned Vmcnt);
990
991/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
992unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
993 unsigned Expcnt);
994
995/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
996unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
997 unsigned Lgkmcnt);
998
999/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
1000/// \p Version. Should not be used on gfx12+, the instruction which needs
1001/// it is deprecated
1002///
1003/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
1004/// Waitcnt[2:0] = \p Expcnt (gfx11+)
1005/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
1006/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
1007/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
1008/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)
1009/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
1010/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
1011/// Waitcnt[15:10] = \p Vmcnt (gfx11)
1012/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
1013///
1014/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
1015/// isa \p Version.
1016///
1017unsigned encodeWaitcnt(const IsaVersion &Version,
1018 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
1019
1020unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
1021
1022// The following methods are only meaningful on targets that support
1023// S_WAIT_*CNT, introduced with gfx12.
1024
1025/// \returns Loadcnt bit mask for given isa \p Version.
1026/// Returns 0 for versions that do not support LOADcnt
1027unsigned getLoadcntBitMask(const IsaVersion &Version);
1028
1029/// \returns Samplecnt bit mask for given isa \p Version.
1030/// Returns 0 for versions that do not support SAMPLEcnt
1031unsigned getSamplecntBitMask(const IsaVersion &Version);
1032
1033/// \returns Bvhcnt bit mask for given isa \p Version.
1034/// Returns 0 for versions that do not support BVHcnt
1035unsigned getBvhcntBitMask(const IsaVersion &Version);
1036
1037/// \returns Dscnt bit mask for given isa \p Version.
1038/// Returns 0 for versions that do not support DScnt
1039unsigned getDscntBitMask(const IsaVersion &Version);
1040
1041/// \returns Dscnt bit mask for given isa \p Version.
1042/// Returns 0 for versions that do not support KMcnt
1043unsigned getKmcntBitMask(const IsaVersion &Version);
1044
1045/// \return STOREcnt or VScnt bit mask for given isa \p Version.
1046/// returns 0 for versions that do not support STOREcnt or VScnt.
1047/// STOREcnt and VScnt are the same counter, the name used
1048/// depends on the ISA version.
1049unsigned getStorecntBitMask(const IsaVersion &Version);
1050
1051// The following are only meaningful on targets that support
1052// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT.
1053
1054/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given
1055/// isa \p Version.
1056Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt);
1057
1058/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given
1059/// isa \p Version.
1060Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt);
1061
1062/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an
1063/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa
1064/// \p Version.
1065unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1066
1067/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an
1068/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa
1069/// \p Version.
1070unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1071
1072namespace Hwreg {
1073
1076
1077struct HwregSize : EncodingField<15, 11, 32> {
1079 constexpr uint64_t encode() const { return Value - 1; }
1080 static ValueType decode(uint64_t Encoded) { return Encoded + 1; }
1081};
1082
1084
1086int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
1087
1089StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
1090
1091} // namespace Hwreg
1092
1093namespace DepCtr {
1094
1096int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1097 const MCSubtargetInfo &STI);
1098bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1099 const MCSubtargetInfo &STI);
1100bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1101 bool &IsDefault, const MCSubtargetInfo &STI);
1102
1103/// \returns Decoded VaVdst from given immediate \p Encoded.
1104unsigned decodeFieldVaVdst(unsigned Encoded);
1105
1106/// \returns Decoded VmVsrc from given immediate \p Encoded.
1107unsigned decodeFieldVmVsrc(unsigned Encoded);
1108
1109/// \returns Decoded SaSdst from given immediate \p Encoded.
1110unsigned decodeFieldSaSdst(unsigned Encoded);
1111
1112/// \returns \p VmVsrc as an encoded Depctr immediate.
1113unsigned encodeFieldVmVsrc(unsigned VmVsrc);
1114
1115/// \returns \p Encoded combined with encoded \p VmVsrc.
1116unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
1117
1118/// \returns \p VaVdst as an encoded Depctr immediate.
1119unsigned encodeFieldVaVdst(unsigned VaVdst);
1120
1121/// \returns \p Encoded combined with encoded \p VaVdst.
1122unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1123
1124/// \returns \p SaSdst as an encoded Depctr immediate.
1125unsigned encodeFieldSaSdst(unsigned SaSdst);
1126
1127/// \returns \p Encoded combined with encoded \p SaSdst.
1128unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1129
1130} // namespace DepCtr
1131
1132namespace Exp {
1133
1134bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1135
1137unsigned getTgtId(const StringRef Name);
1138
1140bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1141
1142} // namespace Exp
1143
1144namespace MTBUFFormat {
1145
1147int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1148
1149void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1150
1151int64_t getDfmt(const StringRef Name);
1152
1153StringRef getDfmtName(unsigned Id);
1154
1155int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1156
1157StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1158
1159bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1160
1161bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1162
1163int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1164
1165StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1166
1167bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1168
1169int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1170 const MCSubtargetInfo &STI);
1171
1172bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1173
1174unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1175
1176} // namespace MTBUFFormat
1177
1178namespace SendMsg {
1179
1181int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1182
1184int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1185
1187StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1188
1190StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1191
1193bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1194
1196bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1197 bool Strict = true);
1198
1200bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1201 const MCSubtargetInfo &STI, bool Strict = true);
1202
1204bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1205
1207bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1208
1209void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1210 uint16_t &StreamId, const MCSubtargetInfo &STI);
1211
1214 uint64_t OpId,
1216
1217} // namespace SendMsg
1218
1219
1220unsigned getInitialPSInputAddr(const Function &F);
1221
1222bool getHasColorExport(const Function &F);
1223
1224bool getHasDepthExport(const Function &F);
1225
1228
1231
1234
1237
1238// These functions are considered entrypoints into the current module, i.e. they
1239// are allowed to be called from outside the current module. This is different
1240// from isEntryFunctionCC, which is only true for functions that are entered by
1241// the hardware. Module entry points include all entry functions but also
1242// include functions that can be called from other functions inside or outside
1243// the current module. Module entry functions are allowed to allocate LDS.
1246
1249
1250bool isKernelCC(const Function *Func);
1251
1252// FIXME: Remove this when calling conventions cleaned up
1255 switch (CC) {
1258 return true;
1259 default:
1260 return false;
1261 }
1262}
1263
1264bool hasXNACK(const MCSubtargetInfo &STI);
1265bool hasSRAMECC(const MCSubtargetInfo &STI);
1266bool hasMIMG_R128(const MCSubtargetInfo &STI);
1267bool hasA16(const MCSubtargetInfo &STI);
1268bool hasG16(const MCSubtargetInfo &STI);
1269bool hasPackedD16(const MCSubtargetInfo &STI);
1270bool hasGDS(const MCSubtargetInfo &STI);
1271unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);
1272unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1273
1274bool isSI(const MCSubtargetInfo &STI);
1275bool isCI(const MCSubtargetInfo &STI);
1276bool isVI(const MCSubtargetInfo &STI);
1277bool isGFX9(const MCSubtargetInfo &STI);
1278bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1279bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);
1280bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1281bool isGFX8Plus(const MCSubtargetInfo &STI);
1282bool isGFX9Plus(const MCSubtargetInfo &STI);
1283bool isGFX10(const MCSubtargetInfo &STI);
1284bool isGFX10_GFX11(const MCSubtargetInfo &STI);
1285bool isGFX10Plus(const MCSubtargetInfo &STI);
1286bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1287bool isGFX10Before1030(const MCSubtargetInfo &STI);
1288bool isGFX11(const MCSubtargetInfo &STI);
1289bool isGFX11Plus(const MCSubtargetInfo &STI);
1290bool isGFX12(const MCSubtargetInfo &STI);
1291bool isGFX12Plus(const MCSubtargetInfo &STI);
1292bool isNotGFX12Plus(const MCSubtargetInfo &STI);
1293bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1294bool isGCN3Encoding(const MCSubtargetInfo &STI);
1295bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1296bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1297bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1298bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);
1299bool isGFX90A(const MCSubtargetInfo &STI);
1300bool isGFX940(const MCSubtargetInfo &STI);
1302bool hasMAIInsts(const MCSubtargetInfo &STI);
1303bool hasVOPD(const MCSubtargetInfo &STI);
1304bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
1305int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1306unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1307
1308/// Is Reg - scalar register
1309bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1310
1311/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
1312/// The bit indicating isHi is the LSB of the encoding.
1313bool isHi(unsigned Reg, const MCRegisterInfo &MRI);
1314
1315/// If \p Reg is a pseudo reg, return the correct hardware register given
1316/// \p STI otherwise return \p Reg.
1317unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1318
1319/// Convert hardware register \p Reg to a pseudo register
1321unsigned mc2PseudoReg(unsigned Reg);
1322
1324bool isInlineValue(unsigned Reg);
1325
1326/// Is this an AMDGPU specific source operand? These include registers,
1327/// inline constants, literals and mandatory literals (KImm).
1328bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1329
1330/// Is this a KImm operand?
1331bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1332
1333/// Is this floating-point operand?
1334bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1335
1336/// Does this operand support only inlinable literals?
1337bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1338
1339/// Get the size in bits of a register from the register class \p RC.
1340unsigned getRegBitWidth(unsigned RCID);
1341
1342/// Get the size in bits of a register from the register class \p RC.
1343unsigned getRegBitWidth(const MCRegisterClass &RC);
1344
1345/// Get size of register operand
1346unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1347 unsigned OpNo);
1348
1350inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1351 switch (OpInfo.OperandType) {
1364 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1366 return 4;
1367
1373 return 8;
1374
1395 return 2;
1396
1397 default:
1398 llvm_unreachable("unhandled operand type");
1399 }
1400}
1401
1403inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1404 return getOperandSize(Desc.operands()[OpNo]);
1405}
1406
1407/// Is this literal inlinable, and not one of the values intended for floating
1408/// point values.
1410inline bool isInlinableIntLiteral(int64_t Literal) {
1411 return Literal >= -16 && Literal <= 64;
1412}
1413
1414/// Is this literal inlinable
1416bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1417
1419bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1420
1422bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1423
1425bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi);
1426
1428bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1429
1431bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi);
1432
1434std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);
1435
1437std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal);
1438
1440std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);
1441
1443bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);
1444
1447
1450
1453
1455bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
1456
1457bool isArgPassedInSGPR(const Argument *Arg);
1458
1459bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1460
1463 int64_t EncodedOffset);
1464
1467 int64_t EncodedOffset,
1468 bool IsBuffer);
1469
1470/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1471/// offsets.
1473
1474/// \returns The encoding that will be used for \p ByteOffset in the
1475/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1476/// S_LOAD instructions have a signed offset, on other subtargets it is
1477/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1478std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1479 int64_t ByteOffset, bool IsBuffer);
1480
1481/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1482/// instruction. This is only useful on CI.s
1483std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1484 int64_t ByteOffset);
1485
1486/// For pre-GFX12 FLAT instructions the offset must be positive;
1487/// MSB is ignored and forced to zero.
1488///
1489/// \return The number of bits available for the signed offset field in flat
1490/// instructions. Note that some forms of the instruction disallow negative
1491/// offsets.
1492unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1493
1494/// \returns true if this offset is small enough to fit in the SMRD
1495/// offset field. \p ByteOffset should be the offset in bytes and
1496/// not the encoded offset.
1497bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1498
1500inline bool isLegalDPALU_DPPControl(unsigned DC) {
1501 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1502}
1503
1504/// \returns true if an instruction may have a 64-bit VGPR operand.
1505bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1506
1507/// \returns true if an instruction is a DP ALU DPP.
1508bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1509
1510/// \returns true if the intrinsic is divergent
1511bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1512
1513/// \returns true if the intrinsic is uniform
1514bool isIntrinsicAlwaysUniform(unsigned IntrID);
1515
1516/// \returns lds block size in terms of dwords. \p
1517/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which
1518/// must be defined in terms of bytes.
1519unsigned getLdsDwGranularity(const MCSubtargetInfo &ST);
1520
1521} // end namespace AMDGPU
1522
1523raw_ostream &operator<<(raw_ostream &OS,
1525
1526} // end namespace llvm
1527
1528#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_READNONE
Definition: Compiler.h:220
#define LLVM_READONLY
Definition: Compiler.h:227
uint64_t Align
std::string Name
uint64_t Size
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
const ComponentInfo & operator[](size_t ComponentIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1455
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:234
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:211
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:227
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_C_BF16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_C_V2BF16
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:212
@ OPERAND_REG_IMM_BF16
Definition: SIDefines.h:205
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:246
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
@ OPERAND_REG_IMM_V2BF16
Definition: SIDefines.h:210
@ OPERAND_REG_IMM_BF16_DEFERRED
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_BF16
Definition: SIDefines.h:240
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:217
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:238
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:244
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:241
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:239
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:242
@ OPERAND_REG_INLINE_AC_V2BF16
Definition: SIDefines.h:245
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:213
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:218
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:228
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
Definition: SIDefines.h:231
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:209
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:208
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
@ Default
The result values are uniform if and only if all operands are uniform.
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Definition: MathExtras.h:201
AMD Kernel Code Object (amd_kernel_code_t).
static constexpr unsigned Width
constexpr EncodingField(ValueType Value)
static constexpr unsigned Offset
static constexpr ValueType Default
static ValueType decode(uint64_t Encoded)
constexpr uint64_t encode() const
static constexpr uint64_t encode(Fields... Values)
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
constexpr uint64_t encode() const
static ValueType decode(uint64_t Encoded)
Represents the counter values to wait for in an s_waitcnt instruction.
Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt, unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
bool hasWaitExceptStoreCnt() const
bool hasWaitStoreCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const
Description of the encoding of one expression Op.