LLVM  7.0.0svn
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "AArch64CallLowering.h"
17 #include "AArch64ISelLowering.h"
19 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Analysis.h"
37 #include "llvm/IR/Argument.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstdint>
46 #include <iterator>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 namespace {
54 struct IncomingArgHandler : public CallLowering::ValueHandler {
55  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
56  CCAssignFn *AssignFn)
57  : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
58 
59  unsigned getStackAddress(uint64_t Size, int64_t Offset,
60  MachinePointerInfo &MPO) override {
61  auto &MFI = MIRBuilder.getMF().getFrameInfo();
62  int FI = MFI.CreateFixedObject(Size, Offset, true);
63  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
64  unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
65  MIRBuilder.buildFrameIndex(AddrReg, FI);
66  StackUsed = std::max(StackUsed, Size + Offset);
67  return AddrReg;
68  }
69 
70  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
71  CCValAssign &VA) override {
72  markPhysRegUsed(PhysReg);
73  switch (VA.getLocInfo()) {
74  default:
75  MIRBuilder.buildCopy(ValVReg, PhysReg);
76  break;
77  case CCValAssign::LocInfo::SExt:
78  case CCValAssign::LocInfo::ZExt:
79  case CCValAssign::LocInfo::AExt: {
80  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
81  MIRBuilder.buildTrunc(ValVReg, Copy);
82  break;
83  }
84  }
85  }
86 
87  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
88  MachinePointerInfo &MPO, CCValAssign &VA) override {
89  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
91  0);
92  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
93  }
94 
95  /// How the physical register gets marked varies between formal
96  /// parameters (it's a basic-block live-in), and a call instruction
97  /// (it's an implicit-def of the BL).
98  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
99 
100  uint64_t StackUsed;
101 };
102 
103 struct FormalArgHandler : public IncomingArgHandler {
104  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
105  CCAssignFn *AssignFn)
106  : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
107 
108  void markPhysRegUsed(unsigned PhysReg) override {
109  MIRBuilder.getMBB().addLiveIn(PhysReg);
110  }
111 };
112 
113 struct CallReturnHandler : public IncomingArgHandler {
114  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
115  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
116  : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
117 
118  void markPhysRegUsed(unsigned PhysReg) override {
119  MIB.addDef(PhysReg, RegState::Implicit);
120  }
121 
123 };
124 
125 struct OutgoingArgHandler : public CallLowering::ValueHandler {
126  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
127  MachineInstrBuilder MIB, CCAssignFn *AssignFn,
128  CCAssignFn *AssignFnVarArg)
129  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
130  AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
131 
132  unsigned getStackAddress(uint64_t Size, int64_t Offset,
133  MachinePointerInfo &MPO) override {
134  LLT p0 = LLT::pointer(0, 64);
135  LLT s64 = LLT::scalar(64);
136  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
137  MIRBuilder.buildCopy(SPReg, AArch64::SP);
138 
139  unsigned OffsetReg = MRI.createGenericVirtualRegister(s64);
140  MIRBuilder.buildConstant(OffsetReg, Offset);
141 
142  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
143  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
144 
145  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
146  return AddrReg;
147  }
148 
149  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
150  CCValAssign &VA) override {
151  MIB.addUse(PhysReg, RegState::Implicit);
152  unsigned ExtReg = extendRegister(ValVReg, VA);
153  MIRBuilder.buildCopy(PhysReg, ExtReg);
154  }
155 
156  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
157  MachinePointerInfo &MPO, CCValAssign &VA) override {
158  if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
159  Size = VA.getLocVT().getSizeInBits() / 8;
160  ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
161  ->getOperand(0)
162  .getReg();
163  }
164  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
165  MPO, MachineMemOperand::MOStore, Size, 0);
166  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
167  }
168 
169  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
170  CCValAssign::LocInfo LocInfo,
171  const CallLowering::ArgInfo &Info,
172  CCState &State) override {
173  bool Res;
174  if (Info.IsFixed)
175  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
176  else
177  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
178 
179  StackSize = State.getNextStackOffset();
180  return Res;
181  }
182 
184  CCAssignFn *AssignFnVarArg;
185  uint64_t StackSize;
186 };
187 } // namespace
188 
189 void AArch64CallLowering::splitToValueTypes(
190  const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
191  const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv,
192  const SplitArgTy &PerformArgSplit) const {
193  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
194  LLVMContext &Ctx = OrigArg.Ty->getContext();
195 
196  if (OrigArg.Ty->isVoidTy())
197  return;
198 
199  SmallVector<EVT, 4> SplitVTs;
201  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
202 
203  if (SplitVTs.size() == 1) {
204  // No splitting to do, but we want to replace the original type (e.g. [1 x
205  // double] -> double).
206  SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx),
207  OrigArg.Flags, OrigArg.IsFixed);
208  return;
209  }
210 
211  unsigned FirstRegIdx = SplitArgs.size();
212  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
213  OrigArg.Ty, CallConv, false);
214  for (auto SplitVT : SplitVTs) {
215  Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
216  SplitArgs.push_back(
218  SplitTy, OrigArg.Flags, OrigArg.IsFixed});
219  if (NeedsRegBlock)
220  SplitArgs.back().Flags.setInConsecutiveRegs();
221  }
222 
223  SplitArgs.back().Flags.setInConsecutiveRegsLast();
224 
225  for (unsigned i = 0; i < Offsets.size(); ++i)
226  PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8);
227 }
228 
230  const Value *Val, unsigned VReg) const {
231  MachineFunction &MF = MIRBuilder.getMF();
232  const Function &F = MF.getFunction();
233 
234  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
235  assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
236  bool Success = true;
237  if (VReg) {
238  MachineRegisterInfo &MRI = MF.getRegInfo();
239 
240  // We zero-extend i1s to i8.
241  if (MRI.getType(VReg).getSizeInBits() == 1)
242  VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg();
243 
244  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
245  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
246  auto &DL = F.getParent()->getDataLayout();
247 
248  ArgInfo OrigArg{VReg, Val->getType()};
249  setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
250 
251  SmallVector<ArgInfo, 8> SplitArgs;
252  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
253  [&](unsigned Reg, uint64_t Offset) {
254  MIRBuilder.buildExtract(Reg, VReg, Offset);
255  });
256 
257  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
258  Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
259  }
260 
261  MIRBuilder.insertInstr(MIB);
262  return Success;
263 }
264 
266  const Function &F,
267  ArrayRef<unsigned> VRegs) const {
268  MachineFunction &MF = MIRBuilder.getMF();
269  MachineBasicBlock &MBB = MIRBuilder.getMBB();
270  MachineRegisterInfo &MRI = MF.getRegInfo();
271  auto &DL = F.getParent()->getDataLayout();
272 
273  SmallVector<ArgInfo, 8> SplitArgs;
274  unsigned i = 0;
275  for (auto &Arg : F.args()) {
276  if (DL.getTypeStoreSize(Arg.getType()) == 0)
277  continue;
278  ArgInfo OrigArg{VRegs[i], Arg.getType()};
279  setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
280  bool Split = false;
281  LLT Ty = MRI.getType(VRegs[i]);
282  unsigned Dst = VRegs[i];
283 
284  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
285  [&](unsigned Reg, uint64_t Offset) {
286  if (!Split) {
287  Split = true;
288  Dst = MRI.createGenericVirtualRegister(Ty);
289  MIRBuilder.buildUndef(Dst);
290  }
291  unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
292  MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
293  Dst = Tmp;
294  });
295 
296  if (Dst != VRegs[i])
297  MIRBuilder.buildCopy(VRegs[i], Dst);
298  ++i;
299  }
300 
301  if (!MBB.empty())
302  MIRBuilder.setInstr(*MBB.begin());
303 
304  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
305  CCAssignFn *AssignFn =
306  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
307 
308  FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
309  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
310  return false;
311 
312  if (F.isVarArg()) {
314  // FIXME: we need to reimplement saveVarArgsRegisters from
315  // AArch64ISelLowering.
316  return false;
317  }
318 
319  // We currently pass all varargs at 8-byte alignment.
320  uint64_t StackOffset = alignTo(Handler.StackUsed, 8);
321 
322  auto &MFI = MIRBuilder.getMF().getFrameInfo();
324  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
325  }
326 
327  // Move back to the end of the basic block.
328  MIRBuilder.setMBB(MBB);
329 
330  return true;
331 }
332 
334  CallingConv::ID CallConv,
335  const MachineOperand &Callee,
336  const ArgInfo &OrigRet,
337  ArrayRef<ArgInfo> OrigArgs) const {
338  MachineFunction &MF = MIRBuilder.getMF();
339  const Function &F = MF.getFunction();
340  MachineRegisterInfo &MRI = MF.getRegInfo();
341  auto &DL = F.getParent()->getDataLayout();
342 
343  SmallVector<ArgInfo, 8> SplitArgs;
344  for (auto &OrigArg : OrigArgs) {
345  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
346  [&](unsigned Reg, uint64_t Offset) {
347  MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset);
348  });
349  }
350 
351  // Find out which ABI gets to decide where things go.
352  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
353  CCAssignFn *AssignFnFixed =
354  TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
355  CCAssignFn *AssignFnVarArg =
356  TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/true);
357 
358  auto CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
359 
360  // Create a temporarily-floating call instruction so we can add the implicit
361  // uses of arg registers.
362  auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR
363  : AArch64::BL);
364  MIB.add(Callee);
365 
366  // Tell the call which registers are clobbered.
367  auto TRI = MF.getSubtarget().getRegisterInfo();
368  MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
369 
370  // Do the actual argument marshalling.
371  SmallVector<unsigned, 8> PhysRegs;
372  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
373  AssignFnVarArg);
374  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
375  return false;
376 
377  // Now we can add the actual call instruction to the correct basic block.
378  MIRBuilder.insertInstr(MIB);
379 
380  // If Callee is a reg, since it is used by a target specific
381  // instruction, it must have a register class matching the
382  // constraint of that instruction.
383  if (Callee.isReg())
385  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
386  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
387 
388  // Finally we can copy the returned value back into its virtual-register. In
389  // symmetry with the arugments, the physical register must be an
390  // implicit-define of the call instruction.
391  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
392  if (OrigRet.Reg) {
393  SplitArgs.clear();
394 
395  SmallVector<uint64_t, 8> RegOffsets;
396  SmallVector<unsigned, 8> SplitRegs;
397  splitToValueTypes(OrigRet, SplitArgs, DL, MRI, F.getCallingConv(),
398  [&](unsigned Reg, uint64_t Offset) {
399  RegOffsets.push_back(Offset);
400  SplitRegs.push_back(Reg);
401  });
402 
403  CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
404  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
405  return false;
406 
407  if (!RegOffsets.empty())
408  MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets);
409  }
410 
411  CallSeqStart.addImm(Handler.StackSize).addImm(0);
412  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
413  .addImm(Handler.StackSize)
414  .addImm(0);
415 
416  return true;
417 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:163
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res = COPY Op.
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildUndef(DstType &&Res)
Build and insert Res = IMPLICIT_DEF.
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:940
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
static const MCPhysReg VRegs[32]
MachineInstrBuilder buildAnyExt(unsigned Res, unsigned Op)
Build and insert Res = G_ANYEXT Op0.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This file contains the simple types necessary to represent the attributes associated with functions a...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
unsigned getSizeInBits() const
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg)
Build and insert Res = G_ZEXT Op.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
amdgpu Simplify well known AMD library false Value * Callee
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0, ...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
size_t size() const
Definition: SmallVector.h:53
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:61
This class contains a discriminated union of information about pointers in memory operands...
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, unsigned VReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
CCValAssign - Represent assignment of one arg/retval to a location.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res = G_TRUNC Op.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:647
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
void setReg(unsigned Reg)
Change the register this operand corresponds to.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
The memory access always returns the same value (or traps).
MachineFunction & getMF()
Getter for the function we currently build.
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:411
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArgsTy &&... Args)
DAG like Generic method for building arbitrary instructions as above.
AArch64CallLowering(const AArch64TargetLowering &TLI)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:47
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
static void Split(std::vector< std::string > &V, StringRef S)
Splits a string of comma separated items in to a vector of strings.
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
iterator_range< arg_iterator > args()
Definition: Function.h:675