LLVM  6.0.0svn
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "AArch64CallLowering.h"
17 #include "AArch64ISelLowering.h"
19 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/ArrayRef.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/Analysis.h"
38 #include "llvm/IR/Argument.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Type.h"
42 #include "llvm/IR/Value.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstdint>
46 #include <iterator>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 namespace {
54 struct IncomingArgHandler : public CallLowering::ValueHandler {
55  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
56  CCAssignFn *AssignFn)
57  : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
58 
59  unsigned getStackAddress(uint64_t Size, int64_t Offset,
60  MachinePointerInfo &MPO) override {
61  auto &MFI = MIRBuilder.getMF().getFrameInfo();
62  int FI = MFI.CreateFixedObject(Size, Offset, true);
63  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
64  unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
65  MIRBuilder.buildFrameIndex(AddrReg, FI);
66  StackUsed = std::max(StackUsed, Size + Offset);
67  return AddrReg;
68  }
69 
70  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
71  CCValAssign &VA) override {
72  markPhysRegUsed(PhysReg);
73  switch (VA.getLocInfo()) {
74  default:
75  MIRBuilder.buildCopy(ValVReg, PhysReg);
76  break;
77  case CCValAssign::LocInfo::SExt:
78  case CCValAssign::LocInfo::ZExt:
79  case CCValAssign::LocInfo::AExt: {
80  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
81  MIRBuilder.buildTrunc(ValVReg, Copy);
82  break;
83  }
84  }
85  }
86 
87  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
88  MachinePointerInfo &MPO, CCValAssign &VA) override {
89  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
91  0);
92  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
93  }
94 
95  /// How the physical register gets marked varies between formal
96  /// parameters (it's a basic-block live-in), and a call instruction
97  /// (it's an implicit-def of the BL).
98  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
99 
100  uint64_t StackUsed;
101 };
102 
103 struct FormalArgHandler : public IncomingArgHandler {
104  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
105  CCAssignFn *AssignFn)
106  : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
107 
108  void markPhysRegUsed(unsigned PhysReg) override {
109  MIRBuilder.getMBB().addLiveIn(PhysReg);
110  }
111 };
112 
113 struct CallReturnHandler : public IncomingArgHandler {
114  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
115  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
116  : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
117 
118  void markPhysRegUsed(unsigned PhysReg) override {
119  MIB.addDef(PhysReg, RegState::Implicit);
120  }
121 
123 };
124 
125 struct OutgoingArgHandler : public CallLowering::ValueHandler {
126  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
127  MachineInstrBuilder MIB, CCAssignFn *AssignFn,
128  CCAssignFn *AssignFnVarArg)
129  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
130  AssignFnVarArg(AssignFnVarArg), StackSize(0) {}
131 
132  unsigned getStackAddress(uint64_t Size, int64_t Offset,
133  MachinePointerInfo &MPO) override {
134  LLT p0 = LLT::pointer(0, 64);
135  LLT s64 = LLT::scalar(64);
136  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
137  MIRBuilder.buildCopy(SPReg, AArch64::SP);
138 
139  unsigned OffsetReg = MRI.createGenericVirtualRegister(s64);
140  MIRBuilder.buildConstant(OffsetReg, Offset);
141 
142  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
143  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
144 
145  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
146  return AddrReg;
147  }
148 
149  void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
150  CCValAssign &VA) override {
151  MIB.addUse(PhysReg, RegState::Implicit);
152  unsigned ExtReg = extendRegister(ValVReg, VA);
153  MIRBuilder.buildCopy(PhysReg, ExtReg);
154  }
155 
156  void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
157  MachinePointerInfo &MPO, CCValAssign &VA) override {
158  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
159  MPO, MachineMemOperand::MOStore, Size, 0);
160  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
161  }
162 
163  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
164  CCValAssign::LocInfo LocInfo,
165  const CallLowering::ArgInfo &Info,
166  CCState &State) override {
167  bool Res;
168  if (Info.IsFixed)
169  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
170  else
171  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
172 
173  StackSize = State.getNextStackOffset();
174  return Res;
175  }
176 
178  CCAssignFn *AssignFnVarArg;
179  uint64_t StackSize;
180 };
181 } // namespace
182 
183 void AArch64CallLowering::splitToValueTypes(
184  const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
185  const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv,
186  const SplitArgTy &PerformArgSplit) const {
187  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
188  LLVMContext &Ctx = OrigArg.Ty->getContext();
189 
190  SmallVector<EVT, 4> SplitVTs;
192  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
193 
194  if (SplitVTs.size() == 1) {
195  // No splitting to do, but we want to replace the original type (e.g. [1 x
196  // double] -> double).
197  SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx),
198  OrigArg.Flags, OrigArg.IsFixed);
199  return;
200  }
201 
202  unsigned FirstRegIdx = SplitArgs.size();
203  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
204  OrigArg.Ty, CallConv, false);
205  for (auto SplitVT : SplitVTs) {
206  Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
207  SplitArgs.push_back(
209  SplitTy, OrigArg.Flags, OrigArg.IsFixed});
210  if (NeedsRegBlock)
211  SplitArgs.back().Flags.setInConsecutiveRegs();
212  }
213 
214  SplitArgs.back().Flags.setInConsecutiveRegsLast();
215 
216  for (unsigned i = 0; i < Offsets.size(); ++i)
217  PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8);
218 }
219 
221  const Value *Val, unsigned VReg) const {
222  MachineFunction &MF = MIRBuilder.getMF();
223  const Function &F = *MF.getFunction();
224 
225  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
226  assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
227  bool Success = true;
228  if (VReg) {
229  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
230  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
231  MachineRegisterInfo &MRI = MF.getRegInfo();
232  auto &DL = F.getParent()->getDataLayout();
233 
234  ArgInfo OrigArg{VReg, Val->getType()};
235  setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
236 
237  SmallVector<ArgInfo, 8> SplitArgs;
238  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
239  [&](unsigned Reg, uint64_t Offset) {
240  MIRBuilder.buildExtract(Reg, VReg, Offset);
241  });
242 
243  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
244  Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
245  }
246 
247  MIRBuilder.insertInstr(MIB);
248  return Success;
249 }
250 
252  const Function &F,
253  ArrayRef<unsigned> VRegs) const {
254  MachineFunction &MF = MIRBuilder.getMF();
255  MachineBasicBlock &MBB = MIRBuilder.getMBB();
256  MachineRegisterInfo &MRI = MF.getRegInfo();
257  auto &DL = F.getParent()->getDataLayout();
258 
259  SmallVector<ArgInfo, 8> SplitArgs;
260  unsigned i = 0;
261  for (auto &Arg : F.args()) {
262  ArgInfo OrigArg{VRegs[i], Arg.getType()};
263  setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
264  bool Split = false;
265  LLT Ty = MRI.getType(VRegs[i]);
266  unsigned Dst = VRegs[i];
267 
268  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(),
269  [&](unsigned Reg, uint64_t Offset) {
270  if (!Split) {
271  Split = true;
272  Dst = MRI.createGenericVirtualRegister(Ty);
273  MIRBuilder.buildUndef(Dst);
274  }
275  unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
276  MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
277  Dst = Tmp;
278  });
279 
280  if (Dst != VRegs[i])
281  MIRBuilder.buildCopy(VRegs[i], Dst);
282  ++i;
283  }
284 
285  if (!MBB.empty())
286  MIRBuilder.setInstr(*MBB.begin());
287 
288  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
289  CCAssignFn *AssignFn =
290  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
291 
292  FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
293  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
294  return false;
295 
296  if (F.isVarArg()) {
298  // FIXME: we need to reimplement saveVarArgsRegisters from
299  // AArch64ISelLowering.
300  return false;
301  }
302 
303  // We currently pass all varargs at 8-byte alignment.
304  uint64_t StackOffset = alignTo(Handler.StackUsed, 8);
305 
306  auto &MFI = MIRBuilder.getMF().getFrameInfo();
308  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
309  }
310 
311  // Move back to the end of the basic block.
312  MIRBuilder.setMBB(MBB);
313 
314  return true;
315 }
316 
318  CallingConv::ID CallConv,
319  const MachineOperand &Callee,
320  const ArgInfo &OrigRet,
321  ArrayRef<ArgInfo> OrigArgs) const {
322  MachineFunction &MF = MIRBuilder.getMF();
323  const Function &F = *MF.getFunction();
324  MachineRegisterInfo &MRI = MF.getRegInfo();
325  auto &DL = F.getParent()->getDataLayout();
326 
327  SmallVector<ArgInfo, 8> SplitArgs;
328  for (auto &OrigArg : OrigArgs) {
329  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv,
330  [&](unsigned Reg, uint64_t Offset) {
331  MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset);
332  });
333  }
334 
335  // Find out which ABI gets to decide where things go.
336  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
337  CCAssignFn *AssignFnFixed =
338  TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
339  CCAssignFn *AssignFnVarArg =
340  TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/true);
341 
342  auto CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
343 
344  // Create a temporarily-floating call instruction so we can add the implicit
345  // uses of arg registers.
346  auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR
347  : AArch64::BL);
348  MIB.add(Callee);
349 
350  // Tell the call which registers are clobbered.
351  auto TRI = MF.getSubtarget().getRegisterInfo();
352  MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
353 
354  // Do the actual argument marshalling.
355  SmallVector<unsigned, 8> PhysRegs;
356  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
357  AssignFnVarArg);
358  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
359  return false;
360 
361  // Now we can add the actual call instruction to the correct basic block.
362  MIRBuilder.insertInstr(MIB);
363 
364  // If Callee is a reg, since it is used by a target specific
365  // instruction, it must have a register class matching the
366  // constraint of that instruction.
367  if (Callee.isReg())
369  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
370  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(),
371  Callee.getReg(), 0));
372 
373  // Finally we can copy the returned value back into its virtual-register. In
374  // symmetry with the arugments, the physical register must be an
375  // implicit-define of the call instruction.
376  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
377  if (OrigRet.Reg) {
378  SplitArgs.clear();
379 
380  SmallVector<uint64_t, 8> RegOffsets;
381  SmallVector<unsigned, 8> SplitRegs;
382  splitToValueTypes(OrigRet, SplitArgs, DL, MRI, F.getCallingConv(),
383  [&](unsigned Reg, uint64_t Offset) {
384  RegOffsets.push_back(Offset);
385  SplitRegs.push_back(Reg);
386  });
387 
388  CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
389  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
390  return false;
391 
392  if (!RegOffsets.empty())
393  MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets);
394  }
395 
396  CallSeqStart.addImm(Handler.StackSize).addImm(0);
397  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
398  .addImm(Handler.StackSize)
399  .addImm(0);
400 
401  return true;
402 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:158
MachineBasicBlock & getMBB()
Getter for the basic block we currently build.
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res<def> = G_GEP Op0, Op1.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
Definition: Utils.cpp:46
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getReg() const
getReg - Returns the register number.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:935
static const MCPhysReg VRegs[32]
MachineInstrBuilder buildTrunc(unsigned Res, unsigned Op)
Build and insert Res<def> = G_TRUNC Op.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:677
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index)
Build and insert `Res0<def>, ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
MachineFunction & getMF()
Getter for the function we currently build.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
amdgpu Simplify well known AMD library false Value * Callee
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:85
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Callback) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Helper class to build MachineInstr.
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:61
This class contains a discriminated union of information about pointers in memory operands...
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res<def> = G_FRAME_INDEX Idx.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, unsigned VReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
CCState - This class holds information needed while lowering arguments and return values...
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res<def> = COPY Op.
CCValAssign - Represent assignment of one arg/retval to a location.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
This file declares the MachineIRBuilder class.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
MachineInstrBuilder buildUndef(unsigned Dst)
Build and insert Res = IMPLICIT_DEF.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:656
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildConstant(unsigned Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
The memory access always returns the same value (or traps).
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:556
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res<def> = G_LOAD Addr, MMO.
AArch64CallLowering(const AArch64TargetLowering &TLI)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
static void Split(std::vector< std::string > &V, StringRef S)
Splits a string of comma separated items in to a vector of strings.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
iterator_range< arg_iterator > args()
Definition: Function.h:621