34#define DEBUG_TYPE "aarch64-disassembler"
76 uint64_t Address,
const void *Decoder);
125 const void *Decoder);
128 const void *Decoder);
131 const void *Decoder);
134 const void *Decoder);
135template <
unsigned NumBitsForTile>
160 const void *Decoder);
163 const void *Decoder);
291template <
int ElementW
idth>
309#include "AArch64GenDisassemblerTables.inc"
310#include "AArch64GenInstrInfo.inc"
312#define Success MCDisassembler::Success
313#define Fail MCDisassembler::Fail
314#define SoftFail MCDisassembler::SoftFail
331 if (Bytes.
size() < 4)
337 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
339 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
341 for (
const auto *Table : Tables) {
350 for (
unsigned i = 0; i <
Desc.getNumOperands(); i++) {
352 switch (
Desc.operands()[i].RegClass) {
355 case AArch64::MPRRegClassID:
358 case AArch64::MPR8RegClassID:
361 case AArch64::ZTRRegClassID:
365 }
else if (
Desc.operands()[i].OperandType ==
371 if (
MI.getOpcode() == AArch64::LDR_ZA ||
372 MI.getOpcode() == AArch64::STR_ZA) {
377 assert(Imm4Op.
isImm() &&
"Unexpected operand type!");
378 MI.addOperand(Imm4Op);
400 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
402 SymbolLookUp, DisInfo);
436 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
464 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
476 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
488 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
500 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
512 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
525 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
539 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
551 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
563 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
577 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
590 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
602 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
614 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
641 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
652 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
663 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
670 const void *Decoder) {
674 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
681 const void *Decoder) {
685 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
692 const void *Decoder) {
696 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
704 const void *Decoder) {
708 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
726 {AArch64::ZAH0, AArch64::ZAH1},
727 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
728 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
729 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
730 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
731 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
732 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
733 AArch64::ZAQ14, AArch64::ZAQ15}};
735template <
unsigned NumBitsForTile>
739 unsigned LastReg = (1 << NumBitsForTile) - 1;
754 AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
766 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
778 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
805 const void *Decoder) {
810 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
817 const void *Decoder) {
818 if ((RegNo * 2) > 14)
821 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
832 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
843 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
854 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
865 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
876 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
887 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
914 if (ImmVal > (1 << 16))
926 int64_t ImmVal = Imm;
929 if (ImmVal & (1 << (19 - 1)))
930 ImmVal |= ~((1LL << 19) - 1);
933 Inst, ImmVal * 4,
Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
969 unsigned Rd = fieldFromInstruction(
Insn, 0, 5);
970 unsigned Rn = fieldFromInstruction(
Insn, 5, 5);
971 unsigned IsToVec = fieldFromInstruction(
Insn, 16, 1);
1068 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1069 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1070 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1071 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1072 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1073 unsigned shift = (shiftHi << 6) | shiftLo;
1077 case AArch64::ADDWrs:
1078 case AArch64::ADDSWrs:
1079 case AArch64::SUBWrs:
1080 case AArch64::SUBSWrs:
1085 case AArch64::ANDWrs:
1086 case AArch64::ANDSWrs:
1087 case AArch64::BICWrs:
1088 case AArch64::BICSWrs:
1089 case AArch64::ORRWrs:
1090 case AArch64::ORNWrs:
1091 case AArch64::EORWrs:
1092 case AArch64::EONWrs: {
1094 if (shiftLo >> 5 == 1)
1101 case AArch64::ADDXrs:
1102 case AArch64::ADDSXrs:
1103 case AArch64::SUBXrs:
1104 case AArch64::SUBSXrs:
1109 case AArch64::ANDXrs:
1110 case AArch64::ANDSXrs:
1111 case AArch64::BICXrs:
1112 case AArch64::BICSXrs:
1113 case AArch64::ORRXrs:
1114 case AArch64::ORNXrs:
1115 case AArch64::EORXrs:
1116 case AArch64::EONXrs:
1130 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1131 unsigned imm = fieldFromInstruction(insn, 5, 16);
1132 unsigned shift = fieldFromInstruction(insn, 21, 2);
1137 case AArch64::MOVZWi:
1138 case AArch64::MOVNWi:
1139 case AArch64::MOVKWi:
1140 if (shift & (1U << 5))
1144 case AArch64::MOVZXi:
1145 case AArch64::MOVNXi:
1146 case AArch64::MOVKXi:
1151 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1163 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1164 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1165 unsigned offset = fieldFromInstruction(insn, 10, 12);
1170 case AArch64::PRFMui:
1174 case AArch64::STRBBui:
1175 case AArch64::LDRBBui:
1176 case AArch64::LDRSBWui:
1177 case AArch64::STRHHui:
1178 case AArch64::LDRHHui:
1179 case AArch64::LDRSHWui:
1180 case AArch64::STRWui:
1181 case AArch64::LDRWui:
1184 case AArch64::LDRSBXui:
1185 case AArch64::LDRSHXui:
1186 case AArch64::LDRSWui:
1187 case AArch64::STRXui:
1188 case AArch64::LDRXui:
1191 case AArch64::LDRQui:
1192 case AArch64::STRQui:
1195 case AArch64::LDRDui:
1196 case AArch64::STRDui:
1199 case AArch64::LDRSui:
1200 case AArch64::STRSui:
1203 case AArch64::LDRHui:
1204 case AArch64::STRHui:
1207 case AArch64::LDRBui:
1208 case AArch64::STRBui:
1222 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1223 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1224 int64_t offset = fieldFromInstruction(insn, 12, 9);
1228 if (offset & (1 << (9 - 1)))
1229 offset |= ~((1LL << 9) - 1);
1235 case AArch64::LDRSBWpre:
1236 case AArch64::LDRSHWpre:
1237 case AArch64::STRBBpre:
1238 case AArch64::LDRBBpre:
1239 case AArch64::STRHHpre:
1240 case AArch64::LDRHHpre:
1241 case AArch64::STRWpre:
1242 case AArch64::LDRWpre:
1243 case AArch64::LDRSBWpost:
1244 case AArch64::LDRSHWpost:
1245 case AArch64::STRBBpost:
1246 case AArch64::LDRBBpost:
1247 case AArch64::STRHHpost:
1248 case AArch64::LDRHHpost:
1249 case AArch64::STRWpost:
1250 case AArch64::LDRWpost:
1251 case AArch64::LDRSBXpre:
1252 case AArch64::LDRSHXpre:
1253 case AArch64::STRXpre:
1254 case AArch64::LDRSWpre:
1255 case AArch64::LDRXpre:
1256 case AArch64::LDRSBXpost:
1257 case AArch64::LDRSHXpost:
1258 case AArch64::STRXpost:
1259 case AArch64::LDRSWpost:
1260 case AArch64::LDRXpost:
1261 case AArch64::LDRQpre:
1262 case AArch64::STRQpre:
1263 case AArch64::LDRQpost:
1264 case AArch64::STRQpost:
1265 case AArch64::LDRDpre:
1266 case AArch64::STRDpre:
1267 case AArch64::LDRDpost:
1268 case AArch64::STRDpost:
1269 case AArch64::LDRSpre:
1270 case AArch64::STRSpre:
1271 case AArch64::LDRSpost:
1272 case AArch64::STRSpost:
1273 case AArch64::LDRHpre:
1274 case AArch64::STRHpre:
1275 case AArch64::LDRHpost:
1276 case AArch64::STRHpost:
1277 case AArch64::LDRBpre:
1278 case AArch64::STRBpre:
1279 case AArch64::LDRBpost:
1280 case AArch64::STRBpost:
1288 case AArch64::PRFUMi:
1292 case AArch64::STURBBi:
1293 case AArch64::LDURBBi:
1294 case AArch64::LDURSBWi:
1295 case AArch64::STURHHi:
1296 case AArch64::LDURHHi:
1297 case AArch64::LDURSHWi:
1298 case AArch64::STURWi:
1299 case AArch64::LDURWi:
1300 case AArch64::LDTRSBWi:
1301 case AArch64::LDTRSHWi:
1302 case AArch64::STTRWi:
1303 case AArch64::LDTRWi:
1304 case AArch64::STTRHi:
1305 case AArch64::LDTRHi:
1306 case AArch64::LDTRBi:
1307 case AArch64::STTRBi:
1308 case AArch64::LDRSBWpre:
1309 case AArch64::LDRSHWpre:
1310 case AArch64::STRBBpre:
1311 case AArch64::LDRBBpre:
1312 case AArch64::STRHHpre:
1313 case AArch64::LDRHHpre:
1314 case AArch64::STRWpre:
1315 case AArch64::LDRWpre:
1316 case AArch64::LDRSBWpost:
1317 case AArch64::LDRSHWpost:
1318 case AArch64::STRBBpost:
1319 case AArch64::LDRBBpost:
1320 case AArch64::STRHHpost:
1321 case AArch64::LDRHHpost:
1322 case AArch64::STRWpost:
1323 case AArch64::LDRWpost:
1324 case AArch64::STLURBi:
1325 case AArch64::STLURHi:
1326 case AArch64::STLURWi:
1327 case AArch64::LDAPURBi:
1328 case AArch64::LDAPURSBWi:
1329 case AArch64::LDAPURHi:
1330 case AArch64::LDAPURSHWi:
1331 case AArch64::LDAPURi:
1334 case AArch64::LDURSBXi:
1335 case AArch64::LDURSHXi:
1336 case AArch64::LDURSWi:
1337 case AArch64::STURXi:
1338 case AArch64::LDURXi:
1339 case AArch64::LDTRSBXi:
1340 case AArch64::LDTRSHXi:
1341 case AArch64::LDTRSWi:
1342 case AArch64::STTRXi:
1343 case AArch64::LDTRXi:
1344 case AArch64::LDRSBXpre:
1345 case AArch64::LDRSHXpre:
1346 case AArch64::STRXpre:
1347 case AArch64::LDRSWpre:
1348 case AArch64::LDRXpre:
1349 case AArch64::LDRSBXpost:
1350 case AArch64::LDRSHXpost:
1351 case AArch64::STRXpost:
1352 case AArch64::LDRSWpost:
1353 case AArch64::LDRXpost:
1354 case AArch64::LDAPURSWi:
1355 case AArch64::LDAPURSHXi:
1356 case AArch64::LDAPURSBXi:
1357 case AArch64::STLURXi:
1358 case AArch64::LDAPURXi:
1361 case AArch64::LDURQi:
1362 case AArch64::STURQi:
1363 case AArch64::LDRQpre:
1364 case AArch64::STRQpre:
1365 case AArch64::LDRQpost:
1366 case AArch64::STRQpost:
1369 case AArch64::LDURDi:
1370 case AArch64::STURDi:
1371 case AArch64::LDRDpre:
1372 case AArch64::STRDpre:
1373 case AArch64::LDRDpost:
1374 case AArch64::STRDpost:
1377 case AArch64::LDURSi:
1378 case AArch64::STURSi:
1379 case AArch64::LDRSpre:
1380 case AArch64::STRSpre:
1381 case AArch64::LDRSpost:
1382 case AArch64::STRSpost:
1385 case AArch64::LDURHi:
1386 case AArch64::STURHi:
1387 case AArch64::LDRHpre:
1388 case AArch64::STRHpre:
1389 case AArch64::LDRHpost:
1390 case AArch64::STRHpost:
1393 case AArch64::LDURBi:
1394 case AArch64::STURBi:
1395 case AArch64::LDRBpre:
1396 case AArch64::STRBpre:
1397 case AArch64::LDRBpost:
1398 case AArch64::STRBpost:
1406 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1407 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1408 bool IsFP = fieldFromInstruction(insn, 26, 1);
1411 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1420 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1421 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1422 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1423 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1429 case AArch64::STLXRW:
1430 case AArch64::STLXRB:
1431 case AArch64::STLXRH:
1432 case AArch64::STXRW:
1433 case AArch64::STXRB:
1434 case AArch64::STXRH:
1437 case AArch64::LDARW:
1438 case AArch64::LDARB:
1439 case AArch64::LDARH:
1440 case AArch64::LDAXRW:
1441 case AArch64::LDAXRB:
1442 case AArch64::LDAXRH:
1443 case AArch64::LDXRW:
1444 case AArch64::LDXRB:
1445 case AArch64::LDXRH:
1446 case AArch64::STLRW:
1447 case AArch64::STLRB:
1448 case AArch64::STLRH:
1449 case AArch64::STLLRW:
1450 case AArch64::STLLRB:
1451 case AArch64::STLLRH:
1452 case AArch64::LDLARW:
1453 case AArch64::LDLARB:
1454 case AArch64::LDLARH:
1457 case AArch64::STLXRX:
1458 case AArch64::STXRX:
1461 case AArch64::LDARX:
1462 case AArch64::LDAXRX:
1463 case AArch64::LDXRX:
1464 case AArch64::STLRX:
1465 case AArch64::LDLARX:
1466 case AArch64::STLLRX:
1469 case AArch64::STLXPW:
1470 case AArch64::STXPW:
1473 case AArch64::LDAXPW:
1474 case AArch64::LDXPW:
1478 case AArch64::STLXPX:
1479 case AArch64::STXPX:
1482 case AArch64::LDAXPX:
1483 case AArch64::LDXPX:
1492 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1493 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1503 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1504 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1505 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1506 int64_t offset = fieldFromInstruction(insn, 15, 7);
1507 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1511 if (offset & (1 << (7 - 1)))
1512 offset |= ~((1LL << 7) - 1);
1515 bool NeedsDisjointWritebackTransfer =
false;
1521 case AArch64::LDPXpost:
1522 case AArch64::STPXpost:
1523 case AArch64::LDPSWpost:
1524 case AArch64::LDPXpre:
1525 case AArch64::STPXpre:
1526 case AArch64::LDPSWpre:
1527 case AArch64::LDPWpost:
1528 case AArch64::STPWpost:
1529 case AArch64::LDPWpre:
1530 case AArch64::STPWpre:
1531 case AArch64::LDPQpost:
1532 case AArch64::STPQpost:
1533 case AArch64::LDPQpre:
1534 case AArch64::STPQpre:
1535 case AArch64::LDPDpost:
1536 case AArch64::STPDpost:
1537 case AArch64::LDPDpre:
1538 case AArch64::STPDpre:
1539 case AArch64::LDPSpost:
1540 case AArch64::STPSpost:
1541 case AArch64::LDPSpre:
1542 case AArch64::STPSpre:
1543 case AArch64::STGPpre:
1544 case AArch64::STGPpost:
1552 case AArch64::LDPXpost:
1553 case AArch64::STPXpost:
1554 case AArch64::LDPSWpost:
1555 case AArch64::LDPXpre:
1556 case AArch64::STPXpre:
1557 case AArch64::LDPSWpre:
1558 case AArch64::STGPpre:
1559 case AArch64::STGPpost:
1560 NeedsDisjointWritebackTransfer =
true;
1562 case AArch64::LDNPXi:
1563 case AArch64::STNPXi:
1564 case AArch64::LDPXi:
1565 case AArch64::STPXi:
1566 case AArch64::LDPSWi:
1567 case AArch64::STGPi:
1571 case AArch64::LDPWpost:
1572 case AArch64::STPWpost:
1573 case AArch64::LDPWpre:
1574 case AArch64::STPWpre:
1575 NeedsDisjointWritebackTransfer =
true;
1577 case AArch64::LDNPWi:
1578 case AArch64::STNPWi:
1579 case AArch64::LDPWi:
1580 case AArch64::STPWi:
1584 case AArch64::LDNPQi:
1585 case AArch64::STNPQi:
1586 case AArch64::LDPQpost:
1587 case AArch64::STPQpost:
1588 case AArch64::LDPQi:
1589 case AArch64::STPQi:
1590 case AArch64::LDPQpre:
1591 case AArch64::STPQpre:
1595 case AArch64::LDNPDi:
1596 case AArch64::STNPDi:
1597 case AArch64::LDPDpost:
1598 case AArch64::STPDpost:
1599 case AArch64::LDPDi:
1600 case AArch64::STPDi:
1601 case AArch64::LDPDpre:
1602 case AArch64::STPDpre:
1606 case AArch64::LDNPSi:
1607 case AArch64::STNPSi:
1608 case AArch64::LDPSpost:
1609 case AArch64::STPSpost:
1610 case AArch64::LDPSi:
1611 case AArch64::STPSi:
1612 case AArch64::LDPSpre:
1613 case AArch64::STPSpre:
1623 if (IsLoad && Rt == Rt2)
1628 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1637 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1638 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1639 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1640 fieldFromInstruction(insn, 12, 9);
1641 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1646 case AArch64::LDRAAwriteback:
1647 case AArch64::LDRABwriteback:
1651 case AArch64::LDRAAindexed:
1652 case AArch64::LDRABindexed:
1658 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1660 if (writeback && Rt == Rn && Rn != 31) {
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1671 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1672 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1673 unsigned extend = fieldFromInstruction(insn, 10, 6);
1675 unsigned shift = extend & 0x7;
1682 case AArch64::ADDWrx:
1683 case AArch64::SUBWrx:
1688 case AArch64::ADDSWrx:
1689 case AArch64::SUBSWrx:
1694 case AArch64::ADDXrx:
1695 case AArch64::SUBXrx:
1700 case AArch64::ADDSXrx:
1701 case AArch64::SUBSXrx:
1706 case AArch64::ADDXrx64:
1707 case AArch64::SUBXrx64:
1712 case AArch64::SUBSXrx64:
1713 case AArch64::ADDSXrx64:
1727 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1728 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1729 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1733 if (Inst.
getOpcode() == AArch64::ANDSXri)
1738 imm = fieldFromInstruction(insn, 10, 13);
1742 if (Inst.
getOpcode() == AArch64::ANDSWri)
1747 imm = fieldFromInstruction(insn, 10, 12);
1758 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1759 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1760 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1761 imm |= fieldFromInstruction(insn, 5, 5);
1773 case AArch64::MOVIv4i16:
1774 case AArch64::MOVIv8i16:
1775 case AArch64::MVNIv4i16:
1776 case AArch64::MVNIv8i16:
1777 case AArch64::MOVIv2i32:
1778 case AArch64::MOVIv4i32:
1779 case AArch64::MVNIv2i32:
1780 case AArch64::MVNIv4i32:
1783 case AArch64::MOVIv2s_msl:
1784 case AArch64::MOVIv4s_msl:
1785 case AArch64::MVNIv2s_msl:
1786 case AArch64::MVNIv4s_msl:
1797 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1798 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1799 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1800 imm |= fieldFromInstruction(insn, 5, 5);
1815 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1816 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1817 imm |= fieldFromInstruction(insn, 29, 2);
1820 if (imm & (1 << (21 - 1)))
1821 imm |= ~((1LL << 21) - 1);
1833 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1834 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1835 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1836 unsigned S = fieldFromInstruction(insn, 29, 1);
1837 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1839 unsigned ShifterVal = (Imm >> 12) & 3;
1840 unsigned ImmVal = Imm & 0xFFF;
1842 if (ShifterVal != 0 && ShifterVal != 1)
1868 int64_t imm = fieldFromInstruction(insn, 0, 26);
1871 if (imm & (1 << (26 - 1)))
1872 imm |= ~((1LL << 26) - 1);
1881 return Op1 == 0b000 && (Op2 == 0b000 ||
1889 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1890 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1891 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1892 uint64_t pstate_field = (op1 << 3) | op2;
1900 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1910 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1911 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1912 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1913 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1914 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1922 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1932 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1933 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1934 bit |= fieldFromInstruction(insn, 19, 5);
1935 int64_t dst = fieldFromInstruction(insn, 5, 14);
1938 if (dst & (1 << (14 - 1)))
1939 dst |= ~((1LL << 14) - 1);
1941 if (fieldFromInstruction(insn, 31, 1) == 0)
1960 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1969 AArch64::WSeqPairsClassRegClassID,
1970 RegNo,
Addr, Decoder);
1977 AArch64::XSeqPairsClassRegClassID,
1978 RegNo,
Addr, Decoder);
1984 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1985 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1986 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1987 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1988 unsigned Rt = fieldFromInstruction(insn, 0, 5);
2004 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
2005 unsigned imm = fieldFromInstruction(insn, 5, 13);
2011 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
2020 if (Imm & ~((1LL << Bits) - 1))
2024 if (Imm & (1 << (Bits - 1)))
2025 Imm |= ~((1LL << Bits) - 1);
2032template <
int ElementW
idth>
2035 unsigned Val = (uint8_t)Imm;
2036 unsigned Shift = (Imm & 0x100) ? 8 : 0;
2037 if (ElementWidth == 8 && Shift)
2054 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2064 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2065 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2066 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2070 if (Rd == Rs || Rs == Rn || Rd == Rn)
2089 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2090 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2091 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2095 if (Rd == Rm || Rm == Rn || Rd == Rn)
2115 unsigned Mask = 0x18;
2116 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2117 if ((Rt & Mask) == Mask)
2120 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2121 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2122 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2123 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2131 case AArch64::PRFMroW:
2134 case AArch64::PRFMroX:
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const MCPhysReg MatrixZATileDecoderTable[5][16]
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.