34#define DEBUG_TYPE "aarch64-disassembler"
76 uint64_t Address,
const void *Decoder);
125 const void *Decoder);
128 const void *Decoder);
131 const void *Decoder);
134 const void *Decoder);
135template <
unsigned NumBitsForTile>
157 const void *Decoder);
160 const void *Decoder);
288template <
int ElementW
idth>
306#include "AArch64GenDisassemblerTables.inc"
307#include "AArch64GenInstrInfo.inc"
309#define Success MCDisassembler::Success
310#define Fail MCDisassembler::Fail
311#define SoftFail MCDisassembler::SoftFail
328 if (Bytes.
size() < 4)
334 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
336 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
338 for (
const auto *Table : Tables) {
347 for (
unsigned i = 0; i <
Desc.getNumOperands(); i++) {
349 switch (
Desc.operands()[i].RegClass) {
352 case AArch64::MPRRegClassID:
355 case AArch64::MPR8RegClassID:
358 case AArch64::ZTRRegClassID:
362 }
else if (
Desc.operands()[i].OperandType ==
368 if (
MI.getOpcode() == AArch64::LDR_ZA ||
369 MI.getOpcode() == AArch64::STR_ZA) {
374 assert(Imm4Op.
isImm() &&
"Unexpected operand type!");
375 MI.addOperand(Imm4Op);
397 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
399 SymbolLookUp, DisInfo);
433 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
461 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
473 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
485 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
497 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
509 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
522 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
536 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
548 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
560 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
574 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
587 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
599 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
611 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
638 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
649 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
660 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
667 const void *Decoder) {
671 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
678 const void *Decoder) {
682 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
689 const void *Decoder) {
693 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
701 const void *Decoder) {
705 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
723 {AArch64::ZAH0, AArch64::ZAH1},
724 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
725 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
726 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
727 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
728 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
729 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
730 AArch64::ZAQ14, AArch64::ZAQ15}};
732template <
unsigned NumBitsForTile>
736 unsigned LastReg = (1 << NumBitsForTile) - 1;
751 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
763 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
790 const void *Decoder) {
795 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
802 const void *Decoder) {
803 if ((RegNo * 2) > 14)
806 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
817 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
828 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
839 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
850 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
861 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
872 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
899 if (ImmVal > (1 << 16))
911 int64_t ImmVal = Imm;
914 if (ImmVal & (1 << (19 - 1)))
915 ImmVal |= ~((1LL << 19) - 1);
918 Inst, ImmVal * 4,
Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
954 unsigned Rd = fieldFromInstruction(
Insn, 0, 5);
955 unsigned Rn = fieldFromInstruction(
Insn, 5, 5);
956 unsigned IsToVec = fieldFromInstruction(
Insn, 16, 1);
1053 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1054 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1055 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1056 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1057 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1058 unsigned shift = (shiftHi << 6) | shiftLo;
1062 case AArch64::ADDWrs:
1063 case AArch64::ADDSWrs:
1064 case AArch64::SUBWrs:
1065 case AArch64::SUBSWrs:
1070 case AArch64::ANDWrs:
1071 case AArch64::ANDSWrs:
1072 case AArch64::BICWrs:
1073 case AArch64::BICSWrs:
1074 case AArch64::ORRWrs:
1075 case AArch64::ORNWrs:
1076 case AArch64::EORWrs:
1077 case AArch64::EONWrs: {
1079 if (shiftLo >> 5 == 1)
1086 case AArch64::ADDXrs:
1087 case AArch64::ADDSXrs:
1088 case AArch64::SUBXrs:
1089 case AArch64::SUBSXrs:
1094 case AArch64::ANDXrs:
1095 case AArch64::ANDSXrs:
1096 case AArch64::BICXrs:
1097 case AArch64::BICSXrs:
1098 case AArch64::ORRXrs:
1099 case AArch64::ORNXrs:
1100 case AArch64::EORXrs:
1101 case AArch64::EONXrs:
1115 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1116 unsigned imm = fieldFromInstruction(insn, 5, 16);
1117 unsigned shift = fieldFromInstruction(insn, 21, 2);
1122 case AArch64::MOVZWi:
1123 case AArch64::MOVNWi:
1124 case AArch64::MOVKWi:
1125 if (shift & (1U << 5))
1129 case AArch64::MOVZXi:
1130 case AArch64::MOVNXi:
1131 case AArch64::MOVKXi:
1136 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1148 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1149 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1150 unsigned offset = fieldFromInstruction(insn, 10, 12);
1155 case AArch64::PRFMui:
1159 case AArch64::STRBBui:
1160 case AArch64::LDRBBui:
1161 case AArch64::LDRSBWui:
1162 case AArch64::STRHHui:
1163 case AArch64::LDRHHui:
1164 case AArch64::LDRSHWui:
1165 case AArch64::STRWui:
1166 case AArch64::LDRWui:
1169 case AArch64::LDRSBXui:
1170 case AArch64::LDRSHXui:
1171 case AArch64::LDRSWui:
1172 case AArch64::STRXui:
1173 case AArch64::LDRXui:
1176 case AArch64::LDRQui:
1177 case AArch64::STRQui:
1180 case AArch64::LDRDui:
1181 case AArch64::STRDui:
1184 case AArch64::LDRSui:
1185 case AArch64::STRSui:
1188 case AArch64::LDRHui:
1189 case AArch64::STRHui:
1192 case AArch64::LDRBui:
1193 case AArch64::STRBui:
1207 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1208 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1209 int64_t offset = fieldFromInstruction(insn, 12, 9);
1213 if (offset & (1 << (9 - 1)))
1214 offset |= ~((1LL << 9) - 1);
1220 case AArch64::LDRSBWpre:
1221 case AArch64::LDRSHWpre:
1222 case AArch64::STRBBpre:
1223 case AArch64::LDRBBpre:
1224 case AArch64::STRHHpre:
1225 case AArch64::LDRHHpre:
1226 case AArch64::STRWpre:
1227 case AArch64::LDRWpre:
1228 case AArch64::LDRSBWpost:
1229 case AArch64::LDRSHWpost:
1230 case AArch64::STRBBpost:
1231 case AArch64::LDRBBpost:
1232 case AArch64::STRHHpost:
1233 case AArch64::LDRHHpost:
1234 case AArch64::STRWpost:
1235 case AArch64::LDRWpost:
1236 case AArch64::LDRSBXpre:
1237 case AArch64::LDRSHXpre:
1238 case AArch64::STRXpre:
1239 case AArch64::LDRSWpre:
1240 case AArch64::LDRXpre:
1241 case AArch64::LDRSBXpost:
1242 case AArch64::LDRSHXpost:
1243 case AArch64::STRXpost:
1244 case AArch64::LDRSWpost:
1245 case AArch64::LDRXpost:
1246 case AArch64::LDRQpre:
1247 case AArch64::STRQpre:
1248 case AArch64::LDRQpost:
1249 case AArch64::STRQpost:
1250 case AArch64::LDRDpre:
1251 case AArch64::STRDpre:
1252 case AArch64::LDRDpost:
1253 case AArch64::STRDpost:
1254 case AArch64::LDRSpre:
1255 case AArch64::STRSpre:
1256 case AArch64::LDRSpost:
1257 case AArch64::STRSpost:
1258 case AArch64::LDRHpre:
1259 case AArch64::STRHpre:
1260 case AArch64::LDRHpost:
1261 case AArch64::STRHpost:
1262 case AArch64::LDRBpre:
1263 case AArch64::STRBpre:
1264 case AArch64::LDRBpost:
1265 case AArch64::STRBpost:
1273 case AArch64::PRFUMi:
1277 case AArch64::STURBBi:
1278 case AArch64::LDURBBi:
1279 case AArch64::LDURSBWi:
1280 case AArch64::STURHHi:
1281 case AArch64::LDURHHi:
1282 case AArch64::LDURSHWi:
1283 case AArch64::STURWi:
1284 case AArch64::LDURWi:
1285 case AArch64::LDTRSBWi:
1286 case AArch64::LDTRSHWi:
1287 case AArch64::STTRWi:
1288 case AArch64::LDTRWi:
1289 case AArch64::STTRHi:
1290 case AArch64::LDTRHi:
1291 case AArch64::LDTRBi:
1292 case AArch64::STTRBi:
1293 case AArch64::LDRSBWpre:
1294 case AArch64::LDRSHWpre:
1295 case AArch64::STRBBpre:
1296 case AArch64::LDRBBpre:
1297 case AArch64::STRHHpre:
1298 case AArch64::LDRHHpre:
1299 case AArch64::STRWpre:
1300 case AArch64::LDRWpre:
1301 case AArch64::LDRSBWpost:
1302 case AArch64::LDRSHWpost:
1303 case AArch64::STRBBpost:
1304 case AArch64::LDRBBpost:
1305 case AArch64::STRHHpost:
1306 case AArch64::LDRHHpost:
1307 case AArch64::STRWpost:
1308 case AArch64::LDRWpost:
1309 case AArch64::STLURBi:
1310 case AArch64::STLURHi:
1311 case AArch64::STLURWi:
1312 case AArch64::LDAPURBi:
1313 case AArch64::LDAPURSBWi:
1314 case AArch64::LDAPURHi:
1315 case AArch64::LDAPURSHWi:
1316 case AArch64::LDAPURi:
1319 case AArch64::LDURSBXi:
1320 case AArch64::LDURSHXi:
1321 case AArch64::LDURSWi:
1322 case AArch64::STURXi:
1323 case AArch64::LDURXi:
1324 case AArch64::LDTRSBXi:
1325 case AArch64::LDTRSHXi:
1326 case AArch64::LDTRSWi:
1327 case AArch64::STTRXi:
1328 case AArch64::LDTRXi:
1329 case AArch64::LDRSBXpre:
1330 case AArch64::LDRSHXpre:
1331 case AArch64::STRXpre:
1332 case AArch64::LDRSWpre:
1333 case AArch64::LDRXpre:
1334 case AArch64::LDRSBXpost:
1335 case AArch64::LDRSHXpost:
1336 case AArch64::STRXpost:
1337 case AArch64::LDRSWpost:
1338 case AArch64::LDRXpost:
1339 case AArch64::LDAPURSWi:
1340 case AArch64::LDAPURSHXi:
1341 case AArch64::LDAPURSBXi:
1342 case AArch64::STLURXi:
1343 case AArch64::LDAPURXi:
1346 case AArch64::LDURQi:
1347 case AArch64::STURQi:
1348 case AArch64::LDRQpre:
1349 case AArch64::STRQpre:
1350 case AArch64::LDRQpost:
1351 case AArch64::STRQpost:
1354 case AArch64::LDURDi:
1355 case AArch64::STURDi:
1356 case AArch64::LDRDpre:
1357 case AArch64::STRDpre:
1358 case AArch64::LDRDpost:
1359 case AArch64::STRDpost:
1362 case AArch64::LDURSi:
1363 case AArch64::STURSi:
1364 case AArch64::LDRSpre:
1365 case AArch64::STRSpre:
1366 case AArch64::LDRSpost:
1367 case AArch64::STRSpost:
1370 case AArch64::LDURHi:
1371 case AArch64::STURHi:
1372 case AArch64::LDRHpre:
1373 case AArch64::STRHpre:
1374 case AArch64::LDRHpost:
1375 case AArch64::STRHpost:
1378 case AArch64::LDURBi:
1379 case AArch64::STURBi:
1380 case AArch64::LDRBpre:
1381 case AArch64::STRBpre:
1382 case AArch64::LDRBpost:
1383 case AArch64::STRBpost:
1391 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1392 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1393 bool IsFP = fieldFromInstruction(insn, 26, 1);
1396 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1405 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1406 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1407 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1408 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1414 case AArch64::STLXRW:
1415 case AArch64::STLXRB:
1416 case AArch64::STLXRH:
1417 case AArch64::STXRW:
1418 case AArch64::STXRB:
1419 case AArch64::STXRH:
1422 case AArch64::LDARW:
1423 case AArch64::LDARB:
1424 case AArch64::LDARH:
1425 case AArch64::LDAXRW:
1426 case AArch64::LDAXRB:
1427 case AArch64::LDAXRH:
1428 case AArch64::LDXRW:
1429 case AArch64::LDXRB:
1430 case AArch64::LDXRH:
1431 case AArch64::STLRW:
1432 case AArch64::STLRB:
1433 case AArch64::STLRH:
1434 case AArch64::STLLRW:
1435 case AArch64::STLLRB:
1436 case AArch64::STLLRH:
1437 case AArch64::LDLARW:
1438 case AArch64::LDLARB:
1439 case AArch64::LDLARH:
1442 case AArch64::STLXRX:
1443 case AArch64::STXRX:
1446 case AArch64::LDARX:
1447 case AArch64::LDAXRX:
1448 case AArch64::LDXRX:
1449 case AArch64::STLRX:
1450 case AArch64::LDLARX:
1451 case AArch64::STLLRX:
1454 case AArch64::STLXPW:
1455 case AArch64::STXPW:
1458 case AArch64::LDAXPW:
1459 case AArch64::LDXPW:
1463 case AArch64::STLXPX:
1464 case AArch64::STXPX:
1467 case AArch64::LDAXPX:
1468 case AArch64::LDXPX:
1477 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1478 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1488 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1489 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1490 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1491 int64_t offset = fieldFromInstruction(insn, 15, 7);
1492 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1496 if (offset & (1 << (7 - 1)))
1497 offset |= ~((1LL << 7) - 1);
1500 bool NeedsDisjointWritebackTransfer =
false;
1506 case AArch64::LDPXpost:
1507 case AArch64::STPXpost:
1508 case AArch64::LDPSWpost:
1509 case AArch64::LDPXpre:
1510 case AArch64::STPXpre:
1511 case AArch64::LDPSWpre:
1512 case AArch64::LDPWpost:
1513 case AArch64::STPWpost:
1514 case AArch64::LDPWpre:
1515 case AArch64::STPWpre:
1516 case AArch64::LDPQpost:
1517 case AArch64::STPQpost:
1518 case AArch64::LDPQpre:
1519 case AArch64::STPQpre:
1520 case AArch64::LDPDpost:
1521 case AArch64::STPDpost:
1522 case AArch64::LDPDpre:
1523 case AArch64::STPDpre:
1524 case AArch64::LDPSpost:
1525 case AArch64::STPSpost:
1526 case AArch64::LDPSpre:
1527 case AArch64::STPSpre:
1528 case AArch64::STGPpre:
1529 case AArch64::STGPpost:
1537 case AArch64::LDPXpost:
1538 case AArch64::STPXpost:
1539 case AArch64::LDPSWpost:
1540 case AArch64::LDPXpre:
1541 case AArch64::STPXpre:
1542 case AArch64::LDPSWpre:
1543 case AArch64::STGPpre:
1544 case AArch64::STGPpost:
1545 NeedsDisjointWritebackTransfer =
true;
1547 case AArch64::LDNPXi:
1548 case AArch64::STNPXi:
1549 case AArch64::LDPXi:
1550 case AArch64::STPXi:
1551 case AArch64::LDPSWi:
1552 case AArch64::STGPi:
1556 case AArch64::LDPWpost:
1557 case AArch64::STPWpost:
1558 case AArch64::LDPWpre:
1559 case AArch64::STPWpre:
1560 NeedsDisjointWritebackTransfer =
true;
1562 case AArch64::LDNPWi:
1563 case AArch64::STNPWi:
1564 case AArch64::LDPWi:
1565 case AArch64::STPWi:
1569 case AArch64::LDNPQi:
1570 case AArch64::STNPQi:
1571 case AArch64::LDPQpost:
1572 case AArch64::STPQpost:
1573 case AArch64::LDPQi:
1574 case AArch64::STPQi:
1575 case AArch64::LDPQpre:
1576 case AArch64::STPQpre:
1580 case AArch64::LDNPDi:
1581 case AArch64::STNPDi:
1582 case AArch64::LDPDpost:
1583 case AArch64::STPDpost:
1584 case AArch64::LDPDi:
1585 case AArch64::STPDi:
1586 case AArch64::LDPDpre:
1587 case AArch64::STPDpre:
1591 case AArch64::LDNPSi:
1592 case AArch64::STNPSi:
1593 case AArch64::LDPSpost:
1594 case AArch64::STPSpost:
1595 case AArch64::LDPSi:
1596 case AArch64::STPSi:
1597 case AArch64::LDPSpre:
1598 case AArch64::STPSpre:
1608 if (IsLoad && Rt == Rt2)
1613 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1622 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1623 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1624 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1625 fieldFromInstruction(insn, 12, 9);
1626 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1631 case AArch64::LDRAAwriteback:
1632 case AArch64::LDRABwriteback:
1636 case AArch64::LDRAAindexed:
1637 case AArch64::LDRABindexed:
1643 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1645 if (writeback && Rt == Rn && Rn != 31) {
1655 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1656 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1657 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1658 unsigned extend = fieldFromInstruction(insn, 10, 6);
1660 unsigned shift = extend & 0x7;
1667 case AArch64::ADDWrx:
1668 case AArch64::SUBWrx:
1673 case AArch64::ADDSWrx:
1674 case AArch64::SUBSWrx:
1679 case AArch64::ADDXrx:
1680 case AArch64::SUBXrx:
1685 case AArch64::ADDSXrx:
1686 case AArch64::SUBSXrx:
1691 case AArch64::ADDXrx64:
1692 case AArch64::SUBXrx64:
1697 case AArch64::SUBSXrx64:
1698 case AArch64::ADDSXrx64:
1712 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1713 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1714 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1718 if (Inst.
getOpcode() == AArch64::ANDSXri)
1723 imm = fieldFromInstruction(insn, 10, 13);
1727 if (Inst.
getOpcode() == AArch64::ANDSWri)
1732 imm = fieldFromInstruction(insn, 10, 12);
1743 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1744 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1745 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1746 imm |= fieldFromInstruction(insn, 5, 5);
1758 case AArch64::MOVIv4i16:
1759 case AArch64::MOVIv8i16:
1760 case AArch64::MVNIv4i16:
1761 case AArch64::MVNIv8i16:
1762 case AArch64::MOVIv2i32:
1763 case AArch64::MOVIv4i32:
1764 case AArch64::MVNIv2i32:
1765 case AArch64::MVNIv4i32:
1768 case AArch64::MOVIv2s_msl:
1769 case AArch64::MOVIv4s_msl:
1770 case AArch64::MVNIv2s_msl:
1771 case AArch64::MVNIv4s_msl:
1782 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1783 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1784 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1785 imm |= fieldFromInstruction(insn, 5, 5);
1800 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1801 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1802 imm |= fieldFromInstruction(insn, 29, 2);
1805 if (imm & (1 << (21 - 1)))
1806 imm |= ~((1LL << 21) - 1);
1818 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1819 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1820 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1821 unsigned S = fieldFromInstruction(insn, 29, 1);
1822 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1824 unsigned ShifterVal = (Imm >> 12) & 3;
1825 unsigned ImmVal = Imm & 0xFFF;
1827 if (ShifterVal != 0 && ShifterVal != 1)
1853 int64_t imm = fieldFromInstruction(insn, 0, 26);
1856 if (imm & (1 << (26 - 1)))
1857 imm |= ~((1LL << 26) - 1);
1866 return Op1 == 0b000 && (Op2 == 0b000 ||
1874 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1875 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1876 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1877 uint64_t pstate_field = (op1 << 3) | op2;
1885 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1895 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1896 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1897 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1898 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1899 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1907 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1917 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1918 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1919 bit |= fieldFromInstruction(insn, 19, 5);
1920 int64_t dst = fieldFromInstruction(insn, 5, 14);
1923 if (dst & (1 << (14 - 1)))
1924 dst |= ~((1LL << 14) - 1);
1926 if (fieldFromInstruction(insn, 31, 1) == 0)
1945 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1954 AArch64::WSeqPairsClassRegClassID,
1955 RegNo,
Addr, Decoder);
1962 AArch64::XSeqPairsClassRegClassID,
1963 RegNo,
Addr, Decoder);
1969 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1970 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1971 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1972 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1973 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1989 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1990 unsigned imm = fieldFromInstruction(insn, 5, 13);
1996 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
2005 if (Imm & ~((1LL << Bits) - 1))
2009 if (Imm & (1 << (Bits - 1)))
2010 Imm |= ~((1LL << Bits) - 1);
2017template <
int ElementW
idth>
2020 unsigned Val = (uint8_t)Imm;
2021 unsigned Shift = (Imm & 0x100) ? 8 : 0;
2022 if (ElementWidth == 8 && Shift)
2039 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2049 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2050 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2051 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2055 if (Rd == Rs || Rs == Rn || Rd == Rn)
2074 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2075 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2076 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2080 if (Rd == Rm || Rm == Rn || Rd == Rn)
2100 unsigned Mask = 0x18;
2101 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2102 if ((Rt & Mask) == Mask)
2105 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2106 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2107 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2108 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2116 case AArch64::PRFMroW:
2119 case AArch64::PRFMroX:
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const MCPhysReg MatrixZATileDecoderTable[5][16]
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.