LLVM  9.0.0svn
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPU.h"
11 #include "SIRegisterInfo.h"
13 
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
17 
19  "Argument Register Usage Information Storage", false, true)
20 
22  const TargetRegisterInfo *TRI) const {
23  if (!isSet()) {
24  OS << "<not set>\n";
25  return;
26  }
27 
28  if (isRegister())
29  OS << "Reg " << printReg(getRegister(), TRI) << '\n';
30  else
31  OS << "Stack offset " << getStackOffset() << '\n';
32 }
33 
35 
36 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
37 
39  return false;
40 }
41 
43  ArgInfoMap.clear();
44  return false;
45 }
46 
48  for (const auto &FI : ArgInfoMap) {
49  OS << "Arguments for " << FI.first->getName() << '\n'
50  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
51  << " DispatchPtr: " << FI.second.DispatchPtr
52  << " QueuePtr: " << FI.second.QueuePtr
53  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
54  << " DispatchID: " << FI.second.DispatchID
55  << " FlatScratchInit: " << FI.second.FlatScratchInit
56  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
57  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
58  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
59  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
60  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
61  << " PrivateSegmentWaveByteOffset: "
62  << FI.second.PrivateSegmentWaveByteOffset
63  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
64  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
65  << " WorkItemIDX " << FI.second.WorkItemIDX
66  << " WorkItemIDY " << FI.second.WorkItemIDY
67  << " WorkItemIDZ " << FI.second.WorkItemIDZ
68  << '\n';
69  }
70 }
71 
72 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
75  switch (Value) {
77  return std::make_pair(
78  PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
79  &AMDGPU::SGPR_128RegClass);
80  }
82  return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
83  &AMDGPU::SGPR_64RegClass);
85  return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr,
86  &AMDGPU::SGPR_32RegClass);
87 
89  return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr,
90  &AMDGPU::SGPR_32RegClass);
92  return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
93  &AMDGPU::SGPR_32RegClass);
95  return std::make_pair(
96  PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
97  &AMDGPU::SGPR_32RegClass);
99  return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
100  &AMDGPU::SGPR_64RegClass);
102  return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
103  &AMDGPU::SGPR_64RegClass);
105  return std::make_pair(DispatchID ? &DispatchID : nullptr,
106  &AMDGPU::SGPR_64RegClass);
108  return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr,
109  &AMDGPU::SGPR_64RegClass);
111  return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr,
112  &AMDGPU::SGPR_64RegClass);
114  return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
115  &AMDGPU::SGPR_64RegClass);
117  return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr,
118  &AMDGPU::VGPR_32RegClass);
120  return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr,
121  &AMDGPU::VGPR_32RegClass);
123  return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr,
124  &AMDGPU::VGPR_32RegClass);
125  }
126  llvm_unreachable("unexpected preloaded value type");
127 }
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Interface definition for SIRegisterInfo.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
unsigned const TargetRegisterInfo * TRI
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
std::pair< const ArgDescriptor *, const TargetRegisterClass * > getPreloadedValue(PreloadedValue Value) const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
#define DEBUG_TYPE
aarch64 promote const
LLVM Value Representation.
Definition: Value.h:72
static int getStackOffset(const MachineFunction &MF, int FI)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...