LLVM  6.0.0svn
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPU.h"
12 #include "SIRegisterInfo.h"
14 
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
18 
20  "Argument Register Usage Information Storage", false, true)
21 
23  const TargetRegisterInfo *TRI) const {
24  if (!isSet()) {
25  OS << "<not set>\n";
26  return;
27  }
28 
29  if (isRegister())
30  OS << "Reg " << PrintReg(getRegister(), TRI) << '\n';
31  else
32  OS << "Stack offset " << getStackOffset() << '\n';
33 }
34 
36 
37 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
38 
40  return false;
41 }
42 
44  ArgInfoMap.clear();
45  return false;
46 }
47 
49  for (const auto &FI : ArgInfoMap) {
50  OS << "Arguments for " << FI.first->getName() << '\n'
51  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
52  << " DispatchPtr: " << FI.second.DispatchPtr
53  << " QueuePtr: " << FI.second.QueuePtr
54  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
55  << " DispatchID: " << FI.second.DispatchID
56  << " FlatScratchInit: " << FI.second.FlatScratchInit
57  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
58  << " GridWorkgroupCountX: " << FI.second.GridWorkGroupCountX
59  << " GridWorkgroupCountY: " << FI.second.GridWorkGroupCountY
60  << " GridWorkgroupCountZ: " << FI.second.GridWorkGroupCountZ
61  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
62  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
63  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
64  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
65  << " PrivateSegmentWaveByteOffset: "
66  << FI.second.PrivateSegmentWaveByteOffset
67  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
68  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
69  << " WorkItemIDX " << FI.second.WorkItemIDX
70  << " WorkItemIDY " << FI.second.WorkItemIDY
71  << " WorkItemIDZ " << FI.second.WorkItemIDZ
72  << '\n';
73  }
74 }
75 
76 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
79  switch (Value) {
81  return std::make_pair(
82  PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
83  &AMDGPU::SGPR_128RegClass);
84  }
86  return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
87  &AMDGPU::SGPR_64RegClass);
89  return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr,
90  &AMDGPU::SGPR_32RegClass);
91 
93  return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr,
94  &AMDGPU::SGPR_32RegClass);
96  return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
97  &AMDGPU::SGPR_32RegClass);
99  return std::make_pair(
100  PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
101  &AMDGPU::SGPR_32RegClass);
103  return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
104  &AMDGPU::SGPR_64RegClass);
106  return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
107  &AMDGPU::SGPR_64RegClass);
109  return std::make_pair(DispatchID ? &DispatchID : nullptr,
110  &AMDGPU::SGPR_64RegClass);
112  return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr,
113  &AMDGPU::SGPR_64RegClass);
115  return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr,
116  &AMDGPU::SGPR_64RegClass);
118  return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
119  &AMDGPU::SGPR_64RegClass);
121  return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr,
122  &AMDGPU::VGPR_32RegClass);
124  return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr,
125  &AMDGPU::VGPR_32RegClass);
127  return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr,
128  &AMDGPU::VGPR_32RegClass);
129  }
130  llvm_unreachable("unexpected preloaded value type");
131 }
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Interface definition for SIRegisterInfo.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
std::pair< const ArgDescriptor *, const TargetRegisterClass * > getPreloadedValue(PreloadedValue Value) const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
#define DEBUG_TYPE
aarch64 promote const
LLVM Value Representation.
Definition: Value.h:73
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...