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SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 private:
25  const GCNSubtarget *Subtarget;
26 
27 public:
29  CallingConv::ID CC,
30  EVT VT) const override;
32  CallingConv::ID CC,
33  EVT VT) const override;
34 
36  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
37  unsigned &NumIntermediates, MVT &RegisterVT) const override;
38 
39 private:
40  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
41  SDValue Chain, uint64_t Offset) const;
42  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
44  const SDLoc &SL, SDValue Chain,
45  uint64_t Offset, unsigned Align, bool Signed,
46  const ISD::InputArg *Arg = nullptr) const;
47 
48  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
49  const SDLoc &SL, SDValue Chain,
50  const ISD::InputArg &Arg) const;
51  SDValue getPreloadedValue(SelectionDAG &DAG,
52  const SIMachineFunctionInfo &MFI,
53  EVT VT,
55 
56  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
57  SelectionDAG &DAG) const override;
58  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
59  MVT VT, unsigned Offset) const;
60  SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
61  SelectionDAG &DAG) const;
62  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
63  SDValue GLC, SelectionDAG &DAG) const;
64 
65  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
66  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
67  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
68 
69  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
70  // (the offset that is included in bounds checking and swizzling, to be split
71  // between the instruction's voffset and immoffset fields) and soffset (the
72  // offset that is excluded from bounds checking and swizzling, to go in the
73  // instruction's soffset field). This function takes the first kind of
74  // offset and figures out how to split it between voffset and immoffset.
75  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
76  SelectionDAG &DAG) const;
77 
78  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
79  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
81  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
88  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
92 
93  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
95  bool IsIntrinsic = false) const;
96 
97  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
98 
99  /// Converts \p Op, which must be of floating point type, to the
100  /// floating point type \p VT, by either extending or truncating it.
101  SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
102  SDValue Op,
103  const SDLoc &DL,
104  EVT VT) const;
105 
106  SDValue convertArgType(
107  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
108  bool Signed, const ISD::InputArg *Arg = nullptr) const;
109 
110  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
111  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
112  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
113 
114  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
115  SelectionDAG &DAG) const;
116 
117  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
118  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
119  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
120  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
121  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
122  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
123 
124  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
125 
126  SDValue performUCharToFloatCombine(SDNode *N,
127  DAGCombinerInfo &DCI) const;
128  SDValue performSHLPtrCombine(SDNode *N,
129  unsigned AS,
130  EVT MemVT,
131  DAGCombinerInfo &DCI) const;
132 
133  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
134 
135  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
136  unsigned Opc, SDValue LHS,
137  const ConstantSDNode *CRHS) const;
138 
139  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
140  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
141  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
142  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
143  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
144  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
145  const APFloat &C) const;
146  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
147 
148  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
149  SDValue Op0, SDValue Op1) const;
150  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
151  SDValue Op0, SDValue Op1, bool Signed) const;
152  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
153  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
154  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
155  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
156  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
157 
158  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
159  unsigned getFusedOpcode(const SelectionDAG &DAG,
160  const SDNode *N0, const SDNode *N1) const;
161  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
162  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
163  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
164  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
165  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
166  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
167  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
168  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
169  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
170  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171 
172  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
173  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
174 
175  unsigned isCFIntrinsic(const SDNode *Intr) const;
176 
177  void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
178 
179  /// \returns True if fixup needs to be emitted for given global value \p GV,
180  /// false otherwise.
181  bool shouldEmitFixup(const GlobalValue *GV) const;
182 
183  /// \returns True if GOT relocation needs to be emitted for given global value
184  /// \p GV, false otherwise.
185  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
186 
187  /// \returns True if PC-relative relocation needs to be emitted for given
188  /// global value \p GV, false otherwise.
189  bool shouldEmitPCReloc(const GlobalValue *GV) const;
190 
191  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
192  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
193  // pointed to by Offsets.
194  void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
195  SDValue *Offsets, unsigned Align = 4) const;
196 
197 public:
198  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
199 
200  const GCNSubtarget *getSubtarget() const;
201 
202  bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
203 
204  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
205 
206  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
207  MachineFunction &MF,
208  unsigned IntrinsicID) const override;
209 
210  bool getAddrModeArguments(IntrinsicInst * /*I*/,
211  SmallVectorImpl<Value*> &/*Ops*/,
212  Type *&/*AccessTy*/) const override;
213 
214  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
215  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
216  unsigned AS,
217  Instruction *I = nullptr) const override;
218 
219  bool canMergeStoresTo(unsigned AS, EVT MemVT,
220  const SelectionDAG &DAG) const override;
221 
222  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
223  unsigned Align,
224  bool *IsFast) const override;
225 
226  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
227  unsigned SrcAlign, bool IsMemset,
228  bool ZeroMemset,
229  bool MemcpyStrSrc,
230  MachineFunction &MF) const override;
231 
232  bool isMemOpUniform(const SDNode *N) const;
233  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
234  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
235  bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
236 
238  getPreferredVectorAction(MVT VT) const override;
239 
241  Type *Ty) const override;
242 
243  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
244 
245  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
246 
247  bool supportSplitCSR(MachineFunction *MF) const override;
248  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
250  MachineBasicBlock *Entry,
251  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
252 
254  bool isVarArg,
256  const SDLoc &DL, SelectionDAG &DAG,
257  SmallVectorImpl<SDValue> &InVals) const override;
258 
259  bool CanLowerReturn(CallingConv::ID CallConv,
260  MachineFunction &MF, bool isVarArg,
262  LLVMContext &Context) const override;
263 
264  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
266  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
267  SelectionDAG &DAG) const override;
268 
269  void passSpecialInputs(
270  CallLoweringInfo &CLI,
271  CCState &CCInfo,
273  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
274  SmallVectorImpl<SDValue> &MemOpChains,
275  SDValue Chain) const;
276 
277  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
278  CallingConv::ID CallConv, bool isVarArg,
280  const SDLoc &DL, SelectionDAG &DAG,
281  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
282  SDValue ThisVal) const;
283 
284  bool mayBeEmittedAsTailCall(const CallInst *) const override;
285 
287  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
289  const SmallVectorImpl<SDValue> &OutVals,
290  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
291 
293  SmallVectorImpl<SDValue> &InVals) const override;
294 
295  unsigned getRegisterByName(const char* RegName, EVT VT,
296  SelectionDAG &DAG) const override;
297 
299  MachineBasicBlock *BB) const;
300 
303  MachineBasicBlock *BB) const override;
304 
305  bool hasBitPreservingFPLogic(EVT VT) const override;
306  bool enableAggressiveFMAFusion(EVT VT) const override;
307  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
308  EVT VT) const override;
309  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
310  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
313  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
314 
316  SelectionDAG &DAG) const override;
317 
318  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
319  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
321  SDNode *Node) const override;
322 
324 
326  SDValue Ptr) const;
327  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
328  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
329  std::pair<unsigned, const TargetRegisterClass *>
331  StringRef Constraint, MVT VT) const override;
332  ConstraintType getConstraintType(StringRef Constraint) const override;
333  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
334  SDValue V) const;
335 
336  void finalizeLowering(MachineFunction &MF) const override;
337 
339  KnownBits &Known,
340  const APInt &DemandedElts,
341  const SelectionDAG &DAG,
342  unsigned Depth = 0) const override;
343 
344  bool isSDNodeSourceOfDivergence(const SDNode *N,
345  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
346 
347  bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
348  unsigned MaxDepth = 5) const;
349  bool denormalsEnabledForType(EVT VT) const;
350 
352  const SelectionDAG &DAG,
353  bool SNaN = false,
354  unsigned Depth = 0) const override;
356 };
357 
358 } // End namespace llvm
359 
360 #endif
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
This class represents a function call, abstracting a target machine&#39;s calling convention.
const GCNSubtarget * getSubtarget() const
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1026
Function Alias Analysis Results
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isMemOpUniform(const SDNode *N) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned Intr
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const override
Insert explicit copies in entry and exit blocks.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const unsigned MaxDepth
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the &#39;Add TID&#39; bit enabled The TID (Thread ID) is multiplied by the ...
CCState - This class holds information needed while lowering arguments and return values...
bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Interface definition of the TargetLowering class that is common to all AMD GPUs.
CCValAssign - Represent assignment of one arg/retval to a location.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Representation of each machine instruction.
Definition: MachineInstr.h:63
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
uint32_t Size
Definition: Profile.cpp:46
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool denormalsEnabledForType(EVT VT) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void computeKnownBitsForFrameIndex(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class is used to represent ISD::LOAD nodes.