LLVM  6.0.0svn
AMDGPUInstrInfo.h
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1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
18 
19 #include "AMDGPU.h"
20 #include "Utils/AMDGPUBaseInfo.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "AMDGPUGenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AMDGPUSubtarget;
29 class MachineFunction;
30 class MachineInstr;
31 class MachineInstrBuilder;
32 
34 private:
35  const AMDGPUSubtarget &ST;
36 
37  virtual void anchor();
38 protected:
40 
41 public:
42  explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
43 
44  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
45  int64_t Offset1, int64_t Offset2,
46  unsigned NumLoads) const override;
47 
48  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
49  /// Return -1 if the target-specific opcode for the pseudo instruction does
50  /// not exist. If Opcode is not a pseudo instruction, this is identity.
51  int pseudoToMCOpcode(int Opcode) const;
52 
53  /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
54  /// equivalent opcode that writes \p Channels Channels.
55  int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
56 };
57 } // End llvm namespace
58 
59 #endif
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
AMDGPUInstrInfo(const AMDGPUSubtarget &st)
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:214
Represents one node in the SelectionDAG.
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...