LLVM  6.0.0svn
AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
33 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Function.h"
39 #include "llvm/Pass.h"
41 #include "llvm/Support/Compiler.h"
43 #include "llvm/Transforms/IPO.h"
46 #include "llvm/Transforms/Scalar.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
54  "r600-ir-structurize",
55  cl::desc("Use StructurizeCFG IR pass"),
56  cl::init(true));
57 
59  "amdgpu-sroa",
60  cl::desc("Run SROA after promote alloca pass"),
62  cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66  cl::desc("Run early if-conversion"),
67  cl::init(false));
68 
70  "r600-if-convert",
71  cl::desc("Use if conversion pass"),
73  cl::init(true));
74 
75 // Option to disable vectorizer for tests.
77  "amdgpu-load-store-vectorizer",
78  cl::desc("Enable load store vectorizer"),
79  cl::init(true),
80  cl::Hidden);
81 
82 // Option to to control global loads scalarization
84  "amdgpu-scalarize-global-loads",
85  cl::desc("Enable global load scalarization"),
86  cl::init(true),
87  cl::Hidden);
88 
89 // Option to run internalize pass.
91  "amdgpu-internalize-symbols",
92  cl::desc("Enable elimination of non-kernel functions and unused globals"),
93  cl::init(false),
94  cl::Hidden);
95 
96 // Option to inline all early.
98  "amdgpu-early-inline-all",
99  cl::desc("Inline all functions early"),
100  cl::init(false),
101  cl::Hidden);
102 
104  "amdgpu-sdwa-peephole",
105  cl::desc("Enable SDWA peepholer"),
106  cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110  cl::desc("Enable AMDGPU Alias Analysis"),
111  cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
115  "enable-si-insert-waitcnts",
116  cl::desc("Use new waitcnt insertion pass"),
117  cl::init(true));
118 
119 // Option to run late CFG structurizer
121  "amdgpu-late-structurize",
122  cl::desc("Enable late CFG structurization"),
124  cl::Hidden);
125 
127  "amdgpu-function-calls",
128  cl::Hidden,
129  cl::desc("Enable AMDGPU function call support"),
130  cl::init(false));
131 
132 // Enable lib calls simplifications
134  "amdgpu-simplify-libcall",
135  cl::desc("Enable mdgpu library simplifications"),
136  cl::init(true),
137  cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140  // Register the target
143 
184 }
185 
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187  return llvm::make_unique<AMDGPUTargetObjectFile>();
188 }
189 
191  return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
192 }
193 
195  return new SIScheduleDAGMI(C);
196 }
197 
198 static ScheduleDAGInstrs *
200  ScheduleDAGMILive *DAG =
201  new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
205  return DAG;
206 }
207 
208 static ScheduleDAGInstrs *
210  auto DAG = new GCNIterativeScheduler(C,
212  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
213  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
214  return DAG;
215 }
216 
218  return new GCNIterativeScheduler(C,
220 }
221 
222 static ScheduleDAGInstrs *
224  auto DAG = new GCNIterativeScheduler(C,
226  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
227  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
228  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
229  return DAG;
230 }
231 
233 R600SchedRegistry("r600", "Run R600's custom scheduler",
235 
237 SISchedRegistry("si", "Run SI's custom scheduler",
239 
241 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
242  "Run GCN scheduler to maximize occupancy",
244 
246 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
247  "Run GCN scheduler to maximize occupancy (experimental)",
249 
251 GCNMinRegSchedRegistry("gcn-minreg",
252  "Run GCN iterative scheduler for minimal register usage (experimental)",
254 
256 GCNILPSchedRegistry("gcn-ilp",
257  "Run GCN iterative scheduler for ILP scheduling (experimental)",
259 
260 static StringRef computeDataLayout(const Triple &TT) {
261  if (TT.getArch() == Triple::r600) {
262  // 32-bit pointers.
263  if (TT.getEnvironmentName() == "amdgiz" ||
264  TT.getEnvironmentName() == "amdgizcl")
265  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
266  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
267  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
268  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
269  }
270 
271  // 32-bit private, local, and region pointers. 64-bit global, constant and
272  // flat.
273  if (TT.getEnvironmentName() == "amdgiz" ||
274  TT.getEnvironmentName() == "amdgizcl")
275  return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
276  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
277  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
278  return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
279  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
280  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
281 }
282 
284 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
285  if (!GPU.empty())
286  return GPU;
287 
288  if (TT.getArch() == Triple::amdgcn)
289  return "generic";
290 
291  return "r600";
292 }
293 
295  // The AMDGPU toolchain only supports generating shared objects, so we
296  // must always use PIC.
297  return Reloc::PIC_;
298 }
299 
301  if (CM)
302  return *CM;
303  return CodeModel::Small;
304 }
305 
307  StringRef CPU, StringRef FS,
308  TargetOptions Options,
311  CodeGenOpt::Level OptLevel)
312  : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
313  FS, Options, getEffectiveRelocModel(RM),
314  getEffectiveCodeModel(CM), OptLevel),
315  TLOF(createTLOF(getTargetTriple())) {
316  AS = AMDGPU::getAMDGPUAS(TT);
317  initAsmInfo();
318 }
319 
321 
323 
325  Attribute GPUAttr = F.getFnAttribute("target-cpu");
326  return GPUAttr.hasAttribute(Attribute::None) ?
327  getTargetCPU() : GPUAttr.getValueAsString();
328 }
329 
331  Attribute FSAttr = F.getFnAttribute("target-features");
332 
333  return FSAttr.hasAttribute(Attribute::None) ?
335  FSAttr.getValueAsString();
336 }
337 
339  return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
340  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
341  AAR.addAAResult(WrapperPass->getResult());
342  });
343 }
344 
345 /// Predicate for Internalize pass.
346 static bool mustPreserveGV(const GlobalValue &GV) {
347  if (const Function *F = dyn_cast<Function>(&GV))
348  return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
349 
350  return !GV.use_empty();
351 }
352 
354  Builder.DivergentTarget = true;
355 
356  bool EnableOpt = getOptLevel() > CodeGenOpt::None;
357  bool Internalize = InternalizeSymbols;
358  bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
359  bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
360  bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
361 
363  delete Builder.Inliner;
365  }
366 
367  if (Internalize) {
368  // If we're generating code, we always have the whole program available. The
369  // relocations expected for externally visible functions aren't supported,
370  // so make sure every non-entry function is hidden.
371  Builder.addExtension(
375  });
376  }
377 
378  Builder.addExtension(
380  [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
382  if (AMDGPUAA) {
385  }
387  if (Internalize) {
389  PM.add(createGlobalDCEPass());
390  }
391  if (EarlyInline)
393  });
394 
395  const auto &Opt = Options;
396  Builder.addExtension(
398  [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
400  if (AMDGPUAA) {
403  }
405  if (LibCallSimplify)
407  });
408 
409  Builder.addExtension(
412  // Add infer address spaces pass to the opt pipeline after inlining
413  // but before SROA to increase SROA opportunities.
415  });
416 }
417 
418 //===----------------------------------------------------------------------===//
419 // R600 Target Machine (R600 -> Cayman)
420 //===----------------------------------------------------------------------===//
421 
423  StringRef CPU, StringRef FS,
427  CodeGenOpt::Level OL, bool JIT)
428  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
430 }
431 
433  const Function &F) const {
434  StringRef GPU = getGPUName(F);
435  StringRef FS = getFeatureString(F);
436 
437  SmallString<128> SubtargetKey(GPU);
438  SubtargetKey.append(FS);
439 
440  auto &I = SubtargetMap[SubtargetKey];
441  if (!I) {
442  // This needs to be done before we create a new subtarget since any
443  // creation will depend on the TM and the code generation flags on the
444  // function that reside in TargetOptions.
446  I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
447  }
448 
449  return I.get();
450 }
451 
452 //===----------------------------------------------------------------------===//
453 // GCN Target Machine (SI+)
454 //===----------------------------------------------------------------------===//
455 
457  StringRef CPU, StringRef FS,
461  CodeGenOpt::Level OL, bool JIT)
462  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
463 
465  StringRef GPU = getGPUName(F);
466  StringRef FS = getFeatureString(F);
467 
468  SmallString<128> SubtargetKey(GPU);
469  SubtargetKey.append(FS);
470 
471  auto &I = SubtargetMap[SubtargetKey];
472  if (!I) {
473  // This needs to be done before we create a new subtarget since any
474  // creation will depend on the TM and the code generation flags on the
475  // function that reside in TargetOptions.
477  I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
478  }
479 
480  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
481 
482  return I.get();
483 }
484 
485 //===----------------------------------------------------------------------===//
486 // AMDGPU Pass Setup
487 //===----------------------------------------------------------------------===//
488 
489 namespace {
490 
491 class AMDGPUPassConfig : public TargetPassConfig {
492 public:
493  AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
494  : TargetPassConfig(TM, PM) {
495  // Exceptions and StackMaps are not supported, so these passes will never do
496  // anything.
497  disablePass(&StackMapLivenessID);
498  disablePass(&FuncletLayoutID);
499  }
500 
501  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
502  return getTM<AMDGPUTargetMachine>();
503  }
504 
506  createMachineScheduler(MachineSchedContext *C) const override {
510  return DAG;
511  }
512 
513  void addEarlyCSEOrGVNPass();
514  void addStraightLineScalarOptimizationPasses();
515  void addIRPasses() override;
516  void addCodeGenPrepare() override;
517  bool addPreISel() override;
518  bool addInstSelector() override;
519  bool addGCPasses() override;
520 };
521 
522 class R600PassConfig final : public AMDGPUPassConfig {
523 public:
524  R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
525  : AMDGPUPassConfig(TM, PM) {}
526 
527  ScheduleDAGInstrs *createMachineScheduler(
528  MachineSchedContext *C) const override {
529  return createR600MachineScheduler(C);
530  }
531 
532  bool addPreISel() override;
533  bool addInstSelector() override;
534  void addPreRegAlloc() override;
535  void addPreSched2() override;
536  void addPreEmitPass() override;
537 };
538 
539 class GCNPassConfig final : public AMDGPUPassConfig {
540 public:
541  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
542  : AMDGPUPassConfig(TM, PM) {
543  // It is necessary to know the register usage of the entire call graph. We
544  // allow calls without EnableAMDGPUFunctionCalls if they are marked
545  // noinline, so this is always required.
546  setRequiresCodeGenSCCOrder(true);
547  }
548 
549  GCNTargetMachine &getGCNTargetMachine() const {
550  return getTM<GCNTargetMachine>();
551  }
552 
554  createMachineScheduler(MachineSchedContext *C) const override;
555 
556  bool addPreISel() override;
557  void addMachineSSAOptimization() override;
558  bool addILPOpts() override;
559  bool addInstSelector() override;
560  bool addIRTranslator() override;
561  bool addLegalizeMachineIR() override;
562  bool addRegBankSelect() override;
563  bool addGlobalInstructionSelect() override;
564  void addFastRegAlloc(FunctionPass *RegAllocPass) override;
565  void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
566  void addPreRegAlloc() override;
567  void addPostRegAlloc() override;
568  void addPreSched2() override;
569  void addPreEmitPass() override;
570 };
571 
572 } // end anonymous namespace
573 
575  return TargetIRAnalysis([this](const Function &F) {
576  return TargetTransformInfo(AMDGPUTTIImpl(this, F));
577  });
578 }
579 
580 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
582  addPass(createGVNPass());
583  else
584  addPass(createEarlyCSEPass());
585 }
586 
587 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
590  // ReassociateGEPs exposes more opportunites for SLSR. See
591  // the example in reassociate-geps-and-slsr.ll.
593  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
594  // EarlyCSE can reuse.
595  addEarlyCSEOrGVNPass();
596  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
597  addPass(createNaryReassociatePass());
598  // NaryReassociate on GEPs creates redundant common expressions, so run
599  // EarlyCSE after it.
600  addPass(createEarlyCSEPass());
601 }
602 
603 void AMDGPUPassConfig::addIRPasses() {
604  const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
605 
606  // There is no reason to run these.
607  disablePass(&StackMapLivenessID);
608  disablePass(&FuncletLayoutID);
609  disablePass(&PatchableFunctionID);
610 
612 
613  if (TM.getTargetTriple().getArch() == Triple::r600 ||
615  // Function calls are not supported, so make sure we inline everything.
616  addPass(createAMDGPUAlwaysInlinePass());
618  // We need to add the barrier noop pass, otherwise adding the function
619  // inlining pass will cause all of the PassConfigs passes to be run
620  // one function at a time, which means if we have a nodule with two
621  // functions, then we will generate code for the first function
622  // without ever running any passes on the second.
623  addPass(createBarrierNoopPass());
624  }
625 
626  if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
627  // TODO: May want to move later or split into an early and late one.
628 
630  }
631 
632  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
634 
635  // Replace OpenCL enqueued block function pointers with global variables.
637 
638  if (TM.getOptLevel() > CodeGenOpt::None) {
639  addPass(createInferAddressSpacesPass());
640  addPass(createAMDGPUPromoteAlloca());
641 
642  if (EnableSROA)
643  addPass(createSROAPass());
644 
645  addStraightLineScalarOptimizationPasses();
646 
648  addPass(createAMDGPUAAWrapperPass());
650  AAResults &AAR) {
651  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
652  AAR.addAAResult(WrapperPass->getResult());
653  }));
654  }
655  }
656 
658 
659  // EarlyCSE is not always strong enough to clean up what LSR produces. For
660  // example, GVN can combine
661  //
662  // %0 = add %a, %b
663  // %1 = add %b, %a
664  //
665  // and
666  //
667  // %0 = shl nsw %a, 2
668  // %1 = shl %a, 2
669  //
670  // but EarlyCSE can do neither of them.
671  if (getOptLevel() != CodeGenOpt::None)
672  addEarlyCSEOrGVNPass();
673 }
674 
675 void AMDGPUPassConfig::addCodeGenPrepare() {
677 
680 }
681 
682 bool AMDGPUPassConfig::addPreISel() {
683  addPass(createFlattenCFGPass());
684  return false;
685 }
686 
687 bool AMDGPUPassConfig::addInstSelector() {
688  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
689  return false;
690 }
691 
692 bool AMDGPUPassConfig::addGCPasses() {
693  // Do nothing. GC is not supported.
694  return false;
695 }
696 
697 //===----------------------------------------------------------------------===//
698 // R600 Pass Setup
699 //===----------------------------------------------------------------------===//
700 
701 bool R600PassConfig::addPreISel() {
702  AMDGPUPassConfig::addPreISel();
703 
705  addPass(createStructurizeCFGPass());
706  return false;
707 }
708 
709 bool R600PassConfig::addInstSelector() {
710  addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
711  return false;
712 }
713 
714 void R600PassConfig::addPreRegAlloc() {
715  addPass(createR600VectorRegMerger());
716 }
717 
718 void R600PassConfig::addPreSched2() {
719  addPass(createR600EmitClauseMarkers(), false);
721  addPass(&IfConverterID, false);
722  addPass(createR600ClauseMergePass(), false);
723 }
724 
725 void R600PassConfig::addPreEmitPass() {
726  addPass(createAMDGPUCFGStructurizerPass(), false);
727  addPass(createR600ExpandSpecialInstrsPass(), false);
728  addPass(&FinalizeMachineBundlesID, false);
729  addPass(createR600Packetizer(), false);
730  addPass(createR600ControlFlowFinalizer(), false);
731 }
732 
734  return new R600PassConfig(*this, PM);
735 }
736 
737 //===----------------------------------------------------------------------===//
738 // GCN Pass Setup
739 //===----------------------------------------------------------------------===//
740 
741 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
742  MachineSchedContext *C) const {
743  const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
744  if (ST.enableSIScheduler())
745  return createSIMachineScheduler(C);
747 }
748 
749 bool GCNPassConfig::addPreISel() {
750  AMDGPUPassConfig::addPreISel();
751 
752  // FIXME: We need to run a pass to propagate the attributes when calls are
753  // supported.
755 
756  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
757  // regions formed by them.
759  if (!LateCFGStructurize) {
760  addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
761  }
762  addPass(createSinkingPass());
764  if (!LateCFGStructurize) {
766  }
767 
768  return false;
769 }
770 
771 void GCNPassConfig::addMachineSSAOptimization() {
773 
774  // We want to fold operands after PeepholeOptimizer has run (or as part of
775  // it), because it will eliminate extra copies making it easier to fold the
776  // real source operand. We want to eliminate dead instructions after, so that
777  // we see fewer uses of the copies. We then need to clean up the dead
778  // instructions leftover after the operands are folded as well.
779  //
780  // XXX - Can we get away without running DeadMachineInstructionElim again?
781  addPass(&SIFoldOperandsID);
783  addPass(&SILoadStoreOptimizerID);
784  if (EnableSDWAPeephole) {
785  addPass(&SIPeepholeSDWAID);
786  addPass(&MachineLICMID);
787  addPass(&MachineCSEID);
788  addPass(&SIFoldOperandsID);
790  }
792 }
793 
794 bool GCNPassConfig::addILPOpts() {
796  addPass(&EarlyIfConverterID);
797 
799  return false;
800 }
801 
802 bool GCNPassConfig::addInstSelector() {
803  AMDGPUPassConfig::addInstSelector();
804  addPass(createSILowerI1CopiesPass());
805  addPass(&SIFixSGPRCopiesID);
806  return false;
807 }
808 
809 bool GCNPassConfig::addIRTranslator() {
810  addPass(new IRTranslator());
811  return false;
812 }
813 
814 bool GCNPassConfig::addLegalizeMachineIR() {
815  addPass(new Legalizer());
816  return false;
817 }
818 
819 bool GCNPassConfig::addRegBankSelect() {
820  addPass(new RegBankSelect());
821  return false;
822 }
823 
824 bool GCNPassConfig::addGlobalInstructionSelect() {
825  addPass(new InstructionSelect());
826  return false;
827 }
828 
829 void GCNPassConfig::addPreRegAlloc() {
830  if (LateCFGStructurize) {
832  }
833  addPass(createSIWholeQuadModePass());
834 }
835 
836 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
837  // FIXME: We have to disable the verifier here because of PHIElimination +
838  // TwoAddressInstructions disabling it.
839 
840  // This must be run immediately after phi elimination and before
841  // TwoAddressInstructions, otherwise the processing of the tied operand of
842  // SI_ELSE will introduce a copy of the tied operand source after the else.
843  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
844 
845  // This must be run after SILowerControlFlow, since it needs to use the
846  // machine-level CFG, but before register allocation.
847  insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
848 
849  TargetPassConfig::addFastRegAlloc(RegAllocPass);
850 }
851 
852 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
854 
855  // This must be run immediately after phi elimination and before
856  // TwoAddressInstructions, otherwise the processing of the tied operand of
857  // SI_ELSE will introduce a copy of the tied operand source after the else.
858  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
859 
860  // This must be run after SILowerControlFlow, since it needs to use the
861  // machine-level CFG, but before register allocation.
862  insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
863 
865 }
866 
867 void GCNPassConfig::addPostRegAlloc() {
868  addPass(&SIFixVGPRCopiesID);
869  addPass(&SIOptimizeExecMaskingID);
871 }
872 
873 void GCNPassConfig::addPreSched2() {
874 }
875 
876 void GCNPassConfig::addPreEmitPass() {
877  // The hazard recognizer that runs as part of the post-ra scheduler does not
878  // guarantee to be able handle all hazards correctly. This is because if there
879  // are multiple scheduling regions in a basic block, the regions are scheduled
880  // bottom up, so when we begin to schedule a region we don't know what
881  // instructions were emitted directly before it.
882  //
883  // Here we add a stand-alone hazard recognizer pass which can handle all
884  // cases.
885  addPass(&PostRAHazardRecognizerID);
886 
888  addPass(createSIInsertWaitcntsPass());
889  else
890  addPass(createSIInsertWaitsPass());
892  addPass(&SIInsertSkipsPassID);
893  addPass(createSIMemoryLegalizerPass());
895  addPass(&BranchRelaxationPassID);
896 }
897 
899  return new GCNPassConfig(*this, PM);
900 }
901 
FunctionPass * createSpeculativeExecutionPass()
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
FunctionPass * createStraightLineStrengthReducePass()
uint64_t CallInst * C
FunctionPass * createGVNPass(bool NoLoads=false)
Create a legacy GVN pass.
Definition: GVN.cpp:2648
StringRef getTargetFeatureString() const
Target & getTheGCNTarget()
The target for GCN GPUs.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine...
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void initializeSIFixVGPRCopiesPass(PassRegistry &)
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:76
char & SILoadStoreOptimizerID
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
char & SIPeepholeSDWAID
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
This file describes how to lower LLVM calls to machine code calls.
char & FuncletLayoutID
This pass lays out funclets contiguously.
AMDGPUAS getAMDGPUAS(const Module &M)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
Analysis pass providing the TargetTransformInfo.
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createAMDGPUCodeGenPreparePass()
F(f)
R600 Machine Scheduler interface.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
FunctionPass * createAMDGPUCFGStructurizerPass()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
FunctionPass * createSIMemoryLegalizerPass()
Pass * Inliner
Inliner - Specifies the inliner to use.
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
StringRef getFeatureString(const Function &F) const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
This file declares the targeting of the InstructionSelector class for AMDGPU.
Pass * createAMDGPUFunctionInliningPass()
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
const AMDGPUSubtarget * getSubtargetImpl() const
This file declares the AMDGPU-specific subclass of TargetLoweringObjectFile.
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
This file contains the simple types necessary to represent the attributes associated with functions a...
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
No attributes have been set.
Definition: Attributes.h:72
void initializeAMDGPUInlinerPass(PassRegistry &)
FunctionPass * createSinkingPass()
Definition: Sink.cpp:306
static MachineSchedRegistry GCNILPSchedRegistry("gcn-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
char & SIOptimizeExecMaskingPreRAID
EP_ModuleOptimizerEarly - This extension point allows adding passes just before the main module-level...
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier, e.g.
Target-Independent Code Generator Pass Configuration Options.
static StringRef computeDataLayout(const Triple &TT)
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
EP_EnabledOnOptLevel0 - This extension point allows adding passes that should not be disabled by O0 o...
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
FunctionPass * createR600ExpandSpecialInstrsPass()
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
Pass * createLoadStoreVectorizerPass()
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
StringRef getTargetCPU() const
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
ModulePass * createGlobalDCEPass()
createGlobalDCEPass - This transform is designed to eliminate unreachable internal globals (functions...
FunctionPass * createR600VectorRegMerger()
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
SI Machine Scheduler interface.
StringRef getGPUName(const Function &F) const
void append(in_iter S, in_iter E)
Append from an iterator pair.
Definition: SmallString.h:75
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
FunctionPass * createSIDebuggerInsertNopsPass()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
FunctionPass * createFlattenCFGPass()
FunctionPass * createSIWholeQuadModePass()
This file provides the interface for LLVM&#39;s Global Value Numbering pass which eliminates fully redund...
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
char & SIInsertSkipsPassID
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
bool isEntryFunctionCC(CallingConv::ID CC)
void LLVMInitializeAMDGPUTarget()
void initializeSIPeepholeSDWAPass(PassRegistry &)
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createR600ControlFlowFinalizer()
char & SIFixWWMLivenessID
static cl::opt< bool > EnableAMDGPUFunctionCalls("amdgpu-function-calls", cl::Hidden, cl::desc("Enable AMDGPU function call support"), cl::init(false))
Legacy wrapper pass to provide the AMDGPUAAResult object.
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
const Triple & getTargetTriple() const
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
void initializeSILowerControlFlowPass(PassRegistry &)
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
ModulePass * createAMDGPULowerIntrinsicsPass()
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createR600ClauseMergePass()
The AMDGPU TargetMachine interface definition for hw codgen targets.
static cl::opt< bool > EnableR600IfConvert("r600-if-convert", cl::desc("Use if conversion pass"), cl::ReallyHidden, cl::init(true))
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
static ScheduleDAGInstrs * createR600MachineScheduler(MachineSchedContext *C)
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable mdgpu library simplifications"), cl::init(true), cl::Hidden)
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
Analysis pass providing a never-invalidated alias analysis result.
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations, allowing them to see the code as it is coming out of the frontend.
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
void initializeSIInsertSkipsPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createAMDGPUAnnotateUniformValues()
This is the AMGPU address space based alias analysis pass.
Provides passes to inlining "always_inline" functions.
char & SIOptimizeExecMaskingID
EP_CGSCCOptimizerLate - This extension point allows adding CallGraphSCC passes at the end of the main...
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIFixWWMLivenessPass(PassRegistry &)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
void initializeSIMemoryLegalizerPass(PassRegistry &)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
ModulePass * createInternalizePass(std::function< bool(const GlobalValue &)> MustPreserveGV)
createInternalizePass - This pass loops over all of the functions in the input module, internalizing all globals (functions and variables) it can.
void initializeSIWholeQuadModePass(PassRegistry &)
void setRequiresStructuredCFG(bool Value)
void initializeR600VectorRegMergerPass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
static cl::opt< bool > EnableSIInsertWaitcntsPass("enable-si-insert-waitcnts", cl::desc("Use new waitcnt insertion pass"), cl::init(true))
FunctionPass * createR600EmitClauseMarkers()
void initializeR600ClauseMergePassPass(PassRegistry &)
StringRef getEnvironmentName() const
getEnvironmentName - Get the optional environment (fourth) component of the triple, or "" if empty.
Definition: Triple.cpp:955
This pass is responsible for selecting generic machine instructions to target-specific instructions...
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
Target - Wrapper for Target specific information.
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
This file declares the targeting of the Machinelegalizer class for AMDGPU.
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
FunctionPass * createInferAddressSpacesPass()
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:569
FunctionPass * createSIShrinkInstructionsPass()
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
void initializeSIDebuggerInsertNopsPass(PassRegistry &)
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
TargetOptions Options
Definition: TargetMachine.h:96
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
#define LLVM_READNONE
Definition: Compiler.h:161
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
char & SIFixSGPRCopiesID
void initializeSIInsertWaitsPass(PassRegistry &)
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &)
FunctionPass * createSROAPass()
Definition: SROA.cpp:4389
bool enableSIScheduler() const
static MachineSchedRegistry R600SchedRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler)
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:568
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
FunctionPass * createSIInsertWaitsPass()
This file declares the IRTranslator pass.
FunctionPass * createAMDGPUUseNativeCallsPass()
char & PostRAHazardRecognizerID
createPostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:270
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1140
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
void initializeSILowerI1CopiesPass(PassRegistry &)
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLImageTypeLoweringPass()
static cl::opt< bool > EnableR600StructurizeCFG("r600-ir-structurize", cl::desc("Use StructurizeCFG IR pass"), cl::init(true))
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
static ImmutablePass * createAMDGPUExternalAAWrapperPass()
bool use_empty() const
Definition: Value.h:328
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:422
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
FunctionPass * createNaryReassociatePass()