LLVM  7.0.0svn
AMDGPU.h
Go to the documentation of this file.
1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 
15 
16 namespace llvm {
17 
18 class AMDGPUTargetMachine;
19 class FunctionPass;
20 class GCNTargetMachine;
21 class ModulePass;
22 class Pass;
23 class Target;
24 class TargetMachine;
25 class TargetOptions;
26 class PassRegistry;
27 class Module;
28 
29 // R600 Passes
30 FunctionPass *createR600VectorRegMerger();
31 FunctionPass *createR600ExpandSpecialInstrsPass();
32 FunctionPass *createR600EmitClauseMarkers();
33 FunctionPass *createR600ClauseMergePass();
34 FunctionPass *createR600Packetizer();
35 FunctionPass *createR600ControlFlowFinalizer();
36 FunctionPass *createAMDGPUCFGStructurizerPass();
37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
38 
39 // SI Passes
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSIPeepholeSDWAPass();
43 FunctionPass *createSILowerI1CopiesPass();
44 FunctionPass *createSIShrinkInstructionsPass();
45 FunctionPass *createSILoadStoreOptimizerPass();
46 FunctionPass *createSIWholeQuadModePass();
49 FunctionPass *createSIFixSGPRCopiesPass();
50 FunctionPass *createSIMemoryLegalizerPass();
51 FunctionPass *createSIDebuggerInsertNopsPass();
52 FunctionPass *createSIInsertWaitcntsPass();
53 FunctionPass *createSIFixWWMLivenessPass();
54 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
55 FunctionPass *createAMDGPUUseNativeCallsPass();
56 FunctionPass *createAMDGPUCodeGenPreparePass();
59 
60 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
61 
64 
65 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
66 
70 
72 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
73 extern char &AMDGPULowerIntrinsicsID;
74 
78 
79 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
80 extern char &AMDGPURewriteOutArgumentsID;
81 
82 void initializeR600ClauseMergePassPass(PassRegistry &);
83 extern char &R600ClauseMergePassID;
84 
85 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
86 extern char &R600ControlFlowFinalizerID;
87 
90 
91 void initializeR600VectorRegMergerPass(PassRegistry &);
92 extern char &R600VectorRegMergerID;
93 
94 void initializeR600PacketizerPass(PassRegistry &);
95 extern char &R600PacketizerID;
96 
97 void initializeSIFoldOperandsPass(PassRegistry &);
98 extern char &SIFoldOperandsID;
99 
100 void initializeSIPeepholeSDWAPass(PassRegistry &);
101 extern char &SIPeepholeSDWAID;
102 
103 void initializeSIShrinkInstructionsPass(PassRegistry&);
104 extern char &SIShrinkInstructionsID;
105 
106 void initializeSIFixSGPRCopiesPass(PassRegistry &);
107 extern char &SIFixSGPRCopiesID;
108 
109 void initializeSIFixVGPRCopiesPass(PassRegistry &);
110 extern char &SIFixVGPRCopiesID;
111 
112 void initializeSILowerI1CopiesPass(PassRegistry &);
113 extern char &SILowerI1CopiesID;
114 
115 void initializeSILoadStoreOptimizerPass(PassRegistry &);
116 extern char &SILoadStoreOptimizerID;
117 
118 void initializeSIWholeQuadModePass(PassRegistry &);
119 extern char &SIWholeQuadModeID;
120 
121 void initializeSILowerControlFlowPass(PassRegistry &);
122 extern char &SILowerControlFlowID;
123 
124 void initializeSIInsertSkipsPass(PassRegistry &);
125 extern char &SIInsertSkipsPassID;
126 
127 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
128 extern char &SIOptimizeExecMaskingID;
129 
130 void initializeSIFixWWMLivenessPass(PassRegistry &);
131 extern char &SIFixWWMLivenessID;
132 
133 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
134 extern char &AMDGPUSimplifyLibCallsID;
135 
136 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
137 extern char &AMDGPUUseNativeCallsID;
138 
139 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
140 extern char &AMDGPUPerfHintAnalysisID;
141 
142 // Passes common to R600 and SI
143 FunctionPass *createAMDGPUPromoteAlloca();
144 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
145 extern char &AMDGPUPromoteAllocaID;
146 
148 FunctionPass *createAMDGPUISelDag(
149  TargetMachine *TM = nullptr,
151 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
153 FunctionPass *createAMDGPUAnnotateUniformValues();
154 
155 ModulePass* createAMDGPUUnifyMetadataPass();
156 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
157 extern char &AMDGPUUnifyMetadataID;
158 
159 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
160 extern char &SIOptimizeExecMaskingPreRAID;
161 
164 
165 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
166 extern char &AMDGPUCodeGenPrepareID;
167 
168 void initializeSIAnnotateControlFlowPass(PassRegistry&);
169 extern char &SIAnnotateControlFlowPassID;
170 
171 void initializeSIMemoryLegalizerPass(PassRegistry&);
172 extern char &SIMemoryLegalizerID;
173 
174 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
175 extern char &SIDebuggerInsertNopsID;
176 
177 void initializeSIInsertWaitcntsPass(PassRegistry&);
178 extern char &SIInsertWaitcntsID;
179 
182 
183 ImmutablePass *createAMDGPUAAWrapperPass();
184 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
185 
186 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
187 
189 void initializeAMDGPUInlinerPass(PassRegistry&);
190 
194 
195 Target &getTheAMDGPUTarget();
196 Target &getTheGCNTarget();
197 
198 namespace AMDGPU {
205 };
206 }
207 
208 } // End namespace llvm
209 
210 /// OpenCL uses address spaces to differentiate between
211 /// various memory regions on the hardware. On the CPU
212 /// all of the address spaces point to the same memory,
213 /// however on the GPU, each address space points to
214 /// a separate piece of memory that is unique from other
215 /// memory locations.
216 struct AMDGPUAS {
217  // The following address space values depend on the triple environment.
218  unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
219  unsigned FLAT_ADDRESS; ///< Address space for flat memory.
220  unsigned REGION_ADDRESS; ///< Address space for region memory.
221 
222  enum : unsigned {
223  // The maximum value for flat, generic, local, private, constant and region.
224  MAX_COMMON_ADDRESS = 5,
225 
226  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
227  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
228  LOCAL_ADDRESS = 3, ///< Address space for local memory.
229 
230  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
231 
232  /// Address space for direct addressible parameter memory (CONST0)
233  PARAM_D_ADDRESS = 6,
234  /// Address space for indirect addressible parameter memory (VTX1)
235  PARAM_I_ADDRESS = 7,
236 
237  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
238  // this order to be able to dynamically index a constant buffer, for
239  // example:
240  //
241  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
242 
243  CONSTANT_BUFFER_0 = 8,
244  CONSTANT_BUFFER_1 = 9,
245  CONSTANT_BUFFER_2 = 10,
246  CONSTANT_BUFFER_3 = 11,
247  CONSTANT_BUFFER_4 = 12,
248  CONSTANT_BUFFER_5 = 13,
249  CONSTANT_BUFFER_6 = 14,
250  CONSTANT_BUFFER_7 = 15,
251  CONSTANT_BUFFER_8 = 16,
252  CONSTANT_BUFFER_9 = 17,
253  CONSTANT_BUFFER_10 = 18,
254  CONSTANT_BUFFER_11 = 19,
255  CONSTANT_BUFFER_12 = 20,
256  CONSTANT_BUFFER_13 = 21,
257  CONSTANT_BUFFER_14 = 22,
258  CONSTANT_BUFFER_15 = 23,
259 
260  // Some places use this if the address space can't be determined.
261  UNKNOWN_ADDRESS_SPACE = ~0u,
262  };
263 };
264 
265 namespace llvm {
266 namespace AMDGPU {
267 AMDGPUAS getAMDGPUAS(const Module &M);
268 AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
269 AMDGPUAS getAMDGPUAS(Triple T);
270 } // namespace AMDGPU
271 } // namespace llvm
272 
273 #endif
Pass * createAMDGPUStructurizeCFGPass()
Target & getTheGCNTarget()
The target for GCN GPUs.
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
char & SIShrinkInstructionsID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPULowerKernelAttributesID
ModulePass * createR600OpenCLImageTypeLoweringPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
char & SILoadStoreOptimizerID
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
char & SIPeepholeSDWAID
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
AMDGPUAS getAMDGPUAS(const Module &M)
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
char & AMDGPUOpenCLEnqueuedBlockLoweringID
FunctionPass * createAMDGPUPromoteAlloca()
ModulePass * createAMDGPULowerKernelAttributesPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
FunctionPass * createAMDGPUCFGStructurizerPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
FunctionPass * createSIMemoryLegalizerPass()
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
char & AMDGPURewriteOutArgumentsID
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:216
Pass * createAMDGPUFunctionInliningPass()
char & AMDGPUUnifyMetadataID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
void initializeAMDGPUInlinerPass(PassRegistry &)
char & SIOptimizeExecMaskingPreRAID
char & R600ControlFlowFinalizerID
FunctionPass * createR600ExpandSpecialInstrsPass()
char & R600PacketizerID
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
char & SILowerI1CopiesID
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createR600VectorRegMerger()
char & R600ExpandSpecialInstrsPassID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIDebuggerInsertNopsPass()
FunctionPass * createSIWholeQuadModePass()
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & AMDGPUUseNativeCallsID
char & SIInsertSkipsPassID
void initializeSIPeepholeSDWAPass(PassRegistry &)
char & AMDGPUAnnotateKernelFeaturesID
char & AMDGPUPerfHintAnalysisID
FunctionPass * createR600ControlFlowFinalizer()
char & SIFixWWMLivenessID
void initializeSILowerControlFlowPass(PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
ModulePass * createAMDGPULowerIntrinsicsPass()
FunctionPass * createR600ClauseMergePass()
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
unsigned REGION_ADDRESS
Address space for region memory.
Definition: AMDGPU.h:220
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeSIInsertSkipsPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIOptimizeExecMaskingID
FunctionPass * createSIFixWWMLivenessPass()
char & SIInsertWaitcntsID
print lazy value Lazy Value Info Printer Pass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIFixWWMLivenessPass(PassRegistry &)
void initializeSIMemoryLegalizerPass(PassRegistry &)
void initializeSIWholeQuadModePass(PassRegistry &)
void initializeR600VectorRegMergerPass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
char & SIMemoryLegalizerID
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
FunctionPass * createR600EmitClauseMarkers()
void initializeR600ClauseMergePassPass(PassRegistry &)
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesPass()
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
char & AMDGPUSimplifyLibCallsID
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createSIShrinkInstructionsPass()
void initializeSIDebuggerInsertNopsPass(PassRegistry &)
FunctionPass * createSIFoldOperandsPass()
unsigned FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:219
char & SIFixSGPRCopiesID
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &)
char & AMDGPUMachineCFGStructurizerID
char & AMDGPULowerIntrinsicsID
FunctionPass * createSILoadStoreOptimizerPass()
FunctionPass * createAMDGPUUseNativeCallsPass()
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SIDebuggerInsertNopsID
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
unsigned PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:218
char & R600ClauseMergePassID