LLVM  9.0.0svn
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
14 
15 namespace llvm {
16 
17 class AMDGPUTargetMachine;
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ModulePass;
21 class Pass;
22 class Target;
23 class TargetMachine;
24 class TargetOptions;
25 class PassRegistry;
26 class Module;
27 
28 // R600 Passes
29 FunctionPass *createR600VectorRegMerger();
30 FunctionPass *createR600ExpandSpecialInstrsPass();
31 FunctionPass *createR600EmitClauseMarkers();
32 FunctionPass *createR600ClauseMergePass();
33 FunctionPass *createR600Packetizer();
34 FunctionPass *createR600ControlFlowFinalizer();
35 FunctionPass *createAMDGPUCFGStructurizerPass();
36 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
37 
38 // SI Passes
39 FunctionPass *createGCNDPPCombinePass();
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSIPeepholeSDWAPass();
43 FunctionPass *createSILowerI1CopiesPass();
44 FunctionPass *createSIFixupVectorISelPass();
45 FunctionPass *createSIAddIMGInitPass();
46 FunctionPass *createSIShrinkInstructionsPass();
47 FunctionPass *createSILoadStoreOptimizerPass();
48 FunctionPass *createSIWholeQuadModePass();
51 FunctionPass *createSIFixSGPRCopiesPass();
52 FunctionPass *createSIMemoryLegalizerPass();
53 FunctionPass *createSIInsertWaitcntsPass();
54 FunctionPass *createSIPreAllocateWWMRegsPass();
55 FunctionPass *createSIFormMemoryClausesPass();
56 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
57 FunctionPass *createAMDGPUUseNativeCallsPass();
58 FunctionPass *createAMDGPUCodeGenPreparePass();
61 FunctionPass *createSIModeRegisterPass();
62 
63 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
64 
67 
68 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
69 
73 
74 FunctionPass *createAMDGPUAtomicOptimizerPass();
75 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
76 extern char &AMDGPUAtomicOptimizerID;
77 
79 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
80 extern char &AMDGPULowerIntrinsicsID;
81 
83 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
84 extern char &AMDGPUFixFunctionBitcastsID;
85 
87 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
88 extern char &AMDGPULowerKernelArgumentsID;
89 
93 
94 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
95 extern char &AMDGPURewriteOutArgumentsID;
96 
97 void initializeGCNDPPCombinePass(PassRegistry &);
98 extern char &GCNDPPCombineID;
99 
100 void initializeR600ClauseMergePassPass(PassRegistry &);
101 extern char &R600ClauseMergePassID;
102 
103 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
104 extern char &R600ControlFlowFinalizerID;
105 
106 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
107 extern char &R600ExpandSpecialInstrsPassID;
108 
109 void initializeR600VectorRegMergerPass(PassRegistry &);
110 extern char &R600VectorRegMergerID;
111 
112 void initializeR600PacketizerPass(PassRegistry &);
113 extern char &R600PacketizerID;
114 
115 void initializeSIFoldOperandsPass(PassRegistry &);
116 extern char &SIFoldOperandsID;
117 
118 void initializeSIPeepholeSDWAPass(PassRegistry &);
119 extern char &SIPeepholeSDWAID;
120 
121 void initializeSIShrinkInstructionsPass(PassRegistry&);
122 extern char &SIShrinkInstructionsID;
123 
124 void initializeSIFixSGPRCopiesPass(PassRegistry &);
125 extern char &SIFixSGPRCopiesID;
126 
127 void initializeSIFixVGPRCopiesPass(PassRegistry &);
128 extern char &SIFixVGPRCopiesID;
129 
130 void initializeSIFixupVectorISelPass(PassRegistry &);
131 extern char &SIFixupVectorISelID;
132 
133 void initializeSILowerI1CopiesPass(PassRegistry &);
134 extern char &SILowerI1CopiesID;
135 
136 void initializeSILoadStoreOptimizerPass(PassRegistry &);
137 extern char &SILoadStoreOptimizerID;
138 
139 void initializeSIWholeQuadModePass(PassRegistry &);
140 extern char &SIWholeQuadModeID;
141 
142 void initializeSILowerControlFlowPass(PassRegistry &);
143 extern char &SILowerControlFlowID;
144 
145 void initializeSIInsertSkipsPass(PassRegistry &);
146 extern char &SIInsertSkipsPassID;
147 
148 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
149 extern char &SIOptimizeExecMaskingID;
150 
151 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
152 extern char &SIPreAllocateWWMRegsID;
153 
154 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
155 extern char &AMDGPUSimplifyLibCallsID;
156 
157 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
158 extern char &AMDGPUUseNativeCallsID;
159 
160 void initializeSIAddIMGInitPass(PassRegistry &);
161 extern char &SIAddIMGInitID;
162 
163 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
164 extern char &AMDGPUPerfHintAnalysisID;
165 
166 // Passes common to R600 and SI
167 FunctionPass *createAMDGPUPromoteAlloca();
168 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
169 extern char &AMDGPUPromoteAllocaID;
170 
172 FunctionPass *createAMDGPUISelDag(
173  TargetMachine *TM = nullptr,
175 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
177 FunctionPass *createAMDGPUAnnotateUniformValues();
178 
179 ModulePass* createAMDGPUUnifyMetadataPass();
180 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
181 extern char &AMDGPUUnifyMetadataID;
182 
183 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
184 extern char &SIOptimizeExecMaskingPreRAID;
185 
188 
189 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
190 extern char &AMDGPUCodeGenPrepareID;
191 
192 void initializeSIAnnotateControlFlowPass(PassRegistry&);
193 extern char &SIAnnotateControlFlowPassID;
194 
195 void initializeSIMemoryLegalizerPass(PassRegistry&);
196 extern char &SIMemoryLegalizerID;
197 
198 void initializeSIModeRegisterPass(PassRegistry&);
199 extern char &SIModeRegisterID;
200 
201 void initializeSIInsertWaitcntsPass(PassRegistry&);
202 extern char &SIInsertWaitcntsID;
203 
204 void initializeSIFormMemoryClausesPass(PassRegistry&);
205 extern char &SIFormMemoryClausesID;
206 
209 
210 ImmutablePass *createAMDGPUAAWrapperPass();
211 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
212 ImmutablePass *createAMDGPUExternalAAWrapperPass();
213 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
214 
215 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
216 
218 void initializeAMDGPUInlinerPass(PassRegistry&);
219 
223 
224 void initializeGCNRegBankReassignPass(PassRegistry &);
225 extern char &GCNRegBankReassignID;
226 
227 void initializeGCNNSAReassignPass(PassRegistry &);
228 extern char &GCNNSAReassignID;
229 
230 namespace AMDGPU {
237 };
238 }
239 
240 } // End namespace llvm
241 
242 /// OpenCL uses address spaces to differentiate between
243 /// various memory regions on the hardware. On the CPU
244 /// all of the address spaces point to the same memory,
245 /// however on the GPU, each address space points to
246 /// a separate piece of memory that is unique from other
247 /// memory locations.
248 namespace AMDGPUAS {
249  enum : unsigned {
250  // The maximum value for flat, generic, local, private, constant and region.
252 
253  FLAT_ADDRESS = 0, ///< Address space for flat memory.
254  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
255  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
256 
257  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
258  LOCAL_ADDRESS = 3, ///< Address space for local memory.
259  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
260 
261  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
262 
263  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
264 
265  /// Address space for direct addressible parameter memory (CONST0).
267  /// Address space for indirect addressible parameter memory (VTX1).
269 
270  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
271  // this order to be able to dynamically index a constant buffer, for
272  // example:
273  //
274  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
275 
292 
293  // Some places use this if the address space can't be determined.
295  };
296 }
297 
298 #endif
char & SIFormMemoryClausesID
Pass * createAMDGPUStructurizeCFGPass()
Address space for indirect addressible parameter memory (VTX1).
Definition: AMDGPU.h:268
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Address space for flat memory.
Definition: AMDGPU.h:253
FunctionPass * createSIPeepholeSDWAPass()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createSIFormMemoryClausesPass()
char & SIShrinkInstructionsID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPULowerKernelAttributesID
char & GCNNSAReassignID
void initializeSIFormMemoryClausesPass(PassRegistry &)
ModulePass * createR600OpenCLImageTypeLoweringPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & SILoadStoreOptimizerID
char & SIPeepholeSDWAID
void initializeSIModeRegisterPass(PassRegistry &)
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:254
char & AMDGPUOpenCLEnqueuedBlockLoweringID
FunctionPass * createAMDGPUPromoteAlloca()
ModulePass * createAMDGPULowerKernelAttributesPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
char & SIFixupVectorISelID
FunctionPass * createAMDGPUCFGStructurizerPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
FunctionPass * createSIAddIMGInitPass()
FunctionPass * createSIMemoryLegalizerPass()
Address space for local memory.
Definition: AMDGPU.h:258
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
char & AMDGPUAtomicOptimizerID
char & AMDGPURewriteOutArgumentsID
Pass * createAMDGPUFunctionInliningPass()
char & AMDGPUUnifyMetadataID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeAMDGPUInlinerPass(PassRegistry &)
char & SIOptimizeExecMaskingPreRAID
char & R600ControlFlowFinalizerID
FunctionPass * createR600ExpandSpecialInstrsPass()
FunctionPass * createSIFixupVectorISelPass()
char & R600PacketizerID
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createR600VectorRegMerger()
Address space for region memory. (GDS)
Definition: AMDGPU.h:255
void initializeSIFixupVectorISelPass(PassRegistry &)
char & R600ExpandSpecialInstrsPassID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
char & GCNDPPCombineID
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUAnnotateUniformValuesPassID
Address space for direct addressible parameter memory (CONST0).
Definition: AMDGPU.h:266
FunctionPass * createSIWholeQuadModePass()
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & AMDGPUUseNativeCallsID
FunctionPass * createGCNDPPCombinePass()
char & SIInsertSkipsPassID
void initializeSIPeepholeSDWAPass(PassRegistry &)
Address space for 32-bit constant memory.
Definition: AMDGPU.h:261
char & AMDGPUAnnotateKernelFeaturesID
char & AMDGPUPerfHintAnalysisID
FunctionPass * createR600ControlFlowFinalizer()
void initializeSILowerControlFlowPass(PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
ModulePass * createAMDGPULowerIntrinsicsPass()
FunctionPass * createSIModeRegisterPass()
FunctionPass * createR600ClauseMergePass()
char & SILowerI1CopiesID
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeSIAddIMGInitPass(PassRegistry &)
Address space for constant memory (VTX2).
Definition: AMDGPU.h:257
void initializeSIInsertSkipsPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIOptimizeExecMaskingID
void initializeGCNRegBankReassignPass(PassRegistry &)
char & SIInsertWaitcntsID
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:263
print lazy value Lazy Value Info Printer Pass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIMemoryLegalizerPass(PassRegistry &)
FunctionPass * createSIPreAllocateWWMRegsPass()
char & SIPreAllocateWWMRegsID
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPUAtomicOptimizerPass()
void initializeR600VectorRegMergerPass(PassRegistry &)
char & SIMemoryLegalizerID
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:248
void initializeGCNDPPCombinePass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createR600EmitClauseMarkers()
void initializeR600ClauseMergePassPass(PassRegistry &)
ModulePass * createAMDGPUFixFunctionBitcastsPass()
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesPass()
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
char & SIModeRegisterID
char & AMDGPUSimplifyLibCallsID
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createSIShrinkInstructionsPass()
FunctionPass * createSIFoldOperandsPass()
char & SIFixSGPRCopiesID
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &)
char & AMDGPUMachineCFGStructurizerID
Address space for private memory.
Definition: AMDGPU.h:259
ImmutablePass * createAMDGPUExternalAAWrapperPass()
char & AMDGPULowerIntrinsicsID
char & GCNRegBankReassignID
FunctionPass * createSILoadStoreOptimizerPass()
FunctionPass * createAMDGPUUseNativeCallsPass()
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
char & AMDGPUFixFunctionBitcastsID
char & SIAddIMGInitID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
char & R600ClauseMergePassID