LLVM  8.0.0svn
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 
15 
16 namespace llvm {
17 
18 class AMDGPUTargetMachine;
19 class FunctionPass;
20 class GCNTargetMachine;
21 class ModulePass;
22 class Pass;
23 class Target;
24 class TargetMachine;
25 class TargetOptions;
26 class PassRegistry;
27 class Module;
28 
29 // R600 Passes
30 FunctionPass *createR600VectorRegMerger();
31 FunctionPass *createR600ExpandSpecialInstrsPass();
32 FunctionPass *createR600EmitClauseMarkers();
33 FunctionPass *createR600ClauseMergePass();
34 FunctionPass *createR600Packetizer();
35 FunctionPass *createR600ControlFlowFinalizer();
36 FunctionPass *createAMDGPUCFGStructurizerPass();
37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
38 
39 // SI Passes
40 FunctionPass *createGCNDPPCombinePass();
41 FunctionPass *createSIAnnotateControlFlowPass();
42 FunctionPass *createSIFoldOperandsPass();
43 FunctionPass *createSIPeepholeSDWAPass();
44 FunctionPass *createSILowerI1CopiesPass();
45 FunctionPass *createSIFixupVectorISelPass();
46 FunctionPass *createSIShrinkInstructionsPass();
47 FunctionPass *createSILoadStoreOptimizerPass();
48 FunctionPass *createSIWholeQuadModePass();
51 FunctionPass *createSIFixSGPRCopiesPass();
52 FunctionPass *createSIMemoryLegalizerPass();
53 FunctionPass *createSIDebuggerInsertNopsPass();
54 FunctionPass *createSIInsertWaitcntsPass();
55 FunctionPass *createSIFixWWMLivenessPass();
56 FunctionPass *createSIFormMemoryClausesPass();
57 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
58 FunctionPass *createAMDGPUUseNativeCallsPass();
59 FunctionPass *createAMDGPUCodeGenPreparePass();
62 FunctionPass *createSIModeRegisterPass();
63 
64 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
65 
68 
69 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
70 
74 
75 FunctionPass *createAMDGPUAtomicOptimizerPass();
76 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
77 extern char &AMDGPUAtomicOptimizerID;
78 
80 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
81 extern char &AMDGPULowerIntrinsicsID;
82 
84 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
85 extern char &AMDGPUFixFunctionBitcastsID;
86 
88 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
89 extern char &AMDGPULowerKernelArgumentsID;
90 
94 
95 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
96 extern char &AMDGPURewriteOutArgumentsID;
97 
98 void initializeGCNDPPCombinePass(PassRegistry &);
99 extern char &GCNDPPCombineID;
100 
101 void initializeR600ClauseMergePassPass(PassRegistry &);
102 extern char &R600ClauseMergePassID;
103 
104 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
105 extern char &R600ControlFlowFinalizerID;
106 
107 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
108 extern char &R600ExpandSpecialInstrsPassID;
109 
110 void initializeR600VectorRegMergerPass(PassRegistry &);
111 extern char &R600VectorRegMergerID;
112 
113 void initializeR600PacketizerPass(PassRegistry &);
114 extern char &R600PacketizerID;
115 
116 void initializeSIFoldOperandsPass(PassRegistry &);
117 extern char &SIFoldOperandsID;
118 
119 void initializeSIPeepholeSDWAPass(PassRegistry &);
120 extern char &SIPeepholeSDWAID;
121 
122 void initializeSIShrinkInstructionsPass(PassRegistry&);
123 extern char &SIShrinkInstructionsID;
124 
125 void initializeSIFixSGPRCopiesPass(PassRegistry &);
126 extern char &SIFixSGPRCopiesID;
127 
128 void initializeSIFixVGPRCopiesPass(PassRegistry &);
129 extern char &SIFixVGPRCopiesID;
130 
131 void initializeSIFixupVectorISelPass(PassRegistry &);
132 extern char &SIFixupVectorISelID;
133 
134 void initializeSILowerI1CopiesPass(PassRegistry &);
135 extern char &SILowerI1CopiesID;
136 
137 void initializeSILoadStoreOptimizerPass(PassRegistry &);
138 extern char &SILoadStoreOptimizerID;
139 
140 void initializeSIWholeQuadModePass(PassRegistry &);
141 extern char &SIWholeQuadModeID;
142 
143 void initializeSILowerControlFlowPass(PassRegistry &);
144 extern char &SILowerControlFlowID;
145 
146 void initializeSIInsertSkipsPass(PassRegistry &);
147 extern char &SIInsertSkipsPassID;
148 
149 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
150 extern char &SIOptimizeExecMaskingID;
151 
152 void initializeSIFixWWMLivenessPass(PassRegistry &);
153 extern char &SIFixWWMLivenessID;
154 
155 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
156 extern char &AMDGPUSimplifyLibCallsID;
157 
158 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
159 extern char &AMDGPUUseNativeCallsID;
160 
161 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
162 extern char &AMDGPUPerfHintAnalysisID;
163 
164 // Passes common to R600 and SI
165 FunctionPass *createAMDGPUPromoteAlloca();
166 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
167 extern char &AMDGPUPromoteAllocaID;
168 
170 FunctionPass *createAMDGPUISelDag(
171  TargetMachine *TM = nullptr,
173 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
175 FunctionPass *createAMDGPUAnnotateUniformValues();
176 
177 ModulePass* createAMDGPUUnifyMetadataPass();
178 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
179 extern char &AMDGPUUnifyMetadataID;
180 
181 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
182 extern char &SIOptimizeExecMaskingPreRAID;
183 
186 
187 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
188 extern char &AMDGPUCodeGenPrepareID;
189 
190 void initializeSIAnnotateControlFlowPass(PassRegistry&);
191 extern char &SIAnnotateControlFlowPassID;
192 
193 void initializeSIMemoryLegalizerPass(PassRegistry&);
194 extern char &SIMemoryLegalizerID;
195 
196 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
197 extern char &SIDebuggerInsertNopsID;
198 
199 void initializeSIModeRegisterPass(PassRegistry&);
200 extern char &SIModeRegisterID;
201 
202 void initializeSIInsertWaitcntsPass(PassRegistry&);
203 extern char &SIInsertWaitcntsID;
204 
205 void initializeSIFormMemoryClausesPass(PassRegistry&);
206 extern char &SIFormMemoryClausesID;
207 
210 
211 ImmutablePass *createAMDGPUAAWrapperPass();
212 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
213 ImmutablePass *createAMDGPUExternalAAWrapperPass();
214 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
215 
216 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
217 
219 void initializeAMDGPUInlinerPass(PassRegistry&);
220 
224 
225 Target &getTheAMDGPUTarget();
226 Target &getTheGCNTarget();
227 
228 namespace AMDGPU {
235 };
236 }
237 
238 } // End namespace llvm
239 
240 /// OpenCL uses address spaces to differentiate between
241 /// various memory regions on the hardware. On the CPU
242 /// all of the address spaces point to the same memory,
243 /// however on the GPU, each address space points to
244 /// a separate piece of memory that is unique from other
245 /// memory locations.
246 namespace AMDGPUAS {
247  enum : unsigned {
248  // The maximum value for flat, generic, local, private, constant and region.
250 
251  FLAT_ADDRESS = 0, ///< Address space for flat memory.
252  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
253  REGION_ADDRESS = 2, ///< Address space for region memory.
254 
255  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
256  LOCAL_ADDRESS = 3, ///< Address space for local memory.
257  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
258 
259  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
260 
261  /// Address space for direct addressible parameter memory (CONST0)
263  /// Address space for indirect addressible parameter memory (VTX1)
265 
266  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
267  // this order to be able to dynamically index a constant buffer, for
268  // example:
269  //
270  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
271 
288 
289  // Some places use this if the address space can't be determined.
291  };
292 }
293 
294 #endif
char & SIFormMemoryClausesID
Pass * createAMDGPUStructurizeCFGPass()
Target & getTheGCNTarget()
The target for GCN GPUs.
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Address space for direct addressible parameter memory (CONST0)
Definition: AMDGPU.h:262
FunctionPass * createSIPeepholeSDWAPass()
This class represents lattice values for constants.
Definition: AllocatorList.h:24
FunctionPass * createSIFormMemoryClausesPass()
char & SIShrinkInstructionsID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPULowerKernelAttributesID
void initializeSIFormMemoryClausesPass(PassRegistry &)
ModulePass * createR600OpenCLImageTypeLoweringPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & SILoadStoreOptimizerID
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
char & SIPeepholeSDWAID
void initializeSIModeRegisterPass(PassRegistry &)
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
char & AMDGPULowerKernelArgumentsID
Address space for 32-bit constant memory.
Definition: AMDGPU.h:259
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
Address space for private memory.
Definition: AMDGPU.h:257
char & AMDGPUOpenCLEnqueuedBlockLoweringID
FunctionPass * createAMDGPUPromoteAlloca()
ModulePass * createAMDGPULowerKernelAttributesPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
char & SIFixupVectorISelID
FunctionPass * createAMDGPUCFGStructurizerPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
FunctionPass * createSIMemoryLegalizerPass()
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
char & AMDGPUAtomicOptimizerID
char & AMDGPURewriteOutArgumentsID
Address space for constant memory (VTX2)
Definition: AMDGPU.h:255
Pass * createAMDGPUFunctionInliningPass()
char & AMDGPUUnifyMetadataID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
void initializeAMDGPUInlinerPass(PassRegistry &)
char & SIOptimizeExecMaskingPreRAID
char & R600ControlFlowFinalizerID
FunctionPass * createR600ExpandSpecialInstrsPass()
FunctionPass * createSIFixupVectorISelPass()
char & R600PacketizerID
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createR600VectorRegMerger()
void initializeSIFixupVectorISelPass(PassRegistry &)
char & R600ExpandSpecialInstrsPassID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
char & GCNDPPCombineID
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIDebuggerInsertNopsPass()
FunctionPass * createSIWholeQuadModePass()
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
Address space for flat memory.
Definition: AMDGPU.h:251
char & AMDGPUUseNativeCallsID
FunctionPass * createGCNDPPCombinePass()
char & SIInsertSkipsPassID
void initializeSIPeepholeSDWAPass(PassRegistry &)
char & AMDGPUAnnotateKernelFeaturesID
char & AMDGPUPerfHintAnalysisID
Address space for indirect addressible parameter memory (VTX1)
Definition: AMDGPU.h:264
FunctionPass * createR600ControlFlowFinalizer()
Address space for local memory.
Definition: AMDGPU.h:256
void initializeSILowerControlFlowPass(PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
ModulePass * createAMDGPULowerIntrinsicsPass()
FunctionPass * createSIModeRegisterPass()
FunctionPass * createR600ClauseMergePass()
char & SILowerI1CopiesID
void initializeSIShrinkInstructionsPass(PassRegistry &)
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:252
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeSIInsertSkipsPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIFixWWMLivenessID
char & SIOptimizeExecMaskingID
FunctionPass * createSIFixWWMLivenessPass()
char & SIInsertWaitcntsID
print lazy value Lazy Value Info Printer Pass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIFixWWMLivenessPass(PassRegistry &)
void initializeSIMemoryLegalizerPass(PassRegistry &)
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPUAtomicOptimizerPass()
void initializeR600VectorRegMergerPass(PassRegistry &)
char & SIMemoryLegalizerID
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:246
void initializeGCNDPPCombinePass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createR600EmitClauseMarkers()
void initializeR600ClauseMergePassPass(PassRegistry &)
ModulePass * createAMDGPUFixFunctionBitcastsPass()
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesPass()
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
char & SIModeRegisterID
char & AMDGPUSimplifyLibCallsID
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createSIShrinkInstructionsPass()
void initializeSIDebuggerInsertNopsPass(PassRegistry &)
FunctionPass * createSIFoldOperandsPass()
char & SIFixSGPRCopiesID
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &)
char & AMDGPUMachineCFGStructurizerID
ImmutablePass * createAMDGPUExternalAAWrapperPass()
char & AMDGPULowerIntrinsicsID
FunctionPass * createSILoadStoreOptimizerPass()
FunctionPass * createAMDGPUUseNativeCallsPass()
Address space for region memory.
Definition: AMDGPU.h:253
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SIDebuggerInsertNopsID
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
char & AMDGPUFixFunctionBitcastsID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
char & R600ClauseMergePassID