LLVM  8.0.0svn
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 
15 
16 namespace llvm {
17 
18 class AMDGPUTargetMachine;
19 class FunctionPass;
20 class GCNTargetMachine;
21 class ModulePass;
22 class Pass;
23 class Target;
24 class TargetMachine;
25 class TargetOptions;
26 class PassRegistry;
27 class Module;
28 
29 // R600 Passes
30 FunctionPass *createR600VectorRegMerger();
31 FunctionPass *createR600ExpandSpecialInstrsPass();
32 FunctionPass *createR600EmitClauseMarkers();
33 FunctionPass *createR600ClauseMergePass();
34 FunctionPass *createR600Packetizer();
35 FunctionPass *createR600ControlFlowFinalizer();
36 FunctionPass *createAMDGPUCFGStructurizerPass();
37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
38 
39 // SI Passes
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSIPeepholeSDWAPass();
43 FunctionPass *createSILowerI1CopiesPass();
44 FunctionPass *createSIShrinkInstructionsPass();
45 FunctionPass *createSILoadStoreOptimizerPass();
46 FunctionPass *createSIWholeQuadModePass();
49 FunctionPass *createSIFixSGPRCopiesPass();
50 FunctionPass *createSIMemoryLegalizerPass();
51 FunctionPass *createSIDebuggerInsertNopsPass();
52 FunctionPass *createSIInsertWaitcntsPass();
53 FunctionPass *createSIFixWWMLivenessPass();
54 FunctionPass *createSIFormMemoryClausesPass();
55 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
56 FunctionPass *createAMDGPUUseNativeCallsPass();
57 FunctionPass *createAMDGPUCodeGenPreparePass();
60 
61 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
62 
65 
66 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
67 
71 
73 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
74 extern char &AMDGPULowerIntrinsicsID;
75 
77 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
78 extern char &AMDGPULowerKernelArgumentsID;
79 
83 
84 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
85 extern char &AMDGPURewriteOutArgumentsID;
86 
87 void initializeR600ClauseMergePassPass(PassRegistry &);
88 extern char &R600ClauseMergePassID;
89 
90 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
91 extern char &R600ControlFlowFinalizerID;
92 
95 
96 void initializeR600VectorRegMergerPass(PassRegistry &);
97 extern char &R600VectorRegMergerID;
98 
99 void initializeR600PacketizerPass(PassRegistry &);
100 extern char &R600PacketizerID;
101 
102 void initializeSIFoldOperandsPass(PassRegistry &);
103 extern char &SIFoldOperandsID;
104 
105 void initializeSIPeepholeSDWAPass(PassRegistry &);
106 extern char &SIPeepholeSDWAID;
107 
108 void initializeSIShrinkInstructionsPass(PassRegistry&);
109 extern char &SIShrinkInstructionsID;
110 
111 void initializeSIFixSGPRCopiesPass(PassRegistry &);
112 extern char &SIFixSGPRCopiesID;
113 
114 void initializeSIFixVGPRCopiesPass(PassRegistry &);
115 extern char &SIFixVGPRCopiesID;
116 
117 void initializeSILowerI1CopiesPass(PassRegistry &);
118 extern char &SILowerI1CopiesID;
119 
120 void initializeSILoadStoreOptimizerPass(PassRegistry &);
121 extern char &SILoadStoreOptimizerID;
122 
123 void initializeSIWholeQuadModePass(PassRegistry &);
124 extern char &SIWholeQuadModeID;
125 
126 void initializeSILowerControlFlowPass(PassRegistry &);
127 extern char &SILowerControlFlowID;
128 
129 void initializeSIInsertSkipsPass(PassRegistry &);
130 extern char &SIInsertSkipsPassID;
131 
132 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
133 extern char &SIOptimizeExecMaskingID;
134 
135 void initializeSIFixWWMLivenessPass(PassRegistry &);
136 extern char &SIFixWWMLivenessID;
137 
138 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
139 extern char &AMDGPUSimplifyLibCallsID;
140 
141 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
142 extern char &AMDGPUUseNativeCallsID;
143 
144 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
145 extern char &AMDGPUPerfHintAnalysisID;
146 
147 // Passes common to R600 and SI
148 FunctionPass *createAMDGPUPromoteAlloca();
149 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
150 extern char &AMDGPUPromoteAllocaID;
151 
153 FunctionPass *createAMDGPUISelDag(
154  TargetMachine *TM = nullptr,
156 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
158 FunctionPass *createAMDGPUAnnotateUniformValues();
159 
160 ModulePass* createAMDGPUUnifyMetadataPass();
161 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
162 extern char &AMDGPUUnifyMetadataID;
163 
164 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
165 extern char &SIOptimizeExecMaskingPreRAID;
166 
169 
170 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
171 extern char &AMDGPUCodeGenPrepareID;
172 
173 void initializeSIAnnotateControlFlowPass(PassRegistry&);
174 extern char &SIAnnotateControlFlowPassID;
175 
176 void initializeSIMemoryLegalizerPass(PassRegistry&);
177 extern char &SIMemoryLegalizerID;
178 
179 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
180 extern char &SIDebuggerInsertNopsID;
181 
182 void initializeSIInsertWaitcntsPass(PassRegistry&);
183 extern char &SIInsertWaitcntsID;
184 
185 void initializeSIFormMemoryClausesPass(PassRegistry&);
186 extern char &SIFormMemoryClausesID;
187 
190 
191 ImmutablePass *createAMDGPUAAWrapperPass();
192 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
193 
194 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
195 
197 void initializeAMDGPUInlinerPass(PassRegistry&);
198 
202 
203 Target &getTheAMDGPUTarget();
204 Target &getTheGCNTarget();
205 
206 namespace AMDGPU {
213 };
214 }
215 
216 } // End namespace llvm
217 
218 /// OpenCL uses address spaces to differentiate between
219 /// various memory regions on the hardware. On the CPU
220 /// all of the address spaces point to the same memory,
221 /// however on the GPU, each address space points to
222 /// a separate piece of memory that is unique from other
223 /// memory locations.
224 namespace AMDGPUAS {
225  enum : unsigned {
226  // The maximum value for flat, generic, local, private, constant and region.
228 
229  FLAT_ADDRESS = 0, ///< Address space for flat memory.
230  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
231  REGION_ADDRESS = 2, ///< Address space for region memory.
232 
233  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
234  LOCAL_ADDRESS = 3, ///< Address space for local memory.
235  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
236 
237  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
238 
239  /// Address space for direct addressible parameter memory (CONST0)
241  /// Address space for indirect addressible parameter memory (VTX1)
243 
244  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
245  // this order to be able to dynamically index a constant buffer, for
246  // example:
247  //
248  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
249 
266 
267  // Some places use this if the address space can't be determined.
269  };
270 }
271 
272 #endif
char & SIFormMemoryClausesID
Pass * createAMDGPUStructurizeCFGPass()
Target & getTheGCNTarget()
The target for GCN GPUs.
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Address space for region memory.
Definition: AMDGPU.h:231
FunctionPass * createSIFormMemoryClausesPass()
char & SIShrinkInstructionsID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPULowerKernelAttributesID
void initializeSIFormMemoryClausesPass(PassRegistry &)
ModulePass * createR600OpenCLImageTypeLoweringPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
char & SILoadStoreOptimizerID
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
char & SIPeepholeSDWAID
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
char & AMDGPUOpenCLEnqueuedBlockLoweringID
FunctionPass * createAMDGPUPromoteAlloca()
ModulePass * createAMDGPULowerKernelAttributesPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
FunctionPass * createAMDGPUCFGStructurizerPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
FunctionPass * createSIMemoryLegalizerPass()
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
char & AMDGPURewriteOutArgumentsID
Pass * createAMDGPUFunctionInliningPass()
char & AMDGPUUnifyMetadataID
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:230
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
void initializeAMDGPUInlinerPass(PassRegistry &)
char & SIOptimizeExecMaskingPreRAID
char & R600ControlFlowFinalizerID
FunctionPass * createR600ExpandSpecialInstrsPass()
char & R600PacketizerID
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
char & SILowerI1CopiesID
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createR600VectorRegMerger()
char & R600ExpandSpecialInstrsPassID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIDebuggerInsertNopsPass()
FunctionPass * createSIWholeQuadModePass()
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & AMDGPUUseNativeCallsID
char & SIInsertSkipsPassID
void initializeSIPeepholeSDWAPass(PassRegistry &)
char & AMDGPUAnnotateKernelFeaturesID
char & AMDGPUPerfHintAnalysisID
FunctionPass * createR600ControlFlowFinalizer()
void initializeSILowerControlFlowPass(PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
ModulePass * createAMDGPULowerIntrinsicsPass()
FunctionPass * createR600ClauseMergePass()
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeSIInsertSkipsPass(PassRegistry &)
void initializeR600PacketizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIFixWWMLivenessID
char & SIOptimizeExecMaskingID
FunctionPass * createSIFixWWMLivenessPass()
Address space for local memory.
Definition: AMDGPU.h:234
Address space for flat memory.
Definition: AMDGPU.h:229
char & SIInsertWaitcntsID
print lazy value Lazy Value Info Printer Pass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIFixWWMLivenessPass(PassRegistry &)
void initializeSIMemoryLegalizerPass(PassRegistry &)
void initializeSIWholeQuadModePass(PassRegistry &)
void initializeR600VectorRegMergerPass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
Address space for constant memory (VTX2)
Definition: AMDGPU.h:233
char & SIMemoryLegalizerID
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:224
FunctionPass * createR600EmitClauseMarkers()
void initializeR600ClauseMergePassPass(PassRegistry &)
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
Address space for indirect addressible parameter memory (VTX1)
Definition: AMDGPU.h:242
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesPass()
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
char & AMDGPUSimplifyLibCallsID
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createSIShrinkInstructionsPass()
void initializeSIDebuggerInsertNopsPass(PassRegistry &)
FunctionPass * createSIFoldOperandsPass()
Address space for direct addressible parameter memory (CONST0)
Definition: AMDGPU.h:240
char & SIFixSGPRCopiesID
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &)
char & AMDGPUMachineCFGStructurizerID
Address space for private memory.
Definition: AMDGPU.h:235
char & AMDGPULowerIntrinsicsID
FunctionPass * createSILoadStoreOptimizerPass()
FunctionPass * createAMDGPUUseNativeCallsPass()
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SIDebuggerInsertNopsID
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
Address space for 32-bit constant memory.
Definition: AMDGPU.h:237
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
char & R600ClauseMergePassID