LLVM  9.0.0svn
SIFixVGPRCopies.cpp
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1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Add implicit use of exec to vector register copies.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPU.h"
15 #include "AMDGPUSubtarget.h"
16 #include "SIInstrInfo.h"
19 
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "si-fix-vgpr-copies"
23 
24 namespace {
25 
26 class SIFixVGPRCopies : public MachineFunctionPass {
27 public:
28  static char ID;
29 
30 public:
31  SIFixVGPRCopies() : MachineFunctionPass(ID) {
33  }
34 
35  bool runOnMachineFunction(MachineFunction &MF) override;
36 
37  StringRef getPassName() const override { return "SI Fix VGPR copies"; }
38 };
39 
40 } // End anonymous namespace.
41 
42 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
43 
44 char SIFixVGPRCopies::ID = 0;
45 
47 
48 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
50  const SIRegisterInfo *TRI = ST.getRegisterInfo();
51  const SIInstrInfo *TII = ST.getInstrInfo();
52  bool Changed = false;
53 
54  for (MachineBasicBlock &MBB : MF) {
55  for (MachineInstr &MI : MBB) {
56  switch (MI.getOpcode()) {
57  case AMDGPU::COPY:
58  if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
59  MI.addOperand(MF,
60  MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
61  LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
62  Changed = true;
63  }
64  break;
65  default:
66  break;
67  }
68  }
69  }
70 
71  return Changed;
72 }
#define DEBUG_TYPE
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AMDGPU specific subclass of TargetSubtarget.
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:616
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void initializeSIFixVGPRCopiesPass(PassRegistry &)
const SIInstrInfo * getInstrInfo() const override
unsigned const TargetRegisterInfo * TRI
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
char & SIFixVGPRCopiesID
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Interface definition for SIInstrInfo.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const SIRegisterInfo * getRegisterInfo() const override