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RegAllocBasic.cpp
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1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AllocationOrder.h"
16 #include "LiveDebugVariables.h"
17 #include "RegAllocBase.h"
18 #include "Spiller.h"
30 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Support/Debug.h"
37 #include <cstdlib>
38 #include <queue>
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "regalloc"
43 
44 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
46 
47 namespace {
48  struct CompSpillWeight {
49  bool operator()(LiveInterval *A, LiveInterval *B) const {
50  return A->weight < B->weight;
51  }
52  };
53 }
54 
55 namespace {
56 /// RABasic provides a minimal implementation of the basic register allocation
57 /// algorithm. It prioritizes live virtual registers by spill weight and spills
58 /// whenever a register is unavailable. This is not practical in production but
59 /// provides a useful baseline both for measuring other allocators and comparing
60 /// the speed of the basic algorithm against other styles of allocators.
61 class RABasic : public MachineFunctionPass,
62  public RegAllocBase,
63  private LiveRangeEdit::Delegate {
64  // context
65  MachineFunction *MF;
66 
67  // state
68  std::unique_ptr<Spiller> SpillerInstance;
69  std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
70  CompSpillWeight> Queue;
71 
72  // Scratch space. Allocated here to avoid repeated malloc calls in
73  // selectOrSplit().
74  BitVector UsableRegs;
75 
76  bool LRE_CanEraseVirtReg(unsigned) override;
77  void LRE_WillShrinkVirtReg(unsigned) override;
78 
79 public:
80  RABasic();
81 
82  /// Return the pass name.
83  StringRef getPassName() const override { return "Basic Register Allocator"; }
84 
85  /// RABasic analysis usage.
86  void getAnalysisUsage(AnalysisUsage &AU) const override;
87 
88  void releaseMemory() override;
89 
90  Spiller &spiller() override { return *SpillerInstance; }
91 
92  void enqueue(LiveInterval *LI) override {
93  Queue.push(LI);
94  }
95 
96  LiveInterval *dequeue() override {
97  if (Queue.empty())
98  return nullptr;
99  LiveInterval *LI = Queue.top();
100  Queue.pop();
101  return LI;
102  }
103 
104  unsigned selectOrSplit(LiveInterval &VirtReg,
105  SmallVectorImpl<unsigned> &SplitVRegs) override;
106 
107  /// Perform register allocation.
108  bool runOnMachineFunction(MachineFunction &mf) override;
109 
110  MachineFunctionProperties getRequiredProperties() const override {
113  }
114 
115  // Helper for spilling all live virtual registers currently unified under preg
116  // that interfere with the most recently queried lvr. Return true if spilling
117  // was successful, and append any new spilled/split intervals to splitLVRs.
118  bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
119  SmallVectorImpl<unsigned> &SplitVRegs);
120 
121  static char ID;
122 };
123 
124 char RABasic::ID = 0;
125 
126 } // end anonymous namespace
127 
129 
130 INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
131  false, false)
135 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
136 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
143  false)
144 
145 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
146  LiveInterval &LI = LIS->getInterval(VirtReg);
147  if (VRM->hasPhys(VirtReg)) {
148  Matrix->unassign(LI);
149  aboutToRemoveInterval(LI);
150  return true;
151  }
152  // Unassigned virtreg is probably in the priority queue.
153  // RegAllocBase will erase it after dequeueing.
154  // Nonetheless, clear the live-range so that the debug
155  // dump will show the right state for that VirtReg.
156  LI.clear();
157  return false;
158 }
159 
160 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
161  if (!VRM->hasPhys(VirtReg))
162  return;
163 
164  // Register is assigned, put it back on the queue for reassignment.
165  LiveInterval &LI = LIS->getInterval(VirtReg);
166  Matrix->unassign(LI);
167  enqueue(&LI);
168 }
169 
170 RABasic::RABasic(): MachineFunctionPass(ID) {
171 }
172 
173 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
174  AU.setPreservesCFG();
182  AU.addRequired<LiveStacks>();
183  AU.addPreserved<LiveStacks>();
190  AU.addRequired<VirtRegMap>();
191  AU.addPreserved<VirtRegMap>();
195 }
196 
197 void RABasic::releaseMemory() {
198  SpillerInstance.reset();
199 }
200 
201 
202 // Spill or split all live virtual registers currently unified under PhysReg
203 // that interfere with VirtReg. The newly spilled or split live intervals are
204 // returned by appending them to SplitVRegs.
205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
206  SmallVectorImpl<unsigned> &SplitVRegs) {
207  // Record each interference and determine if all are spillable before mutating
208  // either the union or live intervals.
210 
211  // Collect interferences assigned to any alias of the physical register.
212  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
213  LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
215  for (unsigned i = Q.interferingVRegs().size(); i; --i) {
216  LiveInterval *Intf = Q.interferingVRegs()[i - 1];
217  if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
218  return false;
219  Intfs.push_back(Intf);
220  }
221  }
222  DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
223  " interferences with " << VirtReg << "\n");
224  assert(!Intfs.empty() && "expected interference");
225 
226  // Spill each interfering vreg allocated to PhysReg or an alias.
227  for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
228  LiveInterval &Spill = *Intfs[i];
229 
230  // Skip duplicates.
231  if (!VRM->hasPhys(Spill.reg))
232  continue;
233 
234  // Deallocate the interfering vreg by removing it from the union.
235  // A LiveInterval instance may not be in a union during modification!
236  Matrix->unassign(Spill);
237 
238  // Spill the extracted interval.
239  LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
240  spiller().spill(LRE);
241  }
242  return true;
243 }
244 
245 // Driver for the register assignment and splitting heuristics.
246 // Manages iteration over the LiveIntervalUnions.
247 //
248 // This is a minimal implementation of register assignment and splitting that
249 // spills whenever we run out of registers.
250 //
251 // selectOrSplit can only be called once per live virtual register. We then do a
252 // single interference test for each register the correct class until we find an
253 // available register. So, the number of interference tests in the worst case is
254 // |vregs| * |machineregs|. And since the number of interference tests is
255 // minimal, there is no value in caching them outside the scope of
256 // selectOrSplit().
257 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
258  SmallVectorImpl<unsigned> &SplitVRegs) {
259  // Populate a list of physical register spill candidates.
260  SmallVector<unsigned, 8> PhysRegSpillCands;
261 
262  // Check for an available register in this class.
263  AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
264  while (unsigned PhysReg = Order.next()) {
265  // Check for interference in PhysReg
266  switch (Matrix->checkInterference(VirtReg, PhysReg)) {
268  // PhysReg is available, allocate it.
269  return PhysReg;
270 
272  // Only virtual registers in the way, we may be able to spill them.
273  PhysRegSpillCands.push_back(PhysReg);
274  continue;
275 
276  default:
277  // RegMask or RegUnit interference.
278  continue;
279  }
280  }
281 
282  // Try to spill another interfering reg with less spill weight.
283  for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
284  PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
285  if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
286  continue;
287 
288  assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
289  "Interference after spill.");
290  // Tell the caller to allocate to this newly freed physical register.
291  return *PhysRegI;
292  }
293 
294  // No other spill candidates were found, so spill the current VirtReg.
295  DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
296  if (!VirtReg.isSpillable())
297  return ~0u;
298  LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
299  spiller().spill(LRE);
300 
301  // The live virtual register requesting allocation was spilled, so tell
302  // the caller not to allocate anything during this round.
303  return 0;
304 }
305 
306 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
307  DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
308  << "********** Function: "
309  << mf.getName() << '\n');
310 
311  MF = &mf;
312  RegAllocBase::init(getAnalysis<VirtRegMap>(),
313  getAnalysis<LiveIntervals>(),
314  getAnalysis<LiveRegMatrix>());
315 
316  calculateSpillWeightsAndHints(*LIS, *MF, VRM,
317  getAnalysis<MachineLoopInfo>(),
318  getAnalysis<MachineBlockFrequencyInfo>());
319 
320  SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
321 
322  allocatePhysRegs();
323  postOptimization();
324 
325  // Diagnostic output before rewriting
326  DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
327 
328  releaseMemory();
329  return true;
330 }
331 
333 {
334  return new RABasic();
335 }
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
No interference, go ahead and assign.
Definition: LiveRegMatrix.h:86
const unsigned reg
Definition: LiveInterval.h:667
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator)
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:638
Spiller interface.
Definition: Spiller.h:24
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
unsigned next(unsigned Limit=0)
Return the next physical register in the allocation order, or 0.
Callback methods for LiveRangeEdit owners.
Definition: LiveRangeEdit.h:49
Live Register Matrix
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
Query interferences between a single live virtual register and a live interval union.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator", false, false) INITIALIZE_PASS_END(RABasic
RegAllocBase provides the register allocation driver and interface that can be extended to add intere...
Definition: RegAllocBase.h:61
SlotIndexes pass.
Definition: SlotIndexes.h:331
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
AnalysisUsage & addPreservedID(const void *ID)
RegisterRegAlloc class - Track the registration of register allocators.
char & RABasicID
Basic register allocator.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
Basic Register Allocator
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, VirtRegMap *VRM, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
AnalysisUsage & addRequiredID(const void *ID)
Definition: Pass.cpp:298
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
Promote Memory to Register
Definition: Mem2Reg.cpp:101
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:285
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MachineFunctionProperties & set(Property P)
Spiller * createInlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
regallocbasic
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:767
#define DEBUG(X)
Definition: Debug.h:118
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Virtual register interference.
Definition: LiveRegMatrix.h:91
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Properties which a MachineFunction may have at a given point in time.