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MachineLICM.cpp
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1 //===- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
12 //
13 // This pass is not intended to be a replacement or a complete alternative
14 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
15 // constructs that are not exposed before lowering and instruction selection.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/Statistic.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/MC/MCRegisterInfo.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/Debug.h"
50 #include <algorithm>
51 #include <cassert>
52 #include <limits>
53 #include <vector>
54 
55 using namespace llvm;
56 
57 #define DEBUG_TYPE "machinelicm"
58 
59 static cl::opt<bool>
60 AvoidSpeculation("avoid-speculation",
61  cl::desc("MachineLICM should avoid speculation"),
62  cl::init(true), cl::Hidden);
63 
64 static cl::opt<bool>
65 HoistCheapInsts("hoist-cheap-insts",
66  cl::desc("MachineLICM should hoist even cheap instructions"),
67  cl::init(false), cl::Hidden);
68 
69 static cl::opt<bool>
70 SinkInstsToAvoidSpills("sink-insts-to-avoid-spills",
71  cl::desc("MachineLICM should sink instructions into "
72  "loops to avoid register spills"),
73  cl::init(false), cl::Hidden);
74 static cl::opt<bool>
75 HoistConstStores("hoist-const-stores",
76  cl::desc("Hoist invariant stores"),
77  cl::init(true), cl::Hidden);
78 
79 STATISTIC(NumHoisted,
80  "Number of machine instructions hoisted out of loops");
81 STATISTIC(NumLowRP,
82  "Number of instructions hoisted in low reg pressure situation");
83 STATISTIC(NumHighLatency,
84  "Number of high latency instructions hoisted");
85 STATISTIC(NumCSEed,
86  "Number of hoisted machine instructions CSEed");
87 STATISTIC(NumPostRAHoisted,
88  "Number of machine instructions hoisted out of loops post regalloc");
89 STATISTIC(NumStoreConst,
90  "Number of stores of const phys reg hoisted out of loops");
91 
92 namespace {
93 
94  class MachineLICMBase : public MachineFunctionPass {
95  const TargetInstrInfo *TII;
96  const TargetLoweringBase *TLI;
97  const TargetRegisterInfo *TRI;
98  const MachineFrameInfo *MFI;
100  TargetSchedModel SchedModel;
101  bool PreRegAlloc;
102 
103  // Various analyses that we use...
104  AliasAnalysis *AA; // Alias analysis info.
105  MachineLoopInfo *MLI; // Current MachineLoopInfo
106  MachineDominatorTree *DT; // Machine dominator tree for the cur loop
107 
108  // State that is updated as we process loops
109  bool Changed; // True if a loop is changed.
110  bool FirstInLoop; // True if it's the first LICM in the loop.
111  MachineLoop *CurLoop; // The current loop we are working on.
112  MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
113 
114  // Exit blocks for CurLoop.
116 
117  bool isExitBlock(const MachineBasicBlock *MBB) const {
118  return is_contained(ExitBlocks, MBB);
119  }
120 
121  // Track 'estimated' register pressure.
122  SmallSet<unsigned, 32> RegSeen;
124 
125  // Register pressure "limit" per register pressure set. If the pressure
126  // is higher than the limit, then it's considered high.
127  SmallVector<unsigned, 8> RegLimit;
128 
129  // Register pressure on path leading from loop preheader to current BB.
131 
132  // For each opcode, keep a list of potential CSE instructions.
134 
135  enum {
136  SpeculateFalse = 0,
137  SpeculateTrue = 1,
138  SpeculateUnknown = 2
139  };
140 
141  // If a MBB does not dominate loop exiting blocks then it may not safe
142  // to hoist loads from this block.
143  // Tri-state: 0 - false, 1 - true, 2 - unknown
144  unsigned SpeculationState;
145 
146  public:
147  MachineLICMBase(char &PassID, bool PreRegAlloc)
148  : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {}
149 
150  bool runOnMachineFunction(MachineFunction &MF) override;
151 
152  void getAnalysisUsage(AnalysisUsage &AU) const override {
159  }
160 
161  void releaseMemory() override {
162  RegSeen.clear();
163  RegPressure.clear();
164  RegLimit.clear();
165  BackTrace.clear();
166  CSEMap.clear();
167  }
168 
169  private:
170  /// Keep track of information about hoisting candidates.
171  struct CandidateInfo {
172  MachineInstr *MI;
173  unsigned Def;
174  int FI;
175 
176  CandidateInfo(MachineInstr *mi, unsigned def, int fi)
177  : MI(mi), Def(def), FI(fi) {}
178  };
179 
180  void HoistRegionPostRA();
181 
182  void HoistPostRA(MachineInstr *MI, unsigned Def);
183 
184  void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
185  BitVector &PhysRegClobbers, SmallSet<int, 32> &StoredFIs,
186  SmallVectorImpl<CandidateInfo> &Candidates);
187 
188  void AddToLiveIns(unsigned Reg);
189 
190  bool IsLICMCandidate(MachineInstr &I);
191 
192  bool IsLoopInvariantInst(MachineInstr &I);
193 
194  bool HasLoopPHIUse(const MachineInstr *MI) const;
195 
196  bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
197  unsigned Reg) const;
198 
199  bool IsCheapInstruction(MachineInstr &MI) const;
200 
201  bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
202  bool Cheap);
203 
204  void UpdateBackTraceRegPressure(const MachineInstr *MI);
205 
206  bool IsProfitableToHoist(MachineInstr &MI);
207 
208  bool IsGuaranteedToExecute(MachineBasicBlock *BB);
209 
210  void EnterScope(MachineBasicBlock *MBB);
211 
212  void ExitScope(MachineBasicBlock *MBB);
213 
214  void ExitScopeIfDone(
215  MachineDomTreeNode *Node,
218 
219  void HoistOutOfLoop(MachineDomTreeNode *HeaderN);
220 
221  void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
222 
223  void SinkIntoLoop();
224 
225  void InitRegPressure(MachineBasicBlock *BB);
226 
227  DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
228  bool ConsiderSeen,
229  bool ConsiderUnseenAsDef);
230 
231  void UpdateRegPressure(const MachineInstr *MI,
232  bool ConsiderUnseenAsDef = false);
233 
234  MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
235 
236  const MachineInstr *
237  LookForDuplicate(const MachineInstr *MI,
238  std::vector<const MachineInstr *> &PrevMIs);
239 
240  bool EliminateCSE(
241  MachineInstr *MI,
242  DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI);
243 
244  bool MayCSE(MachineInstr *MI);
245 
246  bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
247 
248  void InitCSEMap(MachineBasicBlock *BB);
249 
250  MachineBasicBlock *getCurPreheader();
251  };
252 
253  class MachineLICM : public MachineLICMBase {
254  public:
255  static char ID;
256  MachineLICM() : MachineLICMBase(ID, false) {
258  }
259  };
260 
261  class EarlyMachineLICM : public MachineLICMBase {
262  public:
263  static char ID;
264  EarlyMachineLICM() : MachineLICMBase(ID, true) {
266  }
267  };
268 
269 } // end anonymous namespace
270 
271 char MachineLICM::ID;
273 
276 
277 INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE,
278  "Machine Loop Invariant Code Motion", false, false)
283  "Machine Loop Invariant Code Motion", false, false)
284 
285 INITIALIZE_PASS_BEGIN(EarlyMachineLICM, "early-machinelicm",
286  "Early Machine Loop Invariant Code Motion", false, false)
290 INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm",
291  "Early Machine Loop Invariant Code Motion", false, false)
292 
293 /// Test if the given loop is the outer-most loop that has a unique predecessor.
295  // Check whether this loop even has a unique predecessor.
296  if (!CurLoop->getLoopPredecessor())
297  return false;
298  // Ok, now check to see if any of its outer loops do.
299  for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
300  if (L->getLoopPredecessor())
301  return false;
302  // None of them did, so this is the outermost with a unique predecessor.
303  return true;
304 }
305 
306 bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
307  if (skipFunction(MF.getFunction()))
308  return false;
309 
310  Changed = FirstInLoop = false;
311  const TargetSubtargetInfo &ST = MF.getSubtarget();
312  TII = ST.getInstrInfo();
313  TLI = ST.getTargetLowering();
314  TRI = ST.getRegisterInfo();
315  MFI = &MF.getFrameInfo();
316  MRI = &MF.getRegInfo();
317  SchedModel.init(&ST);
318 
319  PreRegAlloc = MRI->isSSA();
320 
321  if (PreRegAlloc)
322  LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
323  else
324  LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
325  LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");
326 
327  if (PreRegAlloc) {
328  // Estimate register pressure during pre-regalloc pass.
329  unsigned NumRPS = TRI->getNumRegPressureSets();
330  RegPressure.resize(NumRPS);
331  std::fill(RegPressure.begin(), RegPressure.end(), 0);
332  RegLimit.resize(NumRPS);
333  for (unsigned i = 0, e = NumRPS; i != e; ++i)
334  RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
335  }
336 
337  // Get our Loop information...
338  MLI = &getAnalysis<MachineLoopInfo>();
339  DT = &getAnalysis<MachineDominatorTree>();
340  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
341 
342  SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
343  while (!Worklist.empty()) {
344  CurLoop = Worklist.pop_back_val();
345  CurPreheader = nullptr;
346  ExitBlocks.clear();
347 
348  // If this is done before regalloc, only visit outer-most preheader-sporting
349  // loops.
350  if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
351  Worklist.append(CurLoop->begin(), CurLoop->end());
352  continue;
353  }
354 
355  CurLoop->getExitBlocks(ExitBlocks);
356 
357  if (!PreRegAlloc)
358  HoistRegionPostRA();
359  else {
360  // CSEMap is initialized for loop header when the first instruction is
361  // being hoisted.
362  MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
363  FirstInLoop = true;
364  HoistOutOfLoop(N);
365  CSEMap.clear();
366 
368  SinkIntoLoop();
369  }
370  }
371 
372  return Changed;
373 }
374 
375 /// Return true if instruction stores to the specified frame.
376 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
377  // Check mayStore before memory operands so that e.g. DBG_VALUEs will return
378  // true since they have no memory operands.
379  if (!MI->mayStore())
380  return false;
381  // If we lost memory operands, conservatively assume that the instruction
382  // writes to all slots.
383  if (MI->memoperands_empty())
384  return true;
385  for (const MachineMemOperand *MemOp : MI->memoperands()) {
386  if (!MemOp->isStore() || !MemOp->getPseudoValue())
387  continue;
389  dyn_cast<FixedStackPseudoSourceValue>(MemOp->getPseudoValue())) {
390  if (Value->getFrameIndex() == FI)
391  return true;
392  }
393  }
394  return false;
395 }
396 
397 /// Examine the instruction for potentai LICM candidate. Also
398 /// gather register def and frame object update information.
399 void MachineLICMBase::ProcessMI(MachineInstr *MI,
400  BitVector &PhysRegDefs,
401  BitVector &PhysRegClobbers,
402  SmallSet<int, 32> &StoredFIs,
403  SmallVectorImpl<CandidateInfo> &Candidates) {
404  bool RuledOut = false;
405  bool HasNonInvariantUse = false;
406  unsigned Def = 0;
407  for (const MachineOperand &MO : MI->operands()) {
408  if (MO.isFI()) {
409  // Remember if the instruction stores to the frame index.
410  int FI = MO.getIndex();
411  if (!StoredFIs.count(FI) &&
412  MFI->isSpillSlotObjectIndex(FI) &&
413  InstructionStoresToFI(MI, FI))
414  StoredFIs.insert(FI);
415  HasNonInvariantUse = true;
416  continue;
417  }
418 
419  // We can't hoist an instruction defining a physreg that is clobbered in
420  // the loop.
421  if (MO.isRegMask()) {
422  PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
423  continue;
424  }
425 
426  if (!MO.isReg())
427  continue;
428  unsigned Reg = MO.getReg();
429  if (!Reg)
430  continue;
432  "Not expecting virtual register!");
433 
434  if (!MO.isDef()) {
435  if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)))
436  // If it's using a non-loop-invariant register, then it's obviously not
437  // safe to hoist.
438  HasNonInvariantUse = true;
439  continue;
440  }
441 
442  if (MO.isImplicit()) {
443  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
444  PhysRegClobbers.set(*AI);
445  if (!MO.isDead())
446  // Non-dead implicit def? This cannot be hoisted.
447  RuledOut = true;
448  // No need to check if a dead implicit def is also defined by
449  // another instruction.
450  continue;
451  }
452 
453  // FIXME: For now, avoid instructions with multiple defs, unless
454  // it's a dead implicit def.
455  if (Def)
456  RuledOut = true;
457  else
458  Def = Reg;
459 
460  // If we have already seen another instruction that defines the same
461  // register, then this is not safe. Two defs is indicated by setting a
462  // PhysRegClobbers bit.
463  for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
464  if (PhysRegDefs.test(*AS))
465  PhysRegClobbers.set(*AS);
466  PhysRegDefs.set(*AS);
467  }
468  if (PhysRegClobbers.test(Reg))
469  // MI defined register is seen defined by another instruction in
470  // the loop, it cannot be a LICM candidate.
471  RuledOut = true;
472  }
473 
474  // Only consider reloads for now and remats which do not have register
475  // operands. FIXME: Consider unfold load folding instructions.
476  if (Def && !RuledOut) {
477  int FI = std::numeric_limits<int>::min();
478  if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
479  (TII->isLoadFromStackSlot(*MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
480  Candidates.push_back(CandidateInfo(MI, Def, FI));
481  }
482 }
483 
484 /// Walk the specified region of the CFG and hoist loop invariants out to the
485 /// preheader.
486 void MachineLICMBase::HoistRegionPostRA() {
487  MachineBasicBlock *Preheader = getCurPreheader();
488  if (!Preheader)
489  return;
490 
491  unsigned NumRegs = TRI->getNumRegs();
492  BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
493  BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
494 
496  SmallSet<int, 32> StoredFIs;
497 
498  // Walk the entire region, count number of defs for each register, and
499  // collect potential LICM candidates.
500  for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
501  // If the header of the loop containing this basic block is a landing pad,
502  // then don't try to hoist instructions out of this loop.
503  const MachineLoop *ML = MLI->getLoopFor(BB);
504  if (ML && ML->getHeader()->isEHPad()) continue;
505 
506  // Conservatively treat live-in's as an external def.
507  // FIXME: That means a reload that're reused in successor block(s) will not
508  // be LICM'ed.
509  for (const auto &LI : BB->liveins()) {
510  for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI)
511  PhysRegDefs.set(*AI);
512  }
513 
514  SpeculationState = SpeculateUnknown;
515  for (MachineInstr &MI : *BB)
516  ProcessMI(&MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
517  }
518 
519  // Gather the registers read / clobbered by the terminator.
520  BitVector TermRegs(NumRegs);
522  if (TI != Preheader->end()) {
523  for (const MachineOperand &MO : TI->operands()) {
524  if (!MO.isReg())
525  continue;
526  unsigned Reg = MO.getReg();
527  if (!Reg)
528  continue;
529  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
530  TermRegs.set(*AI);
531  }
532  }
533 
534  // Now evaluate whether the potential candidates qualify.
535  // 1. Check if the candidate defined register is defined by another
536  // instruction in the loop.
537  // 2. If the candidate is a load from stack slot (always true for now),
538  // check if the slot is stored anywhere in the loop.
539  // 3. Make sure candidate def should not clobber
540  // registers read by the terminator. Similarly its def should not be
541  // clobbered by the terminator.
542  for (CandidateInfo &Candidate : Candidates) {
543  if (Candidate.FI != std::numeric_limits<int>::min() &&
544  StoredFIs.count(Candidate.FI))
545  continue;
546 
547  unsigned Def = Candidate.Def;
548  if (!PhysRegClobbers.test(Def) && !TermRegs.test(Def)) {
549  bool Safe = true;
550  MachineInstr *MI = Candidate.MI;
551  for (const MachineOperand &MO : MI->operands()) {
552  if (!MO.isReg() || MO.isDef() || !MO.getReg())
553  continue;
554  unsigned Reg = MO.getReg();
555  if (PhysRegDefs.test(Reg) ||
556  PhysRegClobbers.test(Reg)) {
557  // If it's using a non-loop-invariant register, then it's obviously
558  // not safe to hoist.
559  Safe = false;
560  break;
561  }
562  }
563  if (Safe)
564  HoistPostRA(MI, Candidate.Def);
565  }
566  }
567 }
568 
569 /// Add register 'Reg' to the livein sets of BBs in the current loop, and make
570 /// sure it is not killed by any instructions in the loop.
571 void MachineLICMBase::AddToLiveIns(unsigned Reg) {
572  for (MachineBasicBlock *BB : CurLoop->getBlocks()) {
573  if (!BB->isLiveIn(Reg))
574  BB->addLiveIn(Reg);
575  for (MachineInstr &MI : *BB) {
576  for (MachineOperand &MO : MI.operands()) {
577  if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
578  if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
579  MO.setIsKill(false);
580  }
581  }
582  }
583 }
584 
585 /// When an instruction is found to only use loop invariant operands that is
586 /// safe to hoist, this instruction is called to do the dirty work.
587 void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) {
588  MachineBasicBlock *Preheader = getCurPreheader();
589 
590  // Now move the instructions to the predecessor, inserting it before any
591  // terminator instructions.
592  LLVM_DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader)
593  << " from " << printMBBReference(*MI->getParent()) << ": "
594  << *MI);
595 
596  // Splice the instruction to the preheader.
597  MachineBasicBlock *MBB = MI->getParent();
598  Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
599 
600  // Add register to livein list to all the BBs in the current loop since a
601  // loop invariant must be kept live throughout the whole loop. This is
602  // important to ensure later passes do not scavenge the def register.
603  AddToLiveIns(Def);
604 
605  ++NumPostRAHoisted;
606  Changed = true;
607 }
608 
609 /// Check if this mbb is guaranteed to execute. If not then a load from this mbb
610 /// may not be safe to hoist.
611 bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB) {
612  if (SpeculationState != SpeculateUnknown)
613  return SpeculationState == SpeculateFalse;
614 
615  if (BB != CurLoop->getHeader()) {
616  // Check loop exiting blocks.
617  SmallVector<MachineBasicBlock*, 8> CurrentLoopExitingBlocks;
618  CurLoop->getExitingBlocks(CurrentLoopExitingBlocks);
619  for (MachineBasicBlock *CurrentLoopExitingBlock : CurrentLoopExitingBlocks)
620  if (!DT->dominates(BB, CurrentLoopExitingBlock)) {
621  SpeculationState = SpeculateTrue;
622  return false;
623  }
624  }
625 
626  SpeculationState = SpeculateFalse;
627  return true;
628 }
629 
630 void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
631  LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
632 
633  // Remember livein register pressure.
634  BackTrace.push_back(RegPressure);
635 }
636 
637 void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
638  LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
639  BackTrace.pop_back();
640 }
641 
642 /// Destroy scope for the MBB that corresponds to the given dominator tree node
643 /// if its a leaf or all of its children are done. Walk up the dominator tree to
644 /// destroy ancestors which are now done.
645 void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node,
648  if (OpenChildren[Node])
649  return;
650 
651  // Pop scope.
652  ExitScope(Node->getBlock());
653 
654  // Now traverse upwards to pop ancestors whose offsprings are all done.
655  while (MachineDomTreeNode *Parent = ParentMap[Node]) {
656  unsigned Left = --OpenChildren[Parent];
657  if (Left != 0)
658  break;
659  ExitScope(Parent->getBlock());
660  Node = Parent;
661  }
662 }
663 
664 /// Walk the specified loop in the CFG (defined by all blocks dominated by the
665 /// specified header block, and that are in the current loop) in depth first
666 /// order w.r.t the DominatorTree. This allows us to visit definitions before
667 /// uses, allowing us to hoist a loop body in one pass without iteration.
668 void MachineLICMBase::HoistOutOfLoop(MachineDomTreeNode *HeaderN) {
669  MachineBasicBlock *Preheader = getCurPreheader();
670  if (!Preheader)
671  return;
672 
677 
678  // Perform a DFS walk to determine the order of visit.
679  WorkList.push_back(HeaderN);
680  while (!WorkList.empty()) {
681  MachineDomTreeNode *Node = WorkList.pop_back_val();
682  assert(Node && "Null dominator tree node?");
683  MachineBasicBlock *BB = Node->getBlock();
684 
685  // If the header of the loop containing this basic block is a landing pad,
686  // then don't try to hoist instructions out of this loop.
687  const MachineLoop *ML = MLI->getLoopFor(BB);
688  if (ML && ML->getHeader()->isEHPad())
689  continue;
690 
691  // If this subregion is not in the top level loop at all, exit.
692  if (!CurLoop->contains(BB))
693  continue;
694 
695  Scopes.push_back(Node);
696  const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
697  unsigned NumChildren = Children.size();
698 
699  // Don't hoist things out of a large switch statement. This often causes
700  // code to be hoisted that wasn't going to be executed, and increases
701  // register pressure in a situation where it's likely to matter.
702  if (BB->succ_size() >= 25)
703  NumChildren = 0;
704 
705  OpenChildren[Node] = NumChildren;
706  // Add children in reverse order as then the next popped worklist node is
707  // the first child of this node. This means we ultimately traverse the
708  // DOM tree in exactly the same order as if we'd recursed.
709  for (int i = (int)NumChildren-1; i >= 0; --i) {
710  MachineDomTreeNode *Child = Children[i];
711  ParentMap[Child] = Node;
712  WorkList.push_back(Child);
713  }
714  }
715 
716  if (Scopes.size() == 0)
717  return;
718 
719  // Compute registers which are livein into the loop headers.
720  RegSeen.clear();
721  BackTrace.clear();
722  InitRegPressure(Preheader);
723 
724  // Now perform LICM.
725  for (MachineDomTreeNode *Node : Scopes) {
726  MachineBasicBlock *MBB = Node->getBlock();
727 
728  EnterScope(MBB);
729 
730  // Process the block
731  SpeculationState = SpeculateUnknown;
733  MII = MBB->begin(), E = MBB->end(); MII != E; ) {
734  MachineBasicBlock::iterator NextMII = MII; ++NextMII;
735  MachineInstr *MI = &*MII;
736  if (!Hoist(MI, Preheader))
737  UpdateRegPressure(MI);
738  // If we have hoisted an instruction that may store, it can only be a
739  // constant store.
740  MII = NextMII;
741  }
742 
743  // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
744  ExitScopeIfDone(Node, OpenChildren, ParentMap);
745  }
746 }
747 
748 /// Sink instructions into loops if profitable. This especially tries to prevent
749 /// register spills caused by register pressure if there is little to no
750 /// overhead moving instructions into loops.
751 void MachineLICMBase::SinkIntoLoop() {
752  MachineBasicBlock *Preheader = getCurPreheader();
753  if (!Preheader)
754  return;
755 
757  for (MachineBasicBlock::instr_iterator I = Preheader->instr_begin();
758  I != Preheader->instr_end(); ++I) {
759  // We need to ensure that we can safely move this instruction into the loop.
760  // As such, it must not have side-effects, e.g. such as a call has.
761  if (IsLoopInvariantInst(*I) && !HasLoopPHIUse(&*I))
762  Candidates.push_back(&*I);
763  }
764 
765  for (MachineInstr *I : Candidates) {
766  const MachineOperand &MO = I->getOperand(0);
767  if (!MO.isDef() || !MO.isReg() || !MO.getReg())
768  continue;
769  if (!MRI->hasOneDef(MO.getReg()))
770  continue;
771  bool CanSink = true;
772  MachineBasicBlock *B = nullptr;
773  for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
774  // FIXME: Come up with a proper cost model that estimates whether sinking
775  // the instruction (and thus possibly executing it on every loop
776  // iteration) is more expensive than a register.
777  // For now assumes that copies are cheap and thus almost always worth it.
778  if (!MI.isCopy()) {
779  CanSink = false;
780  break;
781  }
782  if (!B) {
783  B = MI.getParent();
784  continue;
785  }
786  B = DT->findNearestCommonDominator(B, MI.getParent());
787  if (!B) {
788  CanSink = false;
789  break;
790  }
791  }
792  if (!CanSink || !B || B == Preheader)
793  continue;
794  B->splice(B->getFirstNonPHI(), Preheader, I);
795  }
796 }
797 
798 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
799  return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
800 }
801 
802 /// Find all virtual register references that are liveout of the preheader to
803 /// initialize the starting "register pressure". Note this does not count live
804 /// through (livein but not used) registers.
805 void MachineLICMBase::InitRegPressure(MachineBasicBlock *BB) {
806  std::fill(RegPressure.begin(), RegPressure.end(), 0);
807 
808  // If the preheader has only a single predecessor and it ends with a
809  // fallthrough or an unconditional branch, then scan its predecessor for live
810  // defs as well. This happens whenever the preheader is created by splitting
811  // the critical edge from the loop predecessor to the loop header.
812  if (BB->pred_size() == 1) {
813  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
815  if (!TII->analyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
816  InitRegPressure(*BB->pred_begin());
817  }
818 
819  for (const MachineInstr &MI : *BB)
820  UpdateRegPressure(&MI, /*ConsiderUnseenAsDef=*/true);
821 }
822 
823 /// Update estimate of register pressure after the specified instruction.
824 void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
825  bool ConsiderUnseenAsDef) {
826  auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/true, ConsiderUnseenAsDef);
827  for (const auto &RPIdAndCost : Cost) {
828  unsigned Class = RPIdAndCost.first;
829  if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
830  RegPressure[Class] = 0;
831  else
832  RegPressure[Class] += RPIdAndCost.second;
833  }
834 }
835 
836 /// Calculate the additional register pressure that the registers used in MI
837 /// cause.
838 ///
839 /// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
840 /// figure out which usages are live-ins.
841 /// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
843 MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
844  bool ConsiderUnseenAsDef) {
846  if (MI->isImplicitDef())
847  return Cost;
848  for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
849  const MachineOperand &MO = MI->getOperand(i);
850  if (!MO.isReg() || MO.isImplicit())
851  continue;
852  unsigned Reg = MO.getReg();
854  continue;
855 
856  // FIXME: It seems bad to use RegSeen only for some of these calculations.
857  bool isNew = ConsiderSeen ? RegSeen.insert(Reg).second : false;
858  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
859 
861  int RCCost = 0;
862  if (MO.isDef())
863  RCCost = W.RegWeight;
864  else {
865  bool isKill = isOperandKill(MO, MRI);
866  if (isNew && !isKill && ConsiderUnseenAsDef)
867  // Haven't seen this, it must be a livein.
868  RCCost = W.RegWeight;
869  else if (!isNew && isKill)
870  RCCost = -W.RegWeight;
871  }
872  if (RCCost == 0)
873  continue;
874  const int *PS = TRI->getRegClassPressureSets(RC);
875  for (; *PS != -1; ++PS) {
876  if (Cost.find(*PS) == Cost.end())
877  Cost[*PS] = RCCost;
878  else
879  Cost[*PS] += RCCost;
880  }
881  }
882  return Cost;
883 }
884 
885 /// Return true if this machine instruction loads from global offset table or
886 /// constant pool.
888  assert(MI.mayLoad() && "Expected MI that loads!");
889 
890  // If we lost memory operands, conservatively assume that the instruction
891  // reads from everything..
892  if (MI.memoperands_empty())
893  return true;
894 
895  for (MachineMemOperand *MemOp : MI.memoperands())
896  if (const PseudoSourceValue *PSV = MemOp->getPseudoValue())
897  if (PSV->isGOT() || PSV->isConstantPool())
898  return true;
899 
900  return false;
901 }
902 
903 // This function iterates through all the operands of the input store MI and
904 // checks that each register operand statisfies isCallerPreservedPhysReg.
905 // This means, the value being stored and the address where it is being stored
906 // is constant throughout the body of the function (not including prologue and
907 // epilogue). When called with an MI that isn't a store, it returns false.
908 // A future improvement can be to check if the store registers are constant
909 // throughout the loop rather than throughout the funtion.
910 static bool isInvariantStore(const MachineInstr &MI,
911  const TargetRegisterInfo *TRI,
912  const MachineRegisterInfo *MRI) {
913 
914  bool FoundCallerPresReg = false;
915  if (!MI.mayStore() || MI.hasUnmodeledSideEffects() ||
916  (MI.getNumOperands() == 0))
917  return false;
918 
919  // Check that all register operands are caller-preserved physical registers.
920  for (const MachineOperand &MO : MI.operands()) {
921  if (MO.isReg()) {
922  unsigned Reg = MO.getReg();
923  // If operand is a virtual register, check if it comes from a copy of a
924  // physical register.
926  Reg = TRI->lookThruCopyLike(MO.getReg(), MRI);
928  return false;
929  if (!TRI->isCallerPreservedPhysReg(Reg, *MI.getMF()))
930  return false;
931  else
932  FoundCallerPresReg = true;
933  } else if (!MO.isImm()) {
934  return false;
935  }
936  }
937  return FoundCallerPresReg;
938 }
939 
940 // Return true if the input MI is a copy instruction that feeds an invariant
941 // store instruction. This means that the src of the copy has to satisfy
942 // isCallerPreservedPhysReg and atleast one of it's users should satisfy
943 // isInvariantStore.
945  const MachineRegisterInfo *MRI,
946  const TargetRegisterInfo *TRI) {
947 
948  // FIXME: If targets would like to look through instructions that aren't
949  // pure copies, this can be updated to a query.
950  if (!MI.isCopy())
951  return false;
952 
953  const MachineFunction *MF = MI.getMF();
954  // Check that we are copying a constant physical register.
955  unsigned CopySrcReg = MI.getOperand(1).getReg();
957  return false;
958 
959  if (!TRI->isCallerPreservedPhysReg(CopySrcReg, *MF))
960  return false;
961 
962  unsigned CopyDstReg = MI.getOperand(0).getReg();
963  // Check if any of the uses of the copy are invariant stores.
965  "copy dst is not a virtual reg");
966 
967  for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
968  if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI))
969  return true;
970  }
971  return false;
972 }
973 
974 /// Returns true if the instruction may be a suitable candidate for LICM.
975 /// e.g. If the instruction is a call, then it's obviously not safe to hoist it.
976 bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
977  // Check if it's safe to move the instruction.
978  bool DontMoveAcrossStore = true;
979  if ((!I.isSafeToMove(AA, DontMoveAcrossStore)) &&
980  !(HoistConstStores && isInvariantStore(I, TRI, MRI))) {
981  return false;
982  }
983 
984  // If it is load then check if it is guaranteed to execute by making sure that
985  // it dominates all exiting blocks. If it doesn't, then there is a path out of
986  // the loop which does not execute this load, so we can't hoist it. Loads
987  // from constant memory are not safe to speculate all the time, for example
988  // indexed load from a jump table.
989  // Stores and side effects are already checked by isSafeToMove.
990  if (I.mayLoad() && !mayLoadFromGOTOrConstantPool(I) &&
991  !IsGuaranteedToExecute(I.getParent()))
992  return false;
993 
994  return true;
995 }
996 
997 /// Returns true if the instruction is loop invariant.
998 /// I.e., all virtual register operands are defined outside of the loop,
999 /// physical registers aren't accessed explicitly, and there are no side
1000 /// effects that aren't captured by the operands or other flags.
1001 bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
1002  if (!IsLICMCandidate(I))
1003  return false;
1004 
1005  // The instruction is loop invariant if all of its operands are.
1006  for (const MachineOperand &MO : I.operands()) {
1007  if (!MO.isReg())
1008  continue;
1009 
1010  unsigned Reg = MO.getReg();
1011  if (Reg == 0) continue;
1012 
1013  // Don't hoist an instruction that uses or defines a physical register.
1015  if (MO.isUse()) {
1016  // If the physreg has no defs anywhere, it's just an ambient register
1017  // and we can freely move its uses. Alternatively, if it's allocatable,
1018  // it could get allocated to something with a def during allocation.
1019  // However, if the physreg is known to always be caller saved/restored
1020  // then this use is safe to hoist.
1021  if (!MRI->isConstantPhysReg(Reg) &&
1022  !(TRI->isCallerPreservedPhysReg(Reg, *I.getMF())))
1023  return false;
1024  // Otherwise it's safe to move.
1025  continue;
1026  } else if (!MO.isDead()) {
1027  // A def that isn't dead. We can't move it.
1028  return false;
1029  } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
1030  // If the reg is live into the loop, we can't hoist an instruction
1031  // which would clobber it.
1032  return false;
1033  }
1034  }
1035 
1036  if (!MO.isUse())
1037  continue;
1038 
1039  assert(MRI->getVRegDef(Reg) &&
1040  "Machine instr not mapped for this vreg?!");
1041 
1042  // If the loop contains the definition of an operand, then the instruction
1043  // isn't loop invariant.
1044  if (CurLoop->contains(MRI->getVRegDef(Reg)))
1045  return false;
1046  }
1047 
1048  // If we got this far, the instruction is loop invariant!
1049  return true;
1050 }
1051 
1052 /// Return true if the specified instruction is used by a phi node and hoisting
1053 /// it could cause a copy to be inserted.
1054 bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
1056  do {
1057  MI = Work.pop_back_val();
1058  for (const MachineOperand &MO : MI->operands()) {
1059  if (!MO.isReg() || !MO.isDef())
1060  continue;
1061  unsigned Reg = MO.getReg();
1063  continue;
1064  for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
1065  // A PHI may cause a copy to be inserted.
1066  if (UseMI.isPHI()) {
1067  // A PHI inside the loop causes a copy because the live range of Reg is
1068  // extended across the PHI.
1069  if (CurLoop->contains(&UseMI))
1070  return true;
1071  // A PHI in an exit block can cause a copy to be inserted if the PHI
1072  // has multiple predecessors in the loop with different values.
1073  // For now, approximate by rejecting all exit blocks.
1074  if (isExitBlock(UseMI.getParent()))
1075  return true;
1076  continue;
1077  }
1078  // Look past copies as well.
1079  if (UseMI.isCopy() && CurLoop->contains(&UseMI))
1080  Work.push_back(&UseMI);
1081  }
1082  }
1083  } while (!Work.empty());
1084  return false;
1085 }
1086 
1087 /// Compute operand latency between a def of 'Reg' and an use in the current
1088 /// loop, return true if the target considered it high.
1089 bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI,
1090  unsigned DefIdx,
1091  unsigned Reg) const {
1092  if (MRI->use_nodbg_empty(Reg))
1093  return false;
1094 
1095  for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
1096  if (UseMI.isCopyLike())
1097  continue;
1098  if (!CurLoop->contains(UseMI.getParent()))
1099  continue;
1100  for (unsigned i = 0, e = UseMI.getNumOperands(); i != e; ++i) {
1101  const MachineOperand &MO = UseMI.getOperand(i);
1102  if (!MO.isReg() || !MO.isUse())
1103  continue;
1104  unsigned MOReg = MO.getReg();
1105  if (MOReg != Reg)
1106  continue;
1107 
1108  if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
1109  return true;
1110  }
1111 
1112  // Only look at the first in loop use.
1113  break;
1114  }
1115 
1116  return false;
1117 }
1118 
1119 /// Return true if the instruction is marked "cheap" or the operand latency
1120 /// between its def and a use is one or less.
1121 bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
1122  if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
1123  return true;
1124 
1125  bool isCheap = false;
1126  unsigned NumDefs = MI.getDesc().getNumDefs();
1127  for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1128  MachineOperand &DefMO = MI.getOperand(i);
1129  if (!DefMO.isReg() || !DefMO.isDef())
1130  continue;
1131  --NumDefs;
1132  unsigned Reg = DefMO.getReg();
1134  continue;
1135 
1136  if (!TII->hasLowDefLatency(SchedModel, MI, i))
1137  return false;
1138  isCheap = true;
1139  }
1140 
1141  return isCheap;
1142 }
1143 
1144 /// Visit BBs from header to current BB, check if hoisting an instruction of the
1145 /// given cost matrix can cause high register pressure.
1146 bool
1147 MachineLICMBase::CanCauseHighRegPressure(const DenseMap<unsigned, int>& Cost,
1148  bool CheapInstr) {
1149  for (const auto &RPIdAndCost : Cost) {
1150  if (RPIdAndCost.second <= 0)
1151  continue;
1152 
1153  unsigned Class = RPIdAndCost.first;
1154  int Limit = RegLimit[Class];
1155 
1156  // Don't hoist cheap instructions if they would increase register pressure,
1157  // even if we're under the limit.
1158  if (CheapInstr && !HoistCheapInsts)
1159  return true;
1160 
1161  for (const auto &RP : BackTrace)
1162  if (static_cast<int>(RP[Class]) + RPIdAndCost.second >= Limit)
1163  return true;
1164  }
1165 
1166  return false;
1167 }
1168 
1169 /// Traverse the back trace from header to the current block and update their
1170 /// register pressures to reflect the effect of hoisting MI from the current
1171 /// block to the preheader.
1172 void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
1173  // First compute the 'cost' of the instruction, i.e. its contribution
1174  // to register pressure.
1175  auto Cost = calcRegisterCost(MI, /*ConsiderSeen=*/false,
1176  /*ConsiderUnseenAsDef=*/false);
1177 
1178  // Update register pressure of blocks from loop header to current block.
1179  for (auto &RP : BackTrace)
1180  for (const auto &RPIdAndCost : Cost)
1181  RP[RPIdAndCost.first] += RPIdAndCost.second;
1182 }
1183 
1184 /// Return true if it is potentially profitable to hoist the given loop
1185 /// invariant.
1186 bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
1187  if (MI.isImplicitDef())
1188  return true;
1189 
1190  // Besides removing computation from the loop, hoisting an instruction has
1191  // these effects:
1192  //
1193  // - The value defined by the instruction becomes live across the entire
1194  // loop. This increases register pressure in the loop.
1195  //
1196  // - If the value is used by a PHI in the loop, a copy will be required for
1197  // lowering the PHI after extending the live range.
1198  //
1199  // - When hoisting the last use of a value in the loop, that value no longer
1200  // needs to be live in the loop. This lowers register pressure in the loop.
1201 
1202  if (HoistConstStores && isCopyFeedingInvariantStore(MI, MRI, TRI))
1203  return true;
1204 
1205  bool CheapInstr = IsCheapInstruction(MI);
1206  bool CreatesCopy = HasLoopPHIUse(&MI);
1207 
1208  // Don't hoist a cheap instruction if it would create a copy in the loop.
1209  if (CheapInstr && CreatesCopy) {
1210  LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1211  return false;
1212  }
1213 
1214  // Rematerializable instructions should always be hoisted since the register
1215  // allocator can just pull them down again when needed.
1216  if (TII->isTriviallyReMaterializable(MI, AA))
1217  return true;
1218 
1219  // FIXME: If there are long latency loop-invariant instructions inside the
1220  // loop at this point, why didn't the optimizer's LICM hoist them?
1221  for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1222  const MachineOperand &MO = MI.getOperand(i);
1223  if (!MO.isReg() || MO.isImplicit())
1224  continue;
1225  unsigned Reg = MO.getReg();
1227  continue;
1228  if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
1229  LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI);
1230  ++NumHighLatency;
1231  return true;
1232  }
1233  }
1234 
1235  // Estimate register pressure to determine whether to LICM the instruction.
1236  // In low register pressure situation, we can be more aggressive about
1237  // hoisting. Also, favors hoisting long latency instructions even in
1238  // moderately high pressure situation.
1239  // Cheap instructions will only be hoisted if they don't increase register
1240  // pressure at all.
1241  auto Cost = calcRegisterCost(&MI, /*ConsiderSeen=*/false,
1242  /*ConsiderUnseenAsDef=*/false);
1243 
1244  // Visit BBs from header to current BB, if hoisting this doesn't cause
1245  // high register pressure, then it's safe to proceed.
1246  if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1247  LLVM_DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1248  ++NumLowRP;
1249  return true;
1250  }
1251 
1252  // Don't risk increasing register pressure if it would create copies.
1253  if (CreatesCopy) {
1254  LLVM_DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1255  return false;
1256  }
1257 
1258  // Do not "speculate" in high register pressure situation. If an
1259  // instruction is not guaranteed to be executed in the loop, it's best to be
1260  // conservative.
1261  if (AvoidSpeculation &&
1262  (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1263  LLVM_DEBUG(dbgs() << "Won't speculate: " << MI);
1264  return false;
1265  }
1266 
1267  // High register pressure situation, only hoist if the instruction is going
1268  // to be remat'ed.
1269  if (!TII->isTriviallyReMaterializable(MI, AA) &&
1271  LLVM_DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1272  return false;
1273  }
1274 
1275  return true;
1276 }
1277 
1278 /// Unfold a load from the given machineinstr if the load itself could be
1279 /// hoisted. Return the unfolded and hoistable load, or null if the load
1280 /// couldn't be unfolded or if it wouldn't be hoistable.
1281 MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
1282  // Don't unfold simple loads.
1283  if (MI->canFoldAsLoad())
1284  return nullptr;
1285 
1286  // If not, we may be able to unfold a load and hoist that.
1287  // First test whether the instruction is loading from an amenable
1288  // memory location.
1289  if (!MI->isDereferenceableInvariantLoad(AA))
1290  return nullptr;
1291 
1292  // Next determine the register class for a temporary register.
1293  unsigned LoadRegIndex;
1294  unsigned NewOpc =
1296  /*UnfoldLoad=*/true,
1297  /*UnfoldStore=*/false,
1298  &LoadRegIndex);
1299  if (NewOpc == 0) return nullptr;
1300  const MCInstrDesc &MID = TII->get(NewOpc);
1301  MachineFunction &MF = *MI->getMF();
1302  const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1303  // Ok, we're unfolding. Create a temporary register and do the unfold.
1304  unsigned Reg = MRI->createVirtualRegister(RC);
1305 
1307  bool Success = TII->unfoldMemoryOperand(MF, *MI, Reg,
1308  /*UnfoldLoad=*/true,
1309  /*UnfoldStore=*/false, NewMIs);
1310  (void)Success;
1311  assert(Success &&
1312  "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1313  "succeeded!");
1314  assert(NewMIs.size() == 2 &&
1315  "Unfolded a load into multiple instructions!");
1316  MachineBasicBlock *MBB = MI->getParent();
1318  MBB->insert(Pos, NewMIs[0]);
1319  MBB->insert(Pos, NewMIs[1]);
1320  // If unfolding produced a load that wasn't loop-invariant or profitable to
1321  // hoist, discard the new instructions and bail.
1322  if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1323  NewMIs[0]->eraseFromParent();
1324  NewMIs[1]->eraseFromParent();
1325  return nullptr;
1326  }
1327 
1328  // Update register pressure for the unfolded instruction.
1329  UpdateRegPressure(NewMIs[1]);
1330 
1331  // Otherwise we successfully unfolded a load that we can hoist.
1332  MI->eraseFromParent();
1333  return NewMIs[0];
1334 }
1335 
1336 /// Initialize the CSE map with instructions that are in the current loop
1337 /// preheader that may become duplicates of instructions that are hoisted
1338 /// out of the loop.
1339 void MachineLICMBase::InitCSEMap(MachineBasicBlock *BB) {
1340  for (MachineInstr &MI : *BB)
1341  CSEMap[MI.getOpcode()].push_back(&MI);
1342 }
1343 
1344 /// Find an instruction amount PrevMIs that is a duplicate of MI.
1345 /// Return this instruction if it's found.
1346 const MachineInstr*
1347 MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
1348  std::vector<const MachineInstr*> &PrevMIs) {
1349  for (const MachineInstr *PrevMI : PrevMIs)
1350  if (TII->produceSameValue(*MI, *PrevMI, (PreRegAlloc ? MRI : nullptr)))
1351  return PrevMI;
1352 
1353  return nullptr;
1354 }
1355 
1356 /// Given a LICM'ed instruction, look for an instruction on the preheader that
1357 /// computes the same value. If it's found, do a RAU on with the definition of
1358 /// the existing instruction rather than hoisting the instruction to the
1359 /// preheader.
1360 bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
1361  DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI) {
1362  // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1363  // the undef property onto uses.
1364  if (CI == CSEMap.end() || MI->isImplicitDef())
1365  return false;
1366 
1367  if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1368  LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1369 
1370  // Replace virtual registers defined by MI by their counterparts defined
1371  // by Dup.
1373  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1374  const MachineOperand &MO = MI->getOperand(i);
1375 
1376  // Physical registers may not differ here.
1377  assert((!MO.isReg() || MO.getReg() == 0 ||
1379  MO.getReg() == Dup->getOperand(i).getReg()) &&
1380  "Instructions with different phys regs are not identical!");
1381 
1382  if (MO.isReg() && MO.isDef() &&
1384  Defs.push_back(i);
1385  }
1386 
1388  for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
1389  unsigned Idx = Defs[i];
1390  unsigned Reg = MI->getOperand(Idx).getReg();
1391  unsigned DupReg = Dup->getOperand(Idx).getReg();
1392  OrigRCs.push_back(MRI->getRegClass(DupReg));
1393 
1394  if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
1395  // Restore old RCs if more than one defs.
1396  for (unsigned j = 0; j != i; ++j)
1397  MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1398  return false;
1399  }
1400  }
1401 
1402  for (unsigned Idx : Defs) {
1403  unsigned Reg = MI->getOperand(Idx).getReg();
1404  unsigned DupReg = Dup->getOperand(Idx).getReg();
1405  MRI->replaceRegWith(Reg, DupReg);
1406  MRI->clearKillFlags(DupReg);
1407  }
1408 
1409  MI->eraseFromParent();
1410  ++NumCSEed;
1411  return true;
1412  }
1413  return false;
1414 }
1415 
1416 /// Return true if the given instruction will be CSE'd if it's hoisted out of
1417 /// the loop.
1418 bool MachineLICMBase::MayCSE(MachineInstr *MI) {
1419  unsigned Opcode = MI->getOpcode();
1421  CI = CSEMap.find(Opcode);
1422  // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1423  // the undef property onto uses.
1424  if (CI == CSEMap.end() || MI->isImplicitDef())
1425  return false;
1426 
1427  return LookForDuplicate(MI, CI->second) != nullptr;
1428 }
1429 
1430 /// When an instruction is found to use only loop invariant operands
1431 /// that are safe to hoist, this instruction is called to do the dirty work.
1432 /// It returns true if the instruction is hoisted.
1433 bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1434  // First check whether we should hoist this instruction.
1435  if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1436  // If not, try unfolding a hoistable load.
1437  MI = ExtractHoistableLoad(MI);
1438  if (!MI) return false;
1439  }
1440 
1441  // If we have hoisted an instruction that may store, it can only be a constant
1442  // store.
1443  if (MI->mayStore())
1444  NumStoreConst++;
1445 
1446  // Now move the instructions to the predecessor, inserting it before any
1447  // terminator instructions.
1448  LLVM_DEBUG({
1449  dbgs() << "Hoisting " << *MI;
1450  if (MI->getParent()->getBasicBlock())
1451  dbgs() << " from " << printMBBReference(*MI->getParent());
1452  if (Preheader->getBasicBlock())
1453  dbgs() << " to " << printMBBReference(*Preheader);
1454  dbgs() << "\n";
1455  });
1456 
1457  // If this is the first instruction being hoisted to the preheader,
1458  // initialize the CSE map with potential common expressions.
1459  if (FirstInLoop) {
1460  InitCSEMap(Preheader);
1461  FirstInLoop = false;
1462  }
1463 
1464  // Look for opportunity to CSE the hoisted instruction.
1465  unsigned Opcode = MI->getOpcode();
1467  CI = CSEMap.find(Opcode);
1468  if (!EliminateCSE(MI, CI)) {
1469  // Otherwise, splice the instruction to the preheader.
1470  Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1471 
1472  // Since we are moving the instruction out of its basic block, we do not
1473  // retain its debug location. Doing so would degrade the debugging
1474  // experience and adversely affect the accuracy of profiling information.
1475  MI->setDebugLoc(DebugLoc());
1476 
1477  // Update register pressure for BBs from header to this block.
1478  UpdateBackTraceRegPressure(MI);
1479 
1480  // Clear the kill flags of any register this instruction defines,
1481  // since they may need to be live throughout the entire loop
1482  // rather than just live for part of it.
1483  for (MachineOperand &MO : MI->operands())
1484  if (MO.isReg() && MO.isDef() && !MO.isDead())
1485  MRI->clearKillFlags(MO.getReg());
1486 
1487  // Add to the CSE map.
1488  if (CI != CSEMap.end())
1489  CI->second.push_back(MI);
1490  else
1491  CSEMap[Opcode].push_back(MI);
1492  }
1493 
1494  ++NumHoisted;
1495  Changed = true;
1496 
1497  return true;
1498 }
1499 
1500 /// Get the preheader for the current loop, splitting a critical edge if needed.
1501 MachineBasicBlock *MachineLICMBase::getCurPreheader() {
1502  // Determine the block to which to hoist instructions. If we can't find a
1503  // suitable loop predecessor, we can't do any hoisting.
1504 
1505  // If we've tried to get a preheader and failed, don't try again.
1506  if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1507  return nullptr;
1508 
1509  if (!CurPreheader) {
1510  CurPreheader = CurLoop->getLoopPreheader();
1511  if (!CurPreheader) {
1512  MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1513  if (!Pred) {
1514  CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1515  return nullptr;
1516  }
1517 
1518  CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), *this);
1519  if (!CurPreheader) {
1520  CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1521  return nullptr;
1522  }
1523  }
1524  }
1525  return CurPreheader;
1526 }
BitVector & set()
Definition: BitVector.h:398
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_begin()
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
instr_iterator instr_end()
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
Definition: LoopInfoImpl.h:174
virtual const TargetLowering * getTargetLowering() const
bool test(unsigned Idx) const
Definition: BitVector.h:502
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every &#39;0&#39; bit in Mask.
Definition: BitVector.h:788
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
block Block Frequency true
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock *> &ExitBlocks)
Return true if the specified block is in the list.
Definition: LCSSA.cpp:66
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
bool isCopyLike() const
Return true if the instruction behaves like a copy.
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool...
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
A description of a memory reference used in the backend.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:412
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
BlockT * getHeader() const
Definition: LoopInfo.h:100
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void getExitBlocks(SmallVectorImpl< BlockT *> &ExitBlocks) const
Return all of the successor blocks of this loop.
Definition: LoopInfoImpl.h:63
Machine Loop Invariant Code Motion
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
void clear()
Definition: SmallSet.h:219
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
#define DEBUG_TYPE
Definition: MachineLICM.cpp:57
Base class for the actual dominator tree node.
const std::vector< DomTreeNodeBase * > & getChildren() const
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:363
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn&#39;t ...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
iterator begin() const
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
NodeT * getBlock() const
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:820
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:516
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
Machine Loop Invariant Code false early Early Machine Loop Invariant Code static false bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop)
Test if the given loop is the outer-most loop that has a unique predecessor.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:181
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
void getExitingBlocks(SmallVectorImpl< BlockT *> &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:35
bool isCopy() const
bool isImplicitDef() const
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void initializeMachineLICMPass(PassRegistry &)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
BlockT * getLoopPredecessor() const
If the given loop&#39;s header has exactly one unique predecessor outside the loop, return it...
Definition: LoopInfoImpl.h:202
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:110
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
iterator begin() const
Definition: LoopInfo.h:142
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:381
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Machine Loop Invariant Code false early machinelicm
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:225
unsigned pred_size() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
Special value supplied for machine level alias analysis.
iterator end() const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
unsigned succ_size() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
#define Success
LoopT * getParentLoop() const
Definition: LoopInfo.h:101
Representation of each machine instruction.
Definition: MachineInstr.h:64
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isEHPad() const
Returns true if the block is a landing pad.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:459
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:149
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:753
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
iterator end()
Definition: DenseMap.h:79
INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE, "Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_END(MachineLICM
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator end() const
Definition: LoopInfo.h:143
virtual bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
void initializeEarlyMachineLICMPass(PassRegistry &)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool memoperands_empty() const
Return true if we don&#39;t have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:546
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
LLVM Value Representation.
Definition: Value.h:73
static cl::opt< bool > SinkInstsToAvoidSpills("sink-insts-to-avoid-spills", cl::desc("MachineLICM should sink instructions into " "loops to avoid register spills"), cl::init(false), cl::Hidden)
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
This file describes how to lower LLVM code to machine code.
bool isImplicit() const
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
void resize(size_type N)
Definition: SmallVector.h:351
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1101