LLVM  10.0.0svn
RISCVBaseInfo.h
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1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCInstrDesc.h"
21 
22 namespace llvm {
23 
24 // RISCVII - This namespace holds all of the target specific flags that
25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
26 namespace RISCVII {
27 enum {
46 
48 };
49 
50 enum {
64 };
65 } // namespace RISCVII
66 
67 namespace RISCVOp {
68 enum OperandType : unsigned {
79 };
80 } // namespace RISCVOp
81 
82 // Describes the predecessor/successor bits used in the FENCE instruction.
83 namespace RISCVFenceField {
84 enum FenceField {
85  I = 8,
86  O = 4,
87  R = 2,
88  W = 1
89 };
90 }
91 
92 // Describes the supported floating point rounding mode encodings.
93 namespace RISCVFPRndMode {
95  RNE = 0,
96  RTZ = 1,
97  RDN = 2,
98  RUP = 3,
99  RMM = 4,
100  DYN = 7,
101  Invalid
102 };
103 
105  switch (RndMode) {
106  default:
107  llvm_unreachable("Unknown floating point rounding mode");
108  case RISCVFPRndMode::RNE:
109  return "rne";
110  case RISCVFPRndMode::RTZ:
111  return "rtz";
112  case RISCVFPRndMode::RDN:
113  return "rdn";
114  case RISCVFPRndMode::RUP:
115  return "rup";
116  case RISCVFPRndMode::RMM:
117  return "rmm";
118  case RISCVFPRndMode::DYN:
119  return "dyn";
120  }
121 }
122 
124  return StringSwitch<RoundingMode>(Str)
125  .Case("rne", RISCVFPRndMode::RNE)
126  .Case("rtz", RISCVFPRndMode::RTZ)
127  .Case("rdn", RISCVFPRndMode::RDN)
128  .Case("rup", RISCVFPRndMode::RUP)
129  .Case("rmm", RISCVFPRndMode::RMM)
130  .Case("dyn", RISCVFPRndMode::DYN)
132 }
133 
134 inline static bool isValidRoundingMode(unsigned Mode) {
135  switch (Mode) {
136  default:
137  return false;
138  case RISCVFPRndMode::RNE:
139  case RISCVFPRndMode::RTZ:
140  case RISCVFPRndMode::RDN:
141  case RISCVFPRndMode::RUP:
142  case RISCVFPRndMode::RMM:
143  case RISCVFPRndMode::DYN:
144  return true;
145  }
146 }
147 } // namespace RISCVFPRndMode
148 
149 namespace RISCVSysReg {
150 struct SysReg {
151  const char *Name;
152  unsigned Encoding;
153  // FIXME: add these additional fields when needed.
154  // Privilege Access: Read, Write, Read-Only.
155  // unsigned ReadWrite;
156  // Privilege Mode: User, System or Machine.
157  // unsigned Mode;
158  // Check field name.
159  // unsigned Extra;
160  // Register number without the privilege bits.
161  // unsigned Number;
164 
165  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
166  // Not in 32-bit mode.
167  if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
168  return false;
169  // No required feature associated with the system register.
170  if (FeaturesRequired.none())
171  return true;
172  return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
173  }
174 };
175 
176 #define GET_SysRegsList_DECL
177 #include "RISCVGenSystemOperands.inc"
178 } // end namespace RISCVSysReg
179 
180 namespace RISCVABI {
181 
182 enum ABI {
191 };
192 
193 // Returns the target ABI, or else a StringError if the requested ABIName is
194 // not supported for the given TT and FeatureBits combination.
195 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
196  StringRef ABIName);
197 
198 } // namespace RISCVABI
199 
200 namespace RISCVFeatures {
201 
202 // Validates if the given combination of features are valid for the target
203 // triple. Exits with report_fatal_error if not.
204 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
205 
206 } // namespace RISCVFeatures
207 
208 } // namespace llvm
209 
210 #endif
static bool isValidRoundingMode(unsigned Mode)
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
SI Whole Quad Mode
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static RoundingMode stringToRoundingMode(StringRef Str)
bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
FeatureBitset FeaturesRequired
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
Container class for subtarget features.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
#define I(x, y, z)
Definition: MD5.cpp:58
static StringRef roundingModeToString(RoundingMode RndMode)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void validate(const Triple &TT, const FeatureBitset &FeatureBits)