LLVM 19.0.0git
RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
25
26namespace llvm {
27
28// RISCVII - This namespace holds all of the target specific flags that
29// instruction info tracks. All definitions must match RISCVInstrFormats.td.
30namespace RISCVII {
31enum {
55
58
64
67
68 // Force a tail agnostic policy even this instruction has a tied destination.
71
72 // Is this a _TIED vector pseudo instruction. For these instructions we
73 // shouldn't skip the tied operand when converting to MC instructions.
76
77 // Does this instruction have a SEW operand. It will be the last explicit
78 // operand unless there is a vector policy operand. Used by RVV Pseudos.
81
82 // Does this instruction have a VL operand. It will be the second to last
83 // explicit operand unless there is a vector policy operand. Used by RVV
84 // Pseudos.
87
88 // Does this instruction have a vector policy operand. It will be the last
89 // explicit operand. Used by RVV Pseudos.
92
93 // Is this instruction a vector widening reduction instruction. Used by RVV
94 // Pseudos.
97
98 // Does this instruction care about mask policy. If it is not, the mask policy
99 // could be either agnostic or undisturbed. For example, unmasked, store, and
100 // reduction operations result would not be affected by mask policy, so
101 // compiler has free to select either one.
104
105 // Indicates that the result can be considered sign extended from bit 31. Some
106 // instructions with this flag aren't W instructions, but are either sign
107 // extended from a smaller size, always outputs a small integer, or put zeros
108 // in bits 63:31. Used by the SExtWRemoval pass.
111
114
117
118 // Indicates whether these instructions can partially overlap between source
119 // registers and destination registers according to the vector spec.
120 // 0 -> not a vector pseudo
121 // 1 -> default value for vector pseudos. not widening or narrowing.
122 // 2 -> narrowing case
123 // 3 -> widening case
126};
127
128// Helper functions to read TSFlags.
129/// \returns the format of the instruction.
130static inline unsigned getFormat(uint64_t TSFlags) {
131 return (TSFlags & InstFormatMask) >> InstFormatShift;
132}
133/// \returns the LMUL for the instruction.
134static inline VLMUL getLMul(uint64_t TSFlags) {
135 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
136}
137/// \returns true if tail agnostic is enforced for the instruction.
138static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
139 return TSFlags & ForceTailAgnosticMask;
140}
141/// \returns true if this a _TIED pseudo.
142static inline bool isTiedPseudo(uint64_t TSFlags) {
143 return TSFlags & IsTiedPseudoMask;
144}
145/// \returns true if there is a SEW operand for the instruction.
146static inline bool hasSEWOp(uint64_t TSFlags) {
147 return TSFlags & HasSEWOpMask;
148}
149/// \returns true if there is a VL operand for the instruction.
150static inline bool hasVLOp(uint64_t TSFlags) {
151 return TSFlags & HasVLOpMask;
152}
153/// \returns true if there is a vector policy operand for this instruction.
154static inline bool hasVecPolicyOp(uint64_t TSFlags) {
155 return TSFlags & HasVecPolicyOpMask;
156}
157/// \returns true if it is a vector widening reduction instruction.
158static inline bool isRVVWideningReduction(uint64_t TSFlags) {
159 return TSFlags & IsRVVWideningReductionMask;
160}
161/// \returns true if mask policy is valid for the instruction.
162static inline bool usesMaskPolicy(uint64_t TSFlags) {
163 return TSFlags & UsesMaskPolicyMask;
164}
165
166/// \returns true if there is a rounding mode operand for this instruction
167static inline bool hasRoundModeOp(uint64_t TSFlags) {
168 return TSFlags & HasRoundModeOpMask;
169}
170
171/// \returns true if this instruction uses vxrm
172static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
173
174static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
175 const uint64_t TSFlags = Desc.TSFlags;
176 // This method is only called if we expect to have a VL operand, and all
177 // instructions with VL also have SEW.
178 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
179 unsigned Offset = 2;
180 if (hasVecPolicyOp(TSFlags))
181 Offset = 3;
182 return Desc.getNumOperands() - Offset;
183}
184
185static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
186 const uint64_t TSFlags = Desc.TSFlags;
187 assert(hasSEWOp(TSFlags));
188 unsigned Offset = 1;
189 if (hasVecPolicyOp(TSFlags))
190 Offset = 2;
191 return Desc.getNumOperands() - Offset;
192}
193
194static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
195 assert(hasVecPolicyOp(Desc.TSFlags));
196 return Desc.getNumOperands() - 1;
197}
198
199/// \returns the index to the rounding mode immediate value if any, otherwise
200/// returns -1.
201static inline int getFRMOpNum(const MCInstrDesc &Desc) {
202 const uint64_t TSFlags = Desc.TSFlags;
203 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
204 return -1;
205
206 // The operand order
207 // --------------------------------------
208 // | n-1 (if any) | n-2 | n-3 | n-4 |
209 // | policy | sew | vl | frm |
210 // --------------------------------------
211 return getVLOpNum(Desc) - 1;
212}
213
214/// \returns the index to the rounding mode immediate value if any, otherwise
215/// returns -1.
216static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
217 const uint64_t TSFlags = Desc.TSFlags;
218 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
219 return -1;
220 // The operand order
221 // --------------------------------------
222 // | n-1 (if any) | n-2 | n-3 | n-4 |
223 // | policy | sew | vl | vxrm |
224 // --------------------------------------
225 return getVLOpNum(Desc) - 1;
226}
227
228// Is the first def operand tied to the first use operand. This is true for
229// vector pseudo instructions that have a merge operand for tail/mask
230// undisturbed. It's also true for vector FMA instructions where one of the
231// operands is also the destination register.
232static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
233 return Desc.getNumDefs() < Desc.getNumOperands() &&
234 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
235}
236
237// RISC-V Specific Machine Operand Flags
238enum {
241 MO_LO = 3,
242 MO_HI = 4,
255
256 // Used to differentiate between target-specific "direct" flags and "bitmask"
257 // flags. A machine operand can only have one "direct" flag, but can have
258 // multiple "bitmask" flags.
261} // namespace RISCVII
262
263namespace RISCVOp {
264enum OperandType : unsigned {
301 // Operand is either a register or uimm5, this is used by V extension pseudo
302 // instructions to represent a value that be passed as AVL to either vsetvli
303 // or vsetivli.
305};
306} // namespace RISCVOp
307
308// Describes the predecessor/successor bits used in the FENCE instruction.
309namespace RISCVFenceField {
311 I = 8,
312 O = 4,
313 R = 2,
314 W = 1
316}
317
318// Describes the supported floating point rounding mode encodings.
319namespace RISCVFPRndMode {
321 RNE = 0,
322 RTZ = 1,
323 RDN = 2,
324 RUP = 3,
325 RMM = 4,
326 DYN = 7,
327 Invalid
329
331 switch (RndMode) {
332 default:
333 llvm_unreachable("Unknown floating point rounding mode");
335 return "rne";
337 return "rtz";
339 return "rdn";
341 return "rup";
343 return "rmm";
345 return "dyn";
346 }
347}
348
358}
359
360inline static bool isValidRoundingMode(unsigned Mode) {
361 switch (Mode) {
362 default:
363 return false;
370 return true;
371 }
372}
373} // namespace RISCVFPRndMode
374
375//===----------------------------------------------------------------------===//
376// Floating-point Immediates
377//
378
379namespace RISCVLoadFPImm {
380float getFPImm(unsigned Imm);
381
382/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
383/// immediate value. If the value cannot be represented as a 5-bit binary
384/// encoding, then return -1.
385int getLoadFPImm(APFloat FPImm);
386} // namespace RISCVLoadFPImm
387
388namespace RISCVSysReg {
389struct SysReg {
390 const char *Name;
391 const char *AltName;
392 const char *DeprecatedName;
393 unsigned Encoding;
394 // FIXME: add these additional fields when needed.
395 // Privilege Access: Read, Write, Read-Only.
396 // unsigned ReadWrite;
397 // Privilege Mode: User, System or Machine.
398 // unsigned Mode;
399 // Check field name.
400 // unsigned Extra;
401 // Register number without the privilege bits.
402 // unsigned Number;
405
406 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
407 // Not in 32-bit mode.
408 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
409 return false;
410 // No required feature associated with the system register.
412 return true;
413 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
414 }
415};
416
417#define GET_SysRegsList_DECL
418#include "RISCVGenSearchableTables.inc"
419} // end namespace RISCVSysReg
420
421namespace RISCVInsnOpcode {
423 const char *Name;
424 unsigned Value;
425};
426
427#define GET_RISCVOpcodesList_DECL
428#include "RISCVGenSearchableTables.inc"
429} // end namespace RISCVInsnOpcode
430
431namespace RISCVABI {
432
433enum ABI {
444
445// Returns the target ABI, or else a StringError if the requested ABIName is
446// not supported for the given TT and FeatureBits combination.
447ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
448 StringRef ABIName);
449
450ABI getTargetABI(StringRef ABIName);
451
452// Returns the register used to hold the stack pointer after realignment.
454
455// Returns the register holding shadow call stack pointer.
457
458} // namespace RISCVABI
459
460namespace RISCVFeatures {
461
462// Validates if the given combination of features are valid for the target
463// triple. Exits with report_fatal_error if not.
464void validate(const Triple &TT, const FeatureBitset &FeatureBits);
465
467parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
468
469} // namespace RISCVFeatures
470
471namespace RISCVRVC {
472bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
473bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
474} // namespace RISCVRVC
475
476namespace RISCVZC {
478 RA = 4,
489 // note - to include s10, s11 must also be included
492};
493
494inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
495 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
496 switch (EndReg) {
497 case RISCV::X1:
498 return RLISTENCODE::RA;
499 case RISCV::X8:
500 return RLISTENCODE::RA_S0;
501 case RISCV::X9:
503 case RISCV::X18:
505 case RISCV::X19:
507 case RISCV::X20:
509 case RISCV::X21:
511 case RISCV::X22:
513 case RISCV::X23:
515 case RISCV::X24:
517 case RISCV::X25:
519 case RISCV::X26:
521 case RISCV::X27:
523 default:
524 llvm_unreachable("Undefined input.");
525 }
526}
527
528inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
529 bool IsEABI) {
531 "{ra, s0-s10} is not supported, s11 must be included.");
532 if (IsEABI)
533 return 16;
534 if (!IsRV64) {
535 switch (RlistVal) {
536 case RLISTENCODE::RA:
540 return 16;
545 return 32;
549 return 48;
551 return 64;
552 }
553 } else {
554 switch (RlistVal) {
555 case RLISTENCODE::RA:
557 return 16;
560 return 32;
563 return 48;
566 return 64;
569 return 80;
571 return 96;
573 return 112;
574 }
575 }
576 llvm_unreachable("Unexpected RlistVal");
577}
578
579inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
580 int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
581 if (RlistVal == RLISTENCODE::INVALID_RLIST)
582 return false;
583 unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
584 SpimmVal = (StackAdjustment - stackAdj) / 16;
585 if (SpimmVal > 3)
586 return false;
587 return true;
588}
589
590void printRlist(unsigned SlistEncode, raw_ostream &OS);
591void printSpimm(int64_t Spimm, raw_ostream &OS);
592} // namespace RISCVZC
593
594} // namespace llvm
595
596#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:474
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
@ TargetOverlapConstraintTypeMask
@ TargetOverlapConstraintTypeShift
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:95
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:96
static int getFRMOpNum(const MCInstrDesc &Desc)
static int getVXRMOpNum(const MCInstrDesc &Desc)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool usesVXRM(uint64_t TSFlags)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, bool IsEABI)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64, bool IsEABI)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Description of the encoding of one expression Op.
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const