LLVM  7.0.0svn
TargetSchedule.h
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1 //===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a wrapper around MCSchedModel that allows the interface to
11 // benefit from information currently only available in TargetInstrInfo.
12 // Ideally, the scheduling interface would be fully defined in the MC layer.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
17 #define LLVM_CODEGEN_TARGETSCHEDULE_H
18 
19 #include "llvm/ADT/Optional.h"
20 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/MCSchedule.h"
24 
25 namespace llvm {
26 
27 class MachineInstr;
28 class TargetInstrInfo;
29 
30 /// Provide an instruction scheduling machine model to CodeGen passes.
32  // For efficiency, hold a copy of the statically defined MCSchedModel for this
33  // processor.
34  MCSchedModel SchedModel;
35  InstrItineraryData InstrItins;
36  const TargetSubtargetInfo *STI = nullptr;
37  const TargetInstrInfo *TII = nullptr;
38 
39  SmallVector<unsigned, 16> ResourceFactors;
40  unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
41  unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor.
42 
43  unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
44 
45 public:
46  TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
47 
48  /// \brief Initialize the machine model for instruction scheduling.
49  ///
50  /// The machine model API keeps a copy of the top-level MCSchedModel table
51  /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
52  /// dynamic properties.
53  void init(const TargetSubtargetInfo *TSInfo);
54 
55  /// Return the MCSchedClassDesc for this instruction.
57 
58  /// \brief TargetSubtargetInfo getter.
59  const TargetSubtargetInfo *getSubtargetInfo() const { return STI; }
60 
61  /// \brief TargetInstrInfo getter.
62  const TargetInstrInfo *getInstrInfo() const { return TII; }
63 
64  /// \brief Return true if this machine model includes an instruction-level
65  /// scheduling model.
66  ///
67  /// This is more detailed than the course grain IssueWidth and default
68  /// latency properties, but separate from the per-cycle itinerary data.
69  bool hasInstrSchedModel() const;
70 
71  const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
72 
73  /// \brief Return true if this machine model includes cycle-to-cycle itinerary
74  /// data.
75  ///
76  /// This models scheduling at each stage in the processor pipeline.
77  bool hasInstrItineraries() const;
78 
80  if (hasInstrItineraries())
81  return &InstrItins;
82  return nullptr;
83  }
84 
85  /// \brief Return true if this machine model includes an instruction-level
86  /// scheduling model or cycle-to-cycle itinerary data.
89  }
90 
91  /// \brief Identify the processor corresponding to the current subtarget.
92  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
93 
94  /// \brief Maximum number of micro-ops that may be scheduled per cycle.
95  unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
96 
97  /// \brief Return true if new group must begin.
98  bool mustBeginGroup(const MachineInstr *MI,
99  const MCSchedClassDesc *SC = nullptr) const;
100  /// \brief Return true if current group must end.
101  bool mustEndGroup(const MachineInstr *MI,
102  const MCSchedClassDesc *SC = nullptr) const;
103 
104  /// \brief Return the number of issue slots required for this MI.
105  unsigned getNumMicroOps(const MachineInstr *MI,
106  const MCSchedClassDesc *SC = nullptr) const;
107 
108  /// \brief Get the number of kinds of resources for this target.
109  unsigned getNumProcResourceKinds() const {
110  return SchedModel.getNumProcResourceKinds();
111  }
112 
113  /// \brief Get a processor resource by ID for convenience.
114  const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
115  return SchedModel.getProcResource(PIdx);
116  }
117 
118 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
119  const char *getResourceName(unsigned PIdx) const {
120  if (!PIdx)
121  return "MOps";
122  return SchedModel.getProcResource(PIdx)->Name;
123  }
124 #endif
125 
127 
128  // \brief Get an iterator into the processor resources consumed by this
129  // scheduling class.
131  // The subtarget holds a single resource table for all processors.
132  return STI->getWriteProcResBegin(SC);
133  }
135  return STI->getWriteProcResEnd(SC);
136  }
137 
138  /// \brief Multiply the number of units consumed for a resource by this factor
139  /// to normalize it relative to other resources.
140  unsigned getResourceFactor(unsigned ResIdx) const {
141  return ResourceFactors[ResIdx];
142  }
143 
144  /// \brief Multiply number of micro-ops by this factor to normalize it
145  /// relative to other resources.
146  unsigned getMicroOpFactor() const {
147  return MicroOpFactor;
148  }
149 
150  /// \brief Multiply cycle count by this factor to normalize it relative to
151  /// other resources. This is the number of resource units per cycle.
152  unsigned getLatencyFactor() const {
153  return ResourceLCM;
154  }
155 
156  /// \brief Number of micro-ops that may be buffered for OOO execution.
157  unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
158 
159  /// \brief Number of resource units that may be buffered for OOO execution.
160  /// \return The buffer size in resource units or -1 for unlimited.
161  int getResourceBufferSize(unsigned PIdx) const {
162  return SchedModel.getProcResource(PIdx)->BufferSize;
163  }
164 
165  /// \brief Compute operand latency based on the available machine model.
166  ///
167  /// Compute and return the latency of the given data dependent def and use
168  /// when the operand indices are already known. UseMI may be NULL for an
169  /// unknown user.
170  unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
171  const MachineInstr *UseMI, unsigned UseOperIdx)
172  const;
173 
174  /// \brief Compute the instruction latency based on the available machine
175  /// model.
176  ///
177  /// Compute and return the expected latency of this instruction independent of
178  /// a particular use. computeOperandLatency is the preferred API, but this is
179  /// occasionally useful to help estimate instruction cost.
180  ///
181  /// If UseDefaultDefLatency is false and no new machine sched model is
182  /// present this method falls back to TII->getInstrLatency with an empty
183  /// instruction itinerary (this is so we preserve the previous behavior of the
184  /// if converter after moving it to TargetSchedModel).
185  unsigned computeInstrLatency(const MachineInstr *MI,
186  bool UseDefaultDefLatency = true) const;
187  unsigned computeInstrLatency(unsigned Opcode) const;
188 
189 
190  /// \brief Output dependency latency of a pair of defs of the same register.
191  ///
192  /// This is typically one cycle.
193  unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
194  const MachineInstr *DepMI) const;
195 
196  /// \brief Compute the reciprocal throughput of the given instruction.
198  Optional<double> computeReciprocalThroughput(unsigned Opcode) const;
199 };
200 
201 } // end namespace llvm
202 
203 #endif // LLVM_CODEGEN_TARGETSCHEDULE_H
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
unsigned MicroOpBufferSize
Definition: MCSchedule.h:221
ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned IssueWidth
Definition: MCSchedule.h:204
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:287
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const
unsigned getProcessorID() const
Definition: MCSchedule.h:265
unsigned getMicroOpBufferSize() const
Number of micro-ops that may be buffered for OOO execution.
bool hasInstrSchedModelOrItineraries() const
Return true if this machine model includes an instruction-level scheduling model or cycle-to-cycle it...
Optional< double > computeReciprocalThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
const TargetSubtargetInfo * getSubtargetInfo() const
TargetSubtargetInfo getter.
Provide an instruction scheduling machine model to CodeGen passes.
const InstrItineraryData * getInstrItineraries() const
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
Itinerary data supplied by a subtarget to be used by a target.
const char * getResourceName(unsigned PIdx) const
TargetInstrInfo - Interface to description of machine instruction set.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:62
MachineInstrBuilder & UseMI
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:108
unsigned getLatencyFactor() const
Multiply cycle count by this factor to normalize it relative to other resources.
unsigned getProcessorID() const
Identify the processor corresponding to the current subtarget.
int getResourceBufferSize(unsigned PIdx) const
Number of resource units that may be buffered for OOO execution.
const MCSchedModel * getMCSchedModel() const
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if current group must end.
bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if new group must begin.
Define a kind of processor resource that will be modeled by the scheduler.
Definition: MCSchedule.h:30
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getMicroOpFactor() const
Multiply number of micro-ops by this factor to normalize it relative to other resources.
CHAIN = SC CHAIN, Imm128 - System call.
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
unsigned getResourceFactor(unsigned ResIdx) const
Multiply the number of units consumed for a resource by this factor to normalize it relative to other...
unsigned getNumProcResourceKinds() const
Get the number of kinds of resources for this target.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:60
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
const MCProcResourceDesc * getProcResource(unsigned PIdx) const
Get a processor resource by ID for convenience.
const TargetInstrInfo * getInstrInfo() const
TargetInstrInfo getter.
IRTranslator LLVM IR MI
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:201
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:283