LLVM  7.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
43 #include "llvm/Transforms/Scalar.h"
45 #include <cassert>
46 #include <string>
47 
48 using namespace llvm;
49 
50 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
51  cl::desc("Enable interprocedural register allocation "
52  "to reduce load/store at procedure calls."));
53 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
54  cl::desc("Disable Post Regalloc Scheduler"));
55 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
56  cl::desc("Disable branch folding"));
57 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
58  cl::desc("Disable tail duplication"));
59 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
60  cl::desc("Disable pre-register allocation tail duplication"));
61 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
62  cl::Hidden, cl::desc("Disable probability-driven block placement"));
63 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
64  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
65 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
66  cl::desc("Disable Stack Slot Coloring"));
67 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
68  cl::desc("Disable Machine Dead Code Elimination"));
69 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
70  cl::desc("Disable Early If-conversion"));
71 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
72  cl::desc("Disable Machine LICM"));
73 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
74  cl::desc("Disable Machine Common Subexpression Elimination"));
76  "optimize-regalloc", cl::Hidden,
77  cl::desc("Enable optimized register allocation compilation path."));
78 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
79  cl::Hidden,
80  cl::desc("Disable Machine LICM"));
81 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
82  cl::desc("Disable Machine Sinking"));
83 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
84  cl::desc("Disable Loop Strength Reduction Pass"));
85 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
86  cl::Hidden, cl::desc("Disable ConstantHoisting"));
87 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
88  cl::desc("Disable Codegen Prepare"));
89 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
90  cl::desc("Disable Copy Propagation pass"));
91 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
92  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
94  "enable-implicit-null-checks",
95  cl::desc("Fold null checks into faulting memory operations"),
96  cl::init(false), cl::Hidden);
97 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
98  cl::desc("Disable MergeICmps Pass"),
99  cl::init(false), cl::Hidden);
100 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
101  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
102 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
103  cl::desc("Print LLVM IR input to isel pass"));
104 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
105  cl::desc("Dump garbage collector data"));
106 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
107  cl::desc("Verify generated machine code"),
108  cl::init(false),
110 static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
111  cl::Hidden,
112  cl::desc("Enable machine outliner"));
114  "enable-linkonceodr-outlining",
115  cl::Hidden,
116  cl::desc("Enable the machine outliner on linkonceodr functions"),
117  cl::init(false));
118 // Enable or disable FastISel. Both options are needed, because
119 // FastISel is enabled by default with -fast, and we wish to be
120 // able to enable or disable fast-isel independently from -O0.
122 EnableFastISelOption("fast-isel", cl::Hidden,
123  cl::desc("Enable the \"fast\" instruction selector"));
124 
126  "global-isel", cl::Hidden,
127  cl::desc("Enable the \"global\" instruction selector"));
128 
130  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
131  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
132 
134  "global-isel-abort", cl::Hidden,
135  cl::desc("Enable abort calls when \"global\" instruction selection "
136  "fails to lower/select an instruction: 0 disable the abort, "
137  "1 enable the abort, and "
138  "2 disable the abort but emit a diagnostic on failure"),
139  cl::init(1));
140 
141 // Temporary option to allow experimenting with MachineScheduler as a post-RA
142 // scheduler. Targets can "properly" enable this with
143 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
144 // Targets can return true in targetSchedulesPostRAScheduling() and
145 // insert a PostRA scheduling pass wherever it wants.
146 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
147  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
148 
149 // Experimental option to run live interval analysis early.
150 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
151  cl::desc("Run live interval analysis earlier in the pipeline"));
152 
153 // Experimental option to use CFL-AA in codegen
156  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
157  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
158  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
160  "Enable unification-based CFL-AA"),
162  "Enable inclusion-based CFL-AA"),
163  clEnumValN(CFLAAType::Both, "both",
164  "Enable both variants of CFL-AA")));
165 
166 /// Option names for limiting the codegen pipeline.
167 /// Those are used in error reporting and we didn't want
168 /// to duplicate their names all over the place.
169 const char *StartAfterOptName = "start-after";
170 const char *StartBeforeOptName = "start-before";
171 const char *StopAfterOptName = "stop-after";
172 const char *StopBeforeOptName = "stop-before";
173 
175  StartAfterOpt(StringRef(StartAfterOptName),
176  cl::desc("Resume compilation after a specific pass"),
177  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
178 
180  StartBeforeOpt(StringRef(StartBeforeOptName),
181  cl::desc("Resume compilation before a specific pass"),
182  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
183 
185  StopAfterOpt(StringRef(StopAfterOptName),
186  cl::desc("Stop compilation after a specific pass"),
187  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
188 
190  StopBeforeOpt(StringRef(StopBeforeOptName),
191  cl::desc("Stop compilation before a specific pass"),
192  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
193 
194 /// Allow standard passes to be disabled by command line options. This supports
195 /// simple binary flags that either suppress the pass or do nothing.
196 /// i.e. -disable-mypass=false has no effect.
197 /// These should be converted to boolOrDefault in order to use applyOverride.
199  bool Override) {
200  if (Override)
201  return IdentifyingPassPtr();
202  return PassID;
203 }
204 
205 /// Allow standard passes to be disabled by the command line, regardless of who
206 /// is adding the pass.
207 ///
208 /// StandardID is the pass identified in the standard pass pipeline and provided
209 /// to addPass(). It may be a target-specific ID in the case that the target
210 /// directly adds its own pass, but in that case we harmlessly fall through.
211 ///
212 /// TargetID is the pass that the target has configured to override StandardID.
213 ///
214 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
215 /// pass to run. This allows multiple options to control a single pass depending
216 /// on where in the pipeline that pass is added.
218  IdentifyingPassPtr TargetID) {
219  if (StandardID == &PostRASchedulerID)
220  return applyDisable(TargetID, DisablePostRASched);
221 
222  if (StandardID == &BranchFolderPassID)
223  return applyDisable(TargetID, DisableBranchFold);
224 
225  if (StandardID == &TailDuplicateID)
226  return applyDisable(TargetID, DisableTailDuplicate);
227 
228  if (StandardID == &EarlyTailDuplicateID)
229  return applyDisable(TargetID, DisableEarlyTailDup);
230 
231  if (StandardID == &MachineBlockPlacementID)
232  return applyDisable(TargetID, DisableBlockPlacement);
233 
234  if (StandardID == &StackSlotColoringID)
235  return applyDisable(TargetID, DisableSSC);
236 
237  if (StandardID == &DeadMachineInstructionElimID)
238  return applyDisable(TargetID, DisableMachineDCE);
239 
240  if (StandardID == &EarlyIfConverterID)
241  return applyDisable(TargetID, DisableEarlyIfConversion);
242 
243  if (StandardID == &EarlyMachineLICMID)
244  return applyDisable(TargetID, DisableMachineLICM);
245 
246  if (StandardID == &MachineCSEID)
247  return applyDisable(TargetID, DisableMachineCSE);
248 
249  if (StandardID == &MachineLICMID)
250  return applyDisable(TargetID, DisablePostRAMachineLICM);
251 
252  if (StandardID == &MachineSinkingID)
253  return applyDisable(TargetID, DisableMachineSink);
254 
255  if (StandardID == &MachineCopyPropagationID)
256  return applyDisable(TargetID, DisableCopyProp);
257 
258  return TargetID;
259 }
260 
261 //===---------------------------------------------------------------------===//
262 /// TargetPassConfig
263 //===---------------------------------------------------------------------===//
264 
265 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
266  "Target Pass Configuration", false, false)
267 char TargetPassConfig::ID = 0;
268 
269 namespace {
270 
271 struct InsertedPass {
276 
277  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
278  bool VerifyAfter, bool PrintAfter)
279  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
280  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
281 
283  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
284  if (InsertedPassID.isInstance())
285  return InsertedPassID.getInstance();
286  Pass *NP = Pass::createPass(InsertedPassID.getID());
287  assert(NP && "Pass ID not registered");
288  return NP;
289  }
290 };
291 
292 } // end anonymous namespace
293 
294 namespace llvm {
295 
297 public:
298  // List of passes explicitly substituted by this target. Normally this is
299  // empty, but it is a convenient way to suppress or replace specific passes
300  // that are part of a standard pass pipeline without overridding the entire
301  // pipeline. This mechanism allows target options to inherit a standard pass's
302  // user interface. For example, a target may disable a standard pass by
303  // default by substituting a pass ID of zero, and the user may still enable
304  // that standard pass with an explicit command line option.
306 
307  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
308  /// is inserted after each instance of the first one.
310 };
311 
312 } // end namespace llvm
313 
314 // Out of line virtual method.
316  delete Impl;
317 }
318 
319 static const PassInfo *getPassInfo(StringRef PassName) {
320  if (PassName.empty())
321  return nullptr;
322 
324  const PassInfo *PI = PR.getPassInfo(PassName);
325  if (!PI)
326  report_fatal_error(Twine('\"') + Twine(PassName) +
327  Twine("\" pass is not registered."));
328  return PI;
329 }
330 
332  const PassInfo *PI = getPassInfo(PassName);
333  return PI ? PI->getTypeInfo() : nullptr;
334 }
335 
336 void TargetPassConfig::setStartStopPasses() {
337  StartBefore = getPassIDFromName(StartBeforeOpt);
338  StartAfter = getPassIDFromName(StartAfterOpt);
339  StopBefore = getPassIDFromName(StopBeforeOpt);
340  StopAfter = getPassIDFromName(StopAfterOpt);
341  if (StartBefore && StartAfter)
342  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
343  Twine(StartAfterOptName) + Twine(" specified!"));
344  if (StopBefore && StopAfter)
345  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
346  Twine(StopAfterOptName) + Twine(" specified!"));
347  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
348 }
349 
350 // Out of line constructor provides default values for pass options and
351 // registers all common codegen passes.
353  : ImmutablePass(ID), PM(&pm), TM(&TM) {
354  Impl = new PassConfigImpl();
355 
356  // Register all target independent codegen passes to activate their PassIDs,
357  // including this pass itself.
359 
360  // Also register alias analysis passes required by codegen passes.
363 
364  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
365  TM.Options.PrintMachineCode = true;
366 
367  if (EnableIPRA.getNumOccurrences())
369  else {
370  // If not explicitly specified, use target default.
371  TM.Options.EnableIPRA = TM.useIPRA();
372  }
373 
374  if (TM.Options.EnableIPRA)
376 
377  setStartStopPasses();
378 }
379 
381  return TM->getOptLevel();
382 }
383 
384 /// Insert InsertedPassID pass after TargetPassID.
386  IdentifyingPassPtr InsertedPassID,
387  bool VerifyAfter, bool PrintAfter) {
388  assert(((!InsertedPassID.isInstance() &&
389  TargetPassID != InsertedPassID.getID()) ||
390  (InsertedPassID.isInstance() &&
391  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
392  "Insert a pass after itself!");
393  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
394  PrintAfter);
395 }
396 
397 /// createPassConfig - Create a pass configuration object to be used by
398 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
399 ///
400 /// Targets may override this to extend TargetPassConfig.
402  return new TargetPassConfig(*this, PM);
403 }
404 
406  : ImmutablePass(ID) {
407  report_fatal_error("Trying to construct TargetPassConfig without a target "
408  "machine. Scheduling a CodeGen pass without a target "
409  "triple set?");
410 }
411 
413  return StartBefore || StartAfter || StopBefore || StopAfter;
414 }
415 
416 std::string
419  return std::string();
420  std::string Res;
421  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
423  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
424  StopAfterOptName, StopBeforeOptName};
425  bool IsFirst = true;
426  for (int Idx = 0; Idx < 4; ++Idx)
427  if (!PassNames[Idx]->empty()) {
428  if (!IsFirst)
429  Res += Separator;
430  IsFirst = false;
431  Res += OptNames[Idx];
432  }
433  return Res;
434 }
435 
436 // Helper to verify the analysis is really immutable.
437 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
438  assert(!Initialized && "PassConfig is immutable");
439  Opt = Val;
440 }
441 
443  IdentifyingPassPtr TargetID) {
444  Impl->TargetPasses[StandardID] = TargetID;
445 }
446 
449  I = Impl->TargetPasses.find(ID);
450  if (I == Impl->TargetPasses.end())
451  return ID;
452  return I->second;
453 }
454 
457  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
458  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
459  FinalPtr.getID() != ID;
460 }
461 
462 /// Add a pass to the PassManager if that pass is supposed to be run. If the
463 /// Started/Stopped flags indicate either that the compilation should start at
464 /// a later pass or that it should stop after an earlier pass, then do not add
465 /// the pass. Finally, compare the current pass against the StartAfter
466 /// and StopAfter options and change the Started/Stopped flags accordingly.
467 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
468  assert(!Initialized && "PassConfig is immutable");
469 
470  // Cache the Pass ID here in case the pass manager finds this pass is
471  // redundant with ones already scheduled / available, and deletes it.
472  // Fundamentally, once we add the pass to the manager, we no longer own it
473  // and shouldn't reference it.
474  AnalysisID PassID = P->getPassID();
475 
476  if (StartBefore == PassID)
477  Started = true;
478  if (StopBefore == PassID)
479  Stopped = true;
480  if (Started && !Stopped) {
481  std::string Banner;
482  // Construct banner message before PM->add() as that may delete the pass.
483  if (AddingMachinePasses && (printAfter || verifyAfter))
484  Banner = std::string("After ") + std::string(P->getPassName());
485  PM->add(P);
486  if (AddingMachinePasses) {
487  if (printAfter)
488  addPrintPass(Banner);
489  if (verifyAfter)
490  addVerifyPass(Banner);
491  }
492 
493  // Add the passes after the pass P if there is any.
494  for (auto IP : Impl->InsertedPasses) {
495  if (IP.TargetPassID == PassID)
496  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
497  }
498  } else {
499  delete P;
500  }
501  if (StopAfter == PassID)
502  Stopped = true;
503  if (StartAfter == PassID)
504  Started = true;
505  if (Stopped && !Started)
506  report_fatal_error("Cannot stop compilation after pass that is not run");
507 }
508 
509 /// Add a CodeGen pass at this point in the pipeline after checking for target
510 /// and command line overrides.
511 ///
512 /// addPass cannot return a pointer to the pass instance because is internal the
513 /// PassManager and the instance we create here may already be freed.
515  bool printAfter) {
516  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
517  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
518  if (!FinalPtr.isValid())
519  return nullptr;
520 
521  Pass *P;
522  if (FinalPtr.isInstance())
523  P = FinalPtr.getInstance();
524  else {
525  P = Pass::createPass(FinalPtr.getID());
526  if (!P)
527  llvm_unreachable("Pass ID not registered");
528  }
529  AnalysisID FinalID = P->getPassID();
530  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
531 
532  return FinalID;
533 }
534 
535 void TargetPassConfig::printAndVerify(const std::string &Banner) {
536  addPrintPass(Banner);
537  addVerifyPass(Banner);
538 }
539 
540 void TargetPassConfig::addPrintPass(const std::string &Banner) {
541  if (TM->shouldPrintMachineCode())
542  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
543 }
544 
545 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
546  bool Verify = VerifyMachineCode;
547 #ifdef EXPENSIVE_CHECKS
549  Verify = TM->isMachineVerifierClean();
550 #endif
551  if (Verify)
552  PM->add(createMachineVerifierPass(Banner));
553 }
554 
555 /// Add common target configurable passes that perform LLVM IR to IR transforms
556 /// following machine independent optimization.
558  switch (UseCFLAA) {
561  break;
562  case CFLAAType::Andersen:
564  break;
565  case CFLAAType::Both:
568  break;
569  default:
570  break;
571  }
572 
573  // Basic AliasAnalysis support.
574  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
575  // BasicAliasAnalysis wins if they disagree. This is intended to help
576  // support "obvious" type-punning idioms.
580 
581  // Before running any passes, run the verifier to determine if the input
582  // coming from the front-end and/or optimizer is valid.
583  if (!DisableVerify)
585 
586  // Run loop strength reduction before anything else.
587  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
589  if (PrintLSR)
590  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
591  }
592 
593  if (getOptLevel() != CodeGenOpt::None) {
594  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
595  // loads and compares. ExpandMemCmpPass then tries to expand those calls
596  // into optimally-sized loads and compares. The transforms are enabled by a
597  // target lowering hook.
598  if (!DisableMergeICmps)
601  }
602 
603  // Run GC lowering passes for builtin collectors
604  // TODO: add a pass insertion point here
607 
608  // Make sure that no unreachable blocks are instruction selected.
610 
611  // Prepare expensive constants for SelectionDAG.
614 
617 
618  // Instrument function entry and exit, e.g. with calls to mcount().
620 
621  // Add scalarization of target's unsupported masked memory intrinsics pass.
622  // the unsupported intrinsic will be replaced with a chain of basic blocks,
623  // that stores/loads element one-by-one if the appropriate mask bit is set.
625 
626  // Expand reduction intrinsics into shuffle sequences if the target wants to.
628 }
629 
630 /// Turn exception handling constructs into something the code generators can
631 /// handle.
633  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
634  assert(MCAI && "No MCAsmInfo");
635  switch (MCAI->getExceptionHandlingType()) {
637  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
638  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
639  // catch info can get misplaced when a selector ends up more than one block
640  // removed from the parent invoke(s). This could happen when a landing
641  // pad is shared by multiple invokes and is also a target of a normal
642  // edge from elsewhere.
648  break;
650  // We support using both GCC-style and MSVC-style exceptions on Windows, so
651  // add both preparation passes. Each pass will only actually run if it
652  // recognizes the personality function.
655  break;
658 
659  // The lower invoke pass may create unreachable code. Remove it.
661  break;
662  }
663 }
664 
665 /// Add pass to prepare the LLVM IR for code generation. This should be done
666 /// before exception handling preparation passes.
671 }
672 
673 /// Add common passes that perform LLVM IR to IR transforms in preparation for
674 /// instruction selection.
676  addPreISel();
677 
678  // Force codegen to run according to the callgraph.
680  addPass(new DummyCGSCCPass);
681 
682  // Add both the safe stack and the stack protection passes: each of them will
683  // only protect functions that have corresponding attributes.
686 
687  if (PrintISelInput)
689  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
690 
691  // All passes which modify the LLVM IR are now complete; run the verifier
692  // to ensure that the IR is valid.
693  if (!DisableVerify)
695 }
696 
698  // Enable FastISel with -fast-isel, but allow that to be overridden.
702  TM->setFastISel(true);
703 
704  // Ask the target for an instruction selector.
705  // Explicitly enabling fast-isel should override implicitly enabled
706  // global-isel.
710  TM->setFastISel(false);
711 
712  if (addIRTranslator())
713  return true;
714 
716 
717  if (addLegalizeMachineIR())
718  return true;
719 
720  // Before running the register bank selector, ask the target if it
721  // wants to run some passes.
723 
724  if (addRegBankSelect())
725  return true;
726 
728 
730  return true;
731 
732  // Pass to reset the MachineFunction if the ISel failed.
735 
736  // Provide a fallback path when we do not want to abort on
737  // not-yet-supported input.
739  return true;
740 
741  } else if (addInstSelector())
742  return true;
743 
744  return false;
745 }
746 
748  if (TM->Options.EmulatedTLS)
750 
753  addIRPasses();
756  addISelPrepare();
757 
758  return addCoreISelPasses();
759 }
760 
761 /// -regalloc=... command line option.
762 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
766  cl::desc("Register allocator to use"));
767 
768 /// Add the complete set of target-independent postISel code generator passes.
769 ///
770 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
771 /// with nontrivial configuration or multiple passes are broken out below in
772 /// add%Stage routines.
773 ///
774 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
775 /// addPre/Post methods with empty header implementations allow injecting
776 /// target-specific fixups just before or after major stages. Additionally,
777 /// targets have the flexibility to change pass order within a stage by
778 /// overriding default implementation of add%Stage routines below. Each
779 /// technique has maintainability tradeoffs because alternate pass orders are
780 /// not well supported. addPre/Post works better if the target pass is easily
781 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
782 /// the target should override the stage instead.
783 ///
784 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
785 /// before/after any target-independent pass. But it's currently overkill.
787  AddingMachinePasses = true;
788 
789  // Insert a machine instr printer pass after the specified pass.
790  if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
791  !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
793  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
794  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
795  assert (TPI && IPI && "Pass ID not registered!");
796  const char *TID = (const char *)(TPI->getTypeInfo());
797  const char *IID = (const char *)(IPI->getTypeInfo());
798  insertPass(TID, IID);
799  }
800 
801  // Print the instruction selected machine code...
802  printAndVerify("After Instruction Selection");
803 
804  // Expand pseudo-instructions emitted by ISel.
806 
807  // Add passes that optimize machine instructions in SSA form.
808  if (getOptLevel() != CodeGenOpt::None) {
810  } else {
811  // If the target requests it, assign local variables to stack slots relative
812  // to one another and simplify frame index references where possible.
814  }
815 
816  if (TM->Options.EnableIPRA)
818 
819  // Run pre-ra passes.
820  addPreRegAlloc();
821 
822  // Run register allocation and passes that are tightly coupled with it,
823  // including phi elimination and scheduling.
824  if (getOptimizeRegAlloc())
826  else {
827  if (RegAlloc != &useDefaultRegisterAllocator &&
828  RegAlloc != &createFastRegisterAllocator)
829  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
831  }
832 
833  // Run post-ra passes.
834  addPostRegAlloc();
835 
836  // Insert prolog/epilog code. Eliminate abstract frame index references...
837  if (getOptLevel() != CodeGenOpt::None)
839 
840  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
841  // do so if it hasn't been disabled, substituted, or overridden.
844 
845  /// Add passes that optimize machine instructions after register allocation.
846  if (getOptLevel() != CodeGenOpt::None)
848 
849  // Expand pseudo instructions before second scheduling pass.
851 
852  // Run pre-sched2 passes.
853  addPreSched2();
854 
857 
858  // Second pass scheduler.
859  // Let Target optionally insert this pass by itself at some other
860  // point.
861  if (getOptLevel() != CodeGenOpt::None &&
863  if (MISchedPostRA)
865  else
867  }
868 
869  // GC
870  if (addGCPasses()) {
871  if (PrintGCInfo)
872  addPass(createGCInfoPrinter(dbgs()), false, false);
873  }
874 
875  // Basic block placement.
876  if (getOptLevel() != CodeGenOpt::None)
878 
879  addPreEmitPass();
880 
881  if (TM->Options.EnableIPRA)
882  // Collect register usage information and produce a register mask of
883  // clobbered registers, to be used to optimize call sites.
885 
886  addPass(&FuncletLayoutID, false);
887 
888  addPass(&StackMapLivenessID, false);
889  addPass(&LiveDebugValuesID, false);
890 
891  // Insert before XRay Instrumentation.
892  addPass(&FEntryInserterID, false);
893 
895  addPass(&PatchableFunctionID, false);
896 
899 
900  // Add passes that directly emit MI after all other MI passes.
901  addPreEmitPass2();
902 
903  AddingMachinePasses = false;
904 }
905 
906 /// Add passes that optimize machine instructions in SSA form.
908  // Pre-ra tail duplication.
910 
911  // Optimize PHIs before DCE: removing dead PHI cycles may make more
912  // instructions dead.
913  addPass(&OptimizePHIsID, false);
914 
915  // This pass merges large allocas. StackSlotColoring is a different pass
916  // which merges spill slots.
917  addPass(&StackColoringID, false);
918 
919  // If the target requests it, assign local variables to stack slots relative
920  // to one another and simplify frame index references where possible.
922 
923  // With optimization, dead code should already be eliminated. However
924  // there is one known exception: lowered code for arguments that are only
925  // used by tail calls, where the tail calls reuse the incoming stack
926  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
928 
929  // Allow targets to insert passes that improve instruction level parallelism,
930  // like if-conversion. Such passes will typically need dominator trees and
931  // loop info, just like LICM and CSE below.
932  addILPOpts();
933 
934  addPass(&EarlyMachineLICMID, false);
935  addPass(&MachineCSEID, false);
936 
938 
940  // Clean-up the dead code that may have been generated by peephole
941  // rewriting.
943 }
944 
945 //===---------------------------------------------------------------------===//
946 /// Register Allocation Pass Configuration
947 //===---------------------------------------------------------------------===//
948 
950  switch (OptimizeRegAlloc) {
951  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
952  case cl::BOU_TRUE: return true;
953  case cl::BOU_FALSE: return false;
954  }
955  llvm_unreachable("Invalid optimize-regalloc state");
956 }
957 
958 /// RegisterRegAlloc's global Registry tracks allocator registration.
960 
961 /// A dummy default pass factory indicates whether the register allocator is
962 /// overridden on the command line.
964 
965 static RegisterRegAlloc
966 defaultRegAlloc("default",
967  "pick register allocator based on -O option",
969 
971  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
972 
973  if (!Ctor) {
974  Ctor = RegAlloc;
976  }
977 }
978 
979 /// Instantiate the default register allocator pass for this target for either
980 /// the optimized or unoptimized allocation path. This will be added to the pass
981 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
982 /// in the optimized case.
983 ///
984 /// A target that uses the standard regalloc pass order for fast or optimized
985 /// allocation may still override this for per-target regalloc
986 /// selection. But -regalloc=... always takes precedence.
988  if (Optimized)
990  else
992 }
993 
994 /// Find and instantiate the register allocation pass requested by this target
995 /// at the current optimization level. Different register allocators are
996 /// defined as separate passes because they may require different analysis.
997 ///
998 /// This helper ensures that the regalloc= option is always available,
999 /// even for targets that override the default allocator.
1000 ///
1001 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1002 /// this can be folded into addPass.
1004  // Initialize the global default.
1005  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1007 
1008  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1009  if (Ctor != useDefaultRegisterAllocator)
1010  return Ctor();
1011 
1012  // With no -regalloc= override, ask the target for a regalloc pass.
1013  return createTargetRegisterAllocator(Optimized);
1014 }
1015 
1016 /// Return true if the default global register allocator is in use and
1017 /// has not be overriden on the command line with '-regalloc=...'
1019  return RegAlloc.getNumOccurrences() == 0;
1020 }
1021 
1022 /// Add the minimum set of target-independent passes that are required for
1023 /// register allocation. No coalescing or scheduling.
1025  addPass(&PHIEliminationID, false);
1027 
1028  if (RegAllocPass)
1029  addPass(RegAllocPass);
1030 }
1031 
1032 /// Add standard target-independent passes that are tightly coupled with
1033 /// optimized register allocation, including coalescing, machine instruction
1034 /// scheduling, and register allocation itself.
1036  addPass(&DetectDeadLanesID, false);
1037 
1038  addPass(&ProcessImplicitDefsID, false);
1039 
1040  // LiveVariables currently requires pure SSA form.
1041  //
1042  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1043  // LiveVariables can be removed completely, and LiveIntervals can be directly
1044  // computed. (We still either need to regenerate kill flags after regalloc, or
1045  // preferably fix the scavenger to not depend on them).
1046  addPass(&LiveVariablesID, false);
1047 
1048  // Edge splitting is smarter with machine loop info.
1049  addPass(&MachineLoopInfoID, false);
1050  addPass(&PHIEliminationID, false);
1051 
1052  // Eventually, we want to run LiveIntervals before PHI elimination.
1053  if (EarlyLiveIntervals)
1054  addPass(&LiveIntervalsID, false);
1055 
1058 
1059  // The machine scheduler may accidentally create disconnected components
1060  // when moving subregister definitions around, avoid this by splitting them to
1061  // separate vregs before. Splitting can also improve reg. allocation quality.
1063 
1064  // PreRA instruction scheduling.
1066 
1067  if (RegAllocPass) {
1068  // Add the selected register allocation pass.
1069  addPass(RegAllocPass);
1070 
1071  // Allow targets to change the register assignments before rewriting.
1072  addPreRewrite();
1073 
1074  // Finally rewrite virtual registers.
1076 
1077  // Perform stack slot coloring and post-ra machine LICM.
1078  //
1079  // FIXME: Re-enable coloring with register when it's capable of adding
1080  // kill markers.
1082 
1083  // Run post-ra machine LICM to hoist reloads / remats.
1084  //
1085  // FIXME: can this move into MachineLateOptimization?
1087  }
1088 }
1089 
1090 //===---------------------------------------------------------------------===//
1091 /// Post RegAlloc Pass Configuration
1092 //===---------------------------------------------------------------------===//
1093 
1094 /// Add passes that optimize machine instructions after register allocation.
1096  // Branch folding must be run after regalloc and prolog/epilog insertion.
1098 
1099  // Tail duplication.
1100  // Note that duplicating tail just increases code size and degrades
1101  // performance for targets that require Structured Control Flow.
1102  // In addition it can also make CFG irreducible. Thus we disable it.
1103  if (!TM->requiresStructuredCFG())
1105 
1106  // Copy propagation.
1108 }
1109 
1110 /// Add standard GC passes.
1113  return true;
1114 }
1115 
1116 /// Add standard basic block placement passes.
1119  // Run a separate pass to collect block placement statistics.
1122  }
1123 }
1124 
1125 //===---------------------------------------------------------------------===//
1126 /// GlobalISel Configuration
1127 //===---------------------------------------------------------------------===//
1129  if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1130  return EnableGlobalISelAbort == 1;
1131 
1132  // When no abort behaviour is specified, we don't abort if the target says
1133  // that GISel is enabled.
1134  return !TM->Options.EnableGlobalISel;
1135 }
1136 
1138  return EnableGlobalISelAbort == 2;
1139 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & FEntryInserterID
This pass inserts FEntry calls.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5080
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
static void setDefault(FunctionPassCtor C)
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static MachinePassRegistry Registry
RegisterRegAlloc&#39;s global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:74
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
bool hasLimitedCodeGenPipeline() const
Describe the status of the codegen pipeline set by this target pass config.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:84
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:901
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:655
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< bool > EnableMachineOutliner("enable-machine-outliner", cl::Hidden, cl::desc("Enable machine outliner"))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:72
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:99
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:100
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:626
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
static cl::opt< bool > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
FunctionPass * createWinEHPass()
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:69
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:31
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
static cl::opt< int > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction: 0 disable the abort, " "1 enable the abort, and " "2 disable the abort but emit a diagnostic on failure"), cl::init(1))
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
FunctionPass *(*)() FunctionPassCtor
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
unsigned EmulatedTLS
EmulatedTLS - This flag enables emulated TLS model, using emutls function in the runtime library...
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:601
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static cl::opt< bool > EnableLinkOnceODROutlining("enable-linkonceodr-outlining", cl::Hidden, cl::desc("Enable the machine outliner on linkonceodr functions"), cl::init(false))
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:654
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
Definition: TargetMachine.h:98
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
bool shouldPrintMachineCode() const
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:216
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the .load.relative intrinsic to instructions.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:212
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:555
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
ModulePass * createMachineOutlinerPass(bool OutlineFromLinkOnceODRs=false)
This pass performs outlining on machine instructions directly before printing assembly.
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:232
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
No exception support.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...