LLVM  7.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
43 #include "llvm/Transforms/Scalar.h"
44 #include "llvm/Transforms/Utils.h"
46 #include <cassert>
47 #include <string>
48 
49 using namespace llvm;
50 
51 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
52  cl::desc("Enable interprocedural register allocation "
53  "to reduce load/store at procedure calls."));
54 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
55  cl::desc("Disable Post Regalloc Scheduler"));
56 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
57  cl::desc("Disable branch folding"));
58 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
59  cl::desc("Disable tail duplication"));
60 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
61  cl::desc("Disable pre-register allocation tail duplication"));
62 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
63  cl::Hidden, cl::desc("Disable probability-driven block placement"));
64 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
65  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
66 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
67  cl::desc("Disable Stack Slot Coloring"));
68 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
69  cl::desc("Disable Machine Dead Code Elimination"));
70 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
71  cl::desc("Disable Early If-conversion"));
72 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
73  cl::desc("Disable Machine LICM"));
74 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
75  cl::desc("Disable Machine Common Subexpression Elimination"));
77  "optimize-regalloc", cl::Hidden,
78  cl::desc("Enable optimized register allocation compilation path."));
79 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
80  cl::Hidden,
81  cl::desc("Disable Machine LICM"));
82 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
83  cl::desc("Disable Machine Sinking"));
84 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
85  cl::Hidden,
86  cl::desc("Disable PostRA Machine Sinking"));
87 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
88  cl::desc("Disable Loop Strength Reduction Pass"));
89 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
90  cl::Hidden, cl::desc("Disable ConstantHoisting"));
91 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
92  cl::desc("Disable Codegen Prepare"));
93 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
94  cl::desc("Disable Copy Propagation pass"));
95 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
96  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
98  "enable-implicit-null-checks",
99  cl::desc("Fold null checks into faulting memory operations"),
100  cl::init(false), cl::Hidden);
101 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
102  cl::desc("Disable MergeICmps Pass"),
103  cl::init(false), cl::Hidden);
104 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
105  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
106 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
107  cl::desc("Print LLVM IR input to isel pass"));
108 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
109  cl::desc("Dump garbage collector data"));
110 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
111  cl::desc("Verify generated machine code"),
112  cl::init(false),
114 static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
115  cl::Hidden,
116  cl::desc("Enable machine outliner"));
117 // Enable or disable FastISel. Both options are needed, because
118 // FastISel is enabled by default with -fast, and we wish to be
119 // able to enable or disable fast-isel independently from -O0.
121 EnableFastISelOption("fast-isel", cl::Hidden,
122  cl::desc("Enable the \"fast\" instruction selector"));
123 
125  "global-isel", cl::Hidden,
126  cl::desc("Enable the \"global\" instruction selector"));
127 
129  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
130  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
131 
133  "global-isel-abort", cl::Hidden,
134  cl::desc("Enable abort calls when \"global\" instruction selection "
135  "fails to lower/select an instruction: 0 disable the abort, "
136  "1 enable the abort, and "
137  "2 disable the abort but emit a diagnostic on failure"),
138  cl::init(1));
139 
140 // Temporary option to allow experimenting with MachineScheduler as a post-RA
141 // scheduler. Targets can "properly" enable this with
142 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
143 // Targets can return true in targetSchedulesPostRAScheduling() and
144 // insert a PostRA scheduling pass wherever it wants.
145 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
146  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
147 
148 // Experimental option to run live interval analysis early.
149 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
150  cl::desc("Run live interval analysis earlier in the pipeline"));
151 
152 // Experimental option to use CFL-AA in codegen
155  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
156  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
157  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
159  "Enable unification-based CFL-AA"),
161  "Enable inclusion-based CFL-AA"),
162  clEnumValN(CFLAAType::Both, "both",
163  "Enable both variants of CFL-AA")));
164 
165 /// Option names for limiting the codegen pipeline.
166 /// Those are used in error reporting and we didn't want
167 /// to duplicate their names all over the place.
168 const char *StartAfterOptName = "start-after";
169 const char *StartBeforeOptName = "start-before";
170 const char *StopAfterOptName = "stop-after";
171 const char *StopBeforeOptName = "stop-before";
172 
174  StartAfterOpt(StringRef(StartAfterOptName),
175  cl::desc("Resume compilation after a specific pass"),
176  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
177 
179  StartBeforeOpt(StringRef(StartBeforeOptName),
180  cl::desc("Resume compilation before a specific pass"),
181  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
182 
184  StopAfterOpt(StringRef(StopAfterOptName),
185  cl::desc("Stop compilation after a specific pass"),
186  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
187 
189  StopBeforeOpt(StringRef(StopBeforeOptName),
190  cl::desc("Stop compilation before a specific pass"),
191  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
192 
193 /// Allow standard passes to be disabled by command line options. This supports
194 /// simple binary flags that either suppress the pass or do nothing.
195 /// i.e. -disable-mypass=false has no effect.
196 /// These should be converted to boolOrDefault in order to use applyOverride.
198  bool Override) {
199  if (Override)
200  return IdentifyingPassPtr();
201  return PassID;
202 }
203 
204 /// Allow standard passes to be disabled by the command line, regardless of who
205 /// is adding the pass.
206 ///
207 /// StandardID is the pass identified in the standard pass pipeline and provided
208 /// to addPass(). It may be a target-specific ID in the case that the target
209 /// directly adds its own pass, but in that case we harmlessly fall through.
210 ///
211 /// TargetID is the pass that the target has configured to override StandardID.
212 ///
213 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
214 /// pass to run. This allows multiple options to control a single pass depending
215 /// on where in the pipeline that pass is added.
217  IdentifyingPassPtr TargetID) {
218  if (StandardID == &PostRASchedulerID)
219  return applyDisable(TargetID, DisablePostRASched);
220 
221  if (StandardID == &BranchFolderPassID)
222  return applyDisable(TargetID, DisableBranchFold);
223 
224  if (StandardID == &TailDuplicateID)
225  return applyDisable(TargetID, DisableTailDuplicate);
226 
227  if (StandardID == &EarlyTailDuplicateID)
228  return applyDisable(TargetID, DisableEarlyTailDup);
229 
230  if (StandardID == &MachineBlockPlacementID)
231  return applyDisable(TargetID, DisableBlockPlacement);
232 
233  if (StandardID == &StackSlotColoringID)
234  return applyDisable(TargetID, DisableSSC);
235 
236  if (StandardID == &DeadMachineInstructionElimID)
237  return applyDisable(TargetID, DisableMachineDCE);
238 
239  if (StandardID == &EarlyIfConverterID)
240  return applyDisable(TargetID, DisableEarlyIfConversion);
241 
242  if (StandardID == &EarlyMachineLICMID)
243  return applyDisable(TargetID, DisableMachineLICM);
244 
245  if (StandardID == &MachineCSEID)
246  return applyDisable(TargetID, DisableMachineCSE);
247 
248  if (StandardID == &MachineLICMID)
249  return applyDisable(TargetID, DisablePostRAMachineLICM);
250 
251  if (StandardID == &MachineSinkingID)
252  return applyDisable(TargetID, DisableMachineSink);
253 
254  if (StandardID == &PostRAMachineSinkingID)
255  return applyDisable(TargetID, DisablePostRAMachineSink);
256 
257  if (StandardID == &MachineCopyPropagationID)
258  return applyDisable(TargetID, DisableCopyProp);
259 
260  return TargetID;
261 }
262 
263 //===---------------------------------------------------------------------===//
264 /// TargetPassConfig
265 //===---------------------------------------------------------------------===//
266 
267 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
268  "Target Pass Configuration", false, false)
269 char TargetPassConfig::ID = 0;
270 
271 namespace {
272 
273 struct InsertedPass {
278 
279  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
280  bool VerifyAfter, bool PrintAfter)
281  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
282  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
283 
285  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
286  if (InsertedPassID.isInstance())
287  return InsertedPassID.getInstance();
288  Pass *NP = Pass::createPass(InsertedPassID.getID());
289  assert(NP && "Pass ID not registered");
290  return NP;
291  }
292 };
293 
294 } // end anonymous namespace
295 
296 namespace llvm {
297 
299 public:
300  // List of passes explicitly substituted by this target. Normally this is
301  // empty, but it is a convenient way to suppress or replace specific passes
302  // that are part of a standard pass pipeline without overridding the entire
303  // pipeline. This mechanism allows target options to inherit a standard pass's
304  // user interface. For example, a target may disable a standard pass by
305  // default by substituting a pass ID of zero, and the user may still enable
306  // that standard pass with an explicit command line option.
308 
309  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
310  /// is inserted after each instance of the first one.
312 };
313 
314 } // end namespace llvm
315 
316 // Out of line virtual method.
318  delete Impl;
319 }
320 
321 static const PassInfo *getPassInfo(StringRef PassName) {
322  if (PassName.empty())
323  return nullptr;
324 
326  const PassInfo *PI = PR.getPassInfo(PassName);
327  if (!PI)
328  report_fatal_error(Twine('\"') + Twine(PassName) +
329  Twine("\" pass is not registered."));
330  return PI;
331 }
332 
334  const PassInfo *PI = getPassInfo(PassName);
335  return PI ? PI->getTypeInfo() : nullptr;
336 }
337 
338 void TargetPassConfig::setStartStopPasses() {
339  StartBefore = getPassIDFromName(StartBeforeOpt);
340  StartAfter = getPassIDFromName(StartAfterOpt);
341  StopBefore = getPassIDFromName(StopBeforeOpt);
342  StopAfter = getPassIDFromName(StopAfterOpt);
343  if (StartBefore && StartAfter)
344  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
345  Twine(StartAfterOptName) + Twine(" specified!"));
346  if (StopBefore && StopAfter)
347  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
348  Twine(StopAfterOptName) + Twine(" specified!"));
349  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
350 }
351 
352 // Out of line constructor provides default values for pass options and
353 // registers all common codegen passes.
355  : ImmutablePass(ID), PM(&pm), TM(&TM) {
356  Impl = new PassConfigImpl();
357 
358  // Register all target independent codegen passes to activate their PassIDs,
359  // including this pass itself.
361 
362  // Also register alias analysis passes required by codegen passes.
365 
366  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
367  TM.Options.PrintMachineCode = true;
368 
369  if (EnableIPRA.getNumOccurrences())
371  else {
372  // If not explicitly specified, use target default.
373  TM.Options.EnableIPRA = TM.useIPRA();
374  }
375 
376  if (TM.Options.EnableIPRA)
378 
379  setStartStopPasses();
380 }
381 
383  return TM->getOptLevel();
384 }
385 
386 /// Insert InsertedPassID pass after TargetPassID.
388  IdentifyingPassPtr InsertedPassID,
389  bool VerifyAfter, bool PrintAfter) {
390  assert(((!InsertedPassID.isInstance() &&
391  TargetPassID != InsertedPassID.getID()) ||
392  (InsertedPassID.isInstance() &&
393  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
394  "Insert a pass after itself!");
395  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
396  PrintAfter);
397 }
398 
399 /// createPassConfig - Create a pass configuration object to be used by
400 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
401 ///
402 /// Targets may override this to extend TargetPassConfig.
404  return new TargetPassConfig(*this, PM);
405 }
406 
408  : ImmutablePass(ID) {
409  report_fatal_error("Trying to construct TargetPassConfig without a target "
410  "machine. Scheduling a CodeGen pass without a target "
411  "triple set?");
412 }
413 
415  return StartBefore || StartAfter || StopBefore || StopAfter;
416 }
417 
418 std::string
421  return std::string();
422  std::string Res;
423  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
425  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
426  StopAfterOptName, StopBeforeOptName};
427  bool IsFirst = true;
428  for (int Idx = 0; Idx < 4; ++Idx)
429  if (!PassNames[Idx]->empty()) {
430  if (!IsFirst)
431  Res += Separator;
432  IsFirst = false;
433  Res += OptNames[Idx];
434  }
435  return Res;
436 }
437 
438 // Helper to verify the analysis is really immutable.
439 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
440  assert(!Initialized && "PassConfig is immutable");
441  Opt = Val;
442 }
443 
445  IdentifyingPassPtr TargetID) {
446  Impl->TargetPasses[StandardID] = TargetID;
447 }
448 
451  I = Impl->TargetPasses.find(ID);
452  if (I == Impl->TargetPasses.end())
453  return ID;
454  return I->second;
455 }
456 
459  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
460  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
461  FinalPtr.getID() != ID;
462 }
463 
464 /// Add a pass to the PassManager if that pass is supposed to be run. If the
465 /// Started/Stopped flags indicate either that the compilation should start at
466 /// a later pass or that it should stop after an earlier pass, then do not add
467 /// the pass. Finally, compare the current pass against the StartAfter
468 /// and StopAfter options and change the Started/Stopped flags accordingly.
469 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
470  assert(!Initialized && "PassConfig is immutable");
471 
472  // Cache the Pass ID here in case the pass manager finds this pass is
473  // redundant with ones already scheduled / available, and deletes it.
474  // Fundamentally, once we add the pass to the manager, we no longer own it
475  // and shouldn't reference it.
476  AnalysisID PassID = P->getPassID();
477 
478  if (StartBefore == PassID)
479  Started = true;
480  if (StopBefore == PassID)
481  Stopped = true;
482  if (Started && !Stopped) {
483  std::string Banner;
484  // Construct banner message before PM->add() as that may delete the pass.
485  if (AddingMachinePasses && (printAfter || verifyAfter))
486  Banner = std::string("After ") + std::string(P->getPassName());
487  PM->add(P);
488  if (AddingMachinePasses) {
489  if (printAfter)
490  addPrintPass(Banner);
491  if (verifyAfter)
492  addVerifyPass(Banner);
493  }
494 
495  // Add the passes after the pass P if there is any.
496  for (auto IP : Impl->InsertedPasses) {
497  if (IP.TargetPassID == PassID)
498  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
499  }
500  } else {
501  delete P;
502  }
503  if (StopAfter == PassID)
504  Stopped = true;
505  if (StartAfter == PassID)
506  Started = true;
507  if (Stopped && !Started)
508  report_fatal_error("Cannot stop compilation after pass that is not run");
509 }
510 
511 /// Add a CodeGen pass at this point in the pipeline after checking for target
512 /// and command line overrides.
513 ///
514 /// addPass cannot return a pointer to the pass instance because is internal the
515 /// PassManager and the instance we create here may already be freed.
517  bool printAfter) {
518  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
519  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
520  if (!FinalPtr.isValid())
521  return nullptr;
522 
523  Pass *P;
524  if (FinalPtr.isInstance())
525  P = FinalPtr.getInstance();
526  else {
527  P = Pass::createPass(FinalPtr.getID());
528  if (!P)
529  llvm_unreachable("Pass ID not registered");
530  }
531  AnalysisID FinalID = P->getPassID();
532  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
533 
534  return FinalID;
535 }
536 
537 void TargetPassConfig::printAndVerify(const std::string &Banner) {
538  addPrintPass(Banner);
539  addVerifyPass(Banner);
540 }
541 
542 void TargetPassConfig::addPrintPass(const std::string &Banner) {
543  if (TM->shouldPrintMachineCode())
544  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
545 }
546 
547 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
548  bool Verify = VerifyMachineCode;
549 #ifdef EXPENSIVE_CHECKS
551  Verify = TM->isMachineVerifierClean();
552 #endif
553  if (Verify)
554  PM->add(createMachineVerifierPass(Banner));
555 }
556 
557 /// Add common target configurable passes that perform LLVM IR to IR transforms
558 /// following machine independent optimization.
560  switch (UseCFLAA) {
563  break;
564  case CFLAAType::Andersen:
566  break;
567  case CFLAAType::Both:
570  break;
571  default:
572  break;
573  }
574 
575  // Basic AliasAnalysis support.
576  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
577  // BasicAliasAnalysis wins if they disagree. This is intended to help
578  // support "obvious" type-punning idioms.
582 
583  // Before running any passes, run the verifier to determine if the input
584  // coming from the front-end and/or optimizer is valid.
585  if (!DisableVerify)
587 
588  // Run loop strength reduction before anything else.
589  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
591  if (PrintLSR)
592  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
593  }
594 
595  if (getOptLevel() != CodeGenOpt::None) {
596  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
597  // loads and compares. ExpandMemCmpPass then tries to expand those calls
598  // into optimally-sized loads and compares. The transforms are enabled by a
599  // target lowering hook.
600  if (!DisableMergeICmps)
603  }
604 
605  // Run GC lowering passes for builtin collectors
606  // TODO: add a pass insertion point here
609 
610  // Make sure that no unreachable blocks are instruction selected.
612 
613  // Prepare expensive constants for SelectionDAG.
616 
619 
620  // Instrument function entry and exit, e.g. with calls to mcount().
622 
623  // Add scalarization of target's unsupported masked memory intrinsics pass.
624  // the unsupported intrinsic will be replaced with a chain of basic blocks,
625  // that stores/loads element one-by-one if the appropriate mask bit is set.
627 
628  // Expand reduction intrinsics into shuffle sequences if the target wants to.
630 }
631 
632 /// Turn exception handling constructs into something the code generators can
633 /// handle.
635  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
636  assert(MCAI && "No MCAsmInfo");
637  switch (MCAI->getExceptionHandlingType()) {
639  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
640  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
641  // catch info can get misplaced when a selector ends up more than one block
642  // removed from the parent invoke(s). This could happen when a landing
643  // pad is shared by multiple invokes and is also a target of a normal
644  // edge from elsewhere.
650  break;
652  // We support using both GCC-style and MSVC-style exceptions on Windows, so
653  // add both preparation passes. Each pass will only actually run if it
654  // recognizes the personality function.
657  break;
659  // TODO to prevent warning
660  break;
663 
664  // The lower invoke pass may create unreachable code. Remove it.
666  break;
667  }
668 }
669 
670 /// Add pass to prepare the LLVM IR for code generation. This should be done
671 /// before exception handling preparation passes.
676 }
677 
678 /// Add common passes that perform LLVM IR to IR transforms in preparation for
679 /// instruction selection.
681  addPreISel();
682 
683  // Force codegen to run according to the callgraph.
685  addPass(new DummyCGSCCPass);
686 
687  // Add both the safe stack and the stack protection passes: each of them will
688  // only protect functions that have corresponding attributes.
691 
692  if (PrintISelInput)
694  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
695 
696  // All passes which modify the LLVM IR are now complete; run the verifier
697  // to ensure that the IR is valid.
698  if (!DisableVerify)
700 }
701 
703  // Enable FastISel with -fast-isel, but allow that to be overridden.
707  TM->setFastISel(true);
708 
709  // Ask the target for an instruction selector.
710  // Explicitly enabling fast-isel should override implicitly enabled
711  // global-isel.
715  TM->setFastISel(false);
716 
717  if (addIRTranslator())
718  return true;
719 
721 
722  if (addLegalizeMachineIR())
723  return true;
724 
725  // Before running the register bank selector, ask the target if it
726  // wants to run some passes.
728 
729  if (addRegBankSelect())
730  return true;
731 
733 
735  return true;
736 
737  // Pass to reset the MachineFunction if the ISel failed.
740 
741  // Provide a fallback path when we do not want to abort on
742  // not-yet-supported input.
744  return true;
745 
746  } else if (addInstSelector())
747  return true;
748 
749  return false;
750 }
751 
753  if (TM->useEmulatedTLS())
755 
758  addIRPasses();
761  addISelPrepare();
762 
763  return addCoreISelPasses();
764 }
765 
766 /// -regalloc=... command line option.
767 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
771  cl::desc("Register allocator to use"));
772 
773 /// Add the complete set of target-independent postISel code generator passes.
774 ///
775 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
776 /// with nontrivial configuration or multiple passes are broken out below in
777 /// add%Stage routines.
778 ///
779 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
780 /// addPre/Post methods with empty header implementations allow injecting
781 /// target-specific fixups just before or after major stages. Additionally,
782 /// targets have the flexibility to change pass order within a stage by
783 /// overriding default implementation of add%Stage routines below. Each
784 /// technique has maintainability tradeoffs because alternate pass orders are
785 /// not well supported. addPre/Post works better if the target pass is easily
786 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
787 /// the target should override the stage instead.
788 ///
789 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
790 /// before/after any target-independent pass. But it's currently overkill.
792  AddingMachinePasses = true;
793 
794  // Insert a machine instr printer pass after the specified pass.
795  if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
796  !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
798  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
799  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
800  assert (TPI && IPI && "Pass ID not registered!");
801  const char *TID = (const char *)(TPI->getTypeInfo());
802  const char *IID = (const char *)(IPI->getTypeInfo());
803  insertPass(TID, IID);
804  }
805 
806  // Print the instruction selected machine code...
807  printAndVerify("After Instruction Selection");
808 
809  // Expand pseudo-instructions emitted by ISel.
811 
812  // Add passes that optimize machine instructions in SSA form.
813  if (getOptLevel() != CodeGenOpt::None) {
815  } else {
816  // If the target requests it, assign local variables to stack slots relative
817  // to one another and simplify frame index references where possible.
819  }
820 
821  if (TM->Options.EnableIPRA)
823 
824  // Run pre-ra passes.
825  addPreRegAlloc();
826 
827  // Run register allocation and passes that are tightly coupled with it,
828  // including phi elimination and scheduling.
829  if (getOptimizeRegAlloc())
831  else {
832  if (RegAlloc != &useDefaultRegisterAllocator &&
833  RegAlloc != &createFastRegisterAllocator)
834  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
836  }
837 
838  // Run post-ra passes.
839  addPostRegAlloc();
840 
841  // Insert prolog/epilog code. Eliminate abstract frame index references...
842  if (getOptLevel() != CodeGenOpt::None) {
845  }
846 
847  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
848  // do so if it hasn't been disabled, substituted, or overridden.
851 
852  /// Add passes that optimize machine instructions after register allocation.
853  if (getOptLevel() != CodeGenOpt::None)
855 
856  // Expand pseudo instructions before second scheduling pass.
858 
859  // Run pre-sched2 passes.
860  addPreSched2();
861 
864 
865  // Second pass scheduler.
866  // Let Target optionally insert this pass by itself at some other
867  // point.
868  if (getOptLevel() != CodeGenOpt::None &&
870  if (MISchedPostRA)
872  else
874  }
875 
876  // GC
877  if (addGCPasses()) {
878  if (PrintGCInfo)
879  addPass(createGCInfoPrinter(dbgs()), false, false);
880  }
881 
882  // Basic block placement.
883  if (getOptLevel() != CodeGenOpt::None)
885 
886  addPreEmitPass();
887 
888  if (TM->Options.EnableIPRA)
889  // Collect register usage information and produce a register mask of
890  // clobbered registers, to be used to optimize call sites.
892 
893  addPass(&FuncletLayoutID, false);
894 
895  addPass(&StackMapLivenessID, false);
896  addPass(&LiveDebugValuesID, false);
897 
898  // Insert before XRay Instrumentation.
899  addPass(&FEntryInserterID, false);
900 
902  addPass(&PatchableFunctionID, false);
903 
906 
907  // Add passes that directly emit MI after all other MI passes.
908  addPreEmitPass2();
909 
910  AddingMachinePasses = false;
911 }
912 
913 /// Add passes that optimize machine instructions in SSA form.
915  // Pre-ra tail duplication.
917 
918  // Optimize PHIs before DCE: removing dead PHI cycles may make more
919  // instructions dead.
920  addPass(&OptimizePHIsID, false);
921 
922  // This pass merges large allocas. StackSlotColoring is a different pass
923  // which merges spill slots.
924  addPass(&StackColoringID, false);
925 
926  // If the target requests it, assign local variables to stack slots relative
927  // to one another and simplify frame index references where possible.
929 
930  // With optimization, dead code should already be eliminated. However
931  // there is one known exception: lowered code for arguments that are only
932  // used by tail calls, where the tail calls reuse the incoming stack
933  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
935 
936  // Allow targets to insert passes that improve instruction level parallelism,
937  // like if-conversion. Such passes will typically need dominator trees and
938  // loop info, just like LICM and CSE below.
939  addILPOpts();
940 
941  addPass(&EarlyMachineLICMID, false);
942  addPass(&MachineCSEID, false);
943 
945 
947  // Clean-up the dead code that may have been generated by peephole
948  // rewriting.
950 }
951 
952 //===---------------------------------------------------------------------===//
953 /// Register Allocation Pass Configuration
954 //===---------------------------------------------------------------------===//
955 
957  switch (OptimizeRegAlloc) {
958  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
959  case cl::BOU_TRUE: return true;
960  case cl::BOU_FALSE: return false;
961  }
962  llvm_unreachable("Invalid optimize-regalloc state");
963 }
964 
965 /// RegisterRegAlloc's global Registry tracks allocator registration.
967 
968 /// A dummy default pass factory indicates whether the register allocator is
969 /// overridden on the command line.
971 
972 static RegisterRegAlloc
973 defaultRegAlloc("default",
974  "pick register allocator based on -O option",
976 
978  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
979 
980  if (!Ctor) {
981  Ctor = RegAlloc;
983  }
984 }
985 
986 /// Instantiate the default register allocator pass for this target for either
987 /// the optimized or unoptimized allocation path. This will be added to the pass
988 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
989 /// in the optimized case.
990 ///
991 /// A target that uses the standard regalloc pass order for fast or optimized
992 /// allocation may still override this for per-target regalloc
993 /// selection. But -regalloc=... always takes precedence.
995  if (Optimized)
997  else
999 }
1000 
1001 /// Find and instantiate the register allocation pass requested by this target
1002 /// at the current optimization level. Different register allocators are
1003 /// defined as separate passes because they may require different analysis.
1004 ///
1005 /// This helper ensures that the regalloc= option is always available,
1006 /// even for targets that override the default allocator.
1007 ///
1008 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1009 /// this can be folded into addPass.
1011  // Initialize the global default.
1012  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1014 
1015  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1016  if (Ctor != useDefaultRegisterAllocator)
1017  return Ctor();
1018 
1019  // With no -regalloc= override, ask the target for a regalloc pass.
1020  return createTargetRegisterAllocator(Optimized);
1021 }
1022 
1023 /// Return true if the default global register allocator is in use and
1024 /// has not be overriden on the command line with '-regalloc=...'
1026  return RegAlloc.getNumOccurrences() == 0;
1027 }
1028 
1029 /// Add the minimum set of target-independent passes that are required for
1030 /// register allocation. No coalescing or scheduling.
1032  addPass(&PHIEliminationID, false);
1034 
1035  if (RegAllocPass)
1036  addPass(RegAllocPass);
1037 }
1038 
1039 /// Add standard target-independent passes that are tightly coupled with
1040 /// optimized register allocation, including coalescing, machine instruction
1041 /// scheduling, and register allocation itself.
1043  addPass(&DetectDeadLanesID, false);
1044 
1045  addPass(&ProcessImplicitDefsID, false);
1046 
1047  // LiveVariables currently requires pure SSA form.
1048  //
1049  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1050  // LiveVariables can be removed completely, and LiveIntervals can be directly
1051  // computed. (We still either need to regenerate kill flags after regalloc, or
1052  // preferably fix the scavenger to not depend on them).
1053  addPass(&LiveVariablesID, false);
1054 
1055  // Edge splitting is smarter with machine loop info.
1056  addPass(&MachineLoopInfoID, false);
1057  addPass(&PHIEliminationID, false);
1058 
1059  // Eventually, we want to run LiveIntervals before PHI elimination.
1060  if (EarlyLiveIntervals)
1061  addPass(&LiveIntervalsID, false);
1062 
1065 
1066  // The machine scheduler may accidentally create disconnected components
1067  // when moving subregister definitions around, avoid this by splitting them to
1068  // separate vregs before. Splitting can also improve reg. allocation quality.
1070 
1071  // PreRA instruction scheduling.
1073 
1074  if (RegAllocPass) {
1075  // Add the selected register allocation pass.
1076  addPass(RegAllocPass);
1077 
1078  // Allow targets to change the register assignments before rewriting.
1079  addPreRewrite();
1080 
1081  // Finally rewrite virtual registers.
1083 
1084  // Perform stack slot coloring and post-ra machine LICM.
1085  //
1086  // FIXME: Re-enable coloring with register when it's capable of adding
1087  // kill markers.
1089 
1090  // Copy propagate to forward register uses and try to eliminate COPYs that
1091  // were not coalesced.
1093 
1094  // Run post-ra machine LICM to hoist reloads / remats.
1095  //
1096  // FIXME: can this move into MachineLateOptimization?
1098  }
1099 }
1100 
1101 //===---------------------------------------------------------------------===//
1102 /// Post RegAlloc Pass Configuration
1103 //===---------------------------------------------------------------------===//
1104 
1105 /// Add passes that optimize machine instructions after register allocation.
1107  // Branch folding must be run after regalloc and prolog/epilog insertion.
1109 
1110  // Tail duplication.
1111  // Note that duplicating tail just increases code size and degrades
1112  // performance for targets that require Structured Control Flow.
1113  // In addition it can also make CFG irreducible. Thus we disable it.
1114  if (!TM->requiresStructuredCFG())
1116 
1117  // Copy propagation.
1119 }
1120 
1121 /// Add standard GC passes.
1124  return true;
1125 }
1126 
1127 /// Add standard basic block placement passes.
1130  // Run a separate pass to collect block placement statistics.
1133  }
1134 }
1135 
1136 //===---------------------------------------------------------------------===//
1137 /// GlobalISel Configuration
1138 //===---------------------------------------------------------------------===//
1140  if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1141  return EnableGlobalISelAbort == 1;
1142 
1143  // When no abort behaviour is specified, we don't abort if the target says
1144  // that GISel is enabled.
1145  return !TM->Options.EnableGlobalISel;
1146 }
1147 
1149  return EnableGlobalISelAbort == 2;
1150 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
char & FEntryInserterID
This pass inserts FEntry calls.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5075
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
static void setDefault(FunctionPassCtor C)
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static MachinePassRegistry Registry
RegisterRegAlloc&#39;s global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:75
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
bool hasLimitedCodeGenPipeline() const
Describe the status of the codegen pipeline set by this target pass config.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:86
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:903
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:797
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< bool > EnableMachineOutliner("enable-machine-outliner", cl::Hidden, cl::desc("Enable machine outliner"))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:72
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:99
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
Windows Exception Handling.
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:100
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:630
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
static cl::opt< bool > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
ModulePass * createMachineOutlinerPass()
This pass performs outlining on machine instructions directly before printing assembly.
FunctionPass * createWinEHPass()
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:69
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:31
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
static cl::opt< int > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction: 0 disable the abort, " "1 enable the abort, and " "2 disable the abort but emit a diagnostic on failure"), cl::init(1))
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
FunctionPass *(*)() FunctionPassCtor
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:605
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:654
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
Definition: TargetMachine.h:98
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
bool shouldPrintMachineCode() const
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:217
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative intrinsic to instructions.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:213
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:559
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:244
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
No exception support.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...