LLVM  9.0.0svn
TargetPassConfig.cpp
Go to the documentation of this file.
1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
11 //
12 //===---------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
27 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Verifier.h"
32 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Pass.h"
35 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/Threading.h"
43 #include "llvm/Transforms/Scalar.h"
44 #include "llvm/Transforms/Utils.h"
46 #include <cassert>
47 #include <string>
48 
49 using namespace llvm;
50 
51 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
52  cl::desc("Enable interprocedural register allocation "
53  "to reduce load/store at procedure calls."));
54 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
55  cl::desc("Disable Post Regalloc Scheduler"));
56 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
57  cl::desc("Disable branch folding"));
58 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
59  cl::desc("Disable tail duplication"));
60 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
61  cl::desc("Disable pre-register allocation tail duplication"));
62 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
63  cl::Hidden, cl::desc("Disable probability-driven block placement"));
64 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
65  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
66 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
67  cl::desc("Disable Stack Slot Coloring"));
68 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
69  cl::desc("Disable Machine Dead Code Elimination"));
70 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
71  cl::desc("Disable Early If-conversion"));
72 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
73  cl::desc("Disable Machine LICM"));
74 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
75  cl::desc("Disable Machine Common Subexpression Elimination"));
77  "optimize-regalloc", cl::Hidden,
78  cl::desc("Enable optimized register allocation compilation path."));
79 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
80  cl::Hidden,
81  cl::desc("Disable Machine LICM"));
82 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
83  cl::desc("Disable Machine Sinking"));
84 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
85  cl::Hidden,
86  cl::desc("Disable PostRA Machine Sinking"));
87 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
88  cl::desc("Disable Loop Strength Reduction Pass"));
89 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
90  cl::Hidden, cl::desc("Disable ConstantHoisting"));
91 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
92  cl::desc("Disable Codegen Prepare"));
93 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
94  cl::desc("Disable Copy Propagation pass"));
95 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
96  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
98  "enable-implicit-null-checks",
99  cl::desc("Fold null checks into faulting memory operations"),
100  cl::init(false), cl::Hidden);
101 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
102  cl::desc("Disable MergeICmps Pass"),
103  cl::init(false), cl::Hidden);
104 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
105  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
106 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
107  cl::desc("Print LLVM IR input to isel pass"));
108 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
109  cl::desc("Dump garbage collector data"));
111  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
112  cl::desc("Verify generated machine code"),
115 // Enable or disable the MachineOutliner.
117  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
118  cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
120  "Run on all functions guaranteed to be beneficial"),
121  clEnumValN(NeverOutline, "never", "Disable all outlining"),
122  // Sentinel value for unspecified option.
123  clEnumValN(AlwaysOutline, "", "")));
124 // Enable or disable FastISel. Both options are needed, because
125 // FastISel is enabled by default with -fast, and we wish to be
126 // able to enable or disable fast-isel independently from -O0.
128 EnableFastISelOption("fast-isel", cl::Hidden,
129  cl::desc("Enable the \"fast\" instruction selector"));
130 
132  "global-isel", cl::Hidden,
133  cl::desc("Enable the \"global\" instruction selector"));
134 
136  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
137  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
138 
140  "global-isel-abort", cl::Hidden,
141  cl::desc("Enable abort calls when \"global\" instruction selection "
142  "fails to lower/select an instruction"),
143  cl::values(
144  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
145  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
147  "Disable the abort but emit a diagnostic on failure")));
148 
149 // Temporary option to allow experimenting with MachineScheduler as a post-RA
150 // scheduler. Targets can "properly" enable this with
151 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
152 // Targets can return true in targetSchedulesPostRAScheduling() and
153 // insert a PostRA scheduling pass wherever it wants.
154 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
155  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
156 
157 // Experimental option to run live interval analysis early.
158 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
159  cl::desc("Run live interval analysis earlier in the pipeline"));
160 
161 // Experimental option to use CFL-AA in codegen
164  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
165  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
166  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
168  "Enable unification-based CFL-AA"),
170  "Enable inclusion-based CFL-AA"),
171  clEnumValN(CFLAAType::Both, "both",
172  "Enable both variants of CFL-AA")));
173 
174 /// Option names for limiting the codegen pipeline.
175 /// Those are used in error reporting and we didn't want
176 /// to duplicate their names all over the place.
177 const char *StartAfterOptName = "start-after";
178 const char *StartBeforeOptName = "start-before";
179 const char *StopAfterOptName = "stop-after";
180 const char *StopBeforeOptName = "stop-before";
181 
183  StartAfterOpt(StringRef(StartAfterOptName),
184  cl::desc("Resume compilation after a specific pass"),
185  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
186 
188  StartBeforeOpt(StringRef(StartBeforeOptName),
189  cl::desc("Resume compilation before a specific pass"),
190  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
191 
193  StopAfterOpt(StringRef(StopAfterOptName),
194  cl::desc("Stop compilation after a specific pass"),
195  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
196 
198  StopBeforeOpt(StringRef(StopBeforeOptName),
199  cl::desc("Stop compilation before a specific pass"),
200  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
201 
202 /// Allow standard passes to be disabled by command line options. This supports
203 /// simple binary flags that either suppress the pass or do nothing.
204 /// i.e. -disable-mypass=false has no effect.
205 /// These should be converted to boolOrDefault in order to use applyOverride.
207  bool Override) {
208  if (Override)
209  return IdentifyingPassPtr();
210  return PassID;
211 }
212 
213 /// Allow standard passes to be disabled by the command line, regardless of who
214 /// is adding the pass.
215 ///
216 /// StandardID is the pass identified in the standard pass pipeline and provided
217 /// to addPass(). It may be a target-specific ID in the case that the target
218 /// directly adds its own pass, but in that case we harmlessly fall through.
219 ///
220 /// TargetID is the pass that the target has configured to override StandardID.
221 ///
222 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
223 /// pass to run. This allows multiple options to control a single pass depending
224 /// on where in the pipeline that pass is added.
226  IdentifyingPassPtr TargetID) {
227  if (StandardID == &PostRASchedulerID)
228  return applyDisable(TargetID, DisablePostRASched);
229 
230  if (StandardID == &BranchFolderPassID)
231  return applyDisable(TargetID, DisableBranchFold);
232 
233  if (StandardID == &TailDuplicateID)
234  return applyDisable(TargetID, DisableTailDuplicate);
235 
236  if (StandardID == &EarlyTailDuplicateID)
237  return applyDisable(TargetID, DisableEarlyTailDup);
238 
239  if (StandardID == &MachineBlockPlacementID)
240  return applyDisable(TargetID, DisableBlockPlacement);
241 
242  if (StandardID == &StackSlotColoringID)
243  return applyDisable(TargetID, DisableSSC);
244 
245  if (StandardID == &DeadMachineInstructionElimID)
246  return applyDisable(TargetID, DisableMachineDCE);
247 
248  if (StandardID == &EarlyIfConverterID)
249  return applyDisable(TargetID, DisableEarlyIfConversion);
250 
251  if (StandardID == &EarlyMachineLICMID)
252  return applyDisable(TargetID, DisableMachineLICM);
253 
254  if (StandardID == &MachineCSEID)
255  return applyDisable(TargetID, DisableMachineCSE);
256 
257  if (StandardID == &MachineLICMID)
258  return applyDisable(TargetID, DisablePostRAMachineLICM);
259 
260  if (StandardID == &MachineSinkingID)
261  return applyDisable(TargetID, DisableMachineSink);
262 
263  if (StandardID == &PostRAMachineSinkingID)
264  return applyDisable(TargetID, DisablePostRAMachineSink);
265 
266  if (StandardID == &MachineCopyPropagationID)
267  return applyDisable(TargetID, DisableCopyProp);
268 
269  return TargetID;
270 }
271 
272 //===---------------------------------------------------------------------===//
273 /// TargetPassConfig
274 //===---------------------------------------------------------------------===//
275 
276 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
277  "Target Pass Configuration", false, false)
278 char TargetPassConfig::ID = 0;
279 
280 namespace {
281 
282 struct InsertedPass {
287 
288  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
289  bool VerifyAfter, bool PrintAfter)
290  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
291  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
292 
294  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
295  if (InsertedPassID.isInstance())
296  return InsertedPassID.getInstance();
297  Pass *NP = Pass::createPass(InsertedPassID.getID());
298  assert(NP && "Pass ID not registered");
299  return NP;
300  }
301 };
302 
303 } // end anonymous namespace
304 
305 namespace llvm {
306 
308 public:
309  // List of passes explicitly substituted by this target. Normally this is
310  // empty, but it is a convenient way to suppress or replace specific passes
311  // that are part of a standard pass pipeline without overridding the entire
312  // pipeline. This mechanism allows target options to inherit a standard pass's
313  // user interface. For example, a target may disable a standard pass by
314  // default by substituting a pass ID of zero, and the user may still enable
315  // that standard pass with an explicit command line option.
317 
318  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
319  /// is inserted after each instance of the first one.
321 };
322 
323 } // end namespace llvm
324 
325 // Out of line virtual method.
327  delete Impl;
328 }
329 
330 static const PassInfo *getPassInfo(StringRef PassName) {
331  if (PassName.empty())
332  return nullptr;
333 
335  const PassInfo *PI = PR.getPassInfo(PassName);
336  if (!PI)
337  report_fatal_error(Twine('\"') + Twine(PassName) +
338  Twine("\" pass is not registered."));
339  return PI;
340 }
341 
343  const PassInfo *PI = getPassInfo(PassName);
344  return PI ? PI->getTypeInfo() : nullptr;
345 }
346 
347 static std::pair<StringRef, unsigned>
349  StringRef Name, InstanceNumStr;
350  std::tie(Name, InstanceNumStr) = PassName.split(',');
351 
352  unsigned InstanceNum = 0;
353  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
354  report_fatal_error("invalid pass instance specifier " + PassName);
355 
356  return std::make_pair(Name, InstanceNum);
357 }
358 
359 void TargetPassConfig::setStartStopPasses() {
360  StringRef StartBeforeName;
361  std::tie(StartBeforeName, StartBeforeInstanceNum) =
363 
364  StringRef StartAfterName;
365  std::tie(StartAfterName, StartAfterInstanceNum) =
367 
368  StringRef StopBeforeName;
369  std::tie(StopBeforeName, StopBeforeInstanceNum)
371 
372  StringRef StopAfterName;
373  std::tie(StopAfterName, StopAfterInstanceNum)
375 
376  StartBefore = getPassIDFromName(StartBeforeName);
377  StartAfter = getPassIDFromName(StartAfterName);
378  StopBefore = getPassIDFromName(StopBeforeName);
379  StopAfter = getPassIDFromName(StopAfterName);
380  if (StartBefore && StartAfter)
381  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
382  Twine(StartAfterOptName) + Twine(" specified!"));
383  if (StopBefore && StopAfter)
384  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
385  Twine(StopAfterOptName) + Twine(" specified!"));
386  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
387 }
388 
389 // Out of line constructor provides default values for pass options and
390 // registers all common codegen passes.
392  : ImmutablePass(ID), PM(&pm), TM(&TM) {
393  Impl = new PassConfigImpl();
394 
395  // Register all target independent codegen passes to activate their PassIDs,
396  // including this pass itself.
398 
399  // Also register alias analysis passes required by codegen passes.
402 
403  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
404  TM.Options.PrintMachineCode = true;
405 
406  if (EnableIPRA.getNumOccurrences())
408  else {
409  // If not explicitly specified, use target default.
410  TM.Options.EnableIPRA |= TM.useIPRA();
411  }
412 
413  if (TM.Options.EnableIPRA)
415 
416  if (EnableGlobalISelAbort.getNumOccurrences())
417  TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
418 
419  setStartStopPasses();
420 }
421 
423  return TM->getOptLevel();
424 }
425 
426 /// Insert InsertedPassID pass after TargetPassID.
428  IdentifyingPassPtr InsertedPassID,
429  bool VerifyAfter, bool PrintAfter) {
430  assert(((!InsertedPassID.isInstance() &&
431  TargetPassID != InsertedPassID.getID()) ||
432  (InsertedPassID.isInstance() &&
433  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
434  "Insert a pass after itself!");
435  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
436  PrintAfter);
437 }
438 
439 /// createPassConfig - Create a pass configuration object to be used by
440 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
441 ///
442 /// Targets may override this to extend TargetPassConfig.
444  return new TargetPassConfig(*this, PM);
445 }
446 
448  : ImmutablePass(ID) {
449  report_fatal_error("Trying to construct TargetPassConfig without a target "
450  "machine. Scheduling a CodeGen pass without a target "
451  "triple set?");
452 }
453 
455  return StopBeforeOpt.empty() && StopAfterOpt.empty();
456 }
457 
459  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
461 }
462 
463 std::string
466  return std::string();
467  std::string Res;
468  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
470  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
471  StopAfterOptName, StopBeforeOptName};
472  bool IsFirst = true;
473  for (int Idx = 0; Idx < 4; ++Idx)
474  if (!PassNames[Idx]->empty()) {
475  if (!IsFirst)
476  Res += Separator;
477  IsFirst = false;
478  Res += OptNames[Idx];
479  }
480  return Res;
481 }
482 
483 // Helper to verify the analysis is really immutable.
484 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
485  assert(!Initialized && "PassConfig is immutable");
486  Opt = Val;
487 }
488 
490  IdentifyingPassPtr TargetID) {
491  Impl->TargetPasses[StandardID] = TargetID;
492 }
493 
496  I = Impl->TargetPasses.find(ID);
497  if (I == Impl->TargetPasses.end())
498  return ID;
499  return I->second;
500 }
501 
504  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
505  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
506  FinalPtr.getID() != ID;
507 }
508 
509 /// Add a pass to the PassManager if that pass is supposed to be run. If the
510 /// Started/Stopped flags indicate either that the compilation should start at
511 /// a later pass or that it should stop after an earlier pass, then do not add
512 /// the pass. Finally, compare the current pass against the StartAfter
513 /// and StopAfter options and change the Started/Stopped flags accordingly.
514 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
515  assert(!Initialized && "PassConfig is immutable");
516 
517  // Cache the Pass ID here in case the pass manager finds this pass is
518  // redundant with ones already scheduled / available, and deletes it.
519  // Fundamentally, once we add the pass to the manager, we no longer own it
520  // and shouldn't reference it.
521  AnalysisID PassID = P->getPassID();
522 
523  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
524  Started = true;
525  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
526  Stopped = true;
527  if (Started && !Stopped) {
528  std::string Banner;
529  // Construct banner message before PM->add() as that may delete the pass.
530  if (AddingMachinePasses && (printAfter || verifyAfter))
531  Banner = std::string("After ") + std::string(P->getPassName());
532  PM->add(P);
533  if (AddingMachinePasses) {
534  if (printAfter)
535  addPrintPass(Banner);
536  if (verifyAfter)
537  addVerifyPass(Banner);
538  }
539 
540  // Add the passes after the pass P if there is any.
541  for (auto IP : Impl->InsertedPasses) {
542  if (IP.TargetPassID == PassID)
543  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
544  }
545  } else {
546  delete P;
547  }
548 
549  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
550  Stopped = true;
551 
552  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
553  Started = true;
554  if (Stopped && !Started)
555  report_fatal_error("Cannot stop compilation after pass that is not run");
556 }
557 
558 /// Add a CodeGen pass at this point in the pipeline after checking for target
559 /// and command line overrides.
560 ///
561 /// addPass cannot return a pointer to the pass instance because is internal the
562 /// PassManager and the instance we create here may already be freed.
564  bool printAfter) {
565  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
566  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
567  if (!FinalPtr.isValid())
568  return nullptr;
569 
570  Pass *P;
571  if (FinalPtr.isInstance())
572  P = FinalPtr.getInstance();
573  else {
574  P = Pass::createPass(FinalPtr.getID());
575  if (!P)
576  llvm_unreachable("Pass ID not registered");
577  }
578  AnalysisID FinalID = P->getPassID();
579  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
580 
581  return FinalID;
582 }
583 
584 void TargetPassConfig::printAndVerify(const std::string &Banner) {
585  addPrintPass(Banner);
586  addVerifyPass(Banner);
587 }
588 
589 void TargetPassConfig::addPrintPass(const std::string &Banner) {
590  if (TM->shouldPrintMachineCode())
591  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
592 }
593 
594 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
596 #ifdef EXPENSIVE_CHECKS
598  Verify = TM->isMachineVerifierClean();
599 #endif
600  if (Verify)
601  PM->add(createMachineVerifierPass(Banner));
602 }
603 
604 /// Add common target configurable passes that perform LLVM IR to IR transforms
605 /// following machine independent optimization.
607  switch (UseCFLAA) {
610  break;
611  case CFLAAType::Andersen:
613  break;
614  case CFLAAType::Both:
617  break;
618  default:
619  break;
620  }
621 
622  // Basic AliasAnalysis support.
623  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
624  // BasicAliasAnalysis wins if they disagree. This is intended to help
625  // support "obvious" type-punning idioms.
629 
630  // Before running any passes, run the verifier to determine if the input
631  // coming from the front-end and/or optimizer is valid.
632  if (!DisableVerify)
634 
635  // Run loop strength reduction before anything else.
636  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
638  if (PrintLSR)
639  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
640  }
641 
642  if (getOptLevel() != CodeGenOpt::None) {
643  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
644  // loads and compares. ExpandMemCmpPass then tries to expand those calls
645  // into optimally-sized loads and compares. The transforms are enabled by a
646  // target lowering hook.
647  if (!DisableMergeICmps)
650  }
651 
652  // Run GC lowering passes for builtin collectors
653  // TODO: add a pass insertion point here
656 
657  // Make sure that no unreachable blocks are instruction selected.
659 
660  // Prepare expensive constants for SelectionDAG.
663 
666 
667  // Instrument function entry and exit, e.g. with calls to mcount().
669 
670  // Add scalarization of target's unsupported masked memory intrinsics pass.
671  // the unsupported intrinsic will be replaced with a chain of basic blocks,
672  // that stores/loads element one-by-one if the appropriate mask bit is set.
674 
675  // Expand reduction intrinsics into shuffle sequences if the target wants to.
677 }
678 
679 /// Turn exception handling constructs into something the code generators can
680 /// handle.
682  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
683  assert(MCAI && "No MCAsmInfo");
684  switch (MCAI->getExceptionHandlingType()) {
686  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
687  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
688  // catch info can get misplaced when a selector ends up more than one block
689  // removed from the parent invoke(s). This could happen when a landing
690  // pad is shared by multiple invokes and is also a target of a normal
691  // edge from elsewhere.
697  break;
699  // We support using both GCC-style and MSVC-style exceptions on Windows, so
700  // add both preparation passes. Each pass will only actually run if it
701  // recognizes the personality function.
704  break;
706  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
707  // on catchpads and cleanuppads because it does not outline them into
708  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
709  // should remove PHIs there.
710  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
712  break;
715 
716  // The lower invoke pass may create unreachable code. Remove it.
718  break;
719  }
720 }
721 
722 /// Add pass to prepare the LLVM IR for code generation. This should be done
723 /// before exception handling preparation passes.
728 }
729 
730 /// Add common passes that perform LLVM IR to IR transforms in preparation for
731 /// instruction selection.
733  addPreISel();
734 
735  // Force codegen to run according to the callgraph.
737  addPass(new DummyCGSCCPass);
738 
739  // Add both the safe stack and the stack protection passes: each of them will
740  // only protect functions that have corresponding attributes.
743 
744  if (PrintISelInput)
746  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
747 
748  // All passes which modify the LLVM IR are now complete; run the verifier
749  // to ensure that the IR is valid.
750  if (!DisableVerify)
752 }
753 
755  // Enable FastISel with -fast-isel, but allow that to be overridden.
756  TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
757 
758  // Determine an instruction selector.
759  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
760  SelectorType Selector;
761 
762  if (EnableFastISelOption == cl::BOU_TRUE)
763  Selector = SelectorType::FastISel;
764  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
766  EnableGlobalISelOption != cl::BOU_FALSE))
767  Selector = SelectorType::GlobalISel;
768  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
769  Selector = SelectorType::FastISel;
770  else
771  Selector = SelectorType::SelectionDAG;
772 
773  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
774  if (Selector == SelectorType::FastISel) {
775  TM->setFastISel(true);
776  TM->setGlobalISel(false);
777  } else if (Selector == SelectorType::GlobalISel) {
778  TM->setFastISel(false);
779  TM->setGlobalISel(true);
780  }
781 
782  // Add instruction selector passes.
783  if (Selector == SelectorType::GlobalISel) {
784  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
785  if (addIRTranslator())
786  return true;
787 
789 
790  if (addLegalizeMachineIR())
791  return true;
792 
793  // Before running the register bank selector, ask the target if it
794  // wants to run some passes.
796 
797  if (addRegBankSelect())
798  return true;
799 
801 
803  return true;
804 
805  // Pass to reset the MachineFunction if the ISel failed.
808 
809  // Provide a fallback path when we do not want to abort on
810  // not-yet-supported input.
812  return true;
813 
814  } else if (addInstSelector())
815  return true;
816 
817  return false;
818 }
819 
821  if (TM->useEmulatedTLS())
823 
826  addIRPasses();
829  addISelPrepare();
830 
831  return addCoreISelPasses();
832 }
833 
834 /// -regalloc=... command line option.
835 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
839  cl::desc("Register allocator to use"));
840 
841 /// Add the complete set of target-independent postISel code generator passes.
842 ///
843 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
844 /// with nontrivial configuration or multiple passes are broken out below in
845 /// add%Stage routines.
846 ///
847 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
848 /// addPre/Post methods with empty header implementations allow injecting
849 /// target-specific fixups just before or after major stages. Additionally,
850 /// targets have the flexibility to change pass order within a stage by
851 /// overriding default implementation of add%Stage routines below. Each
852 /// technique has maintainability tradeoffs because alternate pass orders are
853 /// not well supported. addPre/Post works better if the target pass is easily
854 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
855 /// the target should override the stage instead.
856 ///
857 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
858 /// before/after any target-independent pass. But it's currently overkill.
860  AddingMachinePasses = true;
861 
862  // Insert a machine instr printer pass after the specified pass.
863  StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
864  if (!PrintMachineInstrsPassName.equals("") &&
865  !PrintMachineInstrsPassName.equals("option-unspecified")) {
866  if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
868  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
869  assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
870  const char *TID = (const char *)(TPI->getTypeInfo());
871  const char *IID = (const char *)(IPI->getTypeInfo());
872  insertPass(TID, IID);
873  }
874  }
875 
876  // Print the instruction selected machine code...
877  printAndVerify("After Instruction Selection");
878 
879  // Expand pseudo-instructions emitted by ISel.
881 
882  // Add passes that optimize machine instructions in SSA form.
883  if (getOptLevel() != CodeGenOpt::None) {
885  } else {
886  // If the target requests it, assign local variables to stack slots relative
887  // to one another and simplify frame index references where possible.
889  }
890 
891  if (TM->Options.EnableIPRA)
893 
894  // Run pre-ra passes.
895  addPreRegAlloc();
896 
897  // Run register allocation and passes that are tightly coupled with it,
898  // including phi elimination and scheduling.
899  if (getOptimizeRegAlloc())
901  else
902  addFastRegAlloc();
903 
904  // Run post-ra passes.
905  addPostRegAlloc();
906 
907  // Insert prolog/epilog code. Eliminate abstract frame index references...
908  if (getOptLevel() != CodeGenOpt::None) {
911  }
912 
913  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
914  // do so if it hasn't been disabled, substituted, or overridden.
917 
918  /// Add passes that optimize machine instructions after register allocation.
919  if (getOptLevel() != CodeGenOpt::None)
921 
922  // Expand pseudo instructions before second scheduling pass.
924 
925  // Run pre-sched2 passes.
926  addPreSched2();
927 
930 
931  // Second pass scheduler.
932  // Let Target optionally insert this pass by itself at some other
933  // point.
934  if (getOptLevel() != CodeGenOpt::None &&
936  if (MISchedPostRA)
938  else
940  }
941 
942  // GC
943  if (addGCPasses()) {
944  if (PrintGCInfo)
945  addPass(createGCInfoPrinter(dbgs()), false, false);
946  }
947 
948  // Basic block placement.
949  if (getOptLevel() != CodeGenOpt::None)
951 
952  addPreEmitPass();
953 
954  if (TM->Options.EnableIPRA)
955  // Collect register usage information and produce a register mask of
956  // clobbered registers, to be used to optimize call sites.
958 
959  addPass(&FuncletLayoutID, false);
960 
961  addPass(&StackMapLivenessID, false);
962  addPass(&LiveDebugValuesID, false);
963 
964  // Insert before XRay Instrumentation.
965  addPass(&FEntryInserterID, false);
966 
968  addPass(&PatchableFunctionID, false);
969 
971  EnableMachineOutliner != NeverOutline) {
972  bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
973  bool AddOutliner = RunOnAllFunctions ||
975  if (AddOutliner)
976  addPass(createMachineOutlinerPass(RunOnAllFunctions));
977  }
978 
979  // Add passes that directly emit MI after all other MI passes.
980  addPreEmitPass2();
981 
982  AddingMachinePasses = false;
983 }
984 
985 /// Add passes that optimize machine instructions in SSA form.
987  // Pre-ra tail duplication.
989 
990  // Optimize PHIs before DCE: removing dead PHI cycles may make more
991  // instructions dead.
992  addPass(&OptimizePHIsID, false);
993 
994  // This pass merges large allocas. StackSlotColoring is a different pass
995  // which merges spill slots.
996  addPass(&StackColoringID, false);
997 
998  // If the target requests it, assign local variables to stack slots relative
999  // to one another and simplify frame index references where possible.
1001 
1002  // With optimization, dead code should already be eliminated. However
1003  // there is one known exception: lowered code for arguments that are only
1004  // used by tail calls, where the tail calls reuse the incoming stack
1005  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1007 
1008  // Allow targets to insert passes that improve instruction level parallelism,
1009  // like if-conversion. Such passes will typically need dominator trees and
1010  // loop info, just like LICM and CSE below.
1011  addILPOpts();
1012 
1013  addPass(&EarlyMachineLICMID, false);
1014  addPass(&MachineCSEID, false);
1015 
1017 
1019  // Clean-up the dead code that may have been generated by peephole
1020  // rewriting.
1022 }
1023 
1024 //===---------------------------------------------------------------------===//
1025 /// Register Allocation Pass Configuration
1026 //===---------------------------------------------------------------------===//
1027 
1029  switch (OptimizeRegAlloc) {
1030  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1031  case cl::BOU_TRUE: return true;
1032  case cl::BOU_FALSE: return false;
1033  }
1034  llvm_unreachable("Invalid optimize-regalloc state");
1035 }
1036 
1037 /// A dummy default pass factory indicates whether the register allocator is
1038 /// overridden on the command line.
1040 
1041 static RegisterRegAlloc
1042 defaultRegAlloc("default",
1043  "pick register allocator based on -O option",
1045 
1047  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1048 
1049  if (!Ctor) {
1050  Ctor = RegAlloc;
1051  RegisterRegAlloc::setDefault(RegAlloc);
1052  }
1053 }
1054 
1055 /// Instantiate the default register allocator pass for this target for either
1056 /// the optimized or unoptimized allocation path. This will be added to the pass
1057 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1058 /// in the optimized case.
1059 ///
1060 /// A target that uses the standard regalloc pass order for fast or optimized
1061 /// allocation may still override this for per-target regalloc
1062 /// selection. But -regalloc=... always takes precedence.
1064  if (Optimized)
1066  else
1067  return createFastRegisterAllocator();
1068 }
1069 
1070 /// Find and instantiate the register allocation pass requested by this target
1071 /// at the current optimization level. Different register allocators are
1072 /// defined as separate passes because they may require different analysis.
1073 ///
1074 /// This helper ensures that the regalloc= option is always available,
1075 /// even for targets that override the default allocator.
1076 ///
1077 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1078 /// this can be folded into addPass.
1080  // Initialize the global default.
1081  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1083 
1084  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1085  if (Ctor != useDefaultRegisterAllocator)
1086  return Ctor();
1087 
1088  // With no -regalloc= override, ask the target for a regalloc pass.
1089  return createTargetRegisterAllocator(Optimized);
1090 }
1091 
1093  if (RegAlloc != &useDefaultRegisterAllocator &&
1094  RegAlloc != &createFastRegisterAllocator)
1095  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1096 
1097  addPass(createRegAllocPass(false));
1098  return true;
1099 }
1100 
1102  // Add the selected register allocation pass.
1103  addPass(createRegAllocPass(true));
1104 
1105  // Allow targets to change the register assignments before rewriting.
1106  addPreRewrite();
1107 
1108  // Finally rewrite virtual registers.
1110  // Perform stack slot coloring and post-ra machine LICM.
1111  //
1112  // FIXME: Re-enable coloring with register when it's capable of adding
1113  // kill markers.
1115 
1116  return true;
1117 }
1118 
1119 /// Return true if the default global register allocator is in use and
1120 /// has not be overriden on the command line with '-regalloc=...'
1122  return RegAlloc.getNumOccurrences() == 0;
1123 }
1124 
1125 /// Add the minimum set of target-independent passes that are required for
1126 /// register allocation. No coalescing or scheduling.
1128  addPass(&PHIEliminationID, false);
1130 
1132 }
1133 
1134 /// Add standard target-independent passes that are tightly coupled with
1135 /// optimized register allocation, including coalescing, machine instruction
1136 /// scheduling, and register allocation itself.
1138  addPass(&DetectDeadLanesID, false);
1139 
1140  addPass(&ProcessImplicitDefsID, false);
1141 
1142  // LiveVariables currently requires pure SSA form.
1143  //
1144  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1145  // LiveVariables can be removed completely, and LiveIntervals can be directly
1146  // computed. (We still either need to regenerate kill flags after regalloc, or
1147  // preferably fix the scavenger to not depend on them).
1148  addPass(&LiveVariablesID, false);
1149 
1150  // Edge splitting is smarter with machine loop info.
1151  addPass(&MachineLoopInfoID, false);
1152  addPass(&PHIEliminationID, false);
1153 
1154  // Eventually, we want to run LiveIntervals before PHI elimination.
1155  if (EarlyLiveIntervals)
1156  addPass(&LiveIntervalsID, false);
1157 
1160 
1161  // The machine scheduler may accidentally create disconnected components
1162  // when moving subregister definitions around, avoid this by splitting them to
1163  // separate vregs before. Splitting can also improve reg. allocation quality.
1165 
1166  // PreRA instruction scheduling.
1168 
1169  if (addRegAssignmentOptimized()) {
1170  // Copy propagate to forward register uses and try to eliminate COPYs that
1171  // were not coalesced.
1173 
1174  // Run post-ra machine LICM to hoist reloads / remats.
1175  //
1176  // FIXME: can this move into MachineLateOptimization?
1178  }
1179 }
1180 
1181 //===---------------------------------------------------------------------===//
1182 /// Post RegAlloc Pass Configuration
1183 //===---------------------------------------------------------------------===//
1184 
1185 /// Add passes that optimize machine instructions after register allocation.
1187  // Branch folding must be run after regalloc and prolog/epilog insertion.
1189 
1190  // Tail duplication.
1191  // Note that duplicating tail just increases code size and degrades
1192  // performance for targets that require Structured Control Flow.
1193  // In addition it can also make CFG irreducible. Thus we disable it.
1194  if (!TM->requiresStructuredCFG())
1196 
1197  // Copy propagation.
1199 }
1200 
1201 /// Add standard GC passes.
1204  return true;
1205 }
1206 
1207 /// Add standard basic block placement passes.
1210  // Run a separate pass to collect block placement statistics.
1213  }
1214 }
1215 
1216 //===---------------------------------------------------------------------===//
1217 /// GlobalISel Configuration
1218 //===---------------------------------------------------------------------===//
1221 }
1222 
1225 }
1226 
1228  return getOptLevel() != CodeGenOpt::Level::None;
1229 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:645
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & FEntryInserterID
This pass inserts FEntry calls.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5265
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:79
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:86
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:911
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:869
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:132
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), cl::values(clEnumValN(AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(NeverOutline, "never", "Disable all outlining"), clEnumValN(AlwaysOutline, "", "")))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:71
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly&#39;s exception handling s...
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:102
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:91
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
Windows Exception Handling.
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:99
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:643
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
int getNumOccurrences() const
Definition: CommandLine.h:384
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual bool addRegAssignmentOptimized()
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:72
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:30
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:255
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:48
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A utility class that uses RAII to save and restore the value of a variable.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:618
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:160
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
void setGlobalISel(bool Enable)
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
virtual bool addRegAssignmentFast()
Add core register alloator passes which do the actual register assignment and rewriting.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
bool shouldPrintMachineCode() const
static void setDefault(FunctionPassCtor C)
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:232
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:212
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set...
This file provides utility classes that use RAII to save and restore values.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:569
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:249
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
This pass exposes codegen information to IR-level passes.
No exception support.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...