LLVM  9.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include "llvm/Transforms/Utils.h"
47 #include <cassert>
48 #include <string>
49 
50 using namespace llvm;
51 
52 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
53  cl::desc("Enable interprocedural register allocation "
54  "to reduce load/store at procedure calls."));
55 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
56  cl::desc("Disable Post Regalloc Scheduler"));
57 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
58  cl::desc("Disable branch folding"));
59 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
60  cl::desc("Disable tail duplication"));
61 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
62  cl::desc("Disable pre-register allocation tail duplication"));
63 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
64  cl::Hidden, cl::desc("Disable probability-driven block placement"));
65 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
66  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
67 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
68  cl::desc("Disable Stack Slot Coloring"));
69 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
70  cl::desc("Disable Machine Dead Code Elimination"));
71 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
72  cl::desc("Disable Early If-conversion"));
73 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
74  cl::desc("Disable Machine LICM"));
75 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
76  cl::desc("Disable Machine Common Subexpression Elimination"));
78  "optimize-regalloc", cl::Hidden,
79  cl::desc("Enable optimized register allocation compilation path."));
80 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
81  cl::Hidden,
82  cl::desc("Disable Machine LICM"));
83 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
84  cl::desc("Disable Machine Sinking"));
85 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
86  cl::Hidden,
87  cl::desc("Disable PostRA Machine Sinking"));
88 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
89  cl::desc("Disable Loop Strength Reduction Pass"));
90 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
91  cl::Hidden, cl::desc("Disable ConstantHoisting"));
92 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
93  cl::desc("Disable Codegen Prepare"));
94 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
95  cl::desc("Disable Copy Propagation pass"));
96 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
97  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
99  "enable-implicit-null-checks",
100  cl::desc("Fold null checks into faulting memory operations"),
101  cl::init(false), cl::Hidden);
102 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
103  cl::desc("Disable MergeICmps Pass"),
104  cl::init(false), cl::Hidden);
105 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
106  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
107 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
108  cl::desc("Print LLVM IR input to isel pass"));
109 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
110  cl::desc("Dump garbage collector data"));
112  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
113  cl::desc("Verify generated machine code"),
116 // Enable or disable the MachineOutliner.
118  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
119  cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
121  "Run on all functions guaranteed to be beneficial"),
122  clEnumValN(NeverOutline, "never", "Disable all outlining"),
123  // Sentinel value for unspecified option.
124  clEnumValN(AlwaysOutline, "", "")));
125 // Enable or disable FastISel. Both options are needed, because
126 // FastISel is enabled by default with -fast, and we wish to be
127 // able to enable or disable fast-isel independently from -O0.
129 EnableFastISelOption("fast-isel", cl::Hidden,
130  cl::desc("Enable the \"fast\" instruction selector"));
131 
133  "global-isel", cl::Hidden,
134  cl::desc("Enable the \"global\" instruction selector"));
135 
137  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
138  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
139 
141  "global-isel-abort", cl::Hidden,
142  cl::desc("Enable abort calls when \"global\" instruction selection "
143  "fails to lower/select an instruction"),
144  cl::values(
145  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
146  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
148  "Disable the abort but emit a diagnostic on failure")));
149 
150 // Temporary option to allow experimenting with MachineScheduler as a post-RA
151 // scheduler. Targets can "properly" enable this with
152 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
153 // Targets can return true in targetSchedulesPostRAScheduling() and
154 // insert a PostRA scheduling pass wherever it wants.
155 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
156  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
157 
158 // Experimental option to run live interval analysis early.
159 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
160  cl::desc("Run live interval analysis earlier in the pipeline"));
161 
162 // Experimental option to use CFL-AA in codegen
165  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
166  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
167  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
169  "Enable unification-based CFL-AA"),
171  "Enable inclusion-based CFL-AA"),
172  clEnumValN(CFLAAType::Both, "both",
173  "Enable both variants of CFL-AA")));
174 
175 /// Option names for limiting the codegen pipeline.
176 /// Those are used in error reporting and we didn't want
177 /// to duplicate their names all over the place.
178 const char *StartAfterOptName = "start-after";
179 const char *StartBeforeOptName = "start-before";
180 const char *StopAfterOptName = "stop-after";
181 const char *StopBeforeOptName = "stop-before";
182 
184  StartAfterOpt(StringRef(StartAfterOptName),
185  cl::desc("Resume compilation after a specific pass"),
186  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
187 
189  StartBeforeOpt(StringRef(StartBeforeOptName),
190  cl::desc("Resume compilation before a specific pass"),
191  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
192 
194  StopAfterOpt(StringRef(StopAfterOptName),
195  cl::desc("Stop compilation after a specific pass"),
196  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
197 
199  StopBeforeOpt(StringRef(StopBeforeOptName),
200  cl::desc("Stop compilation before a specific pass"),
201  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
202 
203 /// Allow standard passes to be disabled by command line options. This supports
204 /// simple binary flags that either suppress the pass or do nothing.
205 /// i.e. -disable-mypass=false has no effect.
206 /// These should be converted to boolOrDefault in order to use applyOverride.
208  bool Override) {
209  if (Override)
210  return IdentifyingPassPtr();
211  return PassID;
212 }
213 
214 /// Allow standard passes to be disabled by the command line, regardless of who
215 /// is adding the pass.
216 ///
217 /// StandardID is the pass identified in the standard pass pipeline and provided
218 /// to addPass(). It may be a target-specific ID in the case that the target
219 /// directly adds its own pass, but in that case we harmlessly fall through.
220 ///
221 /// TargetID is the pass that the target has configured to override StandardID.
222 ///
223 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
224 /// pass to run. This allows multiple options to control a single pass depending
225 /// on where in the pipeline that pass is added.
227  IdentifyingPassPtr TargetID) {
228  if (StandardID == &PostRASchedulerID)
229  return applyDisable(TargetID, DisablePostRASched);
230 
231  if (StandardID == &BranchFolderPassID)
232  return applyDisable(TargetID, DisableBranchFold);
233 
234  if (StandardID == &TailDuplicateID)
235  return applyDisable(TargetID, DisableTailDuplicate);
236 
237  if (StandardID == &EarlyTailDuplicateID)
238  return applyDisable(TargetID, DisableEarlyTailDup);
239 
240  if (StandardID == &MachineBlockPlacementID)
241  return applyDisable(TargetID, DisableBlockPlacement);
242 
243  if (StandardID == &StackSlotColoringID)
244  return applyDisable(TargetID, DisableSSC);
245 
246  if (StandardID == &DeadMachineInstructionElimID)
247  return applyDisable(TargetID, DisableMachineDCE);
248 
249  if (StandardID == &EarlyIfConverterID)
250  return applyDisable(TargetID, DisableEarlyIfConversion);
251 
252  if (StandardID == &EarlyMachineLICMID)
253  return applyDisable(TargetID, DisableMachineLICM);
254 
255  if (StandardID == &MachineCSEID)
256  return applyDisable(TargetID, DisableMachineCSE);
257 
258  if (StandardID == &MachineLICMID)
259  return applyDisable(TargetID, DisablePostRAMachineLICM);
260 
261  if (StandardID == &MachineSinkingID)
262  return applyDisable(TargetID, DisableMachineSink);
263 
264  if (StandardID == &PostRAMachineSinkingID)
265  return applyDisable(TargetID, DisablePostRAMachineSink);
266 
267  if (StandardID == &MachineCopyPropagationID)
268  return applyDisable(TargetID, DisableCopyProp);
269 
270  return TargetID;
271 }
272 
273 //===---------------------------------------------------------------------===//
274 /// TargetPassConfig
275 //===---------------------------------------------------------------------===//
276 
277 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
278  "Target Pass Configuration", false, false)
279 char TargetPassConfig::ID = 0;
280 
281 namespace {
282 
283 struct InsertedPass {
288 
289  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
290  bool VerifyAfter, bool PrintAfter)
291  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
292  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
293 
295  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
296  if (InsertedPassID.isInstance())
297  return InsertedPassID.getInstance();
298  Pass *NP = Pass::createPass(InsertedPassID.getID());
299  assert(NP && "Pass ID not registered");
300  return NP;
301  }
302 };
303 
304 } // end anonymous namespace
305 
306 namespace llvm {
307 
309 public:
310  // List of passes explicitly substituted by this target. Normally this is
311  // empty, but it is a convenient way to suppress or replace specific passes
312  // that are part of a standard pass pipeline without overridding the entire
313  // pipeline. This mechanism allows target options to inherit a standard pass's
314  // user interface. For example, a target may disable a standard pass by
315  // default by substituting a pass ID of zero, and the user may still enable
316  // that standard pass with an explicit command line option.
318 
319  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
320  /// is inserted after each instance of the first one.
322 };
323 
324 } // end namespace llvm
325 
326 // Out of line virtual method.
328  delete Impl;
329 }
330 
331 static const PassInfo *getPassInfo(StringRef PassName) {
332  if (PassName.empty())
333  return nullptr;
334 
336  const PassInfo *PI = PR.getPassInfo(PassName);
337  if (!PI)
338  report_fatal_error(Twine('\"') + Twine(PassName) +
339  Twine("\" pass is not registered."));
340  return PI;
341 }
342 
344  const PassInfo *PI = getPassInfo(PassName);
345  return PI ? PI->getTypeInfo() : nullptr;
346 }
347 
348 static std::pair<StringRef, unsigned>
350  StringRef Name, InstanceNumStr;
351  std::tie(Name, InstanceNumStr) = PassName.split(',');
352 
353  unsigned InstanceNum = 0;
354  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
355  report_fatal_error("invalid pass instance specifier " + PassName);
356 
357  return std::make_pair(Name, InstanceNum);
358 }
359 
360 void TargetPassConfig::setStartStopPasses() {
361  StringRef StartBeforeName;
362  std::tie(StartBeforeName, StartBeforeInstanceNum) =
364 
365  StringRef StartAfterName;
366  std::tie(StartAfterName, StartAfterInstanceNum) =
368 
369  StringRef StopBeforeName;
370  std::tie(StopBeforeName, StopBeforeInstanceNum)
372 
373  StringRef StopAfterName;
374  std::tie(StopAfterName, StopAfterInstanceNum)
376 
377  StartBefore = getPassIDFromName(StartBeforeName);
378  StartAfter = getPassIDFromName(StartAfterName);
379  StopBefore = getPassIDFromName(StopBeforeName);
380  StopAfter = getPassIDFromName(StopAfterName);
381  if (StartBefore && StartAfter)
382  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
383  Twine(StartAfterOptName) + Twine(" specified!"));
384  if (StopBefore && StopAfter)
385  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
386  Twine(StopAfterOptName) + Twine(" specified!"));
387  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
388 }
389 
390 // Out of line constructor provides default values for pass options and
391 // registers all common codegen passes.
393  : ImmutablePass(ID), PM(&pm), TM(&TM) {
394  Impl = new PassConfigImpl();
395 
396  // Register all target independent codegen passes to activate their PassIDs,
397  // including this pass itself.
399 
400  // Also register alias analysis passes required by codegen passes.
403 
404  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
405  TM.Options.PrintMachineCode = true;
406 
407  if (EnableIPRA.getNumOccurrences())
409  else {
410  // If not explicitly specified, use target default.
411  TM.Options.EnableIPRA = TM.useIPRA();
412  }
413 
414  if (TM.Options.EnableIPRA)
416 
417  if (EnableGlobalISelAbort.getNumOccurrences())
418  TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
419 
420  setStartStopPasses();
421 }
422 
424  return TM->getOptLevel();
425 }
426 
427 /// Insert InsertedPassID pass after TargetPassID.
429  IdentifyingPassPtr InsertedPassID,
430  bool VerifyAfter, bool PrintAfter) {
431  assert(((!InsertedPassID.isInstance() &&
432  TargetPassID != InsertedPassID.getID()) ||
433  (InsertedPassID.isInstance() &&
434  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
435  "Insert a pass after itself!");
436  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
437  PrintAfter);
438 }
439 
440 /// createPassConfig - Create a pass configuration object to be used by
441 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
442 ///
443 /// Targets may override this to extend TargetPassConfig.
445  return new TargetPassConfig(*this, PM);
446 }
447 
449  : ImmutablePass(ID) {
450  report_fatal_error("Trying to construct TargetPassConfig without a target "
451  "machine. Scheduling a CodeGen pass without a target "
452  "triple set?");
453 }
454 
456  return StopBeforeOpt.empty() && StopAfterOpt.empty();
457 }
458 
460  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
462 }
463 
464 std::string
467  return std::string();
468  std::string Res;
469  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
471  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
472  StopAfterOptName, StopBeforeOptName};
473  bool IsFirst = true;
474  for (int Idx = 0; Idx < 4; ++Idx)
475  if (!PassNames[Idx]->empty()) {
476  if (!IsFirst)
477  Res += Separator;
478  IsFirst = false;
479  Res += OptNames[Idx];
480  }
481  return Res;
482 }
483 
484 // Helper to verify the analysis is really immutable.
485 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
486  assert(!Initialized && "PassConfig is immutable");
487  Opt = Val;
488 }
489 
491  IdentifyingPassPtr TargetID) {
492  Impl->TargetPasses[StandardID] = TargetID;
493 }
494 
497  I = Impl->TargetPasses.find(ID);
498  if (I == Impl->TargetPasses.end())
499  return ID;
500  return I->second;
501 }
502 
505  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
506  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
507  FinalPtr.getID() != ID;
508 }
509 
510 /// Add a pass to the PassManager if that pass is supposed to be run. If the
511 /// Started/Stopped flags indicate either that the compilation should start at
512 /// a later pass or that it should stop after an earlier pass, then do not add
513 /// the pass. Finally, compare the current pass against the StartAfter
514 /// and StopAfter options and change the Started/Stopped flags accordingly.
515 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
516  assert(!Initialized && "PassConfig is immutable");
517 
518  // Cache the Pass ID here in case the pass manager finds this pass is
519  // redundant with ones already scheduled / available, and deletes it.
520  // Fundamentally, once we add the pass to the manager, we no longer own it
521  // and shouldn't reference it.
522  AnalysisID PassID = P->getPassID();
523 
524  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
525  Started = true;
526  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
527  Stopped = true;
528  if (Started && !Stopped) {
529  std::string Banner;
530  // Construct banner message before PM->add() as that may delete the pass.
531  if (AddingMachinePasses && (printAfter || verifyAfter))
532  Banner = std::string("After ") + std::string(P->getPassName());
533  PM->add(P);
534  if (AddingMachinePasses) {
535  if (printAfter)
536  addPrintPass(Banner);
537  if (verifyAfter)
538  addVerifyPass(Banner);
539  }
540 
541  // Add the passes after the pass P if there is any.
542  for (auto IP : Impl->InsertedPasses) {
543  if (IP.TargetPassID == PassID)
544  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
545  }
546  } else {
547  delete P;
548  }
549 
550  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
551  Stopped = true;
552 
553  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
554  Started = true;
555  if (Stopped && !Started)
556  report_fatal_error("Cannot stop compilation after pass that is not run");
557 }
558 
559 /// Add a CodeGen pass at this point in the pipeline after checking for target
560 /// and command line overrides.
561 ///
562 /// addPass cannot return a pointer to the pass instance because is internal the
563 /// PassManager and the instance we create here may already be freed.
565  bool printAfter) {
566  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
567  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
568  if (!FinalPtr.isValid())
569  return nullptr;
570 
571  Pass *P;
572  if (FinalPtr.isInstance())
573  P = FinalPtr.getInstance();
574  else {
575  P = Pass::createPass(FinalPtr.getID());
576  if (!P)
577  llvm_unreachable("Pass ID not registered");
578  }
579  AnalysisID FinalID = P->getPassID();
580  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
581 
582  return FinalID;
583 }
584 
585 void TargetPassConfig::printAndVerify(const std::string &Banner) {
586  addPrintPass(Banner);
587  addVerifyPass(Banner);
588 }
589 
590 void TargetPassConfig::addPrintPass(const std::string &Banner) {
591  if (TM->shouldPrintMachineCode())
592  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
593 }
594 
595 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
597 #ifdef EXPENSIVE_CHECKS
599  Verify = TM->isMachineVerifierClean();
600 #endif
601  if (Verify)
602  PM->add(createMachineVerifierPass(Banner));
603 }
604 
605 /// Add common target configurable passes that perform LLVM IR to IR transforms
606 /// following machine independent optimization.
608  switch (UseCFLAA) {
611  break;
612  case CFLAAType::Andersen:
614  break;
615  case CFLAAType::Both:
618  break;
619  default:
620  break;
621  }
622 
623  // Basic AliasAnalysis support.
624  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
625  // BasicAliasAnalysis wins if they disagree. This is intended to help
626  // support "obvious" type-punning idioms.
630 
631  // Before running any passes, run the verifier to determine if the input
632  // coming from the front-end and/or optimizer is valid.
633  if (!DisableVerify)
635 
636  // Run loop strength reduction before anything else.
637  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
639  if (PrintLSR)
640  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
641  }
642 
643  if (getOptLevel() != CodeGenOpt::None) {
644  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
645  // loads and compares. ExpandMemCmpPass then tries to expand those calls
646  // into optimally-sized loads and compares. The transforms are enabled by a
647  // target lowering hook.
648  if (!DisableMergeICmps)
651  }
652 
653  // Run GC lowering passes for builtin collectors
654  // TODO: add a pass insertion point here
657 
658  // Make sure that no unreachable blocks are instruction selected.
660 
661  // Prepare expensive constants for SelectionDAG.
664 
667 
668  // Instrument function entry and exit, e.g. with calls to mcount().
670 
671  // Add scalarization of target's unsupported masked memory intrinsics pass.
672  // the unsupported intrinsic will be replaced with a chain of basic blocks,
673  // that stores/loads element one-by-one if the appropriate mask bit is set.
675 
676  // Expand reduction intrinsics into shuffle sequences if the target wants to.
678 }
679 
680 /// Turn exception handling constructs into something the code generators can
681 /// handle.
683  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
684  assert(MCAI && "No MCAsmInfo");
685  switch (MCAI->getExceptionHandlingType()) {
687  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
688  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
689  // catch info can get misplaced when a selector ends up more than one block
690  // removed from the parent invoke(s). This could happen when a landing
691  // pad is shared by multiple invokes and is also a target of a normal
692  // edge from elsewhere.
698  break;
700  // We support using both GCC-style and MSVC-style exceptions on Windows, so
701  // add both preparation passes. Each pass will only actually run if it
702  // recognizes the personality function.
705  break;
707  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
708  // on catchpads and cleanuppads because it does not outline them into
709  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
710  // should remove PHIs there.
711  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
713  break;
716 
717  // The lower invoke pass may create unreachable code. Remove it.
719  break;
720  }
721 }
722 
723 /// Add pass to prepare the LLVM IR for code generation. This should be done
724 /// before exception handling preparation passes.
729 }
730 
731 /// Add common passes that perform LLVM IR to IR transforms in preparation for
732 /// instruction selection.
734  addPreISel();
735 
736  // Force codegen to run according to the callgraph.
738  addPass(new DummyCGSCCPass);
739 
740  // Add both the safe stack and the stack protection passes: each of them will
741  // only protect functions that have corresponding attributes.
744 
745  if (PrintISelInput)
747  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
748 
749  // All passes which modify the LLVM IR are now complete; run the verifier
750  // to ensure that the IR is valid.
751  if (!DisableVerify)
753 }
754 
756  // Enable FastISel with -fast-isel, but allow that to be overridden.
757  TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
758 
759  // Determine an instruction selector.
760  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
761  SelectorType Selector;
762 
763  if (EnableFastISelOption == cl::BOU_TRUE)
764  Selector = SelectorType::FastISel;
765  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
767  EnableGlobalISelOption != cl::BOU_FALSE))
768  Selector = SelectorType::GlobalISel;
769  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
770  Selector = SelectorType::FastISel;
771  else
772  Selector = SelectorType::SelectionDAG;
773 
774  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
775  if (Selector == SelectorType::FastISel) {
776  TM->setFastISel(true);
777  TM->setGlobalISel(false);
778  } else if (Selector == SelectorType::GlobalISel) {
779  TM->setFastISel(false);
780  TM->setGlobalISel(true);
781  }
782 
783  // Add instruction selector passes.
784  if (Selector == SelectorType::GlobalISel) {
785  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
786  if (addIRTranslator())
787  return true;
788 
790 
791  if (addLegalizeMachineIR())
792  return true;
793 
794  // Before running the register bank selector, ask the target if it
795  // wants to run some passes.
797 
798  if (addRegBankSelect())
799  return true;
800 
802 
804  return true;
805 
806  // Pass to reset the MachineFunction if the ISel failed.
809 
810  // Provide a fallback path when we do not want to abort on
811  // not-yet-supported input.
813  return true;
814 
815  } else if (addInstSelector())
816  return true;
817 
818  return false;
819 }
820 
822  if (TM->useEmulatedTLS())
824 
827  addIRPasses();
830  addISelPrepare();
831 
832  return addCoreISelPasses();
833 }
834 
835 /// -regalloc=... command line option.
836 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
840  cl::desc("Register allocator to use"));
841 
842 /// Add the complete set of target-independent postISel code generator passes.
843 ///
844 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
845 /// with nontrivial configuration or multiple passes are broken out below in
846 /// add%Stage routines.
847 ///
848 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
849 /// addPre/Post methods with empty header implementations allow injecting
850 /// target-specific fixups just before or after major stages. Additionally,
851 /// targets have the flexibility to change pass order within a stage by
852 /// overriding default implementation of add%Stage routines below. Each
853 /// technique has maintainability tradeoffs because alternate pass orders are
854 /// not well supported. addPre/Post works better if the target pass is easily
855 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
856 /// the target should override the stage instead.
857 ///
858 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
859 /// before/after any target-independent pass. But it's currently overkill.
861  AddingMachinePasses = true;
862 
863  // Insert a machine instr printer pass after the specified pass.
864  StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
865  if (!PrintMachineInstrsPassName.equals("") &&
866  !PrintMachineInstrsPassName.equals("option-unspecified")) {
867  if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
869  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
870  assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
871  const char *TID = (const char *)(TPI->getTypeInfo());
872  const char *IID = (const char *)(IPI->getTypeInfo());
873  insertPass(TID, IID);
874  }
875  }
876 
877  // Print the instruction selected machine code...
878  printAndVerify("After Instruction Selection");
879 
880  // Expand pseudo-instructions emitted by ISel.
882 
883  // Add passes that optimize machine instructions in SSA form.
884  if (getOptLevel() != CodeGenOpt::None) {
886  } else {
887  // If the target requests it, assign local variables to stack slots relative
888  // to one another and simplify frame index references where possible.
890  }
891 
892  if (TM->Options.EnableIPRA)
894 
895  // Run pre-ra passes.
896  addPreRegAlloc();
897 
898  // Run register allocation and passes that are tightly coupled with it,
899  // including phi elimination and scheduling.
900  if (getOptimizeRegAlloc())
902  else {
903  if (RegAlloc != &useDefaultRegisterAllocator &&
904  RegAlloc != &createFastRegisterAllocator)
905  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
907  }
908 
909  // Run post-ra passes.
910  addPostRegAlloc();
911 
912  // Insert prolog/epilog code. Eliminate abstract frame index references...
913  if (getOptLevel() != CodeGenOpt::None) {
916  }
917 
918  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
919  // do so if it hasn't been disabled, substituted, or overridden.
922 
923  /// Add passes that optimize machine instructions after register allocation.
924  if (getOptLevel() != CodeGenOpt::None)
926 
927  // Expand pseudo instructions before second scheduling pass.
929 
930  // Run pre-sched2 passes.
931  addPreSched2();
932 
935 
936  // Second pass scheduler.
937  // Let Target optionally insert this pass by itself at some other
938  // point.
939  if (getOptLevel() != CodeGenOpt::None &&
941  if (MISchedPostRA)
943  else
945  }
946 
947  // GC
948  if (addGCPasses()) {
949  if (PrintGCInfo)
950  addPass(createGCInfoPrinter(dbgs()), false, false);
951  }
952 
953  // Basic block placement.
954  if (getOptLevel() != CodeGenOpt::None)
956 
957  addPreEmitPass();
958 
959  if (TM->Options.EnableIPRA)
960  // Collect register usage information and produce a register mask of
961  // clobbered registers, to be used to optimize call sites.
963 
964  addPass(&FuncletLayoutID, false);
965 
966  addPass(&StackMapLivenessID, false);
967  addPass(&LiveDebugValuesID, false);
968 
969  // Insert before XRay Instrumentation.
970  addPass(&FEntryInserterID, false);
971 
973  addPass(&PatchableFunctionID, false);
974 
976  EnableMachineOutliner != NeverOutline) {
977  bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
978  bool AddOutliner = RunOnAllFunctions ||
980  if (AddOutliner)
981  addPass(createMachineOutlinerPass(RunOnAllFunctions));
982  }
983 
984  // Add passes that directly emit MI after all other MI passes.
985  addPreEmitPass2();
986 
987  AddingMachinePasses = false;
988 }
989 
990 /// Add passes that optimize machine instructions in SSA form.
992  // Pre-ra tail duplication.
994 
995  // Optimize PHIs before DCE: removing dead PHI cycles may make more
996  // instructions dead.
997  addPass(&OptimizePHIsID, false);
998 
999  // This pass merges large allocas. StackSlotColoring is a different pass
1000  // which merges spill slots.
1001  addPass(&StackColoringID, false);
1002 
1003  // If the target requests it, assign local variables to stack slots relative
1004  // to one another and simplify frame index references where possible.
1006 
1007  // With optimization, dead code should already be eliminated. However
1008  // there is one known exception: lowered code for arguments that are only
1009  // used by tail calls, where the tail calls reuse the incoming stack
1010  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1012 
1013  // Allow targets to insert passes that improve instruction level parallelism,
1014  // like if-conversion. Such passes will typically need dominator trees and
1015  // loop info, just like LICM and CSE below.
1016  addILPOpts();
1017 
1018  addPass(&EarlyMachineLICMID, false);
1019  addPass(&MachineCSEID, false);
1020 
1022 
1024  // Clean-up the dead code that may have been generated by peephole
1025  // rewriting.
1027 }
1028 
1029 //===---------------------------------------------------------------------===//
1030 /// Register Allocation Pass Configuration
1031 //===---------------------------------------------------------------------===//
1032 
1034  switch (OptimizeRegAlloc) {
1035  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1036  case cl::BOU_TRUE: return true;
1037  case cl::BOU_FALSE: return false;
1038  }
1039  llvm_unreachable("Invalid optimize-regalloc state");
1040 }
1041 
1042 /// RegisterRegAlloc's global Registry tracks allocator registration.
1045 
1046 /// A dummy default pass factory indicates whether the register allocator is
1047 /// overridden on the command line.
1049 
1050 static RegisterRegAlloc
1051 defaultRegAlloc("default",
1052  "pick register allocator based on -O option",
1054 
1056  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1057 
1058  if (!Ctor) {
1059  Ctor = RegAlloc;
1060  RegisterRegAlloc::setDefault(RegAlloc);
1061  }
1062 }
1063 
1064 /// Instantiate the default register allocator pass for this target for either
1065 /// the optimized or unoptimized allocation path. This will be added to the pass
1066 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1067 /// in the optimized case.
1068 ///
1069 /// A target that uses the standard regalloc pass order for fast or optimized
1070 /// allocation may still override this for per-target regalloc
1071 /// selection. But -regalloc=... always takes precedence.
1073  if (Optimized)
1075  else
1076  return createFastRegisterAllocator();
1077 }
1078 
1079 /// Find and instantiate the register allocation pass requested by this target
1080 /// at the current optimization level. Different register allocators are
1081 /// defined as separate passes because they may require different analysis.
1082 ///
1083 /// This helper ensures that the regalloc= option is always available,
1084 /// even for targets that override the default allocator.
1085 ///
1086 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1087 /// this can be folded into addPass.
1089  // Initialize the global default.
1090  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1092 
1093  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1094  if (Ctor != useDefaultRegisterAllocator)
1095  return Ctor();
1096 
1097  // With no -regalloc= override, ask the target for a regalloc pass.
1098  return createTargetRegisterAllocator(Optimized);
1099 }
1100 
1101 /// Return true if the default global register allocator is in use and
1102 /// has not be overriden on the command line with '-regalloc=...'
1104  return RegAlloc.getNumOccurrences() == 0;
1105 }
1106 
1107 /// Add the minimum set of target-independent passes that are required for
1108 /// register allocation. No coalescing or scheduling.
1110  addPass(&PHIEliminationID, false);
1112 
1113  if (RegAllocPass)
1114  addPass(RegAllocPass);
1115 }
1116 
1117 /// Add standard target-independent passes that are tightly coupled with
1118 /// optimized register allocation, including coalescing, machine instruction
1119 /// scheduling, and register allocation itself.
1121  addPass(&DetectDeadLanesID, false);
1122 
1123  addPass(&ProcessImplicitDefsID, false);
1124 
1125  // LiveVariables currently requires pure SSA form.
1126  //
1127  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1128  // LiveVariables can be removed completely, and LiveIntervals can be directly
1129  // computed. (We still either need to regenerate kill flags after regalloc, or
1130  // preferably fix the scavenger to not depend on them).
1131  addPass(&LiveVariablesID, false);
1132 
1133  // Edge splitting is smarter with machine loop info.
1134  addPass(&MachineLoopInfoID, false);
1135  addPass(&PHIEliminationID, false);
1136 
1137  // Eventually, we want to run LiveIntervals before PHI elimination.
1138  if (EarlyLiveIntervals)
1139  addPass(&LiveIntervalsID, false);
1140 
1143 
1144  // The machine scheduler may accidentally create disconnected components
1145  // when moving subregister definitions around, avoid this by splitting them to
1146  // separate vregs before. Splitting can also improve reg. allocation quality.
1148 
1149  // PreRA instruction scheduling.
1151 
1152  if (RegAllocPass) {
1153  // Add the selected register allocation pass.
1154  addPass(RegAllocPass);
1155 
1156  // Allow targets to change the register assignments before rewriting.
1157  addPreRewrite();
1158 
1159  // Finally rewrite virtual registers.
1161 
1162  // Perform stack slot coloring and post-ra machine LICM.
1163  //
1164  // FIXME: Re-enable coloring with register when it's capable of adding
1165  // kill markers.
1167 
1168  // Copy propagate to forward register uses and try to eliminate COPYs that
1169  // were not coalesced.
1171 
1172  // Run post-ra machine LICM to hoist reloads / remats.
1173  //
1174  // FIXME: can this move into MachineLateOptimization?
1176  }
1177 }
1178 
1179 //===---------------------------------------------------------------------===//
1180 /// Post RegAlloc Pass Configuration
1181 //===---------------------------------------------------------------------===//
1182 
1183 /// Add passes that optimize machine instructions after register allocation.
1185  // Branch folding must be run after regalloc and prolog/epilog insertion.
1187 
1188  // Tail duplication.
1189  // Note that duplicating tail just increases code size and degrades
1190  // performance for targets that require Structured Control Flow.
1191  // In addition it can also make CFG irreducible. Thus we disable it.
1192  if (!TM->requiresStructuredCFG())
1194 
1195  // Copy propagation.
1197 }
1198 
1199 /// Add standard GC passes.
1202  return true;
1203 }
1204 
1205 /// Add standard basic block placement passes.
1208  // Run a separate pass to collect block placement statistics.
1211  }
1212 }
1213 
1214 //===---------------------------------------------------------------------===//
1215 /// GlobalISel Configuration
1216 //===---------------------------------------------------------------------===//
1219 }
1220 
1223 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & FEntryInserterID
This pass inserts FEntry calls.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5243
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
static void setDefault(FunctionPassCtor C)
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:75
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
amdgpu Simplify well known AMD library false Value Value const Twine & Name
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:86
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:910
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:827
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), cl::values(clEnumValN(AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(NeverOutline, "never", "Disable all outlining"), clEnumValN(AlwaysOutline, "", "")))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:72
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly&#39;s exception handling s...
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:100
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
Windows Exception Handling.
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:100
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:643
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
int getNumOccurrences() const
Definition: CommandLine.h:384
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterRegAlloc&#39;s global Registry tracks allocator registration.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:70
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:31
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:210
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
FunctionPass *(*)() FunctionPassCtor
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:169
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
A utility class that uses RAII to save and restore the value of a variable.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:618
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
Definition: TargetMachine.h:97
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
void setGlobalISel(bool Enable)
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
bool shouldPrintMachineCode() const
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:217
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:251
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:213
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set...
This file provides utility classes that use RAII to save and restore values.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:570
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
No exception support.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...