LLVM  8.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include "llvm/Transforms/Utils.h"
47 #include <cassert>
48 #include <string>
49 
50 using namespace llvm;
51 
52 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
53  cl::desc("Enable interprocedural register allocation "
54  "to reduce load/store at procedure calls."));
55 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
56  cl::desc("Disable Post Regalloc Scheduler"));
57 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
58  cl::desc("Disable branch folding"));
59 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
60  cl::desc("Disable tail duplication"));
61 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
62  cl::desc("Disable pre-register allocation tail duplication"));
63 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
64  cl::Hidden, cl::desc("Disable probability-driven block placement"));
65 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
66  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
67 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
68  cl::desc("Disable Stack Slot Coloring"));
69 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
70  cl::desc("Disable Machine Dead Code Elimination"));
71 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
72  cl::desc("Disable Early If-conversion"));
73 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
74  cl::desc("Disable Machine LICM"));
75 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
76  cl::desc("Disable Machine Common Subexpression Elimination"));
78  "optimize-regalloc", cl::Hidden,
79  cl::desc("Enable optimized register allocation compilation path."));
80 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
81  cl::Hidden,
82  cl::desc("Disable Machine LICM"));
83 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
84  cl::desc("Disable Machine Sinking"));
85 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
86  cl::Hidden,
87  cl::desc("Disable PostRA Machine Sinking"));
88 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
89  cl::desc("Disable Loop Strength Reduction Pass"));
90 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
91  cl::Hidden, cl::desc("Disable ConstantHoisting"));
92 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
93  cl::desc("Disable Codegen Prepare"));
94 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
95  cl::desc("Disable Copy Propagation pass"));
96 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
97  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
99  "enable-implicit-null-checks",
100  cl::desc("Fold null checks into faulting memory operations"),
101  cl::init(false), cl::Hidden);
102 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
103  cl::desc("Disable MergeICmps Pass"),
104  cl::init(false), cl::Hidden);
105 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
106  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
107 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
108  cl::desc("Print LLVM IR input to isel pass"));
109 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
110  cl::desc("Dump garbage collector data"));
112  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
113  cl::desc("Verify generated machine code"),
116 // Enable or disable the MachineOutliner.
118  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
119  cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
121  "Run on all functions guaranteed to be beneficial"),
122  clEnumValN(NeverOutline, "never", "Disable all outlining"),
123  // Sentinel value for unspecified option.
124  clEnumValN(AlwaysOutline, "", "")));
125 // Enable or disable FastISel. Both options are needed, because
126 // FastISel is enabled by default with -fast, and we wish to be
127 // able to enable or disable fast-isel independently from -O0.
129 EnableFastISelOption("fast-isel", cl::Hidden,
130  cl::desc("Enable the \"fast\" instruction selector"));
131 
133  "global-isel", cl::Hidden,
134  cl::desc("Enable the \"global\" instruction selector"));
135 
137  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
138  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
139 
141  "global-isel-abort", cl::Hidden,
142  cl::desc("Enable abort calls when \"global\" instruction selection "
143  "fails to lower/select an instruction: 0 disable the abort, "
144  "1 enable the abort, and "
145  "2 disable the abort but emit a diagnostic on failure"),
146  cl::init(1));
147 
148 // Temporary option to allow experimenting with MachineScheduler as a post-RA
149 // scheduler. Targets can "properly" enable this with
150 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
151 // Targets can return true in targetSchedulesPostRAScheduling() and
152 // insert a PostRA scheduling pass wherever it wants.
153 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
154  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
155 
156 // Experimental option to run live interval analysis early.
157 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
158  cl::desc("Run live interval analysis earlier in the pipeline"));
159 
160 // Experimental option to use CFL-AA in codegen
163  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
164  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
165  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
167  "Enable unification-based CFL-AA"),
169  "Enable inclusion-based CFL-AA"),
170  clEnumValN(CFLAAType::Both, "both",
171  "Enable both variants of CFL-AA")));
172 
173 /// Option names for limiting the codegen pipeline.
174 /// Those are used in error reporting and we didn't want
175 /// to duplicate their names all over the place.
176 const char *StartAfterOptName = "start-after";
177 const char *StartBeforeOptName = "start-before";
178 const char *StopAfterOptName = "stop-after";
179 const char *StopBeforeOptName = "stop-before";
180 
182  StartAfterOpt(StringRef(StartAfterOptName),
183  cl::desc("Resume compilation after a specific pass"),
184  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
185 
187  StartBeforeOpt(StringRef(StartBeforeOptName),
188  cl::desc("Resume compilation before a specific pass"),
189  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
190 
192  StopAfterOpt(StringRef(StopAfterOptName),
193  cl::desc("Stop compilation after a specific pass"),
194  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
195 
197  StopBeforeOpt(StringRef(StopBeforeOptName),
198  cl::desc("Stop compilation before a specific pass"),
199  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
200 
201 /// Allow standard passes to be disabled by command line options. This supports
202 /// simple binary flags that either suppress the pass or do nothing.
203 /// i.e. -disable-mypass=false has no effect.
204 /// These should be converted to boolOrDefault in order to use applyOverride.
206  bool Override) {
207  if (Override)
208  return IdentifyingPassPtr();
209  return PassID;
210 }
211 
212 /// Allow standard passes to be disabled by the command line, regardless of who
213 /// is adding the pass.
214 ///
215 /// StandardID is the pass identified in the standard pass pipeline and provided
216 /// to addPass(). It may be a target-specific ID in the case that the target
217 /// directly adds its own pass, but in that case we harmlessly fall through.
218 ///
219 /// TargetID is the pass that the target has configured to override StandardID.
220 ///
221 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
222 /// pass to run. This allows multiple options to control a single pass depending
223 /// on where in the pipeline that pass is added.
225  IdentifyingPassPtr TargetID) {
226  if (StandardID == &PostRASchedulerID)
227  return applyDisable(TargetID, DisablePostRASched);
228 
229  if (StandardID == &BranchFolderPassID)
230  return applyDisable(TargetID, DisableBranchFold);
231 
232  if (StandardID == &TailDuplicateID)
233  return applyDisable(TargetID, DisableTailDuplicate);
234 
235  if (StandardID == &EarlyTailDuplicateID)
236  return applyDisable(TargetID, DisableEarlyTailDup);
237 
238  if (StandardID == &MachineBlockPlacementID)
239  return applyDisable(TargetID, DisableBlockPlacement);
240 
241  if (StandardID == &StackSlotColoringID)
242  return applyDisable(TargetID, DisableSSC);
243 
244  if (StandardID == &DeadMachineInstructionElimID)
245  return applyDisable(TargetID, DisableMachineDCE);
246 
247  if (StandardID == &EarlyIfConverterID)
248  return applyDisable(TargetID, DisableEarlyIfConversion);
249 
250  if (StandardID == &EarlyMachineLICMID)
251  return applyDisable(TargetID, DisableMachineLICM);
252 
253  if (StandardID == &MachineCSEID)
254  return applyDisable(TargetID, DisableMachineCSE);
255 
256  if (StandardID == &MachineLICMID)
257  return applyDisable(TargetID, DisablePostRAMachineLICM);
258 
259  if (StandardID == &MachineSinkingID)
260  return applyDisable(TargetID, DisableMachineSink);
261 
262  if (StandardID == &PostRAMachineSinkingID)
263  return applyDisable(TargetID, DisablePostRAMachineSink);
264 
265  if (StandardID == &MachineCopyPropagationID)
266  return applyDisable(TargetID, DisableCopyProp);
267 
268  return TargetID;
269 }
270 
271 //===---------------------------------------------------------------------===//
272 /// TargetPassConfig
273 //===---------------------------------------------------------------------===//
274 
275 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
276  "Target Pass Configuration", false, false)
277 char TargetPassConfig::ID = 0;
278 
279 namespace {
280 
281 struct InsertedPass {
286 
287  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
288  bool VerifyAfter, bool PrintAfter)
289  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
290  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
291 
293  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
294  if (InsertedPassID.isInstance())
295  return InsertedPassID.getInstance();
296  Pass *NP = Pass::createPass(InsertedPassID.getID());
297  assert(NP && "Pass ID not registered");
298  return NP;
299  }
300 };
301 
302 } // end anonymous namespace
303 
304 namespace llvm {
305 
307 public:
308  // List of passes explicitly substituted by this target. Normally this is
309  // empty, but it is a convenient way to suppress or replace specific passes
310  // that are part of a standard pass pipeline without overridding the entire
311  // pipeline. This mechanism allows target options to inherit a standard pass's
312  // user interface. For example, a target may disable a standard pass by
313  // default by substituting a pass ID of zero, and the user may still enable
314  // that standard pass with an explicit command line option.
316 
317  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
318  /// is inserted after each instance of the first one.
320 };
321 
322 } // end namespace llvm
323 
324 // Out of line virtual method.
326  delete Impl;
327 }
328 
329 static const PassInfo *getPassInfo(StringRef PassName) {
330  if (PassName.empty())
331  return nullptr;
332 
334  const PassInfo *PI = PR.getPassInfo(PassName);
335  if (!PI)
336  report_fatal_error(Twine('\"') + Twine(PassName) +
337  Twine("\" pass is not registered."));
338  return PI;
339 }
340 
342  const PassInfo *PI = getPassInfo(PassName);
343  return PI ? PI->getTypeInfo() : nullptr;
344 }
345 
346 void TargetPassConfig::setStartStopPasses() {
347  StartBefore = getPassIDFromName(StartBeforeOpt);
348  StartAfter = getPassIDFromName(StartAfterOpt);
349  StopBefore = getPassIDFromName(StopBeforeOpt);
350  StopAfter = getPassIDFromName(StopAfterOpt);
351  if (StartBefore && StartAfter)
352  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
353  Twine(StartAfterOptName) + Twine(" specified!"));
354  if (StopBefore && StopAfter)
355  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
356  Twine(StopAfterOptName) + Twine(" specified!"));
357  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
358 }
359 
360 // Out of line constructor provides default values for pass options and
361 // registers all common codegen passes.
363  : ImmutablePass(ID), PM(&pm), TM(&TM) {
364  Impl = new PassConfigImpl();
365 
366  // Register all target independent codegen passes to activate their PassIDs,
367  // including this pass itself.
369 
370  // Also register alias analysis passes required by codegen passes.
373 
374  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
375  TM.Options.PrintMachineCode = true;
376 
377  if (EnableIPRA.getNumOccurrences())
379  else {
380  // If not explicitly specified, use target default.
381  TM.Options.EnableIPRA = TM.useIPRA();
382  }
383 
384  if (TM.Options.EnableIPRA)
386 
387  setStartStopPasses();
388 }
389 
391  return TM->getOptLevel();
392 }
393 
394 /// Insert InsertedPassID pass after TargetPassID.
396  IdentifyingPassPtr InsertedPassID,
397  bool VerifyAfter, bool PrintAfter) {
398  assert(((!InsertedPassID.isInstance() &&
399  TargetPassID != InsertedPassID.getID()) ||
400  (InsertedPassID.isInstance() &&
401  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
402  "Insert a pass after itself!");
403  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
404  PrintAfter);
405 }
406 
407 /// createPassConfig - Create a pass configuration object to be used by
408 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
409 ///
410 /// Targets may override this to extend TargetPassConfig.
412  return new TargetPassConfig(*this, PM);
413 }
414 
416  : ImmutablePass(ID) {
417  report_fatal_error("Trying to construct TargetPassConfig without a target "
418  "machine. Scheduling a CodeGen pass without a target "
419  "triple set?");
420 }
421 
423  return StartBefore || StartAfter || StopBefore || StopAfter;
424 }
425 
426 std::string
429  return std::string();
430  std::string Res;
431  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
433  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
434  StopAfterOptName, StopBeforeOptName};
435  bool IsFirst = true;
436  for (int Idx = 0; Idx < 4; ++Idx)
437  if (!PassNames[Idx]->empty()) {
438  if (!IsFirst)
439  Res += Separator;
440  IsFirst = false;
441  Res += OptNames[Idx];
442  }
443  return Res;
444 }
445 
446 // Helper to verify the analysis is really immutable.
447 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
448  assert(!Initialized && "PassConfig is immutable");
449  Opt = Val;
450 }
451 
453  IdentifyingPassPtr TargetID) {
454  Impl->TargetPasses[StandardID] = TargetID;
455 }
456 
459  I = Impl->TargetPasses.find(ID);
460  if (I == Impl->TargetPasses.end())
461  return ID;
462  return I->second;
463 }
464 
467  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
468  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
469  FinalPtr.getID() != ID;
470 }
471 
472 /// Add a pass to the PassManager if that pass is supposed to be run. If the
473 /// Started/Stopped flags indicate either that the compilation should start at
474 /// a later pass or that it should stop after an earlier pass, then do not add
475 /// the pass. Finally, compare the current pass against the StartAfter
476 /// and StopAfter options and change the Started/Stopped flags accordingly.
477 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
478  assert(!Initialized && "PassConfig is immutable");
479 
480  // Cache the Pass ID here in case the pass manager finds this pass is
481  // redundant with ones already scheduled / available, and deletes it.
482  // Fundamentally, once we add the pass to the manager, we no longer own it
483  // and shouldn't reference it.
484  AnalysisID PassID = P->getPassID();
485 
486  if (StartBefore == PassID)
487  Started = true;
488  if (StopBefore == PassID)
489  Stopped = true;
490  if (Started && !Stopped) {
491  std::string Banner;
492  // Construct banner message before PM->add() as that may delete the pass.
493  if (AddingMachinePasses && (printAfter || verifyAfter))
494  Banner = std::string("After ") + std::string(P->getPassName());
495  PM->add(P);
496  if (AddingMachinePasses) {
497  if (printAfter)
498  addPrintPass(Banner);
499  if (verifyAfter)
500  addVerifyPass(Banner);
501  }
502 
503  // Add the passes after the pass P if there is any.
504  for (auto IP : Impl->InsertedPasses) {
505  if (IP.TargetPassID == PassID)
506  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
507  }
508  } else {
509  delete P;
510  }
511  if (StopAfter == PassID)
512  Stopped = true;
513  if (StartAfter == PassID)
514  Started = true;
515  if (Stopped && !Started)
516  report_fatal_error("Cannot stop compilation after pass that is not run");
517 }
518 
519 /// Add a CodeGen pass at this point in the pipeline after checking for target
520 /// and command line overrides.
521 ///
522 /// addPass cannot return a pointer to the pass instance because is internal the
523 /// PassManager and the instance we create here may already be freed.
525  bool printAfter) {
526  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
527  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
528  if (!FinalPtr.isValid())
529  return nullptr;
530 
531  Pass *P;
532  if (FinalPtr.isInstance())
533  P = FinalPtr.getInstance();
534  else {
535  P = Pass::createPass(FinalPtr.getID());
536  if (!P)
537  llvm_unreachable("Pass ID not registered");
538  }
539  AnalysisID FinalID = P->getPassID();
540  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
541 
542  return FinalID;
543 }
544 
545 void TargetPassConfig::printAndVerify(const std::string &Banner) {
546  addPrintPass(Banner);
547  addVerifyPass(Banner);
548 }
549 
550 void TargetPassConfig::addPrintPass(const std::string &Banner) {
551  if (TM->shouldPrintMachineCode())
552  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
553 }
554 
555 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
557 #ifdef EXPENSIVE_CHECKS
559  Verify = TM->isMachineVerifierClean();
560 #endif
561  if (Verify)
562  PM->add(createMachineVerifierPass(Banner));
563 }
564 
565 /// Add common target configurable passes that perform LLVM IR to IR transforms
566 /// following machine independent optimization.
568  switch (UseCFLAA) {
571  break;
572  case CFLAAType::Andersen:
574  break;
575  case CFLAAType::Both:
578  break;
579  default:
580  break;
581  }
582 
583  // Basic AliasAnalysis support.
584  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
585  // BasicAliasAnalysis wins if they disagree. This is intended to help
586  // support "obvious" type-punning idioms.
590 
591  // Before running any passes, run the verifier to determine if the input
592  // coming from the front-end and/or optimizer is valid.
593  if (!DisableVerify)
595 
596  // Run loop strength reduction before anything else.
597  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
599  if (PrintLSR)
600  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
601  }
602 
603  if (getOptLevel() != CodeGenOpt::None) {
604  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
605  // loads and compares. ExpandMemCmpPass then tries to expand those calls
606  // into optimally-sized loads and compares. The transforms are enabled by a
607  // target lowering hook.
608  if (!DisableMergeICmps)
611  }
612 
613  // Run GC lowering passes for builtin collectors
614  // TODO: add a pass insertion point here
617 
618  // Make sure that no unreachable blocks are instruction selected.
620 
621  // Prepare expensive constants for SelectionDAG.
624 
627 
628  // Instrument function entry and exit, e.g. with calls to mcount().
630 
631  // Add scalarization of target's unsupported masked memory intrinsics pass.
632  // the unsupported intrinsic will be replaced with a chain of basic blocks,
633  // that stores/loads element one-by-one if the appropriate mask bit is set.
635 
636  // Expand reduction intrinsics into shuffle sequences if the target wants to.
638 }
639 
640 /// Turn exception handling constructs into something the code generators can
641 /// handle.
643  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
644  assert(MCAI && "No MCAsmInfo");
645  switch (MCAI->getExceptionHandlingType()) {
647  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
648  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
649  // catch info can get misplaced when a selector ends up more than one block
650  // removed from the parent invoke(s). This could happen when a landing
651  // pad is shared by multiple invokes and is also a target of a normal
652  // edge from elsewhere.
658  break;
660  // We support using both GCC-style and MSVC-style exceptions on Windows, so
661  // add both preparation passes. Each pass will only actually run if it
662  // recognizes the personality function.
665  break;
667  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
668  // on catchpads and cleanuppads because it does not outline them into
669  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
670  // should remove PHIs there.
671  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
673  break;
676 
677  // The lower invoke pass may create unreachable code. Remove it.
679  break;
680  }
681 }
682 
683 /// Add pass to prepare the LLVM IR for code generation. This should be done
684 /// before exception handling preparation passes.
689 }
690 
691 /// Add common passes that perform LLVM IR to IR transforms in preparation for
692 /// instruction selection.
694  addPreISel();
695 
696  // Force codegen to run according to the callgraph.
698  addPass(new DummyCGSCCPass);
699 
700  // Add both the safe stack and the stack protection passes: each of them will
701  // only protect functions that have corresponding attributes.
704 
705  if (PrintISelInput)
707  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
708 
709  // All passes which modify the LLVM IR are now complete; run the verifier
710  // to ensure that the IR is valid.
711  if (!DisableVerify)
713 }
714 
716  // Enable FastISel with -fast-isel, but allow that to be overridden.
717  TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
718  if (EnableFastISelOption == cl::BOU_TRUE ||
720  TM->setFastISel(true);
721 
722  // Ask the target for an instruction selector.
723  // Explicitly enabling fast-isel should override implicitly enabled
724  // global-isel.
725  if (EnableGlobalISelOption == cl::BOU_TRUE ||
726  (EnableGlobalISelOption == cl::BOU_UNSET &&
727  TM->Options.EnableGlobalISel && EnableFastISelOption != cl::BOU_TRUE)) {
728  TM->setFastISel(false);
729 
730  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
731  if (addIRTranslator())
732  return true;
733 
735 
736  if (addLegalizeMachineIR())
737  return true;
738 
739  // Before running the register bank selector, ask the target if it
740  // wants to run some passes.
742 
743  if (addRegBankSelect())
744  return true;
745 
747 
749  return true;
750 
751  // Pass to reset the MachineFunction if the ISel failed.
754 
755  // Provide a fallback path when we do not want to abort on
756  // not-yet-supported input.
758  return true;
759 
760  } else if (addInstSelector())
761  return true;
762 
763  return false;
764 }
765 
767  if (TM->useEmulatedTLS())
769 
772  addIRPasses();
775  addISelPrepare();
776 
777  return addCoreISelPasses();
778 }
779 
780 /// -regalloc=... command line option.
781 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
785  cl::desc("Register allocator to use"));
786 
787 /// Add the complete set of target-independent postISel code generator passes.
788 ///
789 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
790 /// with nontrivial configuration or multiple passes are broken out below in
791 /// add%Stage routines.
792 ///
793 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
794 /// addPre/Post methods with empty header implementations allow injecting
795 /// target-specific fixups just before or after major stages. Additionally,
796 /// targets have the flexibility to change pass order within a stage by
797 /// overriding default implementation of add%Stage routines below. Each
798 /// technique has maintainability tradeoffs because alternate pass orders are
799 /// not well supported. addPre/Post works better if the target pass is easily
800 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
801 /// the target should override the stage instead.
802 ///
803 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
804 /// before/after any target-independent pass. But it's currently overkill.
806  AddingMachinePasses = true;
807 
808  // Insert a machine instr printer pass after the specified pass.
809  if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
810  !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
812  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
813  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
814  assert (TPI && IPI && "Pass ID not registered!");
815  const char *TID = (const char *)(TPI->getTypeInfo());
816  const char *IID = (const char *)(IPI->getTypeInfo());
817  insertPass(TID, IID);
818  }
819 
820  // Print the instruction selected machine code...
821  printAndVerify("After Instruction Selection");
822 
823  // Expand pseudo-instructions emitted by ISel.
825 
826  // Add passes that optimize machine instructions in SSA form.
827  if (getOptLevel() != CodeGenOpt::None) {
829  } else {
830  // If the target requests it, assign local variables to stack slots relative
831  // to one another and simplify frame index references where possible.
833  }
834 
835  if (TM->Options.EnableIPRA)
837 
838  // Run pre-ra passes.
839  addPreRegAlloc();
840 
841  // Run register allocation and passes that are tightly coupled with it,
842  // including phi elimination and scheduling.
843  if (getOptimizeRegAlloc())
845  else {
846  if (RegAlloc != &useDefaultRegisterAllocator &&
847  RegAlloc != &createFastRegisterAllocator)
848  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
850  }
851 
852  // Run post-ra passes.
853  addPostRegAlloc();
854 
855  // Insert prolog/epilog code. Eliminate abstract frame index references...
856  if (getOptLevel() != CodeGenOpt::None) {
859  }
860 
861  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
862  // do so if it hasn't been disabled, substituted, or overridden.
865 
866  /// Add passes that optimize machine instructions after register allocation.
867  if (getOptLevel() != CodeGenOpt::None)
869 
870  // Expand pseudo instructions before second scheduling pass.
872 
873  // Run pre-sched2 passes.
874  addPreSched2();
875 
878 
879  // Second pass scheduler.
880  // Let Target optionally insert this pass by itself at some other
881  // point.
882  if (getOptLevel() != CodeGenOpt::None &&
884  if (MISchedPostRA)
886  else
888  }
889 
890  // GC
891  if (addGCPasses()) {
892  if (PrintGCInfo)
893  addPass(createGCInfoPrinter(dbgs()), false, false);
894  }
895 
896  // Basic block placement.
897  if (getOptLevel() != CodeGenOpt::None)
899 
900  addPreEmitPass();
901 
902  if (TM->Options.EnableIPRA)
903  // Collect register usage information and produce a register mask of
904  // clobbered registers, to be used to optimize call sites.
906 
907  addPass(&FuncletLayoutID, false);
908 
909  addPass(&StackMapLivenessID, false);
910  addPass(&LiveDebugValuesID, false);
911 
912  // Insert before XRay Instrumentation.
913  addPass(&FEntryInserterID, false);
914 
916  addPass(&PatchableFunctionID, false);
917 
919  EnableMachineOutliner != NeverOutline) {
920  bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
921  bool AddOutliner = RunOnAllFunctions ||
923  if (AddOutliner)
924  addPass(createMachineOutlinerPass(RunOnAllFunctions));
925  }
926 
927  // Add passes that directly emit MI after all other MI passes.
928  addPreEmitPass2();
929 
930  AddingMachinePasses = false;
931 }
932 
933 /// Add passes that optimize machine instructions in SSA form.
935  // Pre-ra tail duplication.
937 
938  // Optimize PHIs before DCE: removing dead PHI cycles may make more
939  // instructions dead.
940  addPass(&OptimizePHIsID, false);
941 
942  // This pass merges large allocas. StackSlotColoring is a different pass
943  // which merges spill slots.
944  addPass(&StackColoringID, false);
945 
946  // If the target requests it, assign local variables to stack slots relative
947  // to one another and simplify frame index references where possible.
949 
950  // With optimization, dead code should already be eliminated. However
951  // there is one known exception: lowered code for arguments that are only
952  // used by tail calls, where the tail calls reuse the incoming stack
953  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
955 
956  // Allow targets to insert passes that improve instruction level parallelism,
957  // like if-conversion. Such passes will typically need dominator trees and
958  // loop info, just like LICM and CSE below.
959  addILPOpts();
960 
961  addPass(&EarlyMachineLICMID, false);
962  addPass(&MachineCSEID, false);
963 
965 
967  // Clean-up the dead code that may have been generated by peephole
968  // rewriting.
970 }
971 
972 //===---------------------------------------------------------------------===//
973 /// Register Allocation Pass Configuration
974 //===---------------------------------------------------------------------===//
975 
977  switch (OptimizeRegAlloc) {
978  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
979  case cl::BOU_TRUE: return true;
980  case cl::BOU_FALSE: return false;
981  }
982  llvm_unreachable("Invalid optimize-regalloc state");
983 }
984 
985 /// RegisterRegAlloc's global Registry tracks allocator registration.
987 
988 /// A dummy default pass factory indicates whether the register allocator is
989 /// overridden on the command line.
991 
992 static RegisterRegAlloc
993 defaultRegAlloc("default",
994  "pick register allocator based on -O option",
996 
998  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
999 
1000  if (!Ctor) {
1001  Ctor = RegAlloc;
1002  RegisterRegAlloc::setDefault(RegAlloc);
1003  }
1004 }
1005 
1006 /// Instantiate the default register allocator pass for this target for either
1007 /// the optimized or unoptimized allocation path. This will be added to the pass
1008 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1009 /// in the optimized case.
1010 ///
1011 /// A target that uses the standard regalloc pass order for fast or optimized
1012 /// allocation may still override this for per-target regalloc
1013 /// selection. But -regalloc=... always takes precedence.
1015  if (Optimized)
1017  else
1018  return createFastRegisterAllocator();
1019 }
1020 
1021 /// Find and instantiate the register allocation pass requested by this target
1022 /// at the current optimization level. Different register allocators are
1023 /// defined as separate passes because they may require different analysis.
1024 ///
1025 /// This helper ensures that the regalloc= option is always available,
1026 /// even for targets that override the default allocator.
1027 ///
1028 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1029 /// this can be folded into addPass.
1031  // Initialize the global default.
1032  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1034 
1035  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1036  if (Ctor != useDefaultRegisterAllocator)
1037  return Ctor();
1038 
1039  // With no -regalloc= override, ask the target for a regalloc pass.
1040  return createTargetRegisterAllocator(Optimized);
1041 }
1042 
1043 /// Return true if the default global register allocator is in use and
1044 /// has not be overriden on the command line with '-regalloc=...'
1046  return RegAlloc.getNumOccurrences() == 0;
1047 }
1048 
1049 /// Add the minimum set of target-independent passes that are required for
1050 /// register allocation. No coalescing or scheduling.
1052  addPass(&PHIEliminationID, false);
1054 
1055  if (RegAllocPass)
1056  addPass(RegAllocPass);
1057 }
1058 
1059 /// Add standard target-independent passes that are tightly coupled with
1060 /// optimized register allocation, including coalescing, machine instruction
1061 /// scheduling, and register allocation itself.
1063  addPass(&DetectDeadLanesID, false);
1064 
1065  addPass(&ProcessImplicitDefsID, false);
1066 
1067  // LiveVariables currently requires pure SSA form.
1068  //
1069  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1070  // LiveVariables can be removed completely, and LiveIntervals can be directly
1071  // computed. (We still either need to regenerate kill flags after regalloc, or
1072  // preferably fix the scavenger to not depend on them).
1073  addPass(&LiveVariablesID, false);
1074 
1075  // Edge splitting is smarter with machine loop info.
1076  addPass(&MachineLoopInfoID, false);
1077  addPass(&PHIEliminationID, false);
1078 
1079  // Eventually, we want to run LiveIntervals before PHI elimination.
1080  if (EarlyLiveIntervals)
1081  addPass(&LiveIntervalsID, false);
1082 
1085 
1086  // The machine scheduler may accidentally create disconnected components
1087  // when moving subregister definitions around, avoid this by splitting them to
1088  // separate vregs before. Splitting can also improve reg. allocation quality.
1090 
1091  // PreRA instruction scheduling.
1093 
1094  if (RegAllocPass) {
1095  // Add the selected register allocation pass.
1096  addPass(RegAllocPass);
1097 
1098  // Allow targets to change the register assignments before rewriting.
1099  addPreRewrite();
1100 
1101  // Finally rewrite virtual registers.
1103 
1104  // Perform stack slot coloring and post-ra machine LICM.
1105  //
1106  // FIXME: Re-enable coloring with register when it's capable of adding
1107  // kill markers.
1109 
1110  // Copy propagate to forward register uses and try to eliminate COPYs that
1111  // were not coalesced.
1113 
1114  // Run post-ra machine LICM to hoist reloads / remats.
1115  //
1116  // FIXME: can this move into MachineLateOptimization?
1118  }
1119 }
1120 
1121 //===---------------------------------------------------------------------===//
1122 /// Post RegAlloc Pass Configuration
1123 //===---------------------------------------------------------------------===//
1124 
1125 /// Add passes that optimize machine instructions after register allocation.
1127  // Branch folding must be run after regalloc and prolog/epilog insertion.
1129 
1130  // Tail duplication.
1131  // Note that duplicating tail just increases code size and degrades
1132  // performance for targets that require Structured Control Flow.
1133  // In addition it can also make CFG irreducible. Thus we disable it.
1134  if (!TM->requiresStructuredCFG())
1136 
1137  // Copy propagation.
1139 }
1140 
1141 /// Add standard GC passes.
1144  return true;
1145 }
1146 
1147 /// Add standard basic block placement passes.
1150  // Run a separate pass to collect block placement statistics.
1153  }
1154 }
1155 
1156 //===---------------------------------------------------------------------===//
1157 /// GlobalISel Configuration
1158 //===---------------------------------------------------------------------===//
1160  if (EnableGlobalISelAbort.getNumOccurrences() > 0)
1161  return EnableGlobalISelAbort == 1;
1162 
1163  // When no abort behaviour is specified, we don't abort if the target says
1164  // that GISel is enabled.
1165  return !TM->Options.EnableGlobalISel;
1166 }
1167 
1169  return EnableGlobalISelAbort == 2;
1170 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
char & FEntryInserterID
This pass inserts FEntry calls.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5133
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
static void setDefault(FunctionPassCtor C)
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static MachinePassRegistry Registry
RegisterRegAlloc&#39;s global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:75
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
bool hasLimitedCodeGenPipeline() const
Describe the status of the codegen pipeline set by this target pass config.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:86
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:913
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:826
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), cl::values(clEnumValN(AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(NeverOutline, "never", "Disable all outlining"), clEnumValN(AlwaysOutline, "", "")))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:72
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly&#39;s exception handling s...
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:99
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
Windows Exception Handling.
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:100
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:630
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
int getNumOccurrences() const
Definition: CommandLine.h:371
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:69
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:31
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
static cl::opt< int > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction: 0 disable the abort, " "1 enable the abort, and " "2 disable the abort but emit a diagnostic on failure"), cl::init(1))
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
FunctionPass *(*)() FunctionPassCtor
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
A utility class that uses RAII to save and restore the value of a variable.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:605
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
Definition: TargetMachine.h:97
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
bool shouldPrintMachineCode() const
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:217
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative intrinsic to instructions.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:213
This file provides utility classes that use RAII to save and restore values.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:570
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
No exception support.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...