LLVM  6.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
43 #include "llvm/Transforms/Scalar.h"
45 #include <cassert>
46 #include <string>
47 
48 using namespace llvm;
49 
50 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
51  cl::desc("Enable interprocedural register allocation "
52  "to reduce load/store at procedure calls."));
53 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
54  cl::desc("Disable Post Regalloc Scheduler"));
55 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
56  cl::desc("Disable branch folding"));
57 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
58  cl::desc("Disable tail duplication"));
59 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
60  cl::desc("Disable pre-register allocation tail duplication"));
61 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
62  cl::Hidden, cl::desc("Disable probability-driven block placement"));
63 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
64  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
65 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
66  cl::desc("Disable Stack Slot Coloring"));
67 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
68  cl::desc("Disable Machine Dead Code Elimination"));
69 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
70  cl::desc("Disable Early If-conversion"));
71 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
72  cl::desc("Disable Machine LICM"));
73 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
74  cl::desc("Disable Machine Common Subexpression Elimination"));
76  "optimize-regalloc", cl::Hidden,
77  cl::desc("Enable optimized register allocation compilation path."));
78 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
79  cl::Hidden,
80  cl::desc("Disable Machine LICM"));
81 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
82  cl::desc("Disable Machine Sinking"));
83 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
84  cl::desc("Disable Loop Strength Reduction Pass"));
85 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
86  cl::Hidden, cl::desc("Disable ConstantHoisting"));
87 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
88  cl::desc("Disable Codegen Prepare"));
89 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
90  cl::desc("Disable Copy Propagation pass"));
91 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
92  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
94  "enable-implicit-null-checks",
95  cl::desc("Fold null checks into faulting memory operations"),
96  cl::init(false));
98  "enable-mergeicmps",
99  cl::desc("Merge ICmp chains into a single memcmp"),
100  cl::init(false));
101 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
102  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
103 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
104  cl::desc("Print LLVM IR input to isel pass"));
105 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
106  cl::desc("Dump garbage collector data"));
107 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
108  cl::desc("Verify generated machine code"),
109  cl::init(false),
111 static cl::opt<bool> EnableMachineOutliner("enable-machine-outliner",
112  cl::Hidden,
113  cl::desc("Enable machine outliner"));
115  "enable-linkonceodr-outlining",
116  cl::Hidden,
117  cl::desc("Enable the machine outliner on linkonceodr functions"),
118  cl::init(false));
119 // Enable or disable FastISel. Both options are needed, because
120 // FastISel is enabled by default with -fast, and we wish to be
121 // able to enable or disable fast-isel independently from -O0.
123 EnableFastISelOption("fast-isel", cl::Hidden,
124  cl::desc("Enable the \"fast\" instruction selector"));
125 
127  EnableGlobalISel("global-isel", cl::Hidden,
128  cl::desc("Enable the \"global\" instruction selector"));
129 
131 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
132  cl::desc("Print machine instrs"),
133  cl::value_desc("pass-name"), cl::init("option-unspecified"));
134 
136  "global-isel-abort", cl::Hidden,
137  cl::desc("Enable abort calls when \"global\" instruction selection "
138  "fails to lower/select an instruction: 0 disable the abort, "
139  "1 enable the abort, and "
140  "2 disable the abort but emit a diagnostic on failure"),
141  cl::init(1));
142 
143 // Temporary option to allow experimenting with MachineScheduler as a post-RA
144 // scheduler. Targets can "properly" enable this with
145 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
146 // Targets can return true in targetSchedulesPostRAScheduling() and
147 // insert a PostRA scheduling pass wherever it wants.
148 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
149  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
150 
151 // Experimental option to run live interval analysis early.
152 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
153  cl::desc("Run live interval analysis earlier in the pipeline"));
154 
155 // Experimental option to use CFL-AA in codegen
158  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
159  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
160  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
162  "Enable unification-based CFL-AA"),
164  "Enable inclusion-based CFL-AA"),
165  clEnumValN(CFLAAType::Both, "both",
166  "Enable both variants of CFL-AA")));
167 
168 /// Option names for limiting the codegen pipeline.
169 /// Those are used in error reporting and we didn't want
170 /// to duplicate their names all over the place.
171 const char *StartAfterOptName = "start-after";
172 const char *StartBeforeOptName = "start-before";
173 const char *StopAfterOptName = "stop-after";
174 const char *StopBeforeOptName = "stop-before";
175 
177  StartAfterOpt(StringRef(StartAfterOptName),
178  cl::desc("Resume compilation after a specific pass"),
179  cl::value_desc("pass-name"), cl::init(""));
180 
182  StartBeforeOpt(StringRef(StartBeforeOptName),
183  cl::desc("Resume compilation before a specific pass"),
184  cl::value_desc("pass-name"), cl::init(""));
185 
187  StopAfterOpt(StringRef(StopAfterOptName),
188  cl::desc("Stop compilation after a specific pass"),
189  cl::value_desc("pass-name"), cl::init(""));
190 
192  StopBeforeOpt(StringRef(StopBeforeOptName),
193  cl::desc("Stop compilation before a specific pass"),
194  cl::value_desc("pass-name"), cl::init(""));
195 
196 /// Allow standard passes to be disabled by command line options. This supports
197 /// simple binary flags that either suppress the pass or do nothing.
198 /// i.e. -disable-mypass=false has no effect.
199 /// These should be converted to boolOrDefault in order to use applyOverride.
201  bool Override) {
202  if (Override)
203  return IdentifyingPassPtr();
204  return PassID;
205 }
206 
207 /// Allow standard passes to be disabled by the command line, regardless of who
208 /// is adding the pass.
209 ///
210 /// StandardID is the pass identified in the standard pass pipeline and provided
211 /// to addPass(). It may be a target-specific ID in the case that the target
212 /// directly adds its own pass, but in that case we harmlessly fall through.
213 ///
214 /// TargetID is the pass that the target has configured to override StandardID.
215 ///
216 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
217 /// pass to run. This allows multiple options to control a single pass depending
218 /// on where in the pipeline that pass is added.
220  IdentifyingPassPtr TargetID) {
221  if (StandardID == &PostRASchedulerID)
222  return applyDisable(TargetID, DisablePostRASched);
223 
224  if (StandardID == &BranchFolderPassID)
225  return applyDisable(TargetID, DisableBranchFold);
226 
227  if (StandardID == &TailDuplicateID)
228  return applyDisable(TargetID, DisableTailDuplicate);
229 
230  if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
231  return applyDisable(TargetID, DisableEarlyTailDup);
232 
233  if (StandardID == &MachineBlockPlacementID)
234  return applyDisable(TargetID, DisableBlockPlacement);
235 
236  if (StandardID == &StackSlotColoringID)
237  return applyDisable(TargetID, DisableSSC);
238 
239  if (StandardID == &DeadMachineInstructionElimID)
240  return applyDisable(TargetID, DisableMachineDCE);
241 
242  if (StandardID == &EarlyIfConverterID)
243  return applyDisable(TargetID, DisableEarlyIfConversion);
244 
245  if (StandardID == &MachineLICMID)
246  return applyDisable(TargetID, DisableMachineLICM);
247 
248  if (StandardID == &MachineCSEID)
249  return applyDisable(TargetID, DisableMachineCSE);
250 
251  if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
252  return applyDisable(TargetID, DisablePostRAMachineLICM);
253 
254  if (StandardID == &MachineSinkingID)
255  return applyDisable(TargetID, DisableMachineSink);
256 
257  if (StandardID == &MachineCopyPropagationID)
258  return applyDisable(TargetID, DisableCopyProp);
259 
260  return TargetID;
261 }
262 
263 //===---------------------------------------------------------------------===//
264 /// TargetPassConfig
265 //===---------------------------------------------------------------------===//
266 
267 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
268  "Target Pass Configuration", false, false)
269 char TargetPassConfig::ID = 0;
270 
271 // Pseudo Pass IDs.
274 
275 namespace {
276 
277 struct InsertedPass {
278  AnalysisID TargetPassID;
279  IdentifyingPassPtr InsertedPassID;
280  bool VerifyAfter;
281  bool PrintAfter;
282 
283  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
284  bool VerifyAfter, bool PrintAfter)
285  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
286  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
287 
288  Pass *getInsertedPass() const {
289  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
290  if (InsertedPassID.isInstance())
291  return InsertedPassID.getInstance();
292  Pass *NP = Pass::createPass(InsertedPassID.getID());
293  assert(NP && "Pass ID not registered");
294  return NP;
295  }
296 };
297 
298 } // end anonymous namespace
299 
300 namespace llvm {
301 
303 public:
304  // List of passes explicitly substituted by this target. Normally this is
305  // empty, but it is a convenient way to suppress or replace specific passes
306  // that are part of a standard pass pipeline without overridding the entire
307  // pipeline. This mechanism allows target options to inherit a standard pass's
308  // user interface. For example, a target may disable a standard pass by
309  // default by substituting a pass ID of zero, and the user may still enable
310  // that standard pass with an explicit command line option.
312 
313  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
314  /// is inserted after each instance of the first one.
316 };
317 
318 } // end namespace llvm
319 
320 // Out of line virtual method.
322  delete Impl;
323 }
324 
325 static const PassInfo *getPassInfo(StringRef PassName) {
326  if (PassName.empty())
327  return nullptr;
328 
330  const PassInfo *PI = PR.getPassInfo(PassName);
331  if (!PI)
332  report_fatal_error(Twine('\"') + Twine(PassName) +
333  Twine("\" pass is not registered."));
334  return PI;
335 }
336 
338  const PassInfo *PI = getPassInfo(PassName);
339  return PI ? PI->getTypeInfo() : nullptr;
340 }
341 
342 void TargetPassConfig::setStartStopPasses() {
343  StartBefore = getPassIDFromName(StartBeforeOpt);
344  StartAfter = getPassIDFromName(StartAfterOpt);
345  StopBefore = getPassIDFromName(StopBeforeOpt);
346  StopAfter = getPassIDFromName(StopAfterOpt);
347  if (StartBefore && StartAfter)
348  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
349  Twine(StartAfterOptName) + Twine(" specified!"));
350  if (StopBefore && StopAfter)
351  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
352  Twine(StopAfterOptName) + Twine(" specified!"));
353  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
354 }
355 
356 // Out of line constructor provides default values for pass options and
357 // registers all common codegen passes.
359  : ImmutablePass(ID), PM(&pm), TM(&TM) {
360  Impl = new PassConfigImpl();
361 
362  // Register all target independent codegen passes to activate their PassIDs,
363  // including this pass itself.
365 
366  // Also register alias analysis passes required by codegen passes.
369 
370  // Substitute Pseudo Pass IDs for real ones.
373 
374  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
375  TM.Options.PrintMachineCode = true;
376 
377  if (EnableIPRA.getNumOccurrences())
379  else {
380  // If not explicitly specified, use target default.
381  TM.Options.EnableIPRA = TM.useIPRA();
382  }
383 
384  if (TM.Options.EnableIPRA)
386 
387  setStartStopPasses();
388 }
389 
391  return TM->getOptLevel();
392 }
393 
394 /// Insert InsertedPassID pass after TargetPassID.
396  IdentifyingPassPtr InsertedPassID,
397  bool VerifyAfter, bool PrintAfter) {
398  assert(((!InsertedPassID.isInstance() &&
399  TargetPassID != InsertedPassID.getID()) ||
400  (InsertedPassID.isInstance() &&
401  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
402  "Insert a pass after itself!");
403  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
404  PrintAfter);
405 }
406 
407 /// createPassConfig - Create a pass configuration object to be used by
408 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
409 ///
410 /// Targets may override this to extend TargetPassConfig.
412  return new TargetPassConfig(*this, PM);
413 }
414 
416  : ImmutablePass(ID) {
417  report_fatal_error("Trying to construct TargetPassConfig without a target "
418  "machine. Scheduling a CodeGen pass without a target "
419  "triple set?");
420 }
421 
423  return StartBefore || StartAfter || StopBefore || StopAfter;
424 }
425 
426 std::string
429  return std::string();
430  std::string Res;
431  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
433  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
434  StopAfterOptName, StopBeforeOptName};
435  bool IsFirst = true;
436  for (int Idx = 0; Idx < 4; ++Idx)
437  if (!PassNames[Idx]->empty()) {
438  if (!IsFirst)
439  Res += Separator;
440  IsFirst = false;
441  Res += OptNames[Idx];
442  }
443  return Res;
444 }
445 
446 // Helper to verify the analysis is really immutable.
447 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
448  assert(!Initialized && "PassConfig is immutable");
449  Opt = Val;
450 }
451 
453  IdentifyingPassPtr TargetID) {
454  Impl->TargetPasses[StandardID] = TargetID;
455 }
456 
459  I = Impl->TargetPasses.find(ID);
460  if (I == Impl->TargetPasses.end())
461  return ID;
462  return I->second;
463 }
464 
467  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
468  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
469  FinalPtr.getID() != ID;
470 }
471 
472 /// Add a pass to the PassManager if that pass is supposed to be run. If the
473 /// Started/Stopped flags indicate either that the compilation should start at
474 /// a later pass or that it should stop after an earlier pass, then do not add
475 /// the pass. Finally, compare the current pass against the StartAfter
476 /// and StopAfter options and change the Started/Stopped flags accordingly.
477 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
478  assert(!Initialized && "PassConfig is immutable");
479 
480  // Cache the Pass ID here in case the pass manager finds this pass is
481  // redundant with ones already scheduled / available, and deletes it.
482  // Fundamentally, once we add the pass to the manager, we no longer own it
483  // and shouldn't reference it.
484  AnalysisID PassID = P->getPassID();
485 
486  if (StartBefore == PassID)
487  Started = true;
488  if (StopBefore == PassID)
489  Stopped = true;
490  if (Started && !Stopped) {
491  std::string Banner;
492  // Construct banner message before PM->add() as that may delete the pass.
493  if (AddingMachinePasses && (printAfter || verifyAfter))
494  Banner = std::string("After ") + std::string(P->getPassName());
495  PM->add(P);
496  if (AddingMachinePasses) {
497  if (printAfter)
498  addPrintPass(Banner);
499  if (verifyAfter)
500  addVerifyPass(Banner);
501  }
502 
503  // Add the passes after the pass P if there is any.
504  for (auto IP : Impl->InsertedPasses) {
505  if (IP.TargetPassID == PassID)
506  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
507  }
508  } else {
509  delete P;
510  }
511  if (StopAfter == PassID)
512  Stopped = true;
513  if (StartAfter == PassID)
514  Started = true;
515  if (Stopped && !Started)
516  report_fatal_error("Cannot stop compilation after pass that is not run");
517 }
518 
519 /// Add a CodeGen pass at this point in the pipeline after checking for target
520 /// and command line overrides.
521 ///
522 /// addPass cannot return a pointer to the pass instance because is internal the
523 /// PassManager and the instance we create here may already be freed.
525  bool printAfter) {
526  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
527  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
528  if (!FinalPtr.isValid())
529  return nullptr;
530 
531  Pass *P;
532  if (FinalPtr.isInstance())
533  P = FinalPtr.getInstance();
534  else {
535  P = Pass::createPass(FinalPtr.getID());
536  if (!P)
537  llvm_unreachable("Pass ID not registered");
538  }
539  AnalysisID FinalID = P->getPassID();
540  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
541 
542  return FinalID;
543 }
544 
545 void TargetPassConfig::printAndVerify(const std::string &Banner) {
546  addPrintPass(Banner);
547  addVerifyPass(Banner);
548 }
549 
550 void TargetPassConfig::addPrintPass(const std::string &Banner) {
551  if (TM->shouldPrintMachineCode())
552  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
553 }
554 
555 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
556  bool Verify = VerifyMachineCode;
557 #ifdef EXPENSIVE_CHECKS
559  Verify = TM->isMachineVerifierClean();
560 #endif
561  if (Verify)
562  PM->add(createMachineVerifierPass(Banner));
563 }
564 
565 /// Add common target configurable passes that perform LLVM IR to IR transforms
566 /// following machine independent optimization.
568  switch (UseCFLAA) {
571  break;
572  case CFLAAType::Andersen:
574  break;
575  case CFLAAType::Both:
578  break;
579  default:
580  break;
581  }
582 
583  // Basic AliasAnalysis support.
584  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
585  // BasicAliasAnalysis wins if they disagree. This is intended to help
586  // support "obvious" type-punning idioms.
590 
591  // Before running any passes, run the verifier to determine if the input
592  // coming from the front-end and/or optimizer is valid.
593  if (!DisableVerify)
595 
596  // Run loop strength reduction before anything else.
597  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
599  if (PrintLSR)
600  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
601  }
602 
603  if (getOptLevel() != CodeGenOpt::None) {
604  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
605  // loads and compares. ExpandMemCmpPass then tries to expand those calls
606  // into optimally-sized loads and compares. The transforms are enabled by a
607  // target lowering hook.
608  if (EnableMergeICmps)
611  }
612 
613  // Run GC lowering passes for builtin collectors
614  // TODO: add a pass insertion point here
617 
618  // Make sure that no unreachable blocks are instruction selected.
620 
621  // Prepare expensive constants for SelectionDAG.
624 
627 
628  // Instrument function entry and exit, e.g. with calls to mcount().
630 
631  // Add scalarization of target's unsupported masked memory intrinsics pass.
632  // the unsupported intrinsic will be replaced with a chain of basic blocks,
633  // that stores/loads element one-by-one if the appropriate mask bit is set.
635 
636  // Expand reduction intrinsics into shuffle sequences if the target wants to.
638 }
639 
640 /// Turn exception handling constructs into something the code generators can
641 /// handle.
643  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
644  assert(MCAI && "No MCAsmInfo");
645  switch (MCAI->getExceptionHandlingType()) {
647  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
648  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
649  // catch info can get misplaced when a selector ends up more than one block
650  // removed from the parent invoke(s). This could happen when a landing
651  // pad is shared by multiple invokes and is also a target of a normal
652  // edge from elsewhere.
658  break;
660  // We support using both GCC-style and MSVC-style exceptions on Windows, so
661  // add both preparation passes. Each pass will only actually run if it
662  // recognizes the personality function.
665  break;
668 
669  // The lower invoke pass may create unreachable code. Remove it.
671  break;
672  }
673 }
674 
675 /// Add pass to prepare the LLVM IR for code generation. This should be done
676 /// before exception handling preparation passes.
681 }
682 
683 /// Add common passes that perform LLVM IR to IR transforms in preparation for
684 /// instruction selection.
686  addPreISel();
687 
688  // Force codegen to run according to the callgraph.
690  addPass(new DummyCGSCCPass);
691 
692  // Add both the safe stack and the stack protection passes: each of them will
693  // only protect functions that have corresponding attributes.
696 
697  if (PrintISelInput)
699  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
700 
701  // All passes which modify the LLVM IR are now complete; run the verifier
702  // to ensure that the IR is valid.
703  if (!DisableVerify)
705 }
706 
708  // Enable FastISel with -fast, but allow that to be overridden.
712  TM->setFastISel(true);
713 
714  // Ask the target for an isel.
715  // Enable GlobalISel if the target wants to, but allow that to be overriden.
718  if (addIRTranslator())
719  return true;
720 
722 
723  if (addLegalizeMachineIR())
724  return true;
725 
726  // Before running the register bank selector, ask the target if it
727  // wants to run some passes.
729 
730  if (addRegBankSelect())
731  return true;
732 
734 
736  return true;
737 
738  // Pass to reset the MachineFunction if the ISel failed.
741 
742  // Provide a fallback path when we do not want to abort on
743  // not-yet-supported input.
745  return true;
746 
747  } else if (addInstSelector())
748  return true;
749 
750  return false;
751 }
752 
754  if (TM->Options.EmulatedTLS)
756 
759  addIRPasses();
762  addISelPrepare();
763 
764  return addCoreISelPasses();
765 }
766 
767 /// -regalloc=... command line option.
768 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
771 RegAlloc("regalloc",
773  cl::desc("Register allocator to use"));
774 
775 /// Add the complete set of target-independent postISel code generator passes.
776 ///
777 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
778 /// with nontrivial configuration or multiple passes are broken out below in
779 /// add%Stage routines.
780 ///
781 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
782 /// addPre/Post methods with empty header implementations allow injecting
783 /// target-specific fixups just before or after major stages. Additionally,
784 /// targets have the flexibility to change pass order within a stage by
785 /// overriding default implementation of add%Stage routines below. Each
786 /// technique has maintainability tradeoffs because alternate pass orders are
787 /// not well supported. addPre/Post works better if the target pass is easily
788 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
789 /// the target should override the stage instead.
790 ///
791 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
792 /// before/after any target-independent pass. But it's currently overkill.
794  AddingMachinePasses = true;
795 
796  // Insert a machine instr printer pass after the specified pass.
797  if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
798  !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
800  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
801  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
802  assert (TPI && IPI && "Pass ID not registered!");
803  const char *TID = (const char *)(TPI->getTypeInfo());
804  const char *IID = (const char *)(IPI->getTypeInfo());
805  insertPass(TID, IID);
806  }
807 
808  // Print the instruction selected machine code...
809  printAndVerify("After Instruction Selection");
810 
811  // Expand pseudo-instructions emitted by ISel.
813 
814  // Add passes that optimize machine instructions in SSA form.
815  if (getOptLevel() != CodeGenOpt::None) {
817  } else {
818  // If the target requests it, assign local variables to stack slots relative
819  // to one another and simplify frame index references where possible.
821  }
822 
823  if (TM->Options.EnableIPRA)
825 
826  // Run pre-ra passes.
827  addPreRegAlloc();
828 
829  // Run register allocation and passes that are tightly coupled with it,
830  // including phi elimination and scheduling.
831  if (getOptimizeRegAlloc())
833  else {
834  if (RegAlloc != &useDefaultRegisterAllocator &&
835  RegAlloc != &createFastRegisterAllocator)
836  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
838  }
839 
840  // Run post-ra passes.
841  addPostRegAlloc();
842 
843  // Insert prolog/epilog code. Eliminate abstract frame index references...
844  if (getOptLevel() != CodeGenOpt::None)
846 
847  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
848  // do so if it hasn't been disabled, substituted, or overridden.
851 
852  /// Add passes that optimize machine instructions after register allocation.
853  if (getOptLevel() != CodeGenOpt::None)
855 
856  // Expand pseudo instructions before second scheduling pass.
858 
859  // Run pre-sched2 passes.
860  addPreSched2();
861 
864 
865  // Second pass scheduler.
866  // Let Target optionally insert this pass by itself at some other
867  // point.
868  if (getOptLevel() != CodeGenOpt::None &&
870  if (MISchedPostRA)
872  else
874  }
875 
876  // GC
877  if (addGCPasses()) {
878  if (PrintGCInfo)
879  addPass(createGCInfoPrinter(dbgs()), false, false);
880  }
881 
882  // Basic block placement.
883  if (getOptLevel() != CodeGenOpt::None)
885 
886  addPreEmitPass();
887 
888  if (TM->Options.EnableIPRA)
889  // Collect register usage information and produce a register mask of
890  // clobbered registers, to be used to optimize call sites.
892 
893  addPass(&FuncletLayoutID, false);
894 
895  addPass(&StackMapLivenessID, false);
896  addPass(&LiveDebugValuesID, false);
897 
898  // Insert before XRay Instrumentation.
899  addPass(&FEntryInserterID, false);
900 
902  addPass(&PatchableFunctionID, false);
903 
906 
907  AddingMachinePasses = false;
908 }
909 
910 /// Add passes that optimize machine instructions in SSA form.
912  // Pre-ra tail duplication.
914 
915  // Optimize PHIs before DCE: removing dead PHI cycles may make more
916  // instructions dead.
917  addPass(&OptimizePHIsID, false);
918 
919  // This pass merges large allocas. StackSlotColoring is a different pass
920  // which merges spill slots.
921  addPass(&StackColoringID, false);
922 
923  // If the target requests it, assign local variables to stack slots relative
924  // to one another and simplify frame index references where possible.
926 
927  // With optimization, dead code should already be eliminated. However
928  // there is one known exception: lowered code for arguments that are only
929  // used by tail calls, where the tail calls reuse the incoming stack
930  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
932 
933  // Allow targets to insert passes that improve instruction level parallelism,
934  // like if-conversion. Such passes will typically need dominator trees and
935  // loop info, just like LICM and CSE below.
936  addILPOpts();
937 
938  addPass(&MachineLICMID, false);
939  addPass(&MachineCSEID, false);
940 
942 
944  // Clean-up the dead code that may have been generated by peephole
945  // rewriting.
947 }
948 
949 //===---------------------------------------------------------------------===//
950 /// Register Allocation Pass Configuration
951 //===---------------------------------------------------------------------===//
952 
954  switch (OptimizeRegAlloc) {
955  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
956  case cl::BOU_TRUE: return true;
957  case cl::BOU_FALSE: return false;
958  }
959  llvm_unreachable("Invalid optimize-regalloc state");
960 }
961 
962 /// RegisterRegAlloc's global Registry tracks allocator registration.
964 
965 /// A dummy default pass factory indicates whether the register allocator is
966 /// overridden on the command line.
968 
969 static RegisterRegAlloc
970 defaultRegAlloc("default",
971  "pick register allocator based on -O option",
973 
975  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
976 
977  if (!Ctor) {
978  Ctor = RegAlloc;
980  }
981 }
982 
983 /// Instantiate the default register allocator pass for this target for either
984 /// the optimized or unoptimized allocation path. This will be added to the pass
985 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
986 /// in the optimized case.
987 ///
988 /// A target that uses the standard regalloc pass order for fast or optimized
989 /// allocation may still override this for per-target regalloc
990 /// selection. But -regalloc=... always takes precedence.
992  if (Optimized)
994  else
996 }
997 
998 /// Find and instantiate the register allocation pass requested by this target
999 /// at the current optimization level. Different register allocators are
1000 /// defined as separate passes because they may require different analysis.
1001 ///
1002 /// This helper ensures that the regalloc= option is always available,
1003 /// even for targets that override the default allocator.
1004 ///
1005 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1006 /// this can be folded into addPass.
1008  // Initialize the global default.
1009  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1011 
1012  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1013  if (Ctor != useDefaultRegisterAllocator)
1014  return Ctor();
1015 
1016  // With no -regalloc= override, ask the target for a regalloc pass.
1017  return createTargetRegisterAllocator(Optimized);
1018 }
1019 
1020 /// Return true if the default global register allocator is in use and
1021 /// has not be overriden on the command line with '-regalloc=...'
1023  return RegAlloc.getNumOccurrences() == 0;
1024 }
1025 
1026 /// Add the minimum set of target-independent passes that are required for
1027 /// register allocation. No coalescing or scheduling.
1029  addPass(&PHIEliminationID, false);
1031 
1032  if (RegAllocPass)
1033  addPass(RegAllocPass);
1034 }
1035 
1036 /// Add standard target-independent passes that are tightly coupled with
1037 /// optimized register allocation, including coalescing, machine instruction
1038 /// scheduling, and register allocation itself.
1040  addPass(&DetectDeadLanesID, false);
1041 
1042  addPass(&ProcessImplicitDefsID, false);
1043 
1044  // LiveVariables currently requires pure SSA form.
1045  //
1046  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1047  // LiveVariables can be removed completely, and LiveIntervals can be directly
1048  // computed. (We still either need to regenerate kill flags after regalloc, or
1049  // preferably fix the scavenger to not depend on them).
1050  addPass(&LiveVariablesID, false);
1051 
1052  // Edge splitting is smarter with machine loop info.
1053  addPass(&MachineLoopInfoID, false);
1054  addPass(&PHIEliminationID, false);
1055 
1056  // Eventually, we want to run LiveIntervals before PHI elimination.
1057  if (EarlyLiveIntervals)
1058  addPass(&LiveIntervalsID, false);
1059 
1062 
1063  // The machine scheduler may accidentally create disconnected components
1064  // when moving subregister definitions around, avoid this by splitting them to
1065  // separate vregs before. Splitting can also improve reg. allocation quality.
1067 
1068  // PreRA instruction scheduling.
1070 
1071  if (RegAllocPass) {
1072  // Add the selected register allocation pass.
1073  addPass(RegAllocPass);
1074 
1075  // Allow targets to change the register assignments before rewriting.
1076  addPreRewrite();
1077 
1078  // Finally rewrite virtual registers.
1080 
1081  // Perform stack slot coloring and post-ra machine LICM.
1082  //
1083  // FIXME: Re-enable coloring with register when it's capable of adding
1084  // kill markers.
1086 
1087  // Run post-ra machine LICM to hoist reloads / remats.
1088  //
1089  // FIXME: can this move into MachineLateOptimization?
1091  }
1092 }
1093 
1094 //===---------------------------------------------------------------------===//
1095 /// Post RegAlloc Pass Configuration
1096 //===---------------------------------------------------------------------===//
1097 
1098 /// Add passes that optimize machine instructions after register allocation.
1100  // Branch folding must be run after regalloc and prolog/epilog insertion.
1102 
1103  // Tail duplication.
1104  // Note that duplicating tail just increases code size and degrades
1105  // performance for targets that require Structured Control Flow.
1106  // In addition it can also make CFG irreducible. Thus we disable it.
1107  if (!TM->requiresStructuredCFG())
1109 
1110  // Copy propagation.
1112 }
1113 
1114 /// Add standard GC passes.
1117  return true;
1118 }
1119 
1120 /// Add standard basic block placement passes.
1123  // Run a separate pass to collect block placement statistics.
1126  }
1127 }
1128 
1129 //===---------------------------------------------------------------------===//
1130 /// GlobalISel Configuration
1131 //===---------------------------------------------------------------------===//
1132 
1134  return false;
1135 }
1136 
1138  return EnableGlobalISelAbort == 1;
1139 }
1140 
1142  return EnableGlobalISelAbort == 2;
1143 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static cl::opt< bool > EnableMergeICmps("enable-mergeicmps", cl::desc("Merge ICmp chains into a single memcmp"), cl::init(false))
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & FEntryInserterID
This pass inserts FEntry calls.
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""))
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:4977
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
static void setDefault(FunctionPassCtor C)
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static MachinePassRegistry Registry
RegisterRegAlloc&#39;s global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:74
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
const char * StopBeforeOptName
bool hasLimitedCodeGenPipeline() const
Describe the status of the codegen pipeline set by this target pass config.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:84
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:849
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Pass * createMergeICmpsPass()
Definition: MergeICmps.cpp:652
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:134
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< bool > EnableMachineOutliner("enable-machine-outliner", cl::Hidden, cl::desc("Enable machine outliner"))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:72
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
const char * StartBeforeOptName
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:99
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:100
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:626
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
static cl::opt< bool > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore)
static cl::opt< cl::boolOrDefault > EnableGlobalISel("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
FunctionPass * createWinEHPass()
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:69
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""))
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:31
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
static cl::opt< int > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction: 0 disable the abort, " "1 enable the abort, and " "2 disable the abort but emit a diagnostic on failure"), cl::init(1))
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
FunctionPass *(*)() FunctionPassCtor
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
unsigned EmulatedTLS
EmulatedTLS - This flag enables emulated TLS model, using emutls function in the runtime library...
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:601
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static cl::opt< bool > EnableLinkOnceODROutlining("enable-linkonceodr-outlining", cl::Hidden, cl::desc("Enable the machine outliner on linkonceodr functions"), cl::init(false))
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual bool isGlobalISelEnabled() const
Check whether or not GlobalISel should be enabled by default.
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:656
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
TargetOptions Options
Definition: TargetMachine.h:96
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
#define I(x, y, z)
Definition: MD5.cpp:58
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
bool shouldPrintMachineCode() const
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static char EarlyTailDuplicateID
Pseudo Pass IDs.
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:216
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
const char * StopAfterOptName
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the .load.relative intrinsic to instructions.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:212
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:554
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
ModulePass * createMachineOutlinerPass(bool OutlineFromLinkOnceODRs=false)
This pass performs outlining on machine instructions directly before printing assembly.
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""))
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:232
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
This pass exposes codegen information to IR-level passes.
No exception support.
ImmutablePass * createCFLAndersAAWrapperPass()
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...