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MachineCopyPropagation.cpp
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1 //===- MachineCopyPropagation.cpp - Machine Copy Propagation Pass ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is an extremely simple MachineInstr-level copy propagation pass.
11 //
12 // This pass forwards the source of COPYs to the users of their destinations
13 // when doing so is legal. For example:
14 //
15 // %reg1 = COPY %reg0
16 // ...
17 // ... = OP %reg1
18 //
19 // If
20 // - %reg0 has not been clobbered by the time of the use of %reg1
21 // - the register class constraints are satisfied
22 // - the COPY def is the only value that reaches OP
23 // then this pass replaces the above with:
24 //
25 // %reg1 = COPY %reg0
26 // ...
27 // ... = OP %reg0
28 //
29 // This pass also removes some redundant COPYs. For example:
30 //
31 // %R1 = COPY %R0
32 // ... // No clobber of %R1
33 // %R0 = COPY %R1 <<< Removed
34 //
35 // or
36 //
37 // %R1 = COPY %R0
38 // ... // No clobber of %R0
39 // %R1 = COPY %R0 <<< Removed
40 //
41 //===----------------------------------------------------------------------===//
42 
43 #include "llvm/ADT/DenseMap.h"
44 #include "llvm/ADT/STLExtras.h"
45 #include "llvm/ADT/SetVector.h"
46 #include "llvm/ADT/SmallVector.h"
47 #include "llvm/ADT/Statistic.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/Pass.h"
60 #include "llvm/Support/Debug.h"
63 #include <cassert>
64 #include <iterator>
65 
66 using namespace llvm;
67 
68 #define DEBUG_TYPE "machine-cp"
69 
70 STATISTIC(NumDeletes, "Number of dead copies deleted");
71 STATISTIC(NumCopyForwards, "Number of copy uses forwarded");
72 DEBUG_COUNTER(FwdCounter, "machine-cp-fwd",
73  "Controls which register COPYs are forwarded");
74 
75 namespace {
76 
77 class CopyTracker {
78  struct CopyInfo {
81  bool Avail;
82  };
83 
85 
86 public:
87  /// Mark all of the given registers and their subregisters as unavailable for
88  /// copying.
89  void markRegsUnavailable(ArrayRef<unsigned> Regs,
90  const TargetRegisterInfo &TRI) {
91  for (unsigned Reg : Regs) {
92  // Source of copy is no longer available for propagation.
93  for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
94  auto CI = Copies.find(*RUI);
95  if (CI != Copies.end())
96  CI->second.Avail = false;
97  }
98  }
99  }
100 
101  /// Clobber a single register, removing it from the tracker's copy maps.
102  void clobberRegister(unsigned Reg, const TargetRegisterInfo &TRI) {
103  for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
104  auto I = Copies.find(*RUI);
105  if (I != Copies.end()) {
106  // When we clobber the source of a copy, we need to clobber everything
107  // it defined.
108  markRegsUnavailable(I->second.DefRegs, TRI);
109  // When we clobber the destination of a copy, we need to clobber the
110  // whole register it defined.
111  if (MachineInstr *MI = I->second.MI)
112  markRegsUnavailable({MI->getOperand(0).getReg()}, TRI);
113  // Now we can erase the copy.
114  Copies.erase(I);
115  }
116  }
117  }
118 
119  /// Add this copy's registers into the tracker's copy maps.
120  void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) {
121  assert(MI->isCopy() && "Tracking non-copy?");
122 
123  unsigned Def = MI->getOperand(0).getReg();
124  unsigned Src = MI->getOperand(1).getReg();
125 
126  // Remember Def is defined by the copy.
127  for (MCRegUnitIterator RUI(Def, &TRI); RUI.isValid(); ++RUI)
128  Copies[*RUI] = {MI, {}, true};
129 
130  // Remember source that's copied to Def. Once it's clobbered, then
131  // it's no longer available for copy propagation.
132  for (MCRegUnitIterator RUI(Src, &TRI); RUI.isValid(); ++RUI) {
133  auto I = Copies.insert({*RUI, {nullptr, {}, false}});
134  auto &Copy = I.first->second;
135  if (!is_contained(Copy.DefRegs, Def))
136  Copy.DefRegs.push_back(Def);
137  }
138  }
139 
140  bool hasAnyCopies() {
141  return !Copies.empty();
142  }
143 
144  MachineInstr *findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI,
145  bool MustBeAvailable = false) {
146  auto CI = Copies.find(RegUnit);
147  if (CI == Copies.end())
148  return nullptr;
149  if (MustBeAvailable && !CI->second.Avail)
150  return nullptr;
151  return CI->second.MI;
152  }
153 
154  MachineInstr *findAvailCopy(MachineInstr &DestCopy, unsigned Reg,
155  const TargetRegisterInfo &TRI) {
156  // We check the first RegUnit here, since we'll only be interested in the
157  // copy if it copies the entire register anyway.
158  MCRegUnitIterator RUI(Reg, &TRI);
159  MachineInstr *AvailCopy =
160  findCopyForUnit(*RUI, TRI, /*MustBeAvailable=*/true);
161  if (!AvailCopy ||
162  !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg))
163  return nullptr;
164 
165  // Check that the available copy isn't clobbered by any regmasks between
166  // itself and the destination.
167  unsigned AvailSrc = AvailCopy->getOperand(1).getReg();
168  unsigned AvailDef = AvailCopy->getOperand(0).getReg();
169  for (const MachineInstr &MI :
170  make_range(AvailCopy->getIterator(), DestCopy.getIterator()))
171  for (const MachineOperand &MO : MI.operands())
172  if (MO.isRegMask())
173  if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef))
174  return nullptr;
175 
176  return AvailCopy;
177  }
178 
179  void clear() {
180  Copies.clear();
181  }
182 };
183 
184 class MachineCopyPropagation : public MachineFunctionPass {
185  const TargetRegisterInfo *TRI;
186  const TargetInstrInfo *TII;
187  const MachineRegisterInfo *MRI;
188 
189 public:
190  static char ID; // Pass identification, replacement for typeid
191 
192  MachineCopyPropagation() : MachineFunctionPass(ID) {
194  }
195 
196  void getAnalysisUsage(AnalysisUsage &AU) const override {
197  AU.setPreservesCFG();
199  }
200 
201  bool runOnMachineFunction(MachineFunction &MF) override;
202 
203  MachineFunctionProperties getRequiredProperties() const override {
206  }
207 
208 private:
209  void ClobberRegister(unsigned Reg);
210  void ReadRegister(unsigned Reg);
211  void CopyPropagateBlock(MachineBasicBlock &MBB);
212  bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
213  void forwardUses(MachineInstr &MI);
214  bool isForwardableRegClassCopy(const MachineInstr &Copy,
215  const MachineInstr &UseI, unsigned UseIdx);
216  bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
217 
218  /// Candidates for deletion.
219  SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
220 
221  CopyTracker Tracker;
222 
223  bool Changed;
224 };
225 
226 } // end anonymous namespace
227 
229 
231 
232 INITIALIZE_PASS(MachineCopyPropagation, DEBUG_TYPE,
233  "Machine Copy Propagation Pass", false, false)
234 
235 void MachineCopyPropagation::ReadRegister(unsigned Reg) {
236  // If 'Reg' is defined by a copy, the copy is no longer a candidate
237  // for elimination.
238  for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
239  if (MachineInstr *Copy = Tracker.findCopyForUnit(*RUI, *TRI)) {
240  LLVM_DEBUG(dbgs() << "MCP: Copy is used - not dead: "; Copy->dump());
241  MaybeDeadCopies.remove(Copy);
242  }
243  }
244 }
245 
246 /// Return true if \p PreviousCopy did copy register \p Src to register \p Def.
247 /// This fact may have been obscured by sub register usage or may not be true at
248 /// all even though Src and Def are subregisters of the registers used in
249 /// PreviousCopy. e.g.
250 /// isNopCopy("ecx = COPY eax", AX, CX) == true
251 /// isNopCopy("ecx = COPY eax", AH, CL) == false
252 static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src,
253  unsigned Def, const TargetRegisterInfo *TRI) {
254  unsigned PreviousSrc = PreviousCopy.getOperand(1).getReg();
255  unsigned PreviousDef = PreviousCopy.getOperand(0).getReg();
256  if (Src == PreviousSrc) {
257  assert(Def == PreviousDef);
258  return true;
259  }
260  if (!TRI->isSubRegister(PreviousSrc, Src))
261  return false;
262  unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src);
263  return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
264 }
265 
266 /// Remove instruction \p Copy if there exists a previous copy that copies the
267 /// register \p Src to the register \p Def; This may happen indirectly by
268 /// copying the super registers.
269 bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy, unsigned Src,
270  unsigned Def) {
271  // Avoid eliminating a copy from/to a reserved registers as we cannot predict
272  // the value (Example: The sparc zero register is writable but stays zero).
273  if (MRI->isReserved(Src) || MRI->isReserved(Def))
274  return false;
275 
276  // Search for an existing copy.
277  MachineInstr *PrevCopy = Tracker.findAvailCopy(Copy, Def, *TRI);
278  if (!PrevCopy)
279  return false;
280 
281  // Check that the existing copy uses the correct sub registers.
282  if (PrevCopy->getOperand(0).isDead())
283  return false;
284  if (!isNopCopy(*PrevCopy, Src, Def, TRI))
285  return false;
286 
287  LLVM_DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump());
288 
289  // Copy was redundantly redefining either Src or Def. Remove earlier kill
290  // flags between Copy and PrevCopy because the value will be reused now.
291  assert(Copy.isCopy());
292  unsigned CopyDef = Copy.getOperand(0).getReg();
293  assert(CopyDef == Src || CopyDef == Def);
294  for (MachineInstr &MI :
295  make_range(PrevCopy->getIterator(), Copy.getIterator()))
296  MI.clearRegisterKills(CopyDef, TRI);
297 
298  Copy.eraseFromParent();
299  Changed = true;
300  ++NumDeletes;
301  return true;
302 }
303 
304 /// Decide whether we should forward the source of \param Copy to its use in
305 /// \param UseI based on the physical register class constraints of the opcode
306 /// and avoiding introducing more cross-class COPYs.
307 bool MachineCopyPropagation::isForwardableRegClassCopy(const MachineInstr &Copy,
308  const MachineInstr &UseI,
309  unsigned UseIdx) {
310 
311  unsigned CopySrcReg = Copy.getOperand(1).getReg();
312 
313  // If the new register meets the opcode register constraints, then allow
314  // forwarding.
315  if (const TargetRegisterClass *URC =
316  UseI.getRegClassConstraint(UseIdx, TII, TRI))
317  return URC->contains(CopySrcReg);
318 
319  if (!UseI.isCopy())
320  return false;
321 
322  /// COPYs don't have register class constraints, so if the user instruction
323  /// is a COPY, we just try to avoid introducing additional cross-class
324  /// COPYs. For example:
325  ///
326  /// RegClassA = COPY RegClassB // Copy parameter
327  /// ...
328  /// RegClassB = COPY RegClassA // UseI parameter
329  ///
330  /// which after forwarding becomes
331  ///
332  /// RegClassA = COPY RegClassB
333  /// ...
334  /// RegClassB = COPY RegClassB
335  ///
336  /// so we have reduced the number of cross-class COPYs and potentially
337  /// introduced a nop COPY that can be removed.
338  const TargetRegisterClass *UseDstRC =
339  TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());
340 
341  const TargetRegisterClass *SuperRC = UseDstRC;
342  for (TargetRegisterClass::sc_iterator SuperRCI = UseDstRC->getSuperClasses();
343  SuperRC; SuperRC = *SuperRCI++)
344  if (SuperRC->contains(CopySrcReg))
345  return true;
346 
347  return false;
348 }
349 
350 /// Check that \p MI does not have implicit uses that overlap with it's \p Use
351 /// operand (the register being replaced), since these can sometimes be
352 /// implicitly tied to other operands. For example, on AMDGPU:
353 ///
354 /// V_MOVRELS_B32_e32 %VGPR2, %M0<imp-use>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use>
355 ///
356 /// the %VGPR2 is implicitly tied to the larger reg operand, but we have no
357 /// way of knowing we need to update the latter when updating the former.
358 bool MachineCopyPropagation::hasImplicitOverlap(const MachineInstr &MI,
359  const MachineOperand &Use) {
360  for (const MachineOperand &MIUse : MI.uses())
361  if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&
362  MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
363  return true;
364 
365  return false;
366 }
367 
368 /// Look for available copies whose destination register is used by \p MI and
369 /// replace the use in \p MI with the copy's source register.
370 void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
371  if (!Tracker.hasAnyCopies())
372  return;
373 
374  // Look for non-tied explicit vreg uses that have an active COPY
375  // instruction that defines the physical register allocated to them.
376  // Replace the vreg with the source of the active COPY.
377  for (unsigned OpIdx = 0, OpEnd = MI.getNumOperands(); OpIdx < OpEnd;
378  ++OpIdx) {
379  MachineOperand &MOUse = MI.getOperand(OpIdx);
380  // Don't forward into undef use operands since doing so can cause problems
381  // with the machine verifier, since it doesn't treat undef reads as reads,
382  // so we can end up with a live range that ends on an undef read, leading to
383  // an error that the live range doesn't end on a read of the live range
384  // register.
385  if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
386  MOUse.isImplicit())
387  continue;
388 
389  if (!MOUse.getReg())
390  continue;
391 
392  // Check that the register is marked 'renamable' so we know it is safe to
393  // rename it without violating any constraints that aren't expressed in the
394  // IR (e.g. ABI or opcode requirements).
395  if (!MOUse.isRenamable())
396  continue;
397 
398  MachineInstr *Copy = Tracker.findAvailCopy(MI, MOUse.getReg(), *TRI);
399  if (!Copy)
400  continue;
401 
402  unsigned CopyDstReg = Copy->getOperand(0).getReg();
403  const MachineOperand &CopySrc = Copy->getOperand(1);
404  unsigned CopySrcReg = CopySrc.getReg();
405 
406  // FIXME: Don't handle partial uses of wider COPYs yet.
407  if (MOUse.getReg() != CopyDstReg) {
408  LLVM_DEBUG(
409  dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n "
410  << MI);
411  continue;
412  }
413 
414  // Don't forward COPYs of reserved regs unless they are constant.
415  if (MRI->isReserved(CopySrcReg) && !MRI->isConstantPhysReg(CopySrcReg))
416  continue;
417 
418  if (!isForwardableRegClassCopy(*Copy, MI, OpIdx))
419  continue;
420 
421  if (hasImplicitOverlap(MI, MOUse))
422  continue;
423 
424  if (!DebugCounter::shouldExecute(FwdCounter)) {
425  LLVM_DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n "
426  << MI);
427  continue;
428  }
429 
430  LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
431  << "\n with " << printReg(CopySrcReg, TRI)
432  << "\n in " << MI << " from " << *Copy);
433 
434  MOUse.setReg(CopySrcReg);
435  if (!CopySrc.isRenamable())
436  MOUse.setIsRenamable(false);
437 
438  LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
439 
440  // Clear kill markers that may have been invalidated.
441  for (MachineInstr &KMI :
442  make_range(Copy->getIterator(), std::next(MI.getIterator())))
443  KMI.clearRegisterKills(CopySrcReg, TRI);
444 
445  ++NumCopyForwards;
446  Changed = true;
447  }
448 }
449 
450 void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
451  LLVM_DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");
452 
453  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ) {
454  MachineInstr *MI = &*I;
455  ++I;
456 
457  // Analyze copies (which don't overlap themselves).
458  if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(),
459  MI->getOperand(1).getReg())) {
460  unsigned Def = MI->getOperand(0).getReg();
461  unsigned Src = MI->getOperand(1).getReg();
462 
465  "MachineCopyPropagation should be run after register allocation!");
466 
467  // The two copies cancel out and the source of the first copy
468  // hasn't been overridden, eliminate the second one. e.g.
469  // %ecx = COPY %eax
470  // ... nothing clobbered eax.
471  // %eax = COPY %ecx
472  // =>
473  // %ecx = COPY %eax
474  //
475  // or
476  //
477  // %ecx = COPY %eax
478  // ... nothing clobbered eax.
479  // %ecx = COPY %eax
480  // =>
481  // %ecx = COPY %eax
482  if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def))
483  continue;
484 
485  forwardUses(*MI);
486 
487  // Src may have been changed by forwardUses()
488  Src = MI->getOperand(1).getReg();
489 
490  // If Src is defined by a previous copy, the previous copy cannot be
491  // eliminated.
492  ReadRegister(Src);
493  for (const MachineOperand &MO : MI->implicit_operands()) {
494  if (!MO.isReg() || !MO.readsReg())
495  continue;
496  unsigned Reg = MO.getReg();
497  if (!Reg)
498  continue;
499  ReadRegister(Reg);
500  }
501 
502  LLVM_DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump());
503 
504  // Copy is now a candidate for deletion.
505  if (!MRI->isReserved(Def))
506  MaybeDeadCopies.insert(MI);
507 
508  // If 'Def' is previously source of another copy, then this earlier copy's
509  // source is no longer available. e.g.
510  // %xmm9 = copy %xmm2
511  // ...
512  // %xmm2 = copy %xmm0
513  // ...
514  // %xmm2 = copy %xmm9
515  Tracker.clobberRegister(Def, *TRI);
516  for (const MachineOperand &MO : MI->implicit_operands()) {
517  if (!MO.isReg() || !MO.isDef())
518  continue;
519  unsigned Reg = MO.getReg();
520  if (!Reg)
521  continue;
522  Tracker.clobberRegister(Reg, *TRI);
523  }
524 
525  Tracker.trackCopy(MI, *TRI);
526 
527  continue;
528  }
529 
530  // Clobber any earlyclobber regs first.
531  for (const MachineOperand &MO : MI->operands())
532  if (MO.isReg() && MO.isEarlyClobber()) {
533  unsigned Reg = MO.getReg();
534  // If we have a tied earlyclobber, that means it is also read by this
535  // instruction, so we need to make sure we don't remove it as dead
536  // later.
537  if (MO.isTied())
538  ReadRegister(Reg);
539  Tracker.clobberRegister(Reg, *TRI);
540  }
541 
542  forwardUses(*MI);
543 
544  // Not a copy.
546  const MachineOperand *RegMask = nullptr;
547  for (const MachineOperand &MO : MI->operands()) {
548  if (MO.isRegMask())
549  RegMask = &MO;
550  if (!MO.isReg())
551  continue;
552  unsigned Reg = MO.getReg();
553  if (!Reg)
554  continue;
555 
557  "MachineCopyPropagation should be run after register allocation!");
558 
559  if (MO.isDef() && !MO.isEarlyClobber()) {
560  Defs.push_back(Reg);
561  continue;
562  } else if (!MO.isDebug() && MO.readsReg())
563  ReadRegister(Reg);
564  }
565 
566  // The instruction has a register mask operand which means that it clobbers
567  // a large set of registers. Treat clobbered registers the same way as
568  // defined registers.
569  if (RegMask) {
570  // Erase any MaybeDeadCopies whose destination register is clobbered.
572  MaybeDeadCopies.begin();
573  DI != MaybeDeadCopies.end();) {
574  MachineInstr *MaybeDead = *DI;
575  unsigned Reg = MaybeDead->getOperand(0).getReg();
576  assert(!MRI->isReserved(Reg));
577 
578  if (!RegMask->clobbersPhysReg(Reg)) {
579  ++DI;
580  continue;
581  }
582 
583  LLVM_DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
584  MaybeDead->dump());
585 
586  // Make sure we invalidate any entries in the copy maps before erasing
587  // the instruction.
588  Tracker.clobberRegister(Reg, *TRI);
589 
590  // erase() will return the next valid iterator pointing to the next
591  // element after the erased one.
592  DI = MaybeDeadCopies.erase(DI);
593  MaybeDead->eraseFromParent();
594  Changed = true;
595  ++NumDeletes;
596  }
597  }
598 
599  // Any previous copy definition or reading the Defs is no longer available.
600  for (unsigned Reg : Defs)
601  Tracker.clobberRegister(Reg, *TRI);
602  }
603 
604  // If MBB doesn't have successors, delete the copies whose defs are not used.
605  // If MBB does have successors, then conservative assume the defs are live-out
606  // since we don't want to trust live-in lists.
607  if (MBB.succ_empty()) {
608  for (MachineInstr *MaybeDead : MaybeDeadCopies) {
609  LLVM_DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";
610  MaybeDead->dump());
611  assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
612 
613  // Update matching debug values.
614  assert(MaybeDead->isCopy());
615  MaybeDead->changeDebugValuesDefReg(MaybeDead->getOperand(1).getReg());
616 
617  MaybeDead->eraseFromParent();
618  Changed = true;
619  ++NumDeletes;
620  }
621  }
622 
623  MaybeDeadCopies.clear();
624  Tracker.clear();
625 }
626 
627 bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) {
628  if (skipFunction(MF.getFunction()))
629  return false;
630 
631  Changed = false;
632 
633  TRI = MF.getSubtarget().getRegisterInfo();
634  TII = MF.getSubtarget().getInstrInfo();
635  MRI = &MF.getRegInfo();
636 
637  for (MachineBasicBlock &MBB : MF)
638  CopyPropagateBlock(MBB);
639 
640  return Changed;
641 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:492
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:218
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:459
void setIsRenamable(bool Val=true)
INITIALIZE_PASS(MachineCopyPropagation, DEBUG_TYPE, "Machine Copy Propagation Pass", false, false) void MachineCopyPropagation
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:221
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
This file provides an implementation of debug counters.
const TargetRegisterClass *const * sc_iterator
DEBUG_COUNTER(FwdCounter, "machine-cp-fwd", "Controls which register COPYs are forwarded")
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:83
virtual const TargetInstrInfo * getInstrInfo() const
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
TargetInstrInfo - Interface to description of machine instruction set.
#define DEBUG_TYPE
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
unsigned const MachineRegisterInfo * MRI
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
self_iterator getIterator()
Definition: ilist_node.h:82
static bool shouldExecute(unsigned CounterName)
Definition: DebugCounter.h:74
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void initializeMachineCopyPropagationPass(PassRegistry &)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:298
bool isSubRegisterEq(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
MachineOperand class - Representation of each machine instruction operand.
SI Lower i1 Copies
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:286
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:473
static void clear(coro::Shape &Shape)
Definition: Coroutines.cpp:212
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src, unsigned Def, const TargetRegisterInfo *TRI)
Return true if PreviousCopy did copy register Src to register Def.
IRTranslator LLVM IR MI
#define LLVM_DEBUG(X)
Definition: Debug.h:123
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Properties which a MachineFunction may have at a given point in time.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool isImplicit() const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1239