LLVM  8.0.0svn
TargetPassConfig.h
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1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// Target-Independent Code Generator Pass Configuration Options pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
16 
17 #include "llvm/Pass.h"
18 #include "llvm/Support/CodeGen.h"
19 #include <cassert>
20 #include <string>
21 
22 namespace llvm {
23 
24 class LLVMTargetMachine;
25 struct MachineSchedContext;
26 class PassConfigImpl;
27 class ScheduleDAGInstrs;
28 
29 // The old pass manager infrastructure is hidden in a legacy namespace now.
30 namespace legacy {
31 
32 class PassManagerBase;
33 
34 } // end namespace legacy
35 
37 
38 /// Discriminated union of Pass ID types.
39 ///
40 /// The PassConfig API prefers dealing with IDs because they are safer and more
41 /// efficient. IDs decouple configuration from instantiation. This way, when a
42 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
43 /// refer to a Pass pointer after adding it to a pass manager, which deletes
44 /// redundant pass instances.
45 ///
46 /// However, it is convient to directly instantiate target passes with
47 /// non-default ctors. These often don't have a registered PassInfo. Rather than
48 /// force all target passes to implement the pass registry boilerplate, allow
49 /// the PassConfig API to handle either type.
50 ///
51 /// AnalysisID is sadly char*, so PointerIntPair won't work.
53  union {
55  Pass *P;
56  };
57  bool IsInstance = false;
58 
59 public:
60  IdentifyingPassPtr() : P(nullptr) {}
61  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
62  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
63 
64  bool isValid() const { return P; }
65  bool isInstance() const { return IsInstance; }
66 
67  AnalysisID getID() const {
68  assert(!IsInstance && "Not a Pass ID");
69  return ID;
70  }
71 
72  Pass *getInstance() const {
73  assert(IsInstance && "Not a Pass Instance");
74  return P;
75  }
76 };
77 
78 template <> struct isPodLike<IdentifyingPassPtr> {
79  static const bool value = true;
80 };
81 
82 /// Target-Independent Code Generator Pass Configuration Options.
83 ///
84 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
85 /// to the internals of other CodeGen passes.
87 private:
88  PassManagerBase *PM = nullptr;
89  AnalysisID StartBefore = nullptr;
90  AnalysisID StartAfter = nullptr;
91  AnalysisID StopBefore = nullptr;
92  AnalysisID StopAfter = nullptr;
93  bool Started = true;
94  bool Stopped = false;
95  bool AddingMachinePasses = false;
96 
97  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
98  /// a portion of the normal code-gen pass sequence.
99  ///
100  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
101  /// begin at the normal point; otherwise, clear the Started flag to indicate
102  /// that passes should not be added until the starting pass is seen. If the
103  /// Stop pass ID is zero, then compilation will continue to the end.
104  ///
105  /// This function expects that at least one of the StartAfter or the
106  /// StartBefore pass IDs is null.
107  void setStartStopPasses();
108 
109 protected:
111  PassConfigImpl *Impl = nullptr; // Internal data structures
112  bool Initialized = false; // Flagged after all passes are configured.
113 
114  // Target Pass Options
115  // Targets provide a default setting, user flags override.
116  bool DisableVerify = false;
117 
118  /// Default setting for -enable-tail-merge on this target.
119  bool EnableTailMerge = true;
120 
121  /// Require processing of functions such that callees are generated before
122  /// callers.
123  bool RequireCodeGenSCCOrder = false;
124 
125  /// Add the actual instruction selection passes. This does not include
126  /// preparation passes on IR.
127  bool addCoreISelPasses();
128 
129 public:
131  // Dummy constructor.
133 
134  ~TargetPassConfig() override;
135 
136  static char ID;
137 
138  /// Get the right type of TargetMachine for this target.
139  template<typename TMC> TMC &getTM() const {
140  return *static_cast<TMC*>(TM);
141  }
142 
143  //
144  void setInitialized() { Initialized = true; }
145 
146  CodeGenOpt::Level getOptLevel() const;
147 
148  /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
149  /// or `-stop-before` options is set.
150  static bool hasLimitedCodeGenPipeline();
151 
152  /// Returns true if none of the `-stop-before` and `-stop-after` options is
153  /// set.
154  static bool willCompleteCodeGenPipeline();
155 
156  /// If hasLimitedCodeGenPipeline is true, this method
157  /// returns a string with the name of the options, separated
158  /// by \p Separator that caused this pipeline to be limited.
159  std::string
160  getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
161 
162  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
163 
164  bool getEnableTailMerge() const { return EnableTailMerge; }
165  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
166 
167  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
168  void setRequiresCodeGenSCCOrder(bool Enable = true) {
169  setOpt(RequireCodeGenSCCOrder, Enable);
170  }
171 
172  /// Allow the target to override a specific pass without overriding the pass
173  /// pipeline. When passes are added to the standard pipeline at the
174  /// point where StandardID is expected, add TargetID in its place.
175  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
176 
177  /// Insert InsertedPassID pass after TargetPassID pass.
178  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
179  bool VerifyAfter = true, bool PrintAfter = true);
180 
181  /// Allow the target to enable a specific standard pass by default.
182  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
183 
184  /// Allow the target to disable a specific standard pass by default.
185  void disablePass(AnalysisID PassID) {
186  substitutePass(PassID, IdentifyingPassPtr());
187  }
188 
189  /// Return the pass substituted for StandardID by the target.
190  /// If no substitution exists, return StandardID.
191  IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
192 
193  /// Return true if the pass has been substituted by the target or
194  /// overridden on the command line.
195  bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
196 
197  /// Return true if the optimized regalloc pipeline is enabled.
198  bool getOptimizeRegAlloc() const;
199 
200  /// Return true if the default global register allocator is in use and
201  /// has not be overriden on the command line with '-regalloc=...'
202  bool usingDefaultRegAlloc() const;
203 
204  /// High level function that adds all passes necessary to go from llvm IR
205  /// representation to the MI representation.
206  /// Adds IR based lowering and target specific optimization passes and finally
207  /// the core instruction selection passes.
208  /// \returns true if an error occurred, false otherwise.
209  bool addISelPasses();
210 
211  /// Add common target configurable passes that perform LLVM IR to IR
212  /// transforms following machine independent optimization.
213  virtual void addIRPasses();
214 
215  /// Add passes to lower exception handling for the code generator.
216  void addPassesToHandleExceptions();
217 
218  /// Add pass to prepare the LLVM IR for code generation. This should be done
219  /// before exception handling preparation passes.
220  virtual void addCodeGenPrepare();
221 
222  /// Add common passes that perform LLVM IR to IR transforms in preparation for
223  /// instruction selection.
224  virtual void addISelPrepare();
225 
226  /// addInstSelector - This method should install an instruction selector pass,
227  /// which converts from LLVM code to machine instructions.
228  virtual bool addInstSelector() {
229  return true;
230  }
231 
232  /// This method should install an IR translator pass, which converts from
233  /// LLVM code to machine instructions with possibly generic opcodes.
234  virtual bool addIRTranslator() { return true; }
235 
236  /// This method may be implemented by targets that want to run passes
237  /// immediately before legalization.
238  virtual void addPreLegalizeMachineIR() {}
239 
240  /// This method should install a legalize pass, which converts the instruction
241  /// sequence into one that can be selected by the target.
242  virtual bool addLegalizeMachineIR() { return true; }
243 
244  /// This method may be implemented by targets that want to run passes
245  /// immediately before the register bank selection.
246  virtual void addPreRegBankSelect() {}
247 
248  /// This method should install a register bank selector pass, which
249  /// assigns register banks to virtual registers without a register
250  /// class or register banks.
251  virtual bool addRegBankSelect() { return true; }
252 
253  /// This method may be implemented by targets that want to run passes
254  /// immediately before the (global) instruction selection.
256 
257  /// This method should install a (global) instruction selector pass, which
258  /// converts possibly generic instructions to fully target-specific
259  /// instructions, thereby constraining all generic virtual registers to
260  /// register classes.
261  virtual bool addGlobalInstructionSelect() { return true; }
262 
263  /// Add the complete, standard set of LLVM CodeGen passes.
264  /// Fully developed targets will not generally override this.
265  virtual void addMachinePasses();
266 
267  /// Create an instance of ScheduleDAGInstrs to be run within the standard
268  /// MachineScheduler pass for this function and target at the current
269  /// optimization level.
270  ///
271  /// This can also be used to plug a new MachineSchedStrategy into an instance
272  /// of the standard ScheduleDAGMI:
273  /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
274  ///
275  /// Return NULL to select the default (generic) machine scheduler.
276  virtual ScheduleDAGInstrs *
277  createMachineScheduler(MachineSchedContext *C) const {
278  return nullptr;
279  }
280 
281  /// Similar to createMachineScheduler but used when postRA machine scheduling
282  /// is enabled.
283  virtual ScheduleDAGInstrs *
285  return nullptr;
286  }
287 
288  /// printAndVerify - Add a pass to dump then verify the machine function, if
289  /// those steps are enabled.
290  void printAndVerify(const std::string &Banner);
291 
292  /// Add a pass to print the machine function if printing is enabled.
293  void addPrintPass(const std::string &Banner);
294 
295  /// Add a pass to perform basic verification of the machine function if
296  /// verification is enabled.
297  void addVerifyPass(const std::string &Banner);
298 
299  /// Check whether or not GlobalISel should abort on error.
300  /// When this is disabled, GlobalISel will fall back on SDISel instead of
301  /// erroring out.
302  bool isGlobalISelAbortEnabled() const;
303 
304  /// Check whether or not a diagnostic should be emitted when GlobalISel
305  /// uses the fallback path. In other words, it will emit a diagnostic
306  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
307  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
308 
309 protected:
310  // Helper to verify the analysis is really immutable.
311  void setOpt(bool &Opt, bool Val);
312 
313  /// Methods with trivial inline returns are convenient points in the common
314  /// codegen pass pipeline where targets may insert passes. Methods with
315  /// out-of-line standard implementations are major CodeGen stages called by
316  /// addMachinePasses. Some targets may override major stages when inserting
317  /// passes is insufficient, but maintaining overriden stages is more work.
318  ///
319 
320  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
321  /// passes (which are run just before instruction selector).
322  virtual bool addPreISel() {
323  return true;
324  }
325 
326  /// addMachineSSAOptimization - Add standard passes that optimize machine
327  /// instructions in SSA form.
328  virtual void addMachineSSAOptimization();
329 
330  /// Add passes that optimize instruction level parallelism for out-of-order
331  /// targets. These passes are run while the machine code is still in SSA
332  /// form, so they can use MachineTraceMetrics to control their heuristics.
333  ///
334  /// All passes added here should preserve the MachineDominatorTree,
335  /// MachineLoopInfo, and MachineTraceMetrics analyses.
336  virtual bool addILPOpts() {
337  return false;
338  }
339 
340  /// This method may be implemented by targets that want to run passes
341  /// immediately before register allocation.
342  virtual void addPreRegAlloc() { }
343 
344  /// createTargetRegisterAllocator - Create the register allocator pass for
345  /// this target at the current optimization level.
346  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
347 
348  /// addFastRegAlloc - Add the minimum set of target-independent passes that
349  /// are required for fast register allocation.
350  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
351 
352  /// addOptimizedRegAlloc - Add passes related to register allocation.
353  /// LLVMTargetMachine provides standard regalloc passes for most targets.
354  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
355 
356  /// addPreRewrite - Add passes to the optimized register allocation pipeline
357  /// after register allocation is complete, but before virtual registers are
358  /// rewritten to physical registers.
359  ///
360  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
361  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
362  /// When these passes run, VirtRegMap contains legal physreg assignments for
363  /// all virtual registers.
364  virtual bool addPreRewrite() {
365  return false;
366  }
367 
368  /// This method may be implemented by targets that want to run passes after
369  /// register allocation pass pipeline but before prolog-epilog insertion.
370  virtual void addPostRegAlloc() { }
371 
372  /// Add passes that optimize machine instructions after register allocation.
373  virtual void addMachineLateOptimization();
374 
375  /// This method may be implemented by targets that want to run passes after
376  /// prolog-epilog insertion and before the second instruction scheduling pass.
377  virtual void addPreSched2() { }
378 
379  /// addGCPasses - Add late codegen passes that analyze code for garbage
380  /// collection. This should return true if GC info should be printed after
381  /// these passes.
382  virtual bool addGCPasses();
383 
384  /// Add standard basic block placement passes.
385  virtual void addBlockPlacement();
386 
387  /// This pass may be implemented by targets that want to run passes
388  /// immediately before machine code is emitted.
389  virtual void addPreEmitPass() { }
390 
391  /// Targets may add passes immediately before machine code is emitted in this
392  /// callback. This is called even later than `addPreEmitPass`.
393  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
394  // position and remove the `2` suffix here as this callback is what
395  // `addPreEmitPass` *should* be but in reality isn't.
396  virtual void addPreEmitPass2() {}
397 
398  /// Utilities for targets to add passes to the pass manager.
399  ///
400 
401  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
402  /// Return the pass that was added, or zero if no pass was added.
403  /// @p printAfter if true and adding a machine function pass add an extra
404  /// machine printer pass afterwards
405  /// @p verifyAfter if true and adding a machine function pass add an extra
406  /// machine verification pass afterwards.
407  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
408  bool printAfter = true);
409 
410  /// Add a pass to the PassManager if that pass is supposed to be run, as
411  /// determined by the StartAfter and StopAfter options. Takes ownership of the
412  /// pass.
413  /// @p printAfter if true and adding a machine function pass add an extra
414  /// machine printer pass afterwards
415  /// @p verifyAfter if true and adding a machine function pass add an extra
416  /// machine verification pass afterwards.
417  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
418 
419  /// addMachinePasses helper to create the target-selected or overriden
420  /// regalloc pass.
421  FunctionPass *createRegAllocPass(bool Optimized);
422 };
423 
424 } // end namespace llvm
425 
426 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
uint64_t CallInst * C
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool requiresCodeGenSCCOrder() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
block Block Frequency true
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Target-Independent Code Generator Pass Configuration Options.
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVMTargetMachine * TM
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
bool getEnableTailMerge() const
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
void setEnableTailMerge(bool Enable)
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
void pm(uint64_t &Value)
Adjusts a program memory address.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
Definition: ArrayRef.h:530
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A ScheduleDAG for scheduling lists of MachineInstr.
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IdentifyingPassPtr(AnalysisID IDPtr)
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...