LLVM  8.0.0svn
TargetPassConfig.h
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1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// Target-Independent Code Generator Pass Configuration Options pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
16 
17 #include "llvm/Pass.h"
18 #include "llvm/Support/CodeGen.h"
19 #include <cassert>
20 #include <string>
21 
22 namespace llvm {
23 
24 class LLVMTargetMachine;
25 struct MachineSchedContext;
26 class PassConfigImpl;
27 class ScheduleDAGInstrs;
28 
29 // The old pass manager infrastructure is hidden in a legacy namespace now.
30 namespace legacy {
31 
32 class PassManagerBase;
33 
34 } // end namespace legacy
35 
37 
38 /// Discriminated union of Pass ID types.
39 ///
40 /// The PassConfig API prefers dealing with IDs because they are safer and more
41 /// efficient. IDs decouple configuration from instantiation. This way, when a
42 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
43 /// refer to a Pass pointer after adding it to a pass manager, which deletes
44 /// redundant pass instances.
45 ///
46 /// However, it is convient to directly instantiate target passes with
47 /// non-default ctors. These often don't have a registered PassInfo. Rather than
48 /// force all target passes to implement the pass registry boilerplate, allow
49 /// the PassConfig API to handle either type.
50 ///
51 /// AnalysisID is sadly char*, so PointerIntPair won't work.
53  union {
55  Pass *P;
56  };
57  bool IsInstance = false;
58 
59 public:
60  IdentifyingPassPtr() : P(nullptr) {}
61  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
62  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
63 
64  bool isValid() const { return P; }
65  bool isInstance() const { return IsInstance; }
66 
67  AnalysisID getID() const {
68  assert(!IsInstance && "Not a Pass ID");
69  return ID;
70  }
71 
72  Pass *getInstance() const {
73  assert(IsInstance && "Not a Pass Instance");
74  return P;
75  }
76 };
77 
78 template <> struct isPodLike<IdentifyingPassPtr> {
79  static const bool value = true;
80 };
81 
82 /// Target-Independent Code Generator Pass Configuration Options.
83 ///
84 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
85 /// to the internals of other CodeGen passes.
87 private:
88  PassManagerBase *PM = nullptr;
89  AnalysisID StartBefore = nullptr;
90  AnalysisID StartAfter = nullptr;
91  AnalysisID StopBefore = nullptr;
92  AnalysisID StopAfter = nullptr;
93 
94  unsigned StartBeforeInstanceNum = 0;
95  unsigned StartBeforeCount = 0;
96 
97  unsigned StartAfterInstanceNum = 0;
98  unsigned StartAfterCount = 0;
99 
100  unsigned StopBeforeInstanceNum = 0;
101  unsigned StopBeforeCount = 0;
102 
103  unsigned StopAfterInstanceNum = 0;
104  unsigned StopAfterCount = 0;
105 
106  bool Started = true;
107  bool Stopped = false;
108  bool AddingMachinePasses = false;
109 
110  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
111  /// a portion of the normal code-gen pass sequence.
112  ///
113  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
114  /// begin at the normal point; otherwise, clear the Started flag to indicate
115  /// that passes should not be added until the starting pass is seen. If the
116  /// Stop pass ID is zero, then compilation will continue to the end.
117  ///
118  /// This function expects that at least one of the StartAfter or the
119  /// StartBefore pass IDs is null.
120  void setStartStopPasses();
121 
122 protected:
124  PassConfigImpl *Impl = nullptr; // Internal data structures
125  bool Initialized = false; // Flagged after all passes are configured.
126 
127  // Target Pass Options
128  // Targets provide a default setting, user flags override.
129  bool DisableVerify = false;
130 
131  /// Default setting for -enable-tail-merge on this target.
132  bool EnableTailMerge = true;
133 
134  /// Require processing of functions such that callees are generated before
135  /// callers.
136  bool RequireCodeGenSCCOrder = false;
137 
138  /// Add the actual instruction selection passes. This does not include
139  /// preparation passes on IR.
140  bool addCoreISelPasses();
141 
142 public:
144  // Dummy constructor.
146 
147  ~TargetPassConfig() override;
148 
149  static char ID;
150 
151  /// Get the right type of TargetMachine for this target.
152  template<typename TMC> TMC &getTM() const {
153  return *static_cast<TMC*>(TM);
154  }
155 
156  //
157  void setInitialized() { Initialized = true; }
158 
159  CodeGenOpt::Level getOptLevel() const;
160 
161  /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
162  /// or `-stop-before` options is set.
163  static bool hasLimitedCodeGenPipeline();
164 
165  /// Returns true if none of the `-stop-before` and `-stop-after` options is
166  /// set.
167  static bool willCompleteCodeGenPipeline();
168 
169  /// If hasLimitedCodeGenPipeline is true, this method
170  /// returns a string with the name of the options, separated
171  /// by \p Separator that caused this pipeline to be limited.
172  std::string
173  getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
174 
175  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
176 
177  bool getEnableTailMerge() const { return EnableTailMerge; }
178  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
179 
180  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
181  void setRequiresCodeGenSCCOrder(bool Enable = true) {
182  setOpt(RequireCodeGenSCCOrder, Enable);
183  }
184 
185  /// Allow the target to override a specific pass without overriding the pass
186  /// pipeline. When passes are added to the standard pipeline at the
187  /// point where StandardID is expected, add TargetID in its place.
188  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
189 
190  /// Insert InsertedPassID pass after TargetPassID pass.
191  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
192  bool VerifyAfter = true, bool PrintAfter = true);
193 
194  /// Allow the target to enable a specific standard pass by default.
195  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
196 
197  /// Allow the target to disable a specific standard pass by default.
198  void disablePass(AnalysisID PassID) {
199  substitutePass(PassID, IdentifyingPassPtr());
200  }
201 
202  /// Return the pass substituted for StandardID by the target.
203  /// If no substitution exists, return StandardID.
204  IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
205 
206  /// Return true if the pass has been substituted by the target or
207  /// overridden on the command line.
208  bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
209 
210  /// Return true if the optimized regalloc pipeline is enabled.
211  bool getOptimizeRegAlloc() const;
212 
213  /// Return true if the default global register allocator is in use and
214  /// has not be overriden on the command line with '-regalloc=...'
215  bool usingDefaultRegAlloc() const;
216 
217  /// High level function that adds all passes necessary to go from llvm IR
218  /// representation to the MI representation.
219  /// Adds IR based lowering and target specific optimization passes and finally
220  /// the core instruction selection passes.
221  /// \returns true if an error occurred, false otherwise.
222  bool addISelPasses();
223 
224  /// Add common target configurable passes that perform LLVM IR to IR
225  /// transforms following machine independent optimization.
226  virtual void addIRPasses();
227 
228  /// Add passes to lower exception handling for the code generator.
229  void addPassesToHandleExceptions();
230 
231  /// Add pass to prepare the LLVM IR for code generation. This should be done
232  /// before exception handling preparation passes.
233  virtual void addCodeGenPrepare();
234 
235  /// Add common passes that perform LLVM IR to IR transforms in preparation for
236  /// instruction selection.
237  virtual void addISelPrepare();
238 
239  /// addInstSelector - This method should install an instruction selector pass,
240  /// which converts from LLVM code to machine instructions.
241  virtual bool addInstSelector() {
242  return true;
243  }
244 
245  /// This method should install an IR translator pass, which converts from
246  /// LLVM code to machine instructions with possibly generic opcodes.
247  virtual bool addIRTranslator() { return true; }
248 
249  /// This method may be implemented by targets that want to run passes
250  /// immediately before legalization.
251  virtual void addPreLegalizeMachineIR() {}
252 
253  /// This method should install a legalize pass, which converts the instruction
254  /// sequence into one that can be selected by the target.
255  virtual bool addLegalizeMachineIR() { return true; }
256 
257  /// This method may be implemented by targets that want to run passes
258  /// immediately before the register bank selection.
259  virtual void addPreRegBankSelect() {}
260 
261  /// This method should install a register bank selector pass, which
262  /// assigns register banks to virtual registers without a register
263  /// class or register banks.
264  virtual bool addRegBankSelect() { return true; }
265 
266  /// This method may be implemented by targets that want to run passes
267  /// immediately before the (global) instruction selection.
269 
270  /// This method should install a (global) instruction selector pass, which
271  /// converts possibly generic instructions to fully target-specific
272  /// instructions, thereby constraining all generic virtual registers to
273  /// register classes.
274  virtual bool addGlobalInstructionSelect() { return true; }
275 
276  /// Add the complete, standard set of LLVM CodeGen passes.
277  /// Fully developed targets will not generally override this.
278  virtual void addMachinePasses();
279 
280  /// Create an instance of ScheduleDAGInstrs to be run within the standard
281  /// MachineScheduler pass for this function and target at the current
282  /// optimization level.
283  ///
284  /// This can also be used to plug a new MachineSchedStrategy into an instance
285  /// of the standard ScheduleDAGMI:
286  /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
287  ///
288  /// Return NULL to select the default (generic) machine scheduler.
289  virtual ScheduleDAGInstrs *
290  createMachineScheduler(MachineSchedContext *C) const {
291  return nullptr;
292  }
293 
294  /// Similar to createMachineScheduler but used when postRA machine scheduling
295  /// is enabled.
296  virtual ScheduleDAGInstrs *
298  return nullptr;
299  }
300 
301  /// printAndVerify - Add a pass to dump then verify the machine function, if
302  /// those steps are enabled.
303  void printAndVerify(const std::string &Banner);
304 
305  /// Add a pass to print the machine function if printing is enabled.
306  void addPrintPass(const std::string &Banner);
307 
308  /// Add a pass to perform basic verification of the machine function if
309  /// verification is enabled.
310  void addVerifyPass(const std::string &Banner);
311 
312  /// Check whether or not GlobalISel should abort on error.
313  /// When this is disabled, GlobalISel will fall back on SDISel instead of
314  /// erroring out.
315  bool isGlobalISelAbortEnabled() const;
316 
317  /// Check whether or not a diagnostic should be emitted when GlobalISel
318  /// uses the fallback path. In other words, it will emit a diagnostic
319  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
320  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
321 
322 protected:
323  // Helper to verify the analysis is really immutable.
324  void setOpt(bool &Opt, bool Val);
325 
326  /// Methods with trivial inline returns are convenient points in the common
327  /// codegen pass pipeline where targets may insert passes. Methods with
328  /// out-of-line standard implementations are major CodeGen stages called by
329  /// addMachinePasses. Some targets may override major stages when inserting
330  /// passes is insufficient, but maintaining overriden stages is more work.
331  ///
332 
333  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
334  /// passes (which are run just before instruction selector).
335  virtual bool addPreISel() {
336  return true;
337  }
338 
339  /// addMachineSSAOptimization - Add standard passes that optimize machine
340  /// instructions in SSA form.
341  virtual void addMachineSSAOptimization();
342 
343  /// Add passes that optimize instruction level parallelism for out-of-order
344  /// targets. These passes are run while the machine code is still in SSA
345  /// form, so they can use MachineTraceMetrics to control their heuristics.
346  ///
347  /// All passes added here should preserve the MachineDominatorTree,
348  /// MachineLoopInfo, and MachineTraceMetrics analyses.
349  virtual bool addILPOpts() {
350  return false;
351  }
352 
353  /// This method may be implemented by targets that want to run passes
354  /// immediately before register allocation.
355  virtual void addPreRegAlloc() { }
356 
357  /// createTargetRegisterAllocator - Create the register allocator pass for
358  /// this target at the current optimization level.
359  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
360 
361  /// addFastRegAlloc - Add the minimum set of target-independent passes that
362  /// are required for fast register allocation.
363  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
364 
365  /// addOptimizedRegAlloc - Add passes related to register allocation.
366  /// LLVMTargetMachine provides standard regalloc passes for most targets.
367  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
368 
369  /// addPreRewrite - Add passes to the optimized register allocation pipeline
370  /// after register allocation is complete, but before virtual registers are
371  /// rewritten to physical registers.
372  ///
373  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
374  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
375  /// When these passes run, VirtRegMap contains legal physreg assignments for
376  /// all virtual registers.
377  virtual bool addPreRewrite() {
378  return false;
379  }
380 
381  /// This method may be implemented by targets that want to run passes after
382  /// register allocation pass pipeline but before prolog-epilog insertion.
383  virtual void addPostRegAlloc() { }
384 
385  /// Add passes that optimize machine instructions after register allocation.
386  virtual void addMachineLateOptimization();
387 
388  /// This method may be implemented by targets that want to run passes after
389  /// prolog-epilog insertion and before the second instruction scheduling pass.
390  virtual void addPreSched2() { }
391 
392  /// addGCPasses - Add late codegen passes that analyze code for garbage
393  /// collection. This should return true if GC info should be printed after
394  /// these passes.
395  virtual bool addGCPasses();
396 
397  /// Add standard basic block placement passes.
398  virtual void addBlockPlacement();
399 
400  /// This pass may be implemented by targets that want to run passes
401  /// immediately before machine code is emitted.
402  virtual void addPreEmitPass() { }
403 
404  /// Targets may add passes immediately before machine code is emitted in this
405  /// callback. This is called even later than `addPreEmitPass`.
406  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
407  // position and remove the `2` suffix here as this callback is what
408  // `addPreEmitPass` *should* be but in reality isn't.
409  virtual void addPreEmitPass2() {}
410 
411  /// Utilities for targets to add passes to the pass manager.
412  ///
413 
414  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
415  /// Return the pass that was added, or zero if no pass was added.
416  /// @p printAfter if true and adding a machine function pass add an extra
417  /// machine printer pass afterwards
418  /// @p verifyAfter if true and adding a machine function pass add an extra
419  /// machine verification pass afterwards.
420  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
421  bool printAfter = true);
422 
423  /// Add a pass to the PassManager if that pass is supposed to be run, as
424  /// determined by the StartAfter and StopAfter options. Takes ownership of the
425  /// pass.
426  /// @p printAfter if true and adding a machine function pass add an extra
427  /// machine printer pass afterwards
428  /// @p verifyAfter if true and adding a machine function pass add an extra
429  /// machine verification pass afterwards.
430  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
431 
432  /// addMachinePasses helper to create the target-selected or overriden
433  /// regalloc pass.
434  FunctionPass *createRegAllocPass(bool Optimized);
435 };
436 
437 } // end namespace llvm
438 
439 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:81
uint64_t CallInst * C
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
This class represents lattice values for constants.
Definition: AllocatorList.h:24
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool requiresCodeGenSCCOrder() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
block Block Frequency true
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Target-Independent Code Generator Pass Configuration Options.
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVMTargetMachine * TM
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
bool getEnableTailMerge() const
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
void setEnableTailMerge(bool Enable)
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
void pm(uint64_t &Value)
Adjusts a program memory address.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
Definition: ArrayRef.h:530
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
const void * AnalysisID
Definition: Pass.h:49
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A ScheduleDAG for scheduling lists of MachineInstr.
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IdentifyingPassPtr(AnalysisID IDPtr)
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...