LLVM  8.0.0svn
TargetTransformInfo.h
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1 //===- TargetTransformInfo.h ------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This pass exposes codegen information to IR-level passes. Every
11 /// transformation that uses codegen information is broken into three parts:
12 /// 1. The IR-level analysis pass.
13 /// 2. The IR-level transformation interface which provides the needed
14 /// information.
15 /// 3. Codegen-level implementation which uses target-specific hooks.
16 ///
17 /// This file defines #2, which is the interface that IR-level transformations
18 /// use for querying the codegen.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
23 #define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
24 
25 #include "llvm/ADT/Optional.h"
26 #include "llvm/IR/Operator.h"
27 #include "llvm/IR/PassManager.h"
28 #include "llvm/Pass.h"
30 #include "llvm/Support/DataTypes.h"
31 #include <functional>
32 
33 namespace llvm {
34 
35 namespace Intrinsic {
36 enum ID : unsigned;
37 }
38 
39 class Function;
40 class GlobalValue;
41 class IntrinsicInst;
42 class LoadInst;
43 class Loop;
44 class SCEV;
45 class ScalarEvolution;
46 class StoreInst;
47 class SwitchInst;
48 class Type;
49 class User;
50 class Value;
51 
52 /// Information about a load/store intrinsic defined by the target.
54  /// This is the pointer that the intrinsic is loading from or storing to.
55  /// If this is non-null, then analysis/optimization passes can assume that
56  /// this intrinsic is functionally equivalent to a load/store from this
57  /// pointer.
58  Value *PtrVal = nullptr;
59 
60  // Ordering for atomic operations.
62 
63  // Same Id is set by the target for corresponding load/store intrinsics.
64  unsigned short MatchingId = 0;
65 
66  bool ReadMem = false;
67  bool WriteMem = false;
68  bool IsVolatile = false;
69 
70  bool isUnordered() const {
71  return (Ordering == AtomicOrdering::NotAtomic ||
72  Ordering == AtomicOrdering::Unordered) && !IsVolatile;
73  }
74 };
75 
76 /// This pass provides access to the codegen interfaces that are needed
77 /// for IR-level transformations.
79 public:
80  /// Construct a TTI object using a type implementing the \c Concept
81  /// API below.
82  ///
83  /// This is used by targets to construct a TTI wrapping their target-specific
84  /// implementaion that encodes appropriate costs for their target.
85  template <typename T> TargetTransformInfo(T Impl);
86 
87  /// Construct a baseline TTI object using a minimal implementation of
88  /// the \c Concept API below.
89  ///
90  /// The TTI implementation will reflect the information in the DataLayout
91  /// provided if non-null.
92  explicit TargetTransformInfo(const DataLayout &DL);
93 
94  // Provide move semantics.
96  TargetTransformInfo &operator=(TargetTransformInfo &&RHS);
97 
98  // We need to define the destructor out-of-line to define our sub-classes
99  // out-of-line.
101 
102  /// Handle the invalidation of this information.
103  ///
104  /// When used as a result of \c TargetIRAnalysis this method will be called
105  /// when the function this was computed for changes. When it returns false,
106  /// the information is preserved across those changes.
109  // FIXME: We should probably in some way ensure that the subtarget
110  // information for a function hasn't changed.
111  return false;
112  }
113 
114  /// \name Generic Target Information
115  /// @{
116 
117  /// The kind of cost model.
118  ///
119  /// There are several different cost models that can be customized by the
120  /// target. The normalization of each cost model may be target specific.
122  TCK_RecipThroughput, ///< Reciprocal throughput.
123  TCK_Latency, ///< The latency of instruction.
124  TCK_CodeSize ///< Instruction code size.
125  };
126 
127  /// Query the cost of a specified instruction.
128  ///
129  /// Clients should use this interface to query the cost of an existing
130  /// instruction. The instruction must have a valid parent (basic block).
131  ///
132  /// Note, this method does not cache the cost calculation and it
133  /// can be expensive in some cases.
134  int getInstructionCost(const Instruction *I, enum TargetCostKind kind) const {
135  switch (kind){
136  case TCK_RecipThroughput:
137  return getInstructionThroughput(I);
138 
139  case TCK_Latency:
140  return getInstructionLatency(I);
141 
142  case TCK_CodeSize:
143  return getUserCost(I);
144  }
145  llvm_unreachable("Unknown instruction cost kind");
146  }
147 
148  /// Underlying constants for 'cost' values in this interface.
149  ///
150  /// Many APIs in this interface return a cost. This enum defines the
151  /// fundamental values that should be used to interpret (and produce) those
152  /// costs. The costs are returned as an int rather than a member of this
153  /// enumeration because it is expected that the cost of one IR instruction
154  /// may have a multiplicative factor to it or otherwise won't fit directly
155  /// into the enum. Moreover, it is common to sum or average costs which works
156  /// better as simple integral values. Thus this enum only provides constants.
157  /// Also note that the returned costs are signed integers to make it natural
158  /// to add, subtract, and test with zero (a common boundary condition). It is
159  /// not expected that 2^32 is a realistic cost to be modeling at any point.
160  ///
161  /// Note that these costs should usually reflect the intersection of code-size
162  /// cost and execution cost. A free instruction is typically one that folds
163  /// into another instruction. For example, reg-to-reg moves can often be
164  /// skipped by renaming the registers in the CPU, but they still are encoded
165  /// and thus wouldn't be considered 'free' here.
167  TCC_Free = 0, ///< Expected to fold away in lowering.
168  TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
169  TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
170  };
171 
172  /// Estimate the cost of a specific operation when lowered.
173  ///
174  /// Note that this is designed to work on an arbitrary synthetic opcode, and
175  /// thus work for hypothetical queries before an instruction has even been
176  /// formed. However, this does *not* work for GEPs, and must not be called
177  /// for a GEP instruction. Instead, use the dedicated getGEPCost interface as
178  /// analyzing a GEP's cost required more information.
179  ///
180  /// Typically only the result type is required, and the operand type can be
181  /// omitted. However, if the opcode is one of the cast instructions, the
182  /// operand type is required.
183  ///
184  /// The returned cost is defined in terms of \c TargetCostConstants, see its
185  /// comments for a detailed explanation of the cost values.
186  int getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy = nullptr) const;
187 
188  /// Estimate the cost of a GEP operation when lowered.
189  ///
190  /// The contract for this function is the same as \c getOperationCost except
191  /// that it supports an interface that provides extra information specific to
192  /// the GEP operation.
193  int getGEPCost(Type *PointeeType, const Value *Ptr,
194  ArrayRef<const Value *> Operands) const;
195 
196  /// Estimate the cost of a EXT operation when lowered.
197  ///
198  /// The contract for this function is the same as \c getOperationCost except
199  /// that it supports an interface that provides extra information specific to
200  /// the EXT operation.
201  int getExtCost(const Instruction *I, const Value *Src) const;
202 
203  /// Estimate the cost of a function call when lowered.
204  ///
205  /// The contract for this is the same as \c getOperationCost except that it
206  /// supports an interface that provides extra information specific to call
207  /// instructions.
208  ///
209  /// This is the most basic query for estimating call cost: it only knows the
210  /// function type and (potentially) the number of arguments at the call site.
211  /// The latter is only interesting for varargs function types.
212  int getCallCost(FunctionType *FTy, int NumArgs = -1) const;
213 
214  /// Estimate the cost of calling a specific function when lowered.
215  ///
216  /// This overload adds the ability to reason about the particular function
217  /// being called in the event it is a library call with special lowering.
218  int getCallCost(const Function *F, int NumArgs = -1) const;
219 
220  /// Estimate the cost of calling a specific function when lowered.
221  ///
222  /// This overload allows specifying a set of candidate argument values.
223  int getCallCost(const Function *F, ArrayRef<const Value *> Arguments) const;
224 
225  /// \returns A value by which our inlining threshold should be multiplied.
226  /// This is primarily used to bump up the inlining threshold wholesale on
227  /// targets where calls are unusually expensive.
228  ///
229  /// TODO: This is a rather blunt instrument. Perhaps altering the costs of
230  /// individual classes of instructions would be better.
231  unsigned getInliningThresholdMultiplier() const;
232 
233  /// Estimate the cost of an intrinsic when lowered.
234  ///
235  /// Mirrors the \c getCallCost method but uses an intrinsic identifier.
236  int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
237  ArrayRef<Type *> ParamTys) const;
238 
239  /// Estimate the cost of an intrinsic when lowered.
240  ///
241  /// Mirrors the \c getCallCost method but uses an intrinsic identifier.
242  int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
244 
245  /// \return The estimated number of case clusters when lowering \p 'SI'.
246  /// \p JTSize Set a jump table size only when \p SI is suitable for a jump
247  /// table.
248  unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
249  unsigned &JTSize) const;
250 
251  /// Estimate the cost of a given IR user when lowered.
252  ///
253  /// This can estimate the cost of either a ConstantExpr or Instruction when
254  /// lowered. It has two primary advantages over the \c getOperationCost and
255  /// \c getGEPCost above, and one significant disadvantage: it can only be
256  /// used when the IR construct has already been formed.
257  ///
258  /// The advantages are that it can inspect the SSA use graph to reason more
259  /// accurately about the cost. For example, all-constant-GEPs can often be
260  /// folded into a load or other instruction, but if they are used in some
261  /// other context they may not be folded. This routine can distinguish such
262  /// cases.
263  ///
264  /// \p Operands is a list of operands which can be a result of transformations
265  /// of the current operands. The number of the operands on the list must equal
266  /// to the number of the current operands the IR user has. Their order on the
267  /// list must be the same as the order of the current operands the IR user
268  /// has.
269  ///
270  /// The returned cost is defined in terms of \c TargetCostConstants, see its
271  /// comments for a detailed explanation of the cost values.
272  int getUserCost(const User *U, ArrayRef<const Value *> Operands) const;
273 
274  /// This is a helper function which calls the two-argument getUserCost
275  /// with \p Operands which are the current operands U has.
276  int getUserCost(const User *U) const {
278  U->value_op_end());
279  return getUserCost(U, Operands);
280  }
281 
282  /// Return true if branch divergence exists.
283  ///
284  /// Branch divergence has a significantly negative impact on GPU performance
285  /// when threads in the same wavefront take different paths due to conditional
286  /// branches.
287  bool hasBranchDivergence() const;
288 
289  /// Returns whether V is a source of divergence.
290  ///
291  /// This function provides the target-dependent information for
292  /// the target-independent LegacyDivergenceAnalysis. LegacyDivergenceAnalysis first
293  /// builds the dependency graph, and then runs the reachability algorithm
294  /// starting with the sources of divergence.
295  bool isSourceOfDivergence(const Value *V) const;
296 
297  // Returns true for the target specific
298  // set of operations which produce uniform result
299  // even taking non-unform arguments
300  bool isAlwaysUniform(const Value *V) const;
301 
302  /// Returns the address space ID for a target's 'flat' address space. Note
303  /// this is not necessarily the same as addrspace(0), which LLVM sometimes
304  /// refers to as the generic address space. The flat address space is a
305  /// generic address space that can be used access multiple segments of memory
306  /// with different address spaces. Access of a memory location through a
307  /// pointer with this address space is expected to be legal but slower
308  /// compared to the same memory location accessed through a pointer with a
309  /// different address space.
310  //
311  /// This is for targets with different pointer representations which can
312  /// be converted with the addrspacecast instruction. If a pointer is converted
313  /// to this address space, optimizations should attempt to replace the access
314  /// with the source address space.
315  ///
316  /// \returns ~0u if the target does not have such a flat address space to
317  /// optimize away.
318  unsigned getFlatAddressSpace() const;
319 
320  /// Test whether calls to a function lower to actual program function
321  /// calls.
322  ///
323  /// The idea is to test whether the program is likely to require a 'call'
324  /// instruction or equivalent in order to call the given function.
325  ///
326  /// FIXME: It's not clear that this is a good or useful query API. Client's
327  /// should probably move to simpler cost metrics using the above.
328  /// Alternatively, we could split the cost interface into distinct code-size
329  /// and execution-speed costs. This would allow modelling the core of this
330  /// query more accurately as a call is a single small instruction, but
331  /// incurs significant execution cost.
332  bool isLoweredToCall(const Function *F) const;
333 
334  struct LSRCost {
335  /// TODO: Some of these could be merged. Also, a lexical ordering
336  /// isn't always optimal.
337  unsigned Insns;
338  unsigned NumRegs;
339  unsigned AddRecCost;
340  unsigned NumIVMuls;
341  unsigned NumBaseAdds;
342  unsigned ImmCost;
343  unsigned SetupCost;
344  unsigned ScaleCost;
345  };
346 
347  /// Parameters that control the generic loop unrolling transformation.
349  /// The cost threshold for the unrolled loop. Should be relative to the
350  /// getUserCost values returned by this API, and the expectation is that
351  /// the unrolled loop's instructions when run through that interface should
352  /// not exceed this cost. However, this is only an estimate. Also, specific
353  /// loops may be unrolled even with a cost above this threshold if deemed
354  /// profitable. Set this to UINT_MAX to disable the loop body cost
355  /// restriction.
356  unsigned Threshold;
357  /// If complete unrolling will reduce the cost of the loop, we will boost
358  /// the Threshold by a certain percent to allow more aggressive complete
359  /// unrolling. This value provides the maximum boost percentage that we
360  /// can apply to Threshold (The value should be no less than 100).
361  /// BoostedThreshold = Threshold * min(RolledCost / UnrolledCost,
362  /// MaxPercentThresholdBoost / 100)
363  /// E.g. if complete unrolling reduces the loop execution time by 50%
364  /// then we boost the threshold by the factor of 2x. If unrolling is not
365  /// expected to reduce the running time, then we do not increase the
366  /// threshold.
368  /// The cost threshold for the unrolled loop when optimizing for size (set
369  /// to UINT_MAX to disable).
371  /// The cost threshold for the unrolled loop, like Threshold, but used
372  /// for partial/runtime unrolling (set to UINT_MAX to disable).
374  /// The cost threshold for the unrolled loop when optimizing for size, like
375  /// OptSizeThreshold, but used for partial/runtime unrolling (set to
376  /// UINT_MAX to disable).
378  /// A forced unrolling factor (the number of concatenated bodies of the
379  /// original loop in the unrolled loop body). When set to 0, the unrolling
380  /// transformation will select an unrolling factor based on the current cost
381  /// threshold and other factors.
382  unsigned Count;
383  /// A forced peeling factor (the number of bodied of the original loop
384  /// that should be peeled off before the loop body). When set to 0, the
385  /// unrolling transformation will select a peeling factor based on profile
386  /// information and other factors.
387  unsigned PeelCount;
388  /// Default unroll count for loops with run-time trip count.
390  // Set the maximum unrolling factor. The unrolling factor may be selected
391  // using the appropriate cost threshold, but may not exceed this number
392  // (set to UINT_MAX to disable). This does not apply in cases where the
393  // loop is being fully unrolled.
394  unsigned MaxCount;
395  /// Set the maximum unrolling factor for full unrolling. Like MaxCount, but
396  /// applies even if full unrolling is selected. This allows a target to fall
397  /// back to Partial unrolling if full unrolling is above FullUnrollMaxCount.
399  // Represents number of instructions optimized when "back edge"
400  // becomes "fall through" in unrolled loop.
401  // For now we count a conditional branch on a backedge and a comparison
402  // feeding it.
403  unsigned BEInsns;
404  /// Allow partial unrolling (unrolling of loops to expand the size of the
405  /// loop body, not only to eliminate small constant-trip-count loops).
406  bool Partial;
407  /// Allow runtime unrolling (unrolling of loops to expand the size of the
408  /// loop body even when the number of loop iterations is not known at
409  /// compile time).
410  bool Runtime;
411  /// Allow generation of a loop remainder (extra iterations after unroll).
413  /// Allow emitting expensive instructions (such as divisions) when computing
414  /// the trip count of a loop for runtime unrolling.
416  /// Apply loop unroll on any kind of loop
417  /// (mainly to loops that fail runtime unrolling).
418  bool Force;
419  /// Allow using trip count upper bound to unroll loops.
421  /// Allow peeling off loop iterations for loops with low dynamic tripcount.
423  /// Allow unrolling of all the iterations of the runtime loop remainder.
425  /// Allow unroll and jam. Used to enable unroll and jam for the target.
427  /// Threshold for unroll and jam, for inner loop size. The 'Threshold'
428  /// value above is used during unroll and jam for the outer loop size.
429  /// This value is used in the same manner to limit the size of the inner
430  /// loop.
432  };
433 
434  /// Get target-customized preferences for the generic loop unrolling
435  /// transformation. The caller will initialize UP with the current
436  /// target-independent defaults.
437  void getUnrollingPreferences(Loop *L, ScalarEvolution &,
438  UnrollingPreferences &UP) const;
439 
440  /// @}
441 
442  /// \name Scalar Target Information
443  /// @{
444 
445  /// Flags indicating the kind of support for population count.
446  ///
447  /// Compared to the SW implementation, HW support is supposed to
448  /// significantly boost the performance when the population is dense, and it
449  /// may or may not degrade performance if the population is sparse. A HW
450  /// support is considered as "Fast" if it can outperform, or is on a par
451  /// with, SW implementation when the population is sparse; otherwise, it is
452  /// considered as "Slow".
453  enum PopcntSupportKind { PSK_Software, PSK_SlowHardware, PSK_FastHardware };
454 
455  /// Return true if the specified immediate is legal add immediate, that
456  /// is the target has add instructions which can add a register with the
457  /// immediate without having to materialize the immediate into a register.
458  bool isLegalAddImmediate(int64_t Imm) const;
459 
460  /// Return true if the specified immediate is legal icmp immediate,
461  /// that is the target has icmp instructions which can compare a register
462  /// against the immediate without having to materialize the immediate into a
463  /// register.
464  bool isLegalICmpImmediate(int64_t Imm) const;
465 
466  /// Return true if the addressing mode represented by AM is legal for
467  /// this target, for a load/store of the specified type.
468  /// The type may be VoidTy, in which case only return true if the addressing
469  /// mode is legal for a load/store of any legal type.
470  /// If target returns true in LSRWithInstrQueries(), I may be valid.
471  /// TODO: Handle pre/postinc as well.
472  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
473  bool HasBaseReg, int64_t Scale,
474  unsigned AddrSpace = 0,
475  Instruction *I = nullptr) const;
476 
477  /// Return true if LSR cost of C1 is lower than C1.
478  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
479  TargetTransformInfo::LSRCost &C2) const;
480 
481  /// Return true if the target can fuse a compare and branch.
482  /// Loop-strength-reduction (LSR) uses that knowledge to adjust its cost
483  /// calculation for the instructions in a loop.
484  bool canMacroFuseCmp() const;
485 
486  /// \return True is LSR should make efforts to create/preserve post-inc
487  /// addressing mode expressions.
488  bool shouldFavorPostInc() const;
489 
490  /// Return true if the target supports masked load/store
491  /// AVX2 and AVX-512 targets allow masks for consecutive load and store
492  bool isLegalMaskedStore(Type *DataType) const;
493  bool isLegalMaskedLoad(Type *DataType) const;
494 
495  /// Return true if the target supports masked gather/scatter
496  /// AVX-512 fully supports gather and scatter for vectors with 32 and 64
497  /// bits scalar type.
498  bool isLegalMaskedScatter(Type *DataType) const;
499  bool isLegalMaskedGather(Type *DataType) const;
500 
501  /// Return true if the target has a unified operation to calculate division
502  /// and remainder. If so, the additional implicit multiplication and
503  /// subtraction required to calculate a remainder from division are free. This
504  /// can enable more aggressive transformations for division and remainder than
505  /// would typically be allowed using throughput or size cost models.
506  bool hasDivRemOp(Type *DataType, bool IsSigned) const;
507 
508  /// Return true if the given instruction (assumed to be a memory access
509  /// instruction) has a volatile variant. If that's the case then we can avoid
510  /// addrspacecast to generic AS for volatile loads/stores. Default
511  /// implementation returns false, which prevents address space inference for
512  /// volatile loads/stores.
513  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;
514 
515  /// Return true if target doesn't mind addresses in vectors.
516  bool prefersVectorizedAddressing() const;
517 
518  /// Return the cost of the scaling factor used in the addressing
519  /// mode represented by AM for this target, for a load/store
520  /// of the specified type.
521  /// If the AM is supported, the return value must be >= 0.
522  /// If the AM is not supported, it returns a negative value.
523  /// TODO: Handle pre/postinc as well.
524  int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
525  bool HasBaseReg, int64_t Scale,
526  unsigned AddrSpace = 0) const;
527 
528  /// Return true if the loop strength reduce pass should make
529  /// Instruction* based TTI queries to isLegalAddressingMode(). This is
530  /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned
531  /// immediate offset and no index register.
532  bool LSRWithInstrQueries() const;
533 
534  /// Return true if it's free to truncate a value of type Ty1 to type
535  /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
536  /// by referencing its sub-register AX.
537  bool isTruncateFree(Type *Ty1, Type *Ty2) const;
538 
539  /// Return true if it is profitable to hoist instruction in the
540  /// then/else to before if.
541  bool isProfitableToHoist(Instruction *I) const;
542 
543  bool useAA() const;
544 
545  /// Return true if this type is legal.
546  bool isTypeLegal(Type *Ty) const;
547 
548  /// Returns the target's jmp_buf alignment in bytes.
549  unsigned getJumpBufAlignment() const;
550 
551  /// Returns the target's jmp_buf size in bytes.
552  unsigned getJumpBufSize() const;
553 
554  /// Return true if switches should be turned into lookup tables for the
555  /// target.
556  bool shouldBuildLookupTables() const;
557 
558  /// Return true if switches should be turned into lookup tables
559  /// containing this constant value for the target.
560  bool shouldBuildLookupTablesForConstant(Constant *C) const;
561 
562  /// Return true if the input function which is cold at all call sites,
563  /// should use coldcc calling convention.
564  bool useColdCCForColdCall(Function &F) const;
565 
566  unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
567 
568  unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
569  unsigned VF) const;
570 
571  /// If target has efficient vector element load/store instructions, it can
572  /// return true here so that insertion/extraction costs are not added to
573  /// the scalarization cost of a load/store.
574  bool supportsEfficientVectorElementLoadStore() const;
575 
576  /// Don't restrict interleaved unrolling to small loops.
577  bool enableAggressiveInterleaving(bool LoopHasReductions) const;
578 
579  /// If not nullptr, enable inline expansion of memcmp. IsZeroCmp is
580  /// true if this is the expansion of memcmp(p1, p2, s) == 0.
582  // The list of available load sizes (in bytes), sorted in decreasing order.
584  };
585  const MemCmpExpansionOptions *enableMemCmpExpansion(bool IsZeroCmp) const;
586 
587  /// Enable matching of interleaved access groups.
588  bool enableInterleavedAccessVectorization() const;
589 
590  /// Enable matching of interleaved access groups that contain predicated
591  /// accesses or gaps and therefore vectorized using masked
592  /// vector loads/stores.
593  bool enableMaskedInterleavedAccessVectorization() const;
594 
595  /// Indicate that it is potentially unsafe to automatically vectorize
596  /// floating-point operations because the semantics of vector and scalar
597  /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math
598  /// does not support IEEE-754 denormal numbers, while depending on the
599  /// platform, scalar floating-point math does.
600  /// This applies to floating-point math operations and calls, not memory
601  /// operations, shuffles, or casts.
602  bool isFPVectorizationPotentiallyUnsafe() const;
603 
604  /// Determine if the target supports unaligned memory accesses.
605  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
606  unsigned BitWidth, unsigned AddressSpace = 0,
607  unsigned Alignment = 1,
608  bool *Fast = nullptr) const;
609 
610  /// Return hardware support for population count.
611  PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
612 
613  /// Return true if the hardware has a fast square-root instruction.
614  bool haveFastSqrt(Type *Ty) const;
615 
616  /// Return true if it is faster to check if a floating-point value is NaN
617  /// (or not-NaN) versus a comparison against a constant FP zero value.
618  /// Targets should override this if materializing a 0.0 for comparison is
619  /// generally as cheap as checking for ordered/unordered.
620  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const;
621 
622  /// Return the expected cost of supporting the floating point operation
623  /// of the specified type.
624  int getFPOpCost(Type *Ty) const;
625 
626  /// Return the expected cost of materializing for the given integer
627  /// immediate of the specified type.
628  int getIntImmCost(const APInt &Imm, Type *Ty) const;
629 
630  /// Return the expected cost of materialization for the given integer
631  /// immediate of the specified type for a given instruction. The cost can be
632  /// zero if the immediate can be folded into the specified instruction.
633  int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
634  Type *Ty) const;
635  int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
636  Type *Ty) const;
637 
638  /// Return the expected cost for the given integer when optimising
639  /// for size. This is different than the other integer immediate cost
640  /// functions in that it is subtarget agnostic. This is useful when you e.g.
641  /// target one ISA such as Aarch32 but smaller encodings could be possible
642  /// with another such as Thumb. This return value is used as a penalty when
643  /// the total costs for a constant is calculated (the bigger the cost, the
644  /// more beneficial constant hoisting is).
645  int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm,
646  Type *Ty) const;
647  /// @}
648 
649  /// \name Vector Target Information
650  /// @{
651 
652  /// The various kinds of shuffle patterns for vector queries.
653  enum ShuffleKind {
654  SK_Broadcast, ///< Broadcast element 0 to all other elements.
655  SK_Reverse, ///< Reverse the order of the vector.
656  SK_Select, ///< Selects elements from the corresponding lane of
657  ///< either source operand. This is equivalent to a
658  ///< vector select with a constant condition operand.
659  SK_Transpose, ///< Transpose two vectors.
660  SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
661  SK_ExtractSubvector,///< ExtractSubvector Index indicates start offset.
662  SK_PermuteTwoSrc, ///< Merge elements from two source vectors into one
663  ///< with any shuffle mask.
664  SK_PermuteSingleSrc ///< Shuffle elements of single source vector with any
665  ///< shuffle mask.
666  };
667 
668  /// Additional information about an operand's possible values.
670  OK_AnyValue, // Operand can have any value.
671  OK_UniformValue, // Operand is uniform (splat of a value).
672  OK_UniformConstantValue, // Operand is uniform constant.
673  OK_NonUniformConstantValue // Operand is a non uniform constant value.
674  };
675 
676  /// Additional properties of an operand's values.
677  enum OperandValueProperties { OP_None = 0, OP_PowerOf2 = 1 };
678 
679  /// \return The number of scalar or vector registers that the target has.
680  /// If 'Vectors' is true, it returns the number of vector registers. If it is
681  /// set to false, it returns the number of scalar registers.
682  unsigned getNumberOfRegisters(bool Vector) const;
683 
684  /// \return The width of the largest scalar or vector register type.
685  unsigned getRegisterBitWidth(bool Vector) const;
686 
687  /// \return The width of the smallest vector register type.
688  unsigned getMinVectorRegisterBitWidth() const;
689 
690  /// \return True if the vectorization factor should be chosen to
691  /// make the vector of the smallest element type match the size of a
692  /// vector register. For wider element types, this could result in
693  /// creating vectors that span multiple vector registers.
694  /// If false, the vectorization factor will be chosen based on the
695  /// size of the widest element type.
696  bool shouldMaximizeVectorBandwidth(bool OptSize) const;
697 
698  /// \return The minimum vectorization factor for types of given element
699  /// bit width, or 0 if there is no mimimum VF. The returned value only
700  /// applies when shouldMaximizeVectorBandwidth returns true.
701  unsigned getMinimumVF(unsigned ElemWidth) const;
702 
703  /// \return True if it should be considered for address type promotion.
704  /// \p AllowPromotionWithoutCommonHeader Set true if promoting \p I is
705  /// profitable without finding other extensions fed by the same input.
706  bool shouldConsiderAddressTypePromotion(
707  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const;
708 
709  /// \return The size of a cache line in bytes.
710  unsigned getCacheLineSize() const;
711 
712  /// The possible cache levels
713  enum class CacheLevel {
714  L1D, // The L1 data cache
715  L2D, // The L2 data cache
716 
717  // We currently do not model L3 caches, as their sizes differ widely between
718  // microarchitectures. Also, we currently do not have a use for L3 cache
719  // size modeling yet.
720  };
721 
722  /// \return The size of the cache level in bytes, if available.
723  llvm::Optional<unsigned> getCacheSize(CacheLevel Level) const;
724 
725  /// \return The associativity of the cache level, if available.
726  llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) const;
727 
728  /// \return How much before a load we should place the prefetch instruction.
729  /// This is currently measured in number of instructions.
730  unsigned getPrefetchDistance() const;
731 
732  /// \return Some HW prefetchers can handle accesses up to a certain constant
733  /// stride. This is the minimum stride in bytes where it makes sense to start
734  /// adding SW prefetches. The default is 1, i.e. prefetch with any stride.
735  unsigned getMinPrefetchStride() const;
736 
737  /// \return The maximum number of iterations to prefetch ahead. If the
738  /// required number of iterations is more than this number, no prefetching is
739  /// performed.
740  unsigned getMaxPrefetchIterationsAhead() const;
741 
742  /// \return The maximum interleave factor that any transform should try to
743  /// perform for this target. This number depends on the level of parallelism
744  /// and the number of execution units in the CPU.
745  unsigned getMaxInterleaveFactor(unsigned VF) const;
746 
747  /// Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
748  static OperandValueKind getOperandInfo(Value *V,
749  OperandValueProperties &OpProps);
750 
751  /// This is an approximation of reciprocal throughput of a math/logic op.
752  /// A higher cost indicates less expected throughput.
753  /// From Agner Fog's guides, reciprocal throughput is "the average number of
754  /// clock cycles per instruction when the instructions are not part of a
755  /// limiting dependency chain."
756  /// Therefore, costs should be scaled to account for multiple execution units
757  /// on the target that can process this type of instruction. For example, if
758  /// there are 5 scalar integer units and 2 vector integer units that can
759  /// calculate an 'add' in a single cycle, this model should indicate that the
760  /// cost of the vector add instruction is 2.5 times the cost of the scalar
761  /// add instruction.
762  /// \p Args is an optional argument which holds the instruction operands
763  /// values so the TTI can analyze those values searching for special
764  /// cases or optimizations based on those values.
765  int getArithmeticInstrCost(
766  unsigned Opcode, Type *Ty, OperandValueKind Opd1Info = OK_AnyValue,
767  OperandValueKind Opd2Info = OK_AnyValue,
768  OperandValueProperties Opd1PropInfo = OP_None,
769  OperandValueProperties Opd2PropInfo = OP_None,
771 
772  /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
773  /// The index and subtype parameters are used by the subvector insertion and
774  /// extraction shuffle kinds to show the insert/extract point and the type of
775  /// the subvector being inserted/extracted.
776  /// NOTE: For subvector extractions Tp represents the source type.
777  int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
778  Type *SubTp = nullptr) const;
779 
780  /// \return The expected cost of cast instructions, such as bitcast, trunc,
781  /// zext, etc. If there is an existing instruction that holds Opcode, it
782  /// may be passed in the 'I' parameter.
783  int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
784  const Instruction *I = nullptr) const;
785 
786  /// \return The expected cost of a sign- or zero-extended vector extract. Use
787  /// -1 to indicate that there is no information about the index value.
788  int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
789  unsigned Index = -1) const;
790 
791  /// \return The expected cost of control-flow related instructions such as
792  /// Phi, Ret, Br.
793  int getCFInstrCost(unsigned Opcode) const;
794 
795  /// \returns The expected cost of compare and select instructions. If there
796  /// is an existing instruction that holds Opcode, it may be passed in the
797  /// 'I' parameter.
798  int getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
799  Type *CondTy = nullptr, const Instruction *I = nullptr) const;
800 
801  /// \return The expected cost of vector Insert and Extract.
802  /// Use -1 to indicate that there is no information on the index value.
803  int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index = -1) const;
804 
805  /// \return The cost of Load and Store instructions.
806  int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
807  unsigned AddressSpace, const Instruction *I = nullptr) const;
808 
809  /// \return The cost of masked Load and Store instructions.
810  int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
811  unsigned AddressSpace) const;
812 
813  /// \return The cost of Gather or Scatter operation
814  /// \p Opcode - is a type of memory access Load or Store
815  /// \p DataTy - a vector type of the data to be loaded or stored
816  /// \p Ptr - pointer [or vector of pointers] - address[es] in memory
817  /// \p VariableMask - true when the memory access is predicated with a mask
818  /// that is not a compile-time constant
819  /// \p Alignment - alignment of single element
820  int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
821  bool VariableMask, unsigned Alignment) const;
822 
823  /// \return The cost of the interleaved memory operation.
824  /// \p Opcode is the memory operation code
825  /// \p VecTy is the vector type of the interleaved access.
826  /// \p Factor is the interleave factor
827  /// \p Indices is the indices for interleaved load members (as interleaved
828  /// load allows gaps)
829  /// \p Alignment is the alignment of the memory operation
830  /// \p AddressSpace is address space of the pointer.
831  /// \p UseMaskForCond indicates if the memory access is predicated.
832  /// \p UseMaskForGaps indicates if gaps should be masked.
833  int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
834  ArrayRef<unsigned> Indices, unsigned Alignment,
835  unsigned AddressSpace,
836  bool UseMaskForCond = false,
837  bool UseMaskForGaps = false) const;
838 
839  /// Calculate the cost of performing a vector reduction.
840  ///
841  /// This is the cost of reducing the vector value of type \p Ty to a scalar
842  /// value using the operation denoted by \p Opcode. The form of the reduction
843  /// can either be a pairwise reduction or a reduction that splits the vector
844  /// at every reduction level.
845  ///
846  /// Pairwise:
847  /// (v0, v1, v2, v3)
848  /// ((v0+v1), (v2+v3), undef, undef)
849  /// Split:
850  /// (v0, v1, v2, v3)
851  /// ((v0+v2), (v1+v3), undef, undef)
852  int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
853  bool IsPairwiseForm) const;
854  int getMinMaxReductionCost(Type *Ty, Type *CondTy, bool IsPairwiseForm,
855  bool IsUnsigned) const;
856 
857  /// \returns The cost of Intrinsic instructions. Analyses the real arguments.
858  /// Three cases are handled: 1. scalar instruction 2. vector instruction
859  /// 3. scalar instruction which is to be vectorized with VF.
860  int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
862  unsigned VF = 1) const;
863 
864  /// \returns The cost of Intrinsic instructions. Types analysis only.
865  /// If ScalarizationCostPassed is UINT_MAX, the cost of scalarizing the
866  /// arguments and the return value will be computed based on types.
867  int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
869  unsigned ScalarizationCostPassed = UINT_MAX) const;
870 
871  /// \returns The cost of Call instructions.
872  int getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys) const;
873 
874  /// \returns The number of pieces into which the provided type must be
875  /// split during legalization. Zero is returned when the answer is unknown.
876  unsigned getNumberOfParts(Type *Tp) const;
877 
878  /// \returns The cost of the address computation. For most targets this can be
879  /// merged into the instruction indexing mode. Some targets might want to
880  /// distinguish between address computation for memory operations on vector
881  /// types and scalar types. Such targets should override this function.
882  /// The 'SE' parameter holds pointer for the scalar evolution object which
883  /// is used in order to get the Ptr step value in case of constant stride.
884  /// The 'Ptr' parameter holds SCEV of the access pointer.
885  int getAddressComputationCost(Type *Ty, ScalarEvolution *SE = nullptr,
886  const SCEV *Ptr = nullptr) const;
887 
888  /// \returns The cost, if any, of keeping values of the given types alive
889  /// over a callsite.
890  ///
891  /// Some types may require the use of register classes that do not have
892  /// any callee-saved registers, so would require a spill and fill.
893  unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const;
894 
895  /// \returns True if the intrinsic is a supported memory intrinsic. Info
896  /// will contain additional information - whether the intrinsic may write
897  /// or read to memory, volatility and the pointer. Info is undefined
898  /// if false is returned.
899  bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
900 
901  /// \returns The maximum element size, in bytes, for an element
902  /// unordered-atomic memory intrinsic.
903  unsigned getAtomicMemIntrinsicMaxElementSize() const;
904 
905  /// \returns A value which is the result of the given memory intrinsic. New
906  /// instructions may be created to extract the result from the given intrinsic
907  /// memory operation. Returns nullptr if the target cannot create a result
908  /// from the given intrinsic.
909  Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
910  Type *ExpectedType) const;
911 
912  /// \returns The type to use in a loop expansion of a memcpy call.
913  Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
914  unsigned SrcAlign, unsigned DestAlign) const;
915 
916  /// \param[out] OpsOut The operand types to copy RemainingBytes of memory.
917  /// \param RemainingBytes The number of bytes to copy.
918  ///
919  /// Calculates the operand types to use when copying \p RemainingBytes of
920  /// memory, where source and destination alignments are \p SrcAlign and
921  /// \p DestAlign respectively.
922  void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
923  LLVMContext &Context,
924  unsigned RemainingBytes,
925  unsigned SrcAlign,
926  unsigned DestAlign) const;
927 
928  /// \returns True if the two functions have compatible attributes for inlining
929  /// purposes.
930  bool areInlineCompatible(const Function *Caller,
931  const Function *Callee) const;
932 
933  /// The type of load/store indexing.
935  MIM_Unindexed, ///< No indexing.
936  MIM_PreInc, ///< Pre-incrementing.
937  MIM_PreDec, ///< Pre-decrementing.
938  MIM_PostInc, ///< Post-incrementing.
939  MIM_PostDec ///< Post-decrementing.
940  };
941 
942  /// \returns True if the specified indexed load for the given type is legal.
943  bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
944 
945  /// \returns True if the specified indexed store for the given type is legal.
946  bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
947 
948  /// \returns The bitwidth of the largest vector type that should be used to
949  /// load/store in the given address space.
950  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
951 
952  /// \returns True if the load instruction is legal to vectorize.
953  bool isLegalToVectorizeLoad(LoadInst *LI) const;
954 
955  /// \returns True if the store instruction is legal to vectorize.
956  bool isLegalToVectorizeStore(StoreInst *SI) const;
957 
958  /// \returns True if it is legal to vectorize the given load chain.
959  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
960  unsigned Alignment,
961  unsigned AddrSpace) const;
962 
963  /// \returns True if it is legal to vectorize the given store chain.
964  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
965  unsigned Alignment,
966  unsigned AddrSpace) const;
967 
968  /// \returns The new vector factor value if the target doesn't support \p
969  /// SizeInBytes loads or has a better vector factor.
970  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
971  unsigned ChainSizeInBytes,
972  VectorType *VecTy) const;
973 
974  /// \returns The new vector factor value if the target doesn't support \p
975  /// SizeInBytes stores or has a better vector factor.
976  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
977  unsigned ChainSizeInBytes,
978  VectorType *VecTy) const;
979 
980  /// Flags describing the kind of vector reduction.
981  struct ReductionFlags {
982  ReductionFlags() : IsMaxOp(false), IsSigned(false), NoNaN(false) {}
983  bool IsMaxOp; ///< If the op a min/max kind, true if it's a max operation.
984  bool IsSigned; ///< Whether the operation is a signed int reduction.
985  bool NoNaN; ///< If op is an fp min/max, whether NaNs may be present.
986  };
987 
988  /// \returns True if the target wants to handle the given reduction idiom in
989  /// the intrinsics form instead of the shuffle form.
990  bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
991  ReductionFlags Flags) const;
992 
993  /// \returns True if the target wants to expand the given reduction intrinsic
994  /// into a shuffle sequence.
995  bool shouldExpandReduction(const IntrinsicInst *II) const;
996  /// @}
997 
998 private:
999  /// Estimate the latency of specified instruction.
1000  /// Returns 1 as the default value.
1001  int getInstructionLatency(const Instruction *I) const;
1002 
1003  /// Returns the expected throughput cost of the instruction.
1004  /// Returns -1 if the cost is unknown.
1005  int getInstructionThroughput(const Instruction *I) const;
1006 
1007  /// The abstract base class used to type erase specific TTI
1008  /// implementations.
1009  class Concept;
1010 
1011  /// The template model for the base class which wraps a concrete
1012  /// implementation in a type erased interface.
1013  template <typename T> class Model;
1014 
1015  std::unique_ptr<Concept> TTIImpl;
1016 };
1017 
1019 public:
1020  virtual ~Concept() = 0;
1021  virtual const DataLayout &getDataLayout() const = 0;
1022  virtual int getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) = 0;
1023  virtual int getGEPCost(Type *PointeeType, const Value *Ptr,
1024  ArrayRef<const Value *> Operands) = 0;
1025  virtual int getExtCost(const Instruction *I, const Value *Src) = 0;
1026  virtual int getCallCost(FunctionType *FTy, int NumArgs) = 0;
1027  virtual int getCallCost(const Function *F, int NumArgs) = 0;
1028  virtual int getCallCost(const Function *F,
1030  virtual unsigned getInliningThresholdMultiplier() = 0;
1031  virtual int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
1032  ArrayRef<Type *> ParamTys) = 0;
1033  virtual int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
1034  ArrayRef<const Value *> Arguments) = 0;
1035  virtual unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
1036  unsigned &JTSize) = 0;
1037  virtual int
1038  getUserCost(const User *U, ArrayRef<const Value *> Operands) = 0;
1039  virtual bool hasBranchDivergence() = 0;
1040  virtual bool isSourceOfDivergence(const Value *V) = 0;
1041  virtual bool isAlwaysUniform(const Value *V) = 0;
1042  virtual unsigned getFlatAddressSpace() = 0;
1043  virtual bool isLoweredToCall(const Function *F) = 0;
1044  virtual void getUnrollingPreferences(Loop *L, ScalarEvolution &,
1045  UnrollingPreferences &UP) = 0;
1046  virtual bool isLegalAddImmediate(int64_t Imm) = 0;
1047  virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
1048  virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
1049  int64_t BaseOffset, bool HasBaseReg,
1050  int64_t Scale,
1051  unsigned AddrSpace,
1052  Instruction *I) = 0;
1053  virtual bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
1055  virtual bool canMacroFuseCmp() = 0;
1056  virtual bool shouldFavorPostInc() const = 0;
1057  virtual bool isLegalMaskedStore(Type *DataType) = 0;
1058  virtual bool isLegalMaskedLoad(Type *DataType) = 0;
1059  virtual bool isLegalMaskedScatter(Type *DataType) = 0;
1060  virtual bool isLegalMaskedGather(Type *DataType) = 0;
1061  virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
1062  virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
1063  virtual bool prefersVectorizedAddressing() = 0;
1064  virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
1065  int64_t BaseOffset, bool HasBaseReg,
1066  int64_t Scale, unsigned AddrSpace) = 0;
1067  virtual bool LSRWithInstrQueries() = 0;
1068  virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
1069  virtual bool isProfitableToHoist(Instruction *I) = 0;
1070  virtual bool useAA() = 0;
1071  virtual bool isTypeLegal(Type *Ty) = 0;
1072  virtual unsigned getJumpBufAlignment() = 0;
1073  virtual unsigned getJumpBufSize() = 0;
1074  virtual bool shouldBuildLookupTables() = 0;
1075  virtual bool shouldBuildLookupTablesForConstant(Constant *C) = 0;
1076  virtual bool useColdCCForColdCall(Function &F) = 0;
1077  virtual unsigned
1078  getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) = 0;
1079  virtual unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
1080  unsigned VF) = 0;
1081  virtual bool supportsEfficientVectorElementLoadStore() = 0;
1082  virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
1083  virtual const MemCmpExpansionOptions *enableMemCmpExpansion(
1084  bool IsZeroCmp) const = 0;
1085  virtual bool enableInterleavedAccessVectorization() = 0;
1086  virtual bool enableMaskedInterleavedAccessVectorization() = 0;
1087  virtual bool isFPVectorizationPotentiallyUnsafe() = 0;
1088  virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
1089  unsigned BitWidth,
1090  unsigned AddressSpace,
1091  unsigned Alignment,
1092  bool *Fast) = 0;
1093  virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) = 0;
1094  virtual bool haveFastSqrt(Type *Ty) = 0;
1095  virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) = 0;
1096  virtual int getFPOpCost(Type *Ty) = 0;
1097  virtual int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm,
1098  Type *Ty) = 0;
1099  virtual int getIntImmCost(const APInt &Imm, Type *Ty) = 0;
1100  virtual int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
1101  Type *Ty) = 0;
1102  virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
1103  Type *Ty) = 0;
1104  virtual unsigned getNumberOfRegisters(bool Vector) = 0;
1105  virtual unsigned getRegisterBitWidth(bool Vector) const = 0;
1106  virtual unsigned getMinVectorRegisterBitWidth() = 0;
1107  virtual bool shouldMaximizeVectorBandwidth(bool OptSize) const = 0;
1108  virtual unsigned getMinimumVF(unsigned ElemWidth) const = 0;
1109  virtual bool shouldConsiderAddressTypePromotion(
1110  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) = 0;
1111  virtual unsigned getCacheLineSize() = 0;
1112  virtual llvm::Optional<unsigned> getCacheSize(CacheLevel Level) = 0;
1113  virtual llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) = 0;
1114  virtual unsigned getPrefetchDistance() = 0;
1115  virtual unsigned getMinPrefetchStride() = 0;
1116  virtual unsigned getMaxPrefetchIterationsAhead() = 0;
1117  virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
1118  virtual unsigned
1119  getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
1120  OperandValueKind Opd2Info,
1121  OperandValueProperties Opd1PropInfo,
1122  OperandValueProperties Opd2PropInfo,
1123  ArrayRef<const Value *> Args) = 0;
1124  virtual int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
1125  Type *SubTp) = 0;
1126  virtual int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1127  const Instruction *I) = 0;
1128  virtual int getExtractWithExtendCost(unsigned Opcode, Type *Dst,
1129  VectorType *VecTy, unsigned Index) = 0;
1130  virtual int getCFInstrCost(unsigned Opcode) = 0;
1131  virtual int getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
1132  Type *CondTy, const Instruction *I) = 0;
1133  virtual int getVectorInstrCost(unsigned Opcode, Type *Val,
1134  unsigned Index) = 0;
1135  virtual int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
1136  unsigned AddressSpace, const Instruction *I) = 0;
1137  virtual int getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
1138  unsigned Alignment,
1139  unsigned AddressSpace) = 0;
1140  virtual int getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
1141  Value *Ptr, bool VariableMask,
1142  unsigned Alignment) = 0;
1143  virtual int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
1144  unsigned Factor,
1145  ArrayRef<unsigned> Indices,
1146  unsigned Alignment,
1147  unsigned AddressSpace,
1148  bool UseMaskForCond = false,
1149  bool UseMaskForGaps = false) = 0;
1150  virtual int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
1151  bool IsPairwiseForm) = 0;
1152  virtual int getMinMaxReductionCost(Type *Ty, Type *CondTy,
1153  bool IsPairwiseForm, bool IsUnsigned) = 0;
1154  virtual int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
1156  unsigned ScalarizationCostPassed) = 0;
1157  virtual int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
1158  ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) = 0;
1159  virtual int getCallInstrCost(Function *F, Type *RetTy,
1160  ArrayRef<Type *> Tys) = 0;
1161  virtual unsigned getNumberOfParts(Type *Tp) = 0;
1162  virtual int getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
1163  const SCEV *Ptr) = 0;
1164  virtual unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) = 0;
1165  virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst,
1166  MemIntrinsicInfo &Info) = 0;
1167  virtual unsigned getAtomicMemIntrinsicMaxElementSize() const = 0;
1168  virtual Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
1169  Type *ExpectedType) = 0;
1170  virtual Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
1171  unsigned SrcAlign,
1172  unsigned DestAlign) const = 0;
1173  virtual void getMemcpyLoopResidualLoweringType(
1174  SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1175  unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const = 0;
1176  virtual bool areInlineCompatible(const Function *Caller,
1177  const Function *Callee) const = 0;
1178  virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0;
1179  virtual bool isIndexedStoreLegal(MemIndexedMode Mode,Type *Ty) const = 0;
1180  virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const = 0;
1181  virtual bool isLegalToVectorizeLoad(LoadInst *LI) const = 0;
1182  virtual bool isLegalToVectorizeStore(StoreInst *SI) const = 0;
1183  virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
1184  unsigned Alignment,
1185  unsigned AddrSpace) const = 0;
1186  virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
1187  unsigned Alignment,
1188  unsigned AddrSpace) const = 0;
1189  virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1190  unsigned ChainSizeInBytes,
1191  VectorType *VecTy) const = 0;
1192  virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1193  unsigned ChainSizeInBytes,
1194  VectorType *VecTy) const = 0;
1195  virtual bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
1196  ReductionFlags) const = 0;
1197  virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
1198  virtual int getInstructionLatency(const Instruction *I) = 0;
1199 };
1200 
1201 template <typename T>
1203  T Impl;
1204 
1205 public:
1206  Model(T Impl) : Impl(std::move(Impl)) {}
1207  ~Model() override {}
1208 
1209  const DataLayout &getDataLayout() const override {
1210  return Impl.getDataLayout();
1211  }
1212 
1213  int getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) override {
1214  return Impl.getOperationCost(Opcode, Ty, OpTy);
1215  }
1216  int getGEPCost(Type *PointeeType, const Value *Ptr,
1217  ArrayRef<const Value *> Operands) override {
1218  return Impl.getGEPCost(PointeeType, Ptr, Operands);
1219  }
1220  int getExtCost(const Instruction *I, const Value *Src) override {
1221  return Impl.getExtCost(I, Src);
1222  }
1223  int getCallCost(FunctionType *FTy, int NumArgs) override {
1224  return Impl.getCallCost(FTy, NumArgs);
1225  }
1226  int getCallCost(const Function *F, int NumArgs) override {
1227  return Impl.getCallCost(F, NumArgs);
1228  }
1229  int getCallCost(const Function *F,
1231  return Impl.getCallCost(F, Arguments);
1232  }
1233  unsigned getInliningThresholdMultiplier() override {
1234  return Impl.getInliningThresholdMultiplier();
1235  }
1236  int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
1237  ArrayRef<Type *> ParamTys) override {
1238  return Impl.getIntrinsicCost(IID, RetTy, ParamTys);
1239  }
1240  int getIntrinsicCost(Intrinsic::ID IID, Type *RetTy,
1241  ArrayRef<const Value *> Arguments) override {
1242  return Impl.getIntrinsicCost(IID, RetTy, Arguments);
1243  }
1244  int getUserCost(const User *U, ArrayRef<const Value *> Operands) override {
1245  return Impl.getUserCost(U, Operands);
1246  }
1247  bool hasBranchDivergence() override { return Impl.hasBranchDivergence(); }
1248  bool isSourceOfDivergence(const Value *V) override {
1249  return Impl.isSourceOfDivergence(V);
1250  }
1251 
1252  bool isAlwaysUniform(const Value *V) override {
1253  return Impl.isAlwaysUniform(V);
1254  }
1255 
1256  unsigned getFlatAddressSpace() override {
1257  return Impl.getFlatAddressSpace();
1258  }
1259 
1260  bool isLoweredToCall(const Function *F) override {
1261  return Impl.isLoweredToCall(F);
1262  }
1263  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
1264  UnrollingPreferences &UP) override {
1265  return Impl.getUnrollingPreferences(L, SE, UP);
1266  }
1267  bool isLegalAddImmediate(int64_t Imm) override {
1268  return Impl.isLegalAddImmediate(Imm);
1269  }
1270  bool isLegalICmpImmediate(int64_t Imm) override {
1271  return Impl.isLegalICmpImmediate(Imm);
1272  }
1273  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
1274  bool HasBaseReg, int64_t Scale,
1275  unsigned AddrSpace,
1276  Instruction *I) override {
1277  return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
1278  Scale, AddrSpace, I);
1279  }
1280  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
1281  TargetTransformInfo::LSRCost &C2) override {
1282  return Impl.isLSRCostLess(C1, C2);
1283  }
1284  bool canMacroFuseCmp() override {
1285  return Impl.canMacroFuseCmp();
1286  }
1287  bool shouldFavorPostInc() const override {
1288  return Impl.shouldFavorPostInc();
1289  }
1290  bool isLegalMaskedStore(Type *DataType) override {
1291  return Impl.isLegalMaskedStore(DataType);
1292  }
1293  bool isLegalMaskedLoad(Type *DataType) override {
1294  return Impl.isLegalMaskedLoad(DataType);
1295  }
1296  bool isLegalMaskedScatter(Type *DataType) override {
1297  return Impl.isLegalMaskedScatter(DataType);
1298  }
1299  bool isLegalMaskedGather(Type *DataType) override {
1300  return Impl.isLegalMaskedGather(DataType);
1301  }
1302  bool hasDivRemOp(Type *DataType, bool IsSigned) override {
1303  return Impl.hasDivRemOp(DataType, IsSigned);
1304  }
1305  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override {
1306  return Impl.hasVolatileVariant(I, AddrSpace);
1307  }
1308  bool prefersVectorizedAddressing() override {
1309  return Impl.prefersVectorizedAddressing();
1310  }
1311  int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
1312  bool HasBaseReg, int64_t Scale,
1313  unsigned AddrSpace) override {
1314  return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
1315  Scale, AddrSpace);
1316  }
1317  bool LSRWithInstrQueries() override {
1318  return Impl.LSRWithInstrQueries();
1319  }
1320  bool isTruncateFree(Type *Ty1, Type *Ty2) override {
1321  return Impl.isTruncateFree(Ty1, Ty2);
1322  }
1323  bool isProfitableToHoist(Instruction *I) override {
1324  return Impl.isProfitableToHoist(I);
1325  }
1326  bool useAA() override { return Impl.useAA(); }
1327  bool isTypeLegal(Type *Ty) override { return Impl.isTypeLegal(Ty); }
1328  unsigned getJumpBufAlignment() override { return Impl.getJumpBufAlignment(); }
1329  unsigned getJumpBufSize() override { return Impl.getJumpBufSize(); }
1330  bool shouldBuildLookupTables() override {
1331  return Impl.shouldBuildLookupTables();
1332  }
1333  bool shouldBuildLookupTablesForConstant(Constant *C) override {
1334  return Impl.shouldBuildLookupTablesForConstant(C);
1335  }
1336  bool useColdCCForColdCall(Function &F) override {
1337  return Impl.useColdCCForColdCall(F);
1338  }
1339 
1340  unsigned getScalarizationOverhead(Type *Ty, bool Insert,
1341  bool Extract) override {
1342  return Impl.getScalarizationOverhead(Ty, Insert, Extract);
1343  }
1344  unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
1345  unsigned VF) override {
1346  return Impl.getOperandsScalarizationOverhead(Args, VF);
1347  }
1348 
1349  bool supportsEfficientVectorElementLoadStore() override {
1350  return Impl.supportsEfficientVectorElementLoadStore();
1351  }
1352 
1353  bool enableAggressiveInterleaving(bool LoopHasReductions) override {
1354  return Impl.enableAggressiveInterleaving(LoopHasReductions);
1355  }
1356  const MemCmpExpansionOptions *enableMemCmpExpansion(
1357  bool IsZeroCmp) const override {
1358  return Impl.enableMemCmpExpansion(IsZeroCmp);
1359  }
1360  bool enableInterleavedAccessVectorization() override {
1361  return Impl.enableInterleavedAccessVectorization();
1362  }
1363  bool enableMaskedInterleavedAccessVectorization() override {
1364  return Impl.enableMaskedInterleavedAccessVectorization();
1365  }
1366  bool isFPVectorizationPotentiallyUnsafe() override {
1367  return Impl.isFPVectorizationPotentiallyUnsafe();
1368  }
1369  bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
1370  unsigned BitWidth, unsigned AddressSpace,
1371  unsigned Alignment, bool *Fast) override {
1372  return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
1373  Alignment, Fast);
1374  }
1375  PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) override {
1376  return Impl.getPopcntSupport(IntTyWidthInBit);
1377  }
1378  bool haveFastSqrt(Type *Ty) override { return Impl.haveFastSqrt(Ty); }
1379 
1380  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) override {
1381  return Impl.isFCmpOrdCheaperThanFCmpZero(Ty);
1382  }
1383 
1384  int getFPOpCost(Type *Ty) override { return Impl.getFPOpCost(Ty); }
1385 
1386  int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm,
1387  Type *Ty) override {
1388  return Impl.getIntImmCodeSizeCost(Opc, Idx, Imm, Ty);
1389  }
1390  int getIntImmCost(const APInt &Imm, Type *Ty) override {
1391  return Impl.getIntImmCost(Imm, Ty);
1392  }
1393  int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
1394  Type *Ty) override {
1395  return Impl.getIntImmCost(Opc, Idx, Imm, Ty);
1396  }
1397  int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
1398  Type *Ty) override {
1399  return Impl.getIntImmCost(IID, Idx, Imm, Ty);
1400  }
1401  unsigned getNumberOfRegisters(bool Vector) override {
1402  return Impl.getNumberOfRegisters(Vector);
1403  }
1404  unsigned getRegisterBitWidth(bool Vector) const override {
1405  return Impl.getRegisterBitWidth(Vector);
1406  }
1407  unsigned getMinVectorRegisterBitWidth() override {
1408  return Impl.getMinVectorRegisterBitWidth();
1409  }
1410  bool shouldMaximizeVectorBandwidth(bool OptSize) const override {
1411  return Impl.shouldMaximizeVectorBandwidth(OptSize);
1412  }
1413  unsigned getMinimumVF(unsigned ElemWidth) const override {
1414  return Impl.getMinimumVF(ElemWidth);
1415  }
1416  bool shouldConsiderAddressTypePromotion(
1417  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) override {
1418  return Impl.shouldConsiderAddressTypePromotion(
1419  I, AllowPromotionWithoutCommonHeader);
1420  }
1421  unsigned getCacheLineSize() override {
1422  return Impl.getCacheLineSize();
1423  }
1424  llvm::Optional<unsigned> getCacheSize(CacheLevel Level) override {
1425  return Impl.getCacheSize(Level);
1426  }
1427  llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) override {
1428  return Impl.getCacheAssociativity(Level);
1429  }
1430  unsigned getPrefetchDistance() override { return Impl.getPrefetchDistance(); }
1431  unsigned getMinPrefetchStride() override {
1432  return Impl.getMinPrefetchStride();
1433  }
1434  unsigned getMaxPrefetchIterationsAhead() override {
1435  return Impl.getMaxPrefetchIterationsAhead();
1436  }
1437  unsigned getMaxInterleaveFactor(unsigned VF) override {
1438  return Impl.getMaxInterleaveFactor(VF);
1439  }
1440  unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
1441  unsigned &JTSize) override {
1442  return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize);
1443  }
1444  unsigned
1445  getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
1446  OperandValueKind Opd2Info,
1447  OperandValueProperties Opd1PropInfo,
1448  OperandValueProperties Opd2PropInfo,
1449  ArrayRef<const Value *> Args) override {
1450  return Impl.getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
1451  Opd1PropInfo, Opd2PropInfo, Args);
1452  }
1453  int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
1454  Type *SubTp) override {
1455  return Impl.getShuffleCost(Kind, Tp, Index, SubTp);
1456  }
1457  int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1458  const Instruction *I) override {
1459  return Impl.getCastInstrCost(Opcode, Dst, Src, I);
1460  }
1461  int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
1462  unsigned Index) override {
1463  return Impl.getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
1464  }
1465  int getCFInstrCost(unsigned Opcode) override {
1466  return Impl.getCFInstrCost(Opcode);
1467  }
1468  int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1469  const Instruction *I) override {
1470  return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
1471  }
1472  int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) override {
1473  return Impl.getVectorInstrCost(Opcode, Val, Index);
1474  }
1475  int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
1476  unsigned AddressSpace, const Instruction *I) override {
1477  return Impl.getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
1478  }
1479  int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
1480  unsigned AddressSpace) override {
1481  return Impl.getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
1482  }
1483  int getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
1484  Value *Ptr, bool VariableMask,
1485  unsigned Alignment) override {
1486  return Impl.getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
1487  Alignment);
1488  }
1489  int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
1490  ArrayRef<unsigned> Indices, unsigned Alignment,
1491  unsigned AddressSpace, bool UseMaskForCond,
1492  bool UseMaskForGaps) override {
1493  return Impl.getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
1494  Alignment, AddressSpace,
1495  UseMaskForCond, UseMaskForGaps);
1496  }
1497  int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
1498  bool IsPairwiseForm) override {
1499  return Impl.getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
1500  }
1501  int getMinMaxReductionCost(Type *Ty, Type *CondTy,
1502  bool IsPairwiseForm, bool IsUnsigned) override {
1503  return Impl.getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
1504  }
1505  int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy, ArrayRef<Type *> Tys,
1506  FastMathFlags FMF, unsigned ScalarizationCostPassed) override {
1507  return Impl.getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
1508  ScalarizationCostPassed);
1509  }
1510  int getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
1511  ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) override {
1512  return Impl.getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
1513  }
1514  int getCallInstrCost(Function *F, Type *RetTy,
1515  ArrayRef<Type *> Tys) override {
1516  return Impl.getCallInstrCost(F, RetTy, Tys);
1517  }
1518  unsigned getNumberOfParts(Type *Tp) override {
1519  return Impl.getNumberOfParts(Tp);
1520  }
1521  int getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
1522  const SCEV *Ptr) override {
1523  return Impl.getAddressComputationCost(Ty, SE, Ptr);
1524  }
1525  unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) override {
1526  return Impl.getCostOfKeepingLiveOverCall(Tys);
1527  }
1528  bool getTgtMemIntrinsic(IntrinsicInst *Inst,
1529  MemIntrinsicInfo &Info) override {
1530  return Impl.getTgtMemIntrinsic(Inst, Info);
1531  }
1532  unsigned getAtomicMemIntrinsicMaxElementSize() const override {
1533  return Impl.getAtomicMemIntrinsicMaxElementSize();
1534  }
1535  Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
1536  Type *ExpectedType) override {
1537  return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1538  }
1539  Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
1540  unsigned SrcAlign,
1541  unsigned DestAlign) const override {
1542  return Impl.getMemcpyLoopLoweringType(Context, Length, SrcAlign, DestAlign);
1543  }
1544  void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
1545  LLVMContext &Context,
1546  unsigned RemainingBytes,
1547  unsigned SrcAlign,
1548  unsigned DestAlign) const override {
1549  Impl.getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
1550  SrcAlign, DestAlign);
1551  }
1552  bool areInlineCompatible(const Function *Caller,
1553  const Function *Callee) const override {
1554  return Impl.areInlineCompatible(Caller, Callee);
1555  }
1556  bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override {
1557  return Impl.isIndexedLoadLegal(Mode, Ty, getDataLayout());
1558  }
1559  bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override {
1560  return Impl.isIndexedStoreLegal(Mode, Ty, getDataLayout());
1561  }
1562  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override {
1563  return Impl.getLoadStoreVecRegBitWidth(AddrSpace);
1564  }
1565  bool isLegalToVectorizeLoad(LoadInst *LI) const override {
1566  return Impl.isLegalToVectorizeLoad(LI);
1567  }
1568  bool isLegalToVectorizeStore(StoreInst *SI) const override {
1569  return Impl.isLegalToVectorizeStore(SI);
1570  }
1571  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
1572  unsigned Alignment,
1573  unsigned AddrSpace) const override {
1574  return Impl.isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1575  AddrSpace);
1576  }
1577  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
1578  unsigned Alignment,
1579  unsigned AddrSpace) const override {
1580  return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1581  AddrSpace);
1582  }
1583  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1584  unsigned ChainSizeInBytes,
1585  VectorType *VecTy) const override {
1586  return Impl.getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1587  }
1588  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1589  unsigned ChainSizeInBytes,
1590  VectorType *VecTy) const override {
1591  return Impl.getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1592  }
1593  bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
1594  ReductionFlags Flags) const override {
1595  return Impl.useReductionIntrinsic(Opcode, Ty, Flags);
1596  }
1597  bool shouldExpandReduction(const IntrinsicInst *II) const override {
1598  return Impl.shouldExpandReduction(II);
1599  }
1600  int getInstructionLatency(const Instruction *I) override {
1601  return Impl.getInstructionLatency(I);
1602  }
1603 };
1604 
1605 template <typename T>
1607  : TTIImpl(new Model<T>(Impl)) {}
1608 
1609 /// Analysis pass providing the \c TargetTransformInfo.
1610 ///
1611 /// The core idea of the TargetIRAnalysis is to expose an interface through
1612 /// which LLVM targets can analyze and provide information about the middle
1613 /// end's target-independent IR. This supports use cases such as target-aware
1614 /// cost modeling of IR constructs.
1615 ///
1616 /// This is a function analysis because much of the cost modeling for targets
1617 /// is done in a subtarget specific way and LLVM supports compiling different
1618 /// functions targeting different subtargets in order to support runtime
1619 /// dispatch according to the observed subtarget.
1620 class TargetIRAnalysis : public AnalysisInfoMixin<TargetIRAnalysis> {
1621 public:
1623 
1624  /// Default construct a target IR analysis.
1625  ///
1626  /// This will use the module's datalayout to construct a baseline
1627  /// conservative TTI result.
1628  TargetIRAnalysis();
1629 
1630  /// Construct an IR analysis pass around a target-provide callback.
1631  ///
1632  /// The callback will be called with a particular function for which the TTI
1633  /// is needed and must return a TTI object for that function.
1634  TargetIRAnalysis(std::function<Result(const Function &)> TTICallback);
1635 
1636  // Value semantics. We spell out the constructors for MSVC.
1638  : TTICallback(Arg.TTICallback) {}
1640  : TTICallback(std::move(Arg.TTICallback)) {}
1642  TTICallback = RHS.TTICallback;
1643  return *this;
1644  }
1646  TTICallback = std::move(RHS.TTICallback);
1647  return *this;
1648  }
1649 
1650  Result run(const Function &F, FunctionAnalysisManager &);
1651 
1652 private:
1654  static AnalysisKey Key;
1655 
1656  /// The callback used to produce a result.
1657  ///
1658  /// We use a completely opaque callback so that targets can provide whatever
1659  /// mechanism they desire for constructing the TTI for a given function.
1660  ///
1661  /// FIXME: Should we really use std::function? It's relatively inefficient.
1662  /// It might be possible to arrange for even stateful callbacks to outlive
1663  /// the analysis and thus use a function_ref which would be lighter weight.
1664  /// This may also be less error prone as the callback is likely to reference
1665  /// the external TargetMachine, and that reference needs to never dangle.
1666  std::function<Result(const Function &)> TTICallback;
1667 
1668  /// Helper function used as the callback in the default constructor.
1669  static Result getDefaultTTI(const Function &F);
1670 };
1671 
1672 /// Wrapper pass for TargetTransformInfo.
1673 ///
1674 /// This pass can be constructed from a TTI object which it stores internally
1675 /// and is queried by passes.
1677  TargetIRAnalysis TIRA;
1679 
1680  virtual void anchor();
1681 
1682 public:
1683  static char ID;
1684 
1685  /// We must provide a default constructor for the pass but it should
1686  /// never be used.
1687  ///
1688  /// Use the constructor below or call one of the creation routines.
1690 
1692 
1693  TargetTransformInfo &getTTI(const Function &F);
1694 };
1695 
1696 /// Create an analysis pass wrapper around a TTI object.
1697 ///
1698 /// This analysis pass just holds the TTI instance and makes it available to
1699 /// clients.
1701 
1702 } // End llvm namespace
1703 
1704 #endif
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
LLVMContext & Context
Atomic ordering constants.
SI Whole Quad Mode
This class represents lattice values for constants.
Definition: AllocatorList.h:24
constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
TargetIRAnalysis & operator=(const TargetIRAnalysis &RHS)
static unsigned getScalarizationOverhead(Instruction *I, unsigned VF, const TargetTransformInfo &TTI)
Estimate the overhead of scalarizing an instruction.
value_op_iterator value_op_begin()
Definition: User.h:256
The main scalar evolution driver.
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold, but used for partial/runtime unrolling (set to UINT_MAX to disable).
MemIndexedMode
The type of load/store indexing.
unsigned PartialThreshold
The cost threshold for the unrolled loop, like Threshold, but used for partial/runtime unrolling (set...
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Analysis pass providing the TargetTransformInfo.
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
value_op_iterator value_op_end()
Definition: User.h:259
F(f)
An instruction for reading from memory.
Definition: Instructions.h:168
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
TargetIRAnalysis & operator=(TargetIRAnalysis &&RHS)
bool areInlineCompatible(const Function &Caller, const Function &Callee)
int getInstructionCost(const Instruction *I, enum TargetCostKind kind) const
Query the cost of a specified instruction.
Definition: BitVector.h:938
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool AllowPeeling
Allow peeling off loop iterations for loops with low dynamic tripcount.
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
unsigned FullUnrollMaxCount
Set the maximum unrolling factor for full unrolling.
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
Key
PAL metadata keys.
Class to represent function types.
Definition: DerivedTypes.h:103
PopcntSupportKind
Flags indicating the kind of support for population count.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
An instruction for storing to memory.
Definition: Instructions.h:310
Reverse the order of the vector.
amdgpu Simplify well known AMD library false Value * Callee
bool AllowRemainder
Allow generation of a loop remainder (extra iterations after unroll).
ExtractSubvector Index indicates start offset.
If not nullptr, enable inline expansion of memcmp.
Wrapper pass for TargetTransformInfo.
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:154
Flags describing the kind of vector reduction.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
This is an important base class in LLVM.
Definition: Constant.h:42
A CRTP mix-in that provides informational APIs needed for analysis passes.
Definition: PassManager.h:383
AMDGPU Lower Kernel Arguments
unsigned Count
A forced unrolling factor (the number of concatenated bodies of the original loop in the unrolled loo...
TargetIRAnalysis(const TargetIRAnalysis &Arg)
bool IsMaxOp
If the op a min/max kind, true if it&#39;s a max operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
OperandValueProperties
Additional properties of an operand&#39;s values.
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:256
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
AddressSpace
Definition: NVPTXBaseInfo.h:22
unsigned DefaultUnrollRuntimeCount
Default unroll count for loops with run-time trip count.
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:70
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
amdgpu Simplify well known AMD library false Value Value * Arg
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
unsigned Threshold
The cost threshold for the unrolled loop.
This class represents an analyzed expression in the program.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:459
Parameters that control the generic loop unrolling transformation.
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable)...
TargetIRAnalysis(TargetIRAnalysis &&Arg)
#define I(x, y, z)
Definition: MD5.cpp:58
TargetCostConstants
Underlying constants for &#39;cost&#39; values in this interface.
int getUserCost(const User *U) const
This is a helper function which calls the two-argument getUserCost with Operands which are the curren...
InsertSubvector. Index indicates start offset.
unsigned Insns
TODO: Some of these could be merged.
API to communicate dependencies between analyses during invalidation.
Definition: PassManager.h:642
const unsigned Kind
Multiway switch.
TargetTransformInfo Result
LLVM Value Representation.
Definition: Value.h:73
unsigned MaxPercentThresholdBoost
If complete unrolling will reduce the cost of the loop, we will boost the Threshold by a certain perc...
Broadcast element 0 to all other elements.
bool invalidate(Function &, const PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
Handle the invalidation of this information.
bool UpperBound
Allow using trip count upper bound to unroll loops.
print Print MemDeps of function
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:160
OperandValueKind
Additional information about an operand&#39;s possible values.
A container for analyses that lazily runs them and caches their results.
TargetCostKind
The kind of cost model.
CacheLevel
The possible cache levels.
This header defines various interfaces for pass management in LLVM.
Information about a load/store intrinsic defined by the target.
bool NoNaN
If op is an fp min/max, whether NaNs may be present.
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:71
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
ShuffleKind
The various kinds of shuffle patterns for vector queries.
bool IsSigned
Whether the operation is a signed int reduction.