LLVM  9.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63 
64 using namespace llvm;
65 
67  "jump-is-expensive", cl::init(false),
68  cl::desc("Do not create extra branches to split comparison logic."),
69  cl::Hidden);
70 
72  ("min-jump-table-entries", cl::init(4), cl::Hidden,
73  cl::desc("Set minimum number of entries to use a jump table."));
74 
76  ("max-jump-table-size", cl::init(0), cl::Hidden,
77  cl::desc("Set maximum size of jump tables; zero for no limit."));
78 
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82  cl::desc("Minimum density for building a jump table in "
83  "a normal function"));
84 
85 /// Minimum jump table density for -Os or -Oz functions.
87  "optsize-jump-table-density", cl::init(40), cl::Hidden,
88  cl::desc("Minimum density for building a jump table in "
89  "an optsize function"));
90 
91 static bool darwinHasSinCos(const Triple &TT) {
92  assert(TT.isOSDarwin() && "should be called with darwin triple");
93  // Don't bother with 32 bit x86.
94  if (TT.getArch() == Triple::x86)
95  return false;
96  // Macos < 10.9 has no sincos_stret.
97  if (TT.isMacOSX())
98  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99  // iOS < 7.0 has no sincos_stret.
100  if (TT.isiOS())
101  return !TT.isOSVersionLT(7, 0);
102  // Any other darwin such as WatchOS/TvOS is new enough.
103  return true;
104 }
105 
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
112  "min-predictable-branch", cl::init(99),
113  cl::desc("Minimum percentage (0-100) that a condition must be either true "
114  "or false to assume that the condition is predictable"),
115  cl::Hidden);
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // A few names are different on particular architectures or environments.
127  if (TT.isOSDarwin()) {
128  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
129  // of the gnueabi-style __gnu_*_ieee.
130  // FIXME: What about other targets?
131  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
132  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
133 
134  // Some darwins have an optimized __bzero/bzero function.
135  switch (TT.getArch()) {
136  case Triple::x86:
137  case Triple::x86_64:
138  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
139  setLibcallName(RTLIB::BZERO, "__bzero");
140  break;
141  case Triple::aarch64:
142  setLibcallName(RTLIB::BZERO, "bzero");
143  break;
144  default:
145  break;
146  }
147 
148  if (darwinHasSinCos(TT)) {
149  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
150  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
151  if (TT.isWatchABI()) {
152  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
154  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
156  }
157  }
158  } else {
159  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
160  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
161  }
162 
163  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
164  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
165  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
166  setLibcallName(RTLIB::SINCOS_F64, "sincos");
167  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
168  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
169  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
170  }
171 
172  if (TT.isOSOpenBSD()) {
173  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
174  }
175 }
176 
177 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
178 /// UNKNOWN_LIBCALL if there is none.
180  if (OpVT == MVT::f16) {
181  if (RetVT == MVT::f32)
182  return FPEXT_F16_F32;
183  } else if (OpVT == MVT::f32) {
184  if (RetVT == MVT::f64)
185  return FPEXT_F32_F64;
186  if (RetVT == MVT::f128)
187  return FPEXT_F32_F128;
188  if (RetVT == MVT::ppcf128)
189  return FPEXT_F32_PPCF128;
190  } else if (OpVT == MVT::f64) {
191  if (RetVT == MVT::f128)
192  return FPEXT_F64_F128;
193  else if (RetVT == MVT::ppcf128)
194  return FPEXT_F64_PPCF128;
195  } else if (OpVT == MVT::f80) {
196  if (RetVT == MVT::f128)
197  return FPEXT_F80_F128;
198  }
199 
200  return UNKNOWN_LIBCALL;
201 }
202 
203 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
204 /// UNKNOWN_LIBCALL if there is none.
206  if (RetVT == MVT::f16) {
207  if (OpVT == MVT::f32)
208  return FPROUND_F32_F16;
209  if (OpVT == MVT::f64)
210  return FPROUND_F64_F16;
211  if (OpVT == MVT::f80)
212  return FPROUND_F80_F16;
213  if (OpVT == MVT::f128)
214  return FPROUND_F128_F16;
215  if (OpVT == MVT::ppcf128)
216  return FPROUND_PPCF128_F16;
217  } else if (RetVT == MVT::f32) {
218  if (OpVT == MVT::f64)
219  return FPROUND_F64_F32;
220  if (OpVT == MVT::f80)
221  return FPROUND_F80_F32;
222  if (OpVT == MVT::f128)
223  return FPROUND_F128_F32;
224  if (OpVT == MVT::ppcf128)
225  return FPROUND_PPCF128_F32;
226  } else if (RetVT == MVT::f64) {
227  if (OpVT == MVT::f80)
228  return FPROUND_F80_F64;
229  if (OpVT == MVT::f128)
230  return FPROUND_F128_F64;
231  if (OpVT == MVT::ppcf128)
232  return FPROUND_PPCF128_F64;
233  } else if (RetVT == MVT::f80) {
234  if (OpVT == MVT::f128)
235  return FPROUND_F128_F80;
236  }
237 
238  return UNKNOWN_LIBCALL;
239 }
240 
241 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
242 /// UNKNOWN_LIBCALL if there is none.
244  if (OpVT == MVT::f32) {
245  if (RetVT == MVT::i32)
246  return FPTOSINT_F32_I32;
247  if (RetVT == MVT::i64)
248  return FPTOSINT_F32_I64;
249  if (RetVT == MVT::i128)
250  return FPTOSINT_F32_I128;
251  } else if (OpVT == MVT::f64) {
252  if (RetVT == MVT::i32)
253  return FPTOSINT_F64_I32;
254  if (RetVT == MVT::i64)
255  return FPTOSINT_F64_I64;
256  if (RetVT == MVT::i128)
257  return FPTOSINT_F64_I128;
258  } else if (OpVT == MVT::f80) {
259  if (RetVT == MVT::i32)
260  return FPTOSINT_F80_I32;
261  if (RetVT == MVT::i64)
262  return FPTOSINT_F80_I64;
263  if (RetVT == MVT::i128)
264  return FPTOSINT_F80_I128;
265  } else if (OpVT == MVT::f128) {
266  if (RetVT == MVT::i32)
267  return FPTOSINT_F128_I32;
268  if (RetVT == MVT::i64)
269  return FPTOSINT_F128_I64;
270  if (RetVT == MVT::i128)
271  return FPTOSINT_F128_I128;
272  } else if (OpVT == MVT::ppcf128) {
273  if (RetVT == MVT::i32)
274  return FPTOSINT_PPCF128_I32;
275  if (RetVT == MVT::i64)
276  return FPTOSINT_PPCF128_I64;
277  if (RetVT == MVT::i128)
278  return FPTOSINT_PPCF128_I128;
279  }
280  return UNKNOWN_LIBCALL;
281 }
282 
283 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
284 /// UNKNOWN_LIBCALL if there is none.
286  if (OpVT == MVT::f32) {
287  if (RetVT == MVT::i32)
288  return FPTOUINT_F32_I32;
289  if (RetVT == MVT::i64)
290  return FPTOUINT_F32_I64;
291  if (RetVT == MVT::i128)
292  return FPTOUINT_F32_I128;
293  } else if (OpVT == MVT::f64) {
294  if (RetVT == MVT::i32)
295  return FPTOUINT_F64_I32;
296  if (RetVT == MVT::i64)
297  return FPTOUINT_F64_I64;
298  if (RetVT == MVT::i128)
299  return FPTOUINT_F64_I128;
300  } else if (OpVT == MVT::f80) {
301  if (RetVT == MVT::i32)
302  return FPTOUINT_F80_I32;
303  if (RetVT == MVT::i64)
304  return FPTOUINT_F80_I64;
305  if (RetVT == MVT::i128)
306  return FPTOUINT_F80_I128;
307  } else if (OpVT == MVT::f128) {
308  if (RetVT == MVT::i32)
309  return FPTOUINT_F128_I32;
310  if (RetVT == MVT::i64)
311  return FPTOUINT_F128_I64;
312  if (RetVT == MVT::i128)
313  return FPTOUINT_F128_I128;
314  } else if (OpVT == MVT::ppcf128) {
315  if (RetVT == MVT::i32)
316  return FPTOUINT_PPCF128_I32;
317  if (RetVT == MVT::i64)
318  return FPTOUINT_PPCF128_I64;
319  if (RetVT == MVT::i128)
320  return FPTOUINT_PPCF128_I128;
321  }
322  return UNKNOWN_LIBCALL;
323 }
324 
325 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
326 /// UNKNOWN_LIBCALL if there is none.
328  if (OpVT == MVT::i32) {
329  if (RetVT == MVT::f32)
330  return SINTTOFP_I32_F32;
331  if (RetVT == MVT::f64)
332  return SINTTOFP_I32_F64;
333  if (RetVT == MVT::f80)
334  return SINTTOFP_I32_F80;
335  if (RetVT == MVT::f128)
336  return SINTTOFP_I32_F128;
337  if (RetVT == MVT::ppcf128)
338  return SINTTOFP_I32_PPCF128;
339  } else if (OpVT == MVT::i64) {
340  if (RetVT == MVT::f32)
341  return SINTTOFP_I64_F32;
342  if (RetVT == MVT::f64)
343  return SINTTOFP_I64_F64;
344  if (RetVT == MVT::f80)
345  return SINTTOFP_I64_F80;
346  if (RetVT == MVT::f128)
347  return SINTTOFP_I64_F128;
348  if (RetVT == MVT::ppcf128)
349  return SINTTOFP_I64_PPCF128;
350  } else if (OpVT == MVT::i128) {
351  if (RetVT == MVT::f32)
352  return SINTTOFP_I128_F32;
353  if (RetVT == MVT::f64)
354  return SINTTOFP_I128_F64;
355  if (RetVT == MVT::f80)
356  return SINTTOFP_I128_F80;
357  if (RetVT == MVT::f128)
358  return SINTTOFP_I128_F128;
359  if (RetVT == MVT::ppcf128)
360  return SINTTOFP_I128_PPCF128;
361  }
362  return UNKNOWN_LIBCALL;
363 }
364 
365 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
366 /// UNKNOWN_LIBCALL if there is none.
368  if (OpVT == MVT::i32) {
369  if (RetVT == MVT::f32)
370  return UINTTOFP_I32_F32;
371  if (RetVT == MVT::f64)
372  return UINTTOFP_I32_F64;
373  if (RetVT == MVT::f80)
374  return UINTTOFP_I32_F80;
375  if (RetVT == MVT::f128)
376  return UINTTOFP_I32_F128;
377  if (RetVT == MVT::ppcf128)
378  return UINTTOFP_I32_PPCF128;
379  } else if (OpVT == MVT::i64) {
380  if (RetVT == MVT::f32)
381  return UINTTOFP_I64_F32;
382  if (RetVT == MVT::f64)
383  return UINTTOFP_I64_F64;
384  if (RetVT == MVT::f80)
385  return UINTTOFP_I64_F80;
386  if (RetVT == MVT::f128)
387  return UINTTOFP_I64_F128;
388  if (RetVT == MVT::ppcf128)
389  return UINTTOFP_I64_PPCF128;
390  } else if (OpVT == MVT::i128) {
391  if (RetVT == MVT::f32)
392  return UINTTOFP_I128_F32;
393  if (RetVT == MVT::f64)
394  return UINTTOFP_I128_F64;
395  if (RetVT == MVT::f80)
396  return UINTTOFP_I128_F80;
397  if (RetVT == MVT::f128)
398  return UINTTOFP_I128_F128;
399  if (RetVT == MVT::ppcf128)
400  return UINTTOFP_I128_PPCF128;
401  }
402  return UNKNOWN_LIBCALL;
403 }
404 
405 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
406 #define OP_TO_LIBCALL(Name, Enum) \
407  case Name: \
408  switch (VT.SimpleTy) { \
409  default: \
410  return UNKNOWN_LIBCALL; \
411  case MVT::i8: \
412  return Enum##_1; \
413  case MVT::i16: \
414  return Enum##_2; \
415  case MVT::i32: \
416  return Enum##_4; \
417  case MVT::i64: \
418  return Enum##_8; \
419  case MVT::i128: \
420  return Enum##_16; \
421  }
422 
423  switch (Opc) {
424  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
425  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
426  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
427  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
428  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
429  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
430  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
431  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
432  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
433  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
434  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
435  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
436  }
437 
438 #undef OP_TO_LIBCALL
439 
440  return UNKNOWN_LIBCALL;
441 }
442 
444  switch (ElementSize) {
445  case 1:
446  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
447  case 2:
448  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
449  case 4:
450  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
451  case 8:
452  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
453  case 16:
454  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
455  default:
456  return UNKNOWN_LIBCALL;
457  }
458 }
459 
461  switch (ElementSize) {
462  case 1:
463  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
464  case 2:
465  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
466  case 4:
467  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
468  case 8:
469  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
470  case 16:
471  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
472  default:
473  return UNKNOWN_LIBCALL;
474  }
475 }
476 
478  switch (ElementSize) {
479  case 1:
480  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
481  case 2:
482  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
483  case 4:
484  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
485  case 8:
486  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
487  case 16:
488  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
489  default:
490  return UNKNOWN_LIBCALL;
491  }
492 }
493 
494 /// InitCmpLibcallCCs - Set default comparison libcall CC.
495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
500  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
501  CCs[RTLIB::UNE_F32] = ISD::SETNE;
502  CCs[RTLIB::UNE_F64] = ISD::SETNE;
503  CCs[RTLIB::UNE_F128] = ISD::SETNE;
504  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
505  CCs[RTLIB::OGE_F32] = ISD::SETGE;
506  CCs[RTLIB::OGE_F64] = ISD::SETGE;
507  CCs[RTLIB::OGE_F128] = ISD::SETGE;
508  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
509  CCs[RTLIB::OLT_F32] = ISD::SETLT;
510  CCs[RTLIB::OLT_F64] = ISD::SETLT;
511  CCs[RTLIB::OLT_F128] = ISD::SETLT;
512  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
513  CCs[RTLIB::OLE_F32] = ISD::SETLE;
514  CCs[RTLIB::OLE_F64] = ISD::SETLE;
515  CCs[RTLIB::OLE_F128] = ISD::SETLE;
516  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
517  CCs[RTLIB::OGT_F32] = ISD::SETGT;
518  CCs[RTLIB::OGT_F64] = ISD::SETGT;
519  CCs[RTLIB::OGT_F128] = ISD::SETGT;
520  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
521  CCs[RTLIB::UO_F32] = ISD::SETNE;
522  CCs[RTLIB::UO_F64] = ISD::SETNE;
523  CCs[RTLIB::UO_F128] = ISD::SETNE;
524  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
525  CCs[RTLIB::O_F32] = ISD::SETEQ;
526  CCs[RTLIB::O_F64] = ISD::SETEQ;
527  CCs[RTLIB::O_F128] = ISD::SETEQ;
528  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
529 }
530 
531 /// NOTE: The TargetMachine owns TLOF.
533  initActions();
534 
535  // Perform these initializations only once.
537  MaxLoadsPerMemcmp = 8;
541  UseUnderscoreSetJmp = false;
542  UseUnderscoreLongJmp = false;
543  HasMultipleConditionRegisters = false;
544  HasExtractBitsInsn = false;
545  JumpIsExpensive = JumpIsExpensiveOverride;
547  EnableExtLdPromotion = false;
548  HasFloatingPointExceptions = true;
549  StackPointerRegisterToSaveRestore = 0;
550  BooleanContents = UndefinedBooleanContent;
551  BooleanFloatContents = UndefinedBooleanContent;
552  BooleanVectorContents = UndefinedBooleanContent;
553  SchedPreferenceInfo = Sched::ILP;
554  JumpBufSize = 0;
555  JumpBufAlignment = 0;
556  MinFunctionAlignment = 0;
557  PrefFunctionAlignment = 0;
558  PrefLoopAlignment = 0;
560  MinStackArgumentAlignment = 1;
561  // TODO: the default will be switched to 0 in the next commit, along
562  // with the Target-specific changes necessary.
563  MaxAtomicSizeInBitsSupported = 1024;
564 
565  MinCmpXchgSizeInBits = 0;
566  SupportsUnalignedAtomics = false;
567 
568  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
569 
570  InitLibcalls(TM.getTargetTriple());
571  InitCmpLibcallCCs(CmpLibcallCCs);
572 }
573 
575  // All operations default to being supported.
576  memset(OpActions, 0, sizeof(OpActions));
577  memset(LoadExtActions, 0, sizeof(LoadExtActions));
578  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
579  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
580  memset(CondCodeActions, 0, sizeof(CondCodeActions));
581  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
582  std::fill(std::begin(TargetDAGCombineArray),
583  std::end(TargetDAGCombineArray), 0);
584 
585  for (MVT VT : MVT::fp_valuetypes()) {
586  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
587  if (IntVT.isValid()) {
590  }
591  }
592 
593  // Set default actions for various operations.
594  for (MVT VT : MVT::all_valuetypes()) {
595  // Default all indexed load / store to expand.
596  for (unsigned IM = (unsigned)ISD::PRE_INC;
597  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
598  setIndexedLoadAction(IM, VT, Expand);
599  setIndexedStoreAction(IM, VT, Expand);
600  }
601 
602  // Most backends expect to see the node which just returns the value loaded.
604 
605  // These operations default to expand.
628 
629  // Overflow operations default to expand
636 
637  // ADDCARRY operations default to expand
641 
642  // ADDC/ADDE/SUBC/SUBE default to expand.
647 
648  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
651 
653 
654  // These library functions default to expand.
657 
658  // These operations default to expand for vector types.
659  if (VT.isVector()) {
664  }
665 
666  // For most targets @llvm.get.dynamic.area.offset just returns 0.
668  }
669 
670  // Most targets ignore the @llvm.prefetch intrinsic.
672 
673  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
675 
676  // ConstantFP nodes default to expand. Targets can either change this to
677  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
678  // to optimize expansions for certain constants.
684 
685  // These library functions default to expand.
686  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
699  }
700 
701  // Default ISD::TRAP to expand (which turns it into abort).
703 
704  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
705  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
707 }
708 
710  EVT) const {
711  return MVT::getIntegerVT(8 * DL.getPointerSize(0));
712 }
713 
715  bool LegalTypes) const {
716  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
717  if (LHSTy.isVector())
718  return LHSTy;
719  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
720  : getPointerTy(DL);
721 }
722 
723 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
724  assert(isTypeLegal(VT));
725  switch (Op) {
726  default:
727  return false;
728  case ISD::SDIV:
729  case ISD::UDIV:
730  case ISD::SREM:
731  case ISD::UREM:
732  return true;
733  }
734 }
735 
737  // If the command-line option was specified, ignore this request.
738  if (!JumpIsExpensiveOverride.getNumOccurrences())
739  JumpIsExpensive = isExpensive;
740 }
741 
743 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
744  // If this is a simple type, use the ComputeRegisterProp mechanism.
745  if (VT.isSimple()) {
746  MVT SVT = VT.getSimpleVT();
747  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
748  MVT NVT = TransformToType[SVT.SimpleTy];
750 
751  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
753  "Promote may not follow Expand or Promote");
754 
755  if (LA == TypeSplitVector)
756  return LegalizeKind(LA,
757  EVT::getVectorVT(Context, SVT.getVectorElementType(),
758  SVT.getVectorNumElements() / 2));
759  if (LA == TypeScalarizeVector)
760  return LegalizeKind(LA, SVT.getVectorElementType());
761  return LegalizeKind(LA, NVT);
762  }
763 
764  // Handle Extended Scalar Types.
765  if (!VT.isVector()) {
766  assert(VT.isInteger() && "Float types must be simple");
767  unsigned BitSize = VT.getSizeInBits();
768  // First promote to a power-of-two size, then expand if necessary.
769  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
770  EVT NVT = VT.getRoundIntegerType(Context);
771  assert(NVT != VT && "Unable to round integer VT");
772  LegalizeKind NextStep = getTypeConversion(Context, NVT);
773  // Avoid multi-step promotion.
774  if (NextStep.first == TypePromoteInteger)
775  return NextStep;
776  // Return rounded integer type.
777  return LegalizeKind(TypePromoteInteger, NVT);
778  }
779 
781  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
782  }
783 
784  // Handle vector types.
785  unsigned NumElts = VT.getVectorNumElements();
786  EVT EltVT = VT.getVectorElementType();
787 
788  // Vectors with only one element are always scalarized.
789  if (NumElts == 1)
790  return LegalizeKind(TypeScalarizeVector, EltVT);
791 
792  // Try to widen vector elements until the element type is a power of two and
793  // promote it to a legal type later on, for example:
794  // <3 x i8> -> <4 x i8> -> <4 x i32>
795  if (EltVT.isInteger()) {
796  // Vectors with a number of elements that is not a power of two are always
797  // widened, for example <3 x i8> -> <4 x i8>.
798  if (!VT.isPow2VectorType()) {
799  NumElts = (unsigned)NextPowerOf2(NumElts);
800  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
801  return LegalizeKind(TypeWidenVector, NVT);
802  }
803 
804  // Examine the element type.
805  LegalizeKind LK = getTypeConversion(Context, EltVT);
806 
807  // If type is to be expanded, split the vector.
808  // <4 x i140> -> <2 x i140>
809  if (LK.first == TypeExpandInteger)
811  EVT::getVectorVT(Context, EltVT, NumElts / 2));
812 
813  // Promote the integer element types until a legal vector type is found
814  // or until the element integer type is too big. If a legal type was not
815  // found, fallback to the usual mechanism of widening/splitting the
816  // vector.
817  EVT OldEltVT = EltVT;
818  while (true) {
819  // Increase the bitwidth of the element to the next pow-of-two
820  // (which is greater than 8 bits).
821  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
822  .getRoundIntegerType(Context);
823 
824  // Stop trying when getting a non-simple element type.
825  // Note that vector elements may be greater than legal vector element
826  // types. Example: X86 XMM registers hold 64bit element on 32bit
827  // systems.
828  if (!EltVT.isSimple())
829  break;
830 
831  // Build a new vector type and check if it is legal.
832  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
833  // Found a legal promoted vector type.
834  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
836  EVT::getVectorVT(Context, EltVT, NumElts));
837  }
838 
839  // Reset the type to the unexpanded type if we did not find a legal vector
840  // type with a promoted vector element type.
841  EltVT = OldEltVT;
842  }
843 
844  // Try to widen the vector until a legal type is found.
845  // If there is no wider legal type, split the vector.
846  while (true) {
847  // Round up to the next power of 2.
848  NumElts = (unsigned)NextPowerOf2(NumElts);
849 
850  // If there is no simple vector type with this many elements then there
851  // cannot be a larger legal vector type. Note that this assumes that
852  // there are no skipped intermediate vector types in the simple types.
853  if (!EltVT.isSimple())
854  break;
855  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
856  if (LargerVector == MVT())
857  break;
858 
859  // If this type is legal then widen the vector.
860  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
861  return LegalizeKind(TypeWidenVector, LargerVector);
862  }
863 
864  // Widen odd vectors to next power of two.
865  if (!VT.isPow2VectorType()) {
866  EVT NVT = VT.getPow2VectorType(Context);
867  return LegalizeKind(TypeWidenVector, NVT);
868  }
869 
870  // Vectors with illegal element types are expanded.
871  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
872  return LegalizeKind(TypeSplitVector, NVT);
873 }
874 
875 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
876  unsigned &NumIntermediates,
877  MVT &RegisterVT,
878  TargetLoweringBase *TLI) {
879  // Figure out the right, legal destination reg to copy into.
880  unsigned NumElts = VT.getVectorNumElements();
881  MVT EltTy = VT.getVectorElementType();
882 
883  unsigned NumVectorRegs = 1;
884 
885  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
886  // could break down into LHS/RHS like LegalizeDAG does.
887  if (!isPowerOf2_32(NumElts)) {
888  NumVectorRegs = NumElts;
889  NumElts = 1;
890  }
891 
892  // Divide the input until we get to a supported size. This will always
893  // end with a scalar if the target doesn't support vectors.
894  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
895  NumElts >>= 1;
896  NumVectorRegs <<= 1;
897  }
898 
899  NumIntermediates = NumVectorRegs;
900 
901  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
902  if (!TLI->isTypeLegal(NewVT))
903  NewVT = EltTy;
904  IntermediateVT = NewVT;
905 
906  unsigned NewVTSize = NewVT.getSizeInBits();
907 
908  // Convert sizes such as i33 to i64.
909  if (!isPowerOf2_32(NewVTSize))
910  NewVTSize = NextPowerOf2(NewVTSize);
911 
912  MVT DestVT = TLI->getRegisterType(NewVT);
913  RegisterVT = DestVT;
914  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
915  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
916 
917  // Otherwise, promotion or legal types use the same number of registers as
918  // the vector decimated to the appropriate level.
919  return NumVectorRegs;
920 }
921 
922 /// isLegalRC - Return true if the value types that can be represented by the
923 /// specified register class are all legal.
925  const TargetRegisterClass &RC) const {
926  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
927  if (isTypeLegal(*I))
928  return true;
929  return false;
930 }
931 
932 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
933 /// sequence of memory operands that is recognized by PrologEpilogInserter.
936  MachineBasicBlock *MBB) const {
937  MachineInstr *MI = &InitialMI;
938  MachineFunction &MF = *MI->getMF();
939  MachineFrameInfo &MFI = MF.getFrameInfo();
940 
941  // We're handling multiple types of operands here:
942  // PATCHPOINT MetaArgs - live-in, read only, direct
943  // STATEPOINT Deopt Spill - live-through, read only, indirect
944  // STATEPOINT Deopt Alloca - live-through, read only, direct
945  // (We're currently conservative and mark the deopt slots read/write in
946  // practice.)
947  // STATEPOINT GC Spill - live-through, read/write, indirect
948  // STATEPOINT GC Alloca - live-through, read/write, direct
949  // The live-in vs live-through is handled already (the live through ones are
950  // all stack slots), but we need to handle the different type of stackmap
951  // operands and memory effects here.
952 
953  // MI changes inside this loop as we grow operands.
954  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
955  MachineOperand &MO = MI->getOperand(OperIdx);
956  if (!MO.isFI())
957  continue;
958 
959  // foldMemoryOperand builds a new MI after replacing a single FI operand
960  // with the canonical set of five x86 addressing-mode operands.
961  int FI = MO.getIndex();
962  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
963 
964  // Copy operands before the frame-index.
965  for (unsigned i = 0; i < OperIdx; ++i)
966  MIB.add(MI->getOperand(i));
967  // Add frame index operands recognized by stackmaps.cpp
968  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
969  // indirect-mem-ref tag, size, #FI, offset.
970  // Used for spills inserted by StatepointLowering. This codepath is not
971  // used for patchpoints/stackmaps at all, for these spilling is done via
972  // foldMemoryOperand callback only.
973  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
974  MIB.addImm(StackMaps::IndirectMemRefOp);
975  MIB.addImm(MFI.getObjectSize(FI));
976  MIB.add(MI->getOperand(OperIdx));
977  MIB.addImm(0);
978  } else {
979  // direct-mem-ref tag, #FI, offset.
980  // Used by patchpoint, and direct alloca arguments to statepoints
981  MIB.addImm(StackMaps::DirectMemRefOp);
982  MIB.add(MI->getOperand(OperIdx));
983  MIB.addImm(0);
984  }
985  // Copy the operands after the frame index.
986  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
987  MIB.add(MI->getOperand(i));
988 
989  // Inherit previous memory operands.
990  MIB.cloneMemRefs(*MI);
991  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
992 
993  // Add a new memory operand for this FI.
994  assert(MFI.getObjectOffset(FI) != -1);
995 
996  auto Flags = MachineMemOperand::MOLoad;
997  if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1000  }
1002  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1004  MIB->addMemOperand(MF, MMO);
1005 
1006  // Replace the instruction and update the operand index.
1007  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1008  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1009  MI->eraseFromParent();
1010  MI = MIB;
1011  }
1012  return MBB;
1013 }
1014 
1017  MachineBasicBlock *MBB) const {
1018  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1019  "Called emitXRayCustomEvent on the wrong MI!");
1020  auto &MF = *MI.getMF();
1021  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1022  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1023  MIB.add(MI.getOperand(OpIdx));
1024 
1025  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1026  MI.eraseFromParent();
1027  return MBB;
1028 }
1029 
1032  MachineBasicBlock *MBB) const {
1033  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1034  "Called emitXRayTypedEvent on the wrong MI!");
1035  auto &MF = *MI.getMF();
1036  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1037  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1038  MIB.add(MI.getOperand(OpIdx));
1039 
1040  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1041  MI.eraseFromParent();
1042  return MBB;
1043 }
1044 
1045 /// findRepresentativeClass - Return the largest legal super-reg register class
1046 /// of the register class for the specified type and its associated "cost".
1047 // This function is in TargetLowering because it uses RegClassForVT which would
1048 // need to be moved to TargetRegisterInfo and would necessitate moving
1049 // isTypeLegal over as well - a massive change that would just require
1050 // TargetLowering having a TargetRegisterInfo class member that it would use.
1051 std::pair<const TargetRegisterClass *, uint8_t>
1053  MVT VT) const {
1054  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1055  if (!RC)
1056  return std::make_pair(RC, 0);
1057 
1058  // Compute the set of all super-register classes.
1059  BitVector SuperRegRC(TRI->getNumRegClasses());
1060  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1061  SuperRegRC.setBitsInMask(RCI.getMask());
1062 
1063  // Find the first legal register class with the largest spill size.
1064  const TargetRegisterClass *BestRC = RC;
1065  for (unsigned i : SuperRegRC.set_bits()) {
1066  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1067  // We want the largest possible spill size.
1068  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1069  continue;
1070  if (!isLegalRC(*TRI, *SuperRC))
1071  continue;
1072  BestRC = SuperRC;
1073  }
1074  return std::make_pair(BestRC, 1);
1075 }
1076 
1077 /// computeRegisterProperties - Once all of the register classes are added,
1078 /// this allows us to compute derived properties we expose.
1080  const TargetRegisterInfo *TRI) {
1082  "Too many value types for ValueTypeActions to hold!");
1083 
1084  // Everything defaults to needing one register.
1085  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1086  NumRegistersForVT[i] = 1;
1087  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1088  }
1089  // ...except isVoid, which doesn't need any registers.
1090  NumRegistersForVT[MVT::isVoid] = 0;
1091 
1092  // Find the largest integer register class.
1093  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1094  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1095  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1096 
1097  // Every integer value type larger than this largest register takes twice as
1098  // many registers to represent as the previous ValueType.
1099  for (unsigned ExpandedReg = LargestIntReg + 1;
1100  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1101  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1102  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1103  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1106  }
1107 
1108  // Inspect all of the ValueType's smaller than the largest integer
1109  // register to see which ones need promotion.
1110  unsigned LegalIntReg = LargestIntReg;
1111  for (unsigned IntReg = LargestIntReg - 1;
1112  IntReg >= (unsigned)MVT::i1; --IntReg) {
1113  MVT IVT = (MVT::SimpleValueType)IntReg;
1114  if (isTypeLegal(IVT)) {
1115  LegalIntReg = IntReg;
1116  } else {
1117  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1118  (MVT::SimpleValueType)LegalIntReg;
1120  }
1121  }
1122 
1123  // ppcf128 type is really two f64's.
1124  if (!isTypeLegal(MVT::ppcf128)) {
1125  if (isTypeLegal(MVT::f64)) {
1126  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1127  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1128  TransformToType[MVT::ppcf128] = MVT::f64;
1130  } else {
1131  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1132  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1133  TransformToType[MVT::ppcf128] = MVT::i128;
1135  }
1136  }
1137 
1138  // Decide how to handle f128. If the target does not have native f128 support,
1139  // expand it to i128 and we will be generating soft float library calls.
1140  if (!isTypeLegal(MVT::f128)) {
1141  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1142  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1143  TransformToType[MVT::f128] = MVT::i128;
1145  }
1146 
1147  // Decide how to handle f64. If the target does not have native f64 support,
1148  // expand it to i64 and we will be generating soft float library calls.
1149  if (!isTypeLegal(MVT::f64)) {
1150  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1151  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1152  TransformToType[MVT::f64] = MVT::i64;
1154  }
1155 
1156  // Decide how to handle f32. If the target does not have native f32 support,
1157  // expand it to i32 and we will be generating soft float library calls.
1158  if (!isTypeLegal(MVT::f32)) {
1159  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1160  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1161  TransformToType[MVT::f32] = MVT::i32;
1163  }
1164 
1165  // Decide how to handle f16. If the target does not have native f16 support,
1166  // promote it to f32, because there are no f16 library calls (except for
1167  // conversions).
1168  if (!isTypeLegal(MVT::f16)) {
1169  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1170  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1171  TransformToType[MVT::f16] = MVT::f32;
1173  }
1174 
1175  // Loop over all of the vector value types to see which need transformations.
1176  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1177  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1178  MVT VT = (MVT::SimpleValueType) i;
1179  if (isTypeLegal(VT))
1180  continue;
1181 
1182  MVT EltVT = VT.getVectorElementType();
1183  unsigned NElts = VT.getVectorNumElements();
1184  bool IsLegalWiderType = false;
1185  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1186  switch (PreferredAction) {
1187  case TypePromoteInteger:
1188  // Try to promote the elements of integer vectors. If no legal
1189  // promotion was found, fall through to the widen-vector method.
1190  for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1191  MVT SVT = (MVT::SimpleValueType) nVT;
1192  // Promote vectors of integers to vectors with the same number
1193  // of elements, with a wider element type.
1194  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1195  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1196  TransformToType[i] = SVT;
1197  RegisterTypeForVT[i] = SVT;
1198  NumRegistersForVT[i] = 1;
1200  IsLegalWiderType = true;
1201  break;
1202  }
1203  }
1204  if (IsLegalWiderType)
1205  break;
1207 
1208  case TypeWidenVector:
1209  // Try to widen the vector.
1210  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1211  MVT SVT = (MVT::SimpleValueType) nVT;
1212  if (SVT.getVectorElementType() == EltVT
1213  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1214  TransformToType[i] = SVT;
1215  RegisterTypeForVT[i] = SVT;
1216  NumRegistersForVT[i] = 1;
1218  IsLegalWiderType = true;
1219  break;
1220  }
1221  }
1222  if (IsLegalWiderType)
1223  break;
1225 
1226  case TypeSplitVector:
1227  case TypeScalarizeVector: {
1228  MVT IntermediateVT;
1229  MVT RegisterVT;
1230  unsigned NumIntermediates;
1231  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1232  NumIntermediates, RegisterVT, this);
1233  RegisterTypeForVT[i] = RegisterVT;
1234 
1235  MVT NVT = VT.getPow2VectorType();
1236  if (NVT == VT) {
1237  // Type is already a power of 2. The default action is to split.
1238  TransformToType[i] = MVT::Other;
1239  if (PreferredAction == TypeScalarizeVector)
1241  else if (PreferredAction == TypeSplitVector)
1243  else
1244  // Set type action according to the number of elements.
1246  : TypeSplitVector);
1247  } else {
1248  TransformToType[i] = NVT;
1250  }
1251  break;
1252  }
1253  default:
1254  llvm_unreachable("Unknown vector legalization action!");
1255  }
1256  }
1257 
1258  // Determine the 'representative' register class for each value type.
1259  // An representative register class is the largest (meaning one which is
1260  // not a sub-register class / subreg register class) legal register class for
1261  // a group of value types. For example, on i386, i8, i16, and i32
1262  // representative would be GR32; while on x86_64 it's GR64.
1263  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1264  const TargetRegisterClass* RRC;
1265  uint8_t Cost;
1266  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1267  RepRegClassForVT[i] = RRC;
1268  RepRegClassCostForVT[i] = Cost;
1269  }
1270 }
1271 
1273  EVT VT) const {
1274  assert(!VT.isVector() && "No default SetCC type for vectors!");
1275  return getPointerTy(DL).SimpleTy;
1276 }
1277 
1279  return MVT::i32; // return the default value
1280 }
1281 
1282 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1283 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1284 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1285 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1286 ///
1287 /// This method returns the number of registers needed, and the VT for each
1288 /// register. It also returns the VT and quantity of the intermediate values
1289 /// before they are promoted/expanded.
1291  EVT &IntermediateVT,
1292  unsigned &NumIntermediates,
1293  MVT &RegisterVT) const {
1294  unsigned NumElts = VT.getVectorNumElements();
1295 
1296  // If there is a wider vector type with the same element type as this one,
1297  // or a promoted vector type that has the same number of elements which
1298  // are wider, then we should convert to that legal vector type.
1299  // This handles things like <2 x float> -> <4 x float> and
1300  // <4 x i1> -> <4 x i32>.
1301  LegalizeTypeAction TA = getTypeAction(Context, VT);
1302  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1303  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1304  if (isTypeLegal(RegisterEVT)) {
1305  IntermediateVT = RegisterEVT;
1306  RegisterVT = RegisterEVT.getSimpleVT();
1307  NumIntermediates = 1;
1308  return 1;
1309  }
1310  }
1311 
1312  // Figure out the right, legal destination reg to copy into.
1313  EVT EltTy = VT.getVectorElementType();
1314 
1315  unsigned NumVectorRegs = 1;
1316 
1317  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1318  // could break down into LHS/RHS like LegalizeDAG does.
1319  if (!isPowerOf2_32(NumElts)) {
1320  NumVectorRegs = NumElts;
1321  NumElts = 1;
1322  }
1323 
1324  // Divide the input until we get to a supported size. This will always
1325  // end with a scalar if the target doesn't support vectors.
1326  while (NumElts > 1 && !isTypeLegal(
1327  EVT::getVectorVT(Context, EltTy, NumElts))) {
1328  NumElts >>= 1;
1329  NumVectorRegs <<= 1;
1330  }
1331 
1332  NumIntermediates = NumVectorRegs;
1333 
1334  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1335  if (!isTypeLegal(NewVT))
1336  NewVT = EltTy;
1337  IntermediateVT = NewVT;
1338 
1339  MVT DestVT = getRegisterType(Context, NewVT);
1340  RegisterVT = DestVT;
1341  unsigned NewVTSize = NewVT.getSizeInBits();
1342 
1343  // Convert sizes such as i33 to i64.
1344  if (!isPowerOf2_32(NewVTSize))
1345  NewVTSize = NextPowerOf2(NewVTSize);
1346 
1347  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1348  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1349 
1350  // Otherwise, promotion or legal types use the same number of registers as
1351  // the vector decimated to the appropriate level.
1352  return NumVectorRegs;
1353 }
1354 
1355 /// Get the EVTs and ArgFlags collections that represent the legalized return
1356 /// type of the given function. This does not require a DAG or a return value,
1357 /// and is suitable for use before any DAGs for the function are constructed.
1358 /// TODO: Move this out of TargetLowering.cpp.
1360  AttributeList attr,
1362  const TargetLowering &TLI, const DataLayout &DL) {
1363  SmallVector<EVT, 4> ValueVTs;
1364  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1365  unsigned NumValues = ValueVTs.size();
1366  if (NumValues == 0) return;
1367 
1368  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1369  EVT VT = ValueVTs[j];
1370  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1371 
1372  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1373  ExtendKind = ISD::SIGN_EXTEND;
1374  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1375  ExtendKind = ISD::ZERO_EXTEND;
1376 
1377  // FIXME: C calling convention requires the return type to be promoted to
1378  // at least 32-bit. But this is not necessary for non-C calling
1379  // conventions. The frontend should mark functions whose return values
1380  // require promoting with signext or zeroext attributes.
1381  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1382  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1383  if (VT.bitsLT(MinVT))
1384  VT = MinVT;
1385  }
1386 
1387  unsigned NumParts =
1388  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1389  MVT PartVT =
1390  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1391 
1392  // 'inreg' on function refers to return value
1393  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1394  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1395  Flags.setInReg();
1396 
1397  // Propagate extension type if any
1398  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1399  Flags.setSExt();
1400  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1401  Flags.setZExt();
1402 
1403  for (unsigned i = 0; i < NumParts; ++i)
1404  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1405  }
1406 }
1407 
1408 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1409 /// function arguments in the caller parameter area. This is the actual
1410 /// alignment, not its logarithm.
1412  const DataLayout &DL) const {
1413  return DL.getABITypeAlignment(Ty);
1414 }
1415 
1417  const DataLayout &DL, EVT VT,
1418  unsigned AddrSpace,
1419  unsigned Alignment,
1420  bool *Fast) const {
1421  // Check if the specified alignment is sufficient based on the data layout.
1422  // TODO: While using the data layout works in practice, a better solution
1423  // would be to implement this check directly (make this a virtual function).
1424  // For example, the ABI alignment may change based on software platform while
1425  // this function should only be affected by hardware implementation.
1426  Type *Ty = VT.getTypeForEVT(Context);
1427  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1428  // Assume that an access that meets the ABI-specified alignment is fast.
1429  if (Fast != nullptr)
1430  *Fast = true;
1431  return true;
1432  }
1433 
1434  // This is a misaligned access.
1435  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1436 }
1437 
1439  return BranchProbability(MinPercentageForPredictableBranch, 100);
1440 }
1441 
1442 //===----------------------------------------------------------------------===//
1443 // TargetTransformInfo Helpers
1444 //===----------------------------------------------------------------------===//
1445 
1447  enum InstructionOpcodes {
1448 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1449 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1450 #include "llvm/IR/Instruction.def"
1451  };
1452  switch (static_cast<InstructionOpcodes>(Opcode)) {
1453  case Ret: return 0;
1454  case Br: return 0;
1455  case Switch: return 0;
1456  case IndirectBr: return 0;
1457  case Invoke: return 0;
1458  case CallBr: return 0;
1459  case Resume: return 0;
1460  case Unreachable: return 0;
1461  case CleanupRet: return 0;
1462  case CatchRet: return 0;
1463  case CatchPad: return 0;
1464  case CatchSwitch: return 0;
1465  case CleanupPad: return 0;
1466  case FNeg: return ISD::FNEG;
1467  case Add: return ISD::ADD;
1468  case FAdd: return ISD::FADD;
1469  case Sub: return ISD::SUB;
1470  case FSub: return ISD::FSUB;
1471  case Mul: return ISD::MUL;
1472  case FMul: return ISD::FMUL;
1473  case UDiv: return ISD::UDIV;
1474  case SDiv: return ISD::SDIV;
1475  case FDiv: return ISD::FDIV;
1476  case URem: return ISD::UREM;
1477  case SRem: return ISD::SREM;
1478  case FRem: return ISD::FREM;
1479  case Shl: return ISD::SHL;
1480  case LShr: return ISD::SRL;
1481  case AShr: return ISD::SRA;
1482  case And: return ISD::AND;
1483  case Or: return ISD::OR;
1484  case Xor: return ISD::XOR;
1485  case Alloca: return 0;
1486  case Load: return ISD::LOAD;
1487  case Store: return ISD::STORE;
1488  case GetElementPtr: return 0;
1489  case Fence: return 0;
1490  case AtomicCmpXchg: return 0;
1491  case AtomicRMW: return 0;
1492  case Trunc: return ISD::TRUNCATE;
1493  case ZExt: return ISD::ZERO_EXTEND;
1494  case SExt: return ISD::SIGN_EXTEND;
1495  case FPToUI: return ISD::FP_TO_UINT;
1496  case FPToSI: return ISD::FP_TO_SINT;
1497  case UIToFP: return ISD::UINT_TO_FP;
1498  case SIToFP: return ISD::SINT_TO_FP;
1499  case FPTrunc: return ISD::FP_ROUND;
1500  case FPExt: return ISD::FP_EXTEND;
1501  case PtrToInt: return ISD::BITCAST;
1502  case IntToPtr: return ISD::BITCAST;
1503  case BitCast: return ISD::BITCAST;
1504  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1505  case ICmp: return ISD::SETCC;
1506  case FCmp: return ISD::SETCC;
1507  case PHI: return 0;
1508  case Call: return 0;
1509  case Select: return ISD::SELECT;
1510  case UserOp1: return 0;
1511  case UserOp2: return 0;
1512  case VAArg: return 0;
1513  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1514  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1515  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1516  case ExtractValue: return ISD::MERGE_VALUES;
1517  case InsertValue: return ISD::MERGE_VALUES;
1518  case LandingPad: return 0;
1519  }
1520 
1521  llvm_unreachable("Unknown instruction type encountered!");
1522 }
1523 
1524 std::pair<int, MVT>
1526  Type *Ty) const {
1527  LLVMContext &C = Ty->getContext();
1528  EVT MTy = getValueType(DL, Ty);
1529 
1530  int Cost = 1;
1531  // We keep legalizing the type until we find a legal kind. We assume that
1532  // the only operation that costs anything is the split. After splitting
1533  // we need to handle two types.
1534  while (true) {
1535  LegalizeKind LK = getTypeConversion(C, MTy);
1536 
1537  if (LK.first == TypeLegal)
1538  return std::make_pair(Cost, MTy.getSimpleVT());
1539 
1540  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1541  Cost *= 2;
1542 
1543  // Do not loop with f128 type.
1544  if (MTy == LK.second)
1545  return std::make_pair(Cost, MTy.getSimpleVT());
1546 
1547  // Keep legalizing the type.
1548  MTy = LK.second;
1549  }
1550 }
1551 
1553  bool UseTLS) const {
1554  // compiler-rt provides a variable with a magic name. Targets that do not
1555  // link with compiler-rt may also provide such a variable.
1556  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1557  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1558  auto UnsafeStackPtr =
1559  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1560 
1561  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1562 
1563  if (!UnsafeStackPtr) {
1564  auto TLSModel = UseTLS ?
1567  // The global variable is not defined yet, define it ourselves.
1568  // We use the initial-exec TLS model because we do not support the
1569  // variable living anywhere other than in the main executable.
1570  UnsafeStackPtr = new GlobalVariable(
1571  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1572  UnsafeStackPtrVar, nullptr, TLSModel);
1573  } else {
1574  // The variable exists, check its type and attributes.
1575  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1576  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1577  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1578  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1579  (UseTLS ? "" : "not ") + "be thread-local");
1580  }
1581  return UnsafeStackPtr;
1582 }
1583 
1585  if (!TM.getTargetTriple().isAndroid())
1586  return getDefaultSafeStackPointerLocation(IRB, true);
1587 
1588  // Android provides a libc function to retrieve the address of the current
1589  // thread's unsafe stack pointer.
1590  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1591  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1592  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1593  StackPtrTy->getPointerTo(0));
1594  return IRB.CreateCall(Fn);
1595 }
1596 
1597 //===----------------------------------------------------------------------===//
1598 // Loop Strength Reduction hooks
1599 //===----------------------------------------------------------------------===//
1600 
1601 /// isLegalAddressingMode - Return true if the addressing mode represented
1602 /// by AM is legal for this target, for a load/store of the specified type.
1604  const AddrMode &AM, Type *Ty,
1605  unsigned AS, Instruction *I) const {
1606  // The default implementation of this implements a conservative RISCy, r+r and
1607  // r+i addr mode.
1608 
1609  // Allows a sign-extended 16-bit immediate field.
1610  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1611  return false;
1612 
1613  // No global is ever allowed as a base.
1614  if (AM.BaseGV)
1615  return false;
1616 
1617  // Only support r+r,
1618  switch (AM.Scale) {
1619  case 0: // "r+i" or just "i", depending on HasBaseReg.
1620  break;
1621  case 1:
1622  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1623  return false;
1624  // Otherwise we have r+r or r+i.
1625  break;
1626  case 2:
1627  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1628  return false;
1629  // Allow 2*r as r+r.
1630  break;
1631  default: // Don't allow n * r
1632  return false;
1633  }
1634 
1635  return true;
1636 }
1637 
1638 //===----------------------------------------------------------------------===//
1639 // Stack Protector
1640 //===----------------------------------------------------------------------===//
1641 
1642 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1643 // so that SelectionDAG handle SSP.
1645  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1646  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1648  return M.getOrInsertGlobal("__guard_local", PtrTy);
1649  }
1650  return nullptr;
1651 }
1652 
1653 // Currently only support "standard" __stack_chk_guard.
1654 // TODO: add LOAD_STACK_GUARD support.
1656  if (!M.getNamedValue("__stack_chk_guard"))
1657  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1659  nullptr, "__stack_chk_guard");
1660 }
1661 
1662 // Currently only support "standard" __stack_chk_guard.
1663 // TODO: add LOAD_STACK_GUARD support.
1665  return M.getNamedValue("__stack_chk_guard");
1666 }
1667 
1669  return nullptr;
1670 }
1671 
1673  return MinimumJumpTableEntries;
1674 }
1675 
1678 }
1679 
1680 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1681  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1682 }
1683 
1685  return MaximumJumpTableSize;
1686 }
1687 
1689  MaximumJumpTableSize = Val;
1690 }
1691 
1692 //===----------------------------------------------------------------------===//
1693 // Reciprocal Estimates
1694 //===----------------------------------------------------------------------===//
1695 
1696 /// Get the reciprocal estimate attribute string for a function that will
1697 /// override the target defaults.
1699  const Function &F = MF.getFunction();
1700  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1701 }
1702 
1703 /// Construct a string for the given reciprocal operation of the given type.
1704 /// This string should match the corresponding option to the front-end's
1705 /// "-mrecip" flag assuming those strings have been passed through in an
1706 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1707 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1708  std::string Name = VT.isVector() ? "vec-" : "";
1709 
1710  Name += IsSqrt ? "sqrt" : "div";
1711 
1712  // TODO: Handle "half" or other float types?
1713  if (VT.getScalarType() == MVT::f64) {
1714  Name += "d";
1715  } else {
1716  assert(VT.getScalarType() == MVT::f32 &&
1717  "Unexpected FP type for reciprocal estimate");
1718  Name += "f";
1719  }
1720 
1721  return Name;
1722 }
1723 
1724 /// Return the character position and value (a single numeric character) of a
1725 /// customized refinement operation in the input string if it exists. Return
1726 /// false if there is no customized refinement step count.
1728  uint8_t &Value) {
1729  const char RefStepToken = ':';
1730  Position = In.find(RefStepToken);
1731  if (Position == StringRef::npos)
1732  return false;
1733 
1734  StringRef RefStepString = In.substr(Position + 1);
1735  // Allow exactly one numeric character for the additional refinement
1736  // step parameter.
1737  if (RefStepString.size() == 1) {
1738  char RefStepChar = RefStepString[0];
1739  if (RefStepChar >= '0' && RefStepChar <= '9') {
1740  Value = RefStepChar - '0';
1741  return true;
1742  }
1743  }
1744  report_fatal_error("Invalid refinement step for -recip.");
1745 }
1746 
1747 /// For the input attribute string, return one of the ReciprocalEstimate enum
1748 /// status values (enabled, disabled, or not specified) for this operation on
1749 /// the specified data type.
1750 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1751  if (Override.empty())
1752  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1753 
1754  SmallVector<StringRef, 4> OverrideVector;
1755  Override.split(OverrideVector, ',');
1756  unsigned NumArgs = OverrideVector.size();
1757 
1758  // Check if "all", "none", or "default" was specified.
1759  if (NumArgs == 1) {
1760  // Look for an optional setting of the number of refinement steps needed
1761  // for this type of reciprocal operation.
1762  size_t RefPos;
1763  uint8_t RefSteps;
1764  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1765  // Split the string for further processing.
1766  Override = Override.substr(0, RefPos);
1767  }
1768 
1769  // All reciprocal types are enabled.
1770  if (Override == "all")
1772 
1773  // All reciprocal types are disabled.
1774  if (Override == "none")
1775  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1776 
1777  // Target defaults for enablement are used.
1778  if (Override == "default")
1779  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1780  }
1781 
1782  // The attribute string may omit the size suffix ('f'/'d').
1783  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1784  std::string VTNameNoSize = VTName;
1785  VTNameNoSize.pop_back();
1786  static const char DisabledPrefix = '!';
1787 
1788  for (StringRef RecipType : OverrideVector) {
1789  size_t RefPos;
1790  uint8_t RefSteps;
1791  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1792  RecipType = RecipType.substr(0, RefPos);
1793 
1794  // Ignore the disablement token for string matching.
1795  bool IsDisabled = RecipType[0] == DisabledPrefix;
1796  if (IsDisabled)
1797  RecipType = RecipType.substr(1);
1798 
1799  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1800  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1802  }
1803 
1804  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1805 }
1806 
1807 /// For the input attribute string, return the customized refinement step count
1808 /// for this operation on the specified data type. If the step count does not
1809 /// exist, return the ReciprocalEstimate enum value for unspecified.
1810 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1811  if (Override.empty())
1812  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1813 
1814  SmallVector<StringRef, 4> OverrideVector;
1815  Override.split(OverrideVector, ',');
1816  unsigned NumArgs = OverrideVector.size();
1817 
1818  // Check if "all", "default", or "none" was specified.
1819  if (NumArgs == 1) {
1820  // Look for an optional setting of the number of refinement steps needed
1821  // for this type of reciprocal operation.
1822  size_t RefPos;
1823  uint8_t RefSteps;
1824  if (!parseRefinementStep(Override, RefPos, RefSteps))
1825  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1826 
1827  // Split the string for further processing.
1828  Override = Override.substr(0, RefPos);
1829  assert(Override != "none" &&
1830  "Disabled reciprocals, but specifed refinement steps?");
1831 
1832  // If this is a general override, return the specified number of steps.
1833  if (Override == "all" || Override == "default")
1834  return RefSteps;
1835  }
1836 
1837  // The attribute string may omit the size suffix ('f'/'d').
1838  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1839  std::string VTNameNoSize = VTName;
1840  VTNameNoSize.pop_back();
1841 
1842  for (StringRef RecipType : OverrideVector) {
1843  size_t RefPos;
1844  uint8_t RefSteps;
1845  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1846  continue;
1847 
1848  RecipType = RecipType.substr(0, RefPos);
1849  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1850  return RefSteps;
1851  }
1852 
1853  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1854 }
1855 
1857  MachineFunction &MF) const {
1858  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1859 }
1860 
1862  MachineFunction &MF) const {
1863  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1864 }
1865 
1867  MachineFunction &MF) const {
1868  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1869 }
1870 
1872  MachineFunction &MF) const {
1873  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1874 }
1875 
1877  MF.getRegInfo().freezeReservedRegs(MF);
1878 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:537
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
LLVMContext & Context
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:446
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:606
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:366
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:518
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:164
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:48
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:806
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
bool isOSFuchsia() const
Definition: Triple.h:494
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:507
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
Same for subtraction.
Definition: ISDOpcodes.h:253
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:315
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:365
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:409
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:201
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:243
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:392
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:814
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:120
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:455
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:751
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:496
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:83
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:498
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:102
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
The memory access is volatile.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
bool isOSOpenBSD() const
Definition: Triple.h:486
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:628
bool isWatchABI() const
Definition: Triple.h:469
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:331
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:637
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:771
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:774
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(0), cl::Hidden, cl::desc("Set maximum size of jump tables; zero for no limit."))
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:415
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:800
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:555
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:33
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:639
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:52
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:219
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
The memory access writes data.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:316
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:338
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:450
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:574
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:729
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:601
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
FunctionCallee getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:240
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
ValueTypeActionImpl ValueTypeActions
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:311
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:865
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:204
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
static const size_t npos
Definition: StringRef.h:50
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1268
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:615
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:510
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
Same for multiplication.
Definition: ISDOpcodes.h:256
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:928
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2009
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:431
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:344
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:806
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:72
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:780
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:635
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:305
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:442
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:407
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:464
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:473
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:585
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:241
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...