LLVM  10.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63 
64 using namespace llvm;
65 
67  "jump-is-expensive", cl::init(false),
68  cl::desc("Do not create extra branches to split comparison logic."),
69  cl::Hidden);
70 
72  ("min-jump-table-entries", cl::init(4), cl::Hidden,
73  cl::desc("Set minimum number of entries to use a jump table."));
74 
76  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77  cl::desc("Set maximum size of jump tables."));
78 
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82  cl::desc("Minimum density for building a jump table in "
83  "a normal function"));
84 
85 /// Minimum jump table density for -Os or -Oz functions.
87  "optsize-jump-table-density", cl::init(40), cl::Hidden,
88  cl::desc("Minimum density for building a jump table in "
89  "an optsize function"));
90 
91 static bool darwinHasSinCos(const Triple &TT) {
92  assert(TT.isOSDarwin() && "should be called with darwin triple");
93  // Don't bother with 32 bit x86.
94  if (TT.getArch() == Triple::x86)
95  return false;
96  // Macos < 10.9 has no sincos_stret.
97  if (TT.isMacOSX())
98  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99  // iOS < 7.0 has no sincos_stret.
100  if (TT.isiOS())
101  return !TT.isOSVersionLT(7, 0);
102  // Any other darwin such as WatchOS/TvOS is new enough.
103  return true;
104 }
105 
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
112  "min-predictable-branch", cl::init(99),
113  cl::desc("Minimum percentage (0-100) that a condition must be either true "
114  "or false to assume that the condition is predictable"),
115  cl::Hidden);
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127  if (TT.getArch() == Triple::ppc || TT.isPPC64()) {
128  setLibcallName(RTLIB::ADD_F128, "__addkf3");
129  setLibcallName(RTLIB::SUB_F128, "__subkf3");
130  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131  setLibcallName(RTLIB::DIV_F128, "__divkf3");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
139  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
140  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
141  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
142  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
143  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
144  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
145  setLibcallName(RTLIB::UNE_F128, "__nekf2");
146  setLibcallName(RTLIB::OGE_F128, "__gekf2");
147  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
148  setLibcallName(RTLIB::OLE_F128, "__lekf2");
149  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
150  setLibcallName(RTLIB::UO_F128, "__unordkf2");
151  setLibcallName(RTLIB::O_F128, "__unordkf2");
152  }
153 
154  // A few names are different on particular architectures or environments.
155  if (TT.isOSDarwin()) {
156  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
157  // of the gnueabi-style __gnu_*_ieee.
158  // FIXME: What about other targets?
159  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
160  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
161 
162  // Some darwins have an optimized __bzero/bzero function.
163  switch (TT.getArch()) {
164  case Triple::x86:
165  case Triple::x86_64:
166  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
167  setLibcallName(RTLIB::BZERO, "__bzero");
168  break;
169  case Triple::aarch64:
170  case Triple::aarch64_32:
171  setLibcallName(RTLIB::BZERO, "bzero");
172  break;
173  default:
174  break;
175  }
176 
177  if (darwinHasSinCos(TT)) {
178  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
179  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
180  if (TT.isWatchABI()) {
181  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
183  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
185  }
186  }
187  } else {
188  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
189  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
190  }
191 
192  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
193  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
194  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
195  setLibcallName(RTLIB::SINCOS_F64, "sincos");
196  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
197  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
198  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
199  }
200 
201  if (TT.isPS4CPU()) {
202  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
203  setLibcallName(RTLIB::SINCOS_F64, "sincos");
204  }
205 
206  if (TT.isOSOpenBSD()) {
207  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
208  }
209 }
210 
211 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
212 /// UNKNOWN_LIBCALL if there is none.
214  if (OpVT == MVT::f16) {
215  if (RetVT == MVT::f32)
216  return FPEXT_F16_F32;
217  } else if (OpVT == MVT::f32) {
218  if (RetVT == MVT::f64)
219  return FPEXT_F32_F64;
220  if (RetVT == MVT::f128)
221  return FPEXT_F32_F128;
222  if (RetVT == MVT::ppcf128)
223  return FPEXT_F32_PPCF128;
224  } else if (OpVT == MVT::f64) {
225  if (RetVT == MVT::f128)
226  return FPEXT_F64_F128;
227  else if (RetVT == MVT::ppcf128)
228  return FPEXT_F64_PPCF128;
229  } else if (OpVT == MVT::f80) {
230  if (RetVT == MVT::f128)
231  return FPEXT_F80_F128;
232  }
233 
234  return UNKNOWN_LIBCALL;
235 }
236 
237 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
238 /// UNKNOWN_LIBCALL if there is none.
240  if (RetVT == MVT::f16) {
241  if (OpVT == MVT::f32)
242  return FPROUND_F32_F16;
243  if (OpVT == MVT::f64)
244  return FPROUND_F64_F16;
245  if (OpVT == MVT::f80)
246  return FPROUND_F80_F16;
247  if (OpVT == MVT::f128)
248  return FPROUND_F128_F16;
249  if (OpVT == MVT::ppcf128)
250  return FPROUND_PPCF128_F16;
251  } else if (RetVT == MVT::f32) {
252  if (OpVT == MVT::f64)
253  return FPROUND_F64_F32;
254  if (OpVT == MVT::f80)
255  return FPROUND_F80_F32;
256  if (OpVT == MVT::f128)
257  return FPROUND_F128_F32;
258  if (OpVT == MVT::ppcf128)
259  return FPROUND_PPCF128_F32;
260  } else if (RetVT == MVT::f64) {
261  if (OpVT == MVT::f80)
262  return FPROUND_F80_F64;
263  if (OpVT == MVT::f128)
264  return FPROUND_F128_F64;
265  if (OpVT == MVT::ppcf128)
266  return FPROUND_PPCF128_F64;
267  } else if (RetVT == MVT::f80) {
268  if (OpVT == MVT::f128)
269  return FPROUND_F128_F80;
270  }
271 
272  return UNKNOWN_LIBCALL;
273 }
274 
275 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
276 /// UNKNOWN_LIBCALL if there is none.
278  if (OpVT == MVT::f32) {
279  if (RetVT == MVT::i32)
280  return FPTOSINT_F32_I32;
281  if (RetVT == MVT::i64)
282  return FPTOSINT_F32_I64;
283  if (RetVT == MVT::i128)
284  return FPTOSINT_F32_I128;
285  } else if (OpVT == MVT::f64) {
286  if (RetVT == MVT::i32)
287  return FPTOSINT_F64_I32;
288  if (RetVT == MVT::i64)
289  return FPTOSINT_F64_I64;
290  if (RetVT == MVT::i128)
291  return FPTOSINT_F64_I128;
292  } else if (OpVT == MVT::f80) {
293  if (RetVT == MVT::i32)
294  return FPTOSINT_F80_I32;
295  if (RetVT == MVT::i64)
296  return FPTOSINT_F80_I64;
297  if (RetVT == MVT::i128)
298  return FPTOSINT_F80_I128;
299  } else if (OpVT == MVT::f128) {
300  if (RetVT == MVT::i32)
301  return FPTOSINT_F128_I32;
302  if (RetVT == MVT::i64)
303  return FPTOSINT_F128_I64;
304  if (RetVT == MVT::i128)
305  return FPTOSINT_F128_I128;
306  } else if (OpVT == MVT::ppcf128) {
307  if (RetVT == MVT::i32)
308  return FPTOSINT_PPCF128_I32;
309  if (RetVT == MVT::i64)
310  return FPTOSINT_PPCF128_I64;
311  if (RetVT == MVT::i128)
312  return FPTOSINT_PPCF128_I128;
313  }
314  return UNKNOWN_LIBCALL;
315 }
316 
317 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
318 /// UNKNOWN_LIBCALL if there is none.
320  if (OpVT == MVT::f32) {
321  if (RetVT == MVT::i32)
322  return FPTOUINT_F32_I32;
323  if (RetVT == MVT::i64)
324  return FPTOUINT_F32_I64;
325  if (RetVT == MVT::i128)
326  return FPTOUINT_F32_I128;
327  } else if (OpVT == MVT::f64) {
328  if (RetVT == MVT::i32)
329  return FPTOUINT_F64_I32;
330  if (RetVT == MVT::i64)
331  return FPTOUINT_F64_I64;
332  if (RetVT == MVT::i128)
333  return FPTOUINT_F64_I128;
334  } else if (OpVT == MVT::f80) {
335  if (RetVT == MVT::i32)
336  return FPTOUINT_F80_I32;
337  if (RetVT == MVT::i64)
338  return FPTOUINT_F80_I64;
339  if (RetVT == MVT::i128)
340  return FPTOUINT_F80_I128;
341  } else if (OpVT == MVT::f128) {
342  if (RetVT == MVT::i32)
343  return FPTOUINT_F128_I32;
344  if (RetVT == MVT::i64)
345  return FPTOUINT_F128_I64;
346  if (RetVT == MVT::i128)
347  return FPTOUINT_F128_I128;
348  } else if (OpVT == MVT::ppcf128) {
349  if (RetVT == MVT::i32)
350  return FPTOUINT_PPCF128_I32;
351  if (RetVT == MVT::i64)
352  return FPTOUINT_PPCF128_I64;
353  if (RetVT == MVT::i128)
354  return FPTOUINT_PPCF128_I128;
355  }
356  return UNKNOWN_LIBCALL;
357 }
358 
359 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
360 /// UNKNOWN_LIBCALL if there is none.
362  if (OpVT == MVT::i32) {
363  if (RetVT == MVT::f32)
364  return SINTTOFP_I32_F32;
365  if (RetVT == MVT::f64)
366  return SINTTOFP_I32_F64;
367  if (RetVT == MVT::f80)
368  return SINTTOFP_I32_F80;
369  if (RetVT == MVT::f128)
370  return SINTTOFP_I32_F128;
371  if (RetVT == MVT::ppcf128)
372  return SINTTOFP_I32_PPCF128;
373  } else if (OpVT == MVT::i64) {
374  if (RetVT == MVT::f32)
375  return SINTTOFP_I64_F32;
376  if (RetVT == MVT::f64)
377  return SINTTOFP_I64_F64;
378  if (RetVT == MVT::f80)
379  return SINTTOFP_I64_F80;
380  if (RetVT == MVT::f128)
381  return SINTTOFP_I64_F128;
382  if (RetVT == MVT::ppcf128)
383  return SINTTOFP_I64_PPCF128;
384  } else if (OpVT == MVT::i128) {
385  if (RetVT == MVT::f32)
386  return SINTTOFP_I128_F32;
387  if (RetVT == MVT::f64)
388  return SINTTOFP_I128_F64;
389  if (RetVT == MVT::f80)
390  return SINTTOFP_I128_F80;
391  if (RetVT == MVT::f128)
392  return SINTTOFP_I128_F128;
393  if (RetVT == MVT::ppcf128)
394  return SINTTOFP_I128_PPCF128;
395  }
396  return UNKNOWN_LIBCALL;
397 }
398 
399 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
400 /// UNKNOWN_LIBCALL if there is none.
402  if (OpVT == MVT::i32) {
403  if (RetVT == MVT::f32)
404  return UINTTOFP_I32_F32;
405  if (RetVT == MVT::f64)
406  return UINTTOFP_I32_F64;
407  if (RetVT == MVT::f80)
408  return UINTTOFP_I32_F80;
409  if (RetVT == MVT::f128)
410  return UINTTOFP_I32_F128;
411  if (RetVT == MVT::ppcf128)
412  return UINTTOFP_I32_PPCF128;
413  } else if (OpVT == MVT::i64) {
414  if (RetVT == MVT::f32)
415  return UINTTOFP_I64_F32;
416  if (RetVT == MVT::f64)
417  return UINTTOFP_I64_F64;
418  if (RetVT == MVT::f80)
419  return UINTTOFP_I64_F80;
420  if (RetVT == MVT::f128)
421  return UINTTOFP_I64_F128;
422  if (RetVT == MVT::ppcf128)
423  return UINTTOFP_I64_PPCF128;
424  } else if (OpVT == MVT::i128) {
425  if (RetVT == MVT::f32)
426  return UINTTOFP_I128_F32;
427  if (RetVT == MVT::f64)
428  return UINTTOFP_I128_F64;
429  if (RetVT == MVT::f80)
430  return UINTTOFP_I128_F80;
431  if (RetVT == MVT::f128)
432  return UINTTOFP_I128_F128;
433  if (RetVT == MVT::ppcf128)
434  return UINTTOFP_I128_PPCF128;
435  }
436  return UNKNOWN_LIBCALL;
437 }
438 
439 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
440 #define OP_TO_LIBCALL(Name, Enum) \
441  case Name: \
442  switch (VT.SimpleTy) { \
443  default: \
444  return UNKNOWN_LIBCALL; \
445  case MVT::i8: \
446  return Enum##_1; \
447  case MVT::i16: \
448  return Enum##_2; \
449  case MVT::i32: \
450  return Enum##_4; \
451  case MVT::i64: \
452  return Enum##_8; \
453  case MVT::i128: \
454  return Enum##_16; \
455  }
456 
457  switch (Opc) {
458  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
459  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
460  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
461  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
462  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
463  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
464  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
465  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
466  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
467  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
468  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
469  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
470  }
471 
472 #undef OP_TO_LIBCALL
473 
474  return UNKNOWN_LIBCALL;
475 }
476 
478  switch (ElementSize) {
479  case 1:
480  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
481  case 2:
482  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
483  case 4:
484  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
485  case 8:
486  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
487  case 16:
488  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
489  default:
490  return UNKNOWN_LIBCALL;
491  }
492 }
493 
495  switch (ElementSize) {
496  case 1:
497  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
498  case 2:
499  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
500  case 4:
501  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
502  case 8:
503  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
504  case 16:
505  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
506  default:
507  return UNKNOWN_LIBCALL;
508  }
509 }
510 
512  switch (ElementSize) {
513  case 1:
514  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
515  case 2:
516  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
517  case 4:
518  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
519  case 8:
520  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
521  case 16:
522  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
523  default:
524  return UNKNOWN_LIBCALL;
525  }
526 }
527 
528 /// InitCmpLibcallCCs - Set default comparison libcall CC.
529 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
530  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
531  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
532  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
533  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
534  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
535  CCs[RTLIB::UNE_F32] = ISD::SETNE;
536  CCs[RTLIB::UNE_F64] = ISD::SETNE;
537  CCs[RTLIB::UNE_F128] = ISD::SETNE;
538  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
539  CCs[RTLIB::OGE_F32] = ISD::SETGE;
540  CCs[RTLIB::OGE_F64] = ISD::SETGE;
541  CCs[RTLIB::OGE_F128] = ISD::SETGE;
542  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
543  CCs[RTLIB::OLT_F32] = ISD::SETLT;
544  CCs[RTLIB::OLT_F64] = ISD::SETLT;
545  CCs[RTLIB::OLT_F128] = ISD::SETLT;
546  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
547  CCs[RTLIB::OLE_F32] = ISD::SETLE;
548  CCs[RTLIB::OLE_F64] = ISD::SETLE;
549  CCs[RTLIB::OLE_F128] = ISD::SETLE;
550  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
551  CCs[RTLIB::OGT_F32] = ISD::SETGT;
552  CCs[RTLIB::OGT_F64] = ISD::SETGT;
553  CCs[RTLIB::OGT_F128] = ISD::SETGT;
554  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
555  CCs[RTLIB::UO_F32] = ISD::SETNE;
556  CCs[RTLIB::UO_F64] = ISD::SETNE;
557  CCs[RTLIB::UO_F128] = ISD::SETNE;
558  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
559  CCs[RTLIB::O_F32] = ISD::SETEQ;
560  CCs[RTLIB::O_F64] = ISD::SETEQ;
561  CCs[RTLIB::O_F128] = ISD::SETEQ;
562  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
563 }
564 
565 /// NOTE: The TargetMachine owns TLOF.
567  initActions();
568 
569  // Perform these initializations only once.
571  MaxLoadsPerMemcmp = 8;
575  UseUnderscoreSetJmp = false;
576  UseUnderscoreLongJmp = false;
577  HasMultipleConditionRegisters = false;
578  HasExtractBitsInsn = false;
579  JumpIsExpensive = JumpIsExpensiveOverride;
581  EnableExtLdPromotion = false;
582  StackPointerRegisterToSaveRestore = 0;
583  BooleanContents = UndefinedBooleanContent;
584  BooleanFloatContents = UndefinedBooleanContent;
585  BooleanVectorContents = UndefinedBooleanContent;
586  SchedPreferenceInfo = Sched::ILP;
588  // TODO: the default will be switched to 0 in the next commit, along
589  // with the Target-specific changes necessary.
590  MaxAtomicSizeInBitsSupported = 1024;
591 
592  MinCmpXchgSizeInBits = 0;
593  SupportsUnalignedAtomics = false;
594 
595  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
596 
597  InitLibcalls(TM.getTargetTriple());
598  InitCmpLibcallCCs(CmpLibcallCCs);
599 }
600 
602  // All operations default to being supported.
603  memset(OpActions, 0, sizeof(OpActions));
604  memset(LoadExtActions, 0, sizeof(LoadExtActions));
605  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
606  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
607  memset(CondCodeActions, 0, sizeof(CondCodeActions));
608  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
609  std::fill(std::begin(TargetDAGCombineArray),
610  std::end(TargetDAGCombineArray), 0);
611 
612  for (MVT VT : MVT::fp_valuetypes()) {
613  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
614  if (IntVT.isValid()) {
617  }
618  }
619 
620  // Set default actions for various operations.
621  for (MVT VT : MVT::all_valuetypes()) {
622  // Default all indexed load / store to expand.
623  for (unsigned IM = (unsigned)ISD::PRE_INC;
624  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
625  setIndexedLoadAction(IM, VT, Expand);
626  setIndexedStoreAction(IM, VT, Expand);
627  }
628 
629  // Most backends expect to see the node which just returns the value loaded.
631 
632  // These operations default to expand.
657 
658  // Overflow operations default to expand
665 
666  // ADDCARRY operations default to expand
670 
671  // ADDC/ADDE/SUBC/SUBE default to expand.
676 
677  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
680 
682 
683  // These library functions default to expand.
686 
687  // These operations default to expand for vector types.
688  if (VT.isVector()) {
693  }
694 
695  // Constrained floating-point operations default to expand.
728 
729  // For most targets @llvm.get.dynamic.area.offset just returns 0.
731 
732  // Vector reduction default to expand.
746  }
747 
748  // Most targets ignore the @llvm.prefetch intrinsic.
750 
751  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
753 
754  // ConstantFP nodes default to expand. Targets can either change this to
755  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
756  // to optimize expansions for certain constants.
762 
763  // These library functions default to expand.
764  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
781  }
782 
783  // Default ISD::TRAP to expand (which turns it into abort).
785 
786  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
787  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
789 }
790 
792  EVT) const {
794 }
795 
797  bool LegalTypes) const {
798  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
799  if (LHSTy.isVector())
800  return LHSTy;
801  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
802  : getPointerTy(DL);
803 }
804 
805 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
806  assert(isTypeLegal(VT));
807  switch (Op) {
808  default:
809  return false;
810  case ISD::SDIV:
811  case ISD::UDIV:
812  case ISD::SREM:
813  case ISD::UREM:
814  return true;
815  }
816 }
817 
819  // If the command-line option was specified, ignore this request.
820  if (!JumpIsExpensiveOverride.getNumOccurrences())
821  JumpIsExpensive = isExpensive;
822 }
823 
825 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
826  // If this is a simple type, use the ComputeRegisterProp mechanism.
827  if (VT.isSimple()) {
828  MVT SVT = VT.getSimpleVT();
829  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
830  MVT NVT = TransformToType[SVT.SimpleTy];
831  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
832 
833  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
834  (NVT.isVector() ||
835  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
836  "Promote may not follow Expand or Promote");
837 
838  if (LA == TypeSplitVector)
839  return LegalizeKind(LA,
840  EVT::getVectorVT(Context, SVT.getVectorElementType(),
841  SVT.getVectorNumElements() / 2));
842  if (LA == TypeScalarizeVector)
843  return LegalizeKind(LA, SVT.getVectorElementType());
844  return LegalizeKind(LA, NVT);
845  }
846 
847  // Handle Extended Scalar Types.
848  if (!VT.isVector()) {
849  assert(VT.isInteger() && "Float types must be simple");
850  unsigned BitSize = VT.getSizeInBits();
851  // First promote to a power-of-two size, then expand if necessary.
852  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
853  EVT NVT = VT.getRoundIntegerType(Context);
854  assert(NVT != VT && "Unable to round integer VT");
855  LegalizeKind NextStep = getTypeConversion(Context, NVT);
856  // Avoid multi-step promotion.
857  if (NextStep.first == TypePromoteInteger)
858  return NextStep;
859  // Return rounded integer type.
860  return LegalizeKind(TypePromoteInteger, NVT);
861  }
862 
864  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
865  }
866 
867  // Handle vector types.
868  unsigned NumElts = VT.getVectorNumElements();
869  EVT EltVT = VT.getVectorElementType();
870 
871  // Vectors with only one element are always scalarized.
872  if (NumElts == 1)
873  return LegalizeKind(TypeScalarizeVector, EltVT);
874 
875  // Try to widen vector elements until the element type is a power of two and
876  // promote it to a legal type later on, for example:
877  // <3 x i8> -> <4 x i8> -> <4 x i32>
878  if (EltVT.isInteger()) {
879  // Vectors with a number of elements that is not a power of two are always
880  // widened, for example <3 x i8> -> <4 x i8>.
881  if (!VT.isPow2VectorType()) {
882  NumElts = (unsigned)NextPowerOf2(NumElts);
883  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
884  return LegalizeKind(TypeWidenVector, NVT);
885  }
886 
887  // Examine the element type.
888  LegalizeKind LK = getTypeConversion(Context, EltVT);
889 
890  // If type is to be expanded, split the vector.
891  // <4 x i140> -> <2 x i140>
892  if (LK.first == TypeExpandInteger)
894  EVT::getVectorVT(Context, EltVT, NumElts / 2));
895 
896  // Promote the integer element types until a legal vector type is found
897  // or until the element integer type is too big. If a legal type was not
898  // found, fallback to the usual mechanism of widening/splitting the
899  // vector.
900  EVT OldEltVT = EltVT;
901  while (true) {
902  // Increase the bitwidth of the element to the next pow-of-two
903  // (which is greater than 8 bits).
904  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
905  .getRoundIntegerType(Context);
906 
907  // Stop trying when getting a non-simple element type.
908  // Note that vector elements may be greater than legal vector element
909  // types. Example: X86 XMM registers hold 64bit element on 32bit
910  // systems.
911  if (!EltVT.isSimple())
912  break;
913 
914  // Build a new vector type and check if it is legal.
915  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
916  // Found a legal promoted vector type.
917  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
919  EVT::getVectorVT(Context, EltVT, NumElts));
920  }
921 
922  // Reset the type to the unexpanded type if we did not find a legal vector
923  // type with a promoted vector element type.
924  EltVT = OldEltVT;
925  }
926 
927  // Try to widen the vector until a legal type is found.
928  // If there is no wider legal type, split the vector.
929  while (true) {
930  // Round up to the next power of 2.
931  NumElts = (unsigned)NextPowerOf2(NumElts);
932 
933  // If there is no simple vector type with this many elements then there
934  // cannot be a larger legal vector type. Note that this assumes that
935  // there are no skipped intermediate vector types in the simple types.
936  if (!EltVT.isSimple())
937  break;
938  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
939  if (LargerVector == MVT())
940  break;
941 
942  // If this type is legal then widen the vector.
943  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
944  return LegalizeKind(TypeWidenVector, LargerVector);
945  }
946 
947  // Widen odd vectors to next power of two.
948  if (!VT.isPow2VectorType()) {
949  EVT NVT = VT.getPow2VectorType(Context);
950  return LegalizeKind(TypeWidenVector, NVT);
951  }
952 
953  // Vectors with illegal element types are expanded.
954  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
955  return LegalizeKind(TypeSplitVector, NVT);
956 }
957 
958 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
959  unsigned &NumIntermediates,
960  MVT &RegisterVT,
961  TargetLoweringBase *TLI) {
962  // Figure out the right, legal destination reg to copy into.
963  unsigned NumElts = VT.getVectorNumElements();
964  MVT EltTy = VT.getVectorElementType();
965 
966  unsigned NumVectorRegs = 1;
967 
968  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
969  // could break down into LHS/RHS like LegalizeDAG does.
970  if (!isPowerOf2_32(NumElts)) {
971  NumVectorRegs = NumElts;
972  NumElts = 1;
973  }
974 
975  // Divide the input until we get to a supported size. This will always
976  // end with a scalar if the target doesn't support vectors.
977  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
978  NumElts >>= 1;
979  NumVectorRegs <<= 1;
980  }
981 
982  NumIntermediates = NumVectorRegs;
983 
984  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
985  if (!TLI->isTypeLegal(NewVT))
986  NewVT = EltTy;
987  IntermediateVT = NewVT;
988 
989  unsigned NewVTSize = NewVT.getSizeInBits();
990 
991  // Convert sizes such as i33 to i64.
992  if (!isPowerOf2_32(NewVTSize))
993  NewVTSize = NextPowerOf2(NewVTSize);
994 
995  MVT DestVT = TLI->getRegisterType(NewVT);
996  RegisterVT = DestVT;
997  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
998  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
999 
1000  // Otherwise, promotion or legal types use the same number of registers as
1001  // the vector decimated to the appropriate level.
1002  return NumVectorRegs;
1003 }
1004 
1005 /// isLegalRC - Return true if the value types that can be represented by the
1006 /// specified register class are all legal.
1008  const TargetRegisterClass &RC) const {
1009  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1010  if (isTypeLegal(*I))
1011  return true;
1012  return false;
1013 }
1014 
1015 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1016 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1019  MachineBasicBlock *MBB) const {
1020  MachineInstr *MI = &InitialMI;
1021  MachineFunction &MF = *MI->getMF();
1022  MachineFrameInfo &MFI = MF.getFrameInfo();
1023 
1024  // We're handling multiple types of operands here:
1025  // PATCHPOINT MetaArgs - live-in, read only, direct
1026  // STATEPOINT Deopt Spill - live-through, read only, indirect
1027  // STATEPOINT Deopt Alloca - live-through, read only, direct
1028  // (We're currently conservative and mark the deopt slots read/write in
1029  // practice.)
1030  // STATEPOINT GC Spill - live-through, read/write, indirect
1031  // STATEPOINT GC Alloca - live-through, read/write, direct
1032  // The live-in vs live-through is handled already (the live through ones are
1033  // all stack slots), but we need to handle the different type of stackmap
1034  // operands and memory effects here.
1035 
1036  // MI changes inside this loop as we grow operands.
1037  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1038  MachineOperand &MO = MI->getOperand(OperIdx);
1039  if (!MO.isFI())
1040  continue;
1041 
1042  // foldMemoryOperand builds a new MI after replacing a single FI operand
1043  // with the canonical set of five x86 addressing-mode operands.
1044  int FI = MO.getIndex();
1045  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1046 
1047  // Copy operands before the frame-index.
1048  for (unsigned i = 0; i < OperIdx; ++i)
1049  MIB.add(MI->getOperand(i));
1050  // Add frame index operands recognized by stackmaps.cpp
1051  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1052  // indirect-mem-ref tag, size, #FI, offset.
1053  // Used for spills inserted by StatepointLowering. This codepath is not
1054  // used for patchpoints/stackmaps at all, for these spilling is done via
1055  // foldMemoryOperand callback only.
1056  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1057  MIB.addImm(StackMaps::IndirectMemRefOp);
1058  MIB.addImm(MFI.getObjectSize(FI));
1059  MIB.add(MI->getOperand(OperIdx));
1060  MIB.addImm(0);
1061  } else {
1062  // direct-mem-ref tag, #FI, offset.
1063  // Used by patchpoint, and direct alloca arguments to statepoints
1064  MIB.addImm(StackMaps::DirectMemRefOp);
1065  MIB.add(MI->getOperand(OperIdx));
1066  MIB.addImm(0);
1067  }
1068  // Copy the operands after the frame index.
1069  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1070  MIB.add(MI->getOperand(i));
1071 
1072  // Inherit previous memory operands.
1073  MIB.cloneMemRefs(*MI);
1074  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1075 
1076  // Add a new memory operand for this FI.
1077  assert(MFI.getObjectOffset(FI) != -1);
1078 
1079  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1080  // PATCHPOINT should be updated to do the same. (TODO)
1081  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1082  auto Flags = MachineMemOperand::MOLoad;
1084  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1086  MIB->addMemOperand(MF, MMO);
1087  }
1088 
1089  // Replace the instruction and update the operand index.
1090  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1091  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1092  MI->eraseFromParent();
1093  MI = MIB;
1094  }
1095  return MBB;
1096 }
1097 
1100  MachineBasicBlock *MBB) const {
1101  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1102  "Called emitXRayCustomEvent on the wrong MI!");
1103  auto &MF = *MI.getMF();
1104  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1105  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1106  MIB.add(MI.getOperand(OpIdx));
1107 
1108  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1109  MI.eraseFromParent();
1110  return MBB;
1111 }
1112 
1115  MachineBasicBlock *MBB) const {
1116  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1117  "Called emitXRayTypedEvent on the wrong MI!");
1118  auto &MF = *MI.getMF();
1119  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1120  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1121  MIB.add(MI.getOperand(OpIdx));
1122 
1123  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1124  MI.eraseFromParent();
1125  return MBB;
1126 }
1127 
1128 /// findRepresentativeClass - Return the largest legal super-reg register class
1129 /// of the register class for the specified type and its associated "cost".
1130 // This function is in TargetLowering because it uses RegClassForVT which would
1131 // need to be moved to TargetRegisterInfo and would necessitate moving
1132 // isTypeLegal over as well - a massive change that would just require
1133 // TargetLowering having a TargetRegisterInfo class member that it would use.
1134 std::pair<const TargetRegisterClass *, uint8_t>
1136  MVT VT) const {
1137  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1138  if (!RC)
1139  return std::make_pair(RC, 0);
1140 
1141  // Compute the set of all super-register classes.
1142  BitVector SuperRegRC(TRI->getNumRegClasses());
1143  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1144  SuperRegRC.setBitsInMask(RCI.getMask());
1145 
1146  // Find the first legal register class with the largest spill size.
1147  const TargetRegisterClass *BestRC = RC;
1148  for (unsigned i : SuperRegRC.set_bits()) {
1149  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1150  // We want the largest possible spill size.
1151  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1152  continue;
1153  if (!isLegalRC(*TRI, *SuperRC))
1154  continue;
1155  BestRC = SuperRC;
1156  }
1157  return std::make_pair(BestRC, 1);
1158 }
1159 
1160 /// computeRegisterProperties - Once all of the register classes are added,
1161 /// this allows us to compute derived properties we expose.
1163  const TargetRegisterInfo *TRI) {
1165  "Too many value types for ValueTypeActions to hold!");
1166 
1167  // Everything defaults to needing one register.
1168  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1169  NumRegistersForVT[i] = 1;
1170  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1171  }
1172  // ...except isVoid, which doesn't need any registers.
1173  NumRegistersForVT[MVT::isVoid] = 0;
1174 
1175  // Find the largest integer register class.
1176  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1177  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1178  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1179 
1180  // Every integer value type larger than this largest register takes twice as
1181  // many registers to represent as the previous ValueType.
1182  for (unsigned ExpandedReg = LargestIntReg + 1;
1183  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1184  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1185  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1186  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1187  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1189  }
1190 
1191  // Inspect all of the ValueType's smaller than the largest integer
1192  // register to see which ones need promotion.
1193  unsigned LegalIntReg = LargestIntReg;
1194  for (unsigned IntReg = LargestIntReg - 1;
1195  IntReg >= (unsigned)MVT::i1; --IntReg) {
1196  MVT IVT = (MVT::SimpleValueType)IntReg;
1197  if (isTypeLegal(IVT)) {
1198  LegalIntReg = IntReg;
1199  } else {
1200  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1201  (MVT::SimpleValueType)LegalIntReg;
1202  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1203  }
1204  }
1205 
1206  // ppcf128 type is really two f64's.
1207  if (!isTypeLegal(MVT::ppcf128)) {
1208  if (isTypeLegal(MVT::f64)) {
1209  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1210  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1211  TransformToType[MVT::ppcf128] = MVT::f64;
1212  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1213  } else {
1214  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1215  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1216  TransformToType[MVT::ppcf128] = MVT::i128;
1217  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1218  }
1219  }
1220 
1221  // Decide how to handle f128. If the target does not have native f128 support,
1222  // expand it to i128 and we will be generating soft float library calls.
1223  if (!isTypeLegal(MVT::f128)) {
1224  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1225  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1226  TransformToType[MVT::f128] = MVT::i128;
1227  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1228  }
1229 
1230  // Decide how to handle f64. If the target does not have native f64 support,
1231  // expand it to i64 and we will be generating soft float library calls.
1232  if (!isTypeLegal(MVT::f64)) {
1233  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1234  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1235  TransformToType[MVT::f64] = MVT::i64;
1236  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1237  }
1238 
1239  // Decide how to handle f32. If the target does not have native f32 support,
1240  // expand it to i32 and we will be generating soft float library calls.
1241  if (!isTypeLegal(MVT::f32)) {
1242  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1243  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1244  TransformToType[MVT::f32] = MVT::i32;
1245  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1246  }
1247 
1248  // Decide how to handle f16. If the target does not have native f16 support,
1249  // promote it to f32, because there are no f16 library calls (except for
1250  // conversions).
1251  if (!isTypeLegal(MVT::f16)) {
1252  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1253  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1254  TransformToType[MVT::f16] = MVT::f32;
1255  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1256  }
1257 
1258  // Loop over all of the vector value types to see which need transformations.
1259  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1260  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1261  MVT VT = (MVT::SimpleValueType) i;
1262  if (isTypeLegal(VT))
1263  continue;
1264 
1265  MVT EltVT = VT.getVectorElementType();
1266  unsigned NElts = VT.getVectorNumElements();
1267  bool IsLegalWiderType = false;
1268  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1269  switch (PreferredAction) {
1270  case TypePromoteInteger:
1271  // Try to promote the elements of integer vectors. If no legal
1272  // promotion was found, fall through to the widen-vector method.
1273  for (unsigned nVT = i + 1;
1275  MVT SVT = (MVT::SimpleValueType) nVT;
1276  // Promote vectors of integers to vectors with the same number
1277  // of elements, with a wider element type.
1278  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1279  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1280  TransformToType[i] = SVT;
1281  RegisterTypeForVT[i] = SVT;
1282  NumRegistersForVT[i] = 1;
1283  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1284  IsLegalWiderType = true;
1285  break;
1286  }
1287  }
1288  if (IsLegalWiderType)
1289  break;
1291 
1292  case TypeWidenVector:
1293  if (isPowerOf2_32(NElts)) {
1294  // Try to widen the vector.
1295  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1296  MVT SVT = (MVT::SimpleValueType) nVT;
1297  if (SVT.getVectorElementType() == EltVT
1298  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1299  TransformToType[i] = SVT;
1300  RegisterTypeForVT[i] = SVT;
1301  NumRegistersForVT[i] = 1;
1302  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1303  IsLegalWiderType = true;
1304  break;
1305  }
1306  }
1307  if (IsLegalWiderType)
1308  break;
1309  } else {
1310  // Only widen to the next power of 2 to keep consistency with EVT.
1311  MVT NVT = VT.getPow2VectorType();
1312  if (isTypeLegal(NVT)) {
1313  TransformToType[i] = NVT;
1314  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1315  RegisterTypeForVT[i] = NVT;
1316  NumRegistersForVT[i] = 1;
1317  break;
1318  }
1319  }
1321 
1322  case TypeSplitVector:
1323  case TypeScalarizeVector: {
1324  MVT IntermediateVT;
1325  MVT RegisterVT;
1326  unsigned NumIntermediates;
1327  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1328  NumIntermediates, RegisterVT, this);
1329  RegisterTypeForVT[i] = RegisterVT;
1330 
1331  MVT NVT = VT.getPow2VectorType();
1332  if (NVT == VT) {
1333  // Type is already a power of 2. The default action is to split.
1334  TransformToType[i] = MVT::Other;
1335  if (PreferredAction == TypeScalarizeVector)
1336  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1337  else if (PreferredAction == TypeSplitVector)
1338  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1339  else
1340  // Set type action according to the number of elements.
1341  ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1342  : TypeSplitVector);
1343  } else {
1344  TransformToType[i] = NVT;
1345  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1346  }
1347  break;
1348  }
1349  default:
1350  llvm_unreachable("Unknown vector legalization action!");
1351  }
1352  }
1353 
1354  // Determine the 'representative' register class for each value type.
1355  // An representative register class is the largest (meaning one which is
1356  // not a sub-register class / subreg register class) legal register class for
1357  // a group of value types. For example, on i386, i8, i16, and i32
1358  // representative would be GR32; while on x86_64 it's GR64.
1359  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1360  const TargetRegisterClass* RRC;
1361  uint8_t Cost;
1362  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1363  RepRegClassForVT[i] = RRC;
1364  RepRegClassCostForVT[i] = Cost;
1365  }
1366 }
1367 
1369  EVT VT) const {
1370  assert(!VT.isVector() && "No default SetCC type for vectors!");
1371  return getPointerTy(DL).SimpleTy;
1372 }
1373 
1375  return MVT::i32; // return the default value
1376 }
1377 
1378 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1379 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1380 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1381 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1382 ///
1383 /// This method returns the number of registers needed, and the VT for each
1384 /// register. It also returns the VT and quantity of the intermediate values
1385 /// before they are promoted/expanded.
1387  EVT &IntermediateVT,
1388  unsigned &NumIntermediates,
1389  MVT &RegisterVT) const {
1390  unsigned NumElts = VT.getVectorNumElements();
1391 
1392  // If there is a wider vector type with the same element type as this one,
1393  // or a promoted vector type that has the same number of elements which
1394  // are wider, then we should convert to that legal vector type.
1395  // This handles things like <2 x float> -> <4 x float> and
1396  // <4 x i1> -> <4 x i32>.
1397  LegalizeTypeAction TA = getTypeAction(Context, VT);
1398  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1399  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1400  if (isTypeLegal(RegisterEVT)) {
1401  IntermediateVT = RegisterEVT;
1402  RegisterVT = RegisterEVT.getSimpleVT();
1403  NumIntermediates = 1;
1404  return 1;
1405  }
1406  }
1407 
1408  // Figure out the right, legal destination reg to copy into.
1409  EVT EltTy = VT.getVectorElementType();
1410 
1411  unsigned NumVectorRegs = 1;
1412 
1413  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1414  // could break down into LHS/RHS like LegalizeDAG does.
1415  if (!isPowerOf2_32(NumElts)) {
1416  NumVectorRegs = NumElts;
1417  NumElts = 1;
1418  }
1419 
1420  // Divide the input until we get to a supported size. This will always
1421  // end with a scalar if the target doesn't support vectors.
1422  while (NumElts > 1 && !isTypeLegal(
1423  EVT::getVectorVT(Context, EltTy, NumElts))) {
1424  NumElts >>= 1;
1425  NumVectorRegs <<= 1;
1426  }
1427 
1428  NumIntermediates = NumVectorRegs;
1429 
1430  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1431  if (!isTypeLegal(NewVT))
1432  NewVT = EltTy;
1433  IntermediateVT = NewVT;
1434 
1435  MVT DestVT = getRegisterType(Context, NewVT);
1436  RegisterVT = DestVT;
1437  unsigned NewVTSize = NewVT.getSizeInBits();
1438 
1439  // Convert sizes such as i33 to i64.
1440  if (!isPowerOf2_32(NewVTSize))
1441  NewVTSize = NextPowerOf2(NewVTSize);
1442 
1443  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1444  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1445 
1446  // Otherwise, promotion or legal types use the same number of registers as
1447  // the vector decimated to the appropriate level.
1448  return NumVectorRegs;
1449 }
1450 
1451 /// Get the EVTs and ArgFlags collections that represent the legalized return
1452 /// type of the given function. This does not require a DAG or a return value,
1453 /// and is suitable for use before any DAGs for the function are constructed.
1454 /// TODO: Move this out of TargetLowering.cpp.
1456  AttributeList attr,
1458  const TargetLowering &TLI, const DataLayout &DL) {
1459  SmallVector<EVT, 4> ValueVTs;
1460  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1461  unsigned NumValues = ValueVTs.size();
1462  if (NumValues == 0) return;
1463 
1464  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1465  EVT VT = ValueVTs[j];
1466  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1467 
1468  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1469  ExtendKind = ISD::SIGN_EXTEND;
1470  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1471  ExtendKind = ISD::ZERO_EXTEND;
1472 
1473  // FIXME: C calling convention requires the return type to be promoted to
1474  // at least 32-bit. But this is not necessary for non-C calling
1475  // conventions. The frontend should mark functions whose return values
1476  // require promoting with signext or zeroext attributes.
1477  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1478  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1479  if (VT.bitsLT(MinVT))
1480  VT = MinVT;
1481  }
1482 
1483  unsigned NumParts =
1484  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1485  MVT PartVT =
1486  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1487 
1488  // 'inreg' on function refers to return value
1489  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1490  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1491  Flags.setInReg();
1492 
1493  // Propagate extension type if any
1494  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1495  Flags.setSExt();
1496  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1497  Flags.setZExt();
1498 
1499  for (unsigned i = 0; i < NumParts; ++i)
1500  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1501  }
1502 }
1503 
1504 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1505 /// function arguments in the caller parameter area. This is the actual
1506 /// alignment, not its logarithm.
1508  const DataLayout &DL) const {
1509  return DL.getABITypeAlignment(Ty);
1510 }
1511 
1513  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1514  unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1515  // Check if the specified alignment is sufficient based on the data layout.
1516  // TODO: While using the data layout works in practice, a better solution
1517  // would be to implement this check directly (make this a virtual function).
1518  // For example, the ABI alignment may change based on software platform while
1519  // this function should only be affected by hardware implementation.
1520  Type *Ty = VT.getTypeForEVT(Context);
1521  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1522  // Assume that an access that meets the ABI-specified alignment is fast.
1523  if (Fast != nullptr)
1524  *Fast = true;
1525  return true;
1526  }
1527 
1528  // This is a misaligned access.
1529  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1530 }
1531 
1533  LLVMContext &Context, const DataLayout &DL, EVT VT,
1534  const MachineMemOperand &MMO, bool *Fast) const {
1535  return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(),
1536  MMO.getAlignment(), MMO.getFlags(),
1537  Fast);
1538 }
1539 
1541  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1542  unsigned Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1543  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1544  Flags, Fast);
1545 }
1546 
1548  const DataLayout &DL, EVT VT,
1549  const MachineMemOperand &MMO,
1550  bool *Fast) const {
1551  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1552  MMO.getAlignment(), MMO.getFlags(), Fast);
1553 }
1554 
1556  return BranchProbability(MinPercentageForPredictableBranch, 100);
1557 }
1558 
1559 //===----------------------------------------------------------------------===//
1560 // TargetTransformInfo Helpers
1561 //===----------------------------------------------------------------------===//
1562 
1564  enum InstructionOpcodes {
1565 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1566 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1567 #include "llvm/IR/Instruction.def"
1568  };
1569  switch (static_cast<InstructionOpcodes>(Opcode)) {
1570  case Ret: return 0;
1571  case Br: return 0;
1572  case Switch: return 0;
1573  case IndirectBr: return 0;
1574  case Invoke: return 0;
1575  case CallBr: return 0;
1576  case Resume: return 0;
1577  case Unreachable: return 0;
1578  case CleanupRet: return 0;
1579  case CatchRet: return 0;
1580  case CatchPad: return 0;
1581  case CatchSwitch: return 0;
1582  case CleanupPad: return 0;
1583  case FNeg: return ISD::FNEG;
1584  case Add: return ISD::ADD;
1585  case FAdd: return ISD::FADD;
1586  case Sub: return ISD::SUB;
1587  case FSub: return ISD::FSUB;
1588  case Mul: return ISD::MUL;
1589  case FMul: return ISD::FMUL;
1590  case UDiv: return ISD::UDIV;
1591  case SDiv: return ISD::SDIV;
1592  case FDiv: return ISD::FDIV;
1593  case URem: return ISD::UREM;
1594  case SRem: return ISD::SREM;
1595  case FRem: return ISD::FREM;
1596  case Shl: return ISD::SHL;
1597  case LShr: return ISD::SRL;
1598  case AShr: return ISD::SRA;
1599  case And: return ISD::AND;
1600  case Or: return ISD::OR;
1601  case Xor: return ISD::XOR;
1602  case Alloca: return 0;
1603  case Load: return ISD::LOAD;
1604  case Store: return ISD::STORE;
1605  case GetElementPtr: return 0;
1606  case Fence: return 0;
1607  case AtomicCmpXchg: return 0;
1608  case AtomicRMW: return 0;
1609  case Trunc: return ISD::TRUNCATE;
1610  case ZExt: return ISD::ZERO_EXTEND;
1611  case SExt: return ISD::SIGN_EXTEND;
1612  case FPToUI: return ISD::FP_TO_UINT;
1613  case FPToSI: return ISD::FP_TO_SINT;
1614  case UIToFP: return ISD::UINT_TO_FP;
1615  case SIToFP: return ISD::SINT_TO_FP;
1616  case FPTrunc: return ISD::FP_ROUND;
1617  case FPExt: return ISD::FP_EXTEND;
1618  case PtrToInt: return ISD::BITCAST;
1619  case IntToPtr: return ISD::BITCAST;
1620  case BitCast: return ISD::BITCAST;
1621  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1622  case ICmp: return ISD::SETCC;
1623  case FCmp: return ISD::SETCC;
1624  case PHI: return 0;
1625  case Call: return 0;
1626  case Select: return ISD::SELECT;
1627  case UserOp1: return 0;
1628  case UserOp2: return 0;
1629  case VAArg: return 0;
1630  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1631  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1632  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1633  case ExtractValue: return ISD::MERGE_VALUES;
1634  case InsertValue: return ISD::MERGE_VALUES;
1635  case LandingPad: return 0;
1636  }
1637 
1638  llvm_unreachable("Unknown instruction type encountered!");
1639 }
1640 
1641 std::pair<int, MVT>
1643  Type *Ty) const {
1644  LLVMContext &C = Ty->getContext();
1645  EVT MTy = getValueType(DL, Ty);
1646 
1647  int Cost = 1;
1648  // We keep legalizing the type until we find a legal kind. We assume that
1649  // the only operation that costs anything is the split. After splitting
1650  // we need to handle two types.
1651  while (true) {
1652  LegalizeKind LK = getTypeConversion(C, MTy);
1653 
1654  if (LK.first == TypeLegal)
1655  return std::make_pair(Cost, MTy.getSimpleVT());
1656 
1657  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1658  Cost *= 2;
1659 
1660  // Do not loop with f128 type.
1661  if (MTy == LK.second)
1662  return std::make_pair(Cost, MTy.getSimpleVT());
1663 
1664  // Keep legalizing the type.
1665  MTy = LK.second;
1666  }
1667 }
1668 
1670  bool UseTLS) const {
1671  // compiler-rt provides a variable with a magic name. Targets that do not
1672  // link with compiler-rt may also provide such a variable.
1673  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1674  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1675  auto UnsafeStackPtr =
1676  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1677 
1678  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1679 
1680  if (!UnsafeStackPtr) {
1681  auto TLSModel = UseTLS ?
1684  // The global variable is not defined yet, define it ourselves.
1685  // We use the initial-exec TLS model because we do not support the
1686  // variable living anywhere other than in the main executable.
1687  UnsafeStackPtr = new GlobalVariable(
1688  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1689  UnsafeStackPtrVar, nullptr, TLSModel);
1690  } else {
1691  // The variable exists, check its type and attributes.
1692  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1693  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1694  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1695  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1696  (UseTLS ? "" : "not ") + "be thread-local");
1697  }
1698  return UnsafeStackPtr;
1699 }
1700 
1702  if (!TM.getTargetTriple().isAndroid())
1703  return getDefaultSafeStackPointerLocation(IRB, true);
1704 
1705  // Android provides a libc function to retrieve the address of the current
1706  // thread's unsafe stack pointer.
1707  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1708  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1709  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1710  StackPtrTy->getPointerTo(0));
1711  return IRB.CreateCall(Fn);
1712 }
1713 
1714 //===----------------------------------------------------------------------===//
1715 // Loop Strength Reduction hooks
1716 //===----------------------------------------------------------------------===//
1717 
1718 /// isLegalAddressingMode - Return true if the addressing mode represented
1719 /// by AM is legal for this target, for a load/store of the specified type.
1721  const AddrMode &AM, Type *Ty,
1722  unsigned AS, Instruction *I) const {
1723  // The default implementation of this implements a conservative RISCy, r+r and
1724  // r+i addr mode.
1725 
1726  // Allows a sign-extended 16-bit immediate field.
1727  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1728  return false;
1729 
1730  // No global is ever allowed as a base.
1731  if (AM.BaseGV)
1732  return false;
1733 
1734  // Only support r+r,
1735  switch (AM.Scale) {
1736  case 0: // "r+i" or just "i", depending on HasBaseReg.
1737  break;
1738  case 1:
1739  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1740  return false;
1741  // Otherwise we have r+r or r+i.
1742  break;
1743  case 2:
1744  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1745  return false;
1746  // Allow 2*r as r+r.
1747  break;
1748  default: // Don't allow n * r
1749  return false;
1750  }
1751 
1752  return true;
1753 }
1754 
1755 //===----------------------------------------------------------------------===//
1756 // Stack Protector
1757 //===----------------------------------------------------------------------===//
1758 
1759 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1760 // so that SelectionDAG handle SSP.
1762  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1763  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1765  return M.getOrInsertGlobal("__guard_local", PtrTy);
1766  }
1767  return nullptr;
1768 }
1769 
1770 // Currently only support "standard" __stack_chk_guard.
1771 // TODO: add LOAD_STACK_GUARD support.
1773  if (!M.getNamedValue("__stack_chk_guard"))
1774  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1776  nullptr, "__stack_chk_guard");
1777 }
1778 
1779 // Currently only support "standard" __stack_chk_guard.
1780 // TODO: add LOAD_STACK_GUARD support.
1782  return M.getNamedValue("__stack_chk_guard");
1783 }
1784 
1786  return nullptr;
1787 }
1788 
1790  return MinimumJumpTableEntries;
1791 }
1792 
1795 }
1796 
1797 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1798  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1799 }
1800 
1802  return MaximumJumpTableSize;
1803 }
1804 
1806  MaximumJumpTableSize = Val;
1807 }
1808 
1809 //===----------------------------------------------------------------------===//
1810 // Reciprocal Estimates
1811 //===----------------------------------------------------------------------===//
1812 
1813 /// Get the reciprocal estimate attribute string for a function that will
1814 /// override the target defaults.
1816  const Function &F = MF.getFunction();
1817  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1818 }
1819 
1820 /// Construct a string for the given reciprocal operation of the given type.
1821 /// This string should match the corresponding option to the front-end's
1822 /// "-mrecip" flag assuming those strings have been passed through in an
1823 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1824 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1825  std::string Name = VT.isVector() ? "vec-" : "";
1826 
1827  Name += IsSqrt ? "sqrt" : "div";
1828 
1829  // TODO: Handle "half" or other float types?
1830  if (VT.getScalarType() == MVT::f64) {
1831  Name += "d";
1832  } else {
1833  assert(VT.getScalarType() == MVT::f32 &&
1834  "Unexpected FP type for reciprocal estimate");
1835  Name += "f";
1836  }
1837 
1838  return Name;
1839 }
1840 
1841 /// Return the character position and value (a single numeric character) of a
1842 /// customized refinement operation in the input string if it exists. Return
1843 /// false if there is no customized refinement step count.
1845  uint8_t &Value) {
1846  const char RefStepToken = ':';
1847  Position = In.find(RefStepToken);
1848  if (Position == StringRef::npos)
1849  return false;
1850 
1851  StringRef RefStepString = In.substr(Position + 1);
1852  // Allow exactly one numeric character for the additional refinement
1853  // step parameter.
1854  if (RefStepString.size() == 1) {
1855  char RefStepChar = RefStepString[0];
1856  if (RefStepChar >= '0' && RefStepChar <= '9') {
1857  Value = RefStepChar - '0';
1858  return true;
1859  }
1860  }
1861  report_fatal_error("Invalid refinement step for -recip.");
1862 }
1863 
1864 /// For the input attribute string, return one of the ReciprocalEstimate enum
1865 /// status values (enabled, disabled, or not specified) for this operation on
1866 /// the specified data type.
1867 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1868  if (Override.empty())
1869  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1870 
1871  SmallVector<StringRef, 4> OverrideVector;
1872  Override.split(OverrideVector, ',');
1873  unsigned NumArgs = OverrideVector.size();
1874 
1875  // Check if "all", "none", or "default" was specified.
1876  if (NumArgs == 1) {
1877  // Look for an optional setting of the number of refinement steps needed
1878  // for this type of reciprocal operation.
1879  size_t RefPos;
1880  uint8_t RefSteps;
1881  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1882  // Split the string for further processing.
1883  Override = Override.substr(0, RefPos);
1884  }
1885 
1886  // All reciprocal types are enabled.
1887  if (Override == "all")
1889 
1890  // All reciprocal types are disabled.
1891  if (Override == "none")
1892  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1893 
1894  // Target defaults for enablement are used.
1895  if (Override == "default")
1896  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1897  }
1898 
1899  // The attribute string may omit the size suffix ('f'/'d').
1900  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1901  std::string VTNameNoSize = VTName;
1902  VTNameNoSize.pop_back();
1903  static const char DisabledPrefix = '!';
1904 
1905  for (StringRef RecipType : OverrideVector) {
1906  size_t RefPos;
1907  uint8_t RefSteps;
1908  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1909  RecipType = RecipType.substr(0, RefPos);
1910 
1911  // Ignore the disablement token for string matching.
1912  bool IsDisabled = RecipType[0] == DisabledPrefix;
1913  if (IsDisabled)
1914  RecipType = RecipType.substr(1);
1915 
1916  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1917  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1919  }
1920 
1921  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1922 }
1923 
1924 /// For the input attribute string, return the customized refinement step count
1925 /// for this operation on the specified data type. If the step count does not
1926 /// exist, return the ReciprocalEstimate enum value for unspecified.
1927 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1928  if (Override.empty())
1929  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1930 
1931  SmallVector<StringRef, 4> OverrideVector;
1932  Override.split(OverrideVector, ',');
1933  unsigned NumArgs = OverrideVector.size();
1934 
1935  // Check if "all", "default", or "none" was specified.
1936  if (NumArgs == 1) {
1937  // Look for an optional setting of the number of refinement steps needed
1938  // for this type of reciprocal operation.
1939  size_t RefPos;
1940  uint8_t RefSteps;
1941  if (!parseRefinementStep(Override, RefPos, RefSteps))
1942  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1943 
1944  // Split the string for further processing.
1945  Override = Override.substr(0, RefPos);
1946  assert(Override != "none" &&
1947  "Disabled reciprocals, but specifed refinement steps?");
1948 
1949  // If this is a general override, return the specified number of steps.
1950  if (Override == "all" || Override == "default")
1951  return RefSteps;
1952  }
1953 
1954  // The attribute string may omit the size suffix ('f'/'d').
1955  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1956  std::string VTNameNoSize = VTName;
1957  VTNameNoSize.pop_back();
1958 
1959  for (StringRef RecipType : OverrideVector) {
1960  size_t RefPos;
1961  uint8_t RefSteps;
1962  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1963  continue;
1964 
1965  RecipType = RecipType.substr(0, RefPos);
1966  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1967  return RefSteps;
1968  }
1969 
1970  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1971 }
1972 
1974  MachineFunction &MF) const {
1975  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1976 }
1977 
1979  MachineFunction &MF) const {
1980  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1981 }
1982 
1984  MachineFunction &MF) const {
1985  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1986 }
1987 
1989  MachineFunction &MF) const {
1990  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1991 }
1992 
1994  MF.getRegInfo().freezeReservedRegs(MF);
1995 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:596
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:570
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:623
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
LLVMContext & Context
unsigned getAddrSpace() const
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:453
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:634
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:399
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:551
bool isVector() const
Return true if this is a vector value type.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:170
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:48
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:834
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:393
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
bool isOSFuchsia() const
Definition: Triple.h:505
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:540
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:416
Same for subtraction.
Definition: ISDOpcodes.h:253
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:348
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:365
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:442
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:425
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:659
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:842
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:592
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:510
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:126
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1013
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:331
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:779
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:529
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:575
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:556
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:902
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:465
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
bool isOSOpenBSD() const
Definition: Triple.h:497
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:654
bool isWatchABI() const
Definition: Triple.h:476
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:364
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:299
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:663
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:648
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:799
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:802
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:724
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:448
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:828
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:581
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:33
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:672
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:52
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:224
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:316
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:371
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:483
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:600
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:710
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:755
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:629
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
FunctionCallee getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:452
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:240
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:500
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:503
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:344
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Flags
Flags values. These may be or&#39;d together.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:893
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:64
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:204
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:419
static const size_t npos
Definition: StringRef.h:50
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:643
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:521
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:326
Same for multiplication.
Definition: ISDOpcodes.h:256
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:959
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2238
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:438
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:377
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:831
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:74
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:908
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:904
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:107
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:808
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:338
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:475
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:414
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:497
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:506
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:611
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:310
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:241
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...