LLVM  8.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLoweringBase class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalValue.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/IRBuilder.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
55 #include <algorithm>
56 #include <cassert>
57 #include <cstddef>
58 #include <cstdint>
59 #include <cstring>
60 #include <iterator>
61 #include <string>
62 #include <tuple>
63 #include <utility>
64 
65 using namespace llvm;
66 
68  "jump-is-expensive", cl::init(false),
69  cl::desc("Do not create extra branches to split comparison logic."),
70  cl::Hidden);
71 
73  ("min-jump-table-entries", cl::init(4), cl::Hidden,
74  cl::desc("Set minimum number of entries to use a jump table."));
75 
77  ("max-jump-table-size", cl::init(0), cl::Hidden,
78  cl::desc("Set maximum size of jump tables; zero for no limit."));
79 
80 /// Minimum jump table density for normal functions.
81 static cl::opt<unsigned>
82  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
83  cl::desc("Minimum density for building a jump table in "
84  "a normal function"));
85 
86 /// Minimum jump table density for -Os or -Oz functions.
88  "optsize-jump-table-density", cl::init(40), cl::Hidden,
89  cl::desc("Minimum density for building a jump table in "
90  "an optsize function"));
91 
92 static bool darwinHasSinCos(const Triple &TT) {
93  assert(TT.isOSDarwin() && "should be called with darwin triple");
94  // Don't bother with 32 bit x86.
95  if (TT.getArch() == Triple::x86)
96  return false;
97  // Macos < 10.9 has no sincos_stret.
98  if (TT.isMacOSX())
99  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
100  // iOS < 7.0 has no sincos_stret.
101  if (TT.isiOS())
102  return !TT.isOSVersionLT(7, 0);
103  // Any other darwin such as WatchOS/TvOS is new enough.
104  return true;
105 }
106 
107 // Although this default value is arbitrary, it is not random. It is assumed
108 // that a condition that evaluates the same way by a higher percentage than this
109 // is best represented as control flow. Therefore, the default value N should be
110 // set such that the win from N% correct executions is greater than the loss
111 // from (100 - N)% mispredicted executions for the majority of intended targets.
113  "min-predictable-branch", cl::init(99),
114  cl::desc("Minimum percentage (0-100) that a condition must be either true "
115  "or false to assume that the condition is predictable"),
116  cl::Hidden);
117 
118 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
119 #define HANDLE_LIBCALL(code, name) \
120  setLibcallName(RTLIB::code, name);
121 #include "llvm/IR/RuntimeLibcalls.def"
122 #undef HANDLE_LIBCALL
123  // Initialize calling conventions to their default.
124  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
126 
127  // A few names are different on particular architectures or environments.
128  if (TT.isOSDarwin()) {
129  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
130  // of the gnueabi-style __gnu_*_ieee.
131  // FIXME: What about other targets?
132  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
133  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
134 
135  // Some darwins have an optimized __bzero/bzero function.
136  switch (TT.getArch()) {
137  case Triple::x86:
138  case Triple::x86_64:
139  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
140  setLibcallName(RTLIB::BZERO, "__bzero");
141  break;
142  case Triple::aarch64:
143  setLibcallName(RTLIB::BZERO, "bzero");
144  break;
145  default:
146  break;
147  }
148 
149  if (darwinHasSinCos(TT)) {
150  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
151  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
152  if (TT.isWatchABI()) {
153  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
155  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
157  }
158  }
159  } else {
160  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
161  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
162  }
163 
164  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
165  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
166  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
167  setLibcallName(RTLIB::SINCOS_F64, "sincos");
168  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
169  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
170  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
171  }
172 
173  if (TT.isOSOpenBSD()) {
174  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
175  }
176 }
177 
178 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
179 /// UNKNOWN_LIBCALL if there is none.
181  if (OpVT == MVT::f16) {
182  if (RetVT == MVT::f32)
183  return FPEXT_F16_F32;
184  } else if (OpVT == MVT::f32) {
185  if (RetVT == MVT::f64)
186  return FPEXT_F32_F64;
187  if (RetVT == MVT::f128)
188  return FPEXT_F32_F128;
189  if (RetVT == MVT::ppcf128)
190  return FPEXT_F32_PPCF128;
191  } else if (OpVT == MVT::f64) {
192  if (RetVT == MVT::f128)
193  return FPEXT_F64_F128;
194  else if (RetVT == MVT::ppcf128)
195  return FPEXT_F64_PPCF128;
196  } else if (OpVT == MVT::f80) {
197  if (RetVT == MVT::f128)
198  return FPEXT_F80_F128;
199  }
200 
201  return UNKNOWN_LIBCALL;
202 }
203 
204 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
205 /// UNKNOWN_LIBCALL if there is none.
207  if (RetVT == MVT::f16) {
208  if (OpVT == MVT::f32)
209  return FPROUND_F32_F16;
210  if (OpVT == MVT::f64)
211  return FPROUND_F64_F16;
212  if (OpVT == MVT::f80)
213  return FPROUND_F80_F16;
214  if (OpVT == MVT::f128)
215  return FPROUND_F128_F16;
216  if (OpVT == MVT::ppcf128)
217  return FPROUND_PPCF128_F16;
218  } else if (RetVT == MVT::f32) {
219  if (OpVT == MVT::f64)
220  return FPROUND_F64_F32;
221  if (OpVT == MVT::f80)
222  return FPROUND_F80_F32;
223  if (OpVT == MVT::f128)
224  return FPROUND_F128_F32;
225  if (OpVT == MVT::ppcf128)
226  return FPROUND_PPCF128_F32;
227  } else if (RetVT == MVT::f64) {
228  if (OpVT == MVT::f80)
229  return FPROUND_F80_F64;
230  if (OpVT == MVT::f128)
231  return FPROUND_F128_F64;
232  if (OpVT == MVT::ppcf128)
233  return FPROUND_PPCF128_F64;
234  } else if (RetVT == MVT::f80) {
235  if (OpVT == MVT::f128)
236  return FPROUND_F128_F80;
237  }
238 
239  return UNKNOWN_LIBCALL;
240 }
241 
242 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
243 /// UNKNOWN_LIBCALL if there is none.
245  if (OpVT == MVT::f32) {
246  if (RetVT == MVT::i32)
247  return FPTOSINT_F32_I32;
248  if (RetVT == MVT::i64)
249  return FPTOSINT_F32_I64;
250  if (RetVT == MVT::i128)
251  return FPTOSINT_F32_I128;
252  } else if (OpVT == MVT::f64) {
253  if (RetVT == MVT::i32)
254  return FPTOSINT_F64_I32;
255  if (RetVT == MVT::i64)
256  return FPTOSINT_F64_I64;
257  if (RetVT == MVT::i128)
258  return FPTOSINT_F64_I128;
259  } else if (OpVT == MVT::f80) {
260  if (RetVT == MVT::i32)
261  return FPTOSINT_F80_I32;
262  if (RetVT == MVT::i64)
263  return FPTOSINT_F80_I64;
264  if (RetVT == MVT::i128)
265  return FPTOSINT_F80_I128;
266  } else if (OpVT == MVT::f128) {
267  if (RetVT == MVT::i32)
268  return FPTOSINT_F128_I32;
269  if (RetVT == MVT::i64)
270  return FPTOSINT_F128_I64;
271  if (RetVT == MVT::i128)
272  return FPTOSINT_F128_I128;
273  } else if (OpVT == MVT::ppcf128) {
274  if (RetVT == MVT::i32)
275  return FPTOSINT_PPCF128_I32;
276  if (RetVT == MVT::i64)
277  return FPTOSINT_PPCF128_I64;
278  if (RetVT == MVT::i128)
279  return FPTOSINT_PPCF128_I128;
280  }
281  return UNKNOWN_LIBCALL;
282 }
283 
284 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
285 /// UNKNOWN_LIBCALL if there is none.
287  if (OpVT == MVT::f32) {
288  if (RetVT == MVT::i32)
289  return FPTOUINT_F32_I32;
290  if (RetVT == MVT::i64)
291  return FPTOUINT_F32_I64;
292  if (RetVT == MVT::i128)
293  return FPTOUINT_F32_I128;
294  } else if (OpVT == MVT::f64) {
295  if (RetVT == MVT::i32)
296  return FPTOUINT_F64_I32;
297  if (RetVT == MVT::i64)
298  return FPTOUINT_F64_I64;
299  if (RetVT == MVT::i128)
300  return FPTOUINT_F64_I128;
301  } else if (OpVT == MVT::f80) {
302  if (RetVT == MVT::i32)
303  return FPTOUINT_F80_I32;
304  if (RetVT == MVT::i64)
305  return FPTOUINT_F80_I64;
306  if (RetVT == MVT::i128)
307  return FPTOUINT_F80_I128;
308  } else if (OpVT == MVT::f128) {
309  if (RetVT == MVT::i32)
310  return FPTOUINT_F128_I32;
311  if (RetVT == MVT::i64)
312  return FPTOUINT_F128_I64;
313  if (RetVT == MVT::i128)
314  return FPTOUINT_F128_I128;
315  } else if (OpVT == MVT::ppcf128) {
316  if (RetVT == MVT::i32)
317  return FPTOUINT_PPCF128_I32;
318  if (RetVT == MVT::i64)
319  return FPTOUINT_PPCF128_I64;
320  if (RetVT == MVT::i128)
321  return FPTOUINT_PPCF128_I128;
322  }
323  return UNKNOWN_LIBCALL;
324 }
325 
326 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
327 /// UNKNOWN_LIBCALL if there is none.
329  if (OpVT == MVT::i32) {
330  if (RetVT == MVT::f32)
331  return SINTTOFP_I32_F32;
332  if (RetVT == MVT::f64)
333  return SINTTOFP_I32_F64;
334  if (RetVT == MVT::f80)
335  return SINTTOFP_I32_F80;
336  if (RetVT == MVT::f128)
337  return SINTTOFP_I32_F128;
338  if (RetVT == MVT::ppcf128)
339  return SINTTOFP_I32_PPCF128;
340  } else if (OpVT == MVT::i64) {
341  if (RetVT == MVT::f32)
342  return SINTTOFP_I64_F32;
343  if (RetVT == MVT::f64)
344  return SINTTOFP_I64_F64;
345  if (RetVT == MVT::f80)
346  return SINTTOFP_I64_F80;
347  if (RetVT == MVT::f128)
348  return SINTTOFP_I64_F128;
349  if (RetVT == MVT::ppcf128)
350  return SINTTOFP_I64_PPCF128;
351  } else if (OpVT == MVT::i128) {
352  if (RetVT == MVT::f32)
353  return SINTTOFP_I128_F32;
354  if (RetVT == MVT::f64)
355  return SINTTOFP_I128_F64;
356  if (RetVT == MVT::f80)
357  return SINTTOFP_I128_F80;
358  if (RetVT == MVT::f128)
359  return SINTTOFP_I128_F128;
360  if (RetVT == MVT::ppcf128)
361  return SINTTOFP_I128_PPCF128;
362  }
363  return UNKNOWN_LIBCALL;
364 }
365 
366 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
367 /// UNKNOWN_LIBCALL if there is none.
369  if (OpVT == MVT::i32) {
370  if (RetVT == MVT::f32)
371  return UINTTOFP_I32_F32;
372  if (RetVT == MVT::f64)
373  return UINTTOFP_I32_F64;
374  if (RetVT == MVT::f80)
375  return UINTTOFP_I32_F80;
376  if (RetVT == MVT::f128)
377  return UINTTOFP_I32_F128;
378  if (RetVT == MVT::ppcf128)
379  return UINTTOFP_I32_PPCF128;
380  } else if (OpVT == MVT::i64) {
381  if (RetVT == MVT::f32)
382  return UINTTOFP_I64_F32;
383  if (RetVT == MVT::f64)
384  return UINTTOFP_I64_F64;
385  if (RetVT == MVT::f80)
386  return UINTTOFP_I64_F80;
387  if (RetVT == MVT::f128)
388  return UINTTOFP_I64_F128;
389  if (RetVT == MVT::ppcf128)
390  return UINTTOFP_I64_PPCF128;
391  } else if (OpVT == MVT::i128) {
392  if (RetVT == MVT::f32)
393  return UINTTOFP_I128_F32;
394  if (RetVT == MVT::f64)
395  return UINTTOFP_I128_F64;
396  if (RetVT == MVT::f80)
397  return UINTTOFP_I128_F80;
398  if (RetVT == MVT::f128)
399  return UINTTOFP_I128_F128;
400  if (RetVT == MVT::ppcf128)
401  return UINTTOFP_I128_PPCF128;
402  }
403  return UNKNOWN_LIBCALL;
404 }
405 
406 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
407 #define OP_TO_LIBCALL(Name, Enum) \
408  case Name: \
409  switch (VT.SimpleTy) { \
410  default: \
411  return UNKNOWN_LIBCALL; \
412  case MVT::i8: \
413  return Enum##_1; \
414  case MVT::i16: \
415  return Enum##_2; \
416  case MVT::i32: \
417  return Enum##_4; \
418  case MVT::i64: \
419  return Enum##_8; \
420  case MVT::i128: \
421  return Enum##_16; \
422  }
423 
424  switch (Opc) {
425  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
426  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
427  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
428  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
429  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
430  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
431  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
432  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
433  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
434  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
435  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
436  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
437  }
438 
439 #undef OP_TO_LIBCALL
440 
441  return UNKNOWN_LIBCALL;
442 }
443 
445  switch (ElementSize) {
446  case 1:
447  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
448  case 2:
449  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
450  case 4:
451  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
452  case 8:
453  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
454  case 16:
455  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
456  default:
457  return UNKNOWN_LIBCALL;
458  }
459 }
460 
462  switch (ElementSize) {
463  case 1:
464  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
465  case 2:
466  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
467  case 4:
468  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
469  case 8:
470  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
471  case 16:
472  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
473  default:
474  return UNKNOWN_LIBCALL;
475  }
476 }
477 
479  switch (ElementSize) {
480  case 1:
481  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
482  case 2:
483  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
484  case 4:
485  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
486  case 8:
487  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
488  case 16:
489  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
490  default:
491  return UNKNOWN_LIBCALL;
492  }
493 }
494 
495 /// InitCmpLibcallCCs - Set default comparison libcall CC.
496 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
497  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
498  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
499  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
500  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
501  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
502  CCs[RTLIB::UNE_F32] = ISD::SETNE;
503  CCs[RTLIB::UNE_F64] = ISD::SETNE;
504  CCs[RTLIB::UNE_F128] = ISD::SETNE;
505  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
506  CCs[RTLIB::OGE_F32] = ISD::SETGE;
507  CCs[RTLIB::OGE_F64] = ISD::SETGE;
508  CCs[RTLIB::OGE_F128] = ISD::SETGE;
509  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
510  CCs[RTLIB::OLT_F32] = ISD::SETLT;
511  CCs[RTLIB::OLT_F64] = ISD::SETLT;
512  CCs[RTLIB::OLT_F128] = ISD::SETLT;
513  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
514  CCs[RTLIB::OLE_F32] = ISD::SETLE;
515  CCs[RTLIB::OLE_F64] = ISD::SETLE;
516  CCs[RTLIB::OLE_F128] = ISD::SETLE;
517  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
518  CCs[RTLIB::OGT_F32] = ISD::SETGT;
519  CCs[RTLIB::OGT_F64] = ISD::SETGT;
520  CCs[RTLIB::OGT_F128] = ISD::SETGT;
521  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
522  CCs[RTLIB::UO_F32] = ISD::SETNE;
523  CCs[RTLIB::UO_F64] = ISD::SETNE;
524  CCs[RTLIB::UO_F128] = ISD::SETNE;
525  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
526  CCs[RTLIB::O_F32] = ISD::SETEQ;
527  CCs[RTLIB::O_F64] = ISD::SETEQ;
528  CCs[RTLIB::O_F128] = ISD::SETEQ;
529  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
530 }
531 
532 /// NOTE: The TargetMachine owns TLOF.
534  initActions();
535 
536  // Perform these initializations only once.
538  MaxLoadsPerMemcmp = 8;
542  UseUnderscoreSetJmp = false;
543  UseUnderscoreLongJmp = false;
544  HasMultipleConditionRegisters = false;
545  HasExtractBitsInsn = false;
546  JumpIsExpensive = JumpIsExpensiveOverride;
548  EnableExtLdPromotion = false;
549  HasFloatingPointExceptions = true;
550  StackPointerRegisterToSaveRestore = 0;
551  BooleanContents = UndefinedBooleanContent;
552  BooleanFloatContents = UndefinedBooleanContent;
553  BooleanVectorContents = UndefinedBooleanContent;
554  SchedPreferenceInfo = Sched::ILP;
555  JumpBufSize = 0;
556  JumpBufAlignment = 0;
557  MinFunctionAlignment = 0;
558  PrefFunctionAlignment = 0;
559  PrefLoopAlignment = 0;
561  MinStackArgumentAlignment = 1;
562  // TODO: the default will be switched to 0 in the next commit, along
563  // with the Target-specific changes necessary.
564  MaxAtomicSizeInBitsSupported = 1024;
565 
566  MinCmpXchgSizeInBits = 0;
567  SupportsUnalignedAtomics = false;
568 
569  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
570 
571  InitLibcalls(TM.getTargetTriple());
572  InitCmpLibcallCCs(CmpLibcallCCs);
573 }
574 
576  // All operations default to being supported.
577  memset(OpActions, 0, sizeof(OpActions));
578  memset(LoadExtActions, 0, sizeof(LoadExtActions));
579  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
580  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
581  memset(CondCodeActions, 0, sizeof(CondCodeActions));
582  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
583  std::fill(std::begin(TargetDAGCombineArray),
584  std::end(TargetDAGCombineArray), 0);
585 
586  // Set default actions for various operations.
587  for (MVT VT : MVT::all_valuetypes()) {
588  // Default all indexed load / store to expand.
589  for (unsigned IM = (unsigned)ISD::PRE_INC;
590  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
591  setIndexedLoadAction(IM, VT, Expand);
592  setIndexedStoreAction(IM, VT, Expand);
593  }
594 
595  // Most backends expect to see the node which just returns the value loaded.
597 
598  // These operations default to expand.
620 
621  // Overflow operations default to expand
628 
629  // ADDCARRY operations default to expand
633 
634  // ADDC/ADDE/SUBC/SUBE default to expand.
639 
640  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
643 
645 
646  // These library functions default to expand.
649 
650  // These operations default to expand for vector types.
651  if (VT.isVector()) {
656  }
657 
658  // For most targets @llvm.get.dynamic.area.offset just returns 0.
660  }
661 
662  // Most targets ignore the @llvm.prefetch intrinsic.
664 
665  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
667 
668  // ConstantFP nodes default to expand. Targets can either change this to
669  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
670  // to optimize expansions for certain constants.
676 
677  // These library functions default to expand.
678  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
691  }
692 
693  // Default ISD::TRAP to expand (which turns it into abort).
695 
696  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
697  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
699 }
700 
702  EVT) const {
703  return MVT::getIntegerVT(8 * DL.getPointerSize(0));
704 }
705 
707  bool LegalTypes) const {
708  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
709  if (LHSTy.isVector())
710  return LHSTy;
711  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
712  : getPointerTy(DL);
713 }
714 
715 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
716  assert(isTypeLegal(VT));
717  switch (Op) {
718  default:
719  return false;
720  case ISD::SDIV:
721  case ISD::UDIV:
722  case ISD::SREM:
723  case ISD::UREM:
724  return true;
725  }
726 }
727 
729  // If the command-line option was specified, ignore this request.
730  if (!JumpIsExpensiveOverride.getNumOccurrences())
731  JumpIsExpensive = isExpensive;
732 }
733 
735 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
736  // If this is a simple type, use the ComputeRegisterProp mechanism.
737  if (VT.isSimple()) {
738  MVT SVT = VT.getSimpleVT();
739  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
740  MVT NVT = TransformToType[SVT.SimpleTy];
742 
743  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
745  "Promote may not follow Expand or Promote");
746 
747  if (LA == TypeSplitVector)
748  return LegalizeKind(LA,
749  EVT::getVectorVT(Context, SVT.getVectorElementType(),
750  SVT.getVectorNumElements() / 2));
751  if (LA == TypeScalarizeVector)
752  return LegalizeKind(LA, SVT.getVectorElementType());
753  return LegalizeKind(LA, NVT);
754  }
755 
756  // Handle Extended Scalar Types.
757  if (!VT.isVector()) {
758  assert(VT.isInteger() && "Float types must be simple");
759  unsigned BitSize = VT.getSizeInBits();
760  // First promote to a power-of-two size, then expand if necessary.
761  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
762  EVT NVT = VT.getRoundIntegerType(Context);
763  assert(NVT != VT && "Unable to round integer VT");
764  LegalizeKind NextStep = getTypeConversion(Context, NVT);
765  // Avoid multi-step promotion.
766  if (NextStep.first == TypePromoteInteger)
767  return NextStep;
768  // Return rounded integer type.
769  return LegalizeKind(TypePromoteInteger, NVT);
770  }
771 
773  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
774  }
775 
776  // Handle vector types.
777  unsigned NumElts = VT.getVectorNumElements();
778  EVT EltVT = VT.getVectorElementType();
779 
780  // Vectors with only one element are always scalarized.
781  if (NumElts == 1)
782  return LegalizeKind(TypeScalarizeVector, EltVT);
783 
784  // Try to widen vector elements until the element type is a power of two and
785  // promote it to a legal type later on, for example:
786  // <3 x i8> -> <4 x i8> -> <4 x i32>
787  if (EltVT.isInteger()) {
788  // Vectors with a number of elements that is not a power of two are always
789  // widened, for example <3 x i8> -> <4 x i8>.
790  if (!VT.isPow2VectorType()) {
791  NumElts = (unsigned)NextPowerOf2(NumElts);
792  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
793  return LegalizeKind(TypeWidenVector, NVT);
794  }
795 
796  // Examine the element type.
797  LegalizeKind LK = getTypeConversion(Context, EltVT);
798 
799  // If type is to be expanded, split the vector.
800  // <4 x i140> -> <2 x i140>
801  if (LK.first == TypeExpandInteger)
803  EVT::getVectorVT(Context, EltVT, NumElts / 2));
804 
805  // Promote the integer element types until a legal vector type is found
806  // or until the element integer type is too big. If a legal type was not
807  // found, fallback to the usual mechanism of widening/splitting the
808  // vector.
809  EVT OldEltVT = EltVT;
810  while (true) {
811  // Increase the bitwidth of the element to the next pow-of-two
812  // (which is greater than 8 bits).
813  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
814  .getRoundIntegerType(Context);
815 
816  // Stop trying when getting a non-simple element type.
817  // Note that vector elements may be greater than legal vector element
818  // types. Example: X86 XMM registers hold 64bit element on 32bit
819  // systems.
820  if (!EltVT.isSimple())
821  break;
822 
823  // Build a new vector type and check if it is legal.
824  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
825  // Found a legal promoted vector type.
826  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
828  EVT::getVectorVT(Context, EltVT, NumElts));
829  }
830 
831  // Reset the type to the unexpanded type if we did not find a legal vector
832  // type with a promoted vector element type.
833  EltVT = OldEltVT;
834  }
835 
836  // Try to widen the vector until a legal type is found.
837  // If there is no wider legal type, split the vector.
838  while (true) {
839  // Round up to the next power of 2.
840  NumElts = (unsigned)NextPowerOf2(NumElts);
841 
842  // If there is no simple vector type with this many elements then there
843  // cannot be a larger legal vector type. Note that this assumes that
844  // there are no skipped intermediate vector types in the simple types.
845  if (!EltVT.isSimple())
846  break;
847  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
848  if (LargerVector == MVT())
849  break;
850 
851  // If this type is legal then widen the vector.
852  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
853  return LegalizeKind(TypeWidenVector, LargerVector);
854  }
855 
856  // Widen odd vectors to next power of two.
857  if (!VT.isPow2VectorType()) {
858  EVT NVT = VT.getPow2VectorType(Context);
859  return LegalizeKind(TypeWidenVector, NVT);
860  }
861 
862  // Vectors with illegal element types are expanded.
863  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
864  return LegalizeKind(TypeSplitVector, NVT);
865 }
866 
867 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
868  unsigned &NumIntermediates,
869  MVT &RegisterVT,
870  TargetLoweringBase *TLI) {
871  // Figure out the right, legal destination reg to copy into.
872  unsigned NumElts = VT.getVectorNumElements();
873  MVT EltTy = VT.getVectorElementType();
874 
875  unsigned NumVectorRegs = 1;
876 
877  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
878  // could break down into LHS/RHS like LegalizeDAG does.
879  if (!isPowerOf2_32(NumElts)) {
880  NumVectorRegs = NumElts;
881  NumElts = 1;
882  }
883 
884  // Divide the input until we get to a supported size. This will always
885  // end with a scalar if the target doesn't support vectors.
886  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
887  NumElts >>= 1;
888  NumVectorRegs <<= 1;
889  }
890 
891  NumIntermediates = NumVectorRegs;
892 
893  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
894  if (!TLI->isTypeLegal(NewVT))
895  NewVT = EltTy;
896  IntermediateVT = NewVT;
897 
898  unsigned NewVTSize = NewVT.getSizeInBits();
899 
900  // Convert sizes such as i33 to i64.
901  if (!isPowerOf2_32(NewVTSize))
902  NewVTSize = NextPowerOf2(NewVTSize);
903 
904  MVT DestVT = TLI->getRegisterType(NewVT);
905  RegisterVT = DestVT;
906  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
907  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
908 
909  // Otherwise, promotion or legal types use the same number of registers as
910  // the vector decimated to the appropriate level.
911  return NumVectorRegs;
912 }
913 
914 /// isLegalRC - Return true if the value types that can be represented by the
915 /// specified register class are all legal.
917  const TargetRegisterClass &RC) const {
918  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
919  if (isTypeLegal(*I))
920  return true;
921  return false;
922 }
923 
924 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
925 /// sequence of memory operands that is recognized by PrologEpilogInserter.
928  MachineBasicBlock *MBB) const {
929  MachineInstr *MI = &InitialMI;
930  MachineFunction &MF = *MI->getMF();
931  MachineFrameInfo &MFI = MF.getFrameInfo();
932 
933  // We're handling multiple types of operands here:
934  // PATCHPOINT MetaArgs - live-in, read only, direct
935  // STATEPOINT Deopt Spill - live-through, read only, indirect
936  // STATEPOINT Deopt Alloca - live-through, read only, direct
937  // (We're currently conservative and mark the deopt slots read/write in
938  // practice.)
939  // STATEPOINT GC Spill - live-through, read/write, indirect
940  // STATEPOINT GC Alloca - live-through, read/write, direct
941  // The live-in vs live-through is handled already (the live through ones are
942  // all stack slots), but we need to handle the different type of stackmap
943  // operands and memory effects here.
944 
945  // MI changes inside this loop as we grow operands.
946  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
947  MachineOperand &MO = MI->getOperand(OperIdx);
948  if (!MO.isFI())
949  continue;
950 
951  // foldMemoryOperand builds a new MI after replacing a single FI operand
952  // with the canonical set of five x86 addressing-mode operands.
953  int FI = MO.getIndex();
954  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
955 
956  // Copy operands before the frame-index.
957  for (unsigned i = 0; i < OperIdx; ++i)
958  MIB.add(MI->getOperand(i));
959  // Add frame index operands recognized by stackmaps.cpp
960  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
961  // indirect-mem-ref tag, size, #FI, offset.
962  // Used for spills inserted by StatepointLowering. This codepath is not
963  // used for patchpoints/stackmaps at all, for these spilling is done via
964  // foldMemoryOperand callback only.
965  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
966  MIB.addImm(StackMaps::IndirectMemRefOp);
967  MIB.addImm(MFI.getObjectSize(FI));
968  MIB.add(MI->getOperand(OperIdx));
969  MIB.addImm(0);
970  } else {
971  // direct-mem-ref tag, #FI, offset.
972  // Used by patchpoint, and direct alloca arguments to statepoints
973  MIB.addImm(StackMaps::DirectMemRefOp);
974  MIB.add(MI->getOperand(OperIdx));
975  MIB.addImm(0);
976  }
977  // Copy the operands after the frame index.
978  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
979  MIB.add(MI->getOperand(i));
980 
981  // Inherit previous memory operands.
982  MIB.cloneMemRefs(*MI);
983  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
984 
985  // Add a new memory operand for this FI.
986  assert(MFI.getObjectOffset(FI) != -1);
987 
988  auto Flags = MachineMemOperand::MOLoad;
989  if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
992  }
994  MachinePointerInfo::getFixedStack(MF, FI), Flags,
996  MIB->addMemOperand(MF, MMO);
997 
998  // Replace the instruction and update the operand index.
999  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1000  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1001  MI->eraseFromParent();
1002  MI = MIB;
1003  }
1004  return MBB;
1005 }
1006 
1009  MachineBasicBlock *MBB) const {
1010  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1011  "Called emitXRayCustomEvent on the wrong MI!");
1012  auto &MF = *MI.getMF();
1013  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1014  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1015  MIB.add(MI.getOperand(OpIdx));
1016 
1017  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1018  MI.eraseFromParent();
1019  return MBB;
1020 }
1021 
1024  MachineBasicBlock *MBB) const {
1025  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1026  "Called emitXRayTypedEvent on the wrong MI!");
1027  auto &MF = *MI.getMF();
1028  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1029  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1030  MIB.add(MI.getOperand(OpIdx));
1031 
1032  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1033  MI.eraseFromParent();
1034  return MBB;
1035 }
1036 
1037 /// findRepresentativeClass - Return the largest legal super-reg register class
1038 /// of the register class for the specified type and its associated "cost".
1039 // This function is in TargetLowering because it uses RegClassForVT which would
1040 // need to be moved to TargetRegisterInfo and would necessitate moving
1041 // isTypeLegal over as well - a massive change that would just require
1042 // TargetLowering having a TargetRegisterInfo class member that it would use.
1043 std::pair<const TargetRegisterClass *, uint8_t>
1045  MVT VT) const {
1046  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1047  if (!RC)
1048  return std::make_pair(RC, 0);
1049 
1050  // Compute the set of all super-register classes.
1051  BitVector SuperRegRC(TRI->getNumRegClasses());
1052  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1053  SuperRegRC.setBitsInMask(RCI.getMask());
1054 
1055  // Find the first legal register class with the largest spill size.
1056  const TargetRegisterClass *BestRC = RC;
1057  for (unsigned i : SuperRegRC.set_bits()) {
1058  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1059  // We want the largest possible spill size.
1060  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1061  continue;
1062  if (!isLegalRC(*TRI, *SuperRC))
1063  continue;
1064  BestRC = SuperRC;
1065  }
1066  return std::make_pair(BestRC, 1);
1067 }
1068 
1069 /// computeRegisterProperties - Once all of the register classes are added,
1070 /// this allows us to compute derived properties we expose.
1072  const TargetRegisterInfo *TRI) {
1074  "Too many value types for ValueTypeActions to hold!");
1075 
1076  // Everything defaults to needing one register.
1077  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1078  NumRegistersForVT[i] = 1;
1079  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1080  }
1081  // ...except isVoid, which doesn't need any registers.
1082  NumRegistersForVT[MVT::isVoid] = 0;
1083 
1084  // Find the largest integer register class.
1085  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1086  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1087  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1088 
1089  // Every integer value type larger than this largest register takes twice as
1090  // many registers to represent as the previous ValueType.
1091  for (unsigned ExpandedReg = LargestIntReg + 1;
1092  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1093  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1094  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1095  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1098  }
1099 
1100  // Inspect all of the ValueType's smaller than the largest integer
1101  // register to see which ones need promotion.
1102  unsigned LegalIntReg = LargestIntReg;
1103  for (unsigned IntReg = LargestIntReg - 1;
1104  IntReg >= (unsigned)MVT::i1; --IntReg) {
1105  MVT IVT = (MVT::SimpleValueType)IntReg;
1106  if (isTypeLegal(IVT)) {
1107  LegalIntReg = IntReg;
1108  } else {
1109  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1110  (MVT::SimpleValueType)LegalIntReg;
1112  }
1113  }
1114 
1115  // ppcf128 type is really two f64's.
1116  if (!isTypeLegal(MVT::ppcf128)) {
1117  if (isTypeLegal(MVT::f64)) {
1118  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1119  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1120  TransformToType[MVT::ppcf128] = MVT::f64;
1122  } else {
1123  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1124  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1125  TransformToType[MVT::ppcf128] = MVT::i128;
1127  }
1128  }
1129 
1130  // Decide how to handle f128. If the target does not have native f128 support,
1131  // expand it to i128 and we will be generating soft float library calls.
1132  if (!isTypeLegal(MVT::f128)) {
1133  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1134  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1135  TransformToType[MVT::f128] = MVT::i128;
1137  }
1138 
1139  // Decide how to handle f64. If the target does not have native f64 support,
1140  // expand it to i64 and we will be generating soft float library calls.
1141  if (!isTypeLegal(MVT::f64)) {
1142  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1143  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1144  TransformToType[MVT::f64] = MVT::i64;
1146  }
1147 
1148  // Decide how to handle f32. If the target does not have native f32 support,
1149  // expand it to i32 and we will be generating soft float library calls.
1150  if (!isTypeLegal(MVT::f32)) {
1151  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1152  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1153  TransformToType[MVT::f32] = MVT::i32;
1155  }
1156 
1157  // Decide how to handle f16. If the target does not have native f16 support,
1158  // promote it to f32, because there are no f16 library calls (except for
1159  // conversions).
1160  if (!isTypeLegal(MVT::f16)) {
1161  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1162  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1163  TransformToType[MVT::f16] = MVT::f32;
1165  }
1166 
1167  // Loop over all of the vector value types to see which need transformations.
1168  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1169  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1170  MVT VT = (MVT::SimpleValueType) i;
1171  if (isTypeLegal(VT))
1172  continue;
1173 
1174  MVT EltVT = VT.getVectorElementType();
1175  unsigned NElts = VT.getVectorNumElements();
1176  bool IsLegalWiderType = false;
1177  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1178  switch (PreferredAction) {
1179  case TypePromoteInteger:
1180  // Try to promote the elements of integer vectors. If no legal
1181  // promotion was found, fall through to the widen-vector method.
1182  for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1183  MVT SVT = (MVT::SimpleValueType) nVT;
1184  // Promote vectors of integers to vectors with the same number
1185  // of elements, with a wider element type.
1186  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1187  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1188  TransformToType[i] = SVT;
1189  RegisterTypeForVT[i] = SVT;
1190  NumRegistersForVT[i] = 1;
1192  IsLegalWiderType = true;
1193  break;
1194  }
1195  }
1196  if (IsLegalWiderType)
1197  break;
1199 
1200  case TypeWidenVector:
1201  // Try to widen the vector.
1202  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1203  MVT SVT = (MVT::SimpleValueType) nVT;
1204  if (SVT.getVectorElementType() == EltVT
1205  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1206  TransformToType[i] = SVT;
1207  RegisterTypeForVT[i] = SVT;
1208  NumRegistersForVT[i] = 1;
1210  IsLegalWiderType = true;
1211  break;
1212  }
1213  }
1214  if (IsLegalWiderType)
1215  break;
1217 
1218  case TypeSplitVector:
1219  case TypeScalarizeVector: {
1220  MVT IntermediateVT;
1221  MVT RegisterVT;
1222  unsigned NumIntermediates;
1223  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1224  NumIntermediates, RegisterVT, this);
1225  RegisterTypeForVT[i] = RegisterVT;
1226 
1227  MVT NVT = VT.getPow2VectorType();
1228  if (NVT == VT) {
1229  // Type is already a power of 2. The default action is to split.
1230  TransformToType[i] = MVT::Other;
1231  if (PreferredAction == TypeScalarizeVector)
1233  else if (PreferredAction == TypeSplitVector)
1235  else
1236  // Set type action according to the number of elements.
1238  : TypeSplitVector);
1239  } else {
1240  TransformToType[i] = NVT;
1242  }
1243  break;
1244  }
1245  default:
1246  llvm_unreachable("Unknown vector legalization action!");
1247  }
1248  }
1249 
1250  // Determine the 'representative' register class for each value type.
1251  // An representative register class is the largest (meaning one which is
1252  // not a sub-register class / subreg register class) legal register class for
1253  // a group of value types. For example, on i386, i8, i16, and i32
1254  // representative would be GR32; while on x86_64 it's GR64.
1255  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1256  const TargetRegisterClass* RRC;
1257  uint8_t Cost;
1258  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1259  RepRegClassForVT[i] = RRC;
1260  RepRegClassCostForVT[i] = Cost;
1261  }
1262 }
1263 
1265  EVT VT) const {
1266  assert(!VT.isVector() && "No default SetCC type for vectors!");
1267  return getPointerTy(DL).SimpleTy;
1268 }
1269 
1271  return MVT::i32; // return the default value
1272 }
1273 
1274 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1275 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1276 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1277 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1278 ///
1279 /// This method returns the number of registers needed, and the VT for each
1280 /// register. It also returns the VT and quantity of the intermediate values
1281 /// before they are promoted/expanded.
1283  EVT &IntermediateVT,
1284  unsigned &NumIntermediates,
1285  MVT &RegisterVT) const {
1286  unsigned NumElts = VT.getVectorNumElements();
1287 
1288  // If there is a wider vector type with the same element type as this one,
1289  // or a promoted vector type that has the same number of elements which
1290  // are wider, then we should convert to that legal vector type.
1291  // This handles things like <2 x float> -> <4 x float> and
1292  // <4 x i1> -> <4 x i32>.
1293  LegalizeTypeAction TA = getTypeAction(Context, VT);
1294  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1295  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1296  if (isTypeLegal(RegisterEVT)) {
1297  IntermediateVT = RegisterEVT;
1298  RegisterVT = RegisterEVT.getSimpleVT();
1299  NumIntermediates = 1;
1300  return 1;
1301  }
1302  }
1303 
1304  // Figure out the right, legal destination reg to copy into.
1305  EVT EltTy = VT.getVectorElementType();
1306 
1307  unsigned NumVectorRegs = 1;
1308 
1309  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1310  // could break down into LHS/RHS like LegalizeDAG does.
1311  if (!isPowerOf2_32(NumElts)) {
1312  NumVectorRegs = NumElts;
1313  NumElts = 1;
1314  }
1315 
1316  // Divide the input until we get to a supported size. This will always
1317  // end with a scalar if the target doesn't support vectors.
1318  while (NumElts > 1 && !isTypeLegal(
1319  EVT::getVectorVT(Context, EltTy, NumElts))) {
1320  NumElts >>= 1;
1321  NumVectorRegs <<= 1;
1322  }
1323 
1324  NumIntermediates = NumVectorRegs;
1325 
1326  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1327  if (!isTypeLegal(NewVT))
1328  NewVT = EltTy;
1329  IntermediateVT = NewVT;
1330 
1331  MVT DestVT = getRegisterType(Context, NewVT);
1332  RegisterVT = DestVT;
1333  unsigned NewVTSize = NewVT.getSizeInBits();
1334 
1335  // Convert sizes such as i33 to i64.
1336  if (!isPowerOf2_32(NewVTSize))
1337  NewVTSize = NextPowerOf2(NewVTSize);
1338 
1339  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1340  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1341 
1342  // Otherwise, promotion or legal types use the same number of registers as
1343  // the vector decimated to the appropriate level.
1344  return NumVectorRegs;
1345 }
1346 
1347 /// Get the EVTs and ArgFlags collections that represent the legalized return
1348 /// type of the given function. This does not require a DAG or a return value,
1349 /// and is suitable for use before any DAGs for the function are constructed.
1350 /// TODO: Move this out of TargetLowering.cpp.
1352  AttributeList attr,
1354  const TargetLowering &TLI, const DataLayout &DL) {
1355  SmallVector<EVT, 4> ValueVTs;
1356  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1357  unsigned NumValues = ValueVTs.size();
1358  if (NumValues == 0) return;
1359 
1360  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1361  EVT VT = ValueVTs[j];
1362  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1363 
1364  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1365  ExtendKind = ISD::SIGN_EXTEND;
1366  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1367  ExtendKind = ISD::ZERO_EXTEND;
1368 
1369  // FIXME: C calling convention requires the return type to be promoted to
1370  // at least 32-bit. But this is not necessary for non-C calling
1371  // conventions. The frontend should mark functions whose return values
1372  // require promoting with signext or zeroext attributes.
1373  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1374  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1375  if (VT.bitsLT(MinVT))
1376  VT = MinVT;
1377  }
1378 
1379  unsigned NumParts =
1380  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1381  MVT PartVT =
1382  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1383 
1384  // 'inreg' on function refers to return value
1385  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1386  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1387  Flags.setInReg();
1388 
1389  // Propagate extension type if any
1390  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1391  Flags.setSExt();
1392  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1393  Flags.setZExt();
1394 
1395  for (unsigned i = 0; i < NumParts; ++i)
1396  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1397  }
1398 }
1399 
1400 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1401 /// function arguments in the caller parameter area. This is the actual
1402 /// alignment, not its logarithm.
1404  const DataLayout &DL) const {
1405  return DL.getABITypeAlignment(Ty);
1406 }
1407 
1409  const DataLayout &DL, EVT VT,
1410  unsigned AddrSpace,
1411  unsigned Alignment,
1412  bool *Fast) const {
1413  // Check if the specified alignment is sufficient based on the data layout.
1414  // TODO: While using the data layout works in practice, a better solution
1415  // would be to implement this check directly (make this a virtual function).
1416  // For example, the ABI alignment may change based on software platform while
1417  // this function should only be affected by hardware implementation.
1418  Type *Ty = VT.getTypeForEVT(Context);
1419  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1420  // Assume that an access that meets the ABI-specified alignment is fast.
1421  if (Fast != nullptr)
1422  *Fast = true;
1423  return true;
1424  }
1425 
1426  // This is a misaligned access.
1427  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast);
1428 }
1429 
1431  return BranchProbability(MinPercentageForPredictableBranch, 100);
1432 }
1433 
1434 //===----------------------------------------------------------------------===//
1435 // TargetTransformInfo Helpers
1436 //===----------------------------------------------------------------------===//
1437 
1439  enum InstructionOpcodes {
1440 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1441 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1442 #include "llvm/IR/Instruction.def"
1443  };
1444  switch (static_cast<InstructionOpcodes>(Opcode)) {
1445  case Ret: return 0;
1446  case Br: return 0;
1447  case Switch: return 0;
1448  case IndirectBr: return 0;
1449  case Invoke: return 0;
1450  case Resume: return 0;
1451  case Unreachable: return 0;
1452  case CleanupRet: return 0;
1453  case CatchRet: return 0;
1454  case CatchPad: return 0;
1455  case CatchSwitch: return 0;
1456  case CleanupPad: return 0;
1457  case FNeg: return ISD::FNEG;
1458  case Add: return ISD::ADD;
1459  case FAdd: return ISD::FADD;
1460  case Sub: return ISD::SUB;
1461  case FSub: return ISD::FSUB;
1462  case Mul: return ISD::MUL;
1463  case FMul: return ISD::FMUL;
1464  case UDiv: return ISD::UDIV;
1465  case SDiv: return ISD::SDIV;
1466  case FDiv: return ISD::FDIV;
1467  case URem: return ISD::UREM;
1468  case SRem: return ISD::SREM;
1469  case FRem: return ISD::FREM;
1470  case Shl: return ISD::SHL;
1471  case LShr: return ISD::SRL;
1472  case AShr: return ISD::SRA;
1473  case And: return ISD::AND;
1474  case Or: return ISD::OR;
1475  case Xor: return ISD::XOR;
1476  case Alloca: return 0;
1477  case Load: return ISD::LOAD;
1478  case Store: return ISD::STORE;
1479  case GetElementPtr: return 0;
1480  case Fence: return 0;
1481  case AtomicCmpXchg: return 0;
1482  case AtomicRMW: return 0;
1483  case Trunc: return ISD::TRUNCATE;
1484  case ZExt: return ISD::ZERO_EXTEND;
1485  case SExt: return ISD::SIGN_EXTEND;
1486  case FPToUI: return ISD::FP_TO_UINT;
1487  case FPToSI: return ISD::FP_TO_SINT;
1488  case UIToFP: return ISD::UINT_TO_FP;
1489  case SIToFP: return ISD::SINT_TO_FP;
1490  case FPTrunc: return ISD::FP_ROUND;
1491  case FPExt: return ISD::FP_EXTEND;
1492  case PtrToInt: return ISD::BITCAST;
1493  case IntToPtr: return ISD::BITCAST;
1494  case BitCast: return ISD::BITCAST;
1495  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1496  case ICmp: return ISD::SETCC;
1497  case FCmp: return ISD::SETCC;
1498  case PHI: return 0;
1499  case Call: return 0;
1500  case Select: return ISD::SELECT;
1501  case UserOp1: return 0;
1502  case UserOp2: return 0;
1503  case VAArg: return 0;
1504  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1505  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1506  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1507  case ExtractValue: return ISD::MERGE_VALUES;
1508  case InsertValue: return ISD::MERGE_VALUES;
1509  case LandingPad: return 0;
1510  }
1511 
1512  llvm_unreachable("Unknown instruction type encountered!");
1513 }
1514 
1515 std::pair<int, MVT>
1517  Type *Ty) const {
1518  LLVMContext &C = Ty->getContext();
1519  EVT MTy = getValueType(DL, Ty);
1520 
1521  int Cost = 1;
1522  // We keep legalizing the type until we find a legal kind. We assume that
1523  // the only operation that costs anything is the split. After splitting
1524  // we need to handle two types.
1525  while (true) {
1526  LegalizeKind LK = getTypeConversion(C, MTy);
1527 
1528  if (LK.first == TypeLegal)
1529  return std::make_pair(Cost, MTy.getSimpleVT());
1530 
1531  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1532  Cost *= 2;
1533 
1534  // Do not loop with f128 type.
1535  if (MTy == LK.second)
1536  return std::make_pair(Cost, MTy.getSimpleVT());
1537 
1538  // Keep legalizing the type.
1539  MTy = LK.second;
1540  }
1541 }
1542 
1544  bool UseTLS) const {
1545  // compiler-rt provides a variable with a magic name. Targets that do not
1546  // link with compiler-rt may also provide such a variable.
1547  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1548  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1549  auto UnsafeStackPtr =
1550  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1551 
1552  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1553 
1554  if (!UnsafeStackPtr) {
1555  auto TLSModel = UseTLS ?
1558  // The global variable is not defined yet, define it ourselves.
1559  // We use the initial-exec TLS model because we do not support the
1560  // variable living anywhere other than in the main executable.
1561  UnsafeStackPtr = new GlobalVariable(
1562  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1563  UnsafeStackPtrVar, nullptr, TLSModel);
1564  } else {
1565  // The variable exists, check its type and attributes.
1566  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1567  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1568  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1569  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1570  (UseTLS ? "" : "not ") + "be thread-local");
1571  }
1572  return UnsafeStackPtr;
1573 }
1574 
1576  if (!TM.getTargetTriple().isAndroid())
1577  return getDefaultSafeStackPointerLocation(IRB, true);
1578 
1579  // Android provides a libc function to retrieve the address of the current
1580  // thread's unsafe stack pointer.
1581  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1582  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1583  Value *Fn = M->getOrInsertFunction("__safestack_pointer_address",
1584  StackPtrTy->getPointerTo(0));
1585  return IRB.CreateCall(Fn);
1586 }
1587 
1588 //===----------------------------------------------------------------------===//
1589 // Loop Strength Reduction hooks
1590 //===----------------------------------------------------------------------===//
1591 
1592 /// isLegalAddressingMode - Return true if the addressing mode represented
1593 /// by AM is legal for this target, for a load/store of the specified type.
1595  const AddrMode &AM, Type *Ty,
1596  unsigned AS, Instruction *I) const {
1597  // The default implementation of this implements a conservative RISCy, r+r and
1598  // r+i addr mode.
1599 
1600  // Allows a sign-extended 16-bit immediate field.
1601  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1602  return false;
1603 
1604  // No global is ever allowed as a base.
1605  if (AM.BaseGV)
1606  return false;
1607 
1608  // Only support r+r,
1609  switch (AM.Scale) {
1610  case 0: // "r+i" or just "i", depending on HasBaseReg.
1611  break;
1612  case 1:
1613  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1614  return false;
1615  // Otherwise we have r+r or r+i.
1616  break;
1617  case 2:
1618  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1619  return false;
1620  // Allow 2*r as r+r.
1621  break;
1622  default: // Don't allow n * r
1623  return false;
1624  }
1625 
1626  return true;
1627 }
1628 
1629 //===----------------------------------------------------------------------===//
1630 // Stack Protector
1631 //===----------------------------------------------------------------------===//
1632 
1633 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1634 // so that SelectionDAG handle SSP.
1636  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1637  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1639  return M.getOrInsertGlobal("__guard_local", PtrTy);
1640  }
1641  return nullptr;
1642 }
1643 
1644 // Currently only support "standard" __stack_chk_guard.
1645 // TODO: add LOAD_STACK_GUARD support.
1647  if (!M.getNamedValue("__stack_chk_guard"))
1648  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1650  nullptr, "__stack_chk_guard");
1651 }
1652 
1653 // Currently only support "standard" __stack_chk_guard.
1654 // TODO: add LOAD_STACK_GUARD support.
1656  return M.getNamedValue("__stack_chk_guard");
1657 }
1658 
1660  return nullptr;
1661 }
1662 
1664  return MinimumJumpTableEntries;
1665 }
1666 
1669 }
1670 
1671 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1672  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1673 }
1674 
1676  return MaximumJumpTableSize;
1677 }
1678 
1680  MaximumJumpTableSize = Val;
1681 }
1682 
1683 //===----------------------------------------------------------------------===//
1684 // Reciprocal Estimates
1685 //===----------------------------------------------------------------------===//
1686 
1687 /// Get the reciprocal estimate attribute string for a function that will
1688 /// override the target defaults.
1690  const Function &F = MF.getFunction();
1691  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1692 }
1693 
1694 /// Construct a string for the given reciprocal operation of the given type.
1695 /// This string should match the corresponding option to the front-end's
1696 /// "-mrecip" flag assuming those strings have been passed through in an
1697 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1698 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1699  std::string Name = VT.isVector() ? "vec-" : "";
1700 
1701  Name += IsSqrt ? "sqrt" : "div";
1702 
1703  // TODO: Handle "half" or other float types?
1704  if (VT.getScalarType() == MVT::f64) {
1705  Name += "d";
1706  } else {
1707  assert(VT.getScalarType() == MVT::f32 &&
1708  "Unexpected FP type for reciprocal estimate");
1709  Name += "f";
1710  }
1711 
1712  return Name;
1713 }
1714 
1715 /// Return the character position and value (a single numeric character) of a
1716 /// customized refinement operation in the input string if it exists. Return
1717 /// false if there is no customized refinement step count.
1719  uint8_t &Value) {
1720  const char RefStepToken = ':';
1721  Position = In.find(RefStepToken);
1722  if (Position == StringRef::npos)
1723  return false;
1724 
1725  StringRef RefStepString = In.substr(Position + 1);
1726  // Allow exactly one numeric character for the additional refinement
1727  // step parameter.
1728  if (RefStepString.size() == 1) {
1729  char RefStepChar = RefStepString[0];
1730  if (RefStepChar >= '0' && RefStepChar <= '9') {
1731  Value = RefStepChar - '0';
1732  return true;
1733  }
1734  }
1735  report_fatal_error("Invalid refinement step for -recip.");
1736 }
1737 
1738 /// For the input attribute string, return one of the ReciprocalEstimate enum
1739 /// status values (enabled, disabled, or not specified) for this operation on
1740 /// the specified data type.
1741 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1742  if (Override.empty())
1743  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1744 
1745  SmallVector<StringRef, 4> OverrideVector;
1746  Override.split(OverrideVector, ',');
1747  unsigned NumArgs = OverrideVector.size();
1748 
1749  // Check if "all", "none", or "default" was specified.
1750  if (NumArgs == 1) {
1751  // Look for an optional setting of the number of refinement steps needed
1752  // for this type of reciprocal operation.
1753  size_t RefPos;
1754  uint8_t RefSteps;
1755  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1756  // Split the string for further processing.
1757  Override = Override.substr(0, RefPos);
1758  }
1759 
1760  // All reciprocal types are enabled.
1761  if (Override == "all")
1763 
1764  // All reciprocal types are disabled.
1765  if (Override == "none")
1766  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1767 
1768  // Target defaults for enablement are used.
1769  if (Override == "default")
1770  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1771  }
1772 
1773  // The attribute string may omit the size suffix ('f'/'d').
1774  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1775  std::string VTNameNoSize = VTName;
1776  VTNameNoSize.pop_back();
1777  static const char DisabledPrefix = '!';
1778 
1779  for (StringRef RecipType : OverrideVector) {
1780  size_t RefPos;
1781  uint8_t RefSteps;
1782  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1783  RecipType = RecipType.substr(0, RefPos);
1784 
1785  // Ignore the disablement token for string matching.
1786  bool IsDisabled = RecipType[0] == DisabledPrefix;
1787  if (IsDisabled)
1788  RecipType = RecipType.substr(1);
1789 
1790  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1791  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1793  }
1794 
1795  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1796 }
1797 
1798 /// For the input attribute string, return the customized refinement step count
1799 /// for this operation on the specified data type. If the step count does not
1800 /// exist, return the ReciprocalEstimate enum value for unspecified.
1801 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1802  if (Override.empty())
1803  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1804 
1805  SmallVector<StringRef, 4> OverrideVector;
1806  Override.split(OverrideVector, ',');
1807  unsigned NumArgs = OverrideVector.size();
1808 
1809  // Check if "all", "default", or "none" was specified.
1810  if (NumArgs == 1) {
1811  // Look for an optional setting of the number of refinement steps needed
1812  // for this type of reciprocal operation.
1813  size_t RefPos;
1814  uint8_t RefSteps;
1815  if (!parseRefinementStep(Override, RefPos, RefSteps))
1816  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1817 
1818  // Split the string for further processing.
1819  Override = Override.substr(0, RefPos);
1820  assert(Override != "none" &&
1821  "Disabled reciprocals, but specifed refinement steps?");
1822 
1823  // If this is a general override, return the specified number of steps.
1824  if (Override == "all" || Override == "default")
1825  return RefSteps;
1826  }
1827 
1828  // The attribute string may omit the size suffix ('f'/'d').
1829  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1830  std::string VTNameNoSize = VTName;
1831  VTNameNoSize.pop_back();
1832 
1833  for (StringRef RecipType : OverrideVector) {
1834  size_t RefPos;
1835  uint8_t RefSteps;
1836  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1837  continue;
1838 
1839  RecipType = RecipType.substr(0, RefPos);
1840  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1841  return RefSteps;
1842  }
1843 
1844  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1845 }
1846 
1848  MachineFunction &MF) const {
1849  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1850 }
1851 
1853  MachineFunction &MF) const {
1854  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1855 }
1856 
1858  MachineFunction &MF) const {
1859  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1860 }
1861 
1863  MachineFunction &MF) const {
1864  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1865 }
1866 
1868  MF.getRegInfo().freezeReservedRegs(MF);
1869 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:571
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:538
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:475
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:594
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
LLVMContext & Context
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:359
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:447
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:605
Constant * getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:367
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:260
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:519
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:223
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:49
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:802
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
bool isOSFuchsia() const
Definition: Triple.h:495
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:508
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:384
Same for subtraction.
Definition: ISDOpcodes.h:254
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:316
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:366
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
Shift and rotation operations.
Definition: ISDOpcodes.h:410
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:412
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:243
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:393
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:652
RESULT = SMULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same wi...
Definition: ISDOpcodes.h:280
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:743
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:810
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:478
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:290
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:121
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:456
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:959
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:747
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:497
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:467
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:103
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:524
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
The memory access is volatile.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:419
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
Constant * getOrInsertGlobal(StringRef Name, Type *Ty)
Look up the specified global in the module symbol table.
Definition: Module.cpp:205
Simple binary floating point operators.
Definition: ISDOpcodes.h:283
bool isOSOpenBSD() const
Definition: Triple.h:487
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:629
bool isWatchABI() const
Definition: Triple.h:470
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:332
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:232
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:634
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:767
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:770
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(0), cl::Hidden, cl::desc("Set maximum size of jump tables; zero for no limit."))
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:416
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:796
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:556
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:34
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:640
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:53
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:220
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
The memory access writes data.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:265
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:317
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:339
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:451
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:575
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1038
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:600
static bool Enabled
Definition: Statistic.cpp:51
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:420
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:241
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:468
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:471
ValueTypeActionImpl ValueTypeActions
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:312
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
virtual Value * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:859
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:64
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:387
static const size_t npos
Definition: StringRef.h:51
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1274
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:614
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:511
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:273
Same for multiplication.
Definition: ISDOpcodes.h:257
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:922
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:432
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:345
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:807
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
LLVM Value Representation.
Definition: Value.h:73
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:776
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:632
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:331
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:306
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:443
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:408
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:198
Conversion operators.
Definition: ISDOpcodes.h:465
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:474
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:126
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:298
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:584
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:776
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:242
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
CallInst * CreateCall(Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:1883
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...