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NVPTXISelLowering.h
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1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
16 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
17 
18 #include "NVPTX.h"
21 
22 namespace llvm {
23 namespace NVPTXISD {
24 enum NodeType : unsigned {
25  // Start the numbering from where ISD NodeType finishes.
61 
64  LDGV2, // LDG.v2
65  LDGV4, // LDG.v4
66  LDUV2, // LDU.v2
67  LDUV4, // LDU.v4
76  StoreParamS32, // to sext and store a <32bit value, not used currently
77  StoreParamU32, // to zext and store a <32bit value, not used currently
81 
82  // Texture intrinsics
251 
252  // Surface intrinsics
264 
276 
288 
300 
312 
324 
336 
348 
360 
372 
384 
396 
408 
420 
432 };
433 }
434 
435 class NVPTXSubtarget;
436 
437 //===--------------------------------------------------------------------===//
438 // TargetLowering Implementation
439 //===--------------------------------------------------------------------===//
441 public:
442  explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
443  const NVPTXSubtarget &STI);
444  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
445 
446  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
447 
448  const char *getTargetNodeName(unsigned Opcode) const override;
449 
450  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
451  unsigned Intrinsic) const override;
452 
453  /// isLegalAddressingMode - Return true if the addressing mode represented
454  /// by AM is legal for this target, for a load/store of the specified type
455  /// Used to guide target specific optimizations, like loop strength
456  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
457  /// address mode (CodeGenPrepare.cpp)
458  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
459  unsigned AS,
460  Instruction *I = nullptr) const override;
461 
462  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
463  // Truncating 64-bit to 32-bit is free in SASS.
464  if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
465  return false;
466  return SrcTy->getPrimitiveSizeInBits() == 64 &&
467  DstTy->getPrimitiveSizeInBits() == 32;
468  }
469 
471  EVT VT) const override {
472  if (VT.isVector())
473  return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
474  return MVT::i1;
475  }
476 
477  ConstraintType getConstraintType(StringRef Constraint) const override;
478  std::pair<unsigned, const TargetRegisterClass *>
479  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
480  StringRef Constraint, MVT VT) const override;
481 
482  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
483  bool isVarArg,
485  const SDLoc &dl, SelectionDAG &DAG,
486  SmallVectorImpl<SDValue> &InVals) const override;
487 
488  SDValue LowerCall(CallLoweringInfo &CLI,
489  SmallVectorImpl<SDValue> &InVals) const override;
490 
491  std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
493  unsigned retAlignment,
494  ImmutableCallSite CS) const;
495 
496  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
498  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
499  SelectionDAG &DAG) const override;
500 
501  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
502  std::vector<SDValue> &Ops,
503  SelectionDAG &DAG) const override;
504 
506 
507  // PTX always uses 32-bit shift amounts
508  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
509  return MVT::i32;
510  }
511 
513  getPreferredVectorAction(EVT VT) const override;
514 
515  // Get the degree of precision we want from 32-bit floating point division
516  // operations.
517  //
518  // 0 - Use ptx div.approx
519  // 1 - Use ptx.div.full (approximate, but less so than div.approx)
520  // 2 - Use IEEE-compliant div instructions, if available.
521  int getDivF32Level() const;
522 
523  // Get whether we should use a precise or approximate 32-bit floating point
524  // sqrt instruction.
525  bool usePrecSqrtF32() const;
526 
527  // Get whether we should use instructions that flush floating-point denormals
528  // to sign-preserving zero.
529  bool useF32FTZ(const MachineFunction &MF) const;
530 
531  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
532  int &ExtraSteps, bool &UseOneConst,
533  bool Reciprocal) const override;
534 
535  unsigned combineRepeatedFPDivisors() const override { return 2; }
536 
537  bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
538  bool allowUnsafeFPMath(MachineFunction &MF) const;
539 
540  bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
541 
542  bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
543 
544  // The default is to transform llvm.ctlz(x, false) (where false indicates that
545  // x == 0 is not undefined behavior) into a branch that checks whether x is 0
546  // and avoids calling ctlz in that case. We have a dedicated ctlz
547  // instruction, so we say that ctlz is cheap to speculate.
548  bool isCheapToSpeculateCtlz() const override { return true; }
549 
550 private:
551  const NVPTXSubtarget &STI; // cache the subtarget here
552  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
553 
554  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
557 
558  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
559  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
560 
561  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
562  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
563  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
564 
565  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
566  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
567 
568  SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
569 
570  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
571  SelectionDAG &DAG) const override;
572  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
573 
574  unsigned getArgumentAlignment(SDValue Callee, ImmutableCallSite CS, Type *Ty,
575  unsigned Idx, const DataLayout &DL) const;
576 };
577 } // namespace llvm
578 
579 #endif
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
This class represents a function call, abstracting a target machine&#39;s calling convention.
Function Alias Analysis Results
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
amdgpu Simplify well known AMD library false Value * Callee
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
static bool Enabled
Definition: Statistic.cpp:49
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:73
NVPTXTargetMachine.
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
Establish a view to a call site for examination.
Definition: CallSite.h:713
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
const NVPTXTargetMachine * nvTM