LLVM  6.0.0svn
X86FloatingPoint.cpp
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1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
13 // lifetimes.
14 //
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
20 //
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #include "X86.h"
27 #include "X86InstrInfo.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
39 #include "llvm/CodeGen/Passes.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <bitset>
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "x86-codegen"
52 
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
55 
56 namespace {
57  const unsigned ScratchFPReg = 7;
58 
59  struct FPS : public MachineFunctionPass {
60  static char ID;
61  FPS() : MachineFunctionPass(ID) {
63  // This is really only to keep valgrind quiet.
64  // The logic in isLive() is too much for it.
65  memset(Stack, 0, sizeof(Stack));
66  memset(RegMap, 0, sizeof(RegMap));
67  }
68 
69  void getAnalysisUsage(AnalysisUsage &AU) const override {
70  AU.setPreservesCFG();
75  }
76 
77  bool runOnMachineFunction(MachineFunction &MF) override;
78 
79  MachineFunctionProperties getRequiredProperties() const override {
82  }
83 
84  StringRef getPassName() const override { return "X86 FP Stackifier"; }
85 
86  private:
87  const TargetInstrInfo *TII; // Machine instruction info.
88 
89  // Two CFG edges are related if they leave the same block, or enter the same
90  // block. The transitive closure of an edge under this relation is a
91  // LiveBundle. It represents a set of CFG edges where the live FP stack
92  // registers must be allocated identically in the x87 stack.
93  //
94  // A LiveBundle is usually all the edges leaving a block, or all the edges
95  // entering a block, but it can contain more edges if critical edges are
96  // present.
97  //
98  // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
99  // but the exact mapping of FP registers to stack slots is fixed later.
100  struct LiveBundle {
101  // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
102  unsigned Mask;
103 
104  // Number of pre-assigned live registers in FixStack. This is 0 when the
105  // stack order has not yet been fixed.
106  unsigned FixCount;
107 
108  // Assigned stack order for live-in registers.
109  // FixStack[i] == getStackEntry(i) for all i < FixCount.
110  unsigned char FixStack[8];
111 
112  LiveBundle() : Mask(0), FixCount(0) {}
113 
114  // Have the live registers been assigned a stack order yet?
115  bool isFixed() const { return !Mask || FixCount; }
116  };
117 
118  // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
119  // with no live FP registers.
120  SmallVector<LiveBundle, 8> LiveBundles;
121 
122  // The edge bundle analysis provides indices into the LiveBundles vector.
123  EdgeBundles *Bundles;
124 
125  // Return a bitmask of FP registers in block's live-in list.
126  static unsigned calcLiveInMask(MachineBasicBlock *MBB, bool RemoveFPs) {
127  unsigned Mask = 0;
129  I != MBB->livein_end(); ) {
130  MCPhysReg Reg = I->PhysReg;
131  static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132  if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133  Mask |= 1 << (Reg - X86::FP0);
134  if (RemoveFPs) {
135  I = MBB->removeLiveIn(I);
136  continue;
137  }
138  }
139  ++I;
140  }
141  return Mask;
142  }
143 
144  // Partition all the CFG edges into LiveBundles.
145  void bundleCFGRecomputeKillFlags(MachineFunction &MF);
146 
147  MachineBasicBlock *MBB; // Current basic block
148 
149  // The hardware keeps track of how many FP registers are live, so we have
150  // to model that exactly. Usually, each live register corresponds to an
151  // FP<n> register, but when dealing with calls, returns, and inline
152  // assembly, it is sometimes necessary to have live scratch registers.
153  unsigned Stack[8]; // FP<n> Registers in each stack slot...
154  unsigned StackTop; // The current top of the FP stack.
155 
156  enum {
157  NumFPRegs = 8 // Including scratch pseudo-registers.
158  };
159 
160  // For each live FP<n> register, point to its Stack[] entry.
161  // The first entries correspond to FP0-FP6, the rest are scratch registers
162  // used when we need slightly different live registers than what the
163  // register allocator thinks.
164  unsigned RegMap[NumFPRegs];
165 
166  // Set up our stack model to match the incoming registers to MBB.
167  void setupBlockStack();
168 
169  // Shuffle live registers to match the expectations of successor blocks.
170  void finishBlockStack();
171 
172 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
173  void dumpStack() const {
174  dbgs() << "Stack contents:";
175  for (unsigned i = 0; i != StackTop; ++i) {
176  dbgs() << " FP" << Stack[i];
177  assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
178  }
179  }
180 #endif
181 
182  /// getSlot - Return the stack slot number a particular register number is
183  /// in.
184  unsigned getSlot(unsigned RegNo) const {
185  assert(RegNo < NumFPRegs && "Regno out of range!");
186  return RegMap[RegNo];
187  }
188 
189  /// isLive - Is RegNo currently live in the stack?
190  bool isLive(unsigned RegNo) const {
191  unsigned Slot = getSlot(RegNo);
192  return Slot < StackTop && Stack[Slot] == RegNo;
193  }
194 
195  /// getStackEntry - Return the X86::FP<n> register in register ST(i).
196  unsigned getStackEntry(unsigned STi) const {
197  if (STi >= StackTop)
198  report_fatal_error("Access past stack top!");
199  return Stack[StackTop-1-STi];
200  }
201 
202  /// getSTReg - Return the X86::ST(i) register which contains the specified
203  /// FP<RegNo> register.
204  unsigned getSTReg(unsigned RegNo) const {
205  return StackTop - 1 - getSlot(RegNo) + X86::ST0;
206  }
207 
208  // pushReg - Push the specified FP<n> register onto the stack.
209  void pushReg(unsigned Reg) {
210  assert(Reg < NumFPRegs && "Register number out of range!");
211  if (StackTop >= 8)
212  report_fatal_error("Stack overflow!");
213  Stack[StackTop] = Reg;
214  RegMap[Reg] = StackTop++;
215  }
216 
217  // popReg - Pop a register from the stack.
218  void popReg() {
219  if (StackTop == 0)
220  report_fatal_error("Cannot pop empty stack!");
221  RegMap[Stack[--StackTop]] = ~0; // Update state
222  }
223 
224  bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
225  void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
226  DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
227  if (isAtTop(RegNo)) return;
228 
229  unsigned STReg = getSTReg(RegNo);
230  unsigned RegOnTop = getStackEntry(0);
231 
232  // Swap the slots the regs are in.
233  std::swap(RegMap[RegNo], RegMap[RegOnTop]);
234 
235  // Swap stack slot contents.
236  if (RegMap[RegOnTop] >= StackTop)
237  report_fatal_error("Access past stack top!");
238  std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
239 
240  // Emit an fxch to update the runtime processors version of the state.
241  BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
242  ++NumFXCH;
243  }
244 
245  void duplicateToTop(unsigned RegNo, unsigned AsReg,
247  DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
248  unsigned STReg = getSTReg(RegNo);
249  pushReg(AsReg); // New register on top of stack
250 
251  BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
252  }
253 
254  /// popStackAfter - Pop the current value off of the top of the FP stack
255  /// after the specified instruction.
256  void popStackAfter(MachineBasicBlock::iterator &I);
257 
258  /// freeStackSlotAfter - Free the specified register from the register
259  /// stack, so that it is no longer in a register. If the register is
260  /// currently at the top of the stack, we just pop the current instruction,
261  /// otherwise we store the current top-of-stack into the specified slot,
262  /// then pop the top of stack.
263  void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
264 
265  /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
266  /// instruction.
268  freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
269 
270  /// Adjust the live registers to be the set in Mask.
271  void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
272 
273  /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
274  /// st(0), FP reg FixStack[1] is st(1) etc.
275  void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
277 
278  bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
279 
280  void handleCall(MachineBasicBlock::iterator &I);
281  void handleReturn(MachineBasicBlock::iterator &I);
282  void handleZeroArgFP(MachineBasicBlock::iterator &I);
283  void handleOneArgFP(MachineBasicBlock::iterator &I);
284  void handleOneArgFPRW(MachineBasicBlock::iterator &I);
285  void handleTwoArgFP(MachineBasicBlock::iterator &I);
286  void handleCompareFP(MachineBasicBlock::iterator &I);
287  void handleCondMovFP(MachineBasicBlock::iterator &I);
288  void handleSpecialFP(MachineBasicBlock::iterator &I);
289 
290  // Check if a COPY instruction is using FP registers.
291  static bool isFPCopy(MachineInstr &MI) {
292  unsigned DstReg = MI.getOperand(0).getReg();
293  unsigned SrcReg = MI.getOperand(1).getReg();
294 
295  return X86::RFP80RegClass.contains(DstReg) ||
296  X86::RFP80RegClass.contains(SrcReg);
297  }
298 
299  void setKillFlags(MachineBasicBlock &MBB) const;
300  };
301  char FPS::ID = 0;
302 }
303 
305 
306 /// getFPReg - Return the X86::FPx register number for the specified operand.
307 /// For example, this returns 3 for X86::FP3.
308 static unsigned getFPReg(const MachineOperand &MO) {
309  assert(MO.isReg() && "Expected an FP register!");
310  unsigned Reg = MO.getReg();
311  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
312  return Reg - X86::FP0;
313 }
314 
315 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
316 /// register references into FP stack references.
317 ///
318 bool FPS::runOnMachineFunction(MachineFunction &MF) {
319  // We only need to run this pass if there are any FP registers used in this
320  // function. If it is all integer, there is nothing for us to do!
321  bool FPIsUsed = false;
322 
323  static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
324  const MachineRegisterInfo &MRI = MF.getRegInfo();
325  for (unsigned i = 0; i <= 6; ++i)
326  if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
327  FPIsUsed = true;
328  break;
329  }
330 
331  // Early exit.
332  if (!FPIsUsed) return false;
333 
334  Bundles = &getAnalysis<EdgeBundles>();
335  TII = MF.getSubtarget().getInstrInfo();
336 
337  // Prepare cross-MBB liveness.
338  bundleCFGRecomputeKillFlags(MF);
339 
340  StackTop = 0;
341 
342  // Process the function in depth first order so that we process at least one
343  // of the predecessors for every reachable block in the function.
345  MachineBasicBlock *Entry = &MF.front();
346 
347  LiveBundle &Bundle =
348  LiveBundles[Bundles->getBundle(Entry->getNumber(), false)];
349 
350  // In regcall convention, some FP registers may not be passed through
351  // the stack, so they will need to be assigned to the stack first
352  if ((Entry->getParent()->getFunction()->getCallingConv() ==
353  CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) {
354  // In the register calling convention, up to one FP argument could be
355  // saved in the first FP register.
356  // If bundle.mask is non-zero and Bundle.FixCount is zero, it means
357  // that the FP registers contain arguments.
358  // The actual value is passed in FP0.
359  // Here we fix the stack and mark FP0 as pre-assigned register.
360  assert((Bundle.Mask & 0xFE) == 0 &&
361  "Only FP0 could be passed as an argument");
362  Bundle.FixCount = 1;
363  Bundle.FixStack[0] = 0;
364  }
365 
366  bool Changed = false;
367  for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
368  Changed |= processBasicBlock(MF, *BB);
369 
370  // Process any unreachable blocks in arbitrary order now.
371  if (MF.size() != Processed.size())
372  for (MachineBasicBlock &BB : MF)
373  if (Processed.insert(&BB).second)
374  Changed |= processBasicBlock(MF, BB);
375 
376  LiveBundles.clear();
377 
378  return Changed;
379 }
380 
381 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
382 /// live-out sets for the FP registers. Consistent means that the set of
383 /// registers live-out from a block is identical to the live-in set of all
384 /// successors. This is not enforced by the normal live-in lists since
385 /// registers may be implicitly defined, or not used by all successors.
386 void FPS::bundleCFGRecomputeKillFlags(MachineFunction &MF) {
387  assert(LiveBundles.empty() && "Stale data in LiveBundles");
388  LiveBundles.resize(Bundles->getNumBundles());
389 
390  // Gather the actual live-in masks for all MBBs.
391  for (MachineBasicBlock &MBB : MF) {
392  setKillFlags(MBB);
393 
394  const unsigned Mask = calcLiveInMask(&MBB, false);
395  if (!Mask)
396  continue;
397  // Update MBB ingoing bundle mask.
398  LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask;
399  }
400 }
401 
402 /// processBasicBlock - Loop over all of the instructions in the basic block,
403 /// transforming FP instructions into their stack form.
404 ///
405 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
406  bool Changed = false;
407  MBB = &BB;
408 
409  setupBlockStack();
410 
411  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
412  MachineInstr &MI = *I;
413  uint64_t Flags = MI.getDesc().TSFlags;
414 
415  unsigned FPInstClass = Flags & X86II::FPTypeMask;
416  if (MI.isInlineAsm())
417  FPInstClass = X86II::SpecialFP;
418 
419  if (MI.isCopy() && isFPCopy(MI))
420  FPInstClass = X86II::SpecialFP;
421 
422  if (MI.isImplicitDef() &&
423  X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
424  FPInstClass = X86II::SpecialFP;
425 
426  if (MI.isCall())
427  FPInstClass = X86II::SpecialFP;
428 
429  if (FPInstClass == X86II::NotFP)
430  continue; // Efficiently ignore non-fp insts!
431 
432  MachineInstr *PrevMI = nullptr;
433  if (I != BB.begin())
434  PrevMI = &*std::prev(I);
435 
436  ++NumFP; // Keep track of # of pseudo instrs
437  DEBUG(dbgs() << "\nFPInst:\t" << MI);
438 
439  // Get dead variables list now because the MI pointer may be deleted as part
440  // of processing!
441  SmallVector<unsigned, 8> DeadRegs;
442  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
443  const MachineOperand &MO = MI.getOperand(i);
444  if (MO.isReg() && MO.isDead())
445  DeadRegs.push_back(MO.getReg());
446  }
447 
448  switch (FPInstClass) {
449  case X86II::ZeroArgFP: handleZeroArgFP(I); break;
450  case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
451  case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
452  case X86II::TwoArgFP: handleTwoArgFP(I); break;
453  case X86II::CompareFP: handleCompareFP(I); break;
454  case X86II::CondMovFP: handleCondMovFP(I); break;
455  case X86II::SpecialFP: handleSpecialFP(I); break;
456  default: llvm_unreachable("Unknown FP Type!");
457  }
458 
459  // Check to see if any of the values defined by this instruction are dead
460  // after definition. If so, pop them.
461  for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
462  unsigned Reg = DeadRegs[i];
463  // Check if Reg is live on the stack. An inline-asm register operand that
464  // is in the clobber list and marked dead might not be live on the stack.
465  static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
466  if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
467  DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
468  freeStackSlotAfter(I, Reg-X86::FP0);
469  }
470  }
471 
472  // Print out all of the instructions expanded to if -debug
473  DEBUG({
474  MachineBasicBlock::iterator PrevI = PrevMI;
475  if (I == PrevI) {
476  dbgs() << "Just deleted pseudo instruction\n";
477  } else {
479  // Rewind to first instruction newly inserted.
480  while (Start != BB.begin() && std::prev(Start) != PrevI)
481  --Start;
482  dbgs() << "Inserted instructions:\n\t";
483  Start->print(dbgs());
484  while (++Start != std::next(I)) {
485  }
486  }
487  dumpStack();
488  });
489  (void)PrevMI;
490 
491  Changed = true;
492  }
493 
494  finishBlockStack();
495 
496  return Changed;
497 }
498 
499 /// setupBlockStack - Use the live bundles to set up our model of the stack
500 /// to match predecessors' live out stack.
501 void FPS::setupBlockStack() {
502  DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
503  << " derived from " << MBB->getName() << ".\n");
504  StackTop = 0;
505  // Get the live-in bundle for MBB.
506  const LiveBundle &Bundle =
507  LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
508 
509  if (!Bundle.Mask) {
510  DEBUG(dbgs() << "Block has no FP live-ins.\n");
511  return;
512  }
513 
514  // Depth-first iteration should ensure that we always have an assigned stack.
515  assert(Bundle.isFixed() && "Reached block before any predecessors");
516 
517  // Push the fixed live-in registers.
518  for (unsigned i = Bundle.FixCount; i > 0; --i) {
519  DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
520  << unsigned(Bundle.FixStack[i-1]) << '\n');
521  pushReg(Bundle.FixStack[i-1]);
522  }
523 
524  // Kill off unwanted live-ins. This can happen with a critical edge.
525  // FIXME: We could keep these live registers around as zombies. They may need
526  // to be revived at the end of a short block. It might save a few instrs.
527  unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true);
528  adjustLiveRegs(Mask, MBB->begin());
529  DEBUG(MBB->dump());
530 }
531 
532 /// finishBlockStack - Revive live-outs that are implicitly defined out of
533 /// MBB. Shuffle live registers to match the expected fixed stack of any
534 /// predecessors, and ensure that all predecessors are expecting the same
535 /// stack.
536 void FPS::finishBlockStack() {
537  // The RET handling below takes care of return blocks for us.
538  if (MBB->succ_empty())
539  return;
540 
541  DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
542  << " derived from " << MBB->getName() << ".\n");
543 
544  // Get MBB's live-out bundle.
545  unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
546  LiveBundle &Bundle = LiveBundles[BundleIdx];
547 
548  // We may need to kill and define some registers to match successors.
549  // FIXME: This can probably be combined with the shuffle below.
551  adjustLiveRegs(Bundle.Mask, Term);
552 
553  if (!Bundle.Mask) {
554  DEBUG(dbgs() << "No live-outs.\n");
555  return;
556  }
557 
558  // Has the stack order been fixed yet?
559  DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
560  if (Bundle.isFixed()) {
561  DEBUG(dbgs() << "Shuffling stack to match.\n");
562  shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
563  } else {
564  // Not fixed yet, we get to choose.
565  DEBUG(dbgs() << "Fixing stack order now.\n");
566  Bundle.FixCount = StackTop;
567  for (unsigned i = 0; i < StackTop; ++i)
568  Bundle.FixStack[i] = getStackEntry(i);
569  }
570 }
571 
572 
573 //===----------------------------------------------------------------------===//
574 // Efficient Lookup Table Support
575 //===----------------------------------------------------------------------===//
576 
577 namespace {
578  struct TableEntry {
579  uint16_t from;
580  uint16_t to;
581  bool operator<(const TableEntry &TE) const { return from < TE.from; }
582  friend bool operator<(const TableEntry &TE, unsigned V) {
583  return TE.from < V;
584  }
585  friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
586  const TableEntry &TE) {
587  return V < TE.from;
588  }
589  };
590 }
591 
592 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
593  const TableEntry *I = std::lower_bound(Table.begin(), Table.end(), Opcode);
594  if (I != Table.end() && I->from == Opcode)
595  return I->to;
596  return -1;
597 }
598 
599 #ifdef NDEBUG
600 #define ASSERT_SORTED(TABLE)
601 #else
602 #define ASSERT_SORTED(TABLE) \
603  { static bool TABLE##Checked = false; \
604  if (!TABLE##Checked) { \
605  assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) && \
606  "All lookup tables must be sorted for efficient access!"); \
607  TABLE##Checked = true; \
608  } \
609  }
610 #endif
611 
612 //===----------------------------------------------------------------------===//
613 // Register File -> Register Stack Mapping Methods
614 //===----------------------------------------------------------------------===//
615 
616 // OpcodeTable - Sorted map of register instructions to their stack version.
617 // The first element is an register file pseudo instruction, the second is the
618 // concrete X86 instruction which uses the register stack.
619 //
620 static const TableEntry OpcodeTable[] = {
621  { X86::ABS_Fp32 , X86::ABS_F },
622  { X86::ABS_Fp64 , X86::ABS_F },
623  { X86::ABS_Fp80 , X86::ABS_F },
624  { X86::ADD_Fp32m , X86::ADD_F32m },
625  { X86::ADD_Fp64m , X86::ADD_F64m },
626  { X86::ADD_Fp64m32 , X86::ADD_F32m },
627  { X86::ADD_Fp80m32 , X86::ADD_F32m },
628  { X86::ADD_Fp80m64 , X86::ADD_F64m },
629  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
630  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
631  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
632  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
633  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
634  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
635  { X86::CHS_Fp32 , X86::CHS_F },
636  { X86::CHS_Fp64 , X86::CHS_F },
637  { X86::CHS_Fp80 , X86::CHS_F },
638  { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
639  { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
640  { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
641  { X86::CMOVB_Fp32 , X86::CMOVB_F },
642  { X86::CMOVB_Fp64 , X86::CMOVB_F },
643  { X86::CMOVB_Fp80 , X86::CMOVB_F },
644  { X86::CMOVE_Fp32 , X86::CMOVE_F },
645  { X86::CMOVE_Fp64 , X86::CMOVE_F },
646  { X86::CMOVE_Fp80 , X86::CMOVE_F },
647  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
648  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
649  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
650  { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
651  { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
652  { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
653  { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
654  { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
655  { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
656  { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
657  { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
658  { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
659  { X86::CMOVP_Fp32 , X86::CMOVP_F },
660  { X86::CMOVP_Fp64 , X86::CMOVP_F },
661  { X86::CMOVP_Fp80 , X86::CMOVP_F },
662  { X86::COS_Fp32 , X86::COS_F },
663  { X86::COS_Fp64 , X86::COS_F },
664  { X86::COS_Fp80 , X86::COS_F },
665  { X86::DIVR_Fp32m , X86::DIVR_F32m },
666  { X86::DIVR_Fp64m , X86::DIVR_F64m },
667  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
668  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
669  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
670  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
671  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
672  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
673  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
674  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
675  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
676  { X86::DIV_Fp32m , X86::DIV_F32m },
677  { X86::DIV_Fp64m , X86::DIV_F64m },
678  { X86::DIV_Fp64m32 , X86::DIV_F32m },
679  { X86::DIV_Fp80m32 , X86::DIV_F32m },
680  { X86::DIV_Fp80m64 , X86::DIV_F64m },
681  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
682  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
683  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
684  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
685  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
686  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
687  { X86::ILD_Fp16m32 , X86::ILD_F16m },
688  { X86::ILD_Fp16m64 , X86::ILD_F16m },
689  { X86::ILD_Fp16m80 , X86::ILD_F16m },
690  { X86::ILD_Fp32m32 , X86::ILD_F32m },
691  { X86::ILD_Fp32m64 , X86::ILD_F32m },
692  { X86::ILD_Fp32m80 , X86::ILD_F32m },
693  { X86::ILD_Fp64m32 , X86::ILD_F64m },
694  { X86::ILD_Fp64m64 , X86::ILD_F64m },
695  { X86::ILD_Fp64m80 , X86::ILD_F64m },
696  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
697  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
698  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
699  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
700  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
701  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
702  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
703  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
704  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
705  { X86::IST_Fp16m32 , X86::IST_F16m },
706  { X86::IST_Fp16m64 , X86::IST_F16m },
707  { X86::IST_Fp16m80 , X86::IST_F16m },
708  { X86::IST_Fp32m32 , X86::IST_F32m },
709  { X86::IST_Fp32m64 , X86::IST_F32m },
710  { X86::IST_Fp32m80 , X86::IST_F32m },
711  { X86::IST_Fp64m32 , X86::IST_FP64m },
712  { X86::IST_Fp64m64 , X86::IST_FP64m },
713  { X86::IST_Fp64m80 , X86::IST_FP64m },
714  { X86::LD_Fp032 , X86::LD_F0 },
715  { X86::LD_Fp064 , X86::LD_F0 },
716  { X86::LD_Fp080 , X86::LD_F0 },
717  { X86::LD_Fp132 , X86::LD_F1 },
718  { X86::LD_Fp164 , X86::LD_F1 },
719  { X86::LD_Fp180 , X86::LD_F1 },
720  { X86::LD_Fp32m , X86::LD_F32m },
721  { X86::LD_Fp32m64 , X86::LD_F32m },
722  { X86::LD_Fp32m80 , X86::LD_F32m },
723  { X86::LD_Fp64m , X86::LD_F64m },
724  { X86::LD_Fp64m80 , X86::LD_F64m },
725  { X86::LD_Fp80m , X86::LD_F80m },
726  { X86::MUL_Fp32m , X86::MUL_F32m },
727  { X86::MUL_Fp64m , X86::MUL_F64m },
728  { X86::MUL_Fp64m32 , X86::MUL_F32m },
729  { X86::MUL_Fp80m32 , X86::MUL_F32m },
730  { X86::MUL_Fp80m64 , X86::MUL_F64m },
731  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
732  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
733  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
734  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
735  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
736  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
737  { X86::SIN_Fp32 , X86::SIN_F },
738  { X86::SIN_Fp64 , X86::SIN_F },
739  { X86::SIN_Fp80 , X86::SIN_F },
740  { X86::SQRT_Fp32 , X86::SQRT_F },
741  { X86::SQRT_Fp64 , X86::SQRT_F },
742  { X86::SQRT_Fp80 , X86::SQRT_F },
743  { X86::ST_Fp32m , X86::ST_F32m },
744  { X86::ST_Fp64m , X86::ST_F64m },
745  { X86::ST_Fp64m32 , X86::ST_F32m },
746  { X86::ST_Fp80m32 , X86::ST_F32m },
747  { X86::ST_Fp80m64 , X86::ST_F64m },
748  { X86::ST_FpP80m , X86::ST_FP80m },
749  { X86::SUBR_Fp32m , X86::SUBR_F32m },
750  { X86::SUBR_Fp64m , X86::SUBR_F64m },
751  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
752  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
753  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
754  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
755  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
756  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
757  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
758  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
759  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
760  { X86::SUB_Fp32m , X86::SUB_F32m },
761  { X86::SUB_Fp64m , X86::SUB_F64m },
762  { X86::SUB_Fp64m32 , X86::SUB_F32m },
763  { X86::SUB_Fp80m32 , X86::SUB_F32m },
764  { X86::SUB_Fp80m64 , X86::SUB_F64m },
765  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
766  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
767  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
768  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
769  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
770  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
771  { X86::TST_Fp32 , X86::TST_F },
772  { X86::TST_Fp64 , X86::TST_F },
773  { X86::TST_Fp80 , X86::TST_F },
774  { X86::UCOM_FpIr32 , X86::UCOM_FIr },
775  { X86::UCOM_FpIr64 , X86::UCOM_FIr },
776  { X86::UCOM_FpIr80 , X86::UCOM_FIr },
777  { X86::UCOM_Fpr32 , X86::UCOM_Fr },
778  { X86::UCOM_Fpr64 , X86::UCOM_Fr },
779  { X86::UCOM_Fpr80 , X86::UCOM_Fr },
780 };
781 
782 static unsigned getConcreteOpcode(unsigned Opcode) {
783  ASSERT_SORTED(OpcodeTable);
784  int Opc = Lookup(OpcodeTable, Opcode);
785  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
786  return Opc;
787 }
788 
789 //===----------------------------------------------------------------------===//
790 // Helper Methods
791 //===----------------------------------------------------------------------===//
792 
793 // PopTable - Sorted map of instructions to their popping version. The first
794 // element is an instruction, the second is the version which pops.
795 //
796 static const TableEntry PopTable[] = {
797  { X86::ADD_FrST0 , X86::ADD_FPrST0 },
798 
799  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
800  { X86::DIV_FrST0 , X86::DIV_FPrST0 },
801 
802  { X86::IST_F16m , X86::IST_FP16m },
803  { X86::IST_F32m , X86::IST_FP32m },
804 
805  { X86::MUL_FrST0 , X86::MUL_FPrST0 },
806 
807  { X86::ST_F32m , X86::ST_FP32m },
808  { X86::ST_F64m , X86::ST_FP64m },
809  { X86::ST_Frr , X86::ST_FPrr },
810 
811  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
812  { X86::SUB_FrST0 , X86::SUB_FPrST0 },
813 
814  { X86::UCOM_FIr , X86::UCOM_FIPr },
815 
816  { X86::UCOM_FPr , X86::UCOM_FPPr },
817  { X86::UCOM_Fr , X86::UCOM_FPr },
818 };
819 
820 /// popStackAfter - Pop the current value off of the top of the FP stack after
821 /// the specified instruction. This attempts to be sneaky and combine the pop
822 /// into the instruction itself if possible. The iterator is left pointing to
823 /// the last instruction, be it a new pop instruction inserted, or the old
824 /// instruction if it was modified in place.
825 ///
826 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
827  MachineInstr &MI = *I;
828  const DebugLoc &dl = MI.getDebugLoc();
829  ASSERT_SORTED(PopTable);
830 
831  popReg();
832 
833  // Check to see if there is a popping version of this instruction...
834  int Opcode = Lookup(PopTable, I->getOpcode());
835  if (Opcode != -1) {
836  I->setDesc(TII->get(Opcode));
837  if (Opcode == X86::UCOM_FPPr)
838  I->RemoveOperand(0);
839  } else { // Insert an explicit pop
840  I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
841  }
842 }
843 
844 /// freeStackSlotAfter - Free the specified register from the register stack, so
845 /// that it is no longer in a register. If the register is currently at the top
846 /// of the stack, we just pop the current instruction, otherwise we store the
847 /// current top-of-stack into the specified slot, then pop the top of stack.
848 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
849  if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
850  popStackAfter(I);
851  return;
852  }
853 
854  // Otherwise, store the top of stack into the dead slot, killing the operand
855  // without having to add in an explicit xchg then pop.
856  //
857  I = freeStackSlotBefore(++I, FPRegNo);
858 }
859 
860 /// freeStackSlotBefore - Free the specified register without trying any
861 /// folding.
863 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
864  unsigned STReg = getSTReg(FPRegNo);
865  unsigned OldSlot = getSlot(FPRegNo);
866  unsigned TopReg = Stack[StackTop-1];
867  Stack[OldSlot] = TopReg;
868  RegMap[TopReg] = OldSlot;
869  RegMap[FPRegNo] = ~0;
870  Stack[--StackTop] = ~0;
871  return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
872  .addReg(STReg)
873  .getInstr();
874 }
875 
876 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
877 /// registers with a bit in Mask are live.
878 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
879  unsigned Defs = Mask;
880  unsigned Kills = 0;
881  for (unsigned i = 0; i < StackTop; ++i) {
882  unsigned RegNo = Stack[i];
883  if (!(Defs & (1 << RegNo)))
884  // This register is live, but we don't want it.
885  Kills |= (1 << RegNo);
886  else
887  // We don't need to imp-def this live register.
888  Defs &= ~(1 << RegNo);
889  }
890  assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
891 
892  // Produce implicit-defs for free by using killed registers.
893  while (Kills && Defs) {
894  unsigned KReg = countTrailingZeros(Kills);
895  unsigned DReg = countTrailingZeros(Defs);
896  DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
897  std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
898  std::swap(RegMap[KReg], RegMap[DReg]);
899  Kills &= ~(1 << KReg);
900  Defs &= ~(1 << DReg);
901  }
902 
903  // Kill registers by popping.
904  if (Kills && I != MBB->begin()) {
905  MachineBasicBlock::iterator I2 = std::prev(I);
906  while (StackTop) {
907  unsigned KReg = getStackEntry(0);
908  if (!(Kills & (1 << KReg)))
909  break;
910  DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
911  popStackAfter(I2);
912  Kills &= ~(1 << KReg);
913  }
914  }
915 
916  // Manually kill the rest.
917  while (Kills) {
918  unsigned KReg = countTrailingZeros(Kills);
919  DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
920  freeStackSlotBefore(I, KReg);
921  Kills &= ~(1 << KReg);
922  }
923 
924  // Load zeros for all the imp-defs.
925  while(Defs) {
926  unsigned DReg = countTrailingZeros(Defs);
927  DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
928  BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
929  pushReg(DReg);
930  Defs &= ~(1 << DReg);
931  }
932 
933  // Now we should have the correct registers live.
934  DEBUG(dumpStack());
935  assert(StackTop == countPopulation(Mask) && "Live count mismatch");
936 }
937 
938 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
939 /// FixCount entries into the order given by FixStack.
940 /// FIXME: Is there a better algorithm than insertion sort?
941 void FPS::shuffleStackTop(const unsigned char *FixStack,
942  unsigned FixCount,
944  // Move items into place, starting from the desired stack bottom.
945  while (FixCount--) {
946  // Old register at position FixCount.
947  unsigned OldReg = getStackEntry(FixCount);
948  // Desired register at position FixCount.
949  unsigned Reg = FixStack[FixCount];
950  if (Reg == OldReg)
951  continue;
952  // (Reg st0) (OldReg st0) = (Reg OldReg st0)
953  moveToTop(Reg, I);
954  if (FixCount > 0)
955  moveToTop(OldReg, I);
956  }
957  DEBUG(dumpStack());
958 }
959 
960 
961 //===----------------------------------------------------------------------===//
962 // Instruction transformation implementation
963 //===----------------------------------------------------------------------===//
964 
965 void FPS::handleCall(MachineBasicBlock::iterator &I) {
966  unsigned STReturns = 0;
967  const MachineFunction* MF = I->getParent()->getParent();
968 
969  for (const auto &MO : I->operands()) {
970  if (!MO.isReg())
971  continue;
972 
973  unsigned R = MO.getReg() - X86::FP0;
974 
975  if (R < 8) {
977  assert(MO.isDef() && MO.isImplicit());
978  }
979 
980  STReturns |= 1 << R;
981  }
982  }
983 
984  unsigned N = countTrailingOnes(STReturns);
985 
986  // FP registers used for function return must be consecutive starting at
987  // FP0
988  assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
989 
990  // Reset the FP Stack - It is required because of possible leftovers from
991  // passed arguments. The caller should assume that the FP stack is
992  // returned empty (unless the callee returns values on FP stack).
993  while (StackTop > 0)
994  popReg();
995 
996  for (unsigned I = 0; I < N; ++I)
997  pushReg(N - I - 1);
998 }
999 
1000 /// If RET has an FP register use operand, pass the first one in ST(0) and
1001 /// the second one in ST(1).
1002 void FPS::handleReturn(MachineBasicBlock::iterator &I) {
1003  MachineInstr &MI = *I;
1004 
1005  // Find the register operands.
1006  unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1007  unsigned LiveMask = 0;
1008 
1009  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1010  MachineOperand &Op = MI.getOperand(i);
1011  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1012  continue;
1013  // FP Register uses must be kills unless there are two uses of the same
1014  // register, in which case only one will be a kill.
1015  assert(Op.isUse() &&
1016  (Op.isKill() || // Marked kill.
1017  getFPReg(Op) == FirstFPRegOp || // Second instance.
1018  MI.killsRegister(Op.getReg())) && // Later use is marked kill.
1019  "Ret only defs operands, and values aren't live beyond it");
1020 
1021  if (FirstFPRegOp == ~0U)
1022  FirstFPRegOp = getFPReg(Op);
1023  else {
1024  assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1025  SecondFPRegOp = getFPReg(Op);
1026  }
1027  LiveMask |= (1 << getFPReg(Op));
1028 
1029  // Remove the operand so that later passes don't see it.
1030  MI.RemoveOperand(i);
1031  --i;
1032  --e;
1033  }
1034 
1035  // We may have been carrying spurious live-ins, so make sure only the
1036  // returned registers are left live.
1037  adjustLiveRegs(LiveMask, MI);
1038  if (!LiveMask) return; // Quick check to see if any are possible.
1039 
1040  // There are only four possibilities here:
1041  // 1) we are returning a single FP value. In this case, it has to be in
1042  // ST(0) already, so just declare success by removing the value from the
1043  // FP Stack.
1044  if (SecondFPRegOp == ~0U) {
1045  // Assert that the top of stack contains the right FP register.
1046  assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1047  "Top of stack not the right register for RET!");
1048 
1049  // Ok, everything is good, mark the value as not being on the stack
1050  // anymore so that our assertion about the stack being empty at end of
1051  // block doesn't fire.
1052  StackTop = 0;
1053  return;
1054  }
1055 
1056  // Otherwise, we are returning two values:
1057  // 2) If returning the same value for both, we only have one thing in the FP
1058  // stack. Consider: RET FP1, FP1
1059  if (StackTop == 1) {
1060  assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1061  "Stack misconfiguration for RET!");
1062 
1063  // Duplicate the TOS so that we return it twice. Just pick some other FPx
1064  // register to hold it.
1065  unsigned NewReg = ScratchFPReg;
1066  duplicateToTop(FirstFPRegOp, NewReg, MI);
1067  FirstFPRegOp = NewReg;
1068  }
1069 
1070  /// Okay we know we have two different FPx operands now:
1071  assert(StackTop == 2 && "Must have two values live!");
1072 
1073  /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1074  /// in ST(1). In this case, emit an fxch.
1075  if (getStackEntry(0) == SecondFPRegOp) {
1076  assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1077  moveToTop(FirstFPRegOp, MI);
1078  }
1079 
1080  /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1081  /// ST(1). Just remove both from our understanding of the stack and return.
1082  assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1083  assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1084  StackTop = 0;
1085 }
1086 
1087 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
1088 ///
1089 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
1090  MachineInstr &MI = *I;
1091  unsigned DestReg = getFPReg(MI.getOperand(0));
1092 
1093  // Change from the pseudo instruction to the concrete instruction.
1094  MI.RemoveOperand(0); // Remove the explicit ST(0) operand
1095  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1096 
1097  // Result gets pushed on the stack.
1098  pushReg(DestReg);
1099 }
1100 
1101 /// handleOneArgFP - fst <mem>, ST(0)
1102 ///
1103 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
1104  MachineInstr &MI = *I;
1105  unsigned NumOps = MI.getDesc().getNumOperands();
1106  assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1107  "Can only handle fst* & ftst instructions!");
1108 
1109  // Is this the last use of the source register?
1110  unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1111  bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1112 
1113  // FISTP64m is strange because there isn't a non-popping versions.
1114  // If we have one _and_ we don't want to pop the operand, duplicate the value
1115  // on the stack instead of moving it. This ensure that popping the value is
1116  // always ok.
1117  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1118  //
1119  if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1120  MI.getOpcode() == X86::ISTT_Fp16m32 ||
1121  MI.getOpcode() == X86::ISTT_Fp32m32 ||
1122  MI.getOpcode() == X86::ISTT_Fp64m32 ||
1123  MI.getOpcode() == X86::IST_Fp64m64 ||
1124  MI.getOpcode() == X86::ISTT_Fp16m64 ||
1125  MI.getOpcode() == X86::ISTT_Fp32m64 ||
1126  MI.getOpcode() == X86::ISTT_Fp64m64 ||
1127  MI.getOpcode() == X86::IST_Fp64m80 ||
1128  MI.getOpcode() == X86::ISTT_Fp16m80 ||
1129  MI.getOpcode() == X86::ISTT_Fp32m80 ||
1130  MI.getOpcode() == X86::ISTT_Fp64m80 ||
1131  MI.getOpcode() == X86::ST_FpP80m)) {
1132  duplicateToTop(Reg, ScratchFPReg, I);
1133  } else {
1134  moveToTop(Reg, I); // Move to the top of the stack...
1135  }
1136 
1137  // Convert from the pseudo instruction to the concrete instruction.
1138  MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
1139  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1140 
1141  if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1142  MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1143  MI.getOpcode() == X86::ST_FP80m) {
1144  if (StackTop == 0)
1145  report_fatal_error("Stack empty??");
1146  --StackTop;
1147  } else if (KillsSrc) { // Last use of operand?
1148  popStackAfter(I);
1149  }
1150 }
1151 
1152 
1153 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1154 /// replace the value with a newly computed value. These instructions may have
1155 /// non-fp operands after their FP operands.
1156 ///
1157 /// Examples:
1158 /// R1 = fchs R2
1159 /// R1 = fadd R2, [mem]
1160 ///
1161 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1162  MachineInstr &MI = *I;
1163 #ifndef NDEBUG
1164  unsigned NumOps = MI.getDesc().getNumOperands();
1165  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1166 #endif
1167 
1168  // Is this the last use of the source register?
1169  unsigned Reg = getFPReg(MI.getOperand(1));
1170  bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1171 
1172  if (KillsSrc) {
1173  // If this is the last use of the source register, just make sure it's on
1174  // the top of the stack.
1175  moveToTop(Reg, I);
1176  if (StackTop == 0)
1177  report_fatal_error("Stack cannot be empty!");
1178  --StackTop;
1179  pushReg(getFPReg(MI.getOperand(0)));
1180  } else {
1181  // If this is not the last use of the source register, _copy_ it to the top
1182  // of the stack.
1183  duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1184  }
1185 
1186  // Change from the pseudo instruction to the concrete instruction.
1187  MI.RemoveOperand(1); // Drop the source operand.
1188  MI.RemoveOperand(0); // Drop the destination operand.
1189  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1190 }
1191 
1192 
1193 //===----------------------------------------------------------------------===//
1194 // Define tables of various ways to map pseudo instructions
1195 //
1196 
1197 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1198 static const TableEntry ForwardST0Table[] = {
1199  { X86::ADD_Fp32 , X86::ADD_FST0r },
1200  { X86::ADD_Fp64 , X86::ADD_FST0r },
1201  { X86::ADD_Fp80 , X86::ADD_FST0r },
1202  { X86::DIV_Fp32 , X86::DIV_FST0r },
1203  { X86::DIV_Fp64 , X86::DIV_FST0r },
1204  { X86::DIV_Fp80 , X86::DIV_FST0r },
1205  { X86::MUL_Fp32 , X86::MUL_FST0r },
1206  { X86::MUL_Fp64 , X86::MUL_FST0r },
1207  { X86::MUL_Fp80 , X86::MUL_FST0r },
1208  { X86::SUB_Fp32 , X86::SUB_FST0r },
1209  { X86::SUB_Fp64 , X86::SUB_FST0r },
1210  { X86::SUB_Fp80 , X86::SUB_FST0r },
1211 };
1212 
1213 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1214 static const TableEntry ReverseST0Table[] = {
1215  { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1216  { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1217  { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1218  { X86::DIV_Fp32 , X86::DIVR_FST0r },
1219  { X86::DIV_Fp64 , X86::DIVR_FST0r },
1220  { X86::DIV_Fp80 , X86::DIVR_FST0r },
1221  { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1222  { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1223  { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1224  { X86::SUB_Fp32 , X86::SUBR_FST0r },
1225  { X86::SUB_Fp64 , X86::SUBR_FST0r },
1226  { X86::SUB_Fp80 , X86::SUBR_FST0r },
1227 };
1228 
1229 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1230 static const TableEntry ForwardSTiTable[] = {
1231  { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1232  { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1233  { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1234  { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1235  { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1236  { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1237  { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1238  { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1239  { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1240  { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1241  { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1242  { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1243 };
1244 
1245 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1246 static const TableEntry ReverseSTiTable[] = {
1247  { X86::ADD_Fp32 , X86::ADD_FrST0 },
1248  { X86::ADD_Fp64 , X86::ADD_FrST0 },
1249  { X86::ADD_Fp80 , X86::ADD_FrST0 },
1250  { X86::DIV_Fp32 , X86::DIV_FrST0 },
1251  { X86::DIV_Fp64 , X86::DIV_FrST0 },
1252  { X86::DIV_Fp80 , X86::DIV_FrST0 },
1253  { X86::MUL_Fp32 , X86::MUL_FrST0 },
1254  { X86::MUL_Fp64 , X86::MUL_FrST0 },
1255  { X86::MUL_Fp80 , X86::MUL_FrST0 },
1256  { X86::SUB_Fp32 , X86::SUB_FrST0 },
1257  { X86::SUB_Fp64 , X86::SUB_FrST0 },
1258  { X86::SUB_Fp80 , X86::SUB_FrST0 },
1259 };
1260 
1261 
1262 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1263 /// instructions which need to be simplified and possibly transformed.
1264 ///
1265 /// Result: ST(0) = fsub ST(0), ST(i)
1266 /// ST(i) = fsub ST(0), ST(i)
1267 /// ST(0) = fsubr ST(0), ST(i)
1268 /// ST(i) = fsubr ST(0), ST(i)
1269 ///
1270 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1271  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1272  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1273  MachineInstr &MI = *I;
1274 
1275  unsigned NumOperands = MI.getDesc().getNumOperands();
1276  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1277  unsigned Dest = getFPReg(MI.getOperand(0));
1278  unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1279  unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1280  bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1281  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1282  DebugLoc dl = MI.getDebugLoc();
1283 
1284  unsigned TOS = getStackEntry(0);
1285 
1286  // One of our operands must be on the top of the stack. If neither is yet, we
1287  // need to move one.
1288  if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1289  // We can choose to move either operand to the top of the stack. If one of
1290  // the operands is killed by this instruction, we want that one so that we
1291  // can update right on top of the old version.
1292  if (KillsOp0) {
1293  moveToTop(Op0, I); // Move dead operand to TOS.
1294  TOS = Op0;
1295  } else if (KillsOp1) {
1296  moveToTop(Op1, I);
1297  TOS = Op1;
1298  } else {
1299  // All of the operands are live after this instruction executes, so we
1300  // cannot update on top of any operand. Because of this, we must
1301  // duplicate one of the stack elements to the top. It doesn't matter
1302  // which one we pick.
1303  //
1304  duplicateToTop(Op0, Dest, I);
1305  Op0 = TOS = Dest;
1306  KillsOp0 = true;
1307  }
1308  } else if (!KillsOp0 && !KillsOp1) {
1309  // If we DO have one of our operands at the top of the stack, but we don't
1310  // have a dead operand, we must duplicate one of the operands to a new slot
1311  // on the stack.
1312  duplicateToTop(Op0, Dest, I);
1313  Op0 = TOS = Dest;
1314  KillsOp0 = true;
1315  }
1316 
1317  // Now we know that one of our operands is on the top of the stack, and at
1318  // least one of our operands is killed by this instruction.
1319  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1320  "Stack conditions not set up right!");
1321 
1322  // We decide which form to use based on what is on the top of the stack, and
1323  // which operand is killed by this instruction.
1324  ArrayRef<TableEntry> InstTable;
1325  bool isForward = TOS == Op0;
1326  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1327  if (updateST0) {
1328  if (isForward)
1329  InstTable = ForwardST0Table;
1330  else
1331  InstTable = ReverseST0Table;
1332  } else {
1333  if (isForward)
1334  InstTable = ForwardSTiTable;
1335  else
1336  InstTable = ReverseSTiTable;
1337  }
1338 
1339  int Opcode = Lookup(InstTable, MI.getOpcode());
1340  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1341 
1342  // NotTOS - The register which is not on the top of stack...
1343  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1344 
1345  // Replace the old instruction with a new instruction
1346  MBB->remove(&*I++);
1347  I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1348 
1349  // If both operands are killed, pop one off of the stack in addition to
1350  // overwriting the other one.
1351  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1352  assert(!updateST0 && "Should have updated other operand!");
1353  popStackAfter(I); // Pop the top of stack
1354  }
1355 
1356  // Update stack information so that we know the destination register is now on
1357  // the stack.
1358  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1359  assert(UpdatedSlot < StackTop && Dest < 7);
1360  Stack[UpdatedSlot] = Dest;
1361  RegMap[Dest] = UpdatedSlot;
1362  MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction
1363 }
1364 
1365 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1366 /// register arguments and no explicit destinations.
1367 ///
1368 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1369  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1370  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1371  MachineInstr &MI = *I;
1372 
1373  unsigned NumOperands = MI.getDesc().getNumOperands();
1374  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1375  unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1376  unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1377  bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1378  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1379 
1380  // Make sure the first operand is on the top of stack, the other one can be
1381  // anywhere.
1382  moveToTop(Op0, I);
1383 
1384  // Change from the pseudo instruction to the concrete instruction.
1385  MI.getOperand(0).setReg(getSTReg(Op1));
1386  MI.RemoveOperand(1);
1387  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1388 
1389  // If any of the operands are killed by this instruction, free them.
1390  if (KillsOp0) freeStackSlotAfter(I, Op0);
1391  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1392 }
1393 
1394 /// handleCondMovFP - Handle two address conditional move instructions. These
1395 /// instructions move a st(i) register to st(0) iff a condition is true. These
1396 /// instructions require that the first operand is at the top of the stack, but
1397 /// otherwise don't modify the stack at all.
1398 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1399  MachineInstr &MI = *I;
1400 
1401  unsigned Op0 = getFPReg(MI.getOperand(0));
1402  unsigned Op1 = getFPReg(MI.getOperand(2));
1403  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1404 
1405  // The first operand *must* be on the top of the stack.
1406  moveToTop(Op0, I);
1407 
1408  // Change the second operand to the stack register that the operand is in.
1409  // Change from the pseudo instruction to the concrete instruction.
1410  MI.RemoveOperand(0);
1411  MI.RemoveOperand(1);
1412  MI.getOperand(0).setReg(getSTReg(Op1));
1413  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1414 
1415  // If we kill the second operand, make sure to pop it from the stack.
1416  if (Op0 != Op1 && KillsOp1) {
1417  // Get this value off of the register stack.
1418  freeStackSlotAfter(I, Op1);
1419  }
1420 }
1421 
1422 
1423 /// handleSpecialFP - Handle special instructions which behave unlike other
1424 /// floating point instructions. This is primarily intended for use by pseudo
1425 /// instructions.
1426 ///
1427 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1428  MachineInstr &MI = *Inst;
1429 
1430  if (MI.isCall()) {
1431  handleCall(Inst);
1432  return;
1433  }
1434 
1435  if (MI.isReturn()) {
1436  handleReturn(Inst);
1437  return;
1438  }
1439 
1440  switch (MI.getOpcode()) {
1441  default: llvm_unreachable("Unknown SpecialFP instruction!");
1442  case TargetOpcode::COPY: {
1443  // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1444  const MachineOperand &MO1 = MI.getOperand(1);
1445  const MachineOperand &MO0 = MI.getOperand(0);
1446  bool KillsSrc = MI.killsRegister(MO1.getReg());
1447 
1448  // FP <- FP copy.
1449  unsigned DstFP = getFPReg(MO0);
1450  unsigned SrcFP = getFPReg(MO1);
1451  assert(isLive(SrcFP) && "Cannot copy dead register");
1452  if (KillsSrc) {
1453  // If the input operand is killed, we can just change the owner of the
1454  // incoming stack slot into the result.
1455  unsigned Slot = getSlot(SrcFP);
1456  Stack[Slot] = DstFP;
1457  RegMap[DstFP] = Slot;
1458  } else {
1459  // For COPY we just duplicate the specified value to a new stack slot.
1460  // This could be made better, but would require substantial changes.
1461  duplicateToTop(SrcFP, DstFP, Inst);
1462  }
1463  break;
1464  }
1465 
1466  case TargetOpcode::IMPLICIT_DEF: {
1467  // All FP registers must be explicitly defined, so load a 0 instead.
1468  unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1469  DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1470  BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1471  pushReg(Reg);
1472  break;
1473  }
1474 
1475  case TargetOpcode::INLINEASM: {
1476  // The inline asm MachineInstr currently only *uses* FP registers for the
1477  // 'f' constraint. These should be turned into the current ST(x) register
1478  // in the machine instr.
1479  //
1480  // There are special rules for x87 inline assembly. The compiler must know
1481  // exactly how many registers are popped and pushed implicitly by the asm.
1482  // Otherwise it is not possible to restore the stack state after the inline
1483  // asm.
1484  //
1485  // There are 3 kinds of input operands:
1486  //
1487  // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1488  // popped input operand must be in a fixed stack slot, and it is either
1489  // tied to an output operand, or in the clobber list. The MI has ST use
1490  // and def operands for these inputs.
1491  //
1492  // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1493  // preserved by the inline asm. The fixed stack slots must be STn-STm
1494  // following the popped inputs. A fixed input operand cannot be tied to
1495  // an output or appear in the clobber list. The MI has ST use operands
1496  // and no defs for these inputs.
1497  //
1498  // 3. Preserved inputs. These inputs use the "f" constraint which is
1499  // represented as an FP register. The inline asm won't change these
1500  // stack slots.
1501  //
1502  // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1503  // registers do not count as output operands. The inline asm changes the
1504  // stack as if it popped all the popped inputs and then pushed all the
1505  // output operands.
1506 
1507  // Scan the assembly for ST registers used, defined and clobbered. We can
1508  // only tell clobbers from defs by looking at the asm descriptor.
1509  unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1510  unsigned NumOps = 0;
1511  SmallSet<unsigned, 1> FRegIdx;
1512  unsigned RCID;
1513 
1514  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
1515  i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1516  unsigned Flags = MI.getOperand(i).getImm();
1517 
1518  NumOps = InlineAsm::getNumOperandRegisters(Flags);
1519  if (NumOps != 1)
1520  continue;
1521  const MachineOperand &MO = MI.getOperand(i + 1);
1522  if (!MO.isReg())
1523  continue;
1524  unsigned STReg = MO.getReg() - X86::FP0;
1525  if (STReg >= 8)
1526  continue;
1527 
1528  // If the flag has a register class constraint, this must be an operand
1529  // with constraint "f". Record its index and continue.
1530  if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1531  FRegIdx.insert(i + 1);
1532  continue;
1533  }
1534 
1535  switch (InlineAsm::getKind(Flags)) {
1537  STUses |= (1u << STReg);
1538  break;
1541  STDefs |= (1u << STReg);
1542  if (MO.isDead())
1543  STDeadDefs |= (1u << STReg);
1544  break;
1546  STClobbers |= (1u << STReg);
1547  break;
1548  default:
1549  break;
1550  }
1551  }
1552 
1553  if (STUses && !isMask_32(STUses))
1554  MI.emitError("fixed input regs must be last on the x87 stack");
1555  unsigned NumSTUses = countTrailingOnes(STUses);
1556 
1557  // Defs must be contiguous from the stack top. ST0-STn.
1558  if (STDefs && !isMask_32(STDefs)) {
1559  MI.emitError("output regs must be last on the x87 stack");
1560  STDefs = NextPowerOf2(STDefs) - 1;
1561  }
1562  unsigned NumSTDefs = countTrailingOnes(STDefs);
1563 
1564  // So must the clobbered stack slots. ST0-STm, m >= n.
1565  if (STClobbers && !isMask_32(STDefs | STClobbers))
1566  MI.emitError("clobbers must be last on the x87 stack");
1567 
1568  // Popped inputs are the ones that are also clobbered or defined.
1569  unsigned STPopped = STUses & (STDefs | STClobbers);
1570  if (STPopped && !isMask_32(STPopped))
1571  MI.emitError("implicitly popped regs must be last on the x87 stack");
1572  unsigned NumSTPopped = countTrailingOnes(STPopped);
1573 
1574  DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1575  << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1576 
1577 #ifndef NDEBUG
1578  // If any input operand uses constraint "f", all output register
1579  // constraints must be early-clobber defs.
1580  for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I)
1581  if (FRegIdx.count(I)) {
1582  assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1583  "Operands with constraint \"f\" cannot overlap with defs");
1584  }
1585 #endif
1586 
1587  // Collect all FP registers (register operands with constraints "t", "u",
1588  // and "f") to kill afer the instruction.
1589  unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1590  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1591  MachineOperand &Op = MI.getOperand(i);
1592  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1593  continue;
1594  unsigned FPReg = getFPReg(Op);
1595 
1596  // If we kill this operand, make sure to pop it from the stack after the
1597  // asm. We just remember it for now, and pop them all off at the end in
1598  // a batch.
1599  if (Op.isUse() && Op.isKill())
1600  FPKills |= 1U << FPReg;
1601  }
1602 
1603  // Do not include registers that are implicitly popped by defs/clobbers.
1604  FPKills &= ~(STDefs | STClobbers);
1605 
1606  // Now we can rearrange the live registers to match what was requested.
1607  unsigned char STUsesArray[8];
1608 
1609  for (unsigned I = 0; I < NumSTUses; ++I)
1610  STUsesArray[I] = I;
1611 
1612  shuffleStackTop(STUsesArray, NumSTUses, Inst);
1613  DEBUG({dbgs() << "Before asm: "; dumpStack();});
1614 
1615  // With the stack layout fixed, rewrite the FP registers.
1616  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1617  MachineOperand &Op = MI.getOperand(i);
1618  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1619  continue;
1620 
1621  unsigned FPReg = getFPReg(Op);
1622 
1623  if (FRegIdx.count(i))
1624  // Operand with constraint "f".
1625  Op.setReg(getSTReg(FPReg));
1626  else
1627  // Operand with a single register class constraint ("t" or "u").
1628  Op.setReg(X86::ST0 + FPReg);
1629  }
1630 
1631  // Simulate the inline asm popping its inputs and pushing its outputs.
1632  StackTop -= NumSTPopped;
1633 
1634  for (unsigned i = 0; i < NumSTDefs; ++i)
1635  pushReg(NumSTDefs - i - 1);
1636 
1637  // If this asm kills any FP registers (is the last use of them) we must
1638  // explicitly emit pop instructions for them. Do this now after the asm has
1639  // executed so that the ST(x) numbers are not off (which would happen if we
1640  // did this inline with operand rewriting).
1641  //
1642  // Note: this might be a non-optimal pop sequence. We might be able to do
1643  // better by trying to pop in stack order or something.
1644  while (FPKills) {
1645  unsigned FPReg = countTrailingZeros(FPKills);
1646  if (isLive(FPReg))
1647  freeStackSlotAfter(Inst, FPReg);
1648  FPKills &= ~(1U << FPReg);
1649  }
1650 
1651  // Don't delete the inline asm!
1652  return;
1653  }
1654  }
1655 
1656  Inst = MBB->erase(Inst); // Remove the pseudo instruction
1657 
1658  // We want to leave I pointing to the previous instruction, but what if we
1659  // just erased the first instruction?
1660  if (Inst == MBB->begin()) {
1661  DEBUG(dbgs() << "Inserting dummy KILL\n");
1662  Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1663  } else
1664  --Inst;
1665 }
1666 
1667 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1668  const TargetRegisterInfo &TRI =
1670  LivePhysRegs LPR(TRI);
1671 
1672  LPR.addLiveOuts(MBB);
1673 
1674  for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1675  I != E; ++I) {
1676  if (I->isDebugValue())
1677  continue;
1678 
1679  std::bitset<8> Defs;
1681  MachineInstr &MI = *I;
1682 
1683  for (auto &MO : I->operands()) {
1684  if (!MO.isReg())
1685  continue;
1686 
1687  unsigned Reg = MO.getReg() - X86::FP0;
1688 
1689  if (Reg >= 8)
1690  continue;
1691 
1692  if (MO.isDef()) {
1693  Defs.set(Reg);
1694  if (!LPR.contains(MO.getReg()))
1695  MO.setIsDead();
1696  } else
1697  Uses.push_back(&MO);
1698  }
1699 
1700  for (auto *MO : Uses)
1701  if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1702  MO->setIsKill();
1703 
1704  LPR.stepBackward(MI);
1705  }
1706 }
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
static const TableEntry OpcodeTable[]
void push_back(const T &Elt)
Definition: SmallVector.h:212
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:458
unsigned getBundle(unsigned N, bool Out) const
getBundle - Return the ingoing (Out = false) or outgoing (Out = true) bundle number for basic block N...
Definition: EdgeBundles.h:43
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static unsigned getConcreteOpcode(unsigned Opcode)
iterator begin() const
Definition: ArrayRef.h:137
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:204
unsigned size() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getReg() const
getReg - Returns the register number.
bool isInlineAsm() const
Definition: MachineInstr.h:832
STATISTIC(NumFunctions, "Total number of functions")
A debug info location.
Definition: DebugLoc.h:34
static const TableEntry ReverseSTiTable[]
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
Definition: MathExtras.h:397
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
AnalysisUsage & addRequired()
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool contains(unsigned Reg) const
Returns true if register Reg is contained in the set.
Definition: LivePhysRegs.h:106
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:293
std::size_t countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
Definition: MathExtras.h:470
static int Lookup(ArrayRef< TableEntry > Table, unsigned Opcode)
static bool isLive(const MachineInstr &MI, const LivePhysRegs &LiveRegs, const TargetRegisterInfo *TRI, unsigned Reg)
Check if register Reg is live after the MI.
Reg
All possible values of the reg field in the ModR/M byte.
static const TableEntry ForwardST0Table[]
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
LiveInVector::const_iterator livein_iterator
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:287
static unsigned getFPReg(const MachineOperand &MO)
getFPReg - Return the X86::FPx register number for the specified operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
AnalysisUsage & addPreservedID(const void *ID)
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:904
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
reverse_iterator rend()
reverse_iterator rbegin()
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static const TableEntry PopTable[]
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:454
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static const TableEntry ForwardSTiTable[]
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
livein_iterator livein_end() const
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)
Represent the analysis usage information of a pass.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:144
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:81
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool isCopy() const
Definition: MachineInstr.h:857
bool isImplicitDef() const
Definition: MachineInstr.h:831
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:632
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
size_type size() const
Definition: SmallPtrSet.h:93
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:512
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
iterator end() const
Definition: ArrayRef.h:138
std::pair< iterator, bool > insert(NodeRef N)
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:285
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
unsigned getNumBundles() const
getNumBundles - Return the total number of bundles in the CFG.
Definition: EdgeBundles.h:46
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:351
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:948
static const TableEntry ReverseST0Table[]
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
#define ASSERT_SORTED(TABLE)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:118
void initializeEdgeBundlesPass(PassRegistry &)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
livein_iterator livein_begin() const
Properties which a MachineFunction may have at a given point in time.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:65
void resize(size_type N)
Definition: SmallVector.h:355