LLVM  7.0.0svn
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVRISelLowering.h"
16 
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRTargetMachine.h"
31 
32 namespace llvm {
33 
35  : TargetLowering(tm) {
36  // Set up the register classes.
37  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
39 
40  // Compute derived properties from the register classes.
42 
48 
51 
56 
57  for (MVT VT : MVT::integer_valuetypes()) {
58  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
61  }
62  }
63 
65 
66  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
67  // revert into a sub since we don't have an add with immediate instruction.
70 
71  // our shift instructions are only able to shift 1 bit at a time, so handle
72  // this in a custom way.
82 
87 
93 
104 
106 
107  // Add support for postincrement and predecrement load/stores.
116 
118 
123 
124  // Atomic operations which must be lowered to rtlib calls
125  for (MVT VT : MVT::integer_valuetypes()) {
133  }
134 
135  // Division/remainder
144 
145  // Make division and modulus custom
146  for (MVT VT : MVT::integer_valuetypes()) {
149  }
150 
151  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
154 
155  // Expand 16 bit multiplications.
158 
159  for (MVT VT : MVT::integer_valuetypes()) {
162  }
163 
164  for (MVT VT : MVT::integer_valuetypes()) {
168  }
169 
170  for (MVT VT : MVT::integer_valuetypes()) {
172  // TODO: The generated code is pretty poor. Investigate using the
173  // same "shift and subtract with carry" trick that we do for
174  // extending 8-bit to 16-bit. This may require infrastructure
175  // improvements in how we treat 16-bit "registers" to be feasible.
176  }
177 
178  // Division rtlib functions (not supported)
179  setLibcallName(RTLIB::SDIV_I8, nullptr);
180  setLibcallName(RTLIB::SDIV_I16, nullptr);
181  setLibcallName(RTLIB::SDIV_I32, nullptr);
182  setLibcallName(RTLIB::SDIV_I64, nullptr);
183  setLibcallName(RTLIB::SDIV_I128, nullptr);
184  setLibcallName(RTLIB::UDIV_I8, nullptr);
185  setLibcallName(RTLIB::UDIV_I16, nullptr);
186  setLibcallName(RTLIB::UDIV_I32, nullptr);
187  setLibcallName(RTLIB::UDIV_I64, nullptr);
188  setLibcallName(RTLIB::UDIV_I128, nullptr);
189 
190  // Modulus rtlib functions (not supported)
191  setLibcallName(RTLIB::SREM_I8, nullptr);
192  setLibcallName(RTLIB::SREM_I16, nullptr);
193  setLibcallName(RTLIB::SREM_I32, nullptr);
194  setLibcallName(RTLIB::SREM_I64, nullptr);
195  setLibcallName(RTLIB::SREM_I128, nullptr);
196  setLibcallName(RTLIB::UREM_I8, nullptr);
197  setLibcallName(RTLIB::UREM_I16, nullptr);
198  setLibcallName(RTLIB::UREM_I32, nullptr);
199  setLibcallName(RTLIB::UREM_I64, nullptr);
200  setLibcallName(RTLIB::UREM_I128, nullptr);
201 
202  // Division and modulus rtlib functions
203  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
204  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
205  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
206  setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
207  setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
208  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
209  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
210  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
211  setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
212  setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
213 
214  // Several of the runtime library functions use a special calling conv
216  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
218  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
219 
220  // Trigonometric rtlib functions
221  setLibcallName(RTLIB::SIN_F32, "sin");
222  setLibcallName(RTLIB::COS_F32, "cos");
223 
226 }
227 
228 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
229 #define NODE(name) \
230  case AVRISD::name: \
231  return #name
232 
233  switch (Opcode) {
234  default:
235  return nullptr;
236  NODE(RET_FLAG);
237  NODE(RETI_FLAG);
238  NODE(CALL);
239  NODE(WRAPPER);
240  NODE(LSL);
241  NODE(LSR);
242  NODE(ROL);
243  NODE(ROR);
244  NODE(ASR);
245  NODE(LSLLOOP);
246  NODE(LSRLOOP);
247  NODE(ASRLOOP);
248  NODE(BRCOND);
249  NODE(CMP);
250  NODE(CMPC);
251  NODE(TST);
252  NODE(SELECT_CC);
253 #undef NODE
254  }
255 }
256 
258  EVT VT) const {
259  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
260  return MVT::i8;
261 }
262 
263 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
264  //:TODO: this function has to be completely rewritten to produce optimal
265  // code, for now it's producing very long but correct code.
266  unsigned Opc8;
267  const SDNode *N = Op.getNode();
268  EVT VT = Op.getValueType();
269  SDLoc dl(N);
270 
271  // Expand non-constant shifts to loops.
272  if (!isa<ConstantSDNode>(N->getOperand(1))) {
273  switch (Op.getOpcode()) {
274  default:
275  llvm_unreachable("Invalid shift opcode!");
276  case ISD::SHL:
277  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
278  N->getOperand(1));
279  case ISD::SRL:
280  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
281  N->getOperand(1));
282  case ISD::ROTL:
283  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
284  N->getOperand(1));
285  case ISD::ROTR:
286  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
287  N->getOperand(1));
288  case ISD::SRA:
289  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
290  N->getOperand(1));
291  }
292  }
293 
294  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
295  SDValue Victim = N->getOperand(0);
296 
297  switch (Op.getOpcode()) {
298  case ISD::SRA:
299  Opc8 = AVRISD::ASR;
300  break;
301  case ISD::ROTL:
302  Opc8 = AVRISD::ROL;
303  break;
304  case ISD::ROTR:
305  Opc8 = AVRISD::ROR;
306  break;
307  case ISD::SRL:
308  Opc8 = AVRISD::LSR;
309  break;
310  case ISD::SHL:
311  Opc8 = AVRISD::LSL;
312  break;
313  default:
314  llvm_unreachable("Invalid shift opcode");
315  }
316 
317  while (ShiftAmount--) {
318  Victim = DAG.getNode(Opc8, dl, VT, Victim);
319  }
320 
321  return Victim;
322 }
323 
324 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
325  unsigned Opcode = Op->getOpcode();
326  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
327  "Invalid opcode for Div/Rem lowering");
328  bool IsSigned = (Opcode == ISD::SDIVREM);
329  EVT VT = Op->getValueType(0);
330  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
331 
332  RTLIB::Libcall LC;
333  switch (VT.getSimpleVT().SimpleTy) {
334  default:
335  llvm_unreachable("Unexpected request for libcall!");
336  case MVT::i8:
337  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
338  break;
339  case MVT::i16:
340  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
341  break;
342  case MVT::i32:
343  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
344  break;
345  case MVT::i64:
346  LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
347  break;
348  }
349 
350  SDValue InChain = DAG.getEntryNode();
351 
354  for (SDValue const &Value : Op->op_values()) {
355  Entry.Node = Value;
356  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
357  Entry.IsSExt = IsSigned;
358  Entry.IsZExt = !IsSigned;
359  Args.push_back(Entry);
360  }
361 
363  getPointerTy(DAG.getDataLayout()));
364 
365  Type *RetTy = (Type *)StructType::get(Ty, Ty);
366 
367  SDLoc dl(Op);
369  CLI.setDebugLoc(dl)
370  .setChain(InChain)
371  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
372  .setInRegister()
373  .setSExtResult(IsSigned)
374  .setZExtResult(!IsSigned);
375 
376  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
377  return CallInfo.first;
378 }
379 
380 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
381  SelectionDAG &DAG) const {
382  auto DL = DAG.getDataLayout();
383 
384  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
385  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
386 
387  // Create the TargetGlobalAddress node, folding in the constant offset.
388  SDValue Result =
389  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
390  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
391 }
392 
393 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
394  SelectionDAG &DAG) const {
395  auto DL = DAG.getDataLayout();
396  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
397 
398  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
399 
400  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
401 }
402 
403 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
405  switch (CC) {
406  default:
407  llvm_unreachable("Unknown condition code!");
408  case ISD::SETEQ:
409  return AVRCC::COND_EQ;
410  case ISD::SETNE:
411  return AVRCC::COND_NE;
412  case ISD::SETGE:
413  return AVRCC::COND_GE;
414  case ISD::SETLT:
415  return AVRCC::COND_LT;
416  case ISD::SETUGE:
417  return AVRCC::COND_SH;
418  case ISD::SETULT:
419  return AVRCC::COND_LO;
420  }
421 }
422 
423 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
424 /// the given operands.
425 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
426  SDValue &AVRcc, SelectionDAG &DAG,
427  SDLoc DL) const {
428  SDValue Cmp;
429  EVT VT = LHS.getValueType();
430  bool UseTest = false;
431 
432  switch (CC) {
433  default:
434  break;
435  case ISD::SETLE: {
436  // Swap operands and reverse the branching condition.
437  std::swap(LHS, RHS);
438  CC = ISD::SETGE;
439  break;
440  }
441  case ISD::SETGT: {
442  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
443  switch (C->getSExtValue()) {
444  case -1: {
445  // When doing lhs > -1 use a tst instruction on the top part of lhs
446  // and use brpl instead of using a chain of cp/cpc.
447  UseTest = true;
448  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
449  break;
450  }
451  case 0: {
452  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
453  // __zero_reg__ in lhs.
454  RHS = LHS;
455  LHS = DAG.getConstant(0, DL, VT);
456  CC = ISD::SETLT;
457  break;
458  }
459  default: {
460  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
461  // us to fold the constant into the cmp instruction.
462  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
463  CC = ISD::SETGE;
464  break;
465  }
466  }
467  break;
468  }
469  // Swap operands and reverse the branching condition.
470  std::swap(LHS, RHS);
471  CC = ISD::SETLT;
472  break;
473  }
474  case ISD::SETLT: {
475  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
476  switch (C->getSExtValue()) {
477  case 1: {
478  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
479  // __zero_reg__ in lhs.
480  RHS = LHS;
481  LHS = DAG.getConstant(0, DL, VT);
482  CC = ISD::SETGE;
483  break;
484  }
485  case 0: {
486  // When doing lhs < 0 use a tst instruction on the top part of lhs
487  // and use brmi instead of using a chain of cp/cpc.
488  UseTest = true;
489  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
490  break;
491  }
492  }
493  }
494  break;
495  }
496  case ISD::SETULE: {
497  // Swap operands and reverse the branching condition.
498  std::swap(LHS, RHS);
499  CC = ISD::SETUGE;
500  break;
501  }
502  case ISD::SETUGT: {
503  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
504  // fold the constant into the cmp instruction.
505  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
506  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
507  CC = ISD::SETUGE;
508  break;
509  }
510  // Swap operands and reverse the branching condition.
511  std::swap(LHS, RHS);
512  CC = ISD::SETULT;
513  break;
514  }
515  }
516 
517  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
518  // using the default and/or/xor expansion code which is much longer.
519  if (VT == MVT::i32) {
520  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
521  DAG.getIntPtrConstant(0, DL));
522  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
523  DAG.getIntPtrConstant(1, DL));
524  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
525  DAG.getIntPtrConstant(0, DL));
526  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
527  DAG.getIntPtrConstant(1, DL));
528 
529  if (UseTest) {
530  // When using tst we only care about the highest part.
531  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
532  DAG.getIntPtrConstant(1, DL));
533  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
534  } else {
535  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
536  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
537  }
538  } else if (VT == MVT::i64) {
539  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
540  DAG.getIntPtrConstant(0, DL));
541  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
542  DAG.getIntPtrConstant(1, DL));
543 
544  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
545  DAG.getIntPtrConstant(0, DL));
546  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
547  DAG.getIntPtrConstant(1, DL));
548  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
549  DAG.getIntPtrConstant(0, DL));
550  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
551  DAG.getIntPtrConstant(1, DL));
552 
553  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
554  DAG.getIntPtrConstant(0, DL));
555  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
556  DAG.getIntPtrConstant(1, DL));
557 
558  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
559  DAG.getIntPtrConstant(0, DL));
560  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
561  DAG.getIntPtrConstant(1, DL));
562  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
563  DAG.getIntPtrConstant(0, DL));
564  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
565  DAG.getIntPtrConstant(1, DL));
566 
567  if (UseTest) {
568  // When using tst we only care about the highest part.
569  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
570  DAG.getIntPtrConstant(1, DL));
571  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
572  } else {
573  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
574  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
575  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
576  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
577  }
578  } else if (VT == MVT::i8 || VT == MVT::i16) {
579  if (UseTest) {
580  // When using tst we only care about the highest part.
581  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
582  (VT == MVT::i8)
583  ? LHS
585  LHS, DAG.getIntPtrConstant(1, DL)));
586  } else {
587  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
588  }
589  } else {
590  llvm_unreachable("Invalid comparison size");
591  }
592 
593  // When using a test instruction AVRcc is already set.
594  if (!UseTest) {
595  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
596  }
597 
598  return Cmp;
599 }
600 
601 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
602  SDValue Chain = Op.getOperand(0);
603  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
604  SDValue LHS = Op.getOperand(2);
605  SDValue RHS = Op.getOperand(3);
606  SDValue Dest = Op.getOperand(4);
607  SDLoc dl(Op);
608 
609  SDValue TargetCC;
610  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
611 
612  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
613  Cmp);
614 }
615 
616 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
617  SDValue LHS = Op.getOperand(0);
618  SDValue RHS = Op.getOperand(1);
619  SDValue TrueV = Op.getOperand(2);
620  SDValue FalseV = Op.getOperand(3);
621  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
622  SDLoc dl(Op);
623 
624  SDValue TargetCC;
625  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
626 
627  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
628  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
629 
630  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
631 }
632 
633 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
634  SDValue LHS = Op.getOperand(0);
635  SDValue RHS = Op.getOperand(1);
636  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
637  SDLoc DL(Op);
638 
639  SDValue TargetCC;
640  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
641 
642  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
643  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
644  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
645  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
646 
647  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
648 }
649 
650 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
651  const MachineFunction &MF = DAG.getMachineFunction();
653  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
654  auto DL = DAG.getDataLayout();
655  SDLoc dl(Op);
656 
657  // Vastart just stores the address of the VarArgsFrameIndex slot into the
658  // memory location argument.
660 
661  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
662  MachinePointerInfo(SV), 0);
663 }
664 
666  switch (Op.getOpcode()) {
667  default:
668  llvm_unreachable("Don't know how to custom lower this!");
669  case ISD::SHL:
670  case ISD::SRA:
671  case ISD::SRL:
672  case ISD::ROTL:
673  case ISD::ROTR:
674  return LowerShifts(Op, DAG);
675  case ISD::GlobalAddress:
676  return LowerGlobalAddress(Op, DAG);
677  case ISD::BlockAddress:
678  return LowerBlockAddress(Op, DAG);
679  case ISD::BR_CC:
680  return LowerBR_CC(Op, DAG);
681  case ISD::SELECT_CC:
682  return LowerSELECT_CC(Op, DAG);
683  case ISD::SETCC:
684  return LowerSETCC(Op, DAG);
685  case ISD::VASTART:
686  return LowerVASTART(Op, DAG);
687  case ISD::SDIVREM:
688  case ISD::UDIVREM:
689  return LowerDivRem(Op, DAG);
690  }
691 
692  return SDValue();
693 }
694 
695 /// Replace a node with an illegal result type
696 /// with a new node built out of custom code.
699  SelectionDAG &DAG) const {
700  SDLoc DL(N);
701 
702  switch (N->getOpcode()) {
703  case ISD::ADD: {
704  // Convert add (x, imm) into sub (x, -imm).
705  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
706  SDValue Sub = DAG.getNode(
707  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
708  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
709  Results.push_back(Sub);
710  }
711  break;
712  }
713  default: {
714  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
715 
716  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
717  Results.push_back(Res.getValue(I));
718 
719  break;
720  }
721  }
722 }
723 
724 /// Return true if the addressing mode represented
725 /// by AM is legal for this target, for a load/store of the specified type.
727  const AddrMode &AM, Type *Ty,
728  unsigned AS, Instruction *I) const {
729  int64_t Offs = AM.BaseOffs;
730 
731  // Allow absolute addresses.
732  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
733  return true;
734  }
735 
736  // Flash memory instructions only allow zero offsets.
737  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
738  return false;
739  }
740 
741  // Allow reg+<6bit> offset.
742  if (Offs < 0)
743  Offs = -Offs;
744  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
745  return true;
746  }
747 
748  return false;
749 }
750 
751 /// Returns true by value, base pointer and
752 /// offset pointer and addressing mode by reference if the node's address
753 /// can be legally represented as pre-indexed load / store address.
755  SDValue &Offset,
757  SelectionDAG &DAG) const {
758  EVT VT;
759  const SDNode *Op;
760  SDLoc DL(N);
761 
762  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
763  VT = LD->getMemoryVT();
764  Op = LD->getBasePtr().getNode();
765  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
766  return false;
768  return false;
769  }
770  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
771  VT = ST->getMemoryVT();
772  Op = ST->getBasePtr().getNode();
774  return false;
775  }
776  } else {
777  return false;
778  }
779 
780  if (VT != MVT::i8 && VT != MVT::i16) {
781  return false;
782  }
783 
784  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
785  return false;
786  }
787 
788  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
789  int RHSC = RHS->getSExtValue();
790  if (Op->getOpcode() == ISD::SUB)
791  RHSC = -RHSC;
792 
793  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
794  return false;
795  }
796 
797  Base = Op->getOperand(0);
798  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
799  AM = ISD::PRE_DEC;
800 
801  return true;
802  }
803 
804  return false;
805 }
806 
807 /// Returns true by value, base pointer and
808 /// offset pointer and addressing mode by reference if this node can be
809 /// combined with a load / store to form a post-indexed load / store.
811  SDValue &Base,
812  SDValue &Offset,
814  SelectionDAG &DAG) const {
815  EVT VT;
816  SDLoc DL(N);
817 
818  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
819  VT = LD->getMemoryVT();
820  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
821  return false;
822  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
823  VT = ST->getMemoryVT();
825  return false;
826  }
827  } else {
828  return false;
829  }
830 
831  if (VT != MVT::i8 && VT != MVT::i16) {
832  return false;
833  }
834 
835  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
836  return false;
837  }
838 
839  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
840  int RHSC = RHS->getSExtValue();
841  if (Op->getOpcode() == ISD::SUB)
842  RHSC = -RHSC;
843  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
844  return false;
845  }
846 
847  Base = Op->getOperand(0);
848  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
849  AM = ISD::POST_INC;
850 
851  return true;
852  }
853 
854  return false;
855 }
856 
858  const GlobalAddressSDNode *GA) const {
859  return true;
860 }
861 
862 //===----------------------------------------------------------------------===//
863 // Formal Arguments Calling Convention Implementation
864 //===----------------------------------------------------------------------===//
865 
866 #include "AVRGenCallingConv.inc"
867 
868 /// For each argument in a function store the number of pieces it is composed
869 /// of.
870 static void parseFunctionArgs(const Function *F, const DataLayout *TD,
872  for (Argument const &Arg : F->args()) {
873  unsigned Bytes = (TD->getTypeSizeInBits(Arg.getType()) + 7) / 8;
874  Out.push_back((Bytes + 1) / 2);
875  }
876 }
877 
878 /// For external symbols there is no function prototype information so we
879 /// have to rely directly on argument sizes.
882  for (unsigned i = 0, e = In.size(); i != e;) {
883  unsigned Size = 0;
884  unsigned Offset = 0;
885  while ((i != e) && (In[i].PartOffset == Offset)) {
886  Offset += In[i].VT.getStoreSize();
887  ++i;
888  ++Size;
889  }
890  Out.push_back(Size);
891  }
892 }
893 
895  SDValue Callee = CLI.Callee;
896 
897  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
898  return G->getSymbol();
899  }
900 
901  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
902  return G->getGlobal()->getName();
903  }
904 
905  llvm_unreachable("don't know how to get the name for this callee");
906 }
907 
908 /// Analyze incoming and outgoing function arguments. We need custom C++ code
909 /// to handle special constraints in the ABI like reversing the order of the
910 /// pieces of splitted arguments. In addition, all pieces of a certain argument
911 /// have to be passed either using registers or the stack but never mixing both.
913  const Function *F, const DataLayout *TD,
916  CallingConv::ID CallConv,
918  CCState &CCInfo, bool IsCall, bool IsVarArg) {
919  static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
920  AVR::R18, AVR::R16, AVR::R14,
921  AVR::R12, AVR::R10, AVR::R8};
922  static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
923  AVR::R19R18, AVR::R17R16, AVR::R15R14,
924  AVR::R13R12, AVR::R11R10, AVR::R9R8};
925  if (IsVarArg) {
926  // Variadic functions do not need all the analisys below.
927  if (IsCall) {
928  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
929  } else {
930  CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
931  }
932  return;
933  }
934 
935  // Fill in the Args array which will contain original argument sizes.
937  if (IsCall) {
938  parseExternFuncCallArgs(*Outs, Args);
939  } else {
940  assert(F != nullptr && "function should not be null");
941  parseFunctionArgs(F, TD, Args);
942  }
943 
944  unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
945  // Variadic functions always use the stack.
946  bool UsesStack = false;
947  for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
948  unsigned Size = Args[i];
949 
950  // If we have a zero-sized argument, don't attempt to lower it.
951  // AVR-GCC does not support zero-sized arguments and so we need not
952  // worry about ABI compatibility.
953  if (Size == 0) continue;
954 
955  MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
956 
957  // If we have plenty of regs to pass the whole argument do it.
958  if (!UsesStack && (Size <= RegsLeft)) {
959  const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
960 
961  for (unsigned j = 0; j != Size; ++j) {
962  unsigned Reg = CCInfo.AllocateReg(
963  ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
964  CCInfo.addLoc(
965  CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
966  --RegsLeft;
967  }
968 
969  // Reverse the order of the pieces to agree with the "big endian" format
970  // required in the calling convention ABI.
971  std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
972  } else {
973  // Pass the rest of arguments using the stack.
974  UsesStack = true;
975  for (unsigned j = 0; j != Size; ++j) {
976  unsigned Offset = CCInfo.AllocateStack(
977  TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
979  EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
980  CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
982  }
983  }
984  pos += Size;
985  }
986 }
987 
989  const Function *F, const DataLayout *TD,
992  CallingConv::ID CallConv,
994  CCState &CCInfo, bool IsCall, bool IsVarArg) {
995  StringRef FuncName = getFunctionName(CLI);
996 
997  if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
998  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
999  } else {
1000  analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1001  CallConv, ArgLocs, CCInfo,
1002  IsCall, IsVarArg);
1003  }
1004 }
1005 
1007  const Function *F, const DataLayout *TD,
1008  const SmallVectorImpl<ISD::OutputArg> *Outs,
1010  CallingConv::ID CallConv,
1012  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1013  switch (CallConv) {
1014  case CallingConv::AVR_BUILTIN: {
1015  analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
1016  CallConv, ArgLocs, CCInfo,
1017  IsCall, IsVarArg);
1018  return;
1019  }
1020  default: {
1021  analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1022  CallConv, ArgLocs, CCInfo,
1023  IsCall, IsVarArg);
1024  return;
1025  }
1026  }
1027 }
1028 
1029 SDValue AVRTargetLowering::LowerFormalArguments(
1030  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1031  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1032  SmallVectorImpl<SDValue> &InVals) const {
1033  MachineFunction &MF = DAG.getMachineFunction();
1034  MachineFrameInfo &MFI = MF.getFrameInfo();
1035  auto DL = DAG.getDataLayout();
1036 
1037  // Assign locations to all of the incoming arguments.
1039  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1040  *DAG.getContext());
1041 
1042  analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1043  false, isVarArg);
1044 
1045  SDValue ArgValue;
1046  for (CCValAssign &VA : ArgLocs) {
1047 
1048  // Arguments stored on registers.
1049  if (VA.isRegLoc()) {
1050  EVT RegVT = VA.getLocVT();
1051  const TargetRegisterClass *RC;
1052  if (RegVT == MVT::i8) {
1053  RC = &AVR::GPR8RegClass;
1054  } else if (RegVT == MVT::i16) {
1055  RC = &AVR::DREGSRegClass;
1056  } else {
1057  llvm_unreachable("Unknown argument type!");
1058  }
1059 
1060  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1061  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1062 
1063  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1064  // following code will handle zexts or sexts generated by other
1065  // front ends. Otherwise:
1066  // If this is an 8 bit value, it is really passed promoted
1067  // to 16 bits. Insert an assert[sz]ext to capture this, then
1068  // truncate to the right size.
1069  switch (VA.getLocInfo()) {
1070  default:
1071  llvm_unreachable("Unknown loc info!");
1072  case CCValAssign::Full:
1073  break;
1074  case CCValAssign::BCvt:
1075  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1076  break;
1077  case CCValAssign::SExt:
1078  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1079  DAG.getValueType(VA.getValVT()));
1080  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1081  break;
1082  case CCValAssign::ZExt:
1083  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1084  DAG.getValueType(VA.getValVT()));
1085  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1086  break;
1087  }
1088 
1089  InVals.push_back(ArgValue);
1090  } else {
1091  // Sanity check.
1092  assert(VA.isMemLoc());
1093 
1094  EVT LocVT = VA.getLocVT();
1095 
1096  // Create the frame index object for this incoming parameter.
1097  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1098  VA.getLocMemOffset(), true);
1099 
1100  // Create the SelectionDAG nodes corresponding to a load
1101  // from this parameter.
1102  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1103  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1105  0));
1106  }
1107  }
1108 
1109  // If the function takes variable number of arguments, make a frame index for
1110  // the start of the first vararg value... for expansion of llvm.va_start.
1111  if (isVarArg) {
1112  unsigned StackSize = CCInfo.getNextStackOffset();
1114 
1115  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1116  }
1117 
1118  return Chain;
1119 }
1120 
1121 //===----------------------------------------------------------------------===//
1122 // Call Calling Convention Implementation
1123 //===----------------------------------------------------------------------===//
1124 
1125 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1126  SmallVectorImpl<SDValue> &InVals) const {
1127  SelectionDAG &DAG = CLI.DAG;
1128  SDLoc &DL = CLI.DL;
1130  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1132  SDValue Chain = CLI.Chain;
1133  SDValue Callee = CLI.Callee;
1134  bool &isTailCall = CLI.IsTailCall;
1135  CallingConv::ID CallConv = CLI.CallConv;
1136  bool isVarArg = CLI.IsVarArg;
1137 
1138  MachineFunction &MF = DAG.getMachineFunction();
1139 
1140  // AVR does not yet support tail call optimization.
1141  isTailCall = false;
1142 
1143  // Analyze operands of the call, assigning locations to each operand.
1145  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1146  *DAG.getContext());
1147 
1148  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1149  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1150  // node so that legalize doesn't hack it.
1151  const Function *F = nullptr;
1152  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1153  const GlobalValue *GV = G->getGlobal();
1154 
1155  F = cast<Function>(GV);
1156  Callee =
1158  } else if (const ExternalSymbolSDNode *ES =
1159  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1160  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1161  getPointerTy(DAG.getDataLayout()));
1162  }
1163 
1164  analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1165  true, isVarArg);
1166 
1167  // Get a count of how many bytes are to be pushed on the stack.
1168  unsigned NumBytes = CCInfo.getNextStackOffset();
1169 
1170  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1171 
1173 
1174  // First, walk the register assignments, inserting copies.
1175  unsigned AI, AE;
1176  bool HasStackArgs = false;
1177  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1178  CCValAssign &VA = ArgLocs[AI];
1179  EVT RegVT = VA.getLocVT();
1180  SDValue Arg = OutVals[AI];
1181 
1182  // Promote the value if needed. With Clang this should not happen.
1183  switch (VA.getLocInfo()) {
1184  default:
1185  llvm_unreachable("Unknown loc info!");
1186  case CCValAssign::Full:
1187  break;
1188  case CCValAssign::SExt:
1189  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1190  break;
1191  case CCValAssign::ZExt:
1192  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1193  break;
1194  case CCValAssign::AExt:
1195  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1196  break;
1197  case CCValAssign::BCvt:
1198  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1199  break;
1200  }
1201 
1202  // Stop when we encounter a stack argument, we need to process them
1203  // in reverse order in the loop below.
1204  if (VA.isMemLoc()) {
1205  HasStackArgs = true;
1206  break;
1207  }
1208 
1209  // Arguments that can be passed on registers must be kept in the RegsToPass
1210  // vector.
1211  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1212  }
1213 
1214  // Second, stack arguments have to walked in reverse order by inserting
1215  // chained stores, this ensures their order is not changed by the scheduler
1216  // and that the push instruction sequence generated is correct, otherwise they
1217  // can be freely intermixed.
1218  if (HasStackArgs) {
1219  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1220  unsigned Loc = AI - 1;
1221  CCValAssign &VA = ArgLocs[Loc];
1222  SDValue Arg = OutVals[Loc];
1223 
1224  assert(VA.isMemLoc());
1225 
1226  // SP points to one stack slot further so add one to adjust it.
1227  SDValue PtrOff = DAG.getNode(
1228  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1229  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1230  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1231 
1232  Chain =
1233  DAG.getStore(Chain, DL, Arg, PtrOff,
1235  0);
1236  }
1237  }
1238 
1239  // Build a sequence of copy-to-reg nodes chained together with token chain and
1240  // flag operands which copy the outgoing args into registers. The InFlag in
1241  // necessary since all emited instructions must be stuck together.
1242  SDValue InFlag;
1243  for (auto Reg : RegsToPass) {
1244  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1245  InFlag = Chain.getValue(1);
1246  }
1247 
1248  // Returns a chain & a flag for retval copy to use.
1249  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1251  Ops.push_back(Chain);
1252  Ops.push_back(Callee);
1253 
1254  // Add argument registers to the end of the list so that they are known live
1255  // into the call.
1256  for (auto Reg : RegsToPass) {
1257  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1258  }
1259 
1260  // Add a register mask operand representing the call-preserved registers.
1261  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1263  const uint32_t *Mask =
1264  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1265  assert(Mask && "Missing call preserved mask for calling convention");
1266  Ops.push_back(DAG.getRegisterMask(Mask));
1267 
1268  if (InFlag.getNode()) {
1269  Ops.push_back(InFlag);
1270  }
1271 
1272  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1273  InFlag = Chain.getValue(1);
1274 
1275  // Create the CALLSEQ_END node.
1276  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1277  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1278 
1279  if (!Ins.empty()) {
1280  InFlag = Chain.getValue(1);
1281  }
1282 
1283  // Handle result values, copying them out of physregs into vregs that we
1284  // return.
1285  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1286  InVals);
1287 }
1288 
1289 /// Lower the result values of a call into the
1290 /// appropriate copies out of appropriate physical registers.
1291 ///
1292 SDValue AVRTargetLowering::LowerCallResult(
1293  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1294  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1295  SmallVectorImpl<SDValue> &InVals) const {
1296 
1297  // Assign locations to each value returned by this call.
1299  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1300  *DAG.getContext());
1301 
1302  // Handle runtime calling convs.
1303  auto CCFunction = CCAssignFnForReturn(CallConv);
1304  CCInfo.AnalyzeCallResult(Ins, CCFunction);
1305 
1306  if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1307  // Reverse splitted return values to get the "big endian" format required
1308  // to agree with the calling convention ABI.
1309  std::reverse(RVLocs.begin(), RVLocs.end());
1310  }
1311 
1312  // Copy all of the result registers out of their specified physreg.
1313  for (CCValAssign const &RVLoc : RVLocs) {
1314  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1315  InFlag)
1316  .getValue(1);
1317  InFlag = Chain.getValue(2);
1318  InVals.push_back(Chain.getValue(0));
1319  }
1320 
1321  return Chain;
1322 }
1323 
1324 //===----------------------------------------------------------------------===//
1325 // Return Value Calling Convention Implementation
1326 //===----------------------------------------------------------------------===//
1327 
1328 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1329  switch (CC) {
1331  return RetCC_AVR_BUILTIN;
1332  default:
1333  return RetCC_AVR;
1334  }
1335 }
1336 
1337 bool
1338 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1339  MachineFunction &MF, bool isVarArg,
1340  const SmallVectorImpl<ISD::OutputArg> &Outs,
1341  LLVMContext &Context) const
1342 {
1344  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1345 
1346  auto CCFunction = CCAssignFnForReturn(CallConv);
1347  return CCInfo.CheckReturn(Outs, CCFunction);
1348 }
1349 
1350 SDValue
1351 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1352  bool isVarArg,
1353  const SmallVectorImpl<ISD::OutputArg> &Outs,
1354  const SmallVectorImpl<SDValue> &OutVals,
1355  const SDLoc &dl, SelectionDAG &DAG) const {
1356  // CCValAssign - represent the assignment of the return value to locations.
1358 
1359  // CCState - Info about the registers and stack slot.
1360  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1361  *DAG.getContext());
1362 
1363  // Analyze return values.
1364  auto CCFunction = CCAssignFnForReturn(CallConv);
1365  CCInfo.AnalyzeReturn(Outs, CCFunction);
1366 
1367  // If this is the first return lowered for this function, add the regs to
1368  // the liveout set for the function.
1369  MachineFunction &MF = DAG.getMachineFunction();
1370  unsigned e = RVLocs.size();
1371 
1372  // Reverse splitted return values to get the "big endian" format required
1373  // to agree with the calling convention ABI.
1374  if (e > 1) {
1375  std::reverse(RVLocs.begin(), RVLocs.end());
1376  }
1377 
1378  SDValue Flag;
1379  SmallVector<SDValue, 4> RetOps(1, Chain);
1380  // Copy the result values into the output registers.
1381  for (unsigned i = 0; i != e; ++i) {
1382  CCValAssign &VA = RVLocs[i];
1383  assert(VA.isRegLoc() && "Can only return in registers!");
1384 
1385  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1386 
1387  // Guarantee that all emitted copies are stuck together with flags.
1388  Flag = Chain.getValue(1);
1389  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1390  }
1391 
1392  // Don't emit the ret/reti instruction when the naked attribute is present in
1393  // the function being compiled.
1395  AttributeList::FunctionIndex, Attribute::Naked)) {
1396  return Chain;
1397  }
1398 
1399  unsigned RetOpc =
1400  (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1402  : AVRISD::RET_FLAG;
1403 
1404  RetOps[0] = Chain; // Update chain.
1405 
1406  if (Flag.getNode()) {
1407  RetOps.push_back(Flag);
1408  }
1409 
1410  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1411 }
1412 
1413 //===----------------------------------------------------------------------===//
1414 // Custom Inserters
1415 //===----------------------------------------------------------------------===//
1416 
1417 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1418  MachineBasicBlock *BB) const {
1419  unsigned Opc;
1420  const TargetRegisterClass *RC;
1421  MachineFunction *F = BB->getParent();
1422  MachineRegisterInfo &RI = F->getRegInfo();
1423  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1425  DebugLoc dl = MI.getDebugLoc();
1426 
1427  switch (MI.getOpcode()) {
1428  default:
1429  llvm_unreachable("Invalid shift opcode!");
1430  case AVR::Lsl8:
1431  Opc = AVR::LSLRd;
1432  RC = &AVR::GPR8RegClass;
1433  break;
1434  case AVR::Lsl16:
1435  Opc = AVR::LSLWRd;
1436  RC = &AVR::DREGSRegClass;
1437  break;
1438  case AVR::Asr8:
1439  Opc = AVR::ASRRd;
1440  RC = &AVR::GPR8RegClass;
1441  break;
1442  case AVR::Asr16:
1443  Opc = AVR::ASRWRd;
1444  RC = &AVR::DREGSRegClass;
1445  break;
1446  case AVR::Lsr8:
1447  Opc = AVR::LSRRd;
1448  RC = &AVR::GPR8RegClass;
1449  break;
1450  case AVR::Lsr16:
1451  Opc = AVR::LSRWRd;
1452  RC = &AVR::DREGSRegClass;
1453  break;
1454  case AVR::Rol8:
1455  Opc = AVR::ROLRd;
1456  RC = &AVR::GPR8RegClass;
1457  break;
1458  case AVR::Rol16:
1459  Opc = AVR::ROLWRd;
1460  RC = &AVR::DREGSRegClass;
1461  break;
1462  case AVR::Ror8:
1463  Opc = AVR::RORRd;
1464  RC = &AVR::GPR8RegClass;
1465  break;
1466  case AVR::Ror16:
1467  Opc = AVR::RORWRd;
1468  RC = &AVR::DREGSRegClass;
1469  break;
1470  }
1471 
1472  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1473 
1475  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1476  if (I != F->end()) ++I;
1477 
1478  // Create loop block.
1479  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1480  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1481 
1482  F->insert(I, LoopBB);
1483  F->insert(I, RemBB);
1484 
1485  // Update machine-CFG edges by transferring all successors of the current
1486  // block to the block containing instructions after shift.
1487  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1488  BB->end());
1490 
1491  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1492  BB->addSuccessor(LoopBB);
1493  BB->addSuccessor(RemBB);
1494  LoopBB->addSuccessor(RemBB);
1495  LoopBB->addSuccessor(LoopBB);
1496 
1497  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1498  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1499  unsigned ShiftReg = RI.createVirtualRegister(RC);
1500  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1501  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1502  unsigned SrcReg = MI.getOperand(1).getReg();
1503  unsigned DstReg = MI.getOperand(0).getReg();
1504 
1505  // BB:
1506  // cpi N, 0
1507  // breq RemBB
1508  BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1509  BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1510 
1511  // LoopBB:
1512  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1513  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1514  // ShiftReg2 = shift ShiftReg
1515  // ShiftAmt2 = ShiftAmt - 1;
1516  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1517  .addReg(SrcReg)
1518  .addMBB(BB)
1519  .addReg(ShiftReg2)
1520  .addMBB(LoopBB);
1521  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1522  .addReg(ShiftAmtSrcReg)
1523  .addMBB(BB)
1524  .addReg(ShiftAmtReg2)
1525  .addMBB(LoopBB);
1526  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1527  BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1528  .addReg(ShiftAmtReg)
1529  .addImm(1);
1530  BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1531 
1532  // RemBB:
1533  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1534  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1535  .addReg(SrcReg)
1536  .addMBB(BB)
1537  .addReg(ShiftReg2)
1538  .addMBB(LoopBB);
1539 
1540  MI.eraseFromParent(); // The pseudo instruction is gone now.
1541  return RemBB;
1542 }
1543 
1545  if (I->getOpcode() == AVR::COPY) {
1546  unsigned SrcReg = I->getOperand(1).getReg();
1547  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1548  }
1549 
1550  return false;
1551 }
1552 
1553 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1554 // after the result has been evacuated. This is probably not the best way to do
1555 // it, but it works for now.
1556 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1557  MachineBasicBlock *BB) const {
1558  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1561  ++I; // in any case insert *after* the mul instruction
1562  if (isCopyMulResult(I))
1563  ++I;
1564  if (isCopyMulResult(I))
1565  ++I;
1566  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1567  .addReg(AVR::R1)
1568  .addReg(AVR::R1);
1569  return BB;
1570 }
1571 
1574  MachineBasicBlock *MBB) const {
1575  int Opc = MI.getOpcode();
1576 
1577  // Pseudo shift instructions with a non constant shift amount are expanded
1578  // into a loop.
1579  switch (Opc) {
1580  case AVR::Lsl8:
1581  case AVR::Lsl16:
1582  case AVR::Lsr8:
1583  case AVR::Lsr16:
1584  case AVR::Rol8:
1585  case AVR::Rol16:
1586  case AVR::Ror8:
1587  case AVR::Ror16:
1588  case AVR::Asr8:
1589  case AVR::Asr16:
1590  return insertShift(MI, MBB);
1591  case AVR::MULRdRr:
1592  case AVR::MULSRdRr:
1593  return insertMul(MI, MBB);
1594  }
1595 
1596  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1597  "Unexpected instr type to insert");
1598 
1599  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1600  ->getParent()
1601  ->getSubtarget()
1602  .getInstrInfo();
1603  DebugLoc dl = MI.getDebugLoc();
1604 
1605  // To "insert" a SELECT instruction, we insert the diamond
1606  // control-flow pattern. The incoming instruction knows the
1607  // destination vreg to set, the condition code register to branch
1608  // on, the true/false values to select between, and a branch opcode
1609  // to use.
1610 
1611  MachineFunction *MF = MBB->getParent();
1612  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1613  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1614  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1615 
1617  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1618  if (I != MF->end()) ++I;
1619  MF->insert(I, trueMBB);
1620  MF->insert(I, falseMBB);
1621 
1622  // Transfer remaining instructions and all successors of the current
1623  // block to the block which will contain the Phi node for the
1624  // select.
1625  trueMBB->splice(trueMBB->begin(), MBB,
1626  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1627  trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1628 
1630  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1631  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1632  MBB->addSuccessor(falseMBB);
1633  MBB->addSuccessor(trueMBB);
1634 
1635  // Unconditionally flow back to the true block
1636  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1637  falseMBB->addSuccessor(trueMBB);
1638 
1639  // Set up the Phi node to determine where we came from
1640  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1641  .addReg(MI.getOperand(1).getReg())
1642  .addMBB(MBB)
1643  .addReg(MI.getOperand(2).getReg())
1644  .addMBB(falseMBB) ;
1645 
1646  MI.eraseFromParent(); // The pseudo instruction is gone now.
1647  return trueMBB;
1648 }
1649 
1650 //===----------------------------------------------------------------------===//
1651 // Inline Asm Support
1652 //===----------------------------------------------------------------------===//
1653 
1656  if (Constraint.size() == 1) {
1657  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1658  switch (Constraint[0]) {
1659  case 'a': // Simple upper registers
1660  case 'b': // Base pointer registers pairs
1661  case 'd': // Upper register
1662  case 'l': // Lower registers
1663  case 'e': // Pointer register pairs
1664  case 'q': // Stack pointer register
1665  case 'r': // Any register
1666  case 'w': // Special upper register pairs
1667  return C_RegisterClass;
1668  case 't': // Temporary register
1669  case 'x': case 'X': // Pointer register pair X
1670  case 'y': case 'Y': // Pointer register pair Y
1671  case 'z': case 'Z': // Pointer register pair Z
1672  return C_Register;
1673  case 'Q': // A memory address based on Y or Z pointer with displacement.
1674  return C_Memory;
1675  case 'G': // Floating point constant
1676  case 'I': // 6-bit positive integer constant
1677  case 'J': // 6-bit negative integer constant
1678  case 'K': // Integer constant (Range: 2)
1679  case 'L': // Integer constant (Range: 0)
1680  case 'M': // 8-bit integer constant
1681  case 'N': // Integer constant (Range: -1)
1682  case 'O': // Integer constant (Range: 8, 16, 24)
1683  case 'P': // Integer constant (Range: 1)
1684  case 'R': // Integer constant (Range: -6 to 5)x
1685  return C_Other;
1686  default:
1687  break;
1688  }
1689  }
1690 
1691  return TargetLowering::getConstraintType(Constraint);
1692 }
1693 
1694 unsigned
1696  // Not sure if this is actually the right thing to do, but we got to do
1697  // *something* [agnat]
1698  switch (ConstraintCode[0]) {
1699  case 'Q':
1700  return InlineAsm::Constraint_Q;
1701  }
1702  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1703 }
1704 
1707  AsmOperandInfo &info, const char *constraint) const {
1708  ConstraintWeight weight = CW_Invalid;
1709  Value *CallOperandVal = info.CallOperandVal;
1710 
1711  // If we don't have a value, we can't do a match,
1712  // but allow it at the lowest weight.
1713  // (this behaviour has been copied from the ARM backend)
1714  if (!CallOperandVal) {
1715  return CW_Default;
1716  }
1717 
1718  // Look at the constraint type.
1719  switch (*constraint) {
1720  default:
1721  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1722  break;
1723  case 'd':
1724  case 'r':
1725  case 'l':
1726  weight = CW_Register;
1727  break;
1728  case 'a':
1729  case 'b':
1730  case 'e':
1731  case 'q':
1732  case 't':
1733  case 'w':
1734  case 'x': case 'X':
1735  case 'y': case 'Y':
1736  case 'z': case 'Z':
1737  weight = CW_SpecificReg;
1738  break;
1739  case 'G':
1740  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1741  if (C->isZero()) {
1742  weight = CW_Constant;
1743  }
1744  }
1745  break;
1746  case 'I':
1747  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1748  if (isUInt<6>(C->getZExtValue())) {
1749  weight = CW_Constant;
1750  }
1751  }
1752  break;
1753  case 'J':
1754  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1755  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1756  weight = CW_Constant;
1757  }
1758  }
1759  break;
1760  case 'K':
1761  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1762  if (C->getZExtValue() == 2) {
1763  weight = CW_Constant;
1764  }
1765  }
1766  break;
1767  case 'L':
1768  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1769  if (C->getZExtValue() == 0) {
1770  weight = CW_Constant;
1771  }
1772  }
1773  break;
1774  case 'M':
1775  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1776  if (isUInt<8>(C->getZExtValue())) {
1777  weight = CW_Constant;
1778  }
1779  }
1780  break;
1781  case 'N':
1782  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1783  if (C->getSExtValue() == -1) {
1784  weight = CW_Constant;
1785  }
1786  }
1787  break;
1788  case 'O':
1789  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1790  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1791  (C->getZExtValue() == 24)) {
1792  weight = CW_Constant;
1793  }
1794  }
1795  break;
1796  case 'P':
1797  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1798  if (C->getZExtValue() == 1) {
1799  weight = CW_Constant;
1800  }
1801  }
1802  break;
1803  case 'R':
1804  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1805  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1806  weight = CW_Constant;
1807  }
1808  }
1809  break;
1810  case 'Q':
1811  weight = CW_Memory;
1812  break;
1813  }
1814 
1815  return weight;
1816 }
1817 
1818 std::pair<unsigned, const TargetRegisterClass *>
1820  StringRef Constraint,
1821  MVT VT) const {
1822  auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine())
1823  .getSubtargetImpl();
1824 
1825  // We only support i8 and i16.
1826  //
1827  //:FIXME: remove this assert for now since it gets sometimes executed
1828  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1829 
1830  if (Constraint.size() == 1) {
1831  switch (Constraint[0]) {
1832  case 'a': // Simple upper registers r16..r23.
1833  return std::make_pair(0U, &AVR::LD8loRegClass);
1834  case 'b': // Base pointer registers: y, z.
1835  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1836  case 'd': // Upper registers r16..r31.
1837  return std::make_pair(0U, &AVR::LD8RegClass);
1838  case 'l': // Lower registers r0..r15.
1839  return std::make_pair(0U, &AVR::GPR8loRegClass);
1840  case 'e': // Pointer register pairs: x, y, z.
1841  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1842  case 'q': // Stack pointer register: SPH:SPL.
1843  return std::make_pair(0U, &AVR::GPRSPRegClass);
1844  case 'r': // Any register: r0..r31.
1845  if (VT == MVT::i8)
1846  return std::make_pair(0U, &AVR::GPR8RegClass);
1847 
1848  assert(VT == MVT::i16 && "inline asm constraint too large");
1849  return std::make_pair(0U, &AVR::DREGSRegClass);
1850  case 't': // Temporary register: r0.
1851  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1852  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1853  return std::make_pair(0U, &AVR::IWREGSRegClass);
1854  case 'x': // Pointer register pair X: r27:r26.
1855  case 'X':
1856  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1857  case 'y': // Pointer register pair Y: r29:r28.
1858  case 'Y':
1859  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1860  case 'z': // Pointer register pair Z: r31:r30.
1861  case 'Z':
1862  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1863  default:
1864  break;
1865  }
1866  }
1867 
1868  return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(),
1869  Constraint, VT);
1870 }
1871 
1873  std::string &Constraint,
1874  std::vector<SDValue> &Ops,
1875  SelectionDAG &DAG) const {
1876  SDValue Result(0, 0);
1877  SDLoc DL(Op);
1878  EVT Ty = Op.getValueType();
1879 
1880  // Currently only support length 1 constraints.
1881  if (Constraint.length() != 1) {
1882  return;
1883  }
1884 
1885  char ConstraintLetter = Constraint[0];
1886  switch (ConstraintLetter) {
1887  default:
1888  break;
1889  // Deal with integers first:
1890  case 'I':
1891  case 'J':
1892  case 'K':
1893  case 'L':
1894  case 'M':
1895  case 'N':
1896  case 'O':
1897  case 'P':
1898  case 'R': {
1900  if (!C) {
1901  return;
1902  }
1903 
1904  int64_t CVal64 = C->getSExtValue();
1905  uint64_t CUVal64 = C->getZExtValue();
1906  switch (ConstraintLetter) {
1907  case 'I': // 0..63
1908  if (!isUInt<6>(CUVal64))
1909  return;
1910  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1911  break;
1912  case 'J': // -63..0
1913  if (CVal64 < -63 || CVal64 > 0)
1914  return;
1915  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1916  break;
1917  case 'K': // 2
1918  if (CUVal64 != 2)
1919  return;
1920  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1921  break;
1922  case 'L': // 0
1923  if (CUVal64 != 0)
1924  return;
1925  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1926  break;
1927  case 'M': // 0..255
1928  if (!isUInt<8>(CUVal64))
1929  return;
1930  // i8 type may be printed as a negative number,
1931  // e.g. 254 would be printed as -2,
1932  // so we force it to i16 at least.
1933  if (Ty.getSimpleVT() == MVT::i8) {
1934  Ty = MVT::i16;
1935  }
1936  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1937  break;
1938  case 'N': // -1
1939  if (CVal64 != -1)
1940  return;
1941  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1942  break;
1943  case 'O': // 8, 16, 24
1944  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1945  return;
1946  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1947  break;
1948  case 'P': // 1
1949  if (CUVal64 != 1)
1950  return;
1951  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1952  break;
1953  case 'R': // -6..5
1954  if (CVal64 < -6 || CVal64 > 5)
1955  return;
1956  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1957  break;
1958  }
1959 
1960  break;
1961  }
1962  case 'G':
1964  if (!FC || !FC->isZero())
1965  return;
1966  // Soften float to i8 0
1967  Result = DAG.getTargetConstant(0, DL, MVT::i8);
1968  break;
1969  }
1970 
1971  if (Result.getNode()) {
1972  Ops.push_back(Result);
1973  return;
1974  }
1975 
1976  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1977 }
1978 
1979 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
1980  EVT VT,
1981  SelectionDAG &DAG) const {
1982  unsigned Reg;
1983 
1984  if (VT == MVT::i8) {
1985  Reg = StringSwitch<unsigned>(RegName)
1986  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1987  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1988  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1989  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1990  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1991  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1992  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1993  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1994  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
1995  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
1996  .Case("r30", AVR::R30).Case("r31", AVR::R31)
1997  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1998  .Default(0);
1999  } else {
2000  Reg = StringSwitch<unsigned>(RegName)
2001  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2002  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2003  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2004  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2005  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2006  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2007  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2008  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2009  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2010  .Default(0);
2011  }
2012 
2013  if (Reg)
2014  return Reg;
2015 
2016  report_fatal_error("Invalid register name global variable");
2017 }
2018 
2019 } // end of namespace llvm
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:546
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
#define R4(n)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:835
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:618
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:271
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Unsigned lower.
Definition: AVRInstrInfo.h:38
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:667
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Test for zero or minus instruction.
A debug info location.
Definition: DebugLoc.h:34
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
#define R2(n)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
SDValue getExternalSymbol(const char *Sym, EVT VT)
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
const AVRSubtarget * getSubtargetImpl() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:434
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:813
Represents an abstract call instruction, which includes a bunch of information.
A loop of single right bit rotate instructions.
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:380
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:46
CallLoweringInfo & setChain(SDValue InChain)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:778
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:293
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:449
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:390
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:336
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:663
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:233
int64_t getSExtValue() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
A generic AVR implementation.
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:387
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
Return from subroutine.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
SmallVector< ISD::OutputArg, 32 > Outs
CallLoweringInfo & setZExtResult(bool Value=true)
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:917
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:561
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
bool isZero() const
Return true if the value is positive or negative zero.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:335
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
Contains AVR-specific information for each MachineFunction.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
Unsigned same or higher.
Definition: AVRInstrInfo.h:37
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:696
iterator_range< value_op_iterator > op_values() const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
const SDValue & getOperand(unsigned Num) const
LLVMContext & getContext() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:823
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
self_iterator getIterator()
Definition: ilist_node.h:82
AVR conditional branches.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:687
static void parseFunctionArgs(const Function *F, const DataLayout *TD, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:32
lazy value info
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:764
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Calling convention used for AVR signal routines.
Definition: CallingConv.h:180
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
AVRTargetLowering(AVRTargetMachine &TM)
Compare instruction.
A loop of single logical shift right instructions.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
#define R6(n)
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:210
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
#define NODE(name)
CCValAssign - Represent assignment of one arg/retval to a location.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:721
A loop of single left bit rotate instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:682
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:612
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:383
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
Return from ISR.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:660
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:446
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:449
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:184
amdgpu Simplify well known AMD library false Value Value * Arg
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:142
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:530
Bit rotate left.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:403
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:606
Representation of each machine instruction.
Definition: MachineInstr.h:60
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:692
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:654
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
SmallVector< SDValue, 32 > OutVals
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:686
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:464
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Used for AVR interrupt routines.
Definition: CallingConv.h:177
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Logical shift right.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
Arithmetic shift right.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
CallLoweringInfo & setInRegister(bool Value=true)
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
Greater than or equal.
Definition: AVRInstrInfo.h:35
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:46
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:413
Conversion operators.
Definition: ISDOpcodes.h:443
const SDValue & getOperand(unsigned i) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
uint64_t getZExtValue() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:452
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:298
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:396
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
iterator_range< arg_iterator > args()
Definition: Function.h:667
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:603
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:872
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:591