LLVM  6.0.0svn
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVRISelLowering.h"
16 
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRTargetMachine.h"
31 
32 namespace llvm {
33 
35  : TargetLowering(tm) {
36  // Set up the register classes.
37  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
39 
40  // Compute derived properties from the register classes.
42 
47 
50 
55 
56  for (MVT VT : MVT::integer_valuetypes()) {
57  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
60  }
61  }
62 
64 
65  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
66  // revert into a sub since we don't have an add with immediate instruction.
69 
70  // our shift instructions are only able to shift 1 bit at a time, so handle
71  // this in a custom way.
81 
86 
92 
103 
105 
106  // Add support for postincrement and predecrement load/stores.
115 
117 
122 
123  // Atomic operations which must be lowered to rtlib calls
124  for (MVT VT : MVT::integer_valuetypes()) {
132  }
133 
134  // Division/remainder
143 
144  // Make division and modulus custom
145  for (MVT VT : MVT::integer_valuetypes()) {
148  }
149 
150  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
153 
154  // Expand 16 bit multiplications.
157 
158  for (MVT VT : MVT::integer_valuetypes()) {
161  }
162 
163  for (MVT VT : MVT::integer_valuetypes()) {
167  }
168 
169  for (MVT VT : MVT::integer_valuetypes()) {
171  // TODO: The generated code is pretty poor. Investigate using the
172  // same "shift and subtract with carry" trick that we do for
173  // extending 8-bit to 16-bit. This may require infrastructure
174  // improvements in how we treat 16-bit "registers" to be feasible.
175  }
176 
177  // Division rtlib functions (not supported)
178  setLibcallName(RTLIB::SDIV_I8, nullptr);
179  setLibcallName(RTLIB::SDIV_I16, nullptr);
180  setLibcallName(RTLIB::SDIV_I32, nullptr);
181  setLibcallName(RTLIB::SDIV_I64, nullptr);
182  setLibcallName(RTLIB::SDIV_I128, nullptr);
183  setLibcallName(RTLIB::UDIV_I8, nullptr);
184  setLibcallName(RTLIB::UDIV_I16, nullptr);
185  setLibcallName(RTLIB::UDIV_I32, nullptr);
186  setLibcallName(RTLIB::UDIV_I64, nullptr);
187  setLibcallName(RTLIB::UDIV_I128, nullptr);
188 
189  // Modulus rtlib functions (not supported)
190  setLibcallName(RTLIB::SREM_I8, nullptr);
191  setLibcallName(RTLIB::SREM_I16, nullptr);
192  setLibcallName(RTLIB::SREM_I32, nullptr);
193  setLibcallName(RTLIB::SREM_I64, nullptr);
194  setLibcallName(RTLIB::SREM_I128, nullptr);
195  setLibcallName(RTLIB::UREM_I8, nullptr);
196  setLibcallName(RTLIB::UREM_I16, nullptr);
197  setLibcallName(RTLIB::UREM_I32, nullptr);
198  setLibcallName(RTLIB::UREM_I64, nullptr);
199  setLibcallName(RTLIB::UREM_I128, nullptr);
200 
201  // Division and modulus rtlib functions
202  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
203  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
204  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
205  setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
206  setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
207  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
208  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
209  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
210  setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
211  setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
212 
213  // Several of the runtime library functions use a special calling conv
215  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
217  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
218 
219  // Trigonometric rtlib functions
220  setLibcallName(RTLIB::SIN_F32, "sin");
221  setLibcallName(RTLIB::COS_F32, "cos");
222 
225 }
226 
227 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
228 #define NODE(name) \
229  case AVRISD::name: \
230  return #name
231 
232  switch (Opcode) {
233  default:
234  return nullptr;
235  NODE(RET_FLAG);
236  NODE(RETI_FLAG);
237  NODE(CALL);
238  NODE(WRAPPER);
239  NODE(LSL);
240  NODE(LSR);
241  NODE(ROL);
242  NODE(ROR);
243  NODE(ASR);
244  NODE(LSLLOOP);
245  NODE(LSRLOOP);
246  NODE(ASRLOOP);
247  NODE(BRCOND);
248  NODE(CMP);
249  NODE(CMPC);
250  NODE(TST);
251  NODE(SELECT_CC);
252 #undef NODE
253  }
254 }
255 
257  EVT VT) const {
258  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
259  return MVT::i8;
260 }
261 
262 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
263  //:TODO: this function has to be completely rewritten to produce optimal
264  // code, for now it's producing very long but correct code.
265  unsigned Opc8;
266  const SDNode *N = Op.getNode();
267  EVT VT = Op.getValueType();
268  SDLoc dl(N);
269 
270  // Expand non-constant shifts to loops.
271  if (!isa<ConstantSDNode>(N->getOperand(1))) {
272  switch (Op.getOpcode()) {
273  default:
274  llvm_unreachable("Invalid shift opcode!");
275  case ISD::SHL:
276  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
277  N->getOperand(1));
278  case ISD::SRL:
279  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
280  N->getOperand(1));
281  case ISD::ROTL:
282  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
283  N->getOperand(1));
284  case ISD::ROTR:
285  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
286  N->getOperand(1));
287  case ISD::SRA:
288  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
289  N->getOperand(1));
290  }
291  }
292 
293  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
294  SDValue Victim = N->getOperand(0);
295 
296  switch (Op.getOpcode()) {
297  case ISD::SRA:
298  Opc8 = AVRISD::ASR;
299  break;
300  case ISD::ROTL:
301  Opc8 = AVRISD::ROL;
302  break;
303  case ISD::ROTR:
304  Opc8 = AVRISD::ROR;
305  break;
306  case ISD::SRL:
307  Opc8 = AVRISD::LSR;
308  break;
309  case ISD::SHL:
310  Opc8 = AVRISD::LSL;
311  break;
312  default:
313  llvm_unreachable("Invalid shift opcode");
314  }
315 
316  while (ShiftAmount--) {
317  Victim = DAG.getNode(Opc8, dl, VT, Victim);
318  }
319 
320  return Victim;
321 }
322 
323 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
324  unsigned Opcode = Op->getOpcode();
325  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
326  "Invalid opcode for Div/Rem lowering");
327  bool IsSigned = (Opcode == ISD::SDIVREM);
328  EVT VT = Op->getValueType(0);
329  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
330 
331  RTLIB::Libcall LC;
332  switch (VT.getSimpleVT().SimpleTy) {
333  default:
334  llvm_unreachable("Unexpected request for libcall!");
335  case MVT::i8:
336  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
337  break;
338  case MVT::i16:
339  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
340  break;
341  case MVT::i32:
342  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
343  break;
344  case MVT::i64:
345  LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
346  break;
347  }
348 
349  SDValue InChain = DAG.getEntryNode();
350 
353  for (SDValue const &Value : Op->op_values()) {
354  Entry.Node = Value;
355  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
356  Entry.IsSExt = IsSigned;
357  Entry.IsZExt = !IsSigned;
358  Args.push_back(Entry);
359  }
360 
362  getPointerTy(DAG.getDataLayout()));
363 
364  Type *RetTy = (Type *)StructType::get(Ty, Ty);
365 
366  SDLoc dl(Op);
368  CLI.setDebugLoc(dl)
369  .setChain(InChain)
370  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
371  .setInRegister()
372  .setSExtResult(IsSigned)
373  .setZExtResult(!IsSigned);
374 
375  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
376  return CallInfo.first;
377 }
378 
379 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
380  SelectionDAG &DAG) const {
381  auto DL = DAG.getDataLayout();
382 
383  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
384  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
385 
386  // Create the TargetGlobalAddress node, folding in the constant offset.
387  SDValue Result =
388  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
389  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
390 }
391 
392 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
393  SelectionDAG &DAG) const {
394  auto DL = DAG.getDataLayout();
395  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
396 
397  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
398 
399  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
400 }
401 
402 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
404  switch (CC) {
405  default:
406  llvm_unreachable("Unknown condition code!");
407  case ISD::SETEQ:
408  return AVRCC::COND_EQ;
409  case ISD::SETNE:
410  return AVRCC::COND_NE;
411  case ISD::SETGE:
412  return AVRCC::COND_GE;
413  case ISD::SETLT:
414  return AVRCC::COND_LT;
415  case ISD::SETUGE:
416  return AVRCC::COND_SH;
417  case ISD::SETULT:
418  return AVRCC::COND_LO;
419  }
420 }
421 
422 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
423 /// the given operands.
424 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
425  SDValue &AVRcc, SelectionDAG &DAG,
426  SDLoc DL) const {
427  SDValue Cmp;
428  EVT VT = LHS.getValueType();
429  bool UseTest = false;
430 
431  switch (CC) {
432  default:
433  break;
434  case ISD::SETLE: {
435  // Swap operands and reverse the branching condition.
436  std::swap(LHS, RHS);
437  CC = ISD::SETGE;
438  break;
439  }
440  case ISD::SETGT: {
441  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
442  switch (C->getSExtValue()) {
443  case -1: {
444  // When doing lhs > -1 use a tst instruction on the top part of lhs
445  // and use brpl instead of using a chain of cp/cpc.
446  UseTest = true;
447  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
448  break;
449  }
450  case 0: {
451  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
452  // __zero_reg__ in lhs.
453  RHS = LHS;
454  LHS = DAG.getConstant(0, DL, VT);
455  CC = ISD::SETLT;
456  break;
457  }
458  default: {
459  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
460  // us to fold the constant into the cmp instruction.
461  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
462  CC = ISD::SETGE;
463  break;
464  }
465  }
466  break;
467  }
468  // Swap operands and reverse the branching condition.
469  std::swap(LHS, RHS);
470  CC = ISD::SETLT;
471  break;
472  }
473  case ISD::SETLT: {
474  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
475  switch (C->getSExtValue()) {
476  case 1: {
477  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
478  // __zero_reg__ in lhs.
479  RHS = LHS;
480  LHS = DAG.getConstant(0, DL, VT);
481  CC = ISD::SETGE;
482  break;
483  }
484  case 0: {
485  // When doing lhs < 0 use a tst instruction on the top part of lhs
486  // and use brmi instead of using a chain of cp/cpc.
487  UseTest = true;
488  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
489  break;
490  }
491  }
492  }
493  break;
494  }
495  case ISD::SETULE: {
496  // Swap operands and reverse the branching condition.
497  std::swap(LHS, RHS);
498  CC = ISD::SETUGE;
499  break;
500  }
501  case ISD::SETUGT: {
502  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
503  // fold the constant into the cmp instruction.
504  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
505  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
506  CC = ISD::SETUGE;
507  break;
508  }
509  // Swap operands and reverse the branching condition.
510  std::swap(LHS, RHS);
511  CC = ISD::SETULT;
512  break;
513  }
514  }
515 
516  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
517  // using the default and/or/xor expansion code which is much longer.
518  if (VT == MVT::i32) {
519  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
520  DAG.getIntPtrConstant(0, DL));
521  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
522  DAG.getIntPtrConstant(1, DL));
523  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
524  DAG.getIntPtrConstant(0, DL));
525  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
526  DAG.getIntPtrConstant(1, DL));
527 
528  if (UseTest) {
529  // When using tst we only care about the highest part.
530  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
531  DAG.getIntPtrConstant(1, DL));
532  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
533  } else {
534  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
535  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
536  }
537  } else if (VT == MVT::i64) {
538  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
539  DAG.getIntPtrConstant(0, DL));
540  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
541  DAG.getIntPtrConstant(1, DL));
542 
543  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
544  DAG.getIntPtrConstant(0, DL));
545  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
546  DAG.getIntPtrConstant(1, DL));
547  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
548  DAG.getIntPtrConstant(0, DL));
549  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
550  DAG.getIntPtrConstant(1, DL));
551 
552  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
553  DAG.getIntPtrConstant(0, DL));
554  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
555  DAG.getIntPtrConstant(1, DL));
556 
557  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
558  DAG.getIntPtrConstant(0, DL));
559  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
560  DAG.getIntPtrConstant(1, DL));
561  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
562  DAG.getIntPtrConstant(0, DL));
563  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
564  DAG.getIntPtrConstant(1, DL));
565 
566  if (UseTest) {
567  // When using tst we only care about the highest part.
568  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
569  DAG.getIntPtrConstant(1, DL));
570  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
571  } else {
572  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
573  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
574  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
575  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
576  }
577  } else if (VT == MVT::i8 || VT == MVT::i16) {
578  if (UseTest) {
579  // When using tst we only care about the highest part.
580  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
581  (VT == MVT::i8)
582  ? LHS
584  LHS, DAG.getIntPtrConstant(1, DL)));
585  } else {
586  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
587  }
588  } else {
589  llvm_unreachable("Invalid comparison size");
590  }
591 
592  // When using a test instruction AVRcc is already set.
593  if (!UseTest) {
594  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
595  }
596 
597  return Cmp;
598 }
599 
600 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
601  SDValue Chain = Op.getOperand(0);
602  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
603  SDValue LHS = Op.getOperand(2);
604  SDValue RHS = Op.getOperand(3);
605  SDValue Dest = Op.getOperand(4);
606  SDLoc dl(Op);
607 
608  SDValue TargetCC;
609  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
610 
611  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
612  Cmp);
613 }
614 
615 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
616  SDValue LHS = Op.getOperand(0);
617  SDValue RHS = Op.getOperand(1);
618  SDValue TrueV = Op.getOperand(2);
619  SDValue FalseV = Op.getOperand(3);
620  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
621  SDLoc dl(Op);
622 
623  SDValue TargetCC;
624  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
625 
626  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
627  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
628 
629  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
630 }
631 
632 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
633  SDValue LHS = Op.getOperand(0);
634  SDValue RHS = Op.getOperand(1);
635  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
636  SDLoc DL(Op);
637 
638  SDValue TargetCC;
639  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
640 
641  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
642  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
643  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
644  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
645 
646  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
647 }
648 
649 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
650  const MachineFunction &MF = DAG.getMachineFunction();
652  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
653  auto DL = DAG.getDataLayout();
654  SDLoc dl(Op);
655 
656  // Vastart just stores the address of the VarArgsFrameIndex slot into the
657  // memory location argument.
659 
660  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
661  MachinePointerInfo(SV), 0);
662 }
663 
665  switch (Op.getOpcode()) {
666  default:
667  llvm_unreachable("Don't know how to custom lower this!");
668  case ISD::SHL:
669  case ISD::SRA:
670  case ISD::SRL:
671  case ISD::ROTL:
672  case ISD::ROTR:
673  return LowerShifts(Op, DAG);
674  case ISD::GlobalAddress:
675  return LowerGlobalAddress(Op, DAG);
676  case ISD::BlockAddress:
677  return LowerBlockAddress(Op, DAG);
678  case ISD::BR_CC:
679  return LowerBR_CC(Op, DAG);
680  case ISD::SELECT_CC:
681  return LowerSELECT_CC(Op, DAG);
682  case ISD::SETCC:
683  return LowerSETCC(Op, DAG);
684  case ISD::VASTART:
685  return LowerVASTART(Op, DAG);
686  case ISD::SDIVREM:
687  case ISD::UDIVREM:
688  return LowerDivRem(Op, DAG);
689  }
690 
691  return SDValue();
692 }
693 
694 /// Replace a node with an illegal result type
695 /// with a new node built out of custom code.
698  SelectionDAG &DAG) const {
699  SDLoc DL(N);
700 
701  switch (N->getOpcode()) {
702  case ISD::ADD: {
703  // Convert add (x, imm) into sub (x, -imm).
704  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
705  SDValue Sub = DAG.getNode(
706  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
707  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
708  Results.push_back(Sub);
709  }
710  break;
711  }
712  default: {
713  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
714 
715  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
716  Results.push_back(Res.getValue(I));
717 
718  break;
719  }
720  }
721 }
722 
723 /// Return true if the addressing mode represented
724 /// by AM is legal for this target, for a load/store of the specified type.
726  const AddrMode &AM, Type *Ty,
727  unsigned AS, Instruction *I) const {
728  int64_t Offs = AM.BaseOffs;
729 
730  // Allow absolute addresses.
731  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
732  return true;
733  }
734 
735  // Flash memory instructions only allow zero offsets.
736  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
737  return false;
738  }
739 
740  // Allow reg+<6bit> offset.
741  if (Offs < 0)
742  Offs = -Offs;
743  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
744  return true;
745  }
746 
747  return false;
748 }
749 
750 /// Returns true by value, base pointer and
751 /// offset pointer and addressing mode by reference if the node's address
752 /// can be legally represented as pre-indexed load / store address.
754  SDValue &Offset,
756  SelectionDAG &DAG) const {
757  EVT VT;
758  const SDNode *Op;
759  SDLoc DL(N);
760 
761  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
762  VT = LD->getMemoryVT();
763  Op = LD->getBasePtr().getNode();
764  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
765  return false;
767  return false;
768  }
769  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
770  VT = ST->getMemoryVT();
771  Op = ST->getBasePtr().getNode();
773  return false;
774  }
775  } else {
776  return false;
777  }
778 
779  if (VT != MVT::i8 && VT != MVT::i16) {
780  return false;
781  }
782 
783  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
784  return false;
785  }
786 
787  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
788  int RHSC = RHS->getSExtValue();
789  if (Op->getOpcode() == ISD::SUB)
790  RHSC = -RHSC;
791 
792  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
793  return false;
794  }
795 
796  Base = Op->getOperand(0);
797  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
798  AM = ISD::PRE_DEC;
799 
800  return true;
801  }
802 
803  return false;
804 }
805 
806 /// Returns true by value, base pointer and
807 /// offset pointer and addressing mode by reference if this node can be
808 /// combined with a load / store to form a post-indexed load / store.
810  SDValue &Base,
811  SDValue &Offset,
813  SelectionDAG &DAG) const {
814  EVT VT;
815  SDLoc DL(N);
816 
817  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
818  VT = LD->getMemoryVT();
819  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
820  return false;
821  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
822  VT = ST->getMemoryVT();
824  return false;
825  }
826  } else {
827  return false;
828  }
829 
830  if (VT != MVT::i8 && VT != MVT::i16) {
831  return false;
832  }
833 
834  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
835  return false;
836  }
837 
838  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
839  int RHSC = RHS->getSExtValue();
840  if (Op->getOpcode() == ISD::SUB)
841  RHSC = -RHSC;
842  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
843  return false;
844  }
845 
846  Base = Op->getOperand(0);
847  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
848  AM = ISD::POST_INC;
849 
850  return true;
851  }
852 
853  return false;
854 }
855 
857  const GlobalAddressSDNode *GA) const {
858  return true;
859 }
860 
861 //===----------------------------------------------------------------------===//
862 // Formal Arguments Calling Convention Implementation
863 //===----------------------------------------------------------------------===//
864 
865 #include "AVRGenCallingConv.inc"
866 
867 /// For each argument in a function store the number of pieces it is composed
868 /// of.
869 static void parseFunctionArgs(const Function *F, const DataLayout *TD,
871  for (Argument const &Arg : F->args()) {
872  unsigned Bytes = (TD->getTypeSizeInBits(Arg.getType()) + 7) / 8;
873  Out.push_back((Bytes + 1) / 2);
874  }
875 }
876 
877 /// For external symbols there is no function prototype information so we
878 /// have to rely directly on argument sizes.
881  for (unsigned i = 0, e = In.size(); i != e;) {
882  unsigned Size = 0;
883  unsigned Offset = 0;
884  while ((i != e) && (In[i].PartOffset == Offset)) {
885  Offset += In[i].VT.getStoreSize();
886  ++i;
887  ++Size;
888  }
889  Out.push_back(Size);
890  }
891 }
892 
894  SDValue Callee = CLI.Callee;
895 
896  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
897  return G->getSymbol();
898  }
899 
900  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
901  return G->getGlobal()->getName();
902  }
903 
904  llvm_unreachable("don't know how to get the name for this callee");
905 }
906 
907 /// Analyze incoming and outgoing function arguments. We need custom C++ code
908 /// to handle special constraints in the ABI like reversing the order of the
909 /// pieces of splitted arguments. In addition, all pieces of a certain argument
910 /// have to be passed either using registers or the stack but never mixing both.
912  const Function *F, const DataLayout *TD,
915  CallingConv::ID CallConv,
917  CCState &CCInfo, bool IsCall, bool IsVarArg) {
918  static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
919  AVR::R18, AVR::R16, AVR::R14,
920  AVR::R12, AVR::R10, AVR::R8};
921  static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
922  AVR::R19R18, AVR::R17R16, AVR::R15R14,
923  AVR::R13R12, AVR::R11R10, AVR::R9R8};
924  if (IsVarArg) {
925  // Variadic functions do not need all the analisys below.
926  if (IsCall) {
927  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
928  } else {
929  CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
930  }
931  return;
932  }
933 
934  // Fill in the Args array which will contain original argument sizes.
936  if (IsCall) {
937  parseExternFuncCallArgs(*Outs, Args);
938  } else {
939  assert(F != nullptr && "function should not be null");
940  parseFunctionArgs(F, TD, Args);
941  }
942 
943  unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
944  // Variadic functions always use the stack.
945  bool UsesStack = false;
946  for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
947  unsigned Size = Args[i];
948 
949  // If we have a zero-sized argument, don't attempt to lower it.
950  // AVR-GCC does not support zero-sized arguments and so we need not
951  // worry about ABI compatibility.
952  if (Size == 0) continue;
953 
954  MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
955 
956  // If we have plenty of regs to pass the whole argument do it.
957  if (!UsesStack && (Size <= RegsLeft)) {
958  const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
959 
960  for (unsigned j = 0; j != Size; ++j) {
961  unsigned Reg = CCInfo.AllocateReg(
962  ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
963  CCInfo.addLoc(
964  CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
965  --RegsLeft;
966  }
967 
968  // Reverse the order of the pieces to agree with the "big endian" format
969  // required in the calling convention ABI.
970  std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
971  } else {
972  // Pass the rest of arguments using the stack.
973  UsesStack = true;
974  for (unsigned j = 0; j != Size; ++j) {
975  unsigned Offset = CCInfo.AllocateStack(
976  TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
978  EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
979  CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
981  }
982  }
983  pos += Size;
984  }
985 }
986 
988  const Function *F, const DataLayout *TD,
991  CallingConv::ID CallConv,
993  CCState &CCInfo, bool IsCall, bool IsVarArg) {
994  StringRef FuncName = getFunctionName(CLI);
995 
996  if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
997  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
998  } else {
999  analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1000  CallConv, ArgLocs, CCInfo,
1001  IsCall, IsVarArg);
1002  }
1003 }
1004 
1006  const Function *F, const DataLayout *TD,
1007  const SmallVectorImpl<ISD::OutputArg> *Outs,
1009  CallingConv::ID CallConv,
1011  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1012  switch (CallConv) {
1013  case CallingConv::AVR_BUILTIN: {
1014  analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
1015  CallConv, ArgLocs, CCInfo,
1016  IsCall, IsVarArg);
1017  return;
1018  }
1019  default: {
1020  analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1021  CallConv, ArgLocs, CCInfo,
1022  IsCall, IsVarArg);
1023  return;
1024  }
1025  }
1026 }
1027 
1028 SDValue AVRTargetLowering::LowerFormalArguments(
1029  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1030  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1031  SmallVectorImpl<SDValue> &InVals) const {
1032  MachineFunction &MF = DAG.getMachineFunction();
1033  MachineFrameInfo &MFI = MF.getFrameInfo();
1034  auto DL = DAG.getDataLayout();
1035 
1036  // Assign locations to all of the incoming arguments.
1038  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1039  *DAG.getContext());
1040 
1041  analyzeArguments(nullptr, MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1042  false, isVarArg);
1043 
1044  SDValue ArgValue;
1045  for (CCValAssign &VA : ArgLocs) {
1046 
1047  // Arguments stored on registers.
1048  if (VA.isRegLoc()) {
1049  EVT RegVT = VA.getLocVT();
1050  const TargetRegisterClass *RC;
1051  if (RegVT == MVT::i8) {
1052  RC = &AVR::GPR8RegClass;
1053  } else if (RegVT == MVT::i16) {
1054  RC = &AVR::DREGSRegClass;
1055  } else {
1056  llvm_unreachable("Unknown argument type!");
1057  }
1058 
1059  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1060  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1061 
1062  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1063  // following code will handle zexts or sexts generated by other
1064  // front ends. Otherwise:
1065  // If this is an 8 bit value, it is really passed promoted
1066  // to 16 bits. Insert an assert[sz]ext to capture this, then
1067  // truncate to the right size.
1068  switch (VA.getLocInfo()) {
1069  default:
1070  llvm_unreachable("Unknown loc info!");
1071  case CCValAssign::Full:
1072  break;
1073  case CCValAssign::BCvt:
1074  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1075  break;
1076  case CCValAssign::SExt:
1077  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1078  DAG.getValueType(VA.getValVT()));
1079  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1080  break;
1081  case CCValAssign::ZExt:
1082  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1083  DAG.getValueType(VA.getValVT()));
1084  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1085  break;
1086  }
1087 
1088  InVals.push_back(ArgValue);
1089  } else {
1090  // Sanity check.
1091  assert(VA.isMemLoc());
1092 
1093  EVT LocVT = VA.getLocVT();
1094 
1095  // Create the frame index object for this incoming parameter.
1096  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1097  VA.getLocMemOffset(), true);
1098 
1099  // Create the SelectionDAG nodes corresponding to a load
1100  // from this parameter.
1101  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1102  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1104  0));
1105  }
1106  }
1107 
1108  // If the function takes variable number of arguments, make a frame index for
1109  // the start of the first vararg value... for expansion of llvm.va_start.
1110  if (isVarArg) {
1111  unsigned StackSize = CCInfo.getNextStackOffset();
1113 
1114  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1115  }
1116 
1117  return Chain;
1118 }
1119 
1120 //===----------------------------------------------------------------------===//
1121 // Call Calling Convention Implementation
1122 //===----------------------------------------------------------------------===//
1123 
1124 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1125  SmallVectorImpl<SDValue> &InVals) const {
1126  SelectionDAG &DAG = CLI.DAG;
1127  SDLoc &DL = CLI.DL;
1129  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1131  SDValue Chain = CLI.Chain;
1132  SDValue Callee = CLI.Callee;
1133  bool &isTailCall = CLI.IsTailCall;
1134  CallingConv::ID CallConv = CLI.CallConv;
1135  bool isVarArg = CLI.IsVarArg;
1136 
1137  MachineFunction &MF = DAG.getMachineFunction();
1138 
1139  // AVR does not yet support tail call optimization.
1140  isTailCall = false;
1141 
1142  // Analyze operands of the call, assigning locations to each operand.
1144  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1145  *DAG.getContext());
1146 
1147  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1148  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1149  // node so that legalize doesn't hack it.
1150  const Function *F = nullptr;
1151  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1152  const GlobalValue *GV = G->getGlobal();
1153 
1154  F = cast<Function>(GV);
1155  Callee =
1157  } else if (const ExternalSymbolSDNode *ES =
1158  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1159  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1160  getPointerTy(DAG.getDataLayout()));
1161  }
1162 
1163  analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1164  true, isVarArg);
1165 
1166  // Get a count of how many bytes are to be pushed on the stack.
1167  unsigned NumBytes = CCInfo.getNextStackOffset();
1168 
1169  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1170 
1172 
1173  // First, walk the register assignments, inserting copies.
1174  unsigned AI, AE;
1175  bool HasStackArgs = false;
1176  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1177  CCValAssign &VA = ArgLocs[AI];
1178  EVT RegVT = VA.getLocVT();
1179  SDValue Arg = OutVals[AI];
1180 
1181  // Promote the value if needed. With Clang this should not happen.
1182  switch (VA.getLocInfo()) {
1183  default:
1184  llvm_unreachable("Unknown loc info!");
1185  case CCValAssign::Full:
1186  break;
1187  case CCValAssign::SExt:
1188  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1189  break;
1190  case CCValAssign::ZExt:
1191  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1192  break;
1193  case CCValAssign::AExt:
1194  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1195  break;
1196  case CCValAssign::BCvt:
1197  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1198  break;
1199  }
1200 
1201  // Stop when we encounter a stack argument, we need to process them
1202  // in reverse order in the loop below.
1203  if (VA.isMemLoc()) {
1204  HasStackArgs = true;
1205  break;
1206  }
1207 
1208  // Arguments that can be passed on registers must be kept in the RegsToPass
1209  // vector.
1210  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1211  }
1212 
1213  // Second, stack arguments have to walked in reverse order by inserting
1214  // chained stores, this ensures their order is not changed by the scheduler
1215  // and that the push instruction sequence generated is correct, otherwise they
1216  // can be freely intermixed.
1217  if (HasStackArgs) {
1218  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1219  unsigned Loc = AI - 1;
1220  CCValAssign &VA = ArgLocs[Loc];
1221  SDValue Arg = OutVals[Loc];
1222 
1223  assert(VA.isMemLoc());
1224 
1225  // SP points to one stack slot further so add one to adjust it.
1226  SDValue PtrOff = DAG.getNode(
1227  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1228  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1229  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1230 
1231  Chain =
1232  DAG.getStore(Chain, DL, Arg, PtrOff,
1234  0);
1235  }
1236  }
1237 
1238  // Build a sequence of copy-to-reg nodes chained together with token chain and
1239  // flag operands which copy the outgoing args into registers. The InFlag in
1240  // necessary since all emited instructions must be stuck together.
1241  SDValue InFlag;
1242  for (auto Reg : RegsToPass) {
1243  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1244  InFlag = Chain.getValue(1);
1245  }
1246 
1247  // Returns a chain & a flag for retval copy to use.
1248  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1250  Ops.push_back(Chain);
1251  Ops.push_back(Callee);
1252 
1253  // Add argument registers to the end of the list so that they are known live
1254  // into the call.
1255  for (auto Reg : RegsToPass) {
1256  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1257  }
1258 
1259  // Add a register mask operand representing the call-preserved registers.
1260  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1262  const uint32_t *Mask =
1263  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1264  assert(Mask && "Missing call preserved mask for calling convention");
1265  Ops.push_back(DAG.getRegisterMask(Mask));
1266 
1267  if (InFlag.getNode()) {
1268  Ops.push_back(InFlag);
1269  }
1270 
1271  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1272  InFlag = Chain.getValue(1);
1273 
1274  // Create the CALLSEQ_END node.
1275  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1276  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1277 
1278  if (!Ins.empty()) {
1279  InFlag = Chain.getValue(1);
1280  }
1281 
1282  // Handle result values, copying them out of physregs into vregs that we
1283  // return.
1284  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1285  InVals);
1286 }
1287 
1288 /// Lower the result values of a call into the
1289 /// appropriate copies out of appropriate physical registers.
1290 ///
1291 SDValue AVRTargetLowering::LowerCallResult(
1292  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1293  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1294  SmallVectorImpl<SDValue> &InVals) const {
1295 
1296  // Assign locations to each value returned by this call.
1298  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1299  *DAG.getContext());
1300 
1301  // Handle runtime calling convs.
1302  auto CCFunction = CCAssignFnForReturn(CallConv);
1303  CCInfo.AnalyzeCallResult(Ins, CCFunction);
1304 
1305  if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1306  // Reverse splitted return values to get the "big endian" format required
1307  // to agree with the calling convention ABI.
1308  std::reverse(RVLocs.begin(), RVLocs.end());
1309  }
1310 
1311  // Copy all of the result registers out of their specified physreg.
1312  for (CCValAssign const &RVLoc : RVLocs) {
1313  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1314  InFlag)
1315  .getValue(1);
1316  InFlag = Chain.getValue(2);
1317  InVals.push_back(Chain.getValue(0));
1318  }
1319 
1320  return Chain;
1321 }
1322 
1323 //===----------------------------------------------------------------------===//
1324 // Return Value Calling Convention Implementation
1325 //===----------------------------------------------------------------------===//
1326 
1327 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1328  switch (CC) {
1330  return RetCC_AVR_BUILTIN;
1331  default:
1332  return RetCC_AVR;
1333  }
1334 }
1335 
1336 bool
1337 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1338  MachineFunction &MF, bool isVarArg,
1339  const SmallVectorImpl<ISD::OutputArg> &Outs,
1340  LLVMContext &Context) const
1341 {
1343  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1344 
1345  auto CCFunction = CCAssignFnForReturn(CallConv);
1346  return CCInfo.CheckReturn(Outs, CCFunction);
1347 }
1348 
1349 SDValue
1350 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1351  bool isVarArg,
1352  const SmallVectorImpl<ISD::OutputArg> &Outs,
1353  const SmallVectorImpl<SDValue> &OutVals,
1354  const SDLoc &dl, SelectionDAG &DAG) const {
1355  // CCValAssign - represent the assignment of the return value to locations.
1357 
1358  // CCState - Info about the registers and stack slot.
1359  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1360  *DAG.getContext());
1361 
1362  // Analyze return values.
1363  auto CCFunction = CCAssignFnForReturn(CallConv);
1364  CCInfo.AnalyzeReturn(Outs, CCFunction);
1365 
1366  // If this is the first return lowered for this function, add the regs to
1367  // the liveout set for the function.
1368  MachineFunction &MF = DAG.getMachineFunction();
1369  unsigned e = RVLocs.size();
1370 
1371  // Reverse splitted return values to get the "big endian" format required
1372  // to agree with the calling convention ABI.
1373  if (e > 1) {
1374  std::reverse(RVLocs.begin(), RVLocs.end());
1375  }
1376 
1377  SDValue Flag;
1378  SmallVector<SDValue, 4> RetOps(1, Chain);
1379  // Copy the result values into the output registers.
1380  for (unsigned i = 0; i != e; ++i) {
1381  CCValAssign &VA = RVLocs[i];
1382  assert(VA.isRegLoc() && "Can only return in registers!");
1383 
1384  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1385 
1386  // Guarantee that all emitted copies are stuck together with flags.
1387  Flag = Chain.getValue(1);
1388  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1389  }
1390 
1391  // Don't emit the ret/reti instruction when the naked attribute is present in
1392  // the function being compiled.
1394  AttributeList::FunctionIndex, Attribute::Naked)) {
1395  return Chain;
1396  }
1397 
1398  unsigned RetOpc =
1399  (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1401  : AVRISD::RET_FLAG;
1402 
1403  RetOps[0] = Chain; // Update chain.
1404 
1405  if (Flag.getNode()) {
1406  RetOps.push_back(Flag);
1407  }
1408 
1409  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1410 }
1411 
1412 //===----------------------------------------------------------------------===//
1413 // Custom Inserters
1414 //===----------------------------------------------------------------------===//
1415 
1416 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1417  MachineBasicBlock *BB) const {
1418  unsigned Opc;
1419  const TargetRegisterClass *RC;
1420  MachineFunction *F = BB->getParent();
1421  MachineRegisterInfo &RI = F->getRegInfo();
1422  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1424  DebugLoc dl = MI.getDebugLoc();
1425 
1426  switch (MI.getOpcode()) {
1427  default:
1428  llvm_unreachable("Invalid shift opcode!");
1429  case AVR::Lsl8:
1430  Opc = AVR::LSLRd;
1431  RC = &AVR::GPR8RegClass;
1432  break;
1433  case AVR::Lsl16:
1434  Opc = AVR::LSLWRd;
1435  RC = &AVR::DREGSRegClass;
1436  break;
1437  case AVR::Asr8:
1438  Opc = AVR::ASRRd;
1439  RC = &AVR::GPR8RegClass;
1440  break;
1441  case AVR::Asr16:
1442  Opc = AVR::ASRWRd;
1443  RC = &AVR::DREGSRegClass;
1444  break;
1445  case AVR::Lsr8:
1446  Opc = AVR::LSRRd;
1447  RC = &AVR::GPR8RegClass;
1448  break;
1449  case AVR::Lsr16:
1450  Opc = AVR::LSRWRd;
1451  RC = &AVR::DREGSRegClass;
1452  break;
1453  case AVR::Rol8:
1454  Opc = AVR::ROLRd;
1455  RC = &AVR::GPR8RegClass;
1456  break;
1457  case AVR::Rol16:
1458  Opc = AVR::ROLWRd;
1459  RC = &AVR::DREGSRegClass;
1460  break;
1461  case AVR::Ror8:
1462  Opc = AVR::RORRd;
1463  RC = &AVR::GPR8RegClass;
1464  break;
1465  case AVR::Ror16:
1466  Opc = AVR::RORWRd;
1467  RC = &AVR::DREGSRegClass;
1468  break;
1469  }
1470 
1471  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1472 
1474  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1475  if (I != F->end()) ++I;
1476 
1477  // Create loop block.
1478  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1479  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1480 
1481  F->insert(I, LoopBB);
1482  F->insert(I, RemBB);
1483 
1484  // Update machine-CFG edges by transferring all successors of the current
1485  // block to the block containing instructions after shift.
1486  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1487  BB->end());
1489 
1490  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1491  BB->addSuccessor(LoopBB);
1492  BB->addSuccessor(RemBB);
1493  LoopBB->addSuccessor(RemBB);
1494  LoopBB->addSuccessor(LoopBB);
1495 
1496  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1497  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1498  unsigned ShiftReg = RI.createVirtualRegister(RC);
1499  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1500  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1501  unsigned SrcReg = MI.getOperand(1).getReg();
1502  unsigned DstReg = MI.getOperand(0).getReg();
1503 
1504  // BB:
1505  // cpi N, 0
1506  // breq RemBB
1507  BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1508  BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1509 
1510  // LoopBB:
1511  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1512  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1513  // ShiftReg2 = shift ShiftReg
1514  // ShiftAmt2 = ShiftAmt - 1;
1515  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1516  .addReg(SrcReg)
1517  .addMBB(BB)
1518  .addReg(ShiftReg2)
1519  .addMBB(LoopBB);
1520  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1521  .addReg(ShiftAmtSrcReg)
1522  .addMBB(BB)
1523  .addReg(ShiftAmtReg2)
1524  .addMBB(LoopBB);
1525  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1526  BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1527  .addReg(ShiftAmtReg)
1528  .addImm(1);
1529  BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1530 
1531  // RemBB:
1532  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1533  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1534  .addReg(SrcReg)
1535  .addMBB(BB)
1536  .addReg(ShiftReg2)
1537  .addMBB(LoopBB);
1538 
1539  MI.eraseFromParent(); // The pseudo instruction is gone now.
1540  return RemBB;
1541 }
1542 
1544  if (I->getOpcode() == AVR::COPY) {
1545  unsigned SrcReg = I->getOperand(1).getReg();
1546  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1547  }
1548 
1549  return false;
1550 }
1551 
1552 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1553 // after the result has been evacuated. This is probably not the best way to do
1554 // it, but it works for now.
1555 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1556  MachineBasicBlock *BB) const {
1557  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1560  ++I; // in any case insert *after* the mul instruction
1561  if (isCopyMulResult(I))
1562  ++I;
1563  if (isCopyMulResult(I))
1564  ++I;
1565  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1566  .addReg(AVR::R1)
1567  .addReg(AVR::R1);
1568  return BB;
1569 }
1570 
1573  MachineBasicBlock *MBB) const {
1574  int Opc = MI.getOpcode();
1575 
1576  // Pseudo shift instructions with a non constant shift amount are expanded
1577  // into a loop.
1578  switch (Opc) {
1579  case AVR::Lsl8:
1580  case AVR::Lsl16:
1581  case AVR::Lsr8:
1582  case AVR::Lsr16:
1583  case AVR::Rol8:
1584  case AVR::Rol16:
1585  case AVR::Ror8:
1586  case AVR::Ror16:
1587  case AVR::Asr8:
1588  case AVR::Asr16:
1589  return insertShift(MI, MBB);
1590  case AVR::MULRdRr:
1591  case AVR::MULSRdRr:
1592  return insertMul(MI, MBB);
1593  }
1594 
1595  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1596  "Unexpected instr type to insert");
1597 
1598  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1599  ->getParent()
1600  ->getSubtarget()
1601  .getInstrInfo();
1602  DebugLoc dl = MI.getDebugLoc();
1603 
1604  // To "insert" a SELECT instruction, we insert the diamond
1605  // control-flow pattern. The incoming instruction knows the
1606  // destination vreg to set, the condition code register to branch
1607  // on, the true/false values to select between, and a branch opcode
1608  // to use.
1609 
1610  MachineFunction *MF = MBB->getParent();
1611  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1612  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1613  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1614 
1616  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1617  if (I != MF->end()) ++I;
1618  MF->insert(I, trueMBB);
1619  MF->insert(I, falseMBB);
1620 
1621  // Transfer remaining instructions and all successors of the current
1622  // block to the block which will contain the Phi node for the
1623  // select.
1624  trueMBB->splice(trueMBB->begin(), MBB,
1625  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1626  trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1627 
1629  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1630  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1631  MBB->addSuccessor(falseMBB);
1632  MBB->addSuccessor(trueMBB);
1633 
1634  // Unconditionally flow back to the true block
1635  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1636  falseMBB->addSuccessor(trueMBB);
1637 
1638  // Set up the Phi node to determine where we came from
1639  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1640  .addReg(MI.getOperand(1).getReg())
1641  .addMBB(MBB)
1642  .addReg(MI.getOperand(2).getReg())
1643  .addMBB(falseMBB) ;
1644 
1645  MI.eraseFromParent(); // The pseudo instruction is gone now.
1646  return trueMBB;
1647 }
1648 
1649 //===----------------------------------------------------------------------===//
1650 // Inline Asm Support
1651 //===----------------------------------------------------------------------===//
1652 
1655  if (Constraint.size() == 1) {
1656  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1657  switch (Constraint[0]) {
1658  case 'a': // Simple upper registers
1659  case 'b': // Base pointer registers pairs
1660  case 'd': // Upper register
1661  case 'l': // Lower registers
1662  case 'e': // Pointer register pairs
1663  case 'q': // Stack pointer register
1664  case 'r': // Any register
1665  case 'w': // Special upper register pairs
1666  return C_RegisterClass;
1667  case 't': // Temporary register
1668  case 'x': case 'X': // Pointer register pair X
1669  case 'y': case 'Y': // Pointer register pair Y
1670  case 'z': case 'Z': // Pointer register pair Z
1671  return C_Register;
1672  case 'Q': // A memory address based on Y or Z pointer with displacement.
1673  return C_Memory;
1674  case 'G': // Floating point constant
1675  case 'I': // 6-bit positive integer constant
1676  case 'J': // 6-bit negative integer constant
1677  case 'K': // Integer constant (Range: 2)
1678  case 'L': // Integer constant (Range: 0)
1679  case 'M': // 8-bit integer constant
1680  case 'N': // Integer constant (Range: -1)
1681  case 'O': // Integer constant (Range: 8, 16, 24)
1682  case 'P': // Integer constant (Range: 1)
1683  case 'R': // Integer constant (Range: -6 to 5)x
1684  return C_Other;
1685  default:
1686  break;
1687  }
1688  }
1689 
1690  return TargetLowering::getConstraintType(Constraint);
1691 }
1692 
1693 unsigned
1695  // Not sure if this is actually the right thing to do, but we got to do
1696  // *something* [agnat]
1697  switch (ConstraintCode[0]) {
1698  case 'Q':
1699  return InlineAsm::Constraint_Q;
1700  }
1701  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1702 }
1703 
1706  AsmOperandInfo &info, const char *constraint) const {
1707  ConstraintWeight weight = CW_Invalid;
1708  Value *CallOperandVal = info.CallOperandVal;
1709 
1710  // If we don't have a value, we can't do a match,
1711  // but allow it at the lowest weight.
1712  // (this behaviour has been copied from the ARM backend)
1713  if (!CallOperandVal) {
1714  return CW_Default;
1715  }
1716 
1717  // Look at the constraint type.
1718  switch (*constraint) {
1719  default:
1720  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1721  break;
1722  case 'd':
1723  case 'r':
1724  case 'l':
1725  weight = CW_Register;
1726  break;
1727  case 'a':
1728  case 'b':
1729  case 'e':
1730  case 'q':
1731  case 't':
1732  case 'w':
1733  case 'x': case 'X':
1734  case 'y': case 'Y':
1735  case 'z': case 'Z':
1736  weight = CW_SpecificReg;
1737  break;
1738  case 'G':
1739  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1740  if (C->isZero()) {
1741  weight = CW_Constant;
1742  }
1743  }
1744  break;
1745  case 'I':
1746  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1747  if (isUInt<6>(C->getZExtValue())) {
1748  weight = CW_Constant;
1749  }
1750  }
1751  break;
1752  case 'J':
1753  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1754  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1755  weight = CW_Constant;
1756  }
1757  }
1758  break;
1759  case 'K':
1760  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1761  if (C->getZExtValue() == 2) {
1762  weight = CW_Constant;
1763  }
1764  }
1765  break;
1766  case 'L':
1767  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1768  if (C->getZExtValue() == 0) {
1769  weight = CW_Constant;
1770  }
1771  }
1772  break;
1773  case 'M':
1774  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1775  if (isUInt<8>(C->getZExtValue())) {
1776  weight = CW_Constant;
1777  }
1778  }
1779  break;
1780  case 'N':
1781  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1782  if (C->getSExtValue() == -1) {
1783  weight = CW_Constant;
1784  }
1785  }
1786  break;
1787  case 'O':
1788  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1789  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1790  (C->getZExtValue() == 24)) {
1791  weight = CW_Constant;
1792  }
1793  }
1794  break;
1795  case 'P':
1796  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1797  if (C->getZExtValue() == 1) {
1798  weight = CW_Constant;
1799  }
1800  }
1801  break;
1802  case 'R':
1803  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1804  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1805  weight = CW_Constant;
1806  }
1807  }
1808  break;
1809  case 'Q':
1810  weight = CW_Memory;
1811  break;
1812  }
1813 
1814  return weight;
1815 }
1816 
1817 std::pair<unsigned, const TargetRegisterClass *>
1819  StringRef Constraint,
1820  MVT VT) const {
1821  auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine())
1822  .getSubtargetImpl();
1823 
1824  // We only support i8 and i16.
1825  //
1826  //:FIXME: remove this assert for now since it gets sometimes executed
1827  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1828 
1829  if (Constraint.size() == 1) {
1830  switch (Constraint[0]) {
1831  case 'a': // Simple upper registers r16..r23.
1832  return std::make_pair(0U, &AVR::LD8loRegClass);
1833  case 'b': // Base pointer registers: y, z.
1834  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1835  case 'd': // Upper registers r16..r31.
1836  return std::make_pair(0U, &AVR::LD8RegClass);
1837  case 'l': // Lower registers r0..r15.
1838  return std::make_pair(0U, &AVR::GPR8loRegClass);
1839  case 'e': // Pointer register pairs: x, y, z.
1840  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1841  case 'q': // Stack pointer register: SPH:SPL.
1842  return std::make_pair(0U, &AVR::GPRSPRegClass);
1843  case 'r': // Any register: r0..r31.
1844  if (VT == MVT::i8)
1845  return std::make_pair(0U, &AVR::GPR8RegClass);
1846 
1847  assert(VT == MVT::i16 && "inline asm constraint too large");
1848  return std::make_pair(0U, &AVR::DREGSRegClass);
1849  case 't': // Temporary register: r0.
1850  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1851  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1852  return std::make_pair(0U, &AVR::IWREGSRegClass);
1853  case 'x': // Pointer register pair X: r27:r26.
1854  case 'X':
1855  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1856  case 'y': // Pointer register pair Y: r29:r28.
1857  case 'Y':
1858  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1859  case 'z': // Pointer register pair Z: r31:r30.
1860  case 'Z':
1861  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1862  default:
1863  break;
1864  }
1865  }
1866 
1867  return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(),
1868  Constraint, VT);
1869 }
1870 
1872  std::string &Constraint,
1873  std::vector<SDValue> &Ops,
1874  SelectionDAG &DAG) const {
1875  SDValue Result(0, 0);
1876  SDLoc DL(Op);
1877  EVT Ty = Op.getValueType();
1878 
1879  // Currently only support length 1 constraints.
1880  if (Constraint.length() != 1) {
1881  return;
1882  }
1883 
1884  char ConstraintLetter = Constraint[0];
1885  switch (ConstraintLetter) {
1886  default:
1887  break;
1888  // Deal with integers first:
1889  case 'I':
1890  case 'J':
1891  case 'K':
1892  case 'L':
1893  case 'M':
1894  case 'N':
1895  case 'O':
1896  case 'P':
1897  case 'R': {
1899  if (!C) {
1900  return;
1901  }
1902 
1903  int64_t CVal64 = C->getSExtValue();
1904  uint64_t CUVal64 = C->getZExtValue();
1905  switch (ConstraintLetter) {
1906  case 'I': // 0..63
1907  if (!isUInt<6>(CUVal64))
1908  return;
1909  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1910  break;
1911  case 'J': // -63..0
1912  if (CVal64 < -63 || CVal64 > 0)
1913  return;
1914  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1915  break;
1916  case 'K': // 2
1917  if (CUVal64 != 2)
1918  return;
1919  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1920  break;
1921  case 'L': // 0
1922  if (CUVal64 != 0)
1923  return;
1924  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1925  break;
1926  case 'M': // 0..255
1927  if (!isUInt<8>(CUVal64))
1928  return;
1929  // i8 type may be printed as a negative number,
1930  // e.g. 254 would be printed as -2,
1931  // so we force it to i16 at least.
1932  if (Ty.getSimpleVT() == MVT::i8) {
1933  Ty = MVT::i16;
1934  }
1935  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1936  break;
1937  case 'N': // -1
1938  if (CVal64 != -1)
1939  return;
1940  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1941  break;
1942  case 'O': // 8, 16, 24
1943  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1944  return;
1945  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1946  break;
1947  case 'P': // 1
1948  if (CUVal64 != 1)
1949  return;
1950  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1951  break;
1952  case 'R': // -6..5
1953  if (CVal64 < -6 || CVal64 > 5)
1954  return;
1955  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1956  break;
1957  }
1958 
1959  break;
1960  }
1961  case 'G':
1963  if (!FC || !FC->isZero())
1964  return;
1965  // Soften float to i8 0
1966  Result = DAG.getTargetConstant(0, DL, MVT::i8);
1967  break;
1968  }
1969 
1970  if (Result.getNode()) {
1971  Ops.push_back(Result);
1972  return;
1973  }
1974 
1975  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1976 }
1977 
1978 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
1979  EVT VT,
1980  SelectionDAG &DAG) const {
1981  unsigned Reg;
1982 
1983  if (VT == MVT::i8) {
1984  Reg = StringSwitch<unsigned>(RegName)
1985  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1986  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1987  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1988  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1989  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1990  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1991  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1992  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1993  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
1994  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
1995  .Case("r30", AVR::R30).Case("r31", AVR::R31)
1996  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1997  .Default(0);
1998  } else {
1999  Reg = StringSwitch<unsigned>(RegName)
2000  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2001  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2002  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2003  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2004  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2005  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2006  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2007  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2008  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2009  .Default(0);
2010  }
2011 
2012  if (Reg)
2013  return Reg;
2014 
2015  report_fatal_error("Invalid register name global variable");
2016 }
2017 
2018 } // end of namespace llvm
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:545
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
Used for AVR interrupt routines.
Definition: CallingConv.h:177
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
#define R4(n)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:30
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Unsigned lower.
Definition: AVRInstrInfo.h:38
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:666
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Test for zero or minus instruction.
A debug info location.
Definition: DebugLoc.h:34
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
#define R2(n)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
SDValue getExternalSymbol(const char *Sym, EVT VT)
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
const AVRSubtarget * getSubtargetImpl() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:813
Calling convention used for AVR signal routines.
Definition: CallingConv.h:180
Represents an abstract call instruction, which includes a bunch of information.
A loop of single right bit rotate instructions.
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:379
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:46
CallLoweringInfo & setChain(SDValue InChain)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:777
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:446
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:336
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:662
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:186
int64_t getSExtValue() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
A generic AVR implementation.
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
Return from subroutine.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
CallLoweringInfo & setZExtResult(bool Value=true)
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:205
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:558
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
bool isZero() const
Return true if the value is positive or negative zero.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:335
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
Contains AVR-specific information for each MachineFunction.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
Unsigned same or higher.
Definition: AVRInstrInfo.h:37
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:695
iterator_range< value_op_iterator > op_values() const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
const SDValue & getOperand(unsigned Num) const
LLVMContext & getContext() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
self_iterator getIterator()
Definition: ilist_node.h:82
AVR conditional branches.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:686
static void parseFunctionArgs(const Function *F, const DataLayout *TD, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:32
lazy value info
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:763
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
AVRTargetLowering(AVRTargetMachine &TM)
Compare instruction.
A loop of single logical shift right instructions.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
#define R6(n)
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:184
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
#define NODE(name)
CCValAssign - Represent assignment of one arg/retval to a location.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:674
A loop of single left bit rotate instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:682
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:611
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:382
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
Return from ISR.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
amdgpu Simplify well known AMD library false Value Value * Arg
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:530
Bit rotate left.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:403
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
Representation of each machine instruction.
Definition: MachineInstr.h:59
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:691
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:651
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:120
SmallVector< SDValue, 32 > OutVals
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Logical shift right.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
Arithmetic shift right.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
CallLoweringInfo & setInRegister(bool Value=true)
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
Greater than or equal.
Definition: AVRInstrInfo.h:35
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:46
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
Conversion operators.
Definition: ISDOpcodes.h:442
const SDValue & getOperand(unsigned i) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
uint64_t getZExtValue() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
iterator_range< arg_iterator > args()
Definition: Function.h:621
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:600
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:355
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:590