LLVM  7.0.0svn
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVRISelLowering.h"
16 
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRTargetMachine.h"
31 
32 namespace llvm {
33 
35  : TargetLowering(tm) {
36  // Set up the register classes.
37  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
39 
40  // Compute derived properties from the register classes.
42 
48 
51 
56 
57  for (MVT VT : MVT::integer_valuetypes()) {
58  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
61  }
62  }
63 
65 
66  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
67  // revert into a sub since we don't have an add with immediate instruction.
70 
71  // our shift instructions are only able to shift 1 bit at a time, so handle
72  // this in a custom way.
82 
87 
93 
104 
106 
107  // Add support for postincrement and predecrement load/stores.
116 
118 
123 
124  // Atomic operations which must be lowered to rtlib calls
125  for (MVT VT : MVT::integer_valuetypes()) {
133  }
134 
135  // Division/remainder
144 
145  // Make division and modulus custom
146  for (MVT VT : MVT::integer_valuetypes()) {
149  }
150 
151  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
154 
155  // Expand 16 bit multiplications.
158 
159  for (MVT VT : MVT::integer_valuetypes()) {
162  }
163 
164  for (MVT VT : MVT::integer_valuetypes()) {
168  }
169 
170  for (MVT VT : MVT::integer_valuetypes()) {
172  // TODO: The generated code is pretty poor. Investigate using the
173  // same "shift and subtract with carry" trick that we do for
174  // extending 8-bit to 16-bit. This may require infrastructure
175  // improvements in how we treat 16-bit "registers" to be feasible.
176  }
177 
178  // Division rtlib functions (not supported)
179  setLibcallName(RTLIB::SDIV_I8, nullptr);
180  setLibcallName(RTLIB::SDIV_I16, nullptr);
181  setLibcallName(RTLIB::SDIV_I32, nullptr);
182  setLibcallName(RTLIB::SDIV_I64, nullptr);
183  setLibcallName(RTLIB::SDIV_I128, nullptr);
184  setLibcallName(RTLIB::UDIV_I8, nullptr);
185  setLibcallName(RTLIB::UDIV_I16, nullptr);
186  setLibcallName(RTLIB::UDIV_I32, nullptr);
187  setLibcallName(RTLIB::UDIV_I64, nullptr);
188  setLibcallName(RTLIB::UDIV_I128, nullptr);
189 
190  // Modulus rtlib functions (not supported)
191  setLibcallName(RTLIB::SREM_I8, nullptr);
192  setLibcallName(RTLIB::SREM_I16, nullptr);
193  setLibcallName(RTLIB::SREM_I32, nullptr);
194  setLibcallName(RTLIB::SREM_I64, nullptr);
195  setLibcallName(RTLIB::SREM_I128, nullptr);
196  setLibcallName(RTLIB::UREM_I8, nullptr);
197  setLibcallName(RTLIB::UREM_I16, nullptr);
198  setLibcallName(RTLIB::UREM_I32, nullptr);
199  setLibcallName(RTLIB::UREM_I64, nullptr);
200  setLibcallName(RTLIB::UREM_I128, nullptr);
201 
202  // Division and modulus rtlib functions
203  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
204  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
205  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
206  setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
207  setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
208  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
209  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
210  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
211  setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
212  setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
213 
214  // Several of the runtime library functions use a special calling conv
216  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
218  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
219 
220  // Trigonometric rtlib functions
221  setLibcallName(RTLIB::SIN_F32, "sin");
222  setLibcallName(RTLIB::COS_F32, "cos");
223 
226 }
227 
228 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
229 #define NODE(name) \
230  case AVRISD::name: \
231  return #name
232 
233  switch (Opcode) {
234  default:
235  return nullptr;
236  NODE(RET_FLAG);
237  NODE(RETI_FLAG);
238  NODE(CALL);
239  NODE(WRAPPER);
240  NODE(LSL);
241  NODE(LSR);
242  NODE(ROL);
243  NODE(ROR);
244  NODE(ASR);
245  NODE(LSLLOOP);
246  NODE(LSRLOOP);
247  NODE(ASRLOOP);
248  NODE(BRCOND);
249  NODE(CMP);
250  NODE(CMPC);
251  NODE(TST);
252  NODE(SELECT_CC);
253 #undef NODE
254  }
255 }
256 
258  EVT VT) const {
259  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
260  return MVT::i8;
261 }
262 
263 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
264  //:TODO: this function has to be completely rewritten to produce optimal
265  // code, for now it's producing very long but correct code.
266  unsigned Opc8;
267  const SDNode *N = Op.getNode();
268  EVT VT = Op.getValueType();
269  SDLoc dl(N);
270 
271  // Expand non-constant shifts to loops.
272  if (!isa<ConstantSDNode>(N->getOperand(1))) {
273  switch (Op.getOpcode()) {
274  default:
275  llvm_unreachable("Invalid shift opcode!");
276  case ISD::SHL:
277  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
278  N->getOperand(1));
279  case ISD::SRL:
280  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
281  N->getOperand(1));
282  case ISD::ROTL:
283  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
284  N->getOperand(1));
285  case ISD::ROTR:
286  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
287  N->getOperand(1));
288  case ISD::SRA:
289  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
290  N->getOperand(1));
291  }
292  }
293 
294  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
295  SDValue Victim = N->getOperand(0);
296 
297  switch (Op.getOpcode()) {
298  case ISD::SRA:
299  Opc8 = AVRISD::ASR;
300  break;
301  case ISD::ROTL:
302  Opc8 = AVRISD::ROL;
303  break;
304  case ISD::ROTR:
305  Opc8 = AVRISD::ROR;
306  break;
307  case ISD::SRL:
308  Opc8 = AVRISD::LSR;
309  break;
310  case ISD::SHL:
311  Opc8 = AVRISD::LSL;
312  break;
313  default:
314  llvm_unreachable("Invalid shift opcode");
315  }
316 
317  while (ShiftAmount--) {
318  Victim = DAG.getNode(Opc8, dl, VT, Victim);
319  }
320 
321  return Victim;
322 }
323 
324 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
325  unsigned Opcode = Op->getOpcode();
326  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
327  "Invalid opcode for Div/Rem lowering");
328  bool IsSigned = (Opcode == ISD::SDIVREM);
329  EVT VT = Op->getValueType(0);
330  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
331 
332  RTLIB::Libcall LC;
333  switch (VT.getSimpleVT().SimpleTy) {
334  default:
335  llvm_unreachable("Unexpected request for libcall!");
336  case MVT::i8:
337  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
338  break;
339  case MVT::i16:
340  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
341  break;
342  case MVT::i32:
343  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
344  break;
345  case MVT::i64:
346  LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
347  break;
348  case MVT::i128:
349  LC = IsSigned ? RTLIB::SDIVREM_I128 : RTLIB::UDIVREM_I128;
350  break;
351  }
352 
353  SDValue InChain = DAG.getEntryNode();
354 
357  for (SDValue const &Value : Op->op_values()) {
358  Entry.Node = Value;
359  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
360  Entry.IsSExt = IsSigned;
361  Entry.IsZExt = !IsSigned;
362  Args.push_back(Entry);
363  }
364 
366  getPointerTy(DAG.getDataLayout()));
367 
368  Type *RetTy = (Type *)StructType::get(Ty, Ty);
369 
370  SDLoc dl(Op);
372  CLI.setDebugLoc(dl)
373  .setChain(InChain)
374  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
375  .setInRegister()
376  .setSExtResult(IsSigned)
377  .setZExtResult(!IsSigned);
378 
379  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
380  return CallInfo.first;
381 }
382 
383 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
384  SelectionDAG &DAG) const {
385  auto DL = DAG.getDataLayout();
386 
387  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
388  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
389 
390  // Create the TargetGlobalAddress node, folding in the constant offset.
391  SDValue Result =
392  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
393  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
394 }
395 
396 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
397  SelectionDAG &DAG) const {
398  auto DL = DAG.getDataLayout();
399  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
400 
401  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
402 
403  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
404 }
405 
406 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
408  switch (CC) {
409  default:
410  llvm_unreachable("Unknown condition code!");
411  case ISD::SETEQ:
412  return AVRCC::COND_EQ;
413  case ISD::SETNE:
414  return AVRCC::COND_NE;
415  case ISD::SETGE:
416  return AVRCC::COND_GE;
417  case ISD::SETLT:
418  return AVRCC::COND_LT;
419  case ISD::SETUGE:
420  return AVRCC::COND_SH;
421  case ISD::SETULT:
422  return AVRCC::COND_LO;
423  }
424 }
425 
426 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
427 /// the given operands.
428 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
429  SDValue &AVRcc, SelectionDAG &DAG,
430  SDLoc DL) const {
431  SDValue Cmp;
432  EVT VT = LHS.getValueType();
433  bool UseTest = false;
434 
435  switch (CC) {
436  default:
437  break;
438  case ISD::SETLE: {
439  // Swap operands and reverse the branching condition.
440  std::swap(LHS, RHS);
441  CC = ISD::SETGE;
442  break;
443  }
444  case ISD::SETGT: {
445  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
446  switch (C->getSExtValue()) {
447  case -1: {
448  // When doing lhs > -1 use a tst instruction on the top part of lhs
449  // and use brpl instead of using a chain of cp/cpc.
450  UseTest = true;
451  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
452  break;
453  }
454  case 0: {
455  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
456  // __zero_reg__ in lhs.
457  RHS = LHS;
458  LHS = DAG.getConstant(0, DL, VT);
459  CC = ISD::SETLT;
460  break;
461  }
462  default: {
463  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
464  // us to fold the constant into the cmp instruction.
465  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
466  CC = ISD::SETGE;
467  break;
468  }
469  }
470  break;
471  }
472  // Swap operands and reverse the branching condition.
473  std::swap(LHS, RHS);
474  CC = ISD::SETLT;
475  break;
476  }
477  case ISD::SETLT: {
478  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
479  switch (C->getSExtValue()) {
480  case 1: {
481  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
482  // __zero_reg__ in lhs.
483  RHS = LHS;
484  LHS = DAG.getConstant(0, DL, VT);
485  CC = ISD::SETGE;
486  break;
487  }
488  case 0: {
489  // When doing lhs < 0 use a tst instruction on the top part of lhs
490  // and use brmi instead of using a chain of cp/cpc.
491  UseTest = true;
492  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
493  break;
494  }
495  }
496  }
497  break;
498  }
499  case ISD::SETULE: {
500  // Swap operands and reverse the branching condition.
501  std::swap(LHS, RHS);
502  CC = ISD::SETUGE;
503  break;
504  }
505  case ISD::SETUGT: {
506  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
507  // fold the constant into the cmp instruction.
508  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
509  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
510  CC = ISD::SETUGE;
511  break;
512  }
513  // Swap operands and reverse the branching condition.
514  std::swap(LHS, RHS);
515  CC = ISD::SETULT;
516  break;
517  }
518  }
519 
520  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
521  // using the default and/or/xor expansion code which is much longer.
522  if (VT == MVT::i32) {
523  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
524  DAG.getIntPtrConstant(0, DL));
525  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
526  DAG.getIntPtrConstant(1, DL));
527  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
528  DAG.getIntPtrConstant(0, DL));
529  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
530  DAG.getIntPtrConstant(1, DL));
531 
532  if (UseTest) {
533  // When using tst we only care about the highest part.
534  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
535  DAG.getIntPtrConstant(1, DL));
536  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
537  } else {
538  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
539  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
540  }
541  } else if (VT == MVT::i64) {
542  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
543  DAG.getIntPtrConstant(0, DL));
544  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
545  DAG.getIntPtrConstant(1, DL));
546 
547  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
548  DAG.getIntPtrConstant(0, DL));
549  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
550  DAG.getIntPtrConstant(1, DL));
551  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
552  DAG.getIntPtrConstant(0, DL));
553  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
554  DAG.getIntPtrConstant(1, DL));
555 
556  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
557  DAG.getIntPtrConstant(0, DL));
558  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
559  DAG.getIntPtrConstant(1, DL));
560 
561  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
562  DAG.getIntPtrConstant(0, DL));
563  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
564  DAG.getIntPtrConstant(1, DL));
565  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
566  DAG.getIntPtrConstant(0, DL));
567  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
568  DAG.getIntPtrConstant(1, DL));
569 
570  if (UseTest) {
571  // When using tst we only care about the highest part.
572  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
573  DAG.getIntPtrConstant(1, DL));
574  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
575  } else {
576  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
577  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
578  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
579  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
580  }
581  } else if (VT == MVT::i8 || VT == MVT::i16) {
582  if (UseTest) {
583  // When using tst we only care about the highest part.
584  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
585  (VT == MVT::i8)
586  ? LHS
588  LHS, DAG.getIntPtrConstant(1, DL)));
589  } else {
590  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
591  }
592  } else {
593  llvm_unreachable("Invalid comparison size");
594  }
595 
596  // When using a test instruction AVRcc is already set.
597  if (!UseTest) {
598  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
599  }
600 
601  return Cmp;
602 }
603 
604 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
605  SDValue Chain = Op.getOperand(0);
606  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
607  SDValue LHS = Op.getOperand(2);
608  SDValue RHS = Op.getOperand(3);
609  SDValue Dest = Op.getOperand(4);
610  SDLoc dl(Op);
611 
612  SDValue TargetCC;
613  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
614 
615  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
616  Cmp);
617 }
618 
619 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
620  SDValue LHS = Op.getOperand(0);
621  SDValue RHS = Op.getOperand(1);
622  SDValue TrueV = Op.getOperand(2);
623  SDValue FalseV = Op.getOperand(3);
624  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
625  SDLoc dl(Op);
626 
627  SDValue TargetCC;
628  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
629 
630  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
631  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
632 
633  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
634 }
635 
636 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
637  SDValue LHS = Op.getOperand(0);
638  SDValue RHS = Op.getOperand(1);
639  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
640  SDLoc DL(Op);
641 
642  SDValue TargetCC;
643  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
644 
645  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
646  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
647  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
648  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
649 
650  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
651 }
652 
653 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
654  const MachineFunction &MF = DAG.getMachineFunction();
656  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
657  auto DL = DAG.getDataLayout();
658  SDLoc dl(Op);
659 
660  // Vastart just stores the address of the VarArgsFrameIndex slot into the
661  // memory location argument.
663 
664  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
665  MachinePointerInfo(SV), 0);
666 }
667 
669  switch (Op.getOpcode()) {
670  default:
671  llvm_unreachable("Don't know how to custom lower this!");
672  case ISD::SHL:
673  case ISD::SRA:
674  case ISD::SRL:
675  case ISD::ROTL:
676  case ISD::ROTR:
677  return LowerShifts(Op, DAG);
678  case ISD::GlobalAddress:
679  return LowerGlobalAddress(Op, DAG);
680  case ISD::BlockAddress:
681  return LowerBlockAddress(Op, DAG);
682  case ISD::BR_CC:
683  return LowerBR_CC(Op, DAG);
684  case ISD::SELECT_CC:
685  return LowerSELECT_CC(Op, DAG);
686  case ISD::SETCC:
687  return LowerSETCC(Op, DAG);
688  case ISD::VASTART:
689  return LowerVASTART(Op, DAG);
690  case ISD::SDIVREM:
691  case ISD::UDIVREM:
692  return LowerDivRem(Op, DAG);
693  }
694 
695  return SDValue();
696 }
697 
698 /// Replace a node with an illegal result type
699 /// with a new node built out of custom code.
702  SelectionDAG &DAG) const {
703  SDLoc DL(N);
704 
705  switch (N->getOpcode()) {
706  case ISD::ADD: {
707  // Convert add (x, imm) into sub (x, -imm).
708  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
709  SDValue Sub = DAG.getNode(
710  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
711  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
712  Results.push_back(Sub);
713  }
714  break;
715  }
716  default: {
717  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
718 
719  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
720  Results.push_back(Res.getValue(I));
721 
722  break;
723  }
724  }
725 }
726 
727 /// Return true if the addressing mode represented
728 /// by AM is legal for this target, for a load/store of the specified type.
730  const AddrMode &AM, Type *Ty,
731  unsigned AS, Instruction *I) const {
732  int64_t Offs = AM.BaseOffs;
733 
734  // Allow absolute addresses.
735  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
736  return true;
737  }
738 
739  // Flash memory instructions only allow zero offsets.
740  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
741  return false;
742  }
743 
744  // Allow reg+<6bit> offset.
745  if (Offs < 0)
746  Offs = -Offs;
747  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
748  return true;
749  }
750 
751  return false;
752 }
753 
754 /// Returns true by value, base pointer and
755 /// offset pointer and addressing mode by reference if the node's address
756 /// can be legally represented as pre-indexed load / store address.
758  SDValue &Offset,
760  SelectionDAG &DAG) const {
761  EVT VT;
762  const SDNode *Op;
763  SDLoc DL(N);
764 
765  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
766  VT = LD->getMemoryVT();
767  Op = LD->getBasePtr().getNode();
768  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
769  return false;
771  return false;
772  }
773  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
774  VT = ST->getMemoryVT();
775  Op = ST->getBasePtr().getNode();
777  return false;
778  }
779  } else {
780  return false;
781  }
782 
783  if (VT != MVT::i8 && VT != MVT::i16) {
784  return false;
785  }
786 
787  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
788  return false;
789  }
790 
791  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
792  int RHSC = RHS->getSExtValue();
793  if (Op->getOpcode() == ISD::SUB)
794  RHSC = -RHSC;
795 
796  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
797  return false;
798  }
799 
800  Base = Op->getOperand(0);
801  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
802  AM = ISD::PRE_DEC;
803 
804  return true;
805  }
806 
807  return false;
808 }
809 
810 /// Returns true by value, base pointer and
811 /// offset pointer and addressing mode by reference if this node can be
812 /// combined with a load / store to form a post-indexed load / store.
814  SDValue &Base,
815  SDValue &Offset,
817  SelectionDAG &DAG) const {
818  EVT VT;
819  SDLoc DL(N);
820 
821  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
822  VT = LD->getMemoryVT();
823  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
824  return false;
825  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
826  VT = ST->getMemoryVT();
828  return false;
829  }
830  } else {
831  return false;
832  }
833 
834  if (VT != MVT::i8 && VT != MVT::i16) {
835  return false;
836  }
837 
838  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
839  return false;
840  }
841 
842  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
843  int RHSC = RHS->getSExtValue();
844  if (Op->getOpcode() == ISD::SUB)
845  RHSC = -RHSC;
846  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
847  return false;
848  }
849 
850  Base = Op->getOperand(0);
851  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
852  AM = ISD::POST_INC;
853 
854  return true;
855  }
856 
857  return false;
858 }
859 
861  const GlobalAddressSDNode *GA) const {
862  return true;
863 }
864 
865 //===----------------------------------------------------------------------===//
866 // Formal Arguments Calling Convention Implementation
867 //===----------------------------------------------------------------------===//
868 
869 #include "AVRGenCallingConv.inc"
870 
871 /// For each argument in a function store the number of pieces it is composed
872 /// of.
875  for (const ISD::InputArg &Arg : Ins) {
876  if(Arg.PartOffset > 0) continue;
877  unsigned Bytes = ((Arg.ArgVT.getSizeInBits()) + 7) / 8;
878 
879  Out.push_back((Bytes + 1) / 2);
880  }
881 }
882 
883 /// For external symbols there is no function prototype information so we
884 /// have to rely directly on argument sizes.
887  for (unsigned i = 0, e = In.size(); i != e;) {
888  unsigned Size = 0;
889  unsigned Offset = 0;
890  while ((i != e) && (In[i].PartOffset == Offset)) {
891  Offset += In[i].VT.getStoreSize();
892  ++i;
893  ++Size;
894  }
895  Out.push_back(Size);
896  }
897 }
898 
900  SDValue Callee = CLI.Callee;
901 
902  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
903  return G->getSymbol();
904  }
905 
906  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
907  return G->getGlobal()->getName();
908  }
909 
910  llvm_unreachable("don't know how to get the name for this callee");
911 }
912 
913 /// Analyze incoming and outgoing function arguments. We need custom C++ code
914 /// to handle special constraints in the ABI like reversing the order of the
915 /// pieces of splitted arguments. In addition, all pieces of a certain argument
916 /// have to be passed either using registers or the stack but never mixing both.
918  const Function *F, const DataLayout *TD,
921  CallingConv::ID CallConv,
923  CCState &CCInfo, bool IsCall, bool IsVarArg) {
924  static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
925  AVR::R18, AVR::R16, AVR::R14,
926  AVR::R12, AVR::R10, AVR::R8};
927  static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
928  AVR::R19R18, AVR::R17R16, AVR::R15R14,
929  AVR::R13R12, AVR::R11R10, AVR::R9R8};
930  if (IsVarArg) {
931  // Variadic functions do not need all the analisys below.
932  if (IsCall) {
933  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
934  } else {
935  CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
936  }
937  return;
938  }
939 
940  // Fill in the Args array which will contain original argument sizes.
942  if (IsCall) {
943  parseExternFuncCallArgs(*Outs, Args);
944  } else {
945  assert(F != nullptr && "function should not be null");
946  parseFunctionArgs(*Ins, Args);
947  }
948 
949  unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
950  // Variadic functions always use the stack.
951  bool UsesStack = false;
952  for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
953  unsigned Size = Args[i];
954 
955  // If we have a zero-sized argument, don't attempt to lower it.
956  // AVR-GCC does not support zero-sized arguments and so we need not
957  // worry about ABI compatibility.
958  if (Size == 0) continue;
959 
960  MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
961 
962  // If we have plenty of regs to pass the whole argument do it.
963  if (!UsesStack && (Size <= RegsLeft)) {
964  const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
965 
966  for (unsigned j = 0; j != Size; ++j) {
967  unsigned Reg = CCInfo.AllocateReg(
968  ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
969  CCInfo.addLoc(
970  CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
971  --RegsLeft;
972  }
973 
974  // Reverse the order of the pieces to agree with the "big endian" format
975  // required in the calling convention ABI.
976  std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
977  } else {
978  // Pass the rest of arguments using the stack.
979  UsesStack = true;
980  for (unsigned j = 0; j != Size; ++j) {
981  unsigned Offset = CCInfo.AllocateStack(
982  TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
984  EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
985  CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
987  }
988  }
989  pos += Size;
990  }
991 }
992 
994  const Function *F, const DataLayout *TD,
997  CallingConv::ID CallConv,
999  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1000  StringRef FuncName = getFunctionName(CLI);
1001 
1002  if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
1003  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
1004  } else {
1005  analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1006  CallConv, ArgLocs, CCInfo,
1007  IsCall, IsVarArg);
1008  }
1009 }
1010 
1012  const Function *F, const DataLayout *TD,
1013  const SmallVectorImpl<ISD::OutputArg> *Outs,
1015  CallingConv::ID CallConv,
1017  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1018  switch (CallConv) {
1019  case CallingConv::AVR_BUILTIN: {
1020  analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
1021  CallConv, ArgLocs, CCInfo,
1022  IsCall, IsVarArg);
1023  return;
1024  }
1025  default: {
1026  analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1027  CallConv, ArgLocs, CCInfo,
1028  IsCall, IsVarArg);
1029  return;
1030  }
1031  }
1032 }
1033 
1034 SDValue AVRTargetLowering::LowerFormalArguments(
1035  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1036  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1037  SmallVectorImpl<SDValue> &InVals) const {
1038  MachineFunction &MF = DAG.getMachineFunction();
1039  MachineFrameInfo &MFI = MF.getFrameInfo();
1040  auto DL = DAG.getDataLayout();
1041 
1042  // Assign locations to all of the incoming arguments.
1044  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1045  *DAG.getContext());
1046 
1047  analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1048  false, isVarArg);
1049 
1050  SDValue ArgValue;
1051  for (CCValAssign &VA : ArgLocs) {
1052 
1053  // Arguments stored on registers.
1054  if (VA.isRegLoc()) {
1055  EVT RegVT = VA.getLocVT();
1056  const TargetRegisterClass *RC;
1057  if (RegVT == MVT::i8) {
1058  RC = &AVR::GPR8RegClass;
1059  } else if (RegVT == MVT::i16) {
1060  RC = &AVR::DREGSRegClass;
1061  } else {
1062  llvm_unreachable("Unknown argument type!");
1063  }
1064 
1065  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1066  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1067 
1068  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1069  // following code will handle zexts or sexts generated by other
1070  // front ends. Otherwise:
1071  // If this is an 8 bit value, it is really passed promoted
1072  // to 16 bits. Insert an assert[sz]ext to capture this, then
1073  // truncate to the right size.
1074  switch (VA.getLocInfo()) {
1075  default:
1076  llvm_unreachable("Unknown loc info!");
1077  case CCValAssign::Full:
1078  break;
1079  case CCValAssign::BCvt:
1080  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1081  break;
1082  case CCValAssign::SExt:
1083  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1084  DAG.getValueType(VA.getValVT()));
1085  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1086  break;
1087  case CCValAssign::ZExt:
1088  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1089  DAG.getValueType(VA.getValVT()));
1090  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1091  break;
1092  }
1093 
1094  InVals.push_back(ArgValue);
1095  } else {
1096  // Sanity check.
1097  assert(VA.isMemLoc());
1098 
1099  EVT LocVT = VA.getLocVT();
1100 
1101  // Create the frame index object for this incoming parameter.
1102  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1103  VA.getLocMemOffset(), true);
1104 
1105  // Create the SelectionDAG nodes corresponding to a load
1106  // from this parameter.
1107  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1108  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1110  0));
1111  }
1112  }
1113 
1114  // If the function takes variable number of arguments, make a frame index for
1115  // the start of the first vararg value... for expansion of llvm.va_start.
1116  if (isVarArg) {
1117  unsigned StackSize = CCInfo.getNextStackOffset();
1119 
1120  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1121  }
1122 
1123  return Chain;
1124 }
1125 
1126 //===----------------------------------------------------------------------===//
1127 // Call Calling Convention Implementation
1128 //===----------------------------------------------------------------------===//
1129 
1130 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1131  SmallVectorImpl<SDValue> &InVals) const {
1132  SelectionDAG &DAG = CLI.DAG;
1133  SDLoc &DL = CLI.DL;
1135  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1137  SDValue Chain = CLI.Chain;
1138  SDValue Callee = CLI.Callee;
1139  bool &isTailCall = CLI.IsTailCall;
1140  CallingConv::ID CallConv = CLI.CallConv;
1141  bool isVarArg = CLI.IsVarArg;
1142 
1143  MachineFunction &MF = DAG.getMachineFunction();
1144 
1145  // AVR does not yet support tail call optimization.
1146  isTailCall = false;
1147 
1148  // Analyze operands of the call, assigning locations to each operand.
1150  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1151  *DAG.getContext());
1152 
1153  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1154  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1155  // node so that legalize doesn't hack it.
1156  const Function *F = nullptr;
1157  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1158  const GlobalValue *GV = G->getGlobal();
1159 
1160  F = cast<Function>(GV);
1161  Callee =
1163  } else if (const ExternalSymbolSDNode *ES =
1164  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1165  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1166  getPointerTy(DAG.getDataLayout()));
1167  }
1168 
1169  analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1170  true, isVarArg);
1171 
1172  // Get a count of how many bytes are to be pushed on the stack.
1173  unsigned NumBytes = CCInfo.getNextStackOffset();
1174 
1175  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1176 
1178 
1179  // First, walk the register assignments, inserting copies.
1180  unsigned AI, AE;
1181  bool HasStackArgs = false;
1182  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1183  CCValAssign &VA = ArgLocs[AI];
1184  EVT RegVT = VA.getLocVT();
1185  SDValue Arg = OutVals[AI];
1186 
1187  // Promote the value if needed. With Clang this should not happen.
1188  switch (VA.getLocInfo()) {
1189  default:
1190  llvm_unreachable("Unknown loc info!");
1191  case CCValAssign::Full:
1192  break;
1193  case CCValAssign::SExt:
1194  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1195  break;
1196  case CCValAssign::ZExt:
1197  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1198  break;
1199  case CCValAssign::AExt:
1200  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1201  break;
1202  case CCValAssign::BCvt:
1203  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1204  break;
1205  }
1206 
1207  // Stop when we encounter a stack argument, we need to process them
1208  // in reverse order in the loop below.
1209  if (VA.isMemLoc()) {
1210  HasStackArgs = true;
1211  break;
1212  }
1213 
1214  // Arguments that can be passed on registers must be kept in the RegsToPass
1215  // vector.
1216  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1217  }
1218 
1219  // Second, stack arguments have to walked in reverse order by inserting
1220  // chained stores, this ensures their order is not changed by the scheduler
1221  // and that the push instruction sequence generated is correct, otherwise they
1222  // can be freely intermixed.
1223  if (HasStackArgs) {
1224  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1225  unsigned Loc = AI - 1;
1226  CCValAssign &VA = ArgLocs[Loc];
1227  SDValue Arg = OutVals[Loc];
1228 
1229  assert(VA.isMemLoc());
1230 
1231  // SP points to one stack slot further so add one to adjust it.
1232  SDValue PtrOff = DAG.getNode(
1233  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1234  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1235  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1236 
1237  Chain =
1238  DAG.getStore(Chain, DL, Arg, PtrOff,
1240  0);
1241  }
1242  }
1243 
1244  // Build a sequence of copy-to-reg nodes chained together with token chain and
1245  // flag operands which copy the outgoing args into registers. The InFlag in
1246  // necessary since all emited instructions must be stuck together.
1247  SDValue InFlag;
1248  for (auto Reg : RegsToPass) {
1249  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1250  InFlag = Chain.getValue(1);
1251  }
1252 
1253  // Returns a chain & a flag for retval copy to use.
1254  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1256  Ops.push_back(Chain);
1257  Ops.push_back(Callee);
1258 
1259  // Add argument registers to the end of the list so that they are known live
1260  // into the call.
1261  for (auto Reg : RegsToPass) {
1262  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1263  }
1264 
1265  // Add a register mask operand representing the call-preserved registers.
1266  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1268  const uint32_t *Mask =
1269  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1270  assert(Mask && "Missing call preserved mask for calling convention");
1271  Ops.push_back(DAG.getRegisterMask(Mask));
1272 
1273  if (InFlag.getNode()) {
1274  Ops.push_back(InFlag);
1275  }
1276 
1277  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1278  InFlag = Chain.getValue(1);
1279 
1280  // Create the CALLSEQ_END node.
1281  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1282  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1283 
1284  if (!Ins.empty()) {
1285  InFlag = Chain.getValue(1);
1286  }
1287 
1288  // Handle result values, copying them out of physregs into vregs that we
1289  // return.
1290  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1291  InVals);
1292 }
1293 
1294 /// Lower the result values of a call into the
1295 /// appropriate copies out of appropriate physical registers.
1296 ///
1297 SDValue AVRTargetLowering::LowerCallResult(
1298  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1299  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1300  SmallVectorImpl<SDValue> &InVals) const {
1301 
1302  // Assign locations to each value returned by this call.
1304  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1305  *DAG.getContext());
1306 
1307  // Handle runtime calling convs.
1308  auto CCFunction = CCAssignFnForReturn(CallConv);
1309  CCInfo.AnalyzeCallResult(Ins, CCFunction);
1310 
1311  if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1312  // Reverse splitted return values to get the "big endian" format required
1313  // to agree with the calling convention ABI.
1314  std::reverse(RVLocs.begin(), RVLocs.end());
1315  }
1316 
1317  // Copy all of the result registers out of their specified physreg.
1318  for (CCValAssign const &RVLoc : RVLocs) {
1319  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1320  InFlag)
1321  .getValue(1);
1322  InFlag = Chain.getValue(2);
1323  InVals.push_back(Chain.getValue(0));
1324  }
1325 
1326  return Chain;
1327 }
1328 
1329 //===----------------------------------------------------------------------===//
1330 // Return Value Calling Convention Implementation
1331 //===----------------------------------------------------------------------===//
1332 
1333 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1334  switch (CC) {
1336  return RetCC_AVR_BUILTIN;
1337  default:
1338  return RetCC_AVR;
1339  }
1340 }
1341 
1342 bool
1343 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1344  MachineFunction &MF, bool isVarArg,
1345  const SmallVectorImpl<ISD::OutputArg> &Outs,
1346  LLVMContext &Context) const
1347 {
1349  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1350 
1351  auto CCFunction = CCAssignFnForReturn(CallConv);
1352  return CCInfo.CheckReturn(Outs, CCFunction);
1353 }
1354 
1355 SDValue
1356 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1357  bool isVarArg,
1358  const SmallVectorImpl<ISD::OutputArg> &Outs,
1359  const SmallVectorImpl<SDValue> &OutVals,
1360  const SDLoc &dl, SelectionDAG &DAG) const {
1361  // CCValAssign - represent the assignment of the return value to locations.
1363 
1364  // CCState - Info about the registers and stack slot.
1365  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1366  *DAG.getContext());
1367 
1368  // Analyze return values.
1369  auto CCFunction = CCAssignFnForReturn(CallConv);
1370  CCInfo.AnalyzeReturn(Outs, CCFunction);
1371 
1372  // If this is the first return lowered for this function, add the regs to
1373  // the liveout set for the function.
1374  MachineFunction &MF = DAG.getMachineFunction();
1375  unsigned e = RVLocs.size();
1376 
1377  // Reverse splitted return values to get the "big endian" format required
1378  // to agree with the calling convention ABI.
1379  if (e > 1) {
1380  std::reverse(RVLocs.begin(), RVLocs.end());
1381  }
1382 
1383  SDValue Flag;
1384  SmallVector<SDValue, 4> RetOps(1, Chain);
1385  // Copy the result values into the output registers.
1386  for (unsigned i = 0; i != e; ++i) {
1387  CCValAssign &VA = RVLocs[i];
1388  assert(VA.isRegLoc() && "Can only return in registers!");
1389 
1390  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1391 
1392  // Guarantee that all emitted copies are stuck together with flags.
1393  Flag = Chain.getValue(1);
1394  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1395  }
1396 
1397  // Don't emit the ret/reti instruction when the naked attribute is present in
1398  // the function being compiled.
1400  AttributeList::FunctionIndex, Attribute::Naked)) {
1401  return Chain;
1402  }
1403 
1404  unsigned RetOpc =
1405  (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1407  : AVRISD::RET_FLAG;
1408 
1409  RetOps[0] = Chain; // Update chain.
1410 
1411  if (Flag.getNode()) {
1412  RetOps.push_back(Flag);
1413  }
1414 
1415  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1416 }
1417 
1418 //===----------------------------------------------------------------------===//
1419 // Custom Inserters
1420 //===----------------------------------------------------------------------===//
1421 
1422 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1423  MachineBasicBlock *BB) const {
1424  unsigned Opc;
1425  const TargetRegisterClass *RC;
1426  MachineFunction *F = BB->getParent();
1427  MachineRegisterInfo &RI = F->getRegInfo();
1428  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1430  DebugLoc dl = MI.getDebugLoc();
1431 
1432  switch (MI.getOpcode()) {
1433  default:
1434  llvm_unreachable("Invalid shift opcode!");
1435  case AVR::Lsl8:
1436  Opc = AVR::LSLRd;
1437  RC = &AVR::GPR8RegClass;
1438  break;
1439  case AVR::Lsl16:
1440  Opc = AVR::LSLWRd;
1441  RC = &AVR::DREGSRegClass;
1442  break;
1443  case AVR::Asr8:
1444  Opc = AVR::ASRRd;
1445  RC = &AVR::GPR8RegClass;
1446  break;
1447  case AVR::Asr16:
1448  Opc = AVR::ASRWRd;
1449  RC = &AVR::DREGSRegClass;
1450  break;
1451  case AVR::Lsr8:
1452  Opc = AVR::LSRRd;
1453  RC = &AVR::GPR8RegClass;
1454  break;
1455  case AVR::Lsr16:
1456  Opc = AVR::LSRWRd;
1457  RC = &AVR::DREGSRegClass;
1458  break;
1459  case AVR::Rol8:
1460  Opc = AVR::ROLRd;
1461  RC = &AVR::GPR8RegClass;
1462  break;
1463  case AVR::Rol16:
1464  Opc = AVR::ROLWRd;
1465  RC = &AVR::DREGSRegClass;
1466  break;
1467  case AVR::Ror8:
1468  Opc = AVR::RORRd;
1469  RC = &AVR::GPR8RegClass;
1470  break;
1471  case AVR::Ror16:
1472  Opc = AVR::RORWRd;
1473  RC = &AVR::DREGSRegClass;
1474  break;
1475  }
1476 
1477  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1478 
1480  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1481  if (I != F->end()) ++I;
1482 
1483  // Create loop block.
1484  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1485  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1486 
1487  F->insert(I, LoopBB);
1488  F->insert(I, RemBB);
1489 
1490  // Update machine-CFG edges by transferring all successors of the current
1491  // block to the block containing instructions after shift.
1492  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1493  BB->end());
1495 
1496  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1497  BB->addSuccessor(LoopBB);
1498  BB->addSuccessor(RemBB);
1499  LoopBB->addSuccessor(RemBB);
1500  LoopBB->addSuccessor(LoopBB);
1501 
1502  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1503  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1504  unsigned ShiftReg = RI.createVirtualRegister(RC);
1505  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1506  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1507  unsigned SrcReg = MI.getOperand(1).getReg();
1508  unsigned DstReg = MI.getOperand(0).getReg();
1509 
1510  // BB:
1511  // cpi N, 0
1512  // breq RemBB
1513  BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1514  BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1515 
1516  // LoopBB:
1517  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1518  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1519  // ShiftReg2 = shift ShiftReg
1520  // ShiftAmt2 = ShiftAmt - 1;
1521  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1522  .addReg(SrcReg)
1523  .addMBB(BB)
1524  .addReg(ShiftReg2)
1525  .addMBB(LoopBB);
1526  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1527  .addReg(ShiftAmtSrcReg)
1528  .addMBB(BB)
1529  .addReg(ShiftAmtReg2)
1530  .addMBB(LoopBB);
1531  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1532  BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1533  .addReg(ShiftAmtReg)
1534  .addImm(1);
1535  BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1536 
1537  // RemBB:
1538  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1539  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1540  .addReg(SrcReg)
1541  .addMBB(BB)
1542  .addReg(ShiftReg2)
1543  .addMBB(LoopBB);
1544 
1545  MI.eraseFromParent(); // The pseudo instruction is gone now.
1546  return RemBB;
1547 }
1548 
1550  if (I->getOpcode() == AVR::COPY) {
1551  unsigned SrcReg = I->getOperand(1).getReg();
1552  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1553  }
1554 
1555  return false;
1556 }
1557 
1558 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1559 // after the result has been evacuated. This is probably not the best way to do
1560 // it, but it works for now.
1561 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1562  MachineBasicBlock *BB) const {
1563  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1566  ++I; // in any case insert *after* the mul instruction
1567  if (isCopyMulResult(I))
1568  ++I;
1569  if (isCopyMulResult(I))
1570  ++I;
1571  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1572  .addReg(AVR::R1)
1573  .addReg(AVR::R1);
1574  return BB;
1575 }
1576 
1579  MachineBasicBlock *MBB) const {
1580  int Opc = MI.getOpcode();
1581 
1582  // Pseudo shift instructions with a non constant shift amount are expanded
1583  // into a loop.
1584  switch (Opc) {
1585  case AVR::Lsl8:
1586  case AVR::Lsl16:
1587  case AVR::Lsr8:
1588  case AVR::Lsr16:
1589  case AVR::Rol8:
1590  case AVR::Rol16:
1591  case AVR::Ror8:
1592  case AVR::Ror16:
1593  case AVR::Asr8:
1594  case AVR::Asr16:
1595  return insertShift(MI, MBB);
1596  case AVR::MULRdRr:
1597  case AVR::MULSRdRr:
1598  return insertMul(MI, MBB);
1599  }
1600 
1601  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1602  "Unexpected instr type to insert");
1603 
1604  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1605  ->getParent()
1606  ->getSubtarget()
1607  .getInstrInfo();
1608  DebugLoc dl = MI.getDebugLoc();
1609 
1610  // To "insert" a SELECT instruction, we insert the diamond
1611  // control-flow pattern. The incoming instruction knows the
1612  // destination vreg to set, the condition code register to branch
1613  // on, the true/false values to select between, and a branch opcode
1614  // to use.
1615 
1616  MachineFunction *MF = MBB->getParent();
1617  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1618  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1619  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1620 
1622  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1623  if (I != MF->end()) ++I;
1624  MF->insert(I, trueMBB);
1625  MF->insert(I, falseMBB);
1626 
1627  // Transfer remaining instructions and all successors of the current
1628  // block to the block which will contain the Phi node for the
1629  // select.
1630  trueMBB->splice(trueMBB->begin(), MBB,
1631  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1632  trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1633 
1635  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1636  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1637  MBB->addSuccessor(falseMBB);
1638  MBB->addSuccessor(trueMBB);
1639 
1640  // Unconditionally flow back to the true block
1641  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1642  falseMBB->addSuccessor(trueMBB);
1643 
1644  // Set up the Phi node to determine where we came from
1645  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1646  .addReg(MI.getOperand(1).getReg())
1647  .addMBB(MBB)
1648  .addReg(MI.getOperand(2).getReg())
1649  .addMBB(falseMBB) ;
1650 
1651  MI.eraseFromParent(); // The pseudo instruction is gone now.
1652  return trueMBB;
1653 }
1654 
1655 //===----------------------------------------------------------------------===//
1656 // Inline Asm Support
1657 //===----------------------------------------------------------------------===//
1658 
1661  if (Constraint.size() == 1) {
1662  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1663  switch (Constraint[0]) {
1664  case 'a': // Simple upper registers
1665  case 'b': // Base pointer registers pairs
1666  case 'd': // Upper register
1667  case 'l': // Lower registers
1668  case 'e': // Pointer register pairs
1669  case 'q': // Stack pointer register
1670  case 'r': // Any register
1671  case 'w': // Special upper register pairs
1672  return C_RegisterClass;
1673  case 't': // Temporary register
1674  case 'x': case 'X': // Pointer register pair X
1675  case 'y': case 'Y': // Pointer register pair Y
1676  case 'z': case 'Z': // Pointer register pair Z
1677  return C_Register;
1678  case 'Q': // A memory address based on Y or Z pointer with displacement.
1679  return C_Memory;
1680  case 'G': // Floating point constant
1681  case 'I': // 6-bit positive integer constant
1682  case 'J': // 6-bit negative integer constant
1683  case 'K': // Integer constant (Range: 2)
1684  case 'L': // Integer constant (Range: 0)
1685  case 'M': // 8-bit integer constant
1686  case 'N': // Integer constant (Range: -1)
1687  case 'O': // Integer constant (Range: 8, 16, 24)
1688  case 'P': // Integer constant (Range: 1)
1689  case 'R': // Integer constant (Range: -6 to 5)x
1690  return C_Other;
1691  default:
1692  break;
1693  }
1694  }
1695 
1696  return TargetLowering::getConstraintType(Constraint);
1697 }
1698 
1699 unsigned
1701  // Not sure if this is actually the right thing to do, but we got to do
1702  // *something* [agnat]
1703  switch (ConstraintCode[0]) {
1704  case 'Q':
1705  return InlineAsm::Constraint_Q;
1706  }
1707  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1708 }
1709 
1712  AsmOperandInfo &info, const char *constraint) const {
1713  ConstraintWeight weight = CW_Invalid;
1714  Value *CallOperandVal = info.CallOperandVal;
1715 
1716  // If we don't have a value, we can't do a match,
1717  // but allow it at the lowest weight.
1718  // (this behaviour has been copied from the ARM backend)
1719  if (!CallOperandVal) {
1720  return CW_Default;
1721  }
1722 
1723  // Look at the constraint type.
1724  switch (*constraint) {
1725  default:
1726  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1727  break;
1728  case 'd':
1729  case 'r':
1730  case 'l':
1731  weight = CW_Register;
1732  break;
1733  case 'a':
1734  case 'b':
1735  case 'e':
1736  case 'q':
1737  case 't':
1738  case 'w':
1739  case 'x': case 'X':
1740  case 'y': case 'Y':
1741  case 'z': case 'Z':
1742  weight = CW_SpecificReg;
1743  break;
1744  case 'G':
1745  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1746  if (C->isZero()) {
1747  weight = CW_Constant;
1748  }
1749  }
1750  break;
1751  case 'I':
1752  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1753  if (isUInt<6>(C->getZExtValue())) {
1754  weight = CW_Constant;
1755  }
1756  }
1757  break;
1758  case 'J':
1759  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1760  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1761  weight = CW_Constant;
1762  }
1763  }
1764  break;
1765  case 'K':
1766  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1767  if (C->getZExtValue() == 2) {
1768  weight = CW_Constant;
1769  }
1770  }
1771  break;
1772  case 'L':
1773  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1774  if (C->getZExtValue() == 0) {
1775  weight = CW_Constant;
1776  }
1777  }
1778  break;
1779  case 'M':
1780  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1781  if (isUInt<8>(C->getZExtValue())) {
1782  weight = CW_Constant;
1783  }
1784  }
1785  break;
1786  case 'N':
1787  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1788  if (C->getSExtValue() == -1) {
1789  weight = CW_Constant;
1790  }
1791  }
1792  break;
1793  case 'O':
1794  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1795  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1796  (C->getZExtValue() == 24)) {
1797  weight = CW_Constant;
1798  }
1799  }
1800  break;
1801  case 'P':
1802  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1803  if (C->getZExtValue() == 1) {
1804  weight = CW_Constant;
1805  }
1806  }
1807  break;
1808  case 'R':
1809  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1810  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1811  weight = CW_Constant;
1812  }
1813  }
1814  break;
1815  case 'Q':
1816  weight = CW_Memory;
1817  break;
1818  }
1819 
1820  return weight;
1821 }
1822 
1823 std::pair<unsigned, const TargetRegisterClass *>
1825  StringRef Constraint,
1826  MVT VT) const {
1827  auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine())
1828  .getSubtargetImpl();
1829 
1830  // We only support i8 and i16.
1831  //
1832  //:FIXME: remove this assert for now since it gets sometimes executed
1833  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1834 
1835  if (Constraint.size() == 1) {
1836  switch (Constraint[0]) {
1837  case 'a': // Simple upper registers r16..r23.
1838  return std::make_pair(0U, &AVR::LD8loRegClass);
1839  case 'b': // Base pointer registers: y, z.
1840  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1841  case 'd': // Upper registers r16..r31.
1842  return std::make_pair(0U, &AVR::LD8RegClass);
1843  case 'l': // Lower registers r0..r15.
1844  return std::make_pair(0U, &AVR::GPR8loRegClass);
1845  case 'e': // Pointer register pairs: x, y, z.
1846  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1847  case 'q': // Stack pointer register: SPH:SPL.
1848  return std::make_pair(0U, &AVR::GPRSPRegClass);
1849  case 'r': // Any register: r0..r31.
1850  if (VT == MVT::i8)
1851  return std::make_pair(0U, &AVR::GPR8RegClass);
1852 
1853  assert(VT == MVT::i16 && "inline asm constraint too large");
1854  return std::make_pair(0U, &AVR::DREGSRegClass);
1855  case 't': // Temporary register: r0.
1856  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1857  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1858  return std::make_pair(0U, &AVR::IWREGSRegClass);
1859  case 'x': // Pointer register pair X: r27:r26.
1860  case 'X':
1861  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1862  case 'y': // Pointer register pair Y: r29:r28.
1863  case 'Y':
1864  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1865  case 'z': // Pointer register pair Z: r31:r30.
1866  case 'Z':
1867  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1868  default:
1869  break;
1870  }
1871  }
1872 
1873  return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(),
1874  Constraint, VT);
1875 }
1876 
1878  std::string &Constraint,
1879  std::vector<SDValue> &Ops,
1880  SelectionDAG &DAG) const {
1881  SDValue Result(0, 0);
1882  SDLoc DL(Op);
1883  EVT Ty = Op.getValueType();
1884 
1885  // Currently only support length 1 constraints.
1886  if (Constraint.length() != 1) {
1887  return;
1888  }
1889 
1890  char ConstraintLetter = Constraint[0];
1891  switch (ConstraintLetter) {
1892  default:
1893  break;
1894  // Deal with integers first:
1895  case 'I':
1896  case 'J':
1897  case 'K':
1898  case 'L':
1899  case 'M':
1900  case 'N':
1901  case 'O':
1902  case 'P':
1903  case 'R': {
1905  if (!C) {
1906  return;
1907  }
1908 
1909  int64_t CVal64 = C->getSExtValue();
1910  uint64_t CUVal64 = C->getZExtValue();
1911  switch (ConstraintLetter) {
1912  case 'I': // 0..63
1913  if (!isUInt<6>(CUVal64))
1914  return;
1915  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1916  break;
1917  case 'J': // -63..0
1918  if (CVal64 < -63 || CVal64 > 0)
1919  return;
1920  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1921  break;
1922  case 'K': // 2
1923  if (CUVal64 != 2)
1924  return;
1925  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1926  break;
1927  case 'L': // 0
1928  if (CUVal64 != 0)
1929  return;
1930  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1931  break;
1932  case 'M': // 0..255
1933  if (!isUInt<8>(CUVal64))
1934  return;
1935  // i8 type may be printed as a negative number,
1936  // e.g. 254 would be printed as -2,
1937  // so we force it to i16 at least.
1938  if (Ty.getSimpleVT() == MVT::i8) {
1939  Ty = MVT::i16;
1940  }
1941  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1942  break;
1943  case 'N': // -1
1944  if (CVal64 != -1)
1945  return;
1946  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1947  break;
1948  case 'O': // 8, 16, 24
1949  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1950  return;
1951  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1952  break;
1953  case 'P': // 1
1954  if (CUVal64 != 1)
1955  return;
1956  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1957  break;
1958  case 'R': // -6..5
1959  if (CVal64 < -6 || CVal64 > 5)
1960  return;
1961  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1962  break;
1963  }
1964 
1965  break;
1966  }
1967  case 'G':
1969  if (!FC || !FC->isZero())
1970  return;
1971  // Soften float to i8 0
1972  Result = DAG.getTargetConstant(0, DL, MVT::i8);
1973  break;
1974  }
1975 
1976  if (Result.getNode()) {
1977  Ops.push_back(Result);
1978  return;
1979  }
1980 
1981  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1982 }
1983 
1984 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
1985  EVT VT,
1986  SelectionDAG &DAG) const {
1987  unsigned Reg;
1988 
1989  if (VT == MVT::i8) {
1990  Reg = StringSwitch<unsigned>(RegName)
1991  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1992  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1993  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1994  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1995  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1996  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1997  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1998  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1999  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2000  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2001  .Case("r30", AVR::R30).Case("r31", AVR::R31)
2002  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2003  .Default(0);
2004  } else {
2005  Reg = StringSwitch<unsigned>(RegName)
2006  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2007  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2008  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2009  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2010  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2011  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2012  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2013  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2014  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2015  .Default(0);
2016  }
2017 
2018  if (Reg)
2019  return Reg;
2020 
2021  report_fatal_error("Invalid register name global variable");
2022 }
2023 
2024 } // end of namespace llvm
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:539
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
#define R4(n)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:611
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:285
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Unsigned lower.
Definition: AVRInstrInfo.h:38
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:660
unsigned Reg
static void parseFunctionArgs(const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Test for zero or minus instruction.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:34
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
#define R2(n)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
SDValue getExternalSymbol(const char *Sym, EVT VT)
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
const AVRSubtarget * getSubtargetImpl() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:426
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:836
Represents an abstract call instruction, which includes a bunch of information.
A loop of single right bit rotate instructions.
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:380
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:48
CallLoweringInfo & setChain(SDValue InChain)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:771
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:311
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:398
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(T Value)
Definition: StringSwitch.h:203
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:336
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:656
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:237
int64_t getSExtValue() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
A generic AVR implementation.
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
Return from subroutine.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
SmallVector< ISD::OutputArg, 32 > Outs
CallLoweringInfo & setZExtResult(bool Value=true)
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:210
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:911
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:571
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
amdgpu Simplify well known AMD library false Value * Callee
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
TargetInstrInfo - Interface to description of machine instruction set.
bool isZero() const
Return true if the value is positive or negative zero.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:343
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
Contains AVR-specific information for each MachineFunction.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
Unsigned same or higher.
Definition: AVRInstrInfo.h:37
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:689
iterator_range< value_op_iterator > op_values() const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:117
const SDValue & getOperand(unsigned Num) const
LLVMContext & getContext() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:837
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
self_iterator getIterator()
Definition: ilist_node.h:82
AVR conditional branches.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:680
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:32
lazy value info
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:757
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
Calling convention used for AVR signal routines.
Definition: CallingConv.h:180
AVRTargetLowering(AVRTargetMachine &TM)
Compare instruction.
Used for AVR interrupt routines.
Definition: CallingConv.h:177
A loop of single logical shift right instructions.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
#define R6(n)
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
#define NODE(name)
CCValAssign - Represent assignment of one arg/retval to a location.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
A loop of single left bit rotate instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:605
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:383
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
Return from ISR.
int64_t getImm() const
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:184
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:674
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:438
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:441
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
amdgpu Simplify well known AMD library false Value Value * Arg
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:156
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
Bit rotate left.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:428
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:599
Representation of each machine instruction.
Definition: MachineInstr.h:60
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:685
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:668
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:121
SmallVector< SDValue, 32 > OutVals
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:700
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:62
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:456
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Logical shift right.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
Arithmetic shift right.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
CallLoweringInfo & setInRegister(bool Value=true)
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
Greater than or equal.
Definition: AVRInstrInfo.h:35
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:46
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:413
Conversion operators.
Definition: ISDOpcodes.h:435
const SDValue & getOperand(unsigned i) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
uint64_t getZExtValue() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:444
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
LLVMContext * getContext() const
Definition: SelectionDAG.h:404
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:866
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:356
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:584