LLVM  10.0.0svn
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/IR/Function.h"
25 
26 #include "AVR.h"
27 #include "AVRMachineFunctionInfo.h"
28 #include "AVRSubtarget.h"
29 #include "AVRTargetMachine.h"
31 
32 namespace llvm {
33 
35  const AVRSubtarget &STI)
36  : TargetLowering(TM), Subtarget(STI) {
37  // Set up the register classes.
38  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
39  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
40 
41  // Compute derived properties from the register classes.
43 
49 
52 
57 
58  for (MVT VT : MVT::integer_valuetypes()) {
59  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
62  }
63  }
64 
66 
67  for (MVT VT : MVT::integer_valuetypes()) {
72  }
73 
74  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
75  // revert into a sub since we don't have an add with immediate instruction.
78 
79  // our shift instructions are only able to shift 1 bit at a time, so handle
80  // this in a custom way.
90 
95 
101 
112 
114 
115  // Add support for postincrement and predecrement load/stores.
124 
126 
131 
132  // Atomic operations which must be lowered to rtlib calls
133  for (MVT VT : MVT::integer_valuetypes()) {
141  }
142 
143  // Division/remainder
152 
153  // Make division and modulus custom
154  for (MVT VT : MVT::integer_valuetypes()) {
157  }
158 
159  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
162 
163  // Expand 16 bit multiplications.
166 
167  // Expand multiplications to libcalls when there is
168  // no hardware MUL.
172  }
173 
174  for (MVT VT : MVT::integer_valuetypes()) {
177  }
178 
179  for (MVT VT : MVT::integer_valuetypes()) {
183  }
184 
185  for (MVT VT : MVT::integer_valuetypes()) {
187  // TODO: The generated code is pretty poor. Investigate using the
188  // same "shift and subtract with carry" trick that we do for
189  // extending 8-bit to 16-bit. This may require infrastructure
190  // improvements in how we treat 16-bit "registers" to be feasible.
191  }
192 
193  // Division rtlib functions (not supported)
194  setLibcallName(RTLIB::SDIV_I8, nullptr);
195  setLibcallName(RTLIB::SDIV_I16, nullptr);
196  setLibcallName(RTLIB::SDIV_I32, nullptr);
197  setLibcallName(RTLIB::SDIV_I64, nullptr);
198  setLibcallName(RTLIB::SDIV_I128, nullptr);
199  setLibcallName(RTLIB::UDIV_I8, nullptr);
200  setLibcallName(RTLIB::UDIV_I16, nullptr);
201  setLibcallName(RTLIB::UDIV_I32, nullptr);
202  setLibcallName(RTLIB::UDIV_I64, nullptr);
203  setLibcallName(RTLIB::UDIV_I128, nullptr);
204 
205  // Modulus rtlib functions (not supported)
206  setLibcallName(RTLIB::SREM_I8, nullptr);
207  setLibcallName(RTLIB::SREM_I16, nullptr);
208  setLibcallName(RTLIB::SREM_I32, nullptr);
209  setLibcallName(RTLIB::SREM_I64, nullptr);
210  setLibcallName(RTLIB::SREM_I128, nullptr);
211  setLibcallName(RTLIB::UREM_I8, nullptr);
212  setLibcallName(RTLIB::UREM_I16, nullptr);
213  setLibcallName(RTLIB::UREM_I32, nullptr);
214  setLibcallName(RTLIB::UREM_I64, nullptr);
215  setLibcallName(RTLIB::UREM_I128, nullptr);
216 
217  // Division and modulus rtlib functions
218  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
219  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
220  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
221  setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
222  setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
223  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
224  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
225  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
226  setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
227  setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
228 
229  // Several of the runtime library functions use a special calling conv
231  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
233  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
234 
235  // Trigonometric rtlib functions
236  setLibcallName(RTLIB::SIN_F32, "sin");
237  setLibcallName(RTLIB::COS_F32, "cos");
238 
240  setMinimumJumpTableEntries(UINT_MAX);
241 }
242 
243 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
244 #define NODE(name) \
245  case AVRISD::name: \
246  return #name
247 
248  switch (Opcode) {
249  default:
250  return nullptr;
251  NODE(RET_FLAG);
252  NODE(RETI_FLAG);
253  NODE(CALL);
254  NODE(WRAPPER);
255  NODE(LSL);
256  NODE(LSR);
257  NODE(ROL);
258  NODE(ROR);
259  NODE(ASR);
260  NODE(LSLLOOP);
261  NODE(LSRLOOP);
262  NODE(ASRLOOP);
263  NODE(BRCOND);
264  NODE(CMP);
265  NODE(CMPC);
266  NODE(TST);
267  NODE(SELECT_CC);
268 #undef NODE
269  }
270 }
271 
273  EVT VT) const {
274  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
275  return MVT::i8;
276 }
277 
278 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
279  //:TODO: this function has to be completely rewritten to produce optimal
280  // code, for now it's producing very long but correct code.
281  unsigned Opc8;
282  const SDNode *N = Op.getNode();
283  EVT VT = Op.getValueType();
284  SDLoc dl(N);
285 
286  // Expand non-constant shifts to loops.
287  if (!isa<ConstantSDNode>(N->getOperand(1))) {
288  switch (Op.getOpcode()) {
289  default:
290  llvm_unreachable("Invalid shift opcode!");
291  case ISD::SHL:
292  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
293  N->getOperand(1));
294  case ISD::SRL:
295  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
296  N->getOperand(1));
297  case ISD::ROTL:
298  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
299  N->getOperand(1));
300  case ISD::ROTR:
301  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
302  N->getOperand(1));
303  case ISD::SRA:
304  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
305  N->getOperand(1));
306  }
307  }
308 
309  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
310  SDValue Victim = N->getOperand(0);
311 
312  switch (Op.getOpcode()) {
313  case ISD::SRA:
314  Opc8 = AVRISD::ASR;
315  break;
316  case ISD::ROTL:
317  Opc8 = AVRISD::ROL;
318  break;
319  case ISD::ROTR:
320  Opc8 = AVRISD::ROR;
321  break;
322  case ISD::SRL:
323  Opc8 = AVRISD::LSR;
324  break;
325  case ISD::SHL:
326  Opc8 = AVRISD::LSL;
327  break;
328  default:
329  llvm_unreachable("Invalid shift opcode");
330  }
331 
332  while (ShiftAmount--) {
333  Victim = DAG.getNode(Opc8, dl, VT, Victim);
334  }
335 
336  return Victim;
337 }
338 
339 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
340  unsigned Opcode = Op->getOpcode();
341  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
342  "Invalid opcode for Div/Rem lowering");
343  bool IsSigned = (Opcode == ISD::SDIVREM);
344  EVT VT = Op->getValueType(0);
345  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
346 
347  RTLIB::Libcall LC;
348  switch (VT.getSimpleVT().SimpleTy) {
349  default:
350  llvm_unreachable("Unexpected request for libcall!");
351  case MVT::i8:
352  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
353  break;
354  case MVT::i16:
355  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
356  break;
357  case MVT::i32:
358  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
359  break;
360  case MVT::i64:
361  LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
362  break;
363  case MVT::i128:
364  LC = IsSigned ? RTLIB::SDIVREM_I128 : RTLIB::UDIVREM_I128;
365  break;
366  }
367 
368  SDValue InChain = DAG.getEntryNode();
369 
372  for (SDValue const &Value : Op->op_values()) {
373  Entry.Node = Value;
374  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
375  Entry.IsSExt = IsSigned;
376  Entry.IsZExt = !IsSigned;
377  Args.push_back(Entry);
378  }
379 
381  getPointerTy(DAG.getDataLayout()));
382 
383  Type *RetTy = (Type *)StructType::get(Ty, Ty);
384 
385  SDLoc dl(Op);
387  CLI.setDebugLoc(dl)
388  .setChain(InChain)
389  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
390  .setInRegister()
391  .setSExtResult(IsSigned)
392  .setZExtResult(!IsSigned);
393 
394  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
395  return CallInfo.first;
396 }
397 
398 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
399  SelectionDAG &DAG) const {
400  auto DL = DAG.getDataLayout();
401 
402  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
403  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
404 
405  // Create the TargetGlobalAddress node, folding in the constant offset.
406  SDValue Result =
407  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
408  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
409 }
410 
411 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
412  SelectionDAG &DAG) const {
413  auto DL = DAG.getDataLayout();
414  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
415 
416  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
417 
418  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
419 }
420 
421 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
423  switch (CC) {
424  default:
425  llvm_unreachable("Unknown condition code!");
426  case ISD::SETEQ:
427  return AVRCC::COND_EQ;
428  case ISD::SETNE:
429  return AVRCC::COND_NE;
430  case ISD::SETGE:
431  return AVRCC::COND_GE;
432  case ISD::SETLT:
433  return AVRCC::COND_LT;
434  case ISD::SETUGE:
435  return AVRCC::COND_SH;
436  case ISD::SETULT:
437  return AVRCC::COND_LO;
438  }
439 }
440 
441 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
442 /// the given operands.
443 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
444  SDValue &AVRcc, SelectionDAG &DAG,
445  SDLoc DL) const {
446  SDValue Cmp;
447  EVT VT = LHS.getValueType();
448  bool UseTest = false;
449 
450  switch (CC) {
451  default:
452  break;
453  case ISD::SETLE: {
454  // Swap operands and reverse the branching condition.
455  std::swap(LHS, RHS);
456  CC = ISD::SETGE;
457  break;
458  }
459  case ISD::SETGT: {
460  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
461  switch (C->getSExtValue()) {
462  case -1: {
463  // When doing lhs > -1 use a tst instruction on the top part of lhs
464  // and use brpl instead of using a chain of cp/cpc.
465  UseTest = true;
466  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
467  break;
468  }
469  case 0: {
470  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
471  // __zero_reg__ in lhs.
472  RHS = LHS;
473  LHS = DAG.getConstant(0, DL, VT);
474  CC = ISD::SETLT;
475  break;
476  }
477  default: {
478  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
479  // us to fold the constant into the cmp instruction.
480  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
481  CC = ISD::SETGE;
482  break;
483  }
484  }
485  break;
486  }
487  // Swap operands and reverse the branching condition.
488  std::swap(LHS, RHS);
489  CC = ISD::SETLT;
490  break;
491  }
492  case ISD::SETLT: {
493  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
494  switch (C->getSExtValue()) {
495  case 1: {
496  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
497  // __zero_reg__ in lhs.
498  RHS = LHS;
499  LHS = DAG.getConstant(0, DL, VT);
500  CC = ISD::SETGE;
501  break;
502  }
503  case 0: {
504  // When doing lhs < 0 use a tst instruction on the top part of lhs
505  // and use brmi instead of using a chain of cp/cpc.
506  UseTest = true;
507  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
508  break;
509  }
510  }
511  }
512  break;
513  }
514  case ISD::SETULE: {
515  // Swap operands and reverse the branching condition.
516  std::swap(LHS, RHS);
517  CC = ISD::SETUGE;
518  break;
519  }
520  case ISD::SETUGT: {
521  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
522  // fold the constant into the cmp instruction.
523  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
524  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
525  CC = ISD::SETUGE;
526  break;
527  }
528  // Swap operands and reverse the branching condition.
529  std::swap(LHS, RHS);
530  CC = ISD::SETULT;
531  break;
532  }
533  }
534 
535  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
536  // using the default and/or/xor expansion code which is much longer.
537  if (VT == MVT::i32) {
538  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
539  DAG.getIntPtrConstant(0, DL));
540  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
541  DAG.getIntPtrConstant(1, DL));
542  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
543  DAG.getIntPtrConstant(0, DL));
544  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
545  DAG.getIntPtrConstant(1, DL));
546 
547  if (UseTest) {
548  // When using tst we only care about the highest part.
549  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
550  DAG.getIntPtrConstant(1, DL));
551  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
552  } else {
553  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
554  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
555  }
556  } else if (VT == MVT::i64) {
557  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
558  DAG.getIntPtrConstant(0, DL));
559  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
560  DAG.getIntPtrConstant(1, DL));
561 
562  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
563  DAG.getIntPtrConstant(0, DL));
564  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
565  DAG.getIntPtrConstant(1, DL));
566  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
567  DAG.getIntPtrConstant(0, DL));
568  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
569  DAG.getIntPtrConstant(1, DL));
570 
571  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
572  DAG.getIntPtrConstant(0, DL));
573  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
574  DAG.getIntPtrConstant(1, DL));
575 
576  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
577  DAG.getIntPtrConstant(0, DL));
578  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
579  DAG.getIntPtrConstant(1, DL));
580  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
581  DAG.getIntPtrConstant(0, DL));
582  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
583  DAG.getIntPtrConstant(1, DL));
584 
585  if (UseTest) {
586  // When using tst we only care about the highest part.
587  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
588  DAG.getIntPtrConstant(1, DL));
589  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
590  } else {
591  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
592  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
593  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
594  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
595  }
596  } else if (VT == MVT::i8 || VT == MVT::i16) {
597  if (UseTest) {
598  // When using tst we only care about the highest part.
599  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
600  (VT == MVT::i8)
601  ? LHS
603  LHS, DAG.getIntPtrConstant(1, DL)));
604  } else {
605  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
606  }
607  } else {
608  llvm_unreachable("Invalid comparison size");
609  }
610 
611  // When using a test instruction AVRcc is already set.
612  if (!UseTest) {
613  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
614  }
615 
616  return Cmp;
617 }
618 
619 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
620  SDValue Chain = Op.getOperand(0);
621  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
622  SDValue LHS = Op.getOperand(2);
623  SDValue RHS = Op.getOperand(3);
624  SDValue Dest = Op.getOperand(4);
625  SDLoc dl(Op);
626 
627  SDValue TargetCC;
628  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
629 
630  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
631  Cmp);
632 }
633 
634 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
635  SDValue LHS = Op.getOperand(0);
636  SDValue RHS = Op.getOperand(1);
637  SDValue TrueV = Op.getOperand(2);
638  SDValue FalseV = Op.getOperand(3);
639  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
640  SDLoc dl(Op);
641 
642  SDValue TargetCC;
643  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
644 
645  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
646  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
647 
648  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
649 }
650 
651 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
652  SDValue LHS = Op.getOperand(0);
653  SDValue RHS = Op.getOperand(1);
654  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
655  SDLoc DL(Op);
656 
657  SDValue TargetCC;
658  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
659 
660  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
661  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
662  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
663  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
664 
665  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
666 }
667 
668 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
669  const MachineFunction &MF = DAG.getMachineFunction();
671  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
672  auto DL = DAG.getDataLayout();
673  SDLoc dl(Op);
674 
675  // Vastart just stores the address of the VarArgsFrameIndex slot into the
676  // memory location argument.
678 
679  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
680  MachinePointerInfo(SV), 0);
681 }
682 
684  switch (Op.getOpcode()) {
685  default:
686  llvm_unreachable("Don't know how to custom lower this!");
687  case ISD::SHL:
688  case ISD::SRA:
689  case ISD::SRL:
690  case ISD::ROTL:
691  case ISD::ROTR:
692  return LowerShifts(Op, DAG);
693  case ISD::GlobalAddress:
694  return LowerGlobalAddress(Op, DAG);
695  case ISD::BlockAddress:
696  return LowerBlockAddress(Op, DAG);
697  case ISD::BR_CC:
698  return LowerBR_CC(Op, DAG);
699  case ISD::SELECT_CC:
700  return LowerSELECT_CC(Op, DAG);
701  case ISD::SETCC:
702  return LowerSETCC(Op, DAG);
703  case ISD::VASTART:
704  return LowerVASTART(Op, DAG);
705  case ISD::SDIVREM:
706  case ISD::UDIVREM:
707  return LowerDivRem(Op, DAG);
708  }
709 
710  return SDValue();
711 }
712 
713 /// Replace a node with an illegal result type
714 /// with a new node built out of custom code.
717  SelectionDAG &DAG) const {
718  SDLoc DL(N);
719 
720  switch (N->getOpcode()) {
721  case ISD::ADD: {
722  // Convert add (x, imm) into sub (x, -imm).
723  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
724  SDValue Sub = DAG.getNode(
725  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
726  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
727  Results.push_back(Sub);
728  }
729  break;
730  }
731  default: {
732  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
733 
734  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
735  Results.push_back(Res.getValue(I));
736 
737  break;
738  }
739  }
740 }
741 
742 /// Return true if the addressing mode represented
743 /// by AM is legal for this target, for a load/store of the specified type.
745  const AddrMode &AM, Type *Ty,
746  unsigned AS, Instruction *I) const {
747  int64_t Offs = AM.BaseOffs;
748 
749  // Allow absolute addresses.
750  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
751  return true;
752  }
753 
754  // Flash memory instructions only allow zero offsets.
755  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
756  return false;
757  }
758 
759  // Allow reg+<6bit> offset.
760  if (Offs < 0)
761  Offs = -Offs;
762  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
763  return true;
764  }
765 
766  return false;
767 }
768 
769 /// Returns true by value, base pointer and
770 /// offset pointer and addressing mode by reference if the node's address
771 /// can be legally represented as pre-indexed load / store address.
773  SDValue &Offset,
775  SelectionDAG &DAG) const {
776  EVT VT;
777  const SDNode *Op;
778  SDLoc DL(N);
779 
780  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
781  VT = LD->getMemoryVT();
782  Op = LD->getBasePtr().getNode();
783  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
784  return false;
786  return false;
787  }
788  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
789  VT = ST->getMemoryVT();
790  Op = ST->getBasePtr().getNode();
792  return false;
793  }
794  } else {
795  return false;
796  }
797 
798  if (VT != MVT::i8 && VT != MVT::i16) {
799  return false;
800  }
801 
802  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
803  return false;
804  }
805 
806  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
807  int RHSC = RHS->getSExtValue();
808  if (Op->getOpcode() == ISD::SUB)
809  RHSC = -RHSC;
810 
811  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
812  return false;
813  }
814 
815  Base = Op->getOperand(0);
816  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
817  AM = ISD::PRE_DEC;
818 
819  return true;
820  }
821 
822  return false;
823 }
824 
825 /// Returns true by value, base pointer and
826 /// offset pointer and addressing mode by reference if this node can be
827 /// combined with a load / store to form a post-indexed load / store.
829  SDValue &Base,
830  SDValue &Offset,
832  SelectionDAG &DAG) const {
833  EVT VT;
834  SDLoc DL(N);
835 
836  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
837  VT = LD->getMemoryVT();
838  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
839  return false;
840  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
841  VT = ST->getMemoryVT();
843  return false;
844  }
845  } else {
846  return false;
847  }
848 
849  if (VT != MVT::i8 && VT != MVT::i16) {
850  return false;
851  }
852 
853  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
854  return false;
855  }
856 
857  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
858  int RHSC = RHS->getSExtValue();
859  if (Op->getOpcode() == ISD::SUB)
860  RHSC = -RHSC;
861  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
862  return false;
863  }
864 
865  Base = Op->getOperand(0);
866  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
867  AM = ISD::POST_INC;
868 
869  return true;
870  }
871 
872  return false;
873 }
874 
876  const GlobalAddressSDNode *GA) const {
877  return true;
878 }
879 
880 //===----------------------------------------------------------------------===//
881 // Formal Arguments Calling Convention Implementation
882 //===----------------------------------------------------------------------===//
883 
884 #include "AVRGenCallingConv.inc"
885 
886 /// For each argument in a function store the number of pieces it is composed
887 /// of.
890  for (const ISD::InputArg &Arg : Ins) {
891  if(Arg.PartOffset > 0) continue;
892  unsigned Bytes = ((Arg.ArgVT.getSizeInBits()) + 7) / 8;
893 
894  Out.push_back((Bytes + 1) / 2);
895  }
896 }
897 
898 /// For external symbols there is no function prototype information so we
899 /// have to rely directly on argument sizes.
902  for (unsigned i = 0, e = In.size(); i != e;) {
903  unsigned Size = 0;
904  unsigned Offset = 0;
905  while ((i != e) && (In[i].PartOffset == Offset)) {
906  Offset += In[i].VT.getStoreSize();
907  ++i;
908  ++Size;
909  }
910  Out.push_back(Size);
911  }
912 }
913 
915  SDValue Callee = CLI.Callee;
916 
917  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
918  return G->getSymbol();
919  }
920 
921  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
922  return G->getGlobal()->getName();
923  }
924 
925  llvm_unreachable("don't know how to get the name for this callee");
926 }
927 
928 /// Analyze incoming and outgoing function arguments. We need custom C++ code
929 /// to handle special constraints in the ABI like reversing the order of the
930 /// pieces of splitted arguments. In addition, all pieces of a certain argument
931 /// have to be passed either using registers or the stack but never mixing both.
933  const Function *F, const DataLayout *TD,
936  CallingConv::ID CallConv,
938  CCState &CCInfo, bool IsCall, bool IsVarArg) {
939  static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
940  AVR::R18, AVR::R16, AVR::R14,
941  AVR::R12, AVR::R10, AVR::R8};
942  static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
943  AVR::R19R18, AVR::R17R16, AVR::R15R14,
944  AVR::R13R12, AVR::R11R10, AVR::R9R8};
945  if (IsVarArg) {
946  // Variadic functions do not need all the analysis below.
947  if (IsCall) {
948  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
949  } else {
950  CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
951  }
952  return;
953  }
954 
955  // Fill in the Args array which will contain original argument sizes.
957  if (IsCall) {
958  parseExternFuncCallArgs(*Outs, Args);
959  } else {
960  assert(F != nullptr && "function should not be null");
961  parseFunctionArgs(*Ins, Args);
962  }
963 
964  unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
965  // Variadic functions always use the stack.
966  bool UsesStack = false;
967  for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
968  unsigned Size = Args[i];
969 
970  // If we have a zero-sized argument, don't attempt to lower it.
971  // AVR-GCC does not support zero-sized arguments and so we need not
972  // worry about ABI compatibility.
973  if (Size == 0) continue;
974 
975  MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
976 
977  // If we have plenty of regs to pass the whole argument do it.
978  if (!UsesStack && (Size <= RegsLeft)) {
979  const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
980 
981  for (unsigned j = 0; j != Size; ++j) {
982  unsigned Reg = CCInfo.AllocateReg(
983  ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
984  CCInfo.addLoc(
985  CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
986  --RegsLeft;
987  }
988 
989  // Reverse the order of the pieces to agree with the "big endian" format
990  // required in the calling convention ABI.
991  std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
992  } else {
993  // Pass the rest of arguments using the stack.
994  UsesStack = true;
995  for (unsigned j = 0; j != Size; ++j) {
996  unsigned Offset = CCInfo.AllocateStack(
997  TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
999  EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
1000  CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
1002  }
1003  }
1004  pos += Size;
1005  }
1006 }
1007 
1009  const Function *F, const DataLayout *TD,
1010  const SmallVectorImpl<ISD::OutputArg> *Outs,
1012  CallingConv::ID CallConv,
1014  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1015  StringRef FuncName = getFunctionName(CLI);
1016 
1017  if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
1018  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
1019  } else {
1020  analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
1021  CallConv, ArgLocs, CCInfo,
1022  IsCall, IsVarArg);
1023  }
1024 }
1025 
1027  const Function *F, const DataLayout *TD,
1028  const SmallVectorImpl<ISD::OutputArg> *Outs,
1030  CallingConv::ID CallConv,
1032  CCState &CCInfo, bool IsCall, bool IsVarArg) {
1033  switch (CallConv) {
1034  case CallingConv::AVR_BUILTIN: {
1035  analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
1036  CallConv, ArgLocs, CCInfo,
1037  IsCall, IsVarArg);
1038  return;
1039  }
1040  default: {
1041  analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1042  CallConv, ArgLocs, CCInfo,
1043  IsCall, IsVarArg);
1044  return;
1045  }
1046  }
1047 }
1048 
1049 SDValue AVRTargetLowering::LowerFormalArguments(
1050  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1051  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1052  SmallVectorImpl<SDValue> &InVals) const {
1053  MachineFunction &MF = DAG.getMachineFunction();
1054  MachineFrameInfo &MFI = MF.getFrameInfo();
1055  auto DL = DAG.getDataLayout();
1056 
1057  // Assign locations to all of the incoming arguments.
1059  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1060  *DAG.getContext());
1061 
1062  analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1063  false, isVarArg);
1064 
1065  SDValue ArgValue;
1066  for (CCValAssign &VA : ArgLocs) {
1067 
1068  // Arguments stored on registers.
1069  if (VA.isRegLoc()) {
1070  EVT RegVT = VA.getLocVT();
1071  const TargetRegisterClass *RC;
1072  if (RegVT == MVT::i8) {
1073  RC = &AVR::GPR8RegClass;
1074  } else if (RegVT == MVT::i16) {
1075  RC = &AVR::DREGSRegClass;
1076  } else {
1077  llvm_unreachable("Unknown argument type!");
1078  }
1079 
1080  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1081  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1082 
1083  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1084  // following code will handle zexts or sexts generated by other
1085  // front ends. Otherwise:
1086  // If this is an 8 bit value, it is really passed promoted
1087  // to 16 bits. Insert an assert[sz]ext to capture this, then
1088  // truncate to the right size.
1089  switch (VA.getLocInfo()) {
1090  default:
1091  llvm_unreachable("Unknown loc info!");
1092  case CCValAssign::Full:
1093  break;
1094  case CCValAssign::BCvt:
1095  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1096  break;
1097  case CCValAssign::SExt:
1098  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1099  DAG.getValueType(VA.getValVT()));
1100  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1101  break;
1102  case CCValAssign::ZExt:
1103  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1104  DAG.getValueType(VA.getValVT()));
1105  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1106  break;
1107  }
1108 
1109  InVals.push_back(ArgValue);
1110  } else {
1111  // Sanity check.
1112  assert(VA.isMemLoc());
1113 
1114  EVT LocVT = VA.getLocVT();
1115 
1116  // Create the frame index object for this incoming parameter.
1117  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1118  VA.getLocMemOffset(), true);
1119 
1120  // Create the SelectionDAG nodes corresponding to a load
1121  // from this parameter.
1122  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1123  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1125  0));
1126  }
1127  }
1128 
1129  // If the function takes variable number of arguments, make a frame index for
1130  // the start of the first vararg value... for expansion of llvm.va_start.
1131  if (isVarArg) {
1132  unsigned StackSize = CCInfo.getNextStackOffset();
1134 
1135  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1136  }
1137 
1138  return Chain;
1139 }
1140 
1141 //===----------------------------------------------------------------------===//
1142 // Call Calling Convention Implementation
1143 //===----------------------------------------------------------------------===//
1144 
1145 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1146  SmallVectorImpl<SDValue> &InVals) const {
1147  SelectionDAG &DAG = CLI.DAG;
1148  SDLoc &DL = CLI.DL;
1150  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1152  SDValue Chain = CLI.Chain;
1153  SDValue Callee = CLI.Callee;
1154  bool &isTailCall = CLI.IsTailCall;
1155  CallingConv::ID CallConv = CLI.CallConv;
1156  bool isVarArg = CLI.IsVarArg;
1157 
1158  MachineFunction &MF = DAG.getMachineFunction();
1159 
1160  // AVR does not yet support tail call optimization.
1161  isTailCall = false;
1162 
1163  // Analyze operands of the call, assigning locations to each operand.
1165  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1166  *DAG.getContext());
1167 
1168  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1169  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1170  // node so that legalize doesn't hack it.
1171  const Function *F = nullptr;
1172  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1173  const GlobalValue *GV = G->getGlobal();
1174 
1175  F = cast<Function>(GV);
1176  Callee =
1178  } else if (const ExternalSymbolSDNode *ES =
1179  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1180  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1181  getPointerTy(DAG.getDataLayout()));
1182  }
1183 
1184  analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1185  true, isVarArg);
1186 
1187  // Get a count of how many bytes are to be pushed on the stack.
1188  unsigned NumBytes = CCInfo.getNextStackOffset();
1189 
1190  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1191 
1193 
1194  // First, walk the register assignments, inserting copies.
1195  unsigned AI, AE;
1196  bool HasStackArgs = false;
1197  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1198  CCValAssign &VA = ArgLocs[AI];
1199  EVT RegVT = VA.getLocVT();
1200  SDValue Arg = OutVals[AI];
1201 
1202  // Promote the value if needed. With Clang this should not happen.
1203  switch (VA.getLocInfo()) {
1204  default:
1205  llvm_unreachable("Unknown loc info!");
1206  case CCValAssign::Full:
1207  break;
1208  case CCValAssign::SExt:
1209  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1210  break;
1211  case CCValAssign::ZExt:
1212  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1213  break;
1214  case CCValAssign::AExt:
1215  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1216  break;
1217  case CCValAssign::BCvt:
1218  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1219  break;
1220  }
1221 
1222  // Stop when we encounter a stack argument, we need to process them
1223  // in reverse order in the loop below.
1224  if (VA.isMemLoc()) {
1225  HasStackArgs = true;
1226  break;
1227  }
1228 
1229  // Arguments that can be passed on registers must be kept in the RegsToPass
1230  // vector.
1231  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1232  }
1233 
1234  // Second, stack arguments have to walked in reverse order by inserting
1235  // chained stores, this ensures their order is not changed by the scheduler
1236  // and that the push instruction sequence generated is correct, otherwise they
1237  // can be freely intermixed.
1238  if (HasStackArgs) {
1239  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1240  unsigned Loc = AI - 1;
1241  CCValAssign &VA = ArgLocs[Loc];
1242  SDValue Arg = OutVals[Loc];
1243 
1244  assert(VA.isMemLoc());
1245 
1246  // SP points to one stack slot further so add one to adjust it.
1247  SDValue PtrOff = DAG.getNode(
1248  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1249  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1250  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1251 
1252  Chain =
1253  DAG.getStore(Chain, DL, Arg, PtrOff,
1255  0);
1256  }
1257  }
1258 
1259  // Build a sequence of copy-to-reg nodes chained together with token chain and
1260  // flag operands which copy the outgoing args into registers. The InFlag in
1261  // necessary since all emited instructions must be stuck together.
1262  SDValue InFlag;
1263  for (auto Reg : RegsToPass) {
1264  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1265  InFlag = Chain.getValue(1);
1266  }
1267 
1268  // Returns a chain & a flag for retval copy to use.
1269  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1271  Ops.push_back(Chain);
1272  Ops.push_back(Callee);
1273 
1274  // Add argument registers to the end of the list so that they are known live
1275  // into the call.
1276  for (auto Reg : RegsToPass) {
1277  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1278  }
1279 
1280  // Add a register mask operand representing the call-preserved registers.
1282  const uint32_t *Mask =
1283  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1284  assert(Mask && "Missing call preserved mask for calling convention");
1285  Ops.push_back(DAG.getRegisterMask(Mask));
1286 
1287  if (InFlag.getNode()) {
1288  Ops.push_back(InFlag);
1289  }
1290 
1291  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1292  InFlag = Chain.getValue(1);
1293 
1294  // Create the CALLSEQ_END node.
1295  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1296  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1297 
1298  if (!Ins.empty()) {
1299  InFlag = Chain.getValue(1);
1300  }
1301 
1302  // Handle result values, copying them out of physregs into vregs that we
1303  // return.
1304  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1305  InVals);
1306 }
1307 
1308 /// Lower the result values of a call into the
1309 /// appropriate copies out of appropriate physical registers.
1310 ///
1311 SDValue AVRTargetLowering::LowerCallResult(
1312  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1313  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1314  SmallVectorImpl<SDValue> &InVals) const {
1315 
1316  // Assign locations to each value returned by this call.
1318  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1319  *DAG.getContext());
1320 
1321  // Handle runtime calling convs.
1322  auto CCFunction = CCAssignFnForReturn(CallConv);
1323  CCInfo.AnalyzeCallResult(Ins, CCFunction);
1324 
1325  if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1326  // Reverse splitted return values to get the "big endian" format required
1327  // to agree with the calling convention ABI.
1328  std::reverse(RVLocs.begin(), RVLocs.end());
1329  }
1330 
1331  // Copy all of the result registers out of their specified physreg.
1332  for (CCValAssign const &RVLoc : RVLocs) {
1333  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1334  InFlag)
1335  .getValue(1);
1336  InFlag = Chain.getValue(2);
1337  InVals.push_back(Chain.getValue(0));
1338  }
1339 
1340  return Chain;
1341 }
1342 
1343 //===----------------------------------------------------------------------===//
1344 // Return Value Calling Convention Implementation
1345 //===----------------------------------------------------------------------===//
1346 
1347 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1348  switch (CC) {
1350  return RetCC_AVR_BUILTIN;
1351  default:
1352  return RetCC_AVR;
1353  }
1354 }
1355 
1356 bool
1357 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1358  MachineFunction &MF, bool isVarArg,
1359  const SmallVectorImpl<ISD::OutputArg> &Outs,
1360  LLVMContext &Context) const
1361 {
1363  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1364 
1365  auto CCFunction = CCAssignFnForReturn(CallConv);
1366  return CCInfo.CheckReturn(Outs, CCFunction);
1367 }
1368 
1369 SDValue
1370 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1371  bool isVarArg,
1372  const SmallVectorImpl<ISD::OutputArg> &Outs,
1373  const SmallVectorImpl<SDValue> &OutVals,
1374  const SDLoc &dl, SelectionDAG &DAG) const {
1375  // CCValAssign - represent the assignment of the return value to locations.
1377 
1378  // CCState - Info about the registers and stack slot.
1379  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1380  *DAG.getContext());
1381 
1382  // Analyze return values.
1383  auto CCFunction = CCAssignFnForReturn(CallConv);
1384  CCInfo.AnalyzeReturn(Outs, CCFunction);
1385 
1386  // If this is the first return lowered for this function, add the regs to
1387  // the liveout set for the function.
1388  MachineFunction &MF = DAG.getMachineFunction();
1389  unsigned e = RVLocs.size();
1390 
1391  // Reverse splitted return values to get the "big endian" format required
1392  // to agree with the calling convention ABI.
1393  if (e > 1) {
1394  std::reverse(RVLocs.begin(), RVLocs.end());
1395  }
1396 
1397  SDValue Flag;
1398  SmallVector<SDValue, 4> RetOps(1, Chain);
1399  // Copy the result values into the output registers.
1400  for (unsigned i = 0; i != e; ++i) {
1401  CCValAssign &VA = RVLocs[i];
1402  assert(VA.isRegLoc() && "Can only return in registers!");
1403 
1404  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1405 
1406  // Guarantee that all emitted copies are stuck together with flags.
1407  Flag = Chain.getValue(1);
1408  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1409  }
1410 
1411  // Don't emit the ret/reti instruction when the naked attribute is present in
1412  // the function being compiled.
1414  AttributeList::FunctionIndex, Attribute::Naked)) {
1415  return Chain;
1416  }
1417 
1418  unsigned RetOpc =
1419  (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1421  : AVRISD::RET_FLAG;
1422 
1423  RetOps[0] = Chain; // Update chain.
1424 
1425  if (Flag.getNode()) {
1426  RetOps.push_back(Flag);
1427  }
1428 
1429  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1430 }
1431 
1432 //===----------------------------------------------------------------------===//
1433 // Custom Inserters
1434 //===----------------------------------------------------------------------===//
1435 
1436 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1437  MachineBasicBlock *BB) const {
1438  unsigned Opc;
1439  const TargetRegisterClass *RC;
1440  bool HasRepeatedOperand = false;
1441  MachineFunction *F = BB->getParent();
1442  MachineRegisterInfo &RI = F->getRegInfo();
1444  DebugLoc dl = MI.getDebugLoc();
1445 
1446  switch (MI.getOpcode()) {
1447  default:
1448  llvm_unreachable("Invalid shift opcode!");
1449  case AVR::Lsl8:
1450  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1451  RC = &AVR::GPR8RegClass;
1452  HasRepeatedOperand = true;
1453  break;
1454  case AVR::Lsl16:
1455  Opc = AVR::LSLWRd;
1456  RC = &AVR::DREGSRegClass;
1457  break;
1458  case AVR::Asr8:
1459  Opc = AVR::ASRRd;
1460  RC = &AVR::GPR8RegClass;
1461  break;
1462  case AVR::Asr16:
1463  Opc = AVR::ASRWRd;
1464  RC = &AVR::DREGSRegClass;
1465  break;
1466  case AVR::Lsr8:
1467  Opc = AVR::LSRRd;
1468  RC = &AVR::GPR8RegClass;
1469  break;
1470  case AVR::Lsr16:
1471  Opc = AVR::LSRWRd;
1472  RC = &AVR::DREGSRegClass;
1473  break;
1474  case AVR::Rol8:
1475  Opc = AVR::ADCRdRr; // ROL is an alias of ADC Rd, Rd
1476  RC = &AVR::GPR8RegClass;
1477  HasRepeatedOperand = true;
1478  break;
1479  case AVR::Rol16:
1480  Opc = AVR::ROLWRd;
1481  RC = &AVR::DREGSRegClass;
1482  break;
1483  case AVR::Ror8:
1484  Opc = AVR::RORRd;
1485  RC = &AVR::GPR8RegClass;
1486  break;
1487  case AVR::Ror16:
1488  Opc = AVR::RORWRd;
1489  RC = &AVR::DREGSRegClass;
1490  break;
1491  }
1492 
1493  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1494 
1496  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I);
1497  if (I != F->end()) ++I;
1498 
1499  // Create loop block.
1500  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1501  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1502 
1503  F->insert(I, LoopBB);
1504  F->insert(I, RemBB);
1505 
1506  // Update machine-CFG edges by transferring all successors of the current
1507  // block to the block containing instructions after shift.
1508  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1509  BB->end());
1511 
1512  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1513  BB->addSuccessor(LoopBB);
1514  BB->addSuccessor(RemBB);
1515  LoopBB->addSuccessor(RemBB);
1516  LoopBB->addSuccessor(LoopBB);
1517 
1518  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1519  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1520  unsigned ShiftReg = RI.createVirtualRegister(RC);
1521  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1522  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1523  unsigned SrcReg = MI.getOperand(1).getReg();
1524  unsigned DstReg = MI.getOperand(0).getReg();
1525 
1526  // BB:
1527  // cpi N, 0
1528  // breq RemBB
1529  BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1530  BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1531 
1532  // LoopBB:
1533  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1534  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1535  // ShiftReg2 = shift ShiftReg
1536  // ShiftAmt2 = ShiftAmt - 1;
1537  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1538  .addReg(SrcReg)
1539  .addMBB(BB)
1540  .addReg(ShiftReg2)
1541  .addMBB(LoopBB);
1542  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1543  .addReg(ShiftAmtSrcReg)
1544  .addMBB(BB)
1545  .addReg(ShiftAmtReg2)
1546  .addMBB(LoopBB);
1547 
1548  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1549  if (HasRepeatedOperand)
1550  ShiftMI.addReg(ShiftReg);
1551 
1552  BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1553  .addReg(ShiftAmtReg)
1554  .addImm(1);
1555  BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1556 
1557  // RemBB:
1558  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1559  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1560  .addReg(SrcReg)
1561  .addMBB(BB)
1562  .addReg(ShiftReg2)
1563  .addMBB(LoopBB);
1564 
1565  MI.eraseFromParent(); // The pseudo instruction is gone now.
1566  return RemBB;
1567 }
1568 
1570  if (I->getOpcode() == AVR::COPY) {
1571  unsigned SrcReg = I->getOperand(1).getReg();
1572  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1573  }
1574 
1575  return false;
1576 }
1577 
1578 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1579 // after the result has been evacuated. This is probably not the best way to do
1580 // it, but it works for now.
1581 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1582  MachineBasicBlock *BB) const {
1585  ++I; // in any case insert *after* the mul instruction
1586  if (isCopyMulResult(I))
1587  ++I;
1588  if (isCopyMulResult(I))
1589  ++I;
1590  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1591  .addReg(AVR::R1)
1592  .addReg(AVR::R1);
1593  return BB;
1594 }
1595 
1598  MachineBasicBlock *MBB) const {
1599  int Opc = MI.getOpcode();
1600 
1601  // Pseudo shift instructions with a non constant shift amount are expanded
1602  // into a loop.
1603  switch (Opc) {
1604  case AVR::Lsl8:
1605  case AVR::Lsl16:
1606  case AVR::Lsr8:
1607  case AVR::Lsr16:
1608  case AVR::Rol8:
1609  case AVR::Rol16:
1610  case AVR::Ror8:
1611  case AVR::Ror16:
1612  case AVR::Asr8:
1613  case AVR::Asr16:
1614  return insertShift(MI, MBB);
1615  case AVR::MULRdRr:
1616  case AVR::MULSRdRr:
1617  return insertMul(MI, MBB);
1618  }
1619 
1620  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1621  "Unexpected instr type to insert");
1622 
1623  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1624  ->getParent()
1625  ->getSubtarget()
1626  .getInstrInfo();
1627  DebugLoc dl = MI.getDebugLoc();
1628 
1629  // To "insert" a SELECT instruction, we insert the diamond
1630  // control-flow pattern. The incoming instruction knows the
1631  // destination vreg to set, the condition code register to branch
1632  // on, the true/false values to select between, and a branch opcode
1633  // to use.
1634 
1635  MachineFunction *MF = MBB->getParent();
1636  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1637  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1638 
1639  // If the current basic block falls through to another basic block,
1640  // we must insert an unconditional branch to the fallthrough destination
1641  // if we are to insert basic blocks at the prior fallthrough point.
1642  if (FallThrough != nullptr) {
1643  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1644  }
1645 
1646  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1647  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1648 
1650  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I);
1651  if (I != MF->end()) ++I;
1652  MF->insert(I, trueMBB);
1653  MF->insert(I, falseMBB);
1654 
1655  // Transfer remaining instructions and all successors of the current
1656  // block to the block which will contain the Phi node for the
1657  // select.
1658  trueMBB->splice(trueMBB->begin(), MBB,
1659  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1660  trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1661 
1663  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1664  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1665  MBB->addSuccessor(falseMBB);
1666  MBB->addSuccessor(trueMBB);
1667 
1668  // Unconditionally flow back to the true block
1669  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1670  falseMBB->addSuccessor(trueMBB);
1671 
1672  // Set up the Phi node to determine where we came from
1673  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1674  .addReg(MI.getOperand(1).getReg())
1675  .addMBB(MBB)
1676  .addReg(MI.getOperand(2).getReg())
1677  .addMBB(falseMBB) ;
1678 
1679  MI.eraseFromParent(); // The pseudo instruction is gone now.
1680  return trueMBB;
1681 }
1682 
1683 //===----------------------------------------------------------------------===//
1684 // Inline Asm Support
1685 //===----------------------------------------------------------------------===//
1686 
1689  if (Constraint.size() == 1) {
1690  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1691  switch (Constraint[0]) {
1692  case 'a': // Simple upper registers
1693  case 'b': // Base pointer registers pairs
1694  case 'd': // Upper register
1695  case 'l': // Lower registers
1696  case 'e': // Pointer register pairs
1697  case 'q': // Stack pointer register
1698  case 'r': // Any register
1699  case 'w': // Special upper register pairs
1700  return C_RegisterClass;
1701  case 't': // Temporary register
1702  case 'x': case 'X': // Pointer register pair X
1703  case 'y': case 'Y': // Pointer register pair Y
1704  case 'z': case 'Z': // Pointer register pair Z
1705  return C_Register;
1706  case 'Q': // A memory address based on Y or Z pointer with displacement.
1707  return C_Memory;
1708  case 'G': // Floating point constant
1709  case 'I': // 6-bit positive integer constant
1710  case 'J': // 6-bit negative integer constant
1711  case 'K': // Integer constant (Range: 2)
1712  case 'L': // Integer constant (Range: 0)
1713  case 'M': // 8-bit integer constant
1714  case 'N': // Integer constant (Range: -1)
1715  case 'O': // Integer constant (Range: 8, 16, 24)
1716  case 'P': // Integer constant (Range: 1)
1717  case 'R': // Integer constant (Range: -6 to 5)x
1718  return C_Other;
1719  default:
1720  break;
1721  }
1722  }
1723 
1724  return TargetLowering::getConstraintType(Constraint);
1725 }
1726 
1727 unsigned
1729  // Not sure if this is actually the right thing to do, but we got to do
1730  // *something* [agnat]
1731  switch (ConstraintCode[0]) {
1732  case 'Q':
1733  return InlineAsm::Constraint_Q;
1734  }
1735  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1736 }
1737 
1740  AsmOperandInfo &info, const char *constraint) const {
1741  ConstraintWeight weight = CW_Invalid;
1742  Value *CallOperandVal = info.CallOperandVal;
1743 
1744  // If we don't have a value, we can't do a match,
1745  // but allow it at the lowest weight.
1746  // (this behaviour has been copied from the ARM backend)
1747  if (!CallOperandVal) {
1748  return CW_Default;
1749  }
1750 
1751  // Look at the constraint type.
1752  switch (*constraint) {
1753  default:
1754  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1755  break;
1756  case 'd':
1757  case 'r':
1758  case 'l':
1759  weight = CW_Register;
1760  break;
1761  case 'a':
1762  case 'b':
1763  case 'e':
1764  case 'q':
1765  case 't':
1766  case 'w':
1767  case 'x': case 'X':
1768  case 'y': case 'Y':
1769  case 'z': case 'Z':
1770  weight = CW_SpecificReg;
1771  break;
1772  case 'G':
1773  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1774  if (C->isZero()) {
1775  weight = CW_Constant;
1776  }
1777  }
1778  break;
1779  case 'I':
1780  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1781  if (isUInt<6>(C->getZExtValue())) {
1782  weight = CW_Constant;
1783  }
1784  }
1785  break;
1786  case 'J':
1787  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1788  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1789  weight = CW_Constant;
1790  }
1791  }
1792  break;
1793  case 'K':
1794  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1795  if (C->getZExtValue() == 2) {
1796  weight = CW_Constant;
1797  }
1798  }
1799  break;
1800  case 'L':
1801  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1802  if (C->getZExtValue() == 0) {
1803  weight = CW_Constant;
1804  }
1805  }
1806  break;
1807  case 'M':
1808  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1809  if (isUInt<8>(C->getZExtValue())) {
1810  weight = CW_Constant;
1811  }
1812  }
1813  break;
1814  case 'N':
1815  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1816  if (C->getSExtValue() == -1) {
1817  weight = CW_Constant;
1818  }
1819  }
1820  break;
1821  case 'O':
1822  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1823  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1824  (C->getZExtValue() == 24)) {
1825  weight = CW_Constant;
1826  }
1827  }
1828  break;
1829  case 'P':
1830  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1831  if (C->getZExtValue() == 1) {
1832  weight = CW_Constant;
1833  }
1834  }
1835  break;
1836  case 'R':
1837  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1838  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1839  weight = CW_Constant;
1840  }
1841  }
1842  break;
1843  case 'Q':
1844  weight = CW_Memory;
1845  break;
1846  }
1847 
1848  return weight;
1849 }
1850 
1851 std::pair<unsigned, const TargetRegisterClass *>
1853  StringRef Constraint,
1854  MVT VT) const {
1855  // We only support i8 and i16.
1856  //
1857  //:FIXME: remove this assert for now since it gets sometimes executed
1858  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1859 
1860  if (Constraint.size() == 1) {
1861  switch (Constraint[0]) {
1862  case 'a': // Simple upper registers r16..r23.
1863  return std::make_pair(0U, &AVR::LD8loRegClass);
1864  case 'b': // Base pointer registers: y, z.
1865  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1866  case 'd': // Upper registers r16..r31.
1867  return std::make_pair(0U, &AVR::LD8RegClass);
1868  case 'l': // Lower registers r0..r15.
1869  return std::make_pair(0U, &AVR::GPR8loRegClass);
1870  case 'e': // Pointer register pairs: x, y, z.
1871  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1872  case 'q': // Stack pointer register: SPH:SPL.
1873  return std::make_pair(0U, &AVR::GPRSPRegClass);
1874  case 'r': // Any register: r0..r31.
1875  if (VT == MVT::i8)
1876  return std::make_pair(0U, &AVR::GPR8RegClass);
1877 
1878  assert(VT == MVT::i16 && "inline asm constraint too large");
1879  return std::make_pair(0U, &AVR::DREGSRegClass);
1880  case 't': // Temporary register: r0.
1881  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1882  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1883  return std::make_pair(0U, &AVR::IWREGSRegClass);
1884  case 'x': // Pointer register pair X: r27:r26.
1885  case 'X':
1886  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1887  case 'y': // Pointer register pair Y: r29:r28.
1888  case 'Y':
1889  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1890  case 'z': // Pointer register pair Z: r31:r30.
1891  case 'Z':
1892  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1893  default:
1894  break;
1895  }
1896  }
1897 
1899  Subtarget.getRegisterInfo(), Constraint, VT);
1900 }
1901 
1903  std::string &Constraint,
1904  std::vector<SDValue> &Ops,
1905  SelectionDAG &DAG) const {
1906  SDValue Result(0, 0);
1907  SDLoc DL(Op);
1908  EVT Ty = Op.getValueType();
1909 
1910  // Currently only support length 1 constraints.
1911  if (Constraint.length() != 1) {
1912  return;
1913  }
1914 
1915  char ConstraintLetter = Constraint[0];
1916  switch (ConstraintLetter) {
1917  default:
1918  break;
1919  // Deal with integers first:
1920  case 'I':
1921  case 'J':
1922  case 'K':
1923  case 'L':
1924  case 'M':
1925  case 'N':
1926  case 'O':
1927  case 'P':
1928  case 'R': {
1930  if (!C) {
1931  return;
1932  }
1933 
1934  int64_t CVal64 = C->getSExtValue();
1935  uint64_t CUVal64 = C->getZExtValue();
1936  switch (ConstraintLetter) {
1937  case 'I': // 0..63
1938  if (!isUInt<6>(CUVal64))
1939  return;
1940  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1941  break;
1942  case 'J': // -63..0
1943  if (CVal64 < -63 || CVal64 > 0)
1944  return;
1945  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1946  break;
1947  case 'K': // 2
1948  if (CUVal64 != 2)
1949  return;
1950  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1951  break;
1952  case 'L': // 0
1953  if (CUVal64 != 0)
1954  return;
1955  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1956  break;
1957  case 'M': // 0..255
1958  if (!isUInt<8>(CUVal64))
1959  return;
1960  // i8 type may be printed as a negative number,
1961  // e.g. 254 would be printed as -2,
1962  // so we force it to i16 at least.
1963  if (Ty.getSimpleVT() == MVT::i8) {
1964  Ty = MVT::i16;
1965  }
1966  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1967  break;
1968  case 'N': // -1
1969  if (CVal64 != -1)
1970  return;
1971  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1972  break;
1973  case 'O': // 8, 16, 24
1974  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1975  return;
1976  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1977  break;
1978  case 'P': // 1
1979  if (CUVal64 != 1)
1980  return;
1981  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1982  break;
1983  case 'R': // -6..5
1984  if (CVal64 < -6 || CVal64 > 5)
1985  return;
1986  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1987  break;
1988  }
1989 
1990  break;
1991  }
1992  case 'G':
1994  if (!FC || !FC->isZero())
1995  return;
1996  // Soften float to i8 0
1997  Result = DAG.getTargetConstant(0, DL, MVT::i8);
1998  break;
1999  }
2000 
2001  if (Result.getNode()) {
2002  Ops.push_back(Result);
2003  return;
2004  }
2005 
2006  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2007 }
2008 
2009 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
2010  EVT VT,
2011  SelectionDAG &DAG) const {
2012  unsigned Reg;
2013 
2014  if (VT == MVT::i8) {
2015  Reg = StringSwitch<unsigned>(RegName)
2016  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
2017  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
2018  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
2019  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
2020  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
2021  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
2022  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
2023  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
2024  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2025  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
2026  .Case("r30", AVR::R30).Case("r31", AVR::R31)
2027  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2028  .Default(0);
2029  } else {
2030  Reg = StringSwitch<unsigned>(RegName)
2031  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
2032  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
2033  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
2034  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
2035  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
2036  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
2037  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
2038  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
2039  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
2040  .Default(0);
2041  }
2042 
2043  if (Reg)
2044  return Reg;
2045 
2046  report_fatal_error("Invalid register name global variable");
2047 }
2048 
2049 } // end of namespace llvm
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
#define R4(n)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:856
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Unsigned lower.
Definition: AVRInstrInfo.h:37
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
unsigned Reg
static void parseFunctionArgs(const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Test for zero or minus instruction.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
#define R2(n)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
SDValue getExternalSymbol(const char *Sym, EVT VT)
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:480
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
Represents an abstract call instruction, which includes a bunch of information.
A loop of single right bit rotate instructions.
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:217
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:47
CallLoweringInfo & setChain(SDValue InChain)
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:467
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:407
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static StructType * get(LLVMContext &Context, ArrayRef< Type *> Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:341
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:273
int64_t getSExtValue() const
A generic AVR implementation.
const AVRSubtarget & Subtarget
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:404
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
Return from subroutine.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
CallLoweringInfo & setZExtResult(bool Value=true)
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:586
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Calling convention used for AVR signal routines.
Definition: CallingConv.h:179
This class is used to represent ISD::STORE nodes.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
bool isZero() const
Return true if the value is positive or negative zero.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:342
Machine Value Type.
Contains AVR-specific information for each MachineFunction.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:759
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
LLVMContext & getContext() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:844
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
self_iterator getIterator()
Definition: ilist_node.h:81
AVR conditional branches.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
lazy value info
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:827
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
Compare instruction.
A loop of single logical shift right instructions.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
#define R6(n)
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
#define NODE(name)
CCValAssign - Represent assignment of one arg/retval to a location.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
A loop of single left bit rotate instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:746
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:672
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:437
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
CallLoweringInfo & setSExtResult(bool Value=true)
Represents one node in the SelectionDAG.
Return from ISR.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:689
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
Bit rotate left.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:469
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:666
Representation of each machine instruction.
Definition: MachineInstr.h:64
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:755
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:683
SmallVector< SDValue, 32 > OutVals
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:715
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:510
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
Logical shift right.
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
SDValue getValue(unsigned R) const
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:183
Arithmetic shift right.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
CallLoweringInfo & setInRegister(bool Value=true)
LLVM Value Representation.
Definition: Value.h:72
SDValue getRegister(unsigned Reg, EVT VT)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Greater than or equal.
Definition: AVRInstrInfo.h:34
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:45
IRTranslator LLVM IR MI
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
Register getReg() const
getReg - Returns the register number.
Conversion operators.
Definition: ISDOpcodes.h:489
const SDValue & getOperand(unsigned i) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
uint64_t getZExtValue() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Used for AVR interrupt routines.
Definition: CallingConv.h:176
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
bool supportsMultiplication() const
Definition: AVRSubtarget.h:71
LLVMContext * getContext() const
Definition: SelectionDAG.h:414
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:632
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:950
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:404
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:651