LLVM  8.0.0svn
PPCISelLowering.cpp
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1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCISelLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCISelLowering.h"
16 #include "PPC.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCFrameLowering.h"
20 #include "PPCInstrInfo.h"
21 #include "PPCMachineFunctionInfo.h"
22 #include "PPCPerfectShuffle.h"
23 #include "PPCRegisterInfo.h"
24 #include "PPCSubtarget.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/None.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/SmallVector.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/StringRef.h"
37 #include "llvm/ADT/StringSwitch.h"
57 #include "llvm/IR/CallSite.h"
58 #include "llvm/IR/CallingConv.h"
59 #include "llvm/IR/Constant.h"
60 #include "llvm/IR/Constants.h"
61 #include "llvm/IR/DataLayout.h"
62 #include "llvm/IR/DebugLoc.h"
63 #include "llvm/IR/DerivedTypes.h"
64 #include "llvm/IR/Function.h"
65 #include "llvm/IR/GlobalValue.h"
66 #include "llvm/IR/IRBuilder.h"
67 #include "llvm/IR/Instructions.h"
68 #include "llvm/IR/Intrinsics.h"
69 #include "llvm/IR/Module.h"
70 #include "llvm/IR/Type.h"
71 #include "llvm/IR/Use.h"
72 #include "llvm/IR/Value.h"
73 #include "llvm/MC/MCExpr.h"
74 #include "llvm/MC/MCRegisterInfo.h"
77 #include "llvm/Support/Casting.h"
78 #include "llvm/Support/CodeGen.h"
80 #include "llvm/Support/Compiler.h"
81 #include "llvm/Support/Debug.h"
83 #include "llvm/Support/Format.h"
84 #include "llvm/Support/KnownBits.h"
90 #include <algorithm>
91 #include <cassert>
92 #include <cstdint>
93 #include <iterator>
94 #include <list>
95 #include <utility>
96 #include <vector>
97 
98 using namespace llvm;
99 
100 #define DEBUG_TYPE "ppc-lowering"
101 
102 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
103 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
104 
105 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
106 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
107 
108 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
109 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
110 
111 static cl::opt<bool> DisableSCO("disable-ppc-sco",
112 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
113 
114 static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
115 cl::desc("enable quad precision float support on ppc"), cl::Hidden);
116 
117 STATISTIC(NumTailCalls, "Number of tail calls");
118 STATISTIC(NumSiblingCalls, "Number of sibling calls");
119 
120 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
121 
122 // FIXME: Remove this once the bug has been fixed!
124 
126  const PPCSubtarget &STI)
127  : TargetLowering(TM), Subtarget(STI) {
128  // Use _setjmp/_longjmp instead of setjmp/longjmp.
131 
132  // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
133  // arguments are at least 4/8 bytes aligned.
134  bool isPPC64 = Subtarget.isPPC64();
135  setMinStackArgumentAlignment(isPPC64 ? 8:4);
136 
137  // Set up the register classes.
138  addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
139  if (!useSoftFloat()) {
140  if (hasSPE()) {
141  addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
142  addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
143  } else {
144  addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
145  addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
146  }
147  }
148 
149  // Match BITREVERSE to customized fast code sequence in the td file.
152 
153  // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
155 
156  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
157  for (MVT VT : MVT::integer_valuetypes()) {
160  }
161 
163 
164  // PowerPC has pre-inc load and store's.
175  if (!Subtarget.hasSPE()) {
180  }
181 
182  // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
183  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
184  for (MVT VT : ScalarIntVTs) {
189  }
190 
191  if (Subtarget.useCRBits()) {
193 
194  if (isPPC64 || Subtarget.hasFPCVT()) {
197  isPPC64 ? MVT::i64 : MVT::i32);
200  isPPC64 ? MVT::i64 : MVT::i32);
201  } else {
204  }
205 
206  // PowerPC does not support direct load/store of condition registers.
209 
210  // FIXME: Remove this once the ANDI glue bug is fixed:
211  if (ANDIGlueBug)
213 
214  for (MVT VT : MVT::integer_valuetypes()) {
218  }
219 
220  addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
221  }
222 
223  // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
224  // PPC (the libcall is not available).
227 
228  // We do not currently implement these libm ops for PowerPC.
235 
236  // PowerPC has no SREM/UREM instructions unless we are on P9
237  // On P9 we may use a hardware instruction to compute the remainder.
238  // The instructions are not legalized directly because in the cases where the
239  // result of both the remainder and the division is required it is more
240  // efficient to compute the remainder from the result of the division rather
241  // than use the remainder instruction.
242  if (Subtarget.isISA3_0()) {
245  setOperationAction(ISD::SREM, MVT::i64, Custom);
246  setOperationAction(ISD::UREM, MVT::i64, Custom);
247  } else {
250  setOperationAction(ISD::SREM, MVT::i64, Expand);
251  setOperationAction(ISD::UREM, MVT::i64, Expand);
252  }
253 
254  if (Subtarget.hasP9Vector()) {
258  }
259 
260  // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
269 
270  // We don't support sin/cos/sqrt/fmod/pow
281  if (Subtarget.hasSPE()) {
284  } else {
287  }
288 
290 
291  // If we're enabling GP optimizations, use hardware square root
292  if (!Subtarget.hasFSQRT() &&
293  !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
294  Subtarget.hasFRE()))
296 
297  if (!Subtarget.hasFSQRT() &&
298  !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
299  Subtarget.hasFRES()))
301 
302  if (Subtarget.hasFCPSGN()) {
305  } else {
308  }
309 
310  if (Subtarget.hasFPRND()) {
315 
320  }
321 
322  // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
323  // to speed up scalar BSWAP64.
324  // CTPOP or CTTZ were introduced in P8/P9 respectively
326  if (Subtarget.isISA3_0()) {
327  setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
329  setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
330  } else {
331  setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
333  setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
334  }
335 
336  if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
338  setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
339  } else {
341  setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
342  }
343 
344  // PowerPC does not have ROTR
346  setOperationAction(ISD::ROTR, MVT::i64 , Expand);
347 
348  if (!Subtarget.useCRBits()) {
349  // PowerPC does not have Select
354  }
355 
356  // PowerPC wants to turn select_cc of FP into fsel when possible.
359 
360  // PowerPC wants to optimize integer setcc a bit
361  if (!Subtarget.useCRBits())
363 
364  // PowerPC does not have BRCOND which requires SetCC
365  if (!Subtarget.useCRBits())
367 
369 
370  if (Subtarget.hasSPE()) {
371  // SPE has built-in conversions
375  } else {
376  // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
378 
379  // PowerPC does not have [U|S]INT_TO_FP
382  }
383 
384  if (Subtarget.hasDirectMove() && isPPC64) {
389  } else {
394  }
395 
396  // We cannot sextinreg(i1). Expand to shifts.
398 
399  // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
400  // SjLj exception handling but a light-weight setjmp/longjmp replacement to
401  // support continuation, user-level threading, and etc.. As a result, no
402  // other SjLj exception interfaces are implemented and please don't build
403  // your own exception handling based on them.
404  // LLVM/Clang supports zero-cost DWARF exception handling.
407 
408  // We want to legalize GlobalAddress and ConstantPool nodes into the
409  // appropriate instructions to materialize the address.
420 
421  // TRAP is legal.
423 
424  // TRAMPOLINE is custom lowered.
427 
428  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
430 
431  if (Subtarget.isSVR4ABI()) {
432  if (isPPC64) {
433  // VAARG always uses double-word chunks, so promote anything smaller.
435  AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
437  AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
443  } else {
444  // VAARG is custom lowered with the 32-bit SVR4 ABI.
447  }
448  } else
450 
451  if (Subtarget.isSVR4ABI() && !isPPC64)
452  // VACOPY is custom lowered with the 32-bit SVR4 ABI.
454  else
456 
457  // Use the default implementation.
467 
468  // We want to custom lower some of our intrinsics.
470 
471  // To handle counter-based loop conditions.
473 
478 
479  // Comparisons that require checking two conditions.
480  if (Subtarget.hasSPE()) {
485  }
498 
499  if (Subtarget.has64BitSupport()) {
500  // They also have instructions for converting between i64 and fp.
505  // This is just the low 32 bits of a (signed) fp->i64 conversion.
506  // We cannot do this with Promote because i64 is not a legal type.
508 
509  if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
511  } else {
512  // PowerPC does not have FP_TO_UINT on 32-bit implementations.
513  if (Subtarget.hasSPE())
515  else
517  }
518 
519  // With the instructions enabled under FPCVT, we can do everything.
520  if (Subtarget.hasFPCVT()) {
521  if (Subtarget.has64BitSupport()) {
526  }
527 
532  }
533 
534  if (Subtarget.use64BitRegs()) {
535  // 64-bit PowerPC implementations can support i64 types directly
536  addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
537  // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
539  // 64-bit PowerPC wants to expand i128 shifts itself.
543  } else {
544  // 32-bit PowerPC wants to expand i64 shifts itself.
548  }
549 
550  if (Subtarget.hasAltivec()) {
551  // First set operation action for all vector types to expand. Then we
552  // will selectively turn on ones that can be effectively codegen'd.
553  for (MVT VT : MVT::vector_valuetypes()) {
554  // add/sub are legal for all supported vector VT's.
557 
558  // Vector instructions introduced in P8
559  if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
562  }
563  else {
566  }
567 
568  // Vector instructions introduced in P9
569  if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
571  else
573 
574  // We promote all shuffles to v16i8.
577 
578  // We promote all non-typed operations to v4i32.
594 
595  // No other operations are legal.
633 
634  for (MVT InnerVT : MVT::vector_valuetypes()) {
635  setTruncStoreAction(VT, InnerVT, Expand);
636  setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
637  setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
638  setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
639  }
640  }
641 
642  // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
643  // with merges, splats, etc.
645 
651  Subtarget.useCRBits() ? Legal : Expand);
661 
662  addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
663  addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
664  addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
665  addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
666 
669 
670  if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
673  }
674 
675  if (Subtarget.hasP8Altivec())
677  else
679 
682 
685 
690 
691  // Altivec does not contain unordered floating-point compare instructions
696 
697  if (Subtarget.hasVSX()) {
700  if (Subtarget.hasP8Vector()) {
703  }
704  if (Subtarget.hasDirectMove() && isPPC64) {
713  }
715 
721 
723 
726 
729 
730  // Share the Altivec comparison restrictions.
735 
738 
740 
741  if (Subtarget.hasP8Vector())
742  addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
743 
744  addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
745 
746  addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
747  addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
748  addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
749 
750  if (Subtarget.hasP8Altivec()) {
754 
755  // 128 bit shifts can be accomplished via 3 instructions for SHL and
756  // SRL, but not for SRA because of the instructions available:
757  // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
758  // doing
762 
764  }
765  else {
769 
771 
772  // VSX v2i64 only supports non-arithmetic operations.
775  }
776 
781 
783 
788 
791 
796 
797  if (Subtarget.hasDirectMove())
800 
801  addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
802  }
803 
804  if (Subtarget.hasP8Altivec()) {
805  addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
806  addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
807  }
808 
809  if (Subtarget.hasP9Vector()) {
812 
813  // 128 bit shifts can be accomplished via 3 instructions for SHL and
814  // SRL, but not for SRA because of the instructions available:
815  // VS{RL} and VS{RL}O.
819 
820  if (EnableQuadPrecision) {
821  addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
827  // No extending loads to f128 on PPC.
828  for (MVT FPT : MVT::fp_valuetypes())
837 
844 
851  // No implementation for these ops for PowerPC.
857  }
858 
859  }
860 
861  if (Subtarget.hasP9Altivec()) {
864  }
865  }
866 
867  if (Subtarget.hasQPX()) {
872 
875 
878 
881 
882  if (!Subtarget.useCRBits())
885 
893 
896 
900 
911 
914 
917 
918  addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
919 
924 
927 
930 
931  if (!Subtarget.useCRBits())
934 
942 
945 
956 
959 
962 
963  addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
964 
968 
969  if (!Subtarget.useCRBits())
972 
975 
983 
986 
987  addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
988 
993 
998 
1001 
1002  // These need to set FE_INEXACT, and so cannot be vectorized here.
1005 
1006  if (TM.Options.UnsafeFPMath) {
1009 
1012  } else {
1015 
1018  }
1019  }
1020 
1021  if (Subtarget.has64BitSupport())
1023 
1024  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1025 
1026  if (!isPPC64) {
1029  }
1030 
1032 
1033  if (Subtarget.hasAltivec()) {
1034  // Altivec instructions set fields to all zeros or all ones.
1036  }
1037 
1038  if (!isPPC64) {
1039  // These libcalls are not available in 32-bit.
1040  setLibcallName(RTLIB::SHL_I128, nullptr);
1041  setLibcallName(RTLIB::SRL_I128, nullptr);
1042  setLibcallName(RTLIB::SRA_I128, nullptr);
1043  }
1044 
1045  setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1046 
1047  // We have target-specific dag combine patterns for the following nodes:
1054  if (Subtarget.hasFPCVT())
1059  if (Subtarget.useCRBits())
1065 
1069 
1071 
1072  if (Subtarget.useCRBits()) {
1076  }
1077 
1078  // Use reciprocal estimates.
1079  if (TM.Options.UnsafeFPMath) {
1082  }
1083 
1084  // Darwin long double math library functions have $LDBL128 appended.
1085  if (Subtarget.isDarwin()) {
1086  setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1087  setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1088  setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1089  setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1090  setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1091  setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1092  setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1093  setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1094  setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1095  setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1096  }
1097 
1098  if (EnableQuadPrecision) {
1099  setLibcallName(RTLIB::LOG_F128, "logf128");
1100  setLibcallName(RTLIB::LOG2_F128, "log2f128");
1101  setLibcallName(RTLIB::LOG10_F128, "log10f128");
1102  setLibcallName(RTLIB::EXP_F128, "expf128");
1103  setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1104  setLibcallName(RTLIB::SIN_F128, "sinf128");
1105  setLibcallName(RTLIB::COS_F128, "cosf128");
1106  setLibcallName(RTLIB::POW_F128, "powf128");
1107  setLibcallName(RTLIB::FMIN_F128, "fminf128");
1108  setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1109  setLibcallName(RTLIB::POWI_F128, "__powikf2");
1110  setLibcallName(RTLIB::REM_F128, "fmodf128");
1111  }
1112 
1113  // With 32 condition bits, we don't need to sink (and duplicate) compares
1114  // aggressively in CodeGenPrep.
1115  if (Subtarget.useCRBits()) {
1118  }
1119 
1121  if (Subtarget.isDarwin())
1123 
1124  switch (Subtarget.getDarwinDirective()) {
1125  default: break;
1126  case PPC::DIR_970:
1127  case PPC::DIR_A2:
1128  case PPC::DIR_E500:
1129  case PPC::DIR_E500mc:
1130  case PPC::DIR_E5500:
1131  case PPC::DIR_PWR4:
1132  case PPC::DIR_PWR5:
1133  case PPC::DIR_PWR5X:
1134  case PPC::DIR_PWR6:
1135  case PPC::DIR_PWR6X:
1136  case PPC::DIR_PWR7:
1137  case PPC::DIR_PWR8:
1138  case PPC::DIR_PWR9:
1141  break;
1142  }
1143 
1144  if (Subtarget.enableMachineScheduler())
1146  else
1148 
1150 
1151  // The Freescale cores do better with aggressive inlining of memcpy and
1152  // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1153  if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1154  Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1155  MaxStoresPerMemset = 32;
1157  MaxStoresPerMemcpy = 32;
1159  MaxStoresPerMemmove = 32;
1161  } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1162  // The A2 also benefits from (very) aggressive inlining of memcpy and
1163  // friends. The overhead of a the function call, even when warm, can be
1164  // over one hundred cycles.
1165  MaxStoresPerMemset = 128;
1166  MaxStoresPerMemcpy = 128;
1167  MaxStoresPerMemmove = 128;
1168  MaxLoadsPerMemcmp = 128;
1169  } else {
1170  MaxLoadsPerMemcmp = 8;
1172  }
1173 }
1174 
1175 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1176 /// the desired ByVal argument alignment.
1177 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1178  unsigned MaxMaxAlign) {
1179  if (MaxAlign == MaxMaxAlign)
1180  return;
1181  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1182  if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1183  MaxAlign = 32;
1184  else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1185  MaxAlign = 16;
1186  } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1187  unsigned EltAlign = 0;
1188  getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1189  if (EltAlign > MaxAlign)
1190  MaxAlign = EltAlign;
1191  } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1192  for (auto *EltTy : STy->elements()) {
1193  unsigned EltAlign = 0;
1194  getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1195  if (EltAlign > MaxAlign)
1196  MaxAlign = EltAlign;
1197  if (MaxAlign == MaxMaxAlign)
1198  break;
1199  }
1200  }
1201 }
1202 
1203 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1204 /// function arguments in the caller parameter area.
1206  const DataLayout &DL) const {
1207  // Darwin passes everything on 4 byte boundary.
1208  if (Subtarget.isDarwin())
1209  return 4;
1210 
1211  // 16byte and wider vectors are passed on 16byte boundary.
1212  // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1213  unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1214  if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1215  getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1216  return Align;
1217 }
1218 
1220  CallingConv:: ID CC,
1221  EVT VT) const {
1222  if (Subtarget.hasSPE() && VT == MVT::f64)
1223  return 2;
1224  return PPCTargetLowering::getNumRegisters(Context, VT);
1225 }
1226 
1228  CallingConv:: ID CC,
1229  EVT VT) const {
1230  if (Subtarget.hasSPE() && VT == MVT::f64)
1231  return MVT::i32;
1232  return PPCTargetLowering::getRegisterType(Context, VT);
1233 }
1234 
1236  return Subtarget.useSoftFloat();
1237 }
1238 
1240  return Subtarget.hasSPE();
1241 }
1242 
1243 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1244  switch ((PPCISD::NodeType)Opcode) {
1245  case PPCISD::FIRST_NUMBER: break;
1246  case PPCISD::FSEL: return "PPCISD::FSEL";
1247  case PPCISD::FCFID: return "PPCISD::FCFID";
1248  case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1249  case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1250  case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1251  case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1252  case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1253  case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1254  case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1256  return "PPCISD::FP_TO_UINT_IN_VSR,";
1258  return "PPCISD::FP_TO_SINT_IN_VSR";
1259  case PPCISD::FRE: return "PPCISD::FRE";
1260  case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1261  case PPCISD::STFIWX: return "PPCISD::STFIWX";
1262  case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1263  case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1264  case PPCISD::VPERM: return "PPCISD::VPERM";
1265  case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1266  case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1267  case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1268  case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1269  case PPCISD::VECSHL: return "PPCISD::VECSHL";
1270  case PPCISD::CMPB: return "PPCISD::CMPB";
1271  case PPCISD::Hi: return "PPCISD::Hi";
1272  case PPCISD::Lo: return "PPCISD::Lo";
1273  case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1274  case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1275  case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1276  case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1277  case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1278  case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1279  case PPCISD::SRL: return "PPCISD::SRL";
1280  case PPCISD::SRA: return "PPCISD::SRA";
1281  case PPCISD::SHL: return "PPCISD::SHL";
1282  case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1283  case PPCISD::CALL: return "PPCISD::CALL";
1284  case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1285  case PPCISD::MTCTR: return "PPCISD::MTCTR";
1286  case PPCISD::BCTRL: return "PPCISD::BCTRL";
1287  case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1288  case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1289  case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1290  case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1291  case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1292  case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1293  case PPCISD::MFVSR: return "PPCISD::MFVSR";
1294  case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1295  case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1296  case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1297  case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1298  case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1299  case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1300  case PPCISD::VCMP: return "PPCISD::VCMP";
1301  case PPCISD::VCMPo: return "PPCISD::VCMPo";
1302  case PPCISD::LBRX: return "PPCISD::LBRX";
1303  case PPCISD::STBRX: return "PPCISD::STBRX";
1304  case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1305  case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1306  case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1307  case PPCISD::STXSIX: return "PPCISD::STXSIX";
1308  case PPCISD::VEXTS: return "PPCISD::VEXTS";
1309  case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1310  case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1311  case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1313  return "PPCISD::ST_VSR_SCAL_INT";
1314  case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1315  case PPCISD::BDNZ: return "PPCISD::BDNZ";
1316  case PPCISD::BDZ: return "PPCISD::BDZ";
1317  case PPCISD::MFFS: return "PPCISD::MFFS";
1318  case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1319  case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1320  case PPCISD::CR6SET: return "PPCISD::CR6SET";
1321  case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1322  case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1323  case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1324  case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1325  case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1326  case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1327  case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1328  case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1329  case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1330  case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1331  case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1332  case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1333  case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1334  case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1335  case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1336  case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1337  case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1338  case PPCISD::SC: return "PPCISD::SC";
1339  case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1340  case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1341  case PPCISD::RFEBB: return "PPCISD::RFEBB";
1342  case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1343  case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1344  case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1345  case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1346  case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1347  case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1348  case PPCISD::QBFLT: return "PPCISD::QBFLT";
1349  case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1350  case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1351  case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1352  }
1353  return nullptr;
1354 }
1355 
1357  EVT VT) const {
1358  if (!VT.isVector())
1359  return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1360 
1361  if (Subtarget.hasQPX())
1363 
1365 }
1366 
1368  assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1369  return true;
1370 }
1371 
1372 //===----------------------------------------------------------------------===//
1373 // Node matching predicates, for use by the tblgen matching code.
1374 //===----------------------------------------------------------------------===//
1375 
1376 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1378  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1379  return CFP->getValueAPF().isZero();
1380  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1381  // Maybe this has already been legalized into the constant pool?
1382  if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1383  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1384  return CFP->getValueAPF().isZero();
1385  }
1386  return false;
1387 }
1388 
1389 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1390 /// true if Op is undef or if it matches the specified value.
1391 static bool isConstantOrUndef(int Op, int Val) {
1392  return Op < 0 || Op == Val;
1393 }
1394 
1395 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1396 /// VPKUHUM instruction.
1397 /// The ShuffleKind distinguishes between big-endian operations with
1398 /// two different inputs (0), either-endian operations with two identical
1399 /// inputs (1), and little-endian operations with two different inputs (2).
1400 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1402  SelectionDAG &DAG) {
1403  bool IsLE = DAG.getDataLayout().isLittleEndian();
1404  if (ShuffleKind == 0) {
1405  if (IsLE)
1406  return false;
1407  for (unsigned i = 0; i != 16; ++i)
1408  if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1409  return false;
1410  } else if (ShuffleKind == 2) {
1411  if (!IsLE)
1412  return false;
1413  for (unsigned i = 0; i != 16; ++i)
1414  if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1415  return false;
1416  } else if (ShuffleKind == 1) {
1417  unsigned j = IsLE ? 0 : 1;
1418  for (unsigned i = 0; i != 8; ++i)
1419  if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1420  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1421  return false;
1422  }
1423  return true;
1424 }
1425 
1426 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1427 /// VPKUWUM instruction.
1428 /// The ShuffleKind distinguishes between big-endian operations with
1429 /// two different inputs (0), either-endian operations with two identical
1430 /// inputs (1), and little-endian operations with two different inputs (2).
1431 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1433  SelectionDAG &DAG) {
1434  bool IsLE = DAG.getDataLayout().isLittleEndian();
1435  if (ShuffleKind == 0) {
1436  if (IsLE)
1437  return false;
1438  for (unsigned i = 0; i != 16; i += 2)
1439  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1440  !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1441  return false;
1442  } else if (ShuffleKind == 2) {
1443  if (!IsLE)
1444  return false;
1445  for (unsigned i = 0; i != 16; i += 2)
1446  if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1447  !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1448  return false;
1449  } else if (ShuffleKind == 1) {
1450  unsigned j = IsLE ? 0 : 2;
1451  for (unsigned i = 0; i != 8; i += 2)
1452  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1453  !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1454  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1455  !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1456  return false;
1457  }
1458  return true;
1459 }
1460 
1461 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1462 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1463 /// current subtarget.
1464 ///
1465 /// The ShuffleKind distinguishes between big-endian operations with
1466 /// two different inputs (0), either-endian operations with two identical
1467 /// inputs (1), and little-endian operations with two different inputs (2).
1468 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1470  SelectionDAG &DAG) {
1471  const PPCSubtarget& Subtarget =
1472  static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1473  if (!Subtarget.hasP8Vector())
1474  return false;
1475 
1476  bool IsLE = DAG.getDataLayout().isLittleEndian();
1477  if (ShuffleKind == 0) {
1478  if (IsLE)
1479  return false;
1480  for (unsigned i = 0; i != 16; i += 4)
1481  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1482  !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1483  !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1484  !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1485  return false;
1486  } else if (ShuffleKind == 2) {
1487  if (!IsLE)
1488  return false;
1489  for (unsigned i = 0; i != 16; i += 4)
1490  if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1491  !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1492  !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1493  !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1494  return false;
1495  } else if (ShuffleKind == 1) {
1496  unsigned j = IsLE ? 0 : 4;
1497  for (unsigned i = 0; i != 8; i += 4)
1498  if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1499  !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1500  !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1501  !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1502  !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1503  !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1504  !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1505  !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1506  return false;
1507  }
1508  return true;
1509 }
1510 
1511 /// isVMerge - Common function, used to match vmrg* shuffles.
1512 ///
1513 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1514  unsigned LHSStart, unsigned RHSStart) {
1515  if (N->getValueType(0) != MVT::v16i8)
1516  return false;
1517  assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1518  "Unsupported merge size!");
1519 
1520  for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1521  for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1522  if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1523  LHSStart+j+i*UnitSize) ||
1524  !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1525  RHSStart+j+i*UnitSize))
1526  return false;
1527  }
1528  return true;
1529 }
1530 
1531 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1532 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1533 /// The ShuffleKind distinguishes between big-endian merges with two
1534 /// different inputs (0), either-endian merges with two identical inputs (1),
1535 /// and little-endian merges with two different inputs (2). For the latter,
1536 /// the input operands are swapped (see PPCInstrAltivec.td).
1538  unsigned ShuffleKind, SelectionDAG &DAG) {
1539  if (DAG.getDataLayout().isLittleEndian()) {
1540  if (ShuffleKind == 1) // unary
1541  return isVMerge(N, UnitSize, 0, 0);
1542  else if (ShuffleKind == 2) // swapped
1543  return isVMerge(N, UnitSize, 0, 16);
1544  else
1545  return false;
1546  } else {
1547  if (ShuffleKind == 1) // unary
1548  return isVMerge(N, UnitSize, 8, 8);
1549  else if (ShuffleKind == 0) // normal
1550  return isVMerge(N, UnitSize, 8, 24);
1551  else
1552  return false;
1553  }
1554 }
1555 
1556 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1557 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1558 /// The ShuffleKind distinguishes between big-endian merges with two
1559 /// different inputs (0), either-endian merges with two identical inputs (1),
1560 /// and little-endian merges with two different inputs (2). For the latter,
1561 /// the input operands are swapped (see PPCInstrAltivec.td).
1563  unsigned ShuffleKind, SelectionDAG &DAG) {
1564  if (DAG.getDataLayout().isLittleEndian()) {
1565  if (ShuffleKind == 1) // unary
1566  return isVMerge(N, UnitSize, 8, 8);
1567  else if (ShuffleKind == 2) // swapped
1568  return isVMerge(N, UnitSize, 8, 24);
1569  else
1570  return false;
1571  } else {
1572  if (ShuffleKind == 1) // unary
1573  return isVMerge(N, UnitSize, 0, 0);
1574  else if (ShuffleKind == 0) // normal
1575  return isVMerge(N, UnitSize, 0, 16);
1576  else
1577  return false;
1578  }
1579 }
1580 
1581 /**
1582  * Common function used to match vmrgew and vmrgow shuffles
1583  *
1584  * The indexOffset determines whether to look for even or odd words in
1585  * the shuffle mask. This is based on the of the endianness of the target
1586  * machine.
1587  * - Little Endian:
1588  * - Use offset of 0 to check for odd elements
1589  * - Use offset of 4 to check for even elements
1590  * - Big Endian:
1591  * - Use offset of 0 to check for even elements
1592  * - Use offset of 4 to check for odd elements
1593  * A detailed description of the vector element ordering for little endian and
1594  * big endian can be found at
1595  * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1596  * Targeting your applications - what little endian and big endian IBM XL C/C++
1597  * compiler differences mean to you
1598  *
1599  * The mask to the shuffle vector instruction specifies the indices of the
1600  * elements from the two input vectors to place in the result. The elements are
1601  * numbered in array-access order, starting with the first vector. These vectors
1602  * are always of type v16i8, thus each vector will contain 16 elements of size
1603  * 8. More info on the shuffle vector can be found in the
1604  * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1605  * Language Reference.
1606  *
1607  * The RHSStartValue indicates whether the same input vectors are used (unary)
1608  * or two different input vectors are used, based on the following:
1609  * - If the instruction uses the same vector for both inputs, the range of the
1610  * indices will be 0 to 15. In this case, the RHSStart value passed should
1611  * be 0.
1612  * - If the instruction has two different vectors then the range of the
1613  * indices will be 0 to 31. In this case, the RHSStart value passed should
1614  * be 16 (indices 0-15 specify elements in the first vector while indices 16
1615  * to 31 specify elements in the second vector).
1616  *
1617  * \param[in] N The shuffle vector SD Node to analyze
1618  * \param[in] IndexOffset Specifies whether to look for even or odd elements
1619  * \param[in] RHSStartValue Specifies the starting index for the righthand input
1620  * vector to the shuffle_vector instruction
1621  * \return true iff this shuffle vector represents an even or odd word merge
1622  */
1623 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1624  unsigned RHSStartValue) {
1625  if (N->getValueType(0) != MVT::v16i8)
1626  return false;
1627 
1628  for (unsigned i = 0; i < 2; ++i)
1629  for (unsigned j = 0; j < 4; ++j)
1630  if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1631  i*RHSStartValue+j+IndexOffset) ||
1632  !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1633  i*RHSStartValue+j+IndexOffset+8))
1634  return false;
1635  return true;
1636 }
1637 
1638 /**
1639  * Determine if the specified shuffle mask is suitable for the vmrgew or
1640  * vmrgow instructions.
1641  *
1642  * \param[in] N The shuffle vector SD Node to analyze
1643  * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1644  * \param[in] ShuffleKind Identify the type of merge:
1645  * - 0 = big-endian merge with two different inputs;
1646  * - 1 = either-endian merge with two identical inputs;
1647  * - 2 = little-endian merge with two different inputs (inputs are swapped for
1648  * little-endian merges).
1649  * \param[in] DAG The current SelectionDAG
1650  * \return true iff this shuffle mask
1651  */
1653  unsigned ShuffleKind, SelectionDAG &DAG) {
1654  if (DAG.getDataLayout().isLittleEndian()) {
1655  unsigned indexOffset = CheckEven ? 4 : 0;
1656  if (ShuffleKind == 1) // Unary
1657  return isVMerge(N, indexOffset, 0);
1658  else if (ShuffleKind == 2) // swapped
1659  return isVMerge(N, indexOffset, 16);
1660  else
1661  return false;
1662  }
1663  else {
1664  unsigned indexOffset = CheckEven ? 0 : 4;
1665  if (ShuffleKind == 1) // Unary
1666  return isVMerge(N, indexOffset, 0);
1667  else if (ShuffleKind == 0) // Normal
1668  return isVMerge(N, indexOffset, 16);
1669  else
1670  return false;
1671  }
1672  return false;
1673 }
1674 
1675 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1676 /// amount, otherwise return -1.
1677 /// The ShuffleKind distinguishes between big-endian operations with two
1678 /// different inputs (0), either-endian operations with two identical inputs
1679 /// (1), and little-endian operations with two different inputs (2). For the
1680 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1681 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1682  SelectionDAG &DAG) {
1683  if (N->getValueType(0) != MVT::v16i8)
1684  return -1;
1685 
1686  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1687 
1688  // Find the first non-undef value in the shuffle mask.
1689  unsigned i;
1690  for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1691  /*search*/;
1692 
1693  if (i == 16) return -1; // all undef.
1694 
1695  // Otherwise, check to see if the rest of the elements are consecutively
1696  // numbered from this value.
1697  unsigned ShiftAmt = SVOp->getMaskElt(i);
1698  if (ShiftAmt < i) return -1;
1699 
1700  ShiftAmt -= i;
1701  bool isLE = DAG.getDataLayout().isLittleEndian();
1702 
1703  if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1704  // Check the rest of the elements to see if they are consecutive.
1705  for (++i; i != 16; ++i)
1706  if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1707  return -1;
1708  } else if (ShuffleKind == 1) {
1709  // Check the rest of the elements to see if they are consecutive.
1710  for (++i; i != 16; ++i)
1711  if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1712  return -1;
1713  } else
1714  return -1;
1715 
1716  if (isLE)
1717  ShiftAmt = 16 - ShiftAmt;
1718 
1719  return ShiftAmt;
1720 }
1721 
1722 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1723 /// specifies a splat of a single element that is suitable for input to
1724 /// VSPLTB/VSPLTH/VSPLTW.
1726  assert(N->getValueType(0) == MVT::v16i8 &&
1727  (EltSize == 1 || EltSize == 2 || EltSize == 4));
1728 
1729  // The consecutive indices need to specify an element, not part of two
1730  // different elements. So abandon ship early if this isn't the case.
1731  if (N->getMaskElt(0) % EltSize != 0)
1732  return false;
1733 
1734  // This is a splat operation if each element of the permute is the same, and
1735  // if the value doesn't reference the second vector.
1736  unsigned ElementBase = N->getMaskElt(0);
1737 
1738  // FIXME: Handle UNDEF elements too!
1739  if (ElementBase >= 16)
1740  return false;
1741 
1742  // Check that the indices are consecutive, in the case of a multi-byte element
1743  // splatted with a v16i8 mask.
1744  for (unsigned i = 1; i != EltSize; ++i)
1745  if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1746  return false;
1747 
1748  for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1749  if (N->getMaskElt(i) < 0) continue;
1750  for (unsigned j = 0; j != EltSize; ++j)
1751  if (N->getMaskElt(i+j) != N->getMaskElt(j))
1752  return false;
1753  }
1754  return true;
1755 }
1756 
1757 /// Check that the mask is shuffling N byte elements. Within each N byte
1758 /// element of the mask, the indices could be either in increasing or
1759 /// decreasing order as long as they are consecutive.
1760 /// \param[in] N the shuffle vector SD Node to analyze
1761 /// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1762 /// Word/DoubleWord/QuadWord).
1763 /// \param[in] StepLen the delta indices number among the N byte element, if
1764 /// the mask is in increasing/decreasing order then it is 1/-1.
1765 /// \return true iff the mask is shuffling N byte elements.
1766 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1767  int StepLen) {
1768  assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
1769  "Unexpected element width.");
1770  assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
1771 
1772  unsigned NumOfElem = 16 / Width;
1773  unsigned MaskVal[16]; // Width is never greater than 16
1774  for (unsigned i = 0; i < NumOfElem; ++i) {
1775  MaskVal[0] = N->getMaskElt(i * Width);
1776  if ((StepLen == 1) && (MaskVal[0] % Width)) {
1777  return false;
1778  } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1779  return false;
1780  }
1781 
1782  for (unsigned int j = 1; j < Width; ++j) {
1783  MaskVal[j] = N->getMaskElt(i * Width + j);
1784  if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1785  return false;
1786  }
1787  }
1788  }
1789 
1790  return true;
1791 }
1792 
1793 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1794  unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1795  if (!isNByteElemShuffleMask(N, 4, 1))
1796  return false;
1797 
1798  // Now we look at mask elements 0,4,8,12
1799  unsigned M0 = N->getMaskElt(0) / 4;
1800  unsigned M1 = N->getMaskElt(4) / 4;
1801  unsigned M2 = N->getMaskElt(8) / 4;
1802  unsigned M3 = N->getMaskElt(12) / 4;
1803  unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1804  unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1805 
1806  // Below, let H and L be arbitrary elements of the shuffle mask
1807  // where H is in the range [4,7] and L is in the range [0,3].
1808  // H, 1, 2, 3 or L, 5, 6, 7
1809  if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1810  (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1811  ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1812  InsertAtByte = IsLE ? 12 : 0;
1813  Swap = M0 < 4;
1814  return true;
1815  }
1816  // 0, H, 2, 3 or 4, L, 6, 7
1817  if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1818  (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1819  ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1820  InsertAtByte = IsLE ? 8 : 4;
1821  Swap = M1 < 4;
1822  return true;
1823  }
1824  // 0, 1, H, 3 or 4, 5, L, 7
1825  if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1826  (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1827  ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1828  InsertAtByte = IsLE ? 4 : 8;
1829  Swap = M2 < 4;
1830  return true;
1831  }
1832  // 0, 1, 2, H or 4, 5, 6, L
1833  if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1834  (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1835  ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1836  InsertAtByte = IsLE ? 0 : 12;
1837  Swap = M3 < 4;
1838  return true;
1839  }
1840 
1841  // If both vector operands for the shuffle are the same vector, the mask will
1842  // contain only elements from the first one and the second one will be undef.
1843  if (N->getOperand(1).isUndef()) {
1844  ShiftElts = 0;
1845  Swap = true;
1846  unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1847  if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1848  InsertAtByte = IsLE ? 12 : 0;
1849  return true;
1850  }
1851  if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1852  InsertAtByte = IsLE ? 8 : 4;
1853  return true;
1854  }
1855  if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1856  InsertAtByte = IsLE ? 4 : 8;
1857  return true;
1858  }
1859  if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1860  InsertAtByte = IsLE ? 0 : 12;
1861  return true;
1862  }
1863  }
1864 
1865  return false;
1866 }
1867 
1869  bool &Swap, bool IsLE) {
1870  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1871  // Ensure each byte index of the word is consecutive.
1872  if (!isNByteElemShuffleMask(N, 4, 1))
1873  return false;
1874 
1875  // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1876  unsigned M0 = N->getMaskElt(0) / 4;
1877  unsigned M1 = N->getMaskElt(4) / 4;
1878  unsigned M2 = N->getMaskElt(8) / 4;
1879  unsigned M3 = N->getMaskElt(12) / 4;
1880 
1881  // If both vector operands for the shuffle are the same vector, the mask will
1882  // contain only elements from the first one and the second one will be undef.
1883  if (N->getOperand(1).isUndef()) {
1884  assert(M0 < 4 && "Indexing into an undef vector?");
1885  if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1886  return false;
1887 
1888  ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1889  Swap = false;
1890  return true;
1891  }
1892 
1893  // Ensure each word index of the ShuffleVector Mask is consecutive.
1894  if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
1895  return false;
1896 
1897  if (IsLE) {
1898  if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1899  // Input vectors don't need to be swapped if the leading element
1900  // of the result is one of the 3 left elements of the second vector
1901  // (or if there is no shift to be done at all).
1902  Swap = false;
1903  ShiftElts = (8 - M0) % 8;
1904  } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1905  // Input vectors need to be swapped if the leading element
1906  // of the result is one of the 3 left elements of the first vector
1907  // (or if we're shifting by 4 - thereby simply swapping the vectors).
1908  Swap = true;
1909  ShiftElts = (4 - M0) % 4;
1910  }
1911 
1912  return true;
1913  } else { // BE
1914  if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
1915  // Input vectors don't need to be swapped if the leading element
1916  // of the result is one of the 4 elements of the first vector.
1917  Swap = false;
1918  ShiftElts = M0;
1919  } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
1920  // Input vectors need to be swapped if the leading element
1921  // of the result is one of the 4 elements of the right vector.
1922  Swap = true;
1923  ShiftElts = M0 - 4;
1924  }
1925 
1926  return true;
1927  }
1928 }
1929 
1931  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1932 
1933  if (!isNByteElemShuffleMask(N, Width, -1))
1934  return false;
1935 
1936  for (int i = 0; i < 16; i += Width)
1937  if (N->getMaskElt(i) != i + Width - 1)
1938  return false;
1939 
1940  return true;
1941 }
1942 
1944  return isXXBRShuffleMaskHelper(N, 2);
1945 }
1946 
1948  return isXXBRShuffleMaskHelper(N, 4);
1949 }
1950 
1952  return isXXBRShuffleMaskHelper(N, 8);
1953 }
1954 
1956  return isXXBRShuffleMaskHelper(N, 16);
1957 }
1958 
1959 /// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1960 /// if the inputs to the instruction should be swapped and set \p DM to the
1961 /// value for the immediate.
1962 /// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1963 /// AND element 0 of the result comes from the first input (LE) or second input
1964 /// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1965 /// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1966 /// mask.
1968  bool &Swap, bool IsLE) {
1969  assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
1970 
1971  // Ensure each byte index of the double word is consecutive.
1972  if (!isNByteElemShuffleMask(N, 8, 1))
1973  return false;
1974 
1975  unsigned M0 = N->getMaskElt(0) / 8;
1976  unsigned M1 = N->getMaskElt(8) / 8;
1977  assert(((M0 | M1) < 4) && "A mask element out of bounds?");
1978 
1979  // If both vector operands for the shuffle are the same vector, the mask will
1980  // contain only elements from the first one and the second one will be undef.
1981  if (N->getOperand(1).isUndef()) {
1982  if ((M0 | M1) < 2) {
1983  DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
1984  Swap = false;
1985  return true;
1986  } else
1987  return false;
1988  }
1989 
1990  if (IsLE) {
1991  if (M0 > 1 && M1 < 2) {
1992  Swap = false;
1993  } else if (M0 < 2 && M1 > 1) {
1994  M0 = (M0 + 2) % 4;
1995  M1 = (M1 + 2) % 4;
1996  Swap = true;
1997  } else
1998  return false;
1999 
2000  // Note: if control flow comes here that means Swap is already set above
2001  DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2002  return true;
2003  } else { // BE
2004  if (M0 < 2 && M1 > 1) {
2005  Swap = false;
2006  } else if (M0 > 1 && M1 < 2) {
2007  M0 = (M0 + 2) % 4;
2008  M1 = (M1 + 2) % 4;
2009  Swap = true;
2010  } else
2011  return false;
2012 
2013  // Note: if control flow comes here that means Swap is already set above
2014  DM = (M0 << 1) + (M1 & 1);
2015  return true;
2016  }
2017 }
2018 
2019 
2020 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
2021 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
2022 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
2023  SelectionDAG &DAG) {
2024  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2025  assert(isSplatShuffleMask(SVOp, EltSize));
2026  if (DAG.getDataLayout().isLittleEndian())
2027  return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2028  else
2029  return SVOp->getMaskElt(0) / EltSize;
2030 }
2031 
2032 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2033 /// by using a vspltis[bhw] instruction of the specified element size, return
2034 /// the constant being splatted. The ByteSize field indicates the number of
2035 /// bytes of each element [124] -> [bhw].
2036 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2037  SDValue OpVal(nullptr, 0);
2038 
2039  // If ByteSize of the splat is bigger than the element size of the
2040  // build_vector, then we have a case where we are checking for a splat where
2041  // multiple elements of the buildvector are folded together into a single
2042  // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2043  unsigned EltSize = 16/N->getNumOperands();
2044  if (EltSize < ByteSize) {
2045  unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2046  SDValue UniquedVals[4];
2047  assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2048 
2049  // See if all of the elements in the buildvector agree across.
2050  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2051  if (N->getOperand(i).isUndef()) continue;
2052  // If the element isn't a constant, bail fully out.
2053  if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2054 
2055  if (!UniquedVals[i&(Multiple-1)].getNode())
2056  UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2057  else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2058  return SDValue(); // no match.
2059  }
2060 
2061  // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2062  // either constant or undef values that are identical for each chunk. See
2063  // if these chunks can form into a larger vspltis*.
2064 
2065  // Check to see if all of the leading entries are either 0 or -1. If
2066  // neither, then this won't fit into the immediate field.
2067  bool LeadingZero = true;
2068  bool LeadingOnes = true;
2069  for (unsigned i = 0; i != Multiple-1; ++i) {
2070  if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2071 
2072  LeadingZero &= isNullConstant(UniquedVals[i]);
2073  LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2074  }
2075  // Finally, check the least significant entry.
2076  if (LeadingZero) {
2077  if (!UniquedVals[Multiple-1].getNode())
2078  return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2079  int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2080  if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2081  return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2082  }
2083  if (LeadingOnes) {
2084  if (!UniquedVals[Multiple-1].getNode())
2085  return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2086  int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2087  if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2088  return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2089  }
2090 
2091  return SDValue();
2092  }
2093 
2094  // Check to see if this buildvec has a single non-undef value in its elements.
2095  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2096  if (N->getOperand(i).isUndef()) continue;
2097  if (!OpVal.getNode())
2098  OpVal = N->getOperand(i);
2099  else if (OpVal != N->getOperand(i))
2100  return SDValue();
2101  }
2102 
2103  if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2104 
2105  unsigned ValSizeInBytes = EltSize;
2106  uint64_t Value = 0;
2107  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2108  Value = CN->getZExtValue();
2109  } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2110  assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2111  Value = FloatToBits(CN->getValueAPF().convertToFloat());
2112  }
2113 
2114  // If the splat value is larger than the element value, then we can never do
2115  // this splat. The only case that we could fit the replicated bits into our
2116  // immediate field for would be zero, and we prefer to use vxor for it.
2117  if (ValSizeInBytes < ByteSize) return SDValue();
2118 
2119  // If the element value is larger than the splat value, check if it consists
2120  // of a repeated bit pattern of size ByteSize.
2121  if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2122  return SDValue();
2123 
2124  // Properly sign extend the value.
2125  int MaskVal = SignExtend32(Value, ByteSize * 8);
2126 
2127  // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2128  if (MaskVal == 0) return SDValue();
2129 
2130  // Finally, if this value fits in a 5 bit sext field, return it
2131  if (SignExtend32<5>(MaskVal) == MaskVal)
2132  return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2133  return SDValue();
2134 }
2135 
2136 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2137 /// amount, otherwise return -1.
2139  EVT VT = N->getValueType(0);
2140  if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2141  return -1;
2142 
2143  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2144 
2145  // Find the first non-undef value in the shuffle mask.
2146  unsigned i;
2147  for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2148  /*search*/;
2149 
2150  if (i == 4) return -1; // all undef.
2151 
2152  // Otherwise, check to see if the rest of the elements are consecutively
2153  // numbered from this value.
2154  unsigned ShiftAmt = SVOp->getMaskElt(i);
2155  if (ShiftAmt < i) return -1;
2156  ShiftAmt -= i;
2157 
2158  // Check the rest of the elements to see if they are consecutive.
2159  for (++i; i != 4; ++i)
2160  if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2161  return -1;
2162 
2163  return ShiftAmt;
2164 }
2165 
2166 //===----------------------------------------------------------------------===//
2167 // Addressing Mode Selection
2168 //===----------------------------------------------------------------------===//
2169 
2170 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2171 /// or 64-bit immediate, and if the value can be accurately represented as a
2172 /// sign extension from a 16-bit value. If so, this returns true and the
2173 /// immediate.
2174 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2175  if (!isa<ConstantSDNode>(N))
2176  return false;
2177 
2178  Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2179  if (N->getValueType(0) == MVT::i32)
2180  return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2181  else
2182  return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2183 }
2184 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2185  return isIntS16Immediate(Op.getNode(), Imm);
2186 }
2187 
2188 /// SelectAddressRegReg - Given the specified addressed, check to see if it
2189 /// can be represented as an indexed [r+r] operation. Returns false if it
2190 /// can be more efficiently represented with [r+imm].
2192  SDValue &Index,
2193  SelectionDAG &DAG) const {
2194  int16_t imm = 0;
2195  if (N.getOpcode() == ISD::ADD) {
2196  if (isIntS16Immediate(N.getOperand(1), imm))
2197  return false; // r+i
2198  if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2199  return false; // r+i
2200 
2201  Base = N.getOperand(0);
2202  Index = N.getOperand(1);
2203  return true;
2204  } else if (N.getOpcode() == ISD::OR) {
2205  if (isIntS16Immediate(N.getOperand(1), imm))
2206  return false; // r+i can fold it if we can.
2207 
2208  // If this is an or of disjoint bitfields, we can codegen this as an add
2209  // (for better address arithmetic) if the LHS and RHS of the OR are provably
2210  // disjoint.
2211  KnownBits LHSKnown, RHSKnown;
2212  DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2213 
2214  if (LHSKnown.Zero.getBoolValue()) {
2215  DAG.computeKnownBits(N.getOperand(1), RHSKnown);
2216  // If all of the bits are known zero on the LHS or RHS, the add won't
2217  // carry.
2218  if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2219  Base = N.getOperand(0);
2220  Index = N.getOperand(1);
2221  return true;
2222  }
2223  }
2224  }
2225 
2226  return false;
2227 }
2228 
2229 // If we happen to be doing an i64 load or store into a stack slot that has
2230 // less than a 4-byte alignment, then the frame-index elimination may need to
2231 // use an indexed load or store instruction (because the offset may not be a
2232 // multiple of 4). The extra register needed to hold the offset comes from the
2233 // register scavenger, and it is possible that the scavenger will need to use
2234 // an emergency spill slot. As a result, we need to make sure that a spill slot
2235 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2236 // stack slot.
2237 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2238  // FIXME: This does not handle the LWA case.
2239  if (VT != MVT::i64)
2240  return;
2241 
2242  // NOTE: We'll exclude negative FIs here, which come from argument
2243  // lowering, because there are no known test cases triggering this problem
2244  // using packed structures (or similar). We can remove this exclusion if
2245  // we find such a test case. The reason why this is so test-case driven is
2246  // because this entire 'fixup' is only to prevent crashes (from the
2247  // register scavenger) on not-really-valid inputs. For example, if we have:
2248  // %a = alloca i1
2249  // %b = bitcast i1* %a to i64*
2250  // store i64* a, i64 b
2251  // then the store should really be marked as 'align 1', but is not. If it
2252  // were marked as 'align 1' then the indexed form would have been
2253  // instruction-selected initially, and the problem this 'fixup' is preventing
2254  // won't happen regardless.
2255  if (FrameIdx < 0)
2256  return;
2257 
2258  MachineFunction &MF = DAG.getMachineFunction();
2259  MachineFrameInfo &MFI = MF.getFrameInfo();
2260 
2261  unsigned Align = MFI.getObjectAlignment(FrameIdx);
2262  if (Align >= 4)
2263  return;
2264 
2265  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2266  FuncInfo->setHasNonRISpills();
2267 }
2268 
2269 /// Returns true if the address N can be represented by a base register plus
2270 /// a signed 16-bit displacement [r+imm], and if it is not better
2271 /// represented as reg+reg. If \p Alignment is non-zero, only accept
2272 /// displacements that are multiples of that value.
2274  SDValue &Base,
2275  SelectionDAG &DAG,
2276  unsigned Alignment) const {
2277  // FIXME dl should come from parent load or store, not from address
2278  SDLoc dl(N);
2279  // If this can be more profitably realized as r+r, fail.
2280  if (SelectAddressRegReg(N, Disp, Base, DAG))
2281  return false;
2282 
2283  if (N.getOpcode() == ISD::ADD) {
2284  int16_t imm = 0;
2285  if (isIntS16Immediate(N.getOperand(1), imm) &&
2286  (!Alignment || (imm % Alignment) == 0)) {
2287  Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2288  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2289  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2290  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2291  } else {
2292  Base = N.getOperand(0);
2293  }
2294  return true; // [r+i]
2295  } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2296  // Match LOAD (ADD (X, Lo(G))).
2297  assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
2298  && "Cannot handle constant offsets yet!");
2299  Disp = N.getOperand(1).getOperand(0); // The global address.
2300  assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
2301  Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
2302  Disp.getOpcode() == ISD::TargetConstantPool ||
2303  Disp.getOpcode() == ISD::TargetJumpTable);
2304  Base = N.getOperand(0);
2305  return true; // [&g+r]
2306  }
2307  } else if (N.getOpcode() == ISD::OR) {
2308  int16_t imm = 0;
2309  if (isIntS16Immediate(N.getOperand(1), imm) &&
2310  (!Alignment || (imm % Alignment) == 0)) {
2311  // If this is an or of disjoint bitfields, we can codegen this as an add
2312  // (for better address arithmetic) if the LHS and RHS of the OR are
2313  // provably disjoint.
2314  KnownBits LHSKnown;
2315  DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2316 
2317  if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2318  // If all of the bits are known zero on the LHS or RHS, the add won't
2319  // carry.
2320  if (FrameIndexSDNode *FI =
2321  dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2322  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2323  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2324  } else {
2325  Base = N.getOperand(0);
2326  }
2327  Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2328  return true;
2329  }
2330  }
2331  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2332  // Loading from a constant address.
2333 
2334  // If this address fits entirely in a 16-bit sext immediate field, codegen
2335  // this as "d, 0"
2336  int16_t Imm;
2337  if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
2338  Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2339  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2340  CN->getValueType(0));
2341  return true;
2342  }
2343 
2344  // Handle 32-bit sext immediates with LIS + addr mode.
2345  if ((CN->getValueType(0) == MVT::i32 ||
2346  (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2347  (!Alignment || (CN->getZExtValue() % Alignment) == 0)) {
2348  int Addr = (int)CN->getZExtValue();
2349 
2350  // Otherwise, break this down into an LIS + disp.
2351  Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2352 
2353  Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2354  MVT::i32);
2355  unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2356  Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2357  return true;
2358  }
2359  }
2360 
2361  Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2362  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2363  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2364  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2365  } else
2366  Base = N;
2367  return true; // [r+0]
2368 }
2369 
2370 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2371 /// represented as an indexed [r+r] operation.
2373  SDValue &Index,
2374  SelectionDAG &DAG) const {
2375  // Check to see if we can easily represent this as an [r+r] address. This
2376  // will fail if it thinks that the address is more profitably represented as
2377  // reg+imm, e.g. where imm = 0.
2378  if (SelectAddressRegReg(N, Base, Index, DAG))
2379  return true;
2380 
2381  // If the address is the result of an add, we will utilize the fact that the
2382  // address calculation includes an implicit add. However, we can reduce
2383  // register pressure if we do not materialize a constant just for use as the
2384  // index register. We only get rid of the add if it is not an add of a
2385  // value and a 16-bit signed constant and both have a single use.
2386  int16_t imm = 0;
2387  if (N.getOpcode() == ISD::ADD &&
2388  (!isIntS16Immediate(N.getOperand(1), imm) ||
2389  !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2390  Base = N.getOperand(0);
2391  Index = N.getOperand(1);
2392  return true;
2393  }
2394 
2395  // Otherwise, do it the hard way, using R0 as the base register.
2396  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2397  N.getValueType());
2398  Index = N;
2399  return true;
2400 }
2401 
2402 /// Returns true if we should use a direct load into vector instruction
2403 /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2405  if (!N->hasOneUse())
2406  return false;
2407 
2408  // If there are any other uses other than scalar to vector, then we should
2409  // keep it as a scalar load -> direct move pattern to prevent multiple
2410  // loads. Currently, only check for i64 since we have lxsd/lfd to do this
2411  // efficiently, but no update equivalent.
2412  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2413  EVT MemVT = LD->getMemoryVT();
2414  if (MemVT.isSimple() && MemVT.getSimpleVT().SimpleTy == MVT::i64) {
2415  SDNode *User = *(LD->use_begin());
2416  if (User->getOpcode() == ISD::SCALAR_TO_VECTOR)
2417  return true;
2418  }
2419  }
2420 
2421  return false;
2422 }
2423 
2424 /// getPreIndexedAddressParts - returns true by value, base pointer and
2425 /// offset pointer and addressing mode by reference if the node's address
2426 /// can be legally represented as pre-indexed load / store address.
2428  SDValue &Offset,
2429  ISD::MemIndexedMode &AM,
2430  SelectionDAG &DAG) const {
2431  if (DisablePPCPreinc) return false;
2432 
2433  bool isLoad = true;
2434  SDValue Ptr;
2435  EVT VT;
2436  unsigned Alignment;
2437  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2438  Ptr = LD->getBasePtr();
2439  VT = LD->getMemoryVT();
2440  Alignment = LD->getAlignment();
2441  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2442  Ptr = ST->getBasePtr();
2443  VT = ST->getMemoryVT();
2444  Alignment = ST->getAlignment();
2445  isLoad = false;
2446  } else
2447  return false;
2448 
2449  // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2450  // instructions because we can fold these into a more efficient instruction
2451  // instead, (such as LXSD).
2452  if (isLoad && usePartialVectorLoads(N)) {
2453  return false;
2454  }
2455 
2456  // PowerPC doesn't have preinc load/store instructions for vectors (except
2457  // for QPX, which does have preinc r+r forms).
2458  if (VT.isVector()) {
2459  if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2460  return false;
2461  } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2462  AM = ISD::PRE_INC;
2463  return true;
2464  }
2465  }
2466 
2467  if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2468  // Common code will reject creating a pre-inc form if the base pointer
2469  // is a frame index, or if N is a store and the base pointer is either
2470  // the same as or a predecessor of the value being stored. Check for
2471  // those situations here, and try with swapped Base/Offset instead.
2472  bool Swap = false;
2473 
2474  if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2475  Swap = true;
2476  else if (!isLoad) {
2477  SDValue Val = cast<StoreSDNode>(N)->getValue();
2478  if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2479  Swap = true;
2480  }
2481 
2482  if (Swap)
2483  std::swap(Base, Offset);
2484 
2485  AM = ISD::PRE_INC;
2486  return true;
2487  }
2488 
2489  // LDU/STU can only handle immediates that are a multiple of 4.
2490  if (VT != MVT::i64) {
2491  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2492  return false;
2493  } else {
2494  // LDU/STU need an address with at least 4-byte alignment.
2495  if (Alignment < 4)
2496  return false;
2497 
2498  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2499  return false;
2500  }
2501 
2502  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2503  // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2504  // sext i32 to i64 when addr mode is r+i.
2505  if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2506  LD->getExtensionType() == ISD::SEXTLOAD &&
2507  isa<ConstantSDNode>(Offset))
2508  return false;
2509  }
2510 
2511  AM = ISD::PRE_INC;
2512  return true;
2513 }
2514 
2515 //===----------------------------------------------------------------------===//
2516 // LowerOperation implementation
2517 //===----------------------------------------------------------------------===//
2518 
2519 /// Return true if we should reference labels using a PICBase, set the HiOpFlags
2520 /// and LoOpFlags to the target MO flags.
2521 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2522  unsigned &HiOpFlags, unsigned &LoOpFlags,
2523  const GlobalValue *GV = nullptr) {
2524  HiOpFlags = PPCII::MO_HA;
2525  LoOpFlags = PPCII::MO_LO;
2526 
2527  // Don't use the pic base if not in PIC relocation model.
2528  if (IsPIC) {
2529  HiOpFlags |= PPCII::MO_PIC_FLAG;
2530  LoOpFlags |= PPCII::MO_PIC_FLAG;
2531  }
2532 
2533  // If this is a reference to a global value that requires a non-lazy-ptr, make
2534  // sure that instruction lowering adds it.
2535  if (GV && Subtarget.hasLazyResolverStub(GV)) {
2536  HiOpFlags |= PPCII::MO_NLP_FLAG;
2537  LoOpFlags |= PPCII::MO_NLP_FLAG;
2538 
2539  if (GV->hasHiddenVisibility()) {
2540  HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2541  LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2542  }
2543  }
2544 }
2545 
2546 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2547  SelectionDAG &DAG) {
2548  SDLoc DL(HiPart);
2549  EVT PtrVT = HiPart.getValueType();
2550  SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2551 
2552  SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2553  SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2554 
2555  // With PIC, the first instruction is actually "GR+hi(&G)".
2556  if (isPIC)
2557  Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2558  DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2559 
2560  // Generate non-pic code that has direct accesses to the constant pool.
2561  // The address of the global is just (hi(&g)+lo(&g)).
2562  return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2563 }
2564 
2566  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2567  FuncInfo->setUsesTOCBasePtr();
2568 }
2569 
2570 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2572 }
2573 
2574 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2575  SDValue GA) {
2576  EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2577  SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2578  DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2579 
2580  SDValue Ops[] = { GA, Reg };
2581  return DAG.getMemIntrinsicNode(
2582  PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2585 }
2586 
2587 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2588  SelectionDAG &DAG) const {
2589  EVT PtrVT = Op.getValueType();
2590  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2591  const Constant *C = CP->getConstVal();
2592 
2593  // 64-bit SVR4 ABI code is always position-independent.
2594  // The actual address of the GlobalValue is stored in the TOC.
2595  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2596  setUsesTOCBasePtr(DAG);
2597  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2598  return getTOCEntry(DAG, SDLoc(CP), true, GA);
2599  }
2600 
2601  unsigned MOHiFlag, MOLoFlag;
2602  bool IsPIC = isPositionIndependent();
2603  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2604 
2605  if (IsPIC && Subtarget.isSVR4ABI()) {
2606  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2608  return getTOCEntry(DAG, SDLoc(CP), false, GA);
2609  }
2610 
2611  SDValue CPIHi =
2612  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2613  SDValue CPILo =
2614  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2615  return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2616 }
2617 
2618 // For 64-bit PowerPC, prefer the more compact relative encodings.
2619 // This trades 32 bits per jump table entry for one or two instructions
2620 // on the jump site.
2622  if (isJumpTableRelative())
2624 
2626 }
2627 
2629  if (Subtarget.isPPC64())
2630  return true;
2632 }
2633 
2635  SelectionDAG &DAG) const {
2636  if (!Subtarget.isPPC64())
2637  return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2638 
2639  switch (getTargetMachine().getCodeModel()) {
2640  case CodeModel::Small:
2641  case CodeModel::Medium:
2642  return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2643  default:
2644  return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2645  getPointerTy(DAG.getDataLayout()));
2646  }
2647 }
2648 
2649 const MCExpr *
2651  unsigned JTI,
2652  MCContext &Ctx) const {
2653  if (!Subtarget.isPPC64())
2654  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2655 
2656  switch (getTargetMachine().getCodeModel()) {
2657  case CodeModel::Small:
2658  case CodeModel::Medium:
2659  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2660  default:
2661  return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2662  }
2663 }
2664 
2665 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2666  EVT PtrVT = Op.getValueType();
2667  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2668 
2669  // 64-bit SVR4 ABI code is always position-independent.
2670  // The actual address of the GlobalValue is stored in the TOC.
2671  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2672  setUsesTOCBasePtr(DAG);
2673  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2674  return getTOCEntry(DAG, SDLoc(JT), true, GA);
2675  }
2676 
2677  unsigned MOHiFlag, MOLoFlag;
2678  bool IsPIC = isPositionIndependent();
2679  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2680 
2681  if (IsPIC && Subtarget.isSVR4ABI()) {
2682  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2684  return getTOCEntry(DAG, SDLoc(GA), false, GA);
2685  }
2686 
2687  SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2688  SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2689  return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2690 }
2691 
2692 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2693  SelectionDAG &DAG) const {
2694  EVT PtrVT = Op.getValueType();
2695  BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2696  const BlockAddress *BA = BASDN->getBlockAddress();
2697 
2698  // 64-bit SVR4 ABI code is always position-independent.
2699  // The actual BlockAddress is stored in the TOC.
2700  if (Subtarget.isSVR4ABI() &&
2701  (Subtarget.isPPC64() || isPositionIndependent())) {
2702  if (Subtarget.isPPC64())
2703  setUsesTOCBasePtr(DAG);
2704  SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2705  return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA);
2706  }
2707 
2708  unsigned MOHiFlag, MOLoFlag;
2709  bool IsPIC = isPositionIndependent();
2710  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2711  SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2712  SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2713  return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2714 }
2715 
2716 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2717  SelectionDAG &DAG) const {
2718  // FIXME: TLS addresses currently use medium model code sequences,
2719  // which is the most useful form. Eventually support for small and
2720  // large models could be added if users need it, at the cost of
2721  // additional complexity.
2722  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2723  if (DAG.getTarget().useEmulatedTLS())
2724  return LowerToTLSEmulatedModel(GA, DAG);
2725 
2726  SDLoc dl(GA);
2727  const GlobalValue *GV = GA->getGlobal();
2728  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2729  bool is64bit = Subtarget.isPPC64();
2730  const Module *M = DAG.getMachineFunction().getFunction().getParent();
2731  PICLevel::Level picLevel = M->getPICLevel();
2732 
2734 
2735  if (Model == TLSModel::LocalExec) {
2736  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2738  SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2740  SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2741  : DAG.getRegister(PPC::R2, MVT::i32);
2742 
2743  SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2744  return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2745  }
2746 
2747  if (Model == TLSModel::InitialExec) {
2748  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2749  SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2750  PPCII::MO_TLS);
2751  SDValue GOTPtr;
2752  if (is64bit) {
2753  setUsesTOCBasePtr(DAG);
2754  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2755  GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2756  PtrVT, GOTReg, TGA);
2757  } else
2758  GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2759  SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2760  PtrVT, TGA, GOTPtr);
2761  return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2762  }
2763 
2764  if (Model == TLSModel::GeneralDynamic) {
2765  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2766  SDValue GOTPtr;
2767  if (is64bit) {
2768  setUsesTOCBasePtr(DAG);
2769  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2770  GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2771  GOTReg, TGA);
2772  } else {
2773  if (picLevel == PICLevel::SmallPIC)
2774  GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2775  else
2776  GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2777  }
2778  return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2779  GOTPtr, TGA, TGA);
2780  }
2781 
2782  if (Model == TLSModel::LocalDynamic) {
2783  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2784  SDValue GOTPtr;
2785  if (is64bit) {
2786  setUsesTOCBasePtr(DAG);
2787  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2788  GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2789  GOTReg, TGA);
2790  } else {
2791  if (picLevel == PICLevel::SmallPIC)
2792  GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2793  else
2794  GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2795  }
2796  SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2797  PtrVT, GOTPtr, TGA, TGA);
2798  SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2799  PtrVT, TLSAddr, TGA);
2800  return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2801  }
2802 
2803  llvm_unreachable("Unknown TLS model!");
2804 }
2805 
2806 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2807  SelectionDAG &DAG) const {
2808  EVT PtrVT = Op.getValueType();
2809  GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2810  SDLoc DL(GSDN);
2811  const GlobalValue *GV = GSDN->getGlobal();
2812 
2813  // 64-bit SVR4 ABI code is always position-independent.
2814  // The actual address of the GlobalValue is stored in the TOC.
2815  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2816  setUsesTOCBasePtr(DAG);
2817  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2818  return getTOCEntry(DAG, DL, true, GA);
2819  }
2820 
2821  unsigned MOHiFlag, MOLoFlag;
2822  bool IsPIC = isPositionIndependent();
2823  getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2824 
2825  if (IsPIC && Subtarget.isSVR4ABI()) {
2826  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2827  GSDN->getOffset(),
2829  return getTOCEntry(DAG, DL, false, GA);
2830  }
2831 
2832  SDValue GAHi =
2833  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2834  SDValue GALo =
2835  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2836 
2837  SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2838 
2839  // If the global reference is actually to a non-lazy-pointer, we have to do an
2840  // extra load to get the address of the global.
2841  if (MOHiFlag & PPCII::MO_NLP_FLAG)
2842  Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2843  return Ptr;
2844 }
2845 
2846 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2847  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2848  SDLoc dl(Op);
2849 
2850  if (Op.getValueType() == MVT::v2i64) {
2851  // When the operands themselves are v2i64 values, we need to do something
2852  // special because VSX has no underlying comparison operations for these.
2853  if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2854  // Equality can be handled by casting to the legal type for Altivec
2855  // comparisons, everything else needs to be expanded.
2856  if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2857  return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2858  DAG.getSetCC(dl, MVT::v4i32,
2859  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2860  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2861  CC));
2862  }
2863 
2864  return SDValue();
2865  }
2866 
2867  // We handle most of these in the usual way.
2868  return Op;
2869  }
2870 
2871  // If we're comparing for equality to zero, expose the fact that this is
2872  // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2873  // fold the new nodes.
2874  if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2875  return V;
2876 
2877  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2878  // Leave comparisons against 0 and -1 alone for now, since they're usually
2879  // optimized. FIXME: revisit this when we can custom lower all setcc
2880  // optimizations.
2881  if (C->isAllOnesValue() || C->isNullValue())
2882  return SDValue();
2883  }
2884 
2885  // If we have an integer seteq/setne, turn it into a compare against zero
2886  // by xor'ing the rhs with the lhs, which is faster than setting a
2887  // condition register, reading it back out, and masking the correct bit. The
2888  // normal approach here uses sub to do this instead of xor. Using xor exposes
2889  // the result to other bit-twiddling opportunities.
2890  EVT LHSVT = Op.getOperand(0).getValueType();
2891  if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2892  EVT VT = Op.getValueType();
2893  SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2894  Op.getOperand(1));
2895  return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2896  }
2897  return SDValue();
2898 }
2899 
2900 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2901  SDNode *Node = Op.getNode();
2902  EVT VT = Node->getValueType(0);
2903  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2904  SDValue InChain = Node->getOperand(0);
2905  SDValue VAListPtr = Node->getOperand(1);
2906  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2907  SDLoc dl(Node);
2908 
2909  assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2910 
2911  // gpr_index
2912  SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2913  VAListPtr, MachinePointerInfo(SV), MVT::i8);
2914  InChain = GprIndex.getValue(1);
2915 
2916  if (VT == MVT::i64) {
2917  // Check if GprIndex is even
2918  SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2919  DAG.getConstant(1, dl, MVT::i32));
2920  SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2921  DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2922  SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2923  DAG.getConstant(1, dl, MVT::i32));
2924  // Align GprIndex to be even if it isn't
2925  GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2926  GprIndex);
2927  }
2928 
2929  // fpr index is 1 byte after gpr
2930  SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2931  DAG.getConstant(1, dl, MVT::i32));
2932 
2933  // fpr
2934  SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2935  FprPtr, MachinePointerInfo(SV), MVT::i8);
2936  InChain = FprIndex.getValue(1);
2937 
2938  SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2939  DAG.getConstant(8, dl, MVT::i32));
2940 
2941  SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2942  DAG.getConstant(4, dl, MVT::i32));
2943 
2944  // areas
2945  SDValue OverflowArea =
2946  DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2947  InChain = OverflowArea.getValue(1);
2948 
2949  SDValue RegSaveArea =
2950  DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2951  InChain = RegSaveArea.getValue(1);
2952 
2953  // select overflow_area if index > 8
2954  SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2955  DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2956 
2957  // adjustment constant gpr_index * 4/8
2958  SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2959  VT.isInteger() ? GprIndex : FprIndex,
2960  DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2961  MVT::i32));
2962 
2963  // OurReg = RegSaveArea + RegConstant
2964  SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2965  RegConstant);
2966 
2967  // Floating types are 32 bytes into RegSaveArea
2968  if (VT.isFloatingPoint())
2969  OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2970  DAG.getConstant(32, dl, MVT::i32));
2971 
2972  // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2973  SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2974  VT.isInteger() ? GprIndex : FprIndex,
2975  DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2976  MVT::i32));
2977 
2978  InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2979  VT.isInteger() ? VAListPtr : FprPtr,
2981 
2982  // determine if we should load from reg_save_area or overflow_area
2983  SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2984 
2985  // increase overflow_area by 4/8 if gpr/fpr > 8
2986  SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2987  DAG.getConstant(VT.isInteger() ? 4 : 8,
2988  dl, MVT::i32));
2989 
2990  OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2991  OverflowAreaPlusN);
2992 
2993  InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
2995 
2996  return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
2997 }
2998 
2999 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3000  assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
3001 
3002  // We have to copy the entire va_list struct:
3003  // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3004  return DAG.getMemcpy(Op.getOperand(0), Op,
3005  Op.getOperand(1), Op.getOperand(2),
3006  DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
3008 }
3009 
3010 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3011  SelectionDAG &DAG) const {
3012  return Op.getOperand(0);
3013 }
3014 
3015 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3016  SelectionDAG &DAG) const {
3017  SDValue Chain = Op.getOperand(0);
3018  SDValue Trmp = Op.getOperand(1); // trampoline
3019  SDValue FPtr = Op.getOperand(2); // nested function
3020  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3021  SDLoc dl(Op);
3022 
3023  EVT PtrVT = getPointerTy(DAG.getDataLayout());
3024  bool isPPC64 = (PtrVT == MVT::i64);
3025  Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3026 
3029 
3030  Entry.Ty = IntPtrTy;
3031  Entry.Node = Trmp; Args.push_back(Entry);
3032 
3033  // TrampSize == (isPPC64 ? 48 : 40);
3034  Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3035  isPPC64 ? MVT::i64 : MVT::i32);
3036  Args.push_back(Entry);
3037 
3038  Entry.Node = FPtr; Args.push_back(Entry);
3039  Entry.Node = Nest; Args.push_back(Entry);
3040 
3041  // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3043  CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3045  DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3046 
3047  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3048  return CallResult.second;
3049 }
3050 
3051 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3052  MachineFunction &MF = DAG.getMachineFunction();
3053  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3054  EVT PtrVT = getPointerTy(MF.getDataLayout());
3055 
3056  SDLoc dl(Op);
3057 
3058  if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
3059  // vastart just stores the address of the VarArgsFrameIndex slot into the
3060  // memory location argument.
3061  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3062  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3063  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3064  MachinePointerInfo(SV));
3065  }
3066 
3067  // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3068  // We suppose the given va_list is already allocated.
3069  //
3070  // typedef struct {
3071  // char gpr; /* index into the array of 8 GPRs
3072  // * stored in the register save area
3073  // * gpr=0 corresponds to r3,
3074  // * gpr=1 to r4, etc.
3075  // */
3076  // char fpr; /* index into the array of 8 FPRs
3077  // * stored in the register save area
3078  // * fpr=0 corresponds to f1,
3079  // * fpr=1 to f2, etc.
3080  // */
3081  // char *overflow_arg_area;
3082  // /* location on stack that holds
3083  // * the next overflow argument
3084  // */
3085  // char *reg_save_area;
3086  // /* where r3:r10 and f1:f8 (if saved)
3087  // * are stored
3088  // */
3089  // } va_list[1];
3090 
3091  SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3092  SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3093  SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3094  PtrVT);
3095  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3096  PtrVT);
3097 
3098  uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3099  SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3100 
3101  uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3102  SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3103 
3104  uint64_t FPROffset = 1;
3105  SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3106 
3107  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3108 
3109  // Store first byte : number of int regs
3110  SDValue firstStore =
3111  DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3113  uint64_t nextOffset = FPROffset;
3114  SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3115  ConstFPROffset);
3116 
3117  // Store second byte : number of float regs
3118  SDValue secondStore =
3119  DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3120  MachinePointerInfo(SV, nextOffset), MVT::i8);
3121  nextOffset += StackOffset;
3122  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3123 
3124  // Store second word : arguments given on stack
3125  SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3126  MachinePointerInfo(SV, nextOffset));
3127  nextOffset += FrameOffset;
3128  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3129 
3130  // Store third word : arguments given in registers
3131  return DAG.getStore(thirdStore, dl, FR, nextPtr,
3132  MachinePointerInfo(SV, nextOffset));
3133 }
3134 
3135 #include "PPCGenCallingConv.inc"
3136 
3137 // Function whose sole purpose is to kill compiler warnings
3138 // stemming from unused functions included from PPCGenCallingConv.inc.
3139 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
3140  return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
3141 }
3142 
3143 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
3144  CCValAssign::LocInfo &LocInfo,
3145  ISD::ArgFlagsTy &ArgFlags,
3146  CCState &State) {
3147  return true;
3148 }
3149 
3150 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
3151  MVT &LocVT,
3152  CCValAssign::LocInfo &LocInfo,
3153  ISD::ArgFlagsTy &ArgFlags,
3154  CCState &State) {
3155  static const MCPhysReg ArgRegs[] = {
3156  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3157  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3158  };
3159  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3160 
3161  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3162 
3163  // Skip one register if the first unallocated register has an even register
3164  // number and there are still argument registers available which have not been
3165  // allocated yet. RegNum is actually an index into ArgRegs, which means we
3166  // need to skip a register if RegNum is odd.
3167  if (RegNum != NumArgRegs && RegNum % 2 == 1) {
3168  State.AllocateReg(ArgRegs[RegNum]);
3169  }
3170 
3171  // Always return false here, as this function only makes sure that the first
3172  // unallocated register has an odd register number and does not actually
3173  // allocate a register for the current argument.
3174  return false;
3175 }
3176 
3177 bool
3179  MVT &LocVT,
3180  CCValAssign::LocInfo &LocInfo,
3181  ISD::ArgFlagsTy &ArgFlags,
3182  CCState &State) {
3183  static const MCPhysReg ArgRegs[] = {
3184  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3185  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3186  };
3187  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3188 
3189  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3190  int RegsLeft = NumArgRegs - RegNum;
3191 
3192  // Skip if there is not enough registers left for long double type (4 gpr regs
3193  // in soft float mode) and put long double argument on the stack.
3194  if (RegNum != NumArgRegs && RegsLeft < 4) {
3195  for (int i = 0; i < RegsLeft; i++) {
3196  State.AllocateReg(ArgRegs[RegNum + i]);
3197  }
3198  }
3199 
3200  return false;
3201 }
3202 
3203 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
3204  MVT &LocVT,
3205  CCValAssign::LocInfo &LocInfo,
3206  ISD::ArgFlagsTy &ArgFlags,
3207  CCState &State) {
3208  static const MCPhysReg ArgRegs[] = {
3209  PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3210  PPC::F8
3211  };
3212 
3213  const unsigned NumArgRegs = array_lengthof(ArgRegs);
3214 
3215  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3216 
3217  // If there is only one Floating-point register left we need to put both f64
3218  // values of a split ppc_fp128 value on the stack.
3219  if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
3220  State.AllocateReg(ArgRegs[RegNum]);
3221  }
3222 
3223  // Always return false here, as this function only makes sure that the two f64
3224  // values a ppc_fp128 value is split into are both passed in registers or both
3225  // passed on the stack and does not actually allocate a register for the
3226  // current argument.
3227  return false;
3228 }
3229 
3230 /// FPR - The set of FP registers that should be allocated for arguments,
3231 /// on Darwin.
3232 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3233  PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3234  PPC::F11, PPC::F12, PPC::F13};
3235 
3236 /// QFPR - The set of QPX registers that should be allocated for arguments.
3237 static const MCPhysReg QFPR[] = {
3238  PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3239  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3240 
3241 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
3242 /// the stack.
3243 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3244  unsigned PtrByteSize) {
3245  unsigned ArgSize = ArgVT.getStoreSize();
3246  if (Flags.isByVal())
3247  ArgSize = Flags.getByValSize();
3248 
3249  // Round up to multiples of the pointer size, except for array members,
3250  // which are always packed.
3251  if (!Flags.isInConsecutiveRegs())
3252  ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3253 
3254  return ArgSize;
3255 }
3256 
3257 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
3258 /// on the stack.
3259 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3260  ISD::ArgFlagsTy Flags,
3261  unsigned PtrByteSize) {
3262  unsigned Align = PtrByteSize;
3263 
3264  // Altivec parameters are padded to a 16 byte boundary.
3265  if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3266  ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3267  ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3268  ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3269  Align = 16;
3270  // QPX vector types stored in double-precision are padded to a 32 byte
3271  // boundary.
3272  else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3273  Align = 32;
3274 
3275  // ByVal parameters are aligned as requested.
3276  if (Flags.isByVal()) {
3277  unsigned BVAlign = Flags.getByValAlign();
3278  if (BVAlign > PtrByteSize) {
3279  if (BVAlign % PtrByteSize != 0)
3281  "ByVal alignment is not a multiple of the pointer size");
3282 
3283  Align = BVAlign;
3284  }
3285  }
3286 
3287  // Array members are always packed to their original alignment.
3288  if (Flags.isInConsecutiveRegs()) {
3289  // If the array member was split into multiple registers, the first
3290  // needs to be aligned to the size of the full type. (Except for
3291  // ppcf128, which is only aligned as its f64 components.)
3292  if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3293  Align = OrigVT.getStoreSize();
3294  else
3295  Align = ArgVT.getStoreSize();
3296  }
3297 
3298  return Align;
3299 }
3300 
3301 /// CalculateStackSlotUsed - Return whether this argument will use its
3302 /// stack slot (instead of being passed in registers). ArgOffset,
3303 /// AvailableFPRs, and AvailableVRs must hold the current argument
3304 /// position, and will be updated to account for this argument.
3305 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3306  ISD::ArgFlagsTy Flags,
3307  unsigned PtrByteSize,
3308  unsigned LinkageSize,
3309  unsigned ParamAreaSize,
3310  unsigned &ArgOffset,
3311  unsigned &AvailableFPRs,
3312  unsigned &AvailableVRs, bool HasQPX) {
3313  bool UseMemory = false;
3314 
3315  // Respect alignment of argument on the stack.
3316  unsigned Align =
3317  CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3318  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3319  // If there's no space left in the argument save area, we must
3320  // use memory (this check also catches zero-sized arguments).
3321  if (ArgOffset >= LinkageSize + ParamAreaSize)
3322  UseMemory = true;
3323 
3324  // Allocate argument on the stack.
3325  ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3326  if (Flags.isInConsecutiveRegsLast())
3327  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3328  // If we overran the argument save area, we must use memory
3329  // (this check catches arguments passed partially in memory)
3330  if (ArgOffset > LinkageSize + ParamAreaSize)
3331  UseMemory = true;
3332 
3333  // However, if the argument is actually passed in an FPR or a VR,
3334  // we don't use memory after all.
3335  if (!Flags.isByVal()) {
3336  if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3337  // QPX registers overlap with the scalar FP registers.
3338  (HasQPX && (ArgVT == MVT::v4f32 ||
3339  ArgVT == MVT::v4f64 ||
3340  ArgVT == MVT::v4i1)))
3341  if (AvailableFPRs > 0) {
3342  --AvailableFPRs;
3343  return false;
3344  }
3345  if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3346  ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3347  ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3348  ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3349  if (AvailableVRs > 0) {
3350  --AvailableVRs;
3351  return false;
3352  }
3353  }
3354 
3355  return UseMemory;
3356 }
3357 
3358 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
3359 /// ensure minimum alignment required for target.
3361  unsigned NumBytes) {
3362  unsigned TargetAlign = Lowering->getStackAlignment();
3363  unsigned AlignMask = TargetAlign - 1;
3364  NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3365  return NumBytes;
3366 }
3367 
3368 SDValue PPCTargetLowering::LowerFormalArguments(
3369  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3370  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3371  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3372  if (Subtarget.isSVR4ABI()) {
3373  if (Subtarget.isPPC64())
3374  return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3375  dl, DAG, InVals);
3376  else
3377  return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3378  dl, DAG, InVals);
3379  } else {
3380  return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3381  dl, DAG, InVals);
3382  }
3383 }
3384 
3385 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3386  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3387  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3388  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3389 
3390  // 32-bit SVR4 ABI Stack Frame Layout:
3391  // +-----------------------------------+
3392  // +--> | Back chain |
3393  // | +-----------------------------------+
3394  // | | Floating-point register save area |
3395  // | +-----------------------------------+
3396  // | | General register save area |
3397  // | +-----------------------------------+
3398  // | | CR save word |
3399  // | +-----------------------------------+
3400  // | | VRSAVE save word |
3401  // | +-----------------------------------+
3402  // | | Alignment padding |
3403  // | +-----------------------------------+
3404  // | | Vector register save area |
3405  // | +-----------------------------------+
3406  // | | Local variable space |
3407  // | +-----------------------------------+
3408  // | | Parameter list area |
3409  // | +-----------------------------------+
3410  // | | LR save word |
3411  // | +-----------------------------------+
3412  // SP--> +--- | Back chain |
3413  // +-----------------------------------+
3414  //
3415  // Specifications:
3416  // System V Application Binary Interface PowerPC Processor Supplement
3417  // AltiVec Technology Programming Interface Manual
3418 
3419  MachineFunction &MF = DAG.getMachineFunction();
3420  MachineFrameInfo &MFI = MF.getFrameInfo();
3421  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3422 
3423  EVT PtrVT = getPointerTy(MF.getDataLayout());
3424  // Potential tail calls could cause overwriting of argument stack slots.
3425  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3426  (CallConv == CallingConv::Fast));
3427  unsigned PtrByteSize = 4;
3428 
3429  // Assign locations to all of the incoming arguments.
3431  PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3432  *DAG.getContext());
3433 
3434  // Reserve space for the linkage area on the stack.
3435  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3436  CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3437  if (useSoftFloat() || hasSPE())
3438  CCInfo.PreAnalyzeFormalArguments(Ins);
3439 
3440  CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3441  CCInfo.clearWasPPCF128();
3442 
3443  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3444  CCValAssign &VA = ArgLocs[i];
3445 
3446  // Arguments stored in registers.
3447  if (VA.isRegLoc()) {
3448  const TargetRegisterClass *RC;
3449  EVT ValVT = VA.getValVT();
3450 
3451  switch (ValVT.getSimpleVT().SimpleTy) {
3452  default:
3453  llvm_unreachable("ValVT not supported by formal arguments Lowering");
3454  case MVT::i1:
3455  case MVT::i32:
3456  RC = &PPC::GPRCRegClass;
3457  break;
3458  case MVT::f32:
3459  if (Subtarget.hasP8Vector())
3460  RC = &PPC::VSSRCRegClass;
3461  else if (Subtarget.hasSPE())
3462  RC = &PPC::SPE4RCRegClass;
3463  else
3464  RC = &PPC::F4RCRegClass;
3465  break;
3466  case MVT::f64:
3467  if (Subtarget.hasVSX())
3468  RC = &PPC::VSFRCRegClass;
3469  else if (Subtarget.hasSPE())
3470  RC = &PPC::SPERCRegClass;
3471  else
3472  RC = &PPC::F8RCRegClass;
3473  break;
3474  case MVT::v16i8:
3475  case MVT::v8i16:
3476  case MVT::v4i32:
3477  RC = &PPC::VRRCRegClass;
3478  break;
3479  case MVT::v4f32:
3480  RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3481  break;
3482  case MVT::v2f64:
3483  case MVT::v2i64:
3484  RC = &PPC::VRRCRegClass;
3485  break;
3486  case MVT::v4f64:
3487  RC = &PPC::QFRCRegClass;
3488  break;
3489  case MVT::v4i1:
3490  RC = &PPC::QBRCRegClass;
3491  break;
3492  }
3493 
3494  // Transform the arguments stored in physical registers into virtual ones.
3495  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3496  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3497  ValVT == MVT::i1 ? MVT::i32 : ValVT);
3498 
3499  if (ValVT == MVT::i1)
3500  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3501 
3502  InVals.push_back(ArgValue);
3503  } else {
3504  // Argument stored in memory.
3505  assert(VA.isMemLoc());
3506 
3507  // Get the extended size of the argument type in stack
3508  unsigned ArgSize = VA.getLocVT().getStoreSize();
3509  // Get the actual size of the argument type
3510  unsigned ObjSize = VA.getValVT().getStoreSize();
3511  unsigned ArgOffset = VA.getLocMemOffset();
3512  // Stack objects in PPC32 are right justified.
3513  ArgOffset += ArgSize - ObjSize;
3514  int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3515 
3516  // Create load nodes to retrieve arguments from the stack.
3517  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3518  InVals.push_back(
3519  DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3520  }
3521  }
3522 
3523  // Assign locations to all of the incoming aggregate by value arguments.
3524  // Aggregates passed by value are stored in the local variable space of the
3525  // caller's stack frame, right above the parameter list area.
3526  SmallVector<CCValAssign, 16> ByValArgLocs;
3527  CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3528  ByValArgLocs, *DAG.getContext());
3529 
3530  // Reserve stack space for the allocations in CCInfo.
3531  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3532 
3533  CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3534 
3535  // Area that is at least reserved in the caller of this function.
3536  unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3537  MinReservedArea = std::max(MinReservedArea, LinkageSize);
3538 
3539  // Set the size that is at least reserved in caller of this function. Tail
3540  // call optimized function's reserved stack space needs to be aligned so that
3541  // taking the difference between two stack areas will result in an aligned
3542  // stack.
3543  MinReservedArea =
3544  EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3545  FuncInfo->setMinReservedArea(MinReservedArea);
3546 
3547  SmallVector<SDValue, 8> MemOps;
3548 
3549  // If the function takes variable number of arguments, make a frame index for
3550  // the start of the first vararg value... for expansion of llvm.va_start.
3551  if (isVarArg) {
3552  static const MCPhysReg GPArgRegs[] = {
3553  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3554  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3555  };
3556  const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3557 
3558  static const MCPhysReg FPArgRegs[] = {
3559  PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3560  PPC::F8
3561  };
3562  unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3563 
3564  if (useSoftFloat() || hasSPE())
3565  NumFPArgRegs = 0;
3566 
3567  FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3568  FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3569 
3570  // Make room for NumGPArgRegs and NumFPArgRegs.
3571  int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3572  NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3573 
3574  FuncInfo->setVarArgsStackOffset(
3575  MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3576  CCInfo.getNextStackOffset(), true));
3577 
3578  FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3579  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3580 
3581  // The fixed integer arguments of a variadic function are stored to the
3582  // VarArgsFrameIndex on the stack so that they may be loaded by
3583  // dereferencing the result of va_next.
3584  for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3585  // Get an existing live-in vreg, or add a new one.
3586  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3587  if (!VReg)
3588  VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3589 
3590  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3591  SDValue Store =
3592  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3593  MemOps.push_back(Store);
3594  // Increment the address by four for the next argument to store
3595  SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3596  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3597  }
3598 
3599  // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3600  // is set.
3601  // The double arguments are stored to the VarArgsFrameIndex
3602  // on the stack.
3603  for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3604  // Get an existing live-in vreg, or add a new one.
3605  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3606  if (!VReg)
3607  VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3608 
3609  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3610  SDValue Store =
3611  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3612  MemOps.push_back(Store);
3613  // Increment the address by eight for the next argument to store
3614  SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3615  PtrVT);
3616  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3617  }
3618  }
3619 
3620  if (!MemOps.empty())
3621  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3622 
3623  return Chain;
3624 }
3625 
3626 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3627 // value to MVT::i64 and then truncate to the correct register size.
3628 SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3629  EVT ObjectVT, SelectionDAG &DAG,
3630  SDValue ArgVal,
3631  const SDLoc &dl) const {
3632  if (Flags.isSExt())
3633  ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3634  DAG.getValueType(ObjectVT));
3635  else if (Flags.isZExt())
3636  ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3637  DAG.getValueType(ObjectVT));
3638 
3639  return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3640 }
3641 
3642 SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3643  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3644  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3645  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3646  // TODO: add description of PPC stack frame format, or at least some docs.
3647  //
3648  bool isELFv2ABI = Subtarget.isELFv2ABI();
3649  bool isLittleEndian = Subtarget.isLittleEndian();
3650  MachineFunction &MF = DAG.getMachineFunction();
3651  MachineFrameInfo &MFI = MF.getFrameInfo();
3652  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3653 
3654  assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3655  "fastcc not supported on varargs functions");
3656 
3657  EVT PtrVT = getPointerTy(MF.getDataLayout());
3658  // Potential tail calls could cause overwriting of argument stack slots.
3659  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3660  (CallConv == CallingConv::Fast));
3661  unsigned PtrByteSize = 8;
3662  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3663 
3664  static const MCPhysReg GPR[] = {
3665  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3666  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3667  };
3668  static const MCPhysReg VR[] = {
3669  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3670  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3671  };
3672 
3673  const unsigned Num_GPR_Regs = array_lengthof(GPR);
3674  const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3675  const unsigned Num_VR_Regs = array_lengthof(VR);
3676  const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3677 
3678  // Do a first pass over the arguments to determine whether the ABI
3679  // guarantees that our caller has allocated the parameter save area
3680  // on its stack frame. In the ELFv1 ABI, this is always the case;
3681  // in the ELFv2 ABI, it is true if this is a vararg function or if
3682  // any parameter is located in a stack slot.
3683 
3684  bool HasParameterArea = !isELFv2ABI || isVarArg;
3685  unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3686  unsigned NumBytes = LinkageSize;
3687  unsigned AvailableFPRs = Num_FPR_Regs;
3688  unsigned AvailableVRs = Num_VR_Regs;
3689  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3690  if (Ins[i].Flags.isNest())
3691  continue;
3692 
3693  if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3694  PtrByteSize, LinkageSize, ParamAreaSize,
3695  NumBytes, AvailableFPRs, AvailableVRs,
3696  Subtarget.hasQPX()))
3697  HasParameterArea = true;
3698  }
3699 
3700  // Add DAG nodes to load the arguments or copy them out of registers. On
3701  // entry to a function on PPC, the arguments start after the linkage area,
3702  // although the first ones are often in registers.
3703 
3704  unsigned ArgOffset = LinkageSize;
3705  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3706  unsigned &QFPR_idx = FPR_idx;
3707  SmallVector<SDValue, 8> MemOps;
3709  unsigned CurArgIdx = 0;
3710  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3711  SDValue ArgVal;
3712  bool needsLoad = false;
3713  EVT ObjectVT = Ins[ArgNo].VT;
3714  EVT OrigVT = Ins[ArgNo].ArgVT;
3715  unsigned ObjSize = ObjectVT.getStoreSize();
3716  unsigned ArgSize = ObjSize;
3717  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3718  if (Ins[ArgNo].isOrigArg()) {
3719  std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3720  CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3721  }
3722  // We re-align the argument offset for each argument, except when using the
3723  // fast calling convention, when we need to make sure we do that only when
3724  // we'll actually use a stack slot.
3725  unsigned CurArgOffset, Align;
3726  auto ComputeArgOffset = [&]() {
3727  /* Respect alignment of argument on the stack. */
3728  Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3729  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3730  CurArgOffset = ArgOffset;
3731  };
3732 
3733  if (CallConv != CallingConv::Fast) {
3734  ComputeArgOffset();
3735 
3736  /* Compute GPR index associated with argument offset. */
3737  GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3738  GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3739  }
3740 
3741  // FIXME the codegen can be much improved in some cases.
3742  // We do not have to keep everything in memory.
3743  if (Flags.isByVal()) {
3744  assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3745 
3746  if (CallConv == CallingConv::Fast)
3747  ComputeArgOffset();
3748 
3749  // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3750  ObjSize = Flags.getByValSize();
3751  ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3752  // Empty aggregate parameters do not take up registers. Examples:
3753  // struct { } a;
3754  // union { } b;
3755  // int c[0];
3756  // etc. However, we have to provide a place-holder in InVals, so
3757  // pretend we have an 8-byte item at the current address for that
3758  // purpose.
3759  if (!ObjSize) {
3760  int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3761  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3762  InVals.push_back(FIN);
3763  continue;
3764  }
3765 
3766  // Create a stack object covering all stack doublewords occupied
3767  // by the argument. If the argument is (fully or partially) on
3768  // the stack, or if the argument is fully in registers but the
3769  // caller has allocated the parameter save anyway, we can refer
3770  // directly to the caller's stack frame. Otherwise, create a
3771  // local copy in our own frame.
3772  int FI;
3773  if (HasParameterArea ||
3774  ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3775  FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3776  else
3777  FI = MFI.CreateStackObject(ArgSize, Align, false);
3778  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3779 
3780  // Handle aggregates smaller than 8 bytes.
3781  if (ObjSize < PtrByteSize) {
3782  // The value of the object is its address, which differs from the
3783  // address of the enclosing doubleword on big-endian systems.
3784  SDValue Arg = FIN;
3785  if (!isLittleEndian) {
3786  SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3787  Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3788  }
3789  InVals.push_back(Arg);
3790 
3791  if (GPR_idx != Num_GPR_Regs) {
3792  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3793  FuncInfo->addLiveInAttr(VReg, Flags);
3794  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3795  SDValue Store;
3796 
3797  if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3798  EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3799  (ObjSize == 2 ? MVT::i16 : MVT::i32));
3800  Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3801  MachinePointerInfo(&*FuncArg), ObjType);
3802  } else {
3803  // For sizes that don't fit a truncating store (3, 5, 6, 7),
3804  // store the whole register as-is to the parameter save area
3805  // slot.
3806  Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3807  MachinePointerInfo(&*FuncArg));
3808  }
3809 
3810  MemOps.push_back(Store);
3811  }
3812  // Whether we copied from a register or not, advance the offset
3813  // into the parameter save area by a full doubleword.
3814  ArgOffset += PtrByteSize;
3815  continue;
3816  }
3817 
3818  // The value of the object is its address, which is the address of
3819  // its first stack doubleword.
3820  InVals.push_back(FIN);
3821 
3822  // Store whatever pieces of the object are in registers to memory.
3823  for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3824  if (GPR_idx == Num_GPR_Regs)
3825  break;
3826 
3827  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3828  FuncInfo->addLiveInAttr(VReg, Flags);
3829  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3830  SDValue Addr = FIN;
3831  if (j) {
3832  SDValue Off = DAG.getConstant(j, dl, PtrVT);
3833  Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3834  }
3835  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3836  MachinePointerInfo(&*FuncArg, j));
3837  MemOps.push_back(Store);
3838  ++GPR_idx;
3839  }
3840  ArgOffset += ArgSize;
3841  continue;
3842  }
3843 
3844  switch (ObjectVT.getSimpleVT().SimpleTy) {
3845  default: llvm_unreachable("Unhandled argument type!");
3846  case MVT::i1:
3847  case MVT::i32:
3848  case MVT::i64:
3849  if (Flags.isNest()) {
3850  // The 'nest' parameter, if any, is passed in R11.
3851  unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3852  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3853 
3854  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3855  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3856 
3857  break;
3858  }
3859 
3860  // These can be scalar arguments or elements of an integer array type
3861  // passed directly. Clang may use those instead of "byval" aggregate
3862  // types to avoid forcing arguments to memory unnecessarily.
3863  if (GPR_idx != Num_GPR_Regs) {
3864  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3865  FuncInfo->addLiveInAttr(VReg, Flags);
3866  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3867 
3868  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3869  // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3870  // value to MVT::i64 and then truncate to the correct register size.
3871  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3872  } else {
3873  if (CallConv == CallingConv::Fast)
3874  ComputeArgOffset();
3875 
3876  needsLoad = true;
3877  ArgSize = PtrByteSize;
3878  }
3879  if (CallConv != CallingConv::Fast || needsLoad)
3880  ArgOffset += 8;
3881  break;
3882 
3883  case MVT::f32:
3884  case MVT::f64:
3885  // These can be scalar arguments or elements of a float array type
3886  // passed directly. The latter are used to implement ELFv2 homogenous
3887  // float aggregates.
3888  if (FPR_idx != Num_FPR_Regs) {
3889  unsigned VReg;
3890 
3891  if (ObjectVT == MVT::f32)
3892  VReg = MF.addLiveIn(FPR[FPR_idx],
3893  Subtarget.hasP8Vector()
3894  ? &PPC::VSSRCRegClass
3895  : &PPC::F4RCRegClass);
3896  else
3897  VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3898  ? &PPC::VSFRCRegClass
3899  : &PPC::F8RCRegClass);
3900 
3901  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3902  ++FPR_idx;
3903  } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3904  // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3905  // once we support fp <-> gpr moves.
3906 
3907  // This can only ever happen in the presence of f32 array types,
3908  // since otherwise we never run out of FPRs before running out
3909  // of GPRs.
3910  unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3911  FuncInfo->addLiveInAttr(VReg, Flags);
3912  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3913 
3914  if (ObjectVT == MVT::f32) {
3915  if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3916  ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3917  DAG.getConstant(32, dl, MVT::i32));
3918  ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3919  }
3920 
3921  ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3922  } else {
3923  if (CallConv == CallingConv::Fast)
3924  ComputeArgOffset();
3925 
3926  needsLoad = true;
3927  }
3928 
3929  // When passing an array of floats, the array occupies consecutive
3930  // space in the argument area; only round up to the next doubleword
3931  // at the end of the array. Otherwise, each float takes 8 bytes.
3932  if (CallConv != CallingConv::Fast || needsLoad) {
3933  ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3934  ArgOffset += ArgSize;
3935  if (Flags.isInConsecutiveRegsLast())
3936  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3937  }
3938  break;
3939  case MVT::v4f32:
3940  case MVT::v4i32:
3941  case MVT::v8i16:
3942  case MVT::v16i8:
3943  case MVT::v2f64:
3944  case MVT::v2i64:
3945  case MVT::v1i128:
3946  case MVT::f128:
3947  if (!Subtarget.hasQPX()) {
3948  // These can be scalar arguments or elements of a vector array type
3949  // passed directly. The latter are used to implement ELFv2 homogenous
3950  // vector aggregates.
3951  if (VR_idx != Num_VR_Regs) {
3952  unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3953  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3954  ++VR_idx;
3955  } else {
3956  if (CallConv == CallingConv::Fast)
3957  ComputeArgOffset();
3958  needsLoad = true;
3959  }
3960  if (CallConv != CallingConv::Fast || needsLoad)
3961  ArgOffset += 16;
3962  break;
3963  } // not QPX
3964 
3965  assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3966  "Invalid QPX parameter type");
3968 
3969  case MVT::v4f64:
3970  case MVT::v4i1:
3971  // QPX vectors are treated like their scalar floating-point subregisters
3972  // (except that they're larger).
3973  unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3974  if (QFPR_idx != Num_QFPR_Regs) {
3975  const TargetRegisterClass *RC;
3976  switch (ObjectVT.getSimpleVT().SimpleTy) {
3977  case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3978  case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3979  default: RC = &PPC::QBRCRegClass; break;
3980  }
3981 
3982  unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3983  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3984  ++QFPR_idx;
3985  } else {
3986  if (CallConv == CallingConv::Fast)
3987  ComputeArgOffset();
3988  needsLoad = true;
3989  }
3990  if (CallConv != CallingConv::Fast || needsLoad)
3991  ArgOffset += Sz;
3992  break;
3993  }
3994 
3995  // We need to load the argument to a virtual register if we determined
3996  // above that we ran out of physical registers of the appropriate type.
3997  if (needsLoad) {
3998  if (ObjSize < ArgSize && !isLittleEndian)
3999  CurArgOffset += ArgSize - ObjSize;
4000  int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4001  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4002  ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4003  }
4004 
4005  InVals.push_back(ArgVal);
4006  }
4007 
4008  // Area that is at least reserved in the caller of this function.
4009  unsigned MinReservedArea;
4010  if (HasParameterArea)
4011  MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4012  else
4013  MinReservedArea = LinkageSize;
4014 
4015  // Set the size that is at least reserved in caller of this function. Tail
4016  // call optimized functions' reserved stack space needs to be aligned so that
4017  // taking the difference between two stack areas will result in an aligned
4018  // stack.
4019  MinReservedArea =
4020  EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4021  FuncInfo->setMinReservedArea(MinReservedArea);
4022 
4023  // If the function takes variable number of arguments, make a frame index for
4024  // the start of the first vararg value... for expansion of llvm.va_start.
4025  if (isVarArg) {
4026  int Depth = ArgOffset;
4027 
4028  FuncInfo->setVarArgsFrameIndex(
4029  MFI.CreateFixedObject(PtrByteSize, Depth, true));
4030  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4031 
4032  // If this function is vararg, store any remaining integer argument regs
4033  // to their spots on the stack so that they may be loaded by dereferencing
4034  // the result of va_next.
4035  for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4036  GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4037  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4038  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4039  SDValue Store =
4040  DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4041  MemOps.push_back(Store);
4042  // Increment the address by four for the next argument to store
4043  SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4044  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4045  }
4046  }
4047 
4048  if (!MemOps.empty())
4049  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4050 
4051  return Chain;
4052 }
4053 
4054 SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4055  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4056  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4057  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4058  // TODO: add description of PPC stack frame format, or at least some docs.
4059  //
4060  MachineFunction &MF = DAG.getMachineFunction();
4061  MachineFrameInfo &MFI = MF.getFrameInfo();
4062  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4063 
4064  EVT PtrVT = getPointerTy(MF.getDataLayout());
4065  bool isPPC64 = PtrVT == MVT::i64;
4066  // Potential tail calls could cause overwriting of argument stack slots.
4067  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4068  (CallConv == CallingConv::Fast));
4069  unsigned PtrByteSize = isPPC64 ? 8 : 4;
4070  unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4071  unsigned ArgOffset = LinkageSize;
4072  // Area that is at least reserved in caller of this function.
4073  unsigned MinReservedArea = ArgOffset;
4074 
4075  static const MCPhysReg GPR_32[] = { // 32-bit registers.
4076  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4077  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4078  };
4079  static const MCPhysReg GPR_64[] = { // 64-bit registers.
4080  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4081  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4082  };
4083  static const MCPhysReg VR[] = {
4084  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4085  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4086  };
4087 
4088  const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4089  const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4090  const unsigned Num_VR_Regs = array_lengthof( VR);
4091 
4092  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4093 
4094  const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4095 
4096  // In 32-bit non-varargs functions, the stack space for vectors is after the
4097  // stack space for non-vectors. We do not use this space unless we have
4098  // too many vectors to fit in registers, something that only occurs in
4099  // constructed examples:), but we have to walk the arglist to figure
4100  // that out...for the pathological case, compute VecArgOffset as the
4101  // start of the vector parameter area. Computing VecArgOffset is the
4102  // entire point of the following loop.
4103  unsigned VecArgOffset = ArgOffset;
4104  if (!isVarArg && !isPPC64) {
4105  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4106  ++ArgNo) {
4107  EVT ObjectVT = Ins[ArgNo].VT;
4108  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4109 
4110  if (Flags.isByVal()) {
4111  // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4112  unsigned ObjSize = Flags.getByValSize();
4113  unsigned ArgSize =
4114  ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4115  VecArgOffset += ArgSize;
4116  continue;
4117  }
4118 
4119  switch(ObjectVT.getSimpleVT().SimpleTy) {
4120  default: llvm_unreachable("Unhandled argument type!");
4121  case MVT::i1:
4122  case MVT::i32:
4123  case MVT::f32:
4124  VecArgOffset += 4;
4125  break;
4126  case MVT::i64: // PPC64
4127  case MVT::f64:
4128  // FIXME: We are guaranteed to be !isPPC64 at this point.
4129  // Does MVT::i64 apply?
4130  VecArgOffset += 8;
4131  break;
4132  case MVT::v4f32:
4133  case MVT::v4i32:
4134  case MVT::v8i16:
4135  case MVT::v16i8:
4136  // Nothing to do, we're only looking at Nonvector args here.
4137  break;
4138  }
4139  }
4140  }
4141  // We've found where the vector parameter area in memory is. Skip the
4142  // first 12 parameters; these don't use that memory.
4143  VecArgOffset = ((VecArgOffset+15)/16)*16;
4144  VecArgOffset += 12*16;
4145 
4146  // Add DAG nodes to load the arguments or copy them out of registers. On
4147  // entry to a function on PPC, the arguments start after the linkage area,
4148  // although the first ones are often in registers.
4149 
4150  SmallVector<SDValue, 8> MemOps;
4151  unsigned nAltivecParamsAtEnd = 0;
4153  unsigned CurArgIdx = 0;
4154  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4155  SDValue ArgVal;
4156  bool needsLoad = false;
4157  EVT ObjectVT = Ins[ArgNo].VT;
4158  unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4159  unsigned ArgSize = ObjSize;
4160  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4161  if (Ins[ArgNo].isOrigArg()) {
4162  std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4163  CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4164  }
4165  unsigned CurArgOffset = ArgOffset;
4166 
4167  // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4168  if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4169  ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4170  if (isVarArg || isPPC64) {
4171  MinReservedArea = ((MinReservedArea+15)/16)*16;
4172  MinReservedArea += CalculateStackSlotSize(ObjectVT,
4173  Flags,
4174  PtrByteSize);
4175  } else nAltivecParamsAtEnd++;
4176  } else
4177  // Calculate min reserved area.
4178