LLVM  6.0.0svn
HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonISelLowering.h"
16 #include "Hexagon.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/IR/Value.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Support/Casting.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Debug.h"
55 #include <algorithm>
56 #include <cassert>
57 #include <cstddef>
58 #include <cstdint>
59 #include <limits>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-lowering"
65 
66 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67  cl::init(true), cl::Hidden,
68  cl::desc("Control jump table emission on Hexagon target"));
69 
70 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
72  cl::desc("Enable Hexagon SDNode scheduling"));
73 
74 static cl::opt<bool> EnableFastMath("ffast-math",
76  cl::desc("Enable Fast Math processing"));
77 
78 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
80  cl::desc("Set minimum jump tables"));
81 
82 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
84  cl::desc("Max #stores to inline memcpy"));
85 
86 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
88  cl::desc("Max #stores to inline memcpy"));
89 
90 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
92  cl::desc("Max #stores to inline memmove"));
93 
94 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
96  cl::desc("Max #stores to inline memmove"));
97 
98 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
100  cl::desc("Max #stores to inline memset"));
101 
102 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
104  cl::desc("Max #stores to inline memset"));
105 
106 
107 namespace {
108 
109  class HexagonCCState : public CCState {
110  unsigned NumNamedVarArgParams;
111 
112  public:
113  HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
115  int NumNamedVarArgParams)
116  : CCState(CC, isVarArg, MF, locs, C),
117  NumNamedVarArgParams(NumNamedVarArgParams) {}
118 
119  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
120  };
121 
123  Even = 0,
124  Odd,
125  NoPattern
126  };
127 
128 } // end anonymous namespace
129 
130 // Implement calling convention for Hexagon.
131 
132 static bool isHvxVectorType(MVT ty);
133 
134 static bool
135 CC_Hexagon(unsigned ValNo, MVT ValVT,
136  MVT LocVT, CCValAssign::LocInfo LocInfo,
137  ISD::ArgFlagsTy ArgFlags, CCState &State);
138 
139 static bool
140 CC_Hexagon32(unsigned ValNo, MVT ValVT,
141  MVT LocVT, CCValAssign::LocInfo LocInfo,
142  ISD::ArgFlagsTy ArgFlags, CCState &State);
143 
144 static bool
145 CC_Hexagon64(unsigned ValNo, MVT ValVT,
146  MVT LocVT, CCValAssign::LocInfo LocInfo,
147  ISD::ArgFlagsTy ArgFlags, CCState &State);
148 
149 static bool
150 CC_HexagonVector(unsigned ValNo, MVT ValVT,
151  MVT LocVT, CCValAssign::LocInfo LocInfo,
152  ISD::ArgFlagsTy ArgFlags, CCState &State);
153 
154 static bool
155 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156  MVT LocVT, CCValAssign::LocInfo LocInfo,
157  ISD::ArgFlagsTy ArgFlags, CCState &State);
158 
159 static bool
160 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161  MVT LocVT, CCValAssign::LocInfo LocInfo,
162  ISD::ArgFlagsTy ArgFlags, CCState &State);
163 
164 static bool
165 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166  MVT LocVT, CCValAssign::LocInfo LocInfo,
167  ISD::ArgFlagsTy ArgFlags, CCState &State);
168 
169 static bool
170 RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171  MVT LocVT, CCValAssign::LocInfo LocInfo,
172  ISD::ArgFlagsTy ArgFlags, CCState &State);
173 
174 static bool
175 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176  MVT LocVT, CCValAssign::LocInfo LocInfo,
177  ISD::ArgFlagsTy ArgFlags, CCState &State) {
178  HexagonCCState &HState = static_cast<HexagonCCState &>(State);
179 
180  if (ValNo < HState.getNumNamedVarArgParams()) {
181  // Deal with named arguments.
182  return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
183  }
184 
185  // Deal with un-named arguments.
186  unsigned Offset;
187  if (ArgFlags.isByVal()) {
188  // If pass-by-value, the size allocated on stack is decided
189  // by ArgFlags.getByValSize(), not by the size of LocVT.
190  Offset = State.AllocateStack(ArgFlags.getByValSize(),
191  ArgFlags.getByValAlign());
192  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
193  return false;
194  }
195  if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
196  LocVT = MVT::i32;
197  ValVT = MVT::i32;
198  if (ArgFlags.isSExt())
199  LocInfo = CCValAssign::SExt;
200  else if (ArgFlags.isZExt())
201  LocInfo = CCValAssign::ZExt;
202  else
203  LocInfo = CCValAssign::AExt;
204  }
205  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206  Offset = State.AllocateStack(4, 4);
207  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
208  return false;
209  }
210  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211  Offset = State.AllocateStack(8, 8);
212  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
213  return false;
214  }
215  if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216  LocVT == MVT::v16i8) {
217  Offset = State.AllocateStack(16, 16);
218  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
219  return false;
220  }
221  if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222  LocVT == MVT::v32i8) {
223  Offset = State.AllocateStack(32, 32);
224  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225  return false;
226  }
227  if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228  LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229  Offset = State.AllocateStack(64, 64);
230  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
231  return false;
232  }
233  if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234  LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235  Offset = State.AllocateStack(128, 128);
236  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
237  return false;
238  }
239  if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240  LocVT == MVT::v256i8) {
241  Offset = State.AllocateStack(256, 256);
242  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
243  return false;
244  }
245 
246  llvm_unreachable(nullptr);
247 }
248 
249 static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251  if (ArgFlags.isByVal()) {
252  // Passed on stack.
253  unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254  ArgFlags.getByValAlign());
255  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
256  return false;
257  }
258 
259  if (LocVT == MVT::i1) {
260  LocVT = MVT::i32;
261  } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
262  LocVT = MVT::i32;
263  ValVT = MVT::i32;
264  if (ArgFlags.isSExt())
265  LocInfo = CCValAssign::SExt;
266  else if (ArgFlags.isZExt())
267  LocInfo = CCValAssign::ZExt;
268  else
269  LocInfo = CCValAssign::AExt;
270  } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
271  LocVT = MVT::i32;
272  LocInfo = CCValAssign::BCvt;
273  } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
274  LocVT = MVT::i64;
275  LocInfo = CCValAssign::BCvt;
276  }
277 
278  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
279  if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
280  return false;
281  }
282 
283  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
284  if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
285  return false;
286  }
287 
288  if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
289  unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
290  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
291  return false;
292  }
293 
294  if (isHvxVectorType(LocVT)) {
295  if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
296  return false;
297  }
298 
299  return true; // CC didn't match.
300 }
301 
302 
303 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
304  MVT LocVT, CCValAssign::LocInfo LocInfo,
305  ISD::ArgFlagsTy ArgFlags, CCState &State) {
306  static const MCPhysReg RegList[] = {
307  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
308  Hexagon::R5
309  };
310  if (unsigned Reg = State.AllocateReg(RegList)) {
311  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
312  return false;
313  }
314 
315  unsigned Offset = State.AllocateStack(4, 4);
316  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
317  return false;
318 }
319 
320 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
321  MVT LocVT, CCValAssign::LocInfo LocInfo,
322  ISD::ArgFlagsTy ArgFlags, CCState &State) {
323  if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
324  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
325  return false;
326  }
327 
328  static const MCPhysReg RegList1[] = {
329  Hexagon::D1, Hexagon::D2
330  };
331  static const MCPhysReg RegList2[] = {
332  Hexagon::R1, Hexagon::R3
333  };
334  if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
335  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
336  return false;
337  }
338 
339  unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
340  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
341  return false;
342 }
343 
344 static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
345  MVT LocVT, CCValAssign::LocInfo LocInfo,
346  ISD::ArgFlagsTy ArgFlags, CCState &State) {
347  static const MCPhysReg VecLstS[] = {
348  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
349  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
350  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
351  Hexagon::V15
352  };
353  static const MCPhysReg VecLstD[] = {
354  Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
355  Hexagon::W5, Hexagon::W6, Hexagon::W7
356  };
357  auto &MF = State.getMachineFunction();
358  auto &HST = MF.getSubtarget<HexagonSubtarget>();
359 
360  if (HST.useHVX64BOps() &&
361  (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
362  LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
363  if (unsigned Reg = State.AllocateReg(VecLstS)) {
364  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
365  return false;
366  }
367  unsigned Offset = State.AllocateStack(64, 64);
368  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
369  return false;
370  }
371  if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||
372  LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
373  if (unsigned Reg = State.AllocateReg(VecLstD)) {
374  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
375  return false;
376  }
377  unsigned Offset = State.AllocateStack(128, 128);
378  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
379  return false;
380  }
381  // 128B Mode
382  if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||
383  LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
384  if (unsigned Reg = State.AllocateReg(VecLstD)) {
385  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
386  return false;
387  }
388  unsigned Offset = State.AllocateStack(256, 256);
389  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
390  return false;
391  }
392  if (HST.useHVX128BOps() &&
393  (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
394  LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
395  if (unsigned Reg = State.AllocateReg(VecLstS)) {
396  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
397  return false;
398  }
399  unsigned Offset = State.AllocateStack(128, 128);
400  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
401  return false;
402  }
403  return true;
404 }
405 
406 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
407  MVT LocVT, CCValAssign::LocInfo LocInfo,
408  ISD::ArgFlagsTy ArgFlags, CCState &State) {
409  auto &MF = State.getMachineFunction();
410  auto &HST = MF.getSubtarget<HexagonSubtarget>();
411 
412  if (LocVT == MVT::i1) {
413  // Return values of type MVT::i1 still need to be assigned to R0, but
414  // the value type needs to remain i1. LowerCallResult will deal with it,
415  // but it needs to recognize i1 as the value type.
416  LocVT = MVT::i32;
417  } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
418  LocVT = MVT::i32;
419  ValVT = MVT::i32;
420  if (ArgFlags.isSExt())
421  LocInfo = CCValAssign::SExt;
422  else if (ArgFlags.isZExt())
423  LocInfo = CCValAssign::ZExt;
424  else
425  LocInfo = CCValAssign::AExt;
426  } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
427  LocVT = MVT::i32;
428  LocInfo = CCValAssign::BCvt;
429  } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
430  LocVT = MVT::i64;
431  LocInfo = CCValAssign::BCvt;
432  } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
433  LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
434  LocVT == MVT::v512i1) {
435  LocVT = MVT::v16i32;
436  ValVT = MVT::v16i32;
437  LocInfo = CCValAssign::Full;
438  } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
439  LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
440  (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
441  LocVT = MVT::v32i32;
442  ValVT = MVT::v32i32;
443  LocInfo = CCValAssign::Full;
444  } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
445  LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
446  LocVT = MVT::v64i32;
447  ValVT = MVT::v64i32;
448  LocInfo = CCValAssign::Full;
449  }
450  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
451  if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
452  return false;
453  }
454 
455  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
456  if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
457  return false;
458  }
459  if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
460  if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
461  return false;
462  }
463  return true; // CC didn't match.
464 }
465 
466 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
467  MVT LocVT, CCValAssign::LocInfo LocInfo,
468  ISD::ArgFlagsTy ArgFlags, CCState &State) {
469  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
470  // Note that use of registers beyond R1 is not ABI compliant. However there
471  // are (experimental) IR passes which generate internal functions that
472  // return structs using these additional registers.
473  static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
474  Hexagon::R2, Hexagon::R3,
475  Hexagon::R4, Hexagon::R5 };
476  if (unsigned Reg = State.AllocateReg(RegList)) {
477  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
478  return false;
479  }
480  }
481 
482  return true;
483 }
484 
485 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
486  MVT LocVT, CCValAssign::LocInfo LocInfo,
487  ISD::ArgFlagsTy ArgFlags, CCState &State) {
488  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
489  if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
490  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
491  return false;
492  }
493  }
494 
495  return true;
496 }
497 
498 static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
499  MVT LocVT, CCValAssign::LocInfo LocInfo,
500  ISD::ArgFlagsTy ArgFlags, CCState &State) {
501  auto &MF = State.getMachineFunction();
502  auto &HST = MF.getSubtarget<HexagonSubtarget>();
503 
504  if (LocVT == MVT::v16i32) {
505  if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
506  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
507  return false;
508  }
509  } else if (LocVT == MVT::v32i32) {
510  unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;
511  if (unsigned Reg = State.AllocateReg(Req)) {
512  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
513  return false;
514  }
515  } else if (LocVT == MVT::v64i32) {
516  if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
517  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
518  return false;
519  }
520  }
521 
522  return true;
523 }
524 
525 void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
526  if (VT != PromotedLdStVT) {
527  setOperationAction(ISD::LOAD, VT, Promote);
528  AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
529 
530  setOperationAction(ISD::STORE, VT, Promote);
531  AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
532  }
533 }
534 
535 SDValue
537  const {
538  return SDValue();
539 }
540 
541 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
542 /// by "Src" to address "Dst" of size "Size". Alignment information is
543 /// specified by the specific parameter attribute. The copy will be passed as
544 /// a byval function parameter. Sometimes what we are copying is the end of a
545 /// larger object, the part that does not fit in registers.
547  SDValue Chain, ISD::ArgFlagsTy Flags,
548  SelectionDAG &DAG, const SDLoc &dl) {
549  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
550  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
551  /*isVolatile=*/false, /*AlwaysInline=*/false,
552  /*isTailCall=*/false,
554 }
555 
556 static bool isHvxVectorType(MVT Ty) {
557  switch (Ty.SimpleTy) {
558  case MVT::v8i64:
559  case MVT::v16i32:
560  case MVT::v32i16:
561  case MVT::v64i8:
562  case MVT::v16i64:
563  case MVT::v32i32:
564  case MVT::v64i16:
565  case MVT::v128i8:
566  case MVT::v32i64:
567  case MVT::v64i32:
568  case MVT::v128i16:
569  case MVT::v256i8:
570  case MVT::v512i1:
571  case MVT::v1024i1:
572  return true;
573  default:
574  return false;
575  }
576 }
577 
578 bool
580  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
582  LLVMContext &Context) const {
584  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
585  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
586 }
587 
588 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
589 // passed by value, the function prototype is modified to return void and
590 // the value is stored in memory pointed by a pointer passed by caller.
591 SDValue
593  bool isVarArg,
595  const SmallVectorImpl<SDValue> &OutVals,
596  const SDLoc &dl, SelectionDAG &DAG) const {
597  // CCValAssign - represent the assignment of the return value to locations.
599 
600  // CCState - Info about the registers and stack slot.
601  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
602  *DAG.getContext());
603 
604  // Analyze return values of ISD::RET
605  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
606 
607  SDValue Flag;
608  SmallVector<SDValue, 4> RetOps(1, Chain);
609 
610  // Copy the result values into the output registers.
611  for (unsigned i = 0; i != RVLocs.size(); ++i) {
612  CCValAssign &VA = RVLocs[i];
613 
614  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
615 
616  // Guarantee that all emitted copies are stuck together with flags.
617  Flag = Chain.getValue(1);
618  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
619  }
620 
621  RetOps[0] = Chain; // Update chain.
622 
623  // Add the flag if we have it.
624  if (Flag.getNode())
625  RetOps.push_back(Flag);
626 
627  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
628 }
629 
631  // If either no tail call or told not to tail call at all, don't.
632  auto Attr =
633  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
634  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
635  return false;
636 
637  return true;
638 }
639 
640 /// LowerCallResult - Lower the result values of an ISD::CALL into the
641 /// appropriate copies out of appropriate physical registers. This assumes that
642 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
643 /// being lowered. Returns a SDNode with the same number of values as the
644 /// ISD::CALL.
646  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool isVarArg,
647  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
649  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
650  // Assign locations to each value returned by this call.
652 
653  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
654  *DAG.getContext());
655 
656  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
657 
658  // Copy all of the result registers out of their specified physreg.
659  for (unsigned i = 0; i != RVLocs.size(); ++i) {
660  SDValue RetVal;
661  if (RVLocs[i].getValVT() == MVT::i1) {
662  // Return values of type MVT::i1 require special handling. The reason
663  // is that MVT::i1 is associated with the PredRegs register class, but
664  // values of that type are still returned in R0. Generate an explicit
665  // copy into a predicate register from R0, and treat the value of the
666  // predicate register as the call result.
667  auto &MRI = DAG.getMachineFunction().getRegInfo();
668  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
669  MVT::i32, Glue);
670  // FR0 = (Value, Chain, Glue)
671  unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
672  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
673  FR0.getValue(0), FR0.getValue(2));
674  // TPR = (Chain, Glue)
675  // Don't glue this CopyFromReg, because it copies from a virtual
676  // register. If it is glued to the call, InstrEmitter will add it
677  // as an implicit def to the call (EmitMachineNode).
678  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
679  Glue = TPR.getValue(1);
680  Chain = TPR.getValue(0);
681  } else {
682  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
683  RVLocs[i].getValVT(), Glue);
684  Glue = RetVal.getValue(2);
685  Chain = RetVal.getValue(1);
686  }
687  InVals.push_back(RetVal.getValue(0));
688  }
689 
690  return Chain;
691 }
692 
693 /// LowerCall - Functions arguments are copied from virtual regs to
694 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
695 SDValue
697  SmallVectorImpl<SDValue> &InVals) const {
698  SelectionDAG &DAG = CLI.DAG;
699  SDLoc &dl = CLI.DL;
701  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
703  SDValue Chain = CLI.Chain;
704  SDValue Callee = CLI.Callee;
705  bool &IsTailCall = CLI.IsTailCall;
706  CallingConv::ID CallConv = CLI.CallConv;
707  bool IsVarArg = CLI.IsVarArg;
708  bool DoesNotReturn = CLI.DoesNotReturn;
709 
710  bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
712  MachineFrameInfo &MFI = MF.getFrameInfo();
713  auto PtrVT = getPointerTy(MF.getDataLayout());
714 
715  // Check for varargs.
716  unsigned NumNamedVarArgParams = -1U;
717  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
718  const GlobalValue *GV = GAN->getGlobal();
719  Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
720  if (const Function* F = dyn_cast<Function>(GV)) {
721  // If a function has zero args and is a vararg function, that's
722  // disallowed so it must be an undeclared function. Do not assume
723  // varargs if the callee is undefined.
724  if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
725  NumNamedVarArgParams = F->getFunctionType()->getNumParams();
726  }
727  }
728 
729  // Analyze operands of the call, assigning locations to each operand.
731  HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
732  *DAG.getContext(), NumNamedVarArgParams);
733 
734  if (IsVarArg)
735  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
736  else
737  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
738 
739  auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
740  if (Attr.getValueAsString() == "true")
741  IsTailCall = false;
742 
743  if (IsTailCall) {
744  bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
745  IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
746  IsVarArg, IsStructRet,
747  StructAttrFlag,
748  Outs, OutVals, Ins, DAG);
749  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
750  CCValAssign &VA = ArgLocs[i];
751  if (VA.isMemLoc()) {
752  IsTailCall = false;
753  break;
754  }
755  }
756  DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
757  : "Argument must be passed on stack. "
758  "Not eligible for Tail Call\n"));
759  }
760  // Get a count of how many bytes are to be pushed on the stack.
761  unsigned NumBytes = CCInfo.getNextStackOffset();
763  SmallVector<SDValue, 8> MemOpChains;
764 
765  auto &HRI = *Subtarget.getRegisterInfo();
766  SDValue StackPtr =
767  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
768 
769  bool NeedsArgAlign = false;
770  unsigned LargestAlignSeen = 0;
771  // Walk the register/memloc assignments, inserting copies/loads.
772  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
773  CCValAssign &VA = ArgLocs[i];
774  SDValue Arg = OutVals[i];
775  ISD::ArgFlagsTy Flags = Outs[i].Flags;
776  // Record if we need > 8 byte alignment on an argument.
777  bool ArgAlign = isHvxVectorType(VA.getValVT());
778  NeedsArgAlign |= ArgAlign;
779 
780  // Promote the value if needed.
781  switch (VA.getLocInfo()) {
782  default:
783  // Loc info must be one of Full, SExt, ZExt, or AExt.
784  llvm_unreachable("Unknown loc info!");
785  case CCValAssign::BCvt:
786  case CCValAssign::Full:
787  break;
788  case CCValAssign::SExt:
789  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
790  break;
791  case CCValAssign::ZExt:
792  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
793  break;
794  case CCValAssign::AExt:
795  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
796  break;
797  }
798 
799  if (VA.isMemLoc()) {
800  unsigned LocMemOffset = VA.getLocMemOffset();
801  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
802  StackPtr.getValueType());
803  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
804  if (ArgAlign)
805  LargestAlignSeen = std::max(LargestAlignSeen,
806  VA.getLocVT().getStoreSizeInBits() >> 3);
807  if (Flags.isByVal()) {
808  // The argument is a struct passed by value. According to LLVM, "Arg"
809  // is is pointer.
810  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
811  Flags, DAG, dl));
812  } else {
814  DAG.getMachineFunction(), LocMemOffset);
815  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
816  MemOpChains.push_back(S);
817  }
818  continue;
819  }
820 
821  // Arguments that can be passed on register must be kept at RegsToPass
822  // vector.
823  if (VA.isRegLoc())
824  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
825  }
826 
827  if (NeedsArgAlign && Subtarget.hasV60TOps()) {
828  DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
829  // V6 vectors passed by value have 64 or 128 byte alignment depending
830  // on whether we are 64 byte vector mode or 128 byte.
831  bool UseHVX128B = Subtarget.useHVX128BOps();
832  assert(Subtarget.useHVXOps());
833  const unsigned ObjAlign = UseHVX128B ? 128 : 64;
834  LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
835  MFI.ensureMaxAlignment(LargestAlignSeen);
836  }
837  // Transform all store nodes into one single node because all store
838  // nodes are independent of each other.
839  if (!MemOpChains.empty())
840  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
841 
842  SDValue Glue;
843  if (!IsTailCall) {
844  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
845  Glue = Chain.getValue(1);
846  }
847 
848  // Build a sequence of copy-to-reg nodes chained together with token
849  // chain and flag operands which copy the outgoing args into registers.
850  // The Glue is necessary since all emitted instructions must be
851  // stuck together.
852  if (!IsTailCall) {
853  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
854  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
855  RegsToPass[i].second, Glue);
856  Glue = Chain.getValue(1);
857  }
858  } else {
859  // For tail calls lower the arguments to the 'real' stack slot.
860  //
861  // Force all the incoming stack arguments to be loaded from the stack
862  // before any new outgoing arguments are stored to the stack, because the
863  // outgoing stack slots may alias the incoming argument stack slots, and
864  // the alias isn't otherwise explicit. This is slightly more conservative
865  // than necessary, because it means that each store effectively depends
866  // on every argument instead of just those arguments it would clobber.
867  //
868  // Do not flag preceding copytoreg stuff together with the following stuff.
869  Glue = SDValue();
870  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
871  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
872  RegsToPass[i].second, Glue);
873  Glue = Chain.getValue(1);
874  }
875  Glue = SDValue();
876  }
877 
878  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
879  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
880 
881  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
882  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
883  // node so that legalize doesn't hack it.
884  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
885  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
886  } else if (ExternalSymbolSDNode *S =
887  dyn_cast<ExternalSymbolSDNode>(Callee)) {
888  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
889  }
890 
891  // Returns a chain & a flag for retval copy to use.
892  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
894  Ops.push_back(Chain);
895  Ops.push_back(Callee);
896 
897  // Add argument registers to the end of the list so that they are
898  // known live into the call.
899  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
900  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
901  RegsToPass[i].second.getValueType()));
902  }
903 
904  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
905  assert(Mask && "Missing call preserved mask for calling convention");
906  Ops.push_back(DAG.getRegisterMask(Mask));
907 
908  if (Glue.getNode())
909  Ops.push_back(Glue);
910 
911  if (IsTailCall) {
912  MFI.setHasTailCall();
913  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
914  }
915 
916  // Set this here because we need to know this for "hasFP" in frame lowering.
917  // The target-independent code calls getFrameRegister before setting it, and
918  // getFrameRegister uses hasFP to determine whether the function has FP.
919  MFI.setHasCalls(true);
920 
921  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
922  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
923  Glue = Chain.getValue(1);
924 
925  // Create the CALLSEQ_END node.
926  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
927  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
928  Glue = Chain.getValue(1);
929 
930  // Handle result values, copying them out of physregs into vregs that we
931  // return.
932  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
933  InVals, OutVals, Callee);
934 }
935 
936 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
938  bool &IsInc, SelectionDAG &DAG) {
939  if (Ptr->getOpcode() != ISD::ADD)
940  return false;
941 
942  auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
943 
944  bool ValidHVX128BType =
945  HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
946  VT == MVT::v64i16 || VT == MVT::v128i8);
947  bool ValidHVXType =
948  HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
949  VT == MVT::v32i16 || VT == MVT::v64i8);
950 
951  if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||
952  VT == MVT::i16 || VT == MVT::i8) {
953  IsInc = (Ptr->getOpcode() == ISD::ADD);
954  Base = Ptr->getOperand(0);
955  Offset = Ptr->getOperand(1);
956  // Ensure that Offset is a constant.
957  return isa<ConstantSDNode>(Offset);
958  }
959 
960  return false;
961 }
962 
963 /// getPostIndexedAddressParts - returns true by value, base pointer and
964 /// offset pointer and addressing mode by reference if this node can be
965 /// combined with a load / store to form a post-indexed load / store.
967  SDValue &Base,
968  SDValue &Offset,
970  SelectionDAG &DAG) const
971 {
972  EVT VT;
973 
974  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
975  VT = LD->getMemoryVT();
976  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
977  VT = ST->getMemoryVT();
978  if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
979  return false;
980  } else {
981  return false;
982  }
983 
984  bool IsInc = false;
985  bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
986  if (isLegal) {
987  auto &HII = *Subtarget.getInstrInfo();
988  int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
989  if (HII.isValidAutoIncImm(VT, OffsetVal)) {
990  AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
991  return true;
992  }
993  }
994 
995  return false;
996 }
997 
998 SDValue
1000  MachineFunction &MF = DAG.getMachineFunction();
1001  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1002  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1003  unsigned LR = HRI.getRARegister();
1004 
1005  if (Op.getOpcode() != ISD::INLINEASM || HMFI.hasClobberLR())
1006  return Op;
1007 
1008  unsigned NumOps = Op.getNumOperands();
1009  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
1010  --NumOps; // Ignore the flag operand.
1011 
1012  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1013  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
1014  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1015  ++i; // Skip the ID value.
1016 
1017  switch (InlineAsm::getKind(Flags)) {
1018  default:
1019  llvm_unreachable("Bad flags!");
1021  case InlineAsm::Kind_Imm:
1022  case InlineAsm::Kind_Mem:
1023  i += NumVals;
1024  break;
1028  for (; NumVals; --NumVals, ++i) {
1029  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
1030  if (Reg != LR)
1031  continue;
1032  HMFI.setHasClobberLR(true);
1033  return Op;
1034  }
1035  break;
1036  }
1037  }
1038  }
1039 
1040  return Op;
1041 }
1042 
1043 // Need to transform ISD::PREFETCH into something that doesn't inherit
1044 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1045 // SDNPMayStore.
1047  SelectionDAG &DAG) const {
1048  SDValue Chain = Op.getOperand(0);
1049  SDValue Addr = Op.getOperand(1);
1050  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1051  // if the "reg" is fed by an "add".
1052  SDLoc DL(Op);
1053  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1054  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1055 }
1056 
1057 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
1058 // is marked as having side-effects, while the register read on Hexagon does
1059 // not have any. TableGen refuses to accept the direct pattern from that node
1060 // to the A4_tfrcpp.
1062  SelectionDAG &DAG) const {
1063  SDValue Chain = Op.getOperand(0);
1064  SDLoc dl(Op);
1065  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1066  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
1067 }
1068 
1070  SelectionDAG &DAG) const {
1071  SDValue Chain = Op.getOperand(0);
1072  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1073  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1074  if (IntNo == Intrinsic::hexagon_prefetch) {
1075  SDValue Addr = Op.getOperand(2);
1076  SDLoc DL(Op);
1077  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1078  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1079  }
1080  return SDValue();
1081 }
1082 
1083 SDValue
1085  SelectionDAG &DAG) const {
1086  SDValue Chain = Op.getOperand(0);
1087  SDValue Size = Op.getOperand(1);
1088  SDValue Align = Op.getOperand(2);
1089  SDLoc dl(Op);
1090 
1091  ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1092  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
1093 
1094  unsigned A = AlignConst->getSExtValue();
1095  auto &HFI = *Subtarget.getFrameLowering();
1096  // "Zero" means natural stack alignment.
1097  if (A == 0)
1098  A = HFI.getStackAlignment();
1099 
1100  DEBUG({
1101  dbgs () << __func__ << " Align: " << A << " Size: ";
1102  Size.getNode()->dump(&DAG);
1103  dbgs() << "\n";
1104  });
1105 
1106  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1107  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1108  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1109 
1110  DAG.ReplaceAllUsesOfValueWith(Op, AA);
1111  return AA;
1112 }
1113 
1115  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1116  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1117  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1118  MachineFunction &MF = DAG.getMachineFunction();
1119  MachineFrameInfo &MFI = MF.getFrameInfo();
1120  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1121  auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1122 
1123  // Assign locations to all of the incoming arguments.
1125  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1126  *DAG.getContext());
1127 
1128  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1129 
1130  // For LLVM, in the case when returning a struct by value (>8byte),
1131  // the first argument is a pointer that points to the location on caller's
1132  // stack where the return value will be stored. For Hexagon, the location on
1133  // caller's stack is passed only when the struct size is smaller than (and
1134  // equal to) 8 bytes. If not, no address will be passed into callee and
1135  // callee return the result direclty through R0/R1.
1136 
1137  SmallVector<SDValue, 8> MemOps;
1138 
1139  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1140  CCValAssign &VA = ArgLocs[i];
1141  ISD::ArgFlagsTy Flags = Ins[i].Flags;
1142  unsigned ObjSize;
1143  unsigned StackLocation;
1144  int FI;
1145 
1146  if ( (VA.isRegLoc() && !Flags.isByVal())
1147  || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1148  // Arguments passed in registers
1149  // 1. int, long long, ptr args that get allocated in register.
1150  // 2. Large struct that gets an register to put its address in.
1151  EVT RegVT = VA.getLocVT();
1152  if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1153  RegVT == MVT::i32 || RegVT == MVT::f32) {
1154  unsigned VReg =
1155  RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1156  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1157  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1158  // Treat values of type MVT::i1 specially: they are passed in
1159  // registers of type i32, but they need to remain as values of
1160  // type i1 for consistency of the argument lowering.
1161  if (VA.getValVT() == MVT::i1) {
1162  // Generate a copy into a predicate register and use the value
1163  // of the register as the "InVal".
1164  unsigned PReg =
1165  RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
1166  SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1167  Copy.getValue(0));
1168  Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
1169  Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
1170  }
1171  InVals.push_back(Copy);
1172  Chain = Copy.getValue(1);
1173  } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1174  unsigned VReg =
1175  RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1176  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1177  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1178 
1179  // Single Vector
1180  } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1181  RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1182  unsigned VReg =
1183  RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
1184  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1185  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1186  } else if (Subtarget.useHVX128BOps() &&
1187  ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1188  RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1189  unsigned VReg =
1190  RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
1191  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1192  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1193 
1194  // Double Vector
1195  } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1196  RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1197  unsigned VReg =
1198  RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
1199  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1200  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1201  } else if (Subtarget.useHVX128BOps() &&
1202  ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1203  RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1204  unsigned VReg =
1205  RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
1206  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1207  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1208  } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1209  assert(0 && "need to support VecPred regs");
1210  unsigned VReg =
1211  RegInfo.createVirtualRegister(&Hexagon::HvxQRRegClass);
1212  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1213  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1214  } else {
1215  assert (0);
1216  }
1217  } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1218  assert (0 && "ByValSize must be bigger than 8 bytes");
1219  } else {
1220  // Sanity check.
1221  assert(VA.isMemLoc());
1222 
1223  if (Flags.isByVal()) {
1224  // If it's a byval parameter, then we need to compute the
1225  // "real" size, not the size of the pointer.
1226  ObjSize = Flags.getByValSize();
1227  } else {
1228  ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1229  }
1230 
1231  StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
1232  // Create the frame index object for this incoming parameter...
1233  FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1234 
1235  // Create the SelectionDAG nodes cordl, responding to a load
1236  // from this parameter.
1237  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1238 
1239  if (Flags.isByVal()) {
1240  // If it's a pass-by-value aggregate, then do not dereference the stack
1241  // location. Instead, we should generate a reference to the stack
1242  // location.
1243  InVals.push_back(FIN);
1244  } else {
1245  InVals.push_back(
1246  DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
1247  }
1248  }
1249  }
1250 
1251  if (!MemOps.empty())
1252  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1253 
1254  if (isVarArg) {
1255  // This will point to the next argument passed via stack.
1258  CCInfo.getNextStackOffset(),
1259  true);
1260  FuncInfo.setVarArgsFrameIndex(FrameIndex);
1261  }
1262 
1263  return Chain;
1264 }
1265 
1266 SDValue
1268  // VASTART stores the address of the VarArgsFrameIndex slot into the
1269  // memory location argument.
1270  MachineFunction &MF = DAG.getMachineFunction();
1272  SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1273  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1274  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1275  MachinePointerInfo(SV));
1276 }
1277 
1278 static bool isSExtFree(SDValue N) {
1279  // A sign-extend of a truncate of a sign-extend is free.
1280  if (N.getOpcode() == ISD::TRUNCATE &&
1282  return true;
1283  // We have sign-extended loads.
1284  if (N.getOpcode() == ISD::LOAD)
1285  return true;
1286  return false;
1287 }
1288 
1290  SDLoc dl(Op);
1291 
1292  SDValue LHS = Op.getOperand(0);
1293  SDValue RHS = Op.getOperand(1);
1294  SDValue Cmp = Op.getOperand(2);
1295  ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1296 
1297  EVT VT = Op.getValueType();
1298  EVT LHSVT = LHS.getValueType();
1299  EVT RHSVT = RHS.getValueType();
1300 
1301  if (LHSVT == MVT::v2i16) {
1303  unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1304  : ISD::ZERO_EXTEND;
1305  SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1306  SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1307  SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1308  return SC;
1309  }
1310 
1311  // Treat all other vector types as legal.
1312  if (VT.isVector())
1313  return Op;
1314 
1315  // Equals and not equals should use sign-extend, not zero-extend, since
1316  // we can represent small negative values in the compare instructions.
1317  // The LLVM default is to use zero-extend arbitrarily in these cases.
1318  if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1319  (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1320  (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1322  if (C && C->getAPIntValue().isNegative()) {
1323  LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1324  RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1325  return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1326  LHS, RHS, Op.getOperand(2));
1327  }
1328  if (isSExtFree(LHS) || isSExtFree(RHS)) {
1329  LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1330  RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1331  return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1332  LHS, RHS, Op.getOperand(2));
1333  }
1334  }
1335  return SDValue();
1336 }
1337 
1338 SDValue
1340  SDValue PredOp = Op.getOperand(0);
1341  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1342  EVT OpVT = Op1.getValueType();
1343  SDLoc DL(Op);
1344 
1345  if (OpVT == MVT::v2i16) {
1346  SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1347  SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1348  SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1349  SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1350  return TR;
1351  }
1352 
1353  return SDValue();
1354 }
1355 
1356 static Constant *convert_i1_to_i8(const Constant *ConstVal) {
1358  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
1359  if (!CV)
1360  return nullptr;
1361 
1362  LLVMContext &Ctx = ConstVal->getContext();
1363  IRBuilder<> IRB(Ctx);
1364  unsigned NumVectorElements = CV->getNumOperands();
1365  assert(isPowerOf2_32(NumVectorElements) &&
1366  "conversion only supported for pow2 VectorSize!");
1367 
1368  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
1369  uint8_t x = 0;
1370  for (unsigned j = 0; j < 8; ++j) {
1371  uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
1372  x |= y << (7 - j);
1373  }
1374  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
1375  NewConst.push_back(IRB.getInt8(x));
1376  }
1377  return ConstantVector::get(NewConst);
1378 }
1379 
1380 SDValue
1382  EVT ValTy = Op.getValueType();
1383  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1384  Constant *CVal = nullptr;
1385  bool isVTi1Type = false;
1386  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
1387  Type *CValTy = ConstVal->getType();
1388  if (CValTy->isVectorTy() &&
1389  CValTy->getVectorElementType()->isIntegerTy(1)) {
1390  CVal = convert_i1_to_i8(ConstVal);
1391  isVTi1Type = (CVal != nullptr);
1392  }
1393  }
1394  unsigned Align = CPN->getAlignment();
1395  bool IsPositionIndependent = isPositionIndependent();
1396  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1397 
1398  unsigned Offset = 0;
1399  SDValue T;
1400  if (CPN->isMachineConstantPoolEntry())
1401  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1402  TF);
1403  else if (isVTi1Type)
1404  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
1405  else
1406  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1407  TF);
1408 
1409  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1410  "Inconsistent target flag encountered");
1411 
1412  if (IsPositionIndependent)
1413  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1414  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1415 }
1416 
1417 SDValue
1419  EVT VT = Op.getValueType();
1420  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1421  if (isPositionIndependent()) {
1423  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1424  }
1425 
1426  SDValue T = DAG.getTargetJumpTable(Idx, VT);
1427  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1428 }
1429 
1430 SDValue
1432  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1433  MachineFunction &MF = DAG.getMachineFunction();
1434  MachineFrameInfo &MFI = MF.getFrameInfo();
1435  MFI.setReturnAddressIsTaken(true);
1436 
1437  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1438  return SDValue();
1439 
1440  EVT VT = Op.getValueType();
1441  SDLoc dl(Op);
1442  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1443  if (Depth) {
1444  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1445  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1446  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1447  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1448  MachinePointerInfo());
1449  }
1450 
1451  // Return LR, which contains the return address. Mark it an implicit live-in.
1452  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1453  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1454 }
1455 
1456 SDValue
1458  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1460  MFI.setFrameAddressIsTaken(true);
1461 
1462  EVT VT = Op.getValueType();
1463  SDLoc dl(Op);
1464  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1465  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1466  HRI.getFrameRegister(), VT);
1467  while (Depth--)
1468  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1469  MachinePointerInfo());
1470  return FrameAddr;
1471 }
1472 
1473 SDValue
1475  SDLoc dl(Op);
1476  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1477 }
1478 
1479 SDValue
1481  SDLoc dl(Op);
1482  auto *GAN = cast<GlobalAddressSDNode>(Op);
1483  auto PtrVT = getPointerTy(DAG.getDataLayout());
1484  auto *GV = GAN->getGlobal();
1485  int64_t Offset = GAN->getOffset();
1486 
1487  auto &HLOF = *HTM.getObjFileLowering();
1488  Reloc::Model RM = HTM.getRelocationModel();
1489 
1490  if (RM == Reloc::Static) {
1491  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1492  const GlobalObject *GO = GV->getBaseObject();
1493  if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1494  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1495  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1496  }
1497 
1498  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1499  if (UsePCRel) {
1500  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1502  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1503  }
1504 
1505  // Use GOT index.
1506  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1507  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1508  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1509  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1510 }
1511 
1512 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1513 SDValue
1515  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1516  SDLoc dl(Op);
1517  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1518 
1519  Reloc::Model RM = HTM.getRelocationModel();
1520  if (RM == Reloc::Static) {
1521  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1522  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1523  }
1524 
1525  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1526  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1527 }
1528 
1529 SDValue
1531  const {
1532  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1535  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1536 }
1537 
1538 SDValue
1540  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1541  unsigned char OperandFlags) const {
1542  MachineFunction &MF = DAG.getMachineFunction();
1543  MachineFrameInfo &MFI = MF.getFrameInfo();
1544  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1545  SDLoc dl(GA);
1546  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1547  GA->getValueType(0),
1548  GA->getOffset(),
1549  OperandFlags);
1550  // Create Operands for the call.The Operands should have the following:
1551  // 1. Chain SDValue
1552  // 2. Callee which in this case is the Global address value.
1553  // 3. Registers live into the call.In this case its R0, as we
1554  // have just one argument to be passed.
1555  // 4. Glue.
1556  // Note: The order is important.
1557 
1558  const auto &HRI = *Subtarget.getRegisterInfo();
1559  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1560  assert(Mask && "Missing call preserved mask for calling convention");
1561  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1562  DAG.getRegisterMask(Mask), Glue };
1563  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1564 
1565  // Inform MFI that function has calls.
1566  MFI.setAdjustsStack(true);
1567 
1568  Glue = Chain.getValue(1);
1569  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1570 }
1571 
1572 //
1573 // Lower using the intial executable model for TLS addresses
1574 //
1575 SDValue
1577  SelectionDAG &DAG) const {
1578  SDLoc dl(GA);
1579  int64_t Offset = GA->getOffset();
1580  auto PtrVT = getPointerTy(DAG.getDataLayout());
1581 
1582  // Get the thread pointer.
1583  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1584 
1585  bool IsPositionIndependent = isPositionIndependent();
1586  unsigned char TF =
1587  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1588 
1589  // First generate the TLS symbol address
1590  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1591  Offset, TF);
1592 
1593  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1594 
1595  if (IsPositionIndependent) {
1596  // Generate the GOT pointer in case of position independent code
1597  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1598 
1599  // Add the TLS Symbol address to GOT pointer.This gives
1600  // GOT relative relocation for the symbol.
1601  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1602  }
1603 
1604  // Load the offset value for TLS symbol.This offset is relative to
1605  // thread pointer.
1606  SDValue LoadOffset =
1607  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1608 
1609  // Address of the thread local variable is the add of thread
1610  // pointer and the offset of the variable.
1611  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1612 }
1613 
1614 //
1615 // Lower using the local executable model for TLS addresses
1616 //
1617 SDValue
1619  SelectionDAG &DAG) const {
1620  SDLoc dl(GA);
1621  int64_t Offset = GA->getOffset();
1622  auto PtrVT = getPointerTy(DAG.getDataLayout());
1623 
1624  // Get the thread pointer.
1625  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1626  // Generate the TLS symbol address
1627  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1629  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1630 
1631  // Address of the thread local variable is the add of thread
1632  // pointer and the offset of the variable.
1633  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1634 }
1635 
1636 //
1637 // Lower using the general dynamic model for TLS addresses
1638 //
1639 SDValue
1641  SelectionDAG &DAG) const {
1642  SDLoc dl(GA);
1643  int64_t Offset = GA->getOffset();
1644  auto PtrVT = getPointerTy(DAG.getDataLayout());
1645 
1646  // First generate the TLS symbol address
1647  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1649 
1650  // Then, generate the GOT pointer
1651  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1652 
1653  // Add the TLS symbol and the GOT pointer
1654  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1655  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1656 
1657  // Copy over the argument to R0
1658  SDValue InFlag;
1659  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1660  InFlag = Chain.getValue(1);
1661 
1662  unsigned Flags =
1663  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1666 
1667  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1668  Hexagon::R0, Flags);
1669 }
1670 
1671 //
1672 // Lower TLS addresses.
1673 //
1674 // For now for dynamic models, we only support the general dynamic model.
1675 //
1676 SDValue
1678  SelectionDAG &DAG) const {
1679  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1680 
1681  switch (HTM.getTLSModel(GA->getGlobal())) {
1684  return LowerToTLSGeneralDynamicModel(GA, DAG);
1685  case TLSModel::InitialExec:
1686  return LowerToTLSInitialExecModel(GA, DAG);
1687  case TLSModel::LocalExec:
1688  return LowerToTLSLocalExecModel(GA, DAG);
1689  }
1690  llvm_unreachable("Bogus TLS model");
1691 }
1692 
1693 //===----------------------------------------------------------------------===//
1694 // TargetLowering Implementation
1695 //===----------------------------------------------------------------------===//
1696 
1698  const HexagonSubtarget &ST)
1699  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1700  Subtarget(ST) {
1701  bool IsV4 = !Subtarget.hasV5TOps();
1702  auto &HRI = *Subtarget.getRegisterInfo();
1703 
1707  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1708 
1711 
1714  else
1716 
1717  // Limits for inline expansion of memcpy/memmove
1724 
1725  //
1726  // Set up register classes.
1727  //
1728 
1729  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1730  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1731  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1732  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1733  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1734  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1735  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1736  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1737  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1738  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1739  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1740 
1741  if (Subtarget.hasV5TOps()) {
1742  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1743  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1744  }
1745 
1746  if (Subtarget.hasV60TOps()) {
1747  if (Subtarget.useHVX64BOps()) {
1748  addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
1749  addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
1750  addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
1751  addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass);
1752  addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
1753  addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
1754  addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
1755  addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);
1756  addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
1757  } else if (Subtarget.useHVX128BOps()) {
1758  addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
1759  addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
1760  addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
1761  addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass);
1762  addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
1763  addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
1764  addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
1765  addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass);
1766  addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass);
1767  }
1768  }
1769 
1770  //
1771  // Handling of scalar operations.
1772  //
1773  // All operations default to "legal", except:
1774  // - indexed loads and stores (pre-/post-incremented),
1775  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1776  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1777  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1778  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1779  // which default to "expand" for at least one type.
1780 
1781  // Misc operations.
1782  setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1783  setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1784 
1797 
1798  // Custom legalize GlobalAddress nodes into CONST32.
1802 
1803  // Hexagon needs to optimize cases with negative constants.
1806 
1807  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1811 
1815 
1816  if (EmitJumpTables)
1818  else
1821 
1822  // Hexagon has instructions for add/sub with carry. The problem with
1823  // modeling these instructions is that they produce 2 results: Rdd and Px.
1824  // To model the update of Px, we will have to use Defs[p0..p3] which will
1825  // cause any predicate live range to spill. So, we pretend we dont't have
1826  // these instructions.
1843 
1844  // Only add and sub that detect overflow are the saturating ones.
1845  for (MVT VT : MVT::integer_valuetypes()) {
1850  }
1851 
1856 
1857  // In V5, popcount can count # of 1s in i64 but returns i32.
1858  // On V4 it will be expanded (set later).
1863 
1869 
1870  for (unsigned IntExpOp :
1875  setOperationAction(IntExpOp, MVT::i32, Expand);
1876  setOperationAction(IntExpOp, MVT::i64, Expand);
1877  }
1878 
1879  for (unsigned FPExpOp :
1882  setOperationAction(FPExpOp, MVT::f32, Expand);
1883  setOperationAction(FPExpOp, MVT::f64, Expand);
1884  }
1885 
1886  // No extending loads from i32.
1887  for (MVT VT : MVT::integer_valuetypes()) {
1891  }
1892  // Turn FP truncstore into trunc + store.
1894  // Turn FP extload into load/fpextend.
1895  for (MVT VT : MVT::fp_valuetypes())
1897 
1898  // Expand BR_CC and SELECT_CC for all integer and fp types.
1899  for (MVT VT : MVT::integer_valuetypes()) {
1902  }
1903  for (MVT VT : MVT::fp_valuetypes()) {
1906  }
1908 
1909  //
1910  // Handling of vector operations.
1911  //
1912 
1913  promoteLdStType(MVT::v4i8, MVT::i32);
1914  promoteLdStType(MVT::v2i16, MVT::i32);
1915  promoteLdStType(MVT::v8i8, MVT::i64);
1916  promoteLdStType(MVT::v4i16, MVT::i64);
1917  promoteLdStType(MVT::v2i32, MVT::i64);
1918 
1919  // Set the action for vector operations to "expand", then override it with
1920  // either "custom" or "legal" for specific cases.
1921  static const unsigned VectExpOps[] = {
1922  // Integer arithmetic:
1927  // Logical/bit:
1930  // Floating point arithmetic/math functions:
1937  // Misc:
1939  // Vector:
1944  };
1945 
1946  for (MVT VT : MVT::vector_valuetypes()) {
1947  for (unsigned VectExpOp : VectExpOps)
1948  setOperationAction(VectExpOp, VT, Expand);
1949 
1950  // Expand all extending loads and truncating stores:
1951  for (MVT TargetVT : MVT::vector_valuetypes()) {
1952  if (TargetVT == VT)
1953  continue;
1954  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1955  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1956  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1957  setTruncStoreAction(VT, TargetVT, Expand);
1958  }
1959 
1960  // Normalize all inputs to SELECT to be vectors of i32.
1961  if (VT.getVectorElementType() != MVT::i32) {
1962  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1964  AddPromotedToType(ISD::SELECT, VT, VT32);
1965  }
1969  }
1970 
1971  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1972  // are legal.
1979 
1980  // Types natively supported:
1981  for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1983  MVT::v2i32, MVT::v1i64}) {
1990 
1991  setOperationAction(ISD::ADD, NativeVT, Legal);
1992  setOperationAction(ISD::SUB, NativeVT, Legal);
1993  setOperationAction(ISD::MUL, NativeVT, Legal);
1994  setOperationAction(ISD::AND, NativeVT, Legal);
1995  setOperationAction(ISD::OR, NativeVT, Legal);
1996  setOperationAction(ISD::XOR, NativeVT, Legal);
1997  }
1998 
2001  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
2002  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
2003 
2004  if (Subtarget.useHVXOps()) {
2005  if (Subtarget.useHVX64BOps()) {
2010  // We try to generate the vpack{e/o} instructions. If we fail
2011  // we fall back upon ExpandOp.
2012  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
2013  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
2017  } else if (Subtarget.useHVX128BOps()) {
2022  // We try to generate the vpack{e/o} instructions. If we fail
2023  // we fall back upon ExpandOp.
2024  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
2025  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
2030  } else {
2031  llvm_unreachable("Unrecognized HVX mode");
2032  }
2033  }
2034  // Subtarget-specific operation actions.
2035  //
2036  if (Subtarget.hasV5TOps()) {
2041 
2044 
2057  } else { // V4
2067 
2072 
2073  // Expand these operations for both f32 and f64:
2074  for (unsigned FPExpOpV4 :
2076  setOperationAction(FPExpOpV4, MVT::f32, Expand);
2077  setOperationAction(FPExpOpV4, MVT::f64, Expand);
2078  }
2079 
2080  for (ISD::CondCode FPExpCCV4 :
2082  ISD::SETUO, ISD::SETO}) {
2083  setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2084  setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2085  }
2086  }
2087 
2088  // Handling of indexed loads/stores: default is "expand".
2089  //
2090  for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2093  }
2094 
2095  if (Subtarget.useHVX64BOps()) {
2100  }
2101  } else if (Subtarget.useHVX128BOps()) {
2106  }
2107  }
2108 
2110 
2111  //
2112  // Library calls for unsupported operations
2113  //
2114  bool FastMath = EnableFastMath;
2115 
2116  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2117  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2118  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2119  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2120  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2121  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2122  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2123  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2124 
2125  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2126  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2127  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2128  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2129  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2130  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2131 
2132  if (IsV4) {
2133  // Handle single-precision floating point operations on V4.
2134  if (FastMath) {
2135  setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2136  setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2137  setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2138  setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2139  setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2140  // Double-precision compares.
2141  setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2142  setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2143  } else {
2144  setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2145  setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2146  setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2147  setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2148  setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2149  // Double-precision compares.
2150  setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2151  setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2152  }
2153  }
2154 
2155  // This is the only fast library function for sqrtd.
2156  if (FastMath)
2157  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2158 
2159  // Prefix is: nothing for "slow-math",
2160  // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2161  // (actually, keep fast-math and fast-math2 separate for now)
2162  if (FastMath) {
2163  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2164  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2165  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2166  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2167  // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2168  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2169  } else {
2170  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2171  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2172  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2173  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2174  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2175  }
2176 
2177  if (Subtarget.hasV5TOps()) {
2178  if (FastMath)
2179  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2180  else
2181  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2182  } else {
2183  // V4
2184  setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2185  setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2186  setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2187  setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2188  setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2189  setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2190  setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2191  setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2192  setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2193  setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2194  setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2195  setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2196  setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2197  setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2198  setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2199  setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2200  setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2201  setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2202  setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2203  setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2204  setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2205  setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2206  setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2207  setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2208  setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2209  setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2210  setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2211  setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2212  setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2213  setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2214  }
2215 
2216  // These cause problems when the shift amount is non-constant.
2217  setLibcallName(RTLIB::SHL_I128, nullptr);
2218  setLibcallName(RTLIB::SRL_I128, nullptr);
2219  setLibcallName(RTLIB::SRA_I128, nullptr);
2220 }
2221 
2222 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2223  switch ((HexagonISD::NodeType)Opcode) {
2224  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2225  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2226  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2227  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2228  case HexagonISD::CALL: return "HexagonISD::CALL";
2229  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2230  case HexagonISD::CALLR: return "HexagonISD::CALLR";
2231  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2232  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2233  case HexagonISD::CONST32: return "HexagonISD::CONST32";
2234  case HexagonISD::CP: return "HexagonISD::CP";
2235  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2236  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2237  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2238  case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2239  case HexagonISD::INSERT: return "HexagonISD::INSERT";
2240  case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2241  case HexagonISD::JT: return "HexagonISD::JT";
2242  case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2243  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2244  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2245  case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2246  case HexagonISD::VPACKE: return "HexagonISD::VPACKE";
2247  case HexagonISD::VPACKO: return "HexagonISD::VPACKO";
2248  case HexagonISD::VASL: return "HexagonISD::VASL";
2249  case HexagonISD::VASR: return "HexagonISD::VASR";
2250  case HexagonISD::VLSR: return "HexagonISD::VLSR";
2251  case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
2252  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
2253  case HexagonISD::OP_END: break;
2254  }
2255  return nullptr;
2256 }
2257 
2259  EVT MTy1 = EVT::getEVT(Ty1);
2260  EVT MTy2 = EVT::getEVT(Ty2);
2261  if (!MTy1.isSimple() || !MTy2.isSimple())
2262  return false;
2263  return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2264 }
2265 
2267  if (!VT1.isSimple() || !VT2.isSimple())
2268  return false;
2269  return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2270 }
2271 
2273  return isOperationLegalOrCustom(ISD::FMA, VT);
2274 }
2275 
2276 // Should we expand the build vector with shuffles?
2278  unsigned DefinedValues) const {
2279  // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2280  EVT EltVT = VT.getVectorElementType();
2281  int EltBits = EltVT.getSizeInBits();
2282  if ((EltBits != 8) && (EltBits != 16))
2283  return false;
2284 
2285  return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2286 }
2287 
2289  int even_start = -2;
2290  int odd_start = -1;
2291  size_t mask_len = Mask.size();
2292  for (auto idx : Mask) {
2293  if ((idx - even_start) == 2)
2294  even_start = idx;
2295  else
2296  break;
2297  }
2298  if (even_start == (int)(mask_len * 2) - 2)
2299  return StridedLoadKind::Even;
2300  for (auto idx : Mask) {
2301  if ((idx - odd_start) == 2)
2302  odd_start = idx;
2303  else
2304  break;
2305  }
2306  if (odd_start == (int)(mask_len * 2) - 1)
2307  return StridedLoadKind::Odd;
2308 
2309  return StridedLoadKind::NoPattern;
2310 }
2311 
2313  EVT VT) const {
2314  if (Subtarget.useHVXOps())
2315  return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2316  return true;
2317 }
2318 
2319 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2320 // to select data from, V3 is the permutation.
2321 SDValue
2323  const {
2324  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2325  SDValue V1 = Op.getOperand(0);
2326  SDValue V2 = Op.getOperand(1);
2327  SDLoc dl(Op);
2328  EVT VT = Op.getValueType();
2329  bool UseHVX = Subtarget.useHVXOps();
2330 
2331  if (V2.isUndef())
2332  V2 = V1;
2333 
2334  if (SVN->isSplat()) {
2335  int Lane = SVN->getSplatIndex();
2336  if (Lane == -1) Lane = 0;
2337 
2338  // Test if V1 is a SCALAR_TO_VECTOR.
2339  if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2340  return DAG.getNode(HexagonISD::VSPLAT, dl, VT, V1.getOperand(0));
2341 
2342  // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2343  // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2344  // reaches it).
2345  if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2346  !isa<ConstantSDNode>(V1.getOperand(0))) {
2347  bool IsScalarToVector = true;
2348  for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2349  if (!V1.getOperand(i).isUndef()) {
2350  IsScalarToVector = false;
2351  break;
2352  }
2353  }
2354  if (IsScalarToVector)
2355  return DAG.getNode(HexagonISD::VSPLAT, dl, VT, V1.getOperand(0));
2356  }
2357  return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
2358  DAG.getConstant(Lane, dl, MVT::i32));
2359  }
2360 
2361  if (UseHVX) {
2362  ArrayRef<int> Mask = SVN->getMask();
2363  size_t MaskLen = Mask.size();
2364  unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;
2365 
2366  if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) ||
2367  (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) {
2368  StridedLoadKind Pattern = isStridedLoad(Mask);
2369  if (Pattern == StridedLoadKind::NoPattern)
2370  return SDValue();
2371 
2372  unsigned Opc = Pattern == StridedLoadKind::Even ? HexagonISD::VPACKE
2374  return DAG.getNode(Opc, dl, VT, {Op.getOperand(1), Op.getOperand(0)});
2375  }
2376  // We used to assert in the "else" part here, but that is bad for Halide
2377  // Halide creates intermediate double registers by interleaving two
2378  // concatenated vector registers. The interleaving requires vector_shuffle
2379  // nodes and we shouldn't barf on a double register result of a
2380  // vector_shuffle because it is most likely an intermediate result.
2381  }
2382  // FIXME: We need to support more general vector shuffles. See
2383  // below the comment from the ARM backend that deals in the general
2384  // case with the vector shuffles. For now, let expand handle these.
2385  return SDValue();
2386 
2387  // If the shuffle is not directly supported and it has 4 elements, use
2388  // the PerfectShuffle-generated table to synthesize it from other shuffles.
2389 }
2390 
2391 // If BUILD_VECTOR has same base element repeated several times,
2392 // report true.
2394  unsigned NElts = BVN->getNumOperands();
2395  SDValue V0 = BVN->getOperand(0);
2396 
2397  for (unsigned i = 1, e = NElts; i != e; ++i) {
2398  if (BVN->getOperand(i) != V0)
2399  return false;
2400  }
2401  return true;
2402 }
2403 
2404 // Lower a vector shift. Try to convert
2405 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2406 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2407 SDValue
2409  BuildVectorSDNode *BVN = nullptr;
2410  SDValue V1 = Op.getOperand(0);
2411  SDValue V2 = Op.getOperand(1);
2412  SDValue V3;
2413  SDLoc dl(Op);
2414  EVT VT = Op.getValueType();
2415 
2416  if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2417  isCommonSplatElement(BVN))
2418  V3 = V2;
2419  else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2420  isCommonSplatElement(BVN))
2421  V3 = V1;
2422  else
2423  return SDValue();
2424 
2425  SDValue CommonSplat = BVN->getOperand(0);
2426  SDValue Result;
2427 
2428  if (VT.getSimpleVT() == MVT::v4i16) {
2429  switch (Op.getOpcode()) {
2430  case ISD::SRA:
2431  Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
2432  break;
2433  case ISD::SHL:
2434  Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
2435  break;
2436  case ISD::SRL:
2437  Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
2438  break;
2439  default:
2440  return SDValue();
2441  }
2442  } else if (VT.getSimpleVT() == MVT::v2i32) {
2443  switch (Op.getOpcode()) {
2444  case ISD::SRA:
2445  Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
2446  break;
2447  case ISD::SHL:
2448  Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
2449  break;
2450  case ISD::SRL:
2451  Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
2452  break;
2453  default:
2454  return SDValue();
2455  }
2456  } else {
2457  return SDValue();
2458  }
2459 
2460  return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2461 }
2462 
2463 SDValue
2465  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2466  SDLoc dl(Op);
2467  EVT VT = Op.getValueType();
2468 
2469  unsigned Size = VT.getSizeInBits();
2470 
2471  // Only handle vectors of 64 bits or shorter.
2472  if (Size > 64)
2473  return SDValue();
2474 
2475  unsigned NElts = BVN->getNumOperands();
2476 
2477  // Try to generate a SPLAT instruction.
2478  if (VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v2i32) {
2479  APInt APSplatBits, APSplatUndef;
2480  unsigned SplatBitSize;
2481  bool HasAnyUndefs;
2482  if (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2483  HasAnyUndefs, 0, false)) {
2484  if (SplatBitSize == VT.getVectorElementType().getSizeInBits()) {
2485  unsigned ZV = APSplatBits.getZExtValue();
2486  assert(SplatBitSize <= 32 && "Can only handle up to i32");
2487  // Sign-extend the splat value from SplatBitSize to 32.
2488  int32_t SV = SplatBitSize < 32
2489  ? int32_t(ZV << (32-SplatBitSize)) >> (32-SplatBitSize)
2490  : int32_t(ZV);
2491  return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
2492  DAG.getConstant(SV, dl, MVT::i32));
2493  }
2494  }
2495  }
2496 
2497  // Try to generate COMBINE to build v2i32 vectors.
2498  if (VT.getSimpleVT() == MVT::v2i32) {
2499  SDValue V0 = BVN->getOperand(0);
2500  SDValue V1 = BVN->getOperand(1);
2501 
2502  if (V0.isUndef())
2503  V0 = DAG.getConstant(0, dl, MVT::i32);
2504  if (V1.isUndef())
2505  V1 = DAG.getConstant(0, dl, MVT::i32);
2506 
2509  // If the element isn't a constant, it is in a register:
2510  // generate a COMBINE Register Register instruction.
2511  if (!C0 || !C1)
2512  return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2513 
2514  // If one of the operands is an 8 bit integer constant, generate
2515  // a COMBINE Immediate Immediate instruction.
2516  if (isInt<8>(C0->getSExtValue()) ||
2517  isInt<8>(C1->getSExtValue()))
2518  return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2519  }
2520 
2521  // Try to generate a S2_packhl to build v2i16 vectors.
2522  if (VT.getSimpleVT() == MVT::v2i16) {
2523  for (unsigned i = 0, e = NElts; i != e; ++i) {
2524  if (BVN->getOperand(i).isUndef())
2525  continue;
2527  // If the element isn't a constant, it is in a register:
2528  // generate a S2_packhl instruction.
2529  if (!Cst) {
2530  SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2531  BVN->getOperand(1), BVN->getOperand(0));
2532 
2533  return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2534  pack);
2535  }
2536  }
2537  }
2538 
2539  // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2540  // and insert_vector_elt for all the other cases.
2541  uint64_t Res = 0;
2542  unsigned EltSize = Size / NElts;
2543  SDValue ConstVal;
2544  uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2545  bool HasNonConstantElements = false;
2546 
2547  for (unsigned i = 0, e = NElts; i != e; ++i) {
2548  // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2549  // combine, const64, etc. are Big Endian.
2550  unsigned OpIdx = NElts - i - 1;
2551  SDValue Operand = BVN->getOperand(OpIdx);
2552  if (Operand.isUndef())
2553  continue;
2554 
2555  int64_t Val = 0;
2556  if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2557  Val = Cst->getSExtValue();
2558  else
2559  HasNonConstantElements = true;
2560 
2561  Val &= Mask;
2562  Res = (Res << EltSize) | Val;
2563  }
2564 
2565  if (Size > 64)
2566  return SDValue();
2567 
2568  if (Size == 64)
2569  ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2570  else
2571  ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2572 
2573  // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2574  // ConstVal, the constant part of the vector.
2575  if (HasNonConstantElements) {
2576  EVT EltVT = VT.getVectorElementType();
2577  SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2578  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2579  DAG.getConstant(32, dl, MVT::i64));
2580 
2581  for (unsigned i = 0, e = NElts; i != e; ++i) {
2582  // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2583  // is Big Endian.
2584  unsigned OpIdx = NElts - i - 1;
2585  SDValue Operand = BVN->getOperand(OpIdx);
2586  if (isa<ConstantSDNode>(Operand))
2587  // This operand is already in ConstVal.
2588  continue;
2589 
2590  if (VT.getSizeInBits() == 64 &&
2591  Operand.getValueSizeInBits() == 32) {
2592  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2593  Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2594  }
2595 
2596  SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2597  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2598  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2599  const SDValue Ops[] = {ConstVal, Operand, Combined};
2600 
2601  if (VT.getSizeInBits() == 32)
2602  ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2603  else
2604  ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2605  }
2606  }
2607 
2608  return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2609 }
2610 
2611 SDValue
2613  SelectionDAG &DAG) const {
2614  SDLoc dl(Op);
2615  bool UseHVX = Subtarget.useHVXOps();
2616  EVT VT = Op.getValueType();
2617  unsigned NElts = Op.getNumOperands();
2618  SDValue Vec0 = Op.getOperand(0);
2619  EVT VecVT = Vec0.getValueType();
2620  unsigned Width = VecVT.getSizeInBits();
2621 
2622  if (NElts == 2) {
2623  MVT ST = VecVT.getSimpleVT();
2624  // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2625  // into a single v8i8.
2626  if (ST == MVT::v2i16 || ST == MVT::v4i8)
2627  return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2628 
2629  if (UseHVX) {
2630  assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) ||
2631  (Width == 128 * 8 && Subtarget.useHVX128BOps()));
2632  SDValue Vec1 = Op.getOperand(1);
2633  MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32;
2634  MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32;
2635  SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2636  SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2637  SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2638  return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2639  }
2640  }
2641 
2642  if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2643  return SDValue();
2644 
2645  SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2646  SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2647  SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2648  // Create the "width" part of the argument to insert_rp/insertp_rp.
2649  SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2650  SDValue V = C0;
2651 
2652  for (unsigned i = 0, e = NElts; i != e; ++i) {
2653  unsigned N = NElts-i-1;
2654  SDValue OpN = Op.getOperand(N);
2655 
2656  if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2657  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2658  OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2659  }
2660  SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2661  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2662  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2663  if (VT.getSizeInBits() == 32)
2664  V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2665  else if (VT.getSizeInBits() == 64)
2666  V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2667  else
2668  return SDValue();
2669  }
2670 
2671  return DAG.getNode(ISD::BITCAST, dl, VT, V);
2672 }
2673 
2674 SDValue
2676  SelectionDAG &DAG) const {
2677  EVT VT = Op.getOperand(0).getValueType();
2678  SDLoc dl(Op);
2679  bool UseHVX = Subtarget.useHVXOps();
2680  bool UseHVX64B = Subtarget.useHVX64BOps();
2681  // Just in case...
2682 
2683  if (!VT.isVector() || !UseHVX)
2684  return SDValue();
2685 
2686  EVT ResVT = Op.getValueType();
2687  unsigned ResSize = ResVT.getSizeInBits();
2688  unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8);
2689  unsigned OpSize = VT.getSizeInBits();
2690 
2691  // We deal only with cases where the result is the vector size
2692  // and the vector operand is a double register.
2693  if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2694  !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2695  return SDValue();
2696 
2698  if (!Cst)
2699  return SDValue();
2700  unsigned Val = Cst->getZExtValue();
2701 
2702  // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2703  if (Val == 0) {
2704  SDValue Vec = Op.getOperand(0);
2705  return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2706  }
2707 
2708  if (ResVT.getVectorNumElements() == Val) {
2709  SDValue Vec = Op.getOperand(0);
2710  return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2711  }
2712 
2713  return SDValue();
2714 }
2715 
2716 SDValue
2718  SelectionDAG &DAG) const {
2719  // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2720  // be able to simplify it to an EXTRACT_SUBREG.
2721  if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2723  return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2724 
2725  EVT VT = Op.getValueType();
2726  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2727  SDLoc dl(Op);
2728  SDValue Idx = Op.getOperand(1);
2729  SDValue Vec = Op.getOperand(0);
2730  EVT VecVT = Vec.getValueType();
2731  EVT EltVT = VecVT.getVectorElementType();
2732  int EltSize = EltVT.getSizeInBits();
2734  EltSize : VTN * EltSize, dl, MVT::i64);
2735 
2736  // Constant element number.
2737  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2738  uint64_t X = CI->getZExtValue();
2739  SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2740  const SDValue Ops[] = {Vec, Width, Offset};
2741 
2742  ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2743  assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2744 
2745  SDValue N;
2746  MVT SVT = VecVT.getSimpleVT();
2747  uint64_t W = CW->getZExtValue();
2748 
2749  if (W == 1) {
2750  MVT LocVT = MVT::getIntegerVT(SVT.getSizeInBits());
2751  SDValue VecCast = DAG.getNode(ISD::BITCAST, dl, LocVT, Vec);
2752  SDValue Shifted = DAG.getNode(ISD::SRA, dl, LocVT, VecCast, Offset);
2753  return DAG.getNode(ISD::AND, dl, LocVT, Shifted,
2754  DAG.getConstant(1, dl, LocVT));
2755  } else if (W == 32) {
2756  // Translate this node into EXTRACT_SUBREG.
2757  unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
2758 
2759  if (X == 0)
2760  Subreg = Hexagon::isub_lo;
2761  else if (SVT == MVT::v2i32 && X == 1)
2762  Subreg = Hexagon::isub_hi;
2763  else if (SVT == MVT::v4i16 && X == 2)
2764  Subreg = Hexagon::isub_hi;
2765  else if (SVT == MVT::v8i8 && X == 4)
2766  Subreg = Hexagon::isub_hi;
2767  else
2768  llvm_unreachable("Bad offset");
2769  N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2770 
2771  } else if (SVT.getSizeInBits() == 32) {
2772  N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2773  } else if (SVT.getSizeInBits() == 64) {
2774  N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2775  if (VT.getSizeInBits() == 32)
2776  N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2777  } else
2778  return SDValue();
2779 
2780  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2781  }
2782 
2783  // Variable element number.
2784  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2785  DAG.getConstant(EltSize, dl, MVT::i32));
2786  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2787  DAG.getConstant(32, dl, MVT::i64));
2788  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2789 
2790  const SDValue Ops[] = {Vec, Combined};
2791 
2792  SDValue N;
2793  if (VecVT.getSizeInBits() == 32) {
2794  N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2795  } else {
2796  N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2797  if (VT.getSizeInBits() == 32)
2798  N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2799  }
2800  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2801 }
2802 
2803 SDValue
2805  SelectionDAG &DAG) const {
2806  EVT VT = Op.getValueType();
2807  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2808  SDLoc dl(Op);
2809  SDValue Vec = Op.getOperand(0);
2810  SDValue Val = Op.getOperand(1);
2811  SDValue Idx = Op.getOperand(2);
2812  EVT VecVT = Vec.getValueType();
2813  EVT EltVT = VecVT.getVectorElementType();
2814  int EltSize = EltVT.getSizeInBits();
2815  SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2816  EltSize : VTN * EltSize, dl, MVT::i64);
2817 
2818  if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2819  SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2820  const SDValue Ops[] = {Vec, Val, Width, Offset};
2821 
2822  SDValue N;
2823  if (VT.getSizeInBits() == 32)
2824  N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2825  else if (VT.getSizeInBits() == 64)
2826  N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2827  else
2828  return SDValue();
2829 
2830  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2831  }
2832 
2833  // Variable element number.
2834  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2835  DAG.getConstant(EltSize, dl, MVT::i32));
2836  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2837  DAG.getConstant(32, dl, MVT::i64));
2838  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2839 
2840  if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2841  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2842  Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2843  }
2844 
2845  const SDValue Ops[] = {Vec, Val, Combined};
2846 
2847  SDValue N;
2848  if (VT.getSizeInBits() == 32)
2849  N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2850  else if (VT.getSizeInBits() == 64)
2851  N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2852  else
2853  return SDValue();
2854 
2855  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2856 }
2857 
2858 bool
2860  // Assuming the caller does not have either a signext or zeroext modifier, and
2861  // only one value is accepted, any reasonable truncation is allowed.
2862  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2863  return false;
2864 
2865  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2866  // fragile at the moment: any support for multiple value returns would be
2867  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2868  return Ty1->getPrimitiveSizeInBits() <= 32;
2869 }
2870 
2871 SDValue
2873  SDValue Chain = Op.getOperand(0);
2874  SDValue Offset = Op.getOperand(1);
2875  SDValue Handler = Op.getOperand(2);
2876  SDLoc dl(Op);
2877  auto PtrVT = getPointerTy(DAG.getDataLayout());
2878 
2879  // Mark function as containing a call to EH_RETURN.
2880  HexagonMachineFunctionInfo *FuncInfo =
2882  FuncInfo->setHasEHReturn();
2883 
2884  unsigned OffsetReg = Hexagon::R28;
2885 
2886  SDValue StoreAddr =
2887  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2888  DAG.getIntPtrConstant(4, dl));
2889  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2890  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2891 
2892  // Not needed we already use it as explict input to EH_RETURN.
2893  // MF.getRegInfo().addLiveOut(OffsetReg);
2894 
2895  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2896 }
2897 
2898 SDValue
2900  unsigned Opc = Op.getOpcode();
2901  switch (Opc) {
2902  default:
2903 #ifndef NDEBUG
2904  Op.getNode()->dumpr(&DAG);
2905  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2906  errs() << "Check for a non-legal type in this operation\n";
2907 #endif
2908  llvm_unreachable("Should not custom lower this!");
2909  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2910  case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2911  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2912  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2913  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2914  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2915  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2916  case ISD::SRA:
2917  case ISD::SHL:
2918  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2919  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2920  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2921  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2922  // Frame & Return address. Currently unimplemented.
2923  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2924  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2925  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2926  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2927  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2928  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2929  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2930  case ISD::VASTART: return LowerVASTART(Op, DAG);
2931  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2932  case ISD::SETCC: return LowerSETCC(Op, DAG);
2933  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2934  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2935  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2936  case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2937  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2938  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2939  }
2940 }
2941 
2942 /// Returns relocation base for the given PIC jumptable.
2943 SDValue
2945  SelectionDAG &DAG) const {
2946  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2947  EVT VT = Table.getValueType();
2949  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2950 }
2951 
2952 //===----------------------------------------------------------------------===//
2953 // Inline Assembly Support
2954 //===----------------------------------------------------------------------===//
2955 
2958  if (Constraint.size() == 1) {
2959  switch (Constraint[0]) {
2960  case 'q':
2961  case 'v':
2962  if (Subtarget.useHVXOps())
2963  return C_RegisterClass;
2964  break;
2965  case 'a':
2966  return C_RegisterClass;
2967  default:
2968  break;
2969  }
2970  }
2971  return TargetLowering::getConstraintType(Constraint);
2972 }
2973 
2974 std::pair<unsigned, const TargetRegisterClass*>
2976  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2977 
2978  if (Constraint.size() == 1) {
2979  switch (Constraint[0]) {
2980  case 'r': // R0-R31
2981  switch (VT.SimpleTy) {
2982  default:
2983  return {0u, nullptr};
2984  case MVT::i1:
2985  case MVT::i8:
2986  case MVT::i16:
2987  case MVT::i32:
2988  case MVT::f32:
2989  return {0u, &Hexagon::IntRegsRegClass};
2990  case MVT::i64:
2991  case MVT::f64:
2992  return {0u, &Hexagon::DoubleRegsRegClass};
2993  }
2994  break;
2995  case 'a': // M0-M1
2996  if (VT != MVT::i32)
2997  return {0u, nullptr};
2998  return {0u, &Hexagon::ModRegsRegClass};
2999  case 'q': // q0-q3
3000  switch (VT.getSizeInBits()) {
3001  default:
3002  return {0u, nullptr};
3003  case 512:
3004  case 1024:
3005  return {0u, &Hexagon::HvxQRRegClass};
3006  }
3007  break;
3008  case 'v': // V0-V31
3009  switch (VT.getSizeInBits()) {
3010  default:
3011  return {0u, nullptr};
3012  case 512:
3013  return {0u, &Hexagon::HvxVRRegClass};
3014  case 1024:
3015  if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
3016  return {0u, &Hexagon::HvxVRRegClass};
3017  return {0u, &Hexagon::HvxWRRegClass};
3018  case 2048:
3019  return {0u, &Hexagon::HvxWRRegClass};
3020  }
3021  break;
3022  default:
3023  return {0u, nullptr};
3024  }
3025  }
3026 
3027  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3028 }
3029 
3030 /// isFPImmLegal - Returns true if the target can instruction select the
3031 /// specified FP immediate natively. If false, the legalizer will
3032 /// materialize the FP immediate as a load from a constant pool.
3034  return Subtarget.hasV5TOps();
3035 }
3036 
3037 /// isLegalAddressingMode - Return true if the addressing mode represented by
3038 /// AM is legal for this target, for a load/store of the specified type.
3040  const AddrMode &AM, Type *Ty,
3041  unsigned AS, Instruction *I) const {
3042  if (Ty->isSized()) {
3043  // When LSR detects uses of the same base address to access different
3044  // types (e.g. unions), it will assume a conservative type for these
3045  // uses:
3046  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3047  // The type Ty passed here would then be "void". Skip the alignment
3048  // checks, but do not return false right away, since that confuses
3049  // LSR into crashing.
3050  unsigned A = DL.getABITypeAlignment(Ty);
3051  // The base offset must be a multiple of the alignment.
3052  if ((AM.BaseOffs % A) != 0)
3053  return false;
3054  // The shifted offset must fit in 11 bits.
3055  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3056  return false;
3057  }
3058 
3059  // No global is ever allowed as a base.
3060  if (AM.BaseGV)
3061  return false;
3062 
3063  int Scale = AM.Scale;
3064  if (Scale < 0)
3065  Scale = -Scale;
3066  switch (Scale) {
3067  case 0: // No scale reg, "r+i", "r", or just "i".
3068  break;
3069  default: // No scaled addressing mode.
3070  return false;
3071  }
3072  return true;
3073 }
3074 
3075 /// Return true if folding a constant offset with the given GlobalAddress is
3076 /// legal. It is frequently not legal in PIC relocation models.
3078  const {
3079  return HTM.getRelocationModel() == Reloc::Static;
3080 }
3081 
3082 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3083 /// icmp immediate, that is the target has icmp instructions which can compare
3084 /// a register against the immediate without having to materialize the
3085 /// immediate into a register.
3087  return Imm >= -512 && Imm <= 511;
3088 }
3089 
3090 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3091 /// for tail call optimization. Targets which want to do tail call
3092 /// optimization should implement this function.
3094  SDValue Callee,
3095  CallingConv::ID CalleeCC,
3096  bool isVarArg,
3097  bool isCalleeStructRet,
3098  bool isCallerStructRet,
3099  const SmallVectorImpl<ISD::OutputArg> &Outs,
3100  const SmallVectorImpl<SDValue> &OutVals,
3102  SelectionDAG& DAG) const {
3103  const Function *CallerF = DAG.getMachineFunction().getFunction();
3104  CallingConv::ID CallerCC = CallerF->getCallingConv();
3105  bool CCMatch = CallerCC == CalleeCC;
3106 
3107  // ***************************************************************************
3108  // Look for obvious safe cases to perform tail call optimization that do not
3109  // require ABI changes.
3110  // ***************************************************************************
3111 
3112  // If this is a tail call via a function pointer, then don't do it!
3113  if (!isa<GlobalAddressSDNode>(Callee) &&
3114  !isa<ExternalSymbolSDNode>(Callee)) {
3115  return false;
3116  }
3117 
3118  // Do not optimize if the calling conventions do not match and the conventions
3119  // used are not C or Fast.
3120  if (!CCMatch) {
3121  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3122  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3123  // If R & E, then ok.
3124  if (!R || !E)
3125  return false;
3126  }
3127 
3128  // Do not tail call optimize vararg calls.
3129  if (isVarArg)
3130  return false;
3131 
3132  // Also avoid tail call optimization if either caller or callee uses struct
3133  // return semantics.
3134  if (isCalleeStructRet || isCallerStructRet)
3135  return false;
3136 
3137  // In addition to the cases above, we also disable Tail Call Optimization if
3138  // the calling convention code that at least one outgoing argument needs to
3139  // go on the stack. We cannot check that here because at this point that
3140  // information is not available.
3141  return true;
3142 }
3143 
3144 /// Returns the target specific optimal type for load and store operations as
3145 /// a result of memset, memcpy, and memmove lowering.
3146 ///
3147 /// If DstAlign is zero that means it's safe to destination alignment can
3148 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3149 /// a need to check it against alignment requirement, probably because the
3150 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3151 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3152 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3153 /// does not need to be loaded. It returns EVT::Other if the type should be
3154 /// determined using generic target-independent logic.
3156  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3157  bool MemcpyStrSrc, MachineFunction &MF) const {
3158 
3159  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3160  return (GivenA % MinA) == 0;
3161  };
3162 
3163  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3164  return MVT::i64;
3165  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3166  return MVT::i32;
3167  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3168  return MVT::i16;
3169 
3170  return MVT::Other;
3171 }
3172 
3174  unsigned AS, unsigned Align, bool *Fast) const {
3175  if (Fast)
3176  *Fast = false;
3177 
3178  switch (VT.getSimpleVT().SimpleTy) {
3179  default:
3180  return false;
3181  case MVT::v64i8:
3182  case MVT::v128i8:
3183  case MVT::v256i8:
3184  case MVT::v32i16:
3185  case MVT::v64i16:
3186  case MVT::v128i16:
3187  case MVT::v16i32:
3188  case MVT::v32i32:
3189  case MVT::v64i32:
3190  case MVT::v8i64:
3191  case MVT::v16i64:
3192  case MVT::v32i64:
3193  return true;
3194  }
3195  return false;
3196 }
3197 
3198 std::pair<const TargetRegisterClass*, uint8_t>
3200  MVT VT) const {
3201  const TargetRegisterClass *RRC = nullptr;
3202 
3203  uint8_t Cost = 1;
3204  switch (VT.SimpleTy) {
3205  default:
3207  case MVT::v64i8:
3208  case MVT::v32i16:
3209  case MVT::v16i32:
3210  case MVT::v8i64:
3211  RRC = &Hexagon::HvxVRRegClass;
3212  break;
3213  case MVT::v128i8:
3214  case MVT::v64i16:
3215  case MVT::v32i32:
3216  case MVT::v16i64:
3217  if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3218  Subtarget.useHVX128BOps())
3219  RRC = &Hexagon::HvxVRRegClass;
3220  else
3221  RRC = &Hexagon::HvxWRRegClass;
3222  break;
3223  case MVT::v256i8:
3224  case MVT::v128i16:
3225  case MVT::v64i32:
3226  case MVT::v32i64:
3227  RRC = &Hexagon::HvxWRRegClass;
3228  break;
3229  }
3230  return std::make_pair(RRC, Cost);
3231 }
3232 
3234  AtomicOrdering Ord) const {
3235  BasicBlock *BB = Builder.GetInsertBlock();
3236  Module *M = BB->getParent()->getParent();
3237  Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3238  unsigned SZ = Ty->getPrimitiveSizeInBits();
3239  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3240  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3241  : Intrinsic::hexagon_L4_loadd_locked;
3242  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3243  return Builder.CreateCall(Fn, Addr, "larx");
3244 }
3245 
3246 /// Perform a store-conditional operation to Addr. Return the status of the
3247 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3249  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3250  BasicBlock *BB = Builder.GetInsertBlock();
3251  Module *M = BB->getParent()->getParent();
3252  Type *Ty = Val->getType();
3253  unsigned SZ = Ty->getPrimitiveSizeInBits();
3254  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3255  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3256  : Intrinsic::hexagon_S4_stored_locked;
3257  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3258  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3259  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3260  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3261  return Ext;
3262 }
3263 
3266  // Do not expand loads and stores that don't exceed 64 bits.
3267  return LI->getType()->getPrimitiveSizeInBits() > 64
3270 }
3271 
3273  // Do not expand loads and stores that don't exceed 64 bits.
3274  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3275 }
3276 
3278  AtomicCmpXchgInst *AI) const {
3279  const DataLayout &DL = AI->getModule()->getDataLayout();
3280  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3281  return Size >= 4 && Size <= 8;
3282 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
bool isMachineConstantPoolEntry() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
Type * getVectorElementType() const
Definition: Type.h:368
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:545
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:512
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
Definition: Instructions.h:395
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:569
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isUndef() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:333
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:342
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:262
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Y = RRC X, rotate right via carry.
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:666
This class represents a function call, abstracting a target machine&#39;s calling convention.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
unsigned getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:295
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:728
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Hexagon target-specific information for each MachineFunction.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
unsigned second
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
F(f)
An instruction for reading from memory.
Definition: Instructions.h:164
MachineFunction & getMachineFunction() const
SDNode * getNode() const
get the SDNode which holds the desired result
#define R2(n)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:253
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:212
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:328
The address of the GOT.
Definition: ISDOpcodes.h:66
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:748
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
Definition: ISDOpcodes.h:955
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:511
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:813
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Shift and rotation operations.
Definition: ISDOpcodes.h:379
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:237
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
#define Hexagon_PointerSize
Definition: Hexagon.h:20
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:446
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:634
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:662
unsigned getSizeInBits() const
int64_t getSExtValue() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:298
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:455
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
#define T
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:122
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:398
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
An instruction for storing to memory.
Definition: Instructions.h:306
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1387
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:714
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:949
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
amdgpu Simplify well known AMD library false Value * Callee
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:980
MVT getVectorElementType() const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Value * getOperand(unsigned i) const
Definition: User.h:154
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
This class is used to represent ISD::STORE nodes.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:498
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:302
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:357
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:421
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
Definition: ISDOpcodes.h:259
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, SDValue &Base, SDValue &Offset, bool &IsInc, SelectionDAG &DAG)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:695
const SDValue & getOperand(unsigned Num) const
static bool CC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:307
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const APInt & getAPIntValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
static mvt_range vector_valuetypes()
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:1550
Constant Vector Declarations.
Definition: Constants.h:491
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:686
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:530
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static bool isSExtFree(SDValue N)
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:617
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:611
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void dump() const
Dump this node, for debugging.
#define HEXAGON_LRFP_SIZE
Definition: Hexagon.h:27
unsigned getNumOperands() const
Definition: User.h:176
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:314
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
#define HEXAGON_GOT_SYM_NAME
Definition: Hexagon.h:43
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
static bool isHvxVectorType(MVT ty)
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
Module.h This file contains the declarations for the Module class.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:682
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:382
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
CHAIN = SC CHAIN, Imm128 - System call.
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:308
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:531
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:57
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
static StridedLoadKind isStridedLoad(const ArrayRef< int > &Mask)
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
bool isTailCall() const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:287
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:651
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:151
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
MO_GOT - Indicates a GOT-relative relocation.
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
LOAD and STORE have token chains as th