LLVM  7.0.0svn
HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonISelLowering.h"
16 #include "Hexagon.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/IR/Value.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <limits>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-lowering"
66 
67 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
68  cl::init(true), cl::Hidden,
69  cl::desc("Control jump table emission on Hexagon target"));
70 
71 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
73  cl::desc("Enable Hexagon SDNode scheduling"));
74 
75 static cl::opt<bool> EnableFastMath("ffast-math",
77  cl::desc("Enable Fast Math processing"));
78 
79 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
81  cl::desc("Set minimum jump tables"));
82 
83 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
85  cl::desc("Max #stores to inline memcpy"));
86 
87 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
89  cl::desc("Max #stores to inline memcpy"));
90 
91 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
93  cl::desc("Max #stores to inline memmove"));
94 
95 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
97  cl::desc("Max #stores to inline memmove"));
98 
99 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
101  cl::desc("Max #stores to inline memset"));
102 
103 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
105  cl::desc("Max #stores to inline memset"));
106 
107 static cl::opt<bool> AlignLoads("hexagon-align-loads",
108  cl::Hidden, cl::init(false),
109  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
110 
111 
112 namespace {
113 
114  class HexagonCCState : public CCState {
115  unsigned NumNamedVarArgParams = 0;
116 
117  public:
118  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
120  unsigned NumNamedArgs)
121  : CCState(CC, IsVarArg, MF, locs, C),
122  NumNamedVarArgParams(NumNamedArgs) {}
123  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
124  };
125 
126 } // end anonymous namespace
127 
128 
129 // Implement calling convention for Hexagon.
130 
131 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
132  CCValAssign::LocInfo &LocInfo,
133  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
134  static const MCPhysReg ArgRegs[] = {
135  Hexagon::R0, Hexagon::R1, Hexagon::R2,
136  Hexagon::R3, Hexagon::R4, Hexagon::R5
137  };
138  const unsigned NumArgRegs = array_lengthof(ArgRegs);
139  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
140 
141  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
142  if (RegNum != NumArgRegs && RegNum % 2 == 1)
143  State.AllocateReg(ArgRegs[RegNum]);
144 
145  // Always return false here, as this function only makes sure that the first
146  // unallocated register has an even register number and does not actually
147  // allocate a register for the current argument.
148  return false;
149 }
150 
151 #include "HexagonGenCallingConv.inc"
152 
153 
154 void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
155  if (VT != PromotedLdStVT) {
156  setOperationAction(ISD::LOAD, VT, Promote);
157  AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
158 
159  setOperationAction(ISD::STORE, VT, Promote);
160  AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
161  }
162 }
163 
164 SDValue
166  const {
167  return SDValue();
168 }
169 
170 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
171 /// by "Src" to address "Dst" of size "Size". Alignment information is
172 /// specified by the specific parameter attribute. The copy will be passed as
173 /// a byval function parameter. Sometimes what we are copying is the end of a
174 /// larger object, the part that does not fit in registers.
176  SDValue Chain, ISD::ArgFlagsTy Flags,
177  SelectionDAG &DAG, const SDLoc &dl) {
178  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
179  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
180  /*isVolatile=*/false, /*AlwaysInline=*/false,
181  /*isTailCall=*/false,
183 }
184 
185 bool
187  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
189  LLVMContext &Context) const {
191  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
192 
194  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
195  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
196 }
197 
198 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
199 // passed by value, the function prototype is modified to return void and
200 // the value is stored in memory pointed by a pointer passed by caller.
201 SDValue
203  bool IsVarArg,
205  const SmallVectorImpl<SDValue> &OutVals,
206  const SDLoc &dl, SelectionDAG &DAG) const {
207  // CCValAssign - represent the assignment of the return value to locations.
209 
210  // CCState - Info about the registers and stack slot.
211  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
212  *DAG.getContext());
213 
214  // Analyze return values of ISD::RET
215  if (Subtarget.useHVXOps())
216  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
217  else
218  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
219 
220  SDValue Flag;
221  SmallVector<SDValue, 4> RetOps(1, Chain);
222 
223  // Copy the result values into the output registers.
224  for (unsigned i = 0; i != RVLocs.size(); ++i) {
225  CCValAssign &VA = RVLocs[i];
226 
227  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
228 
229  // Guarantee that all emitted copies are stuck together with flags.
230  Flag = Chain.getValue(1);
231  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
232  }
233 
234  RetOps[0] = Chain; // Update chain.
235 
236  // Add the flag if we have it.
237  if (Flag.getNode())
238  RetOps.push_back(Flag);
239 
240  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
241 }
242 
244  // If either no tail call or told not to tail call at all, don't.
245  auto Attr =
246  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
247  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
248  return false;
249 
250  return true;
251 }
252 
253 /// LowerCallResult - Lower the result values of an ISD::CALL into the
254 /// appropriate copies out of appropriate physical registers. This assumes that
255 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
256 /// being lowered. Returns a SDNode with the same number of values as the
257 /// ISD::CALL.
259  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
260  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
262  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
263  // Assign locations to each value returned by this call.
265 
266  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
267  *DAG.getContext());
268 
269  if (Subtarget.useHVXOps())
270  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
271  else
272  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
273 
274  // Copy all of the result registers out of their specified physreg.
275  for (unsigned i = 0; i != RVLocs.size(); ++i) {
276  SDValue RetVal;
277  if (RVLocs[i].getValVT() == MVT::i1) {
278  // Return values of type MVT::i1 require special handling. The reason
279  // is that MVT::i1 is associated with the PredRegs register class, but
280  // values of that type are still returned in R0. Generate an explicit
281  // copy into a predicate register from R0, and treat the value of the
282  // predicate register as the call result.
283  auto &MRI = DAG.getMachineFunction().getRegInfo();
284  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
285  MVT::i32, Glue);
286  // FR0 = (Value, Chain, Glue)
287  unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
288  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
289  FR0.getValue(0), FR0.getValue(2));
290  // TPR = (Chain, Glue)
291  // Don't glue this CopyFromReg, because it copies from a virtual
292  // register. If it is glued to the call, InstrEmitter will add it
293  // as an implicit def to the call (EmitMachineNode).
294  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
295  Glue = TPR.getValue(1);
296  Chain = TPR.getValue(0);
297  } else {
298  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
299  RVLocs[i].getValVT(), Glue);
300  Glue = RetVal.getValue(2);
301  Chain = RetVal.getValue(1);
302  }
303  InVals.push_back(RetVal.getValue(0));
304  }
305 
306  return Chain;
307 }
308 
309 /// LowerCall - Functions arguments are copied from virtual regs to
310 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
311 SDValue
313  SmallVectorImpl<SDValue> &InVals) const {
314  SelectionDAG &DAG = CLI.DAG;
315  SDLoc &dl = CLI.DL;
317  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
319  SDValue Chain = CLI.Chain;
320  SDValue Callee = CLI.Callee;
321  CallingConv::ID CallConv = CLI.CallConv;
322  bool IsVarArg = CLI.IsVarArg;
323  bool DoesNotReturn = CLI.DoesNotReturn;
324 
325  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
327  MachineFrameInfo &MFI = MF.getFrameInfo();
328  auto PtrVT = getPointerTy(MF.getDataLayout());
329 
330  unsigned NumParams = CLI.CS.getInstruction()
331  ? CLI.CS.getFunctionType()->getNumParams()
332  : 0;
333  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
334  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
335 
336  // Analyze operands of the call, assigning locations to each operand.
338  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
339  NumParams);
340 
341  if (Subtarget.useHVXOps())
342  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
343  else
344  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
345 
346  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
347  if (Attr.getValueAsString() == "true")
348  CLI.IsTailCall = false;
349 
350  if (CLI.IsTailCall) {
351  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
352  CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
353  IsVarArg, IsStructRet, StructAttrFlag, Outs,
354  OutVals, Ins, DAG);
355  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
356  CCValAssign &VA = ArgLocs[i];
357  if (VA.isMemLoc()) {
358  CLI.IsTailCall = false;
359  break;
360  }
361  }
362  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
363  : "Argument must be passed on stack. "
364  "Not eligible for Tail Call\n"));
365  }
366  // Get a count of how many bytes are to be pushed on the stack.
367  unsigned NumBytes = CCInfo.getNextStackOffset();
369  SmallVector<SDValue, 8> MemOpChains;
370 
371  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
372  SDValue StackPtr =
373  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
374 
375  bool NeedsArgAlign = false;
376  unsigned LargestAlignSeen = 0;
377  // Walk the register/memloc assignments, inserting copies/loads.
378  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
379  CCValAssign &VA = ArgLocs[i];
380  SDValue Arg = OutVals[i];
381  ISD::ArgFlagsTy Flags = Outs[i].Flags;
382  // Record if we need > 8 byte alignment on an argument.
383  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
384  NeedsArgAlign |= ArgAlign;
385 
386  // Promote the value if needed.
387  switch (VA.getLocInfo()) {
388  default:
389  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
390  llvm_unreachable("Unknown loc info!");
391  case CCValAssign::Full:
392  break;
393  case CCValAssign::BCvt:
394  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
395  break;
396  case CCValAssign::SExt:
397  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
398  break;
399  case CCValAssign::ZExt:
400  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
401  break;
402  case CCValAssign::AExt:
403  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
404  break;
405  }
406 
407  if (VA.isMemLoc()) {
408  unsigned LocMemOffset = VA.getLocMemOffset();
409  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
410  StackPtr.getValueType());
411  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
412  if (ArgAlign)
413  LargestAlignSeen = std::max(LargestAlignSeen,
414  VA.getLocVT().getStoreSizeInBits() >> 3);
415  if (Flags.isByVal()) {
416  // The argument is a struct passed by value. According to LLVM, "Arg"
417  // is a pointer.
418  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
419  Flags, DAG, dl));
420  } else {
422  DAG.getMachineFunction(), LocMemOffset);
423  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
424  MemOpChains.push_back(S);
425  }
426  continue;
427  }
428 
429  // Arguments that can be passed on register must be kept at RegsToPass
430  // vector.
431  if (VA.isRegLoc())
432  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
433  }
434 
435  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
436  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
437  unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
438  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
439  MFI.ensureMaxAlignment(LargestAlignSeen);
440  }
441  // Transform all store nodes into one single node because all store
442  // nodes are independent of each other.
443  if (!MemOpChains.empty())
444  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
445 
446  SDValue Glue;
447  if (!CLI.IsTailCall) {
448  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
449  Glue = Chain.getValue(1);
450  }
451 
452  // Build a sequence of copy-to-reg nodes chained together with token
453  // chain and flag operands which copy the outgoing args into registers.
454  // The Glue is necessary since all emitted instructions must be
455  // stuck together.
456  if (!CLI.IsTailCall) {
457  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
458  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
459  RegsToPass[i].second, Glue);
460  Glue = Chain.getValue(1);
461  }
462  } else {
463  // For tail calls lower the arguments to the 'real' stack slot.
464  //
465  // Force all the incoming stack arguments to be loaded from the stack
466  // before any new outgoing arguments are stored to the stack, because the
467  // outgoing stack slots may alias the incoming argument stack slots, and
468  // the alias isn't otherwise explicit. This is slightly more conservative
469  // than necessary, because it means that each store effectively depends
470  // on every argument instead of just those arguments it would clobber.
471  //
472  // Do not flag preceding copytoreg stuff together with the following stuff.
473  Glue = SDValue();
474  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
475  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
476  RegsToPass[i].second, Glue);
477  Glue = Chain.getValue(1);
478  }
479  Glue = SDValue();
480  }
481 
482  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
483  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
484 
485  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
486  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
487  // node so that legalize doesn't hack it.
488  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
489  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
490  } else if (ExternalSymbolSDNode *S =
491  dyn_cast<ExternalSymbolSDNode>(Callee)) {
492  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
493  }
494 
495  // Returns a chain & a flag for retval copy to use.
496  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
498  Ops.push_back(Chain);
499  Ops.push_back(Callee);
500 
501  // Add argument registers to the end of the list so that they are
502  // known live into the call.
503  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
504  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
505  RegsToPass[i].second.getValueType()));
506  }
507 
508  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
509  assert(Mask && "Missing call preserved mask for calling convention");
510  Ops.push_back(DAG.getRegisterMask(Mask));
511 
512  if (Glue.getNode())
513  Ops.push_back(Glue);
514 
515  if (CLI.IsTailCall) {
516  MFI.setHasTailCall();
517  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
518  }
519 
520  // Set this here because we need to know this for "hasFP" in frame lowering.
521  // The target-independent code calls getFrameRegister before setting it, and
522  // getFrameRegister uses hasFP to determine whether the function has FP.
523  MFI.setHasCalls(true);
524 
525  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
526  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
527  Glue = Chain.getValue(1);
528 
529  // Create the CALLSEQ_END node.
530  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
531  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
532  Glue = Chain.getValue(1);
533 
534  // Handle result values, copying them out of physregs into vregs that we
535  // return.
536  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
537  InVals, OutVals, Callee);
538 }
539 
540 /// Returns true by value, base pointer and offset pointer and addressing
541 /// mode by reference if this node can be combined with a load / store to
542 /// form a post-indexed load / store.
545  SelectionDAG &DAG) const {
547  if (!LSN)
548  return false;
549  EVT VT = LSN->getMemoryVT();
550  if (!VT.isSimple())
551  return false;
552  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
553  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
554  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
555  VT == MVT::v4i16 || VT == MVT::v8i8 ||
556  Subtarget.isHVXVectorType(VT.getSimpleVT());
557  if (!IsLegalType)
558  return false;
559 
560  if (Op->getOpcode() != ISD::ADD)
561  return false;
562  Base = Op->getOperand(0);
563  Offset = Op->getOperand(1);
564  if (!isa<ConstantSDNode>(Offset.getNode()))
565  return false;
566  AM = ISD::POST_INC;
567 
568  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
569  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
570 }
571 
572 SDValue
575  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
576  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
577  unsigned LR = HRI.getRARegister();
578 
579  if (Op.getOpcode() != ISD::INLINEASM || HMFI.hasClobberLR())
580  return Op;
581 
582  unsigned NumOps = Op.getNumOperands();
583  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
584  --NumOps; // Ignore the flag operand.
585 
586  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
587  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
588  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
589  ++i; // Skip the ID value.
590 
591  switch (InlineAsm::getKind(Flags)) {
592  default:
593  llvm_unreachable("Bad flags!");
595  case InlineAsm::Kind_Imm:
596  case InlineAsm::Kind_Mem:
597  i += NumVals;
598  break;
602  for (; NumVals; --NumVals, ++i) {
603  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
604  if (Reg != LR)
605  continue;
606  HMFI.setHasClobberLR(true);
607  return Op;
608  }
609  break;
610  }
611  }
612  }
613 
614  return Op;
615 }
616 
617 // Need to transform ISD::PREFETCH into something that doesn't inherit
618 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
619 // SDNPMayStore.
621  SelectionDAG &DAG) const {
622  SDValue Chain = Op.getOperand(0);
623  SDValue Addr = Op.getOperand(1);
624  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
625  // if the "reg" is fed by an "add".
626  SDLoc DL(Op);
627  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
628  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
629 }
630 
631 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
632 // is marked as having side-effects, while the register read on Hexagon does
633 // not have any. TableGen refuses to accept the direct pattern from that node
634 // to the A4_tfrcpp.
636  SelectionDAG &DAG) const {
637  SDValue Chain = Op.getOperand(0);
638  SDLoc dl(Op);
640  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
641 }
642 
644  SelectionDAG &DAG) const {
645  SDValue Chain = Op.getOperand(0);
646  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
647  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
648  if (IntNo == Intrinsic::hexagon_prefetch) {
649  SDValue Addr = Op.getOperand(2);
650  SDLoc DL(Op);
651  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
652  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
653  }
654  return SDValue();
655 }
656 
657 SDValue
659  SelectionDAG &DAG) const {
660  SDValue Chain = Op.getOperand(0);
661  SDValue Size = Op.getOperand(1);
662  SDValue Align = Op.getOperand(2);
663  SDLoc dl(Op);
664 
666  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
667 
668  unsigned A = AlignConst->getSExtValue();
669  auto &HFI = *Subtarget.getFrameLowering();
670  // "Zero" means natural stack alignment.
671  if (A == 0)
672  A = HFI.getStackAlignment();
673 
674  LLVM_DEBUG({
675  dbgs () << __func__ << " Align: " << A << " Size: ";
676  Size.getNode()->dump(&DAG);
677  dbgs() << "\n";
678  });
679 
680  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
682  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
683 
684  DAG.ReplaceAllUsesOfValueWith(Op, AA);
685  return AA;
686 }
687 
689  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
690  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
691  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
693  MachineFrameInfo &MFI = MF.getFrameInfo();
695 
696  // Assign locations to all of the incoming arguments.
698  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
700 
701  if (Subtarget.useHVXOps())
702  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
703  else
704  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
705 
706  // For LLVM, in the case when returning a struct by value (>8byte),
707  // the first argument is a pointer that points to the location on caller's
708  // stack where the return value will be stored. For Hexagon, the location on
709  // caller's stack is passed only when the struct size is smaller than (and
710  // equal to) 8 bytes. If not, no address will be passed into callee and
711  // callee return the result direclty through R0/R1.
712 
713  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
714 
715  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
716  CCValAssign &VA = ArgLocs[i];
717  ISD::ArgFlagsTy Flags = Ins[i].Flags;
718  bool ByVal = Flags.isByVal();
719 
720  // Arguments passed in registers:
721  // 1. 32- and 64-bit values and HVX vectors are passed directly,
722  // 2. Large structs are passed via an address, and the address is
723  // passed in a register.
724  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
725  llvm_unreachable("ByValSize must be bigger than 8 bytes");
726 
727  bool InReg = VA.isRegLoc() &&
728  (!ByVal || (ByVal && Flags.getByValSize() > 8));
729 
730  if (InReg) {
731  MVT RegVT = VA.getLocVT();
732  if (VA.getLocInfo() == CCValAssign::BCvt)
733  RegVT = VA.getValVT();
734 
735  const TargetRegisterClass *RC = getRegClassFor(RegVT);
736  unsigned VReg = MRI.createVirtualRegister(RC);
737  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
738 
739  // Treat values of type MVT::i1 specially: they are passed in
740  // registers of type i32, but they need to remain as values of
741  // type i1 for consistency of the argument lowering.
742  if (VA.getValVT() == MVT::i1) {
743  assert(RegVT.getSizeInBits() <= 32);
744  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
745  Copy, DAG.getConstant(1, dl, RegVT));
746  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
747  ISD::SETNE);
748  } else {
749 #ifndef NDEBUG
750  unsigned RegSize = RegVT.getSizeInBits();
751  assert(RegSize == 32 || RegSize == 64 ||
752  Subtarget.isHVXVectorType(RegVT));
753 #endif
754  }
755  InVals.push_back(Copy);
756  MRI.addLiveIn(VA.getLocReg(), VReg);
757  } else {
758  assert(VA.isMemLoc() && "Argument should be passed in memory");
759 
760  // If it's a byval parameter, then we need to compute the
761  // "real" size, not the size of the pointer.
762  unsigned ObjSize = Flags.isByVal()
763  ? Flags.getByValSize()
764  : VA.getLocVT().getStoreSizeInBits() / 8;
765 
766  // Create the frame index object for this incoming parameter.
768  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
769  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
770 
771  if (Flags.isByVal()) {
772  // If it's a pass-by-value aggregate, then do not dereference the stack
773  // location. Instead, we should generate a reference to the stack
774  // location.
775  InVals.push_back(FIN);
776  } else {
777  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
779  InVals.push_back(L);
780  }
781  }
782  }
783 
784 
785  if (IsVarArg) {
786  // This will point to the next argument passed via stack.
787  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
788  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
789  HMFI.setVarArgsFrameIndex(FI);
790  }
791 
792  return Chain;
793 }
794 
795 SDValue
797  // VASTART stores the address of the VarArgsFrameIndex slot into the
798  // memory location argument.
802  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
803  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
804  MachinePointerInfo(SV));
805 }
806 
808  const SDLoc &dl(Op);
809  SDValue LHS = Op.getOperand(0);
810  SDValue RHS = Op.getOperand(1);
811  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
812  MVT ResTy = ty(Op);
813  MVT OpTy = ty(LHS);
814 
815  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
816  MVT ElemTy = OpTy.getVectorElementType();
817  assert(ElemTy.isScalarInteger());
819  OpTy.getVectorNumElements());
820  return DAG.getSetCC(dl, ResTy,
821  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
822  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
823  }
824 
825  // Treat all other vector types as legal.
826  if (ResTy.isVector())
827  return Op;
828 
829  // Comparisons of short integers should use sign-extend, not zero-extend,
830  // since we can represent small negative values in the compare instructions.
831  // The LLVM default is to use zero-extend arbitrarily in these cases.
832  auto isSExtFree = [this](SDValue N) {
833  switch (N.getOpcode()) {
834  case ISD::TRUNCATE: {
835  // A sign-extend of a truncate of a sign-extend is free.
836  SDValue Op = N.getOperand(0);
837  if (Op.getOpcode() != ISD::AssertSext)
838  return false;
839  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
840  unsigned ThisBW = ty(N).getSizeInBits();
841  unsigned OrigBW = OrigTy.getSizeInBits();
842  // The type that was sign-extended to get the AssertSext must be
843  // narrower than the type of N (so that N has still the same value
844  // as the original).
845  return ThisBW >= OrigBW;
846  }
847  case ISD::LOAD:
848  // We have sign-extended loads.
849  return true;
850  }
851  return false;
852  };
853 
854  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
856  bool IsNegative = C && C->getAPIntValue().isNegative();
857  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
858  return DAG.getSetCC(dl, ResTy,
859  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
860  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
861  }
862 
863  return SDValue();
864 }
865 
866 SDValue
868  SDValue PredOp = Op.getOperand(0);
869  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
870  EVT OpVT = Op1.getValueType();
871  SDLoc DL(Op);
872 
873  if (OpVT == MVT::v2i16) {
874  SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
875  SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
876  SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
877  SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
878  return TR;
879  }
880 
881  return SDValue();
882 }
883 
884 static Constant *convert_i1_to_i8(const Constant *ConstVal) {
886  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
887  if (!CV)
888  return nullptr;
889 
890  LLVMContext &Ctx = ConstVal->getContext();
891  IRBuilder<> IRB(Ctx);
892  unsigned NumVectorElements = CV->getNumOperands();
893  assert(isPowerOf2_32(NumVectorElements) &&
894  "conversion only supported for pow2 VectorSize!");
895 
896  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
897  uint8_t x = 0;
898  for (unsigned j = 0; j < 8; ++j) {
899  uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
900  x |= y << (7 - j);
901  }
902  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
903  NewConst.push_back(IRB.getInt8(x));
904  }
905  return ConstantVector::get(NewConst);
906 }
907 
908 SDValue
910  EVT ValTy = Op.getValueType();
911  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
912  Constant *CVal = nullptr;
913  bool isVTi1Type = false;
914  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
915  Type *CValTy = ConstVal->getType();
916  if (CValTy->isVectorTy() &&
917  CValTy->getVectorElementType()->isIntegerTy(1)) {
918  CVal = convert_i1_to_i8(ConstVal);
919  isVTi1Type = (CVal != nullptr);
920  }
921  }
922  unsigned Align = CPN->getAlignment();
923  bool IsPositionIndependent = isPositionIndependent();
924  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
925 
926  unsigned Offset = 0;
927  SDValue T;
928  if (CPN->isMachineConstantPoolEntry())
929  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
930  TF);
931  else if (isVTi1Type)
932  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
933  else
934  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);
935 
936  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
937  "Inconsistent target flag encountered");
938 
939  if (IsPositionIndependent)
940  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
941  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
942 }
943 
944 SDValue
946  EVT VT = Op.getValueType();
947  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
948  if (isPositionIndependent()) {
950  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
951  }
952 
953  SDValue T = DAG.getTargetJumpTable(Idx, VT);
954  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
955 }
956 
957 SDValue
959  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
961  MachineFrameInfo &MFI = MF.getFrameInfo();
962  MFI.setReturnAddressIsTaken(true);
963 
964  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
965  return SDValue();
966 
967  EVT VT = Op.getValueType();
968  SDLoc dl(Op);
969  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
970  if (Depth) {
971  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
972  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
973  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
974  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
976  }
977 
978  // Return LR, which contains the return address. Mark it an implicit live-in.
979  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
980  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
981 }
982 
983 SDValue
985  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
987  MFI.setFrameAddressIsTaken(true);
988 
989  EVT VT = Op.getValueType();
990  SDLoc dl(Op);
991  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
992  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
993  HRI.getFrameRegister(), VT);
994  while (Depth--)
995  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
997  return FrameAddr;
998 }
999 
1000 SDValue
1002  SDLoc dl(Op);
1003  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1004 }
1005 
1006 SDValue
1008  SDLoc dl(Op);
1009  auto *GAN = cast<GlobalAddressSDNode>(Op);
1010  auto PtrVT = getPointerTy(DAG.getDataLayout());
1011  auto *GV = GAN->getGlobal();
1012  int64_t Offset = GAN->getOffset();
1013 
1014  auto &HLOF = *HTM.getObjFileLowering();
1015  Reloc::Model RM = HTM.getRelocationModel();
1016 
1017  if (RM == Reloc::Static) {
1018  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1019  const GlobalObject *GO = GV->getBaseObject();
1020  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1021  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1022  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1023  }
1024 
1025  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1026  if (UsePCRel) {
1027  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1029  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1030  }
1031 
1032  // Use GOT index.
1033  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1034  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1035  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1036  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1037 }
1038 
1039 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1040 SDValue
1042  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1043  SDLoc dl(Op);
1044  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1045 
1046  Reloc::Model RM = HTM.getRelocationModel();
1047  if (RM == Reloc::Static) {
1048  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1049  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1050  }
1051 
1052  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1053  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1054 }
1055 
1056 SDValue
1058  const {
1059  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1062  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1063 }
1064 
1065 SDValue
1067  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1068  unsigned char OperandFlags) const {
1069  MachineFunction &MF = DAG.getMachineFunction();
1070  MachineFrameInfo &MFI = MF.getFrameInfo();
1071  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1072  SDLoc dl(GA);
1073  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1074  GA->getValueType(0),
1075  GA->getOffset(),
1076  OperandFlags);
1077  // Create Operands for the call.The Operands should have the following:
1078  // 1. Chain SDValue
1079  // 2. Callee which in this case is the Global address value.
1080  // 3. Registers live into the call.In this case its R0, as we
1081  // have just one argument to be passed.
1082  // 4. Glue.
1083  // Note: The order is important.
1084 
1085  const auto &HRI = *Subtarget.getRegisterInfo();
1086  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1087  assert(Mask && "Missing call preserved mask for calling convention");
1088  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1089  DAG.getRegisterMask(Mask), Glue };
1090  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1091 
1092  // Inform MFI that function has calls.
1093  MFI.setAdjustsStack(true);
1094 
1095  Glue = Chain.getValue(1);
1096  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1097 }
1098 
1099 //
1100 // Lower using the intial executable model for TLS addresses
1101 //
1102 SDValue
1104  SelectionDAG &DAG) const {
1105  SDLoc dl(GA);
1106  int64_t Offset = GA->getOffset();
1107  auto PtrVT = getPointerTy(DAG.getDataLayout());
1108 
1109  // Get the thread pointer.
1110  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1111 
1112  bool IsPositionIndependent = isPositionIndependent();
1113  unsigned char TF =
1114  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1115 
1116  // First generate the TLS symbol address
1117  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1118  Offset, TF);
1119 
1120  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1121 
1122  if (IsPositionIndependent) {
1123  // Generate the GOT pointer in case of position independent code
1124  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1125 
1126  // Add the TLS Symbol address to GOT pointer.This gives
1127  // GOT relative relocation for the symbol.
1128  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1129  }
1130 
1131  // Load the offset value for TLS symbol.This offset is relative to
1132  // thread pointer.
1133  SDValue LoadOffset =
1134  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1135 
1136  // Address of the thread local variable is the add of thread
1137  // pointer and the offset of the variable.
1138  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1139 }
1140 
1141 //
1142 // Lower using the local executable model for TLS addresses
1143 //
1144 SDValue
1146  SelectionDAG &DAG) const {
1147  SDLoc dl(GA);
1148  int64_t Offset = GA->getOffset();
1149  auto PtrVT = getPointerTy(DAG.getDataLayout());
1150 
1151  // Get the thread pointer.
1152  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1153  // Generate the TLS symbol address
1154  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1156  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1157 
1158  // Address of the thread local variable is the add of thread
1159  // pointer and the offset of the variable.
1160  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1161 }
1162 
1163 //
1164 // Lower using the general dynamic model for TLS addresses
1165 //
1166 SDValue
1168  SelectionDAG &DAG) const {
1169  SDLoc dl(GA);
1170  int64_t Offset = GA->getOffset();
1171  auto PtrVT = getPointerTy(DAG.getDataLayout());
1172 
1173  // First generate the TLS symbol address
1174  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1176 
1177  // Then, generate the GOT pointer
1178  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1179 
1180  // Add the TLS symbol and the GOT pointer
1181  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1182  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1183 
1184  // Copy over the argument to R0
1185  SDValue InFlag;
1186  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1187  InFlag = Chain.getValue(1);
1188 
1189  unsigned Flags =
1190  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1193 
1194  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1195  Hexagon::R0, Flags);
1196 }
1197 
1198 //
1199 // Lower TLS addresses.
1200 //
1201 // For now for dynamic models, we only support the general dynamic model.
1202 //
1203 SDValue
1205  SelectionDAG &DAG) const {
1206  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1207 
1208  switch (HTM.getTLSModel(GA->getGlobal())) {
1211  return LowerToTLSGeneralDynamicModel(GA, DAG);
1212  case TLSModel::InitialExec:
1213  return LowerToTLSInitialExecModel(GA, DAG);
1214  case TLSModel::LocalExec:
1215  return LowerToTLSLocalExecModel(GA, DAG);
1216  }
1217  llvm_unreachable("Bogus TLS model");
1218 }
1219 
1220 //===----------------------------------------------------------------------===//
1221 // TargetLowering Implementation
1222 //===----------------------------------------------------------------------===//
1223 
1225  const HexagonSubtarget &ST)
1226  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1227  Subtarget(ST) {
1228  bool IsV4 = !Subtarget.hasV5Ops();
1229  auto &HRI = *Subtarget.getRegisterInfo();
1230 
1234  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1237 
1240 
1243  else
1245 
1246  // Limits for inline expansion of memcpy/memmove
1253 
1254  //
1255  // Set up register classes.
1256  //
1257 
1258  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1259  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1260  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1261  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1262  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1263  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1264  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1265  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1266  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1267  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1268  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1269 
1270  if (Subtarget.hasV5Ops()) {
1271  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1272  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1273  }
1274 
1275  //
1276  // Handling of scalar operations.
1277  //
1278  // All operations default to "legal", except:
1279  // - indexed loads and stores (pre-/post-incremented),
1280  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1281  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1282  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1283  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1284  // which default to "expand" for at least one type.
1285 
1286  // Misc operations.
1287  setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1288  setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1289 
1302 
1303  // Custom legalize GlobalAddress nodes into CONST32.
1307 
1308  // Hexagon needs to optimize cases with negative constants.
1313 
1314  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1319 
1323 
1324  if (EmitJumpTables)
1326  else
1329 
1332 
1333  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1334  // but they only operate on i64.
1335  for (MVT VT : MVT::integer_valuetypes()) {
1342  }
1345 
1350 
1351  // In V5, popcount can count # of 1s in i64 but returns i32.
1352  // On V4 it will be expanded (set later).
1357 
1362 
1363  for (unsigned IntExpOp :
1368  for (MVT VT : MVT::integer_valuetypes())
1369  setOperationAction(IntExpOp, VT, Expand);
1370  }
1371 
1372  for (unsigned FPExpOp :
1375  for (MVT VT : MVT::fp_valuetypes())
1376  setOperationAction(FPExpOp, VT, Expand);
1377  }
1378 
1379  // No extending loads from i32.
1380  for (MVT VT : MVT::integer_valuetypes()) {
1384  }
1385  // Turn FP truncstore into trunc + store.
1387  // Turn FP extload into load/fpextend.
1388  for (MVT VT : MVT::fp_valuetypes())
1390 
1391  // Expand BR_CC and SELECT_CC for all integer and fp types.
1392  for (MVT VT : MVT::integer_valuetypes()) {
1395  }
1396  for (MVT VT : MVT::fp_valuetypes()) {
1399  }
1401 
1402  //
1403  // Handling of vector operations.
1404  //
1405 
1406  promoteLdStType(MVT::v4i8, MVT::i32);
1407  promoteLdStType(MVT::v2i16, MVT::i32);
1408  promoteLdStType(MVT::v8i8, MVT::i64);
1409  promoteLdStType(MVT::v4i16, MVT::i64);
1410  promoteLdStType(MVT::v2i32, MVT::i64);
1411 
1412  // Set the action for vector operations to "expand", then override it with
1413  // either "custom" or "legal" for specific cases.
1414  static const unsigned VectExpOps[] = {
1415  // Integer arithmetic:
1419  // Logical/bit:
1422  // Floating point arithmetic/math functions:
1429  // Misc:
1431  // Vector:
1436  };
1437 
1438  for (MVT VT : MVT::vector_valuetypes()) {
1439  for (unsigned VectExpOp : VectExpOps)
1440  setOperationAction(VectExpOp, VT, Expand);
1441 
1442  // Expand all extending loads and truncating stores:
1443  for (MVT TargetVT : MVT::vector_valuetypes()) {
1444  if (TargetVT == VT)
1445  continue;
1446  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1447  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1448  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1449  setTruncStoreAction(VT, TargetVT, Expand);
1450  }
1451 
1452  // Normalize all inputs to SELECT to be vectors of i32.
1453  if (VT.getVectorElementType() != MVT::i32) {
1454  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1456  AddPromotedToType(ISD::SELECT, VT, VT32);
1457  }
1461  }
1462 
1463  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1464  // are legal.
1471 
1472  // Types natively supported:
1473  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1481 
1482  setOperationAction(ISD::ADD, NativeVT, Legal);
1483  setOperationAction(ISD::SUB, NativeVT, Legal);
1484  setOperationAction(ISD::MUL, NativeVT, Legal);
1485  setOperationAction(ISD::AND, NativeVT, Legal);
1486  setOperationAction(ISD::OR, NativeVT, Legal);
1487  setOperationAction(ISD::XOR, NativeVT, Legal);
1488  }
1489 
1490  // Custom lower unaligned loads.
1491  for (MVT VecVT : {MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1494  }
1495 
1496  for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v2i32, MVT::v4i16, MVT::v2i32}) {
1501  }
1502 
1503  // Custom-lower bitcasts from i8 to v8i1.
1507  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1508  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1509  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1510 
1511  // Subtarget-specific operation actions.
1512  //
1513  if (Subtarget.hasV60Ops()) {
1516  }
1517  if (Subtarget.hasV5Ops()) {
1522 
1525 
1538  } else { // V4
1548 
1553 
1554  // Expand these operations for both f32 and f64:
1555  for (unsigned FPExpOpV4 :
1557  setOperationAction(FPExpOpV4, MVT::f32, Expand);
1558  setOperationAction(FPExpOpV4, MVT::f64, Expand);
1559  }
1560 
1561  for (ISD::CondCode FPExpCCV4 :
1563  ISD::SETUO, ISD::SETO}) {
1564  setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
1565  setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
1566  }
1567  }
1568 
1569  // Handling of indexed loads/stores: default is "expand".
1570  //
1575  }
1576 
1577  if (Subtarget.useHVXOps())
1578  initializeHVXLowering();
1579 
1581 
1582  //
1583  // Library calls for unsupported operations
1584  //
1585  bool FastMath = EnableFastMath;
1586 
1587  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1588  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1589  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1590  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1591  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1592  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1593  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1594  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1595 
1596  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1597  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1598  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1599  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1600  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1601  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1602 
1603  if (IsV4) {
1604  // Handle single-precision floating point operations on V4.
1605  if (FastMath) {
1606  setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
1607  setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
1608  setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
1609  setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
1610  setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
1611  // Double-precision compares.
1612  setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
1613  setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
1614  } else {
1615  setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1616  setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1617  setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1618  setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1619  setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1620  // Double-precision compares.
1621  setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1622  setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1623  }
1624  }
1625 
1626  // This is the only fast library function for sqrtd.
1627  if (FastMath)
1628  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1629 
1630  // Prefix is: nothing for "slow-math",
1631  // "fast2_" for V4 fast-math and V5+ fast-math double-precision
1632  // (actually, keep fast-math and fast-math2 separate for now)
1633  if (FastMath) {
1634  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1635  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1636  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1637  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1638  // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
1639  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1640  } else {
1641  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1642  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1643  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1644  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1645  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1646  }
1647 
1648  if (Subtarget.hasV5Ops()) {
1649  if (FastMath)
1650  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1651  else
1652  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1653  } else {
1654  // V4
1655  setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1656  setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1657  setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1658  setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1659  setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1660  setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1661  setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1662  setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1663  setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1664  setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1665  setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1666  setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1667  setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1668  setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1669  setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1670  setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1671  setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1672  setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1673  setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1674  setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1675  setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1676  setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1677  setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1678  setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1679  setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1680  setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1681  setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1682  setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1683  setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1684  setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1685  }
1686 
1687  // These cause problems when the shift amount is non-constant.
1688  setLibcallName(RTLIB::SHL_I128, nullptr);
1689  setLibcallName(RTLIB::SRL_I128, nullptr);
1690  setLibcallName(RTLIB::SRA_I128, nullptr);
1691 }
1692 
1693 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1694  switch ((HexagonISD::NodeType)Opcode) {
1695  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1696  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1697  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1698  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1699  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1700  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1701  case HexagonISD::CALL: return "HexagonISD::CALL";
1702  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1703  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1704  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1705  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1706  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1707  case HexagonISD::CP: return "HexagonISD::CP";
1708  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1709  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1710  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1711  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1712  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1713  case HexagonISD::JT: return "HexagonISD::JT";
1714  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1715  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1716  case HexagonISD::VASL: return "HexagonISD::VASL";
1717  case HexagonISD::VASR: return "HexagonISD::VASR";
1718  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1719  case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
1720  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1721  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1722  case HexagonISD::VROR: return "HexagonISD::VROR";
1723  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1724  case HexagonISD::VZERO: return "HexagonISD::VZERO";
1725  case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW";
1726  case HexagonISD::D2P: return "HexagonISD::D2P";
1727  case HexagonISD::P2D: return "HexagonISD::P2D";
1728  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1729  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1730  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1731  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1732  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1733  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1734  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1735  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1736  case HexagonISD::OP_END: break;
1737  }
1738  return nullptr;
1739 }
1740 
1741 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1742 // intrinsic.
1743 static bool isBrevLdIntrinsic(const Value *Inst) {
1744  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1745  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1746  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1747  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1748  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1749  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1750  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1751 }
1752 
1753 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1754 // instruction. So far we only handle bitcast, extract value and bit reverse
1755 // load intrinsic instructions. Should we handle CGEP ?
1757  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1758  Operator::getOpcode(V) == Instruction::BitCast)
1759  V = cast<Operator>(V)->getOperand(0);
1760  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1761  V = cast<Instruction>(V)->getOperand(0);
1762  return V;
1763 }
1764 
1765 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1766 // a back edge. If the back edge comes from the intrinsic itself, the incoming
1767 // edge is returned.
1768 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1769  const BasicBlock *Parent = PN->getParent();
1770  int Idx = -1;
1771  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1772  BasicBlock *Blk = PN->getIncomingBlock(i);
1773  // Determine if the back edge is originated from intrinsic.
1774  if (Blk == Parent) {
1775  Value *BackEdgeVal = PN->getIncomingValue(i);
1776  Value *BaseVal;
1777  // Loop over till we return the same Value or we hit the IntrBaseVal.
1778  do {
1779  BaseVal = BackEdgeVal;
1780  BackEdgeVal = getBrevLdObject(BackEdgeVal);
1781  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1782  // If the getBrevLdObject returns IntrBaseVal, we should return the
1783  // incoming edge.
1784  if (IntrBaseVal == BackEdgeVal)
1785  continue;
1786  Idx = i;
1787  break;
1788  } else // Set the node to incoming edge.
1789  Idx = i;
1790  }
1791  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
1792  return PN->getIncomingValue(Idx);
1793 }
1794 
1795 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
1796 // pointer points to, for the bit-reverse load intrinsic. Setting this to
1797 // memoperand might help alias analysis to figure out the dependencies.
1799  Value *IntrBaseVal = V;
1800  Value *BaseVal;
1801  // Loop over till we return the same Value, implies we either figure out
1802  // the object or we hit a PHI
1803  do {
1804  BaseVal = V;
1805  V = getBrevLdObject(V);
1806  } while (BaseVal != V);
1807 
1808  // Identify the object from PHINode.
1809  if (const PHINode *PN = dyn_cast<PHINode>(V))
1810  return returnEdge(PN, IntrBaseVal);
1811  // For non PHI nodes, the object is the last value returned by getBrevLdObject
1812  else
1813  return V;
1814 }
1815 
1816 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1817 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1818 /// true and store the intrinsic information into the IntrinsicInfo that was
1819 /// passed to the function.
1821  const CallInst &I,
1822  MachineFunction &MF,
1823  unsigned Intrinsic) const {
1824  switch (Intrinsic) {
1825  case Intrinsic::hexagon_L2_loadrd_pbr:
1826  case Intrinsic::hexagon_L2_loadri_pbr:
1827  case Intrinsic::hexagon_L2_loadrh_pbr:
1828  case Intrinsic::hexagon_L2_loadruh_pbr:
1829  case Intrinsic::hexagon_L2_loadrb_pbr:
1830  case Intrinsic::hexagon_L2_loadrub_pbr: {
1831  Info.opc = ISD::INTRINSIC_W_CHAIN;
1832  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1833  auto &Cont = I.getCalledFunction()->getParent()->getContext();
1834  // The intrinsic function call is of the form { ElTy, i8* }
1835  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
1836  // should be derived from ElTy.
1837  PointerType *PtrTy = I.getCalledFunction()
1838  ->getReturnType()
1839  ->getContainedType(0)
1840  ->getPointerTo();
1841  Info.memVT = MVT::getVT(PtrTy->getElementType());
1842  llvm::Value *BasePtrVal = I.getOperand(0);
1843  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
1844  // The offset value comes through Modifier register. For now, assume the
1845  // offset is 0.
1846  Info.offset = 0;
1847  Info.align = DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont));
1849  return true;
1850  }
1851  case Intrinsic::hexagon_V6_vgathermw:
1852  case Intrinsic::hexagon_V6_vgathermw_128B:
1853  case Intrinsic::hexagon_V6_vgathermh:
1854  case Intrinsic::hexagon_V6_vgathermh_128B:
1855  case Intrinsic::hexagon_V6_vgathermhw:
1856  case Intrinsic::hexagon_V6_vgathermhw_128B:
1857  case Intrinsic::hexagon_V6_vgathermwq:
1858  case Intrinsic::hexagon_V6_vgathermwq_128B:
1859  case Intrinsic::hexagon_V6_vgathermhq:
1860  case Intrinsic::hexagon_V6_vgathermhq_128B:
1861  case Intrinsic::hexagon_V6_vgathermhwq:
1862  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
1863  const Module &M = *I.getParent()->getParent()->getParent();
1864  Info.opc = ISD::INTRINSIC_W_CHAIN;
1865  Type *VecTy = I.getArgOperand(1)->getType();
1866  Info.memVT = MVT::getVT(VecTy);
1867  Info.ptrVal = I.getArgOperand(0);
1868  Info.offset = 0;
1869  Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
1873  return true;
1874  }
1875  default:
1876  break;
1877  }
1878  return false;
1879 }
1880 
1882  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1883 }
1884 
1886  if (!VT1.isSimple() || !VT2.isSimple())
1887  return false;
1888  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1889 }
1890 
1892  return isOperationLegalOrCustom(ISD::FMA, VT);
1893 }
1894 
1895 // Should we expand the build vector with shuffles?
1897  unsigned DefinedValues) const {
1898  return false;
1899 }
1900 
1902  EVT VT) const {
1903  return true;
1904 }
1905 
1908  if (VT.getVectorNumElements() == 1)
1910 
1911  // Always widen vectors of i1.
1912  MVT ElemTy = VT.getSimpleVT().getVectorElementType();
1913  if (ElemTy == MVT::i1)
1915 
1916  if (Subtarget.useHVXOps()) {
1917  // If the size of VT is at least half of the vector length,
1918  // widen the vector. Note: the threshold was not selected in
1919  // any scientific way.
1920  ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
1921  if (llvm::find(Tys, ElemTy) != Tys.end()) {
1922  unsigned HwWidth = 8*Subtarget.getVectorLength();
1923  unsigned VecWidth = VT.getSizeInBits();
1924  if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
1926  }
1927  }
1929 }
1930 
1931 std::pair<SDValue, int>
1932 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
1933  if (Addr.getOpcode() == ISD::ADD) {
1934  SDValue Op1 = Addr.getOperand(1);
1935  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
1936  return { Addr.getOperand(0), CN->getSExtValue() };
1937  }
1938  return { Addr, 0 };
1939 }
1940 
1941 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
1942 // to select data from, V3 is the permutation.
1943 SDValue
1945  const {
1946  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
1947  ArrayRef<int> AM = SVN->getMask();
1948  assert(AM.size() <= 8 && "Unexpected shuffle mask");
1949  unsigned VecLen = AM.size();
1950 
1951  MVT VecTy = ty(Op);
1952  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
1953  "HVX shuffles should be legal");
1954  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
1955 
1956  SDValue Op0 = Op.getOperand(0);
1957  SDValue Op1 = Op.getOperand(1);
1958  const SDLoc &dl(Op);
1959 
1960  // If the inputs are not the same as the output, bail. This is not an
1961  // error situation, but complicates the handling and the default expansion
1962  // (into BUILD_VECTOR) should be adequate.
1963  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
1964  return SDValue();
1965 
1966  // Normalize the mask so that the first non-negative index comes from
1967  // the first operand.
1968  SmallVector<int,8> Mask(AM.begin(), AM.end());
1969  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
1970  if (F == AM.size())
1971  return DAG.getUNDEF(VecTy);
1972  if (AM[F] >= int(VecLen)) {
1974  std::swap(Op0, Op1);
1975  }
1976 
1977  // Express the shuffle mask in terms of bytes.
1978  SmallVector<int,8> ByteMask;
1979  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
1980  for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
1981  int M = Mask[i];
1982  if (M < 0) {
1983  for (unsigned j = 0; j != ElemBytes; ++j)
1984  ByteMask.push_back(-1);
1985  } else {
1986  for (unsigned j = 0; j != ElemBytes; ++j)
1987  ByteMask.push_back(M*ElemBytes + j);
1988  }
1989  }
1990  assert(ByteMask.size() <= 8);
1991 
1992  // All non-undef (non-negative) indexes are well within [0..127], so they
1993  // fit in a single byte. Build two 64-bit words:
1994  // - MaskIdx where each byte is the corresponding index (for non-negative
1995  // indexes), and 0xFF for negative indexes, and
1996  // - MaskUnd that has 0xFF for each negative index.
1997  uint64_t MaskIdx = 0;
1998  uint64_t MaskUnd = 0;
1999  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
2000  unsigned S = 8*i;
2001  uint64_t M = ByteMask[i] & 0xFF;
2002  if (M == 0xFF)
2003  MaskUnd |= M << S;
2004  MaskIdx |= M << S;
2005  }
2006 
2007  if (ByteMask.size() == 4) {
2008  // Identity.
2009  if (MaskIdx == (0x03020100 | MaskUnd))
2010  return Op0;
2011  // Byte swap.
2012  if (MaskIdx == (0x00010203 | MaskUnd)) {
2013  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2014  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2015  return DAG.getBitcast(VecTy, T1);
2016  }
2017 
2018  // Byte packs.
2019  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
2020  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
2021  if (MaskIdx == (0x06040200 | MaskUnd))
2022  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2023  if (MaskIdx == (0x07050301 | MaskUnd))
2024  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2025 
2026  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
2027  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
2028  if (MaskIdx == (0x02000604 | MaskUnd))
2029  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2030  if (MaskIdx == (0x03010705 | MaskUnd))
2031  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2032  }
2033 
2034  if (ByteMask.size() == 8) {
2035  // Identity.
2036  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2037  return Op0;
2038  // Byte swap.
2039  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2040  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2041  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2042  return DAG.getBitcast(VecTy, T1);
2043  }
2044 
2045  // Halfword picks.
2046  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2047  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2048  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2049  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2050  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2051  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2052  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2053  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2054  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2055  VectorPair P = opSplit(Op0, dl, DAG);
2056  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2057  }
2058 
2059  // Byte packs.
2060  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2061  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2062  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2063  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2064  }
2065 
2066  return SDValue();
2067 }
2068 
2069 // Create a Hexagon-specific node for shifting a vector by an integer.
2070 SDValue
2071 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2072  const {
2073  if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
2074  if (SDValue S = BVN->getSplatValue()) {
2075  unsigned NewOpc;
2076  switch (Op.getOpcode()) {
2077  case ISD::SHL:
2078  NewOpc = HexagonISD::VASL;
2079  break;
2080  case ISD::SRA:
2081  NewOpc = HexagonISD::VASR;
2082  break;
2083  case ISD::SRL:
2084  NewOpc = HexagonISD::VLSR;
2085  break;
2086  default:
2087  llvm_unreachable("Unexpected shift opcode");
2088  }
2089  return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
2090  }
2091  }
2092 
2093  return SDValue();
2094 }
2095 
2096 SDValue
2098  return getVectorShiftByInt(Op, DAG);
2099 }
2100 
2101 SDValue
2103  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2104  return Op;
2105  return SDValue();
2106 }
2107 
2108 SDValue
2110  MVT ResTy = ty(Op);
2111  SDValue InpV = Op.getOperand(0);
2112  MVT InpTy = ty(InpV);
2113  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2114  const SDLoc &dl(Op);
2115 
2116  // Handle conversion from i8 to v8i1.
2117  if (ResTy == MVT::v8i1) {
2118  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2119  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2120  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2121  }
2122 
2123  return SDValue();
2124 }
2125 
2126 bool
2127 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2128  MVT VecTy, SelectionDAG &DAG,
2129  MutableArrayRef<ConstantInt*> Consts) const {
2130  MVT ElemTy = VecTy.getVectorElementType();
2131  unsigned ElemWidth = ElemTy.getSizeInBits();
2132  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2133  bool AllConst = true;
2134 
2135  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2136  SDValue V = Values[i];
2137  if (V.isUndef()) {
2138  Consts[i] = ConstantInt::get(IntTy, 0);
2139  continue;
2140  }
2141  // Make sure to always cast to IntTy.
2142  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2143  const ConstantInt *CI = CN->getConstantIntValue();
2144  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2145  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2146  const ConstantFP *CF = CN->getConstantFPValue();
2147  APInt A = CF->getValueAPF().bitcastToAPInt();
2148  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2149  } else {
2150  AllConst = false;
2151  }
2152  }
2153  return AllConst;
2154 }
2155 
2156 SDValue
2157 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2158  MVT VecTy, SelectionDAG &DAG) const {
2159  MVT ElemTy = VecTy.getVectorElementType();
2160  assert(VecTy.getVectorNumElements() == Elem.size());
2161 
2162  SmallVector<ConstantInt*,4> Consts(Elem.size());
2163  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2164 
2165  unsigned First, Num = Elem.size();
2166  for (First = 0; First != Num; ++First)
2167  if (!isUndef(Elem[First]))
2168  break;
2169  if (First == Num)
2170  return DAG.getUNDEF(VecTy);
2171 
2172  if (AllConst &&
2173  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2174  return getZero(dl, VecTy, DAG);
2175 
2176  if (ElemTy == MVT::i16) {
2177  assert(Elem.size() == 2);
2178  if (AllConst) {
2179  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2180  Consts[1]->getZExtValue() << 16;
2181  return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2182  }
2183  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2184  {Elem[1], Elem[0]}, DAG);
2185  return DAG.getBitcast(MVT::v2i16, N);
2186  }
2187 
2188  if (ElemTy == MVT::i8) {
2189  // First try generating a constant.
2190  if (AllConst) {
2191  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2192  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2193  (Consts[1]->getZExtValue() & 0xFF) << 16 |
2194  Consts[2]->getZExtValue() << 24;
2195  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2196  }
2197 
2198  // Then try splat.
2199  bool IsSplat = true;
2200  for (unsigned i = 0; i != Num; ++i) {
2201  if (i == First)
2202  continue;
2203  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2204  continue;
2205  IsSplat = false;
2206  break;
2207  }
2208  if (IsSplat) {
2209  // Legalize the operand to VSPLAT.
2210  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2211  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2212  }
2213 
2214  // Generate
2215  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2216  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2217  assert(Elem.size() == 4);
2218  SDValue Vs[4];
2219  for (unsigned i = 0; i != 4; ++i) {
2220  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2221  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2222  }
2223  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2224  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2225  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2226  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2227  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2228 
2229  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2230  return DAG.getBitcast(MVT::v4i8, R);
2231  }
2232 
2233 #ifndef NDEBUG
2234  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2235 #endif
2236  llvm_unreachable("Unexpected vector element type");
2237 }
2238 
2239 SDValue
2240 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2241  MVT VecTy, SelectionDAG &DAG) const {
2242  MVT ElemTy = VecTy.getVectorElementType();
2243  assert(VecTy.getVectorNumElements() == Elem.size());
2244 
2245  SmallVector<ConstantInt*,8> Consts(Elem.size());
2246  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2247 
2248  unsigned First, Num = Elem.size();
2249  for (First = 0; First != Num; ++First)
2250  if (!isUndef(Elem[First]))
2251  break;
2252  if (First == Num)
2253  return DAG.getUNDEF(VecTy);
2254 
2255  if (AllConst &&
2256  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2257  return getZero(dl, VecTy, DAG);
2258 
2259  // First try splat if possible.
2260  if (ElemTy == MVT::i16) {
2261  bool IsSplat = true;
2262  for (unsigned i = 0; i != Num; ++i) {
2263  if (i == First)
2264  continue;
2265  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2266  continue;
2267  IsSplat = false;
2268  break;
2269  }
2270  if (IsSplat) {
2271  // Legalize the operand to VSPLAT.
2272  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2273  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2274  }
2275  }
2276 
2277  // Then try constant.
2278  if (AllConst) {
2279  uint64_t Val = 0;
2280  unsigned W = ElemTy.getSizeInBits();
2281  uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2282  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2283  for (unsigned i = 0; i != Num; ++i)
2284  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2285  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2286  return DAG.getBitcast(VecTy, V0);
2287  }
2288 
2289  // Build two 32-bit vectors and concatenate.
2290  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2291  SDValue L = (ElemTy == MVT::i32)
2292  ? Elem[0]
2293  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2294  SDValue H = (ElemTy == MVT::i32)
2295  ? Elem[1]
2296  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2297  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2298 }
2299 
2300 SDValue
2301 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2302  const SDLoc &dl, MVT ValTy, MVT ResTy,
2303  SelectionDAG &DAG) const {
2304  MVT VecTy = ty(VecV);
2305  assert(!ValTy.isVector() ||
2306  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2307  unsigned VecWidth = VecTy.getSizeInBits();
2308  unsigned ValWidth = ValTy.getSizeInBits();
2309  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2310  assert((VecWidth % ElemWidth) == 0);
2311  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2312 
2313  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2314  // without any coprocessors).
2315  if (ElemWidth == 1) {
2316  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
2317  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2318  // Check if this is an extract of the lowest bit.
2319  if (IdxN) {
2320  // Extracting the lowest bit is a no-op, but it changes the type,
2321  // so it must be kept as an operation to avoid errors related to
2322  // type mismatches.
2323  if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2324  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2325  }
2326 
2327  // If the value extracted is a single bit, use tstbit.
2328  if (ValWidth == 1) {
2329  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2330  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV);
2331  }
2332 
2333  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2334  // a predicate register. The elements of the vector are repeated
2335  // in the register (if necessary) so that the total number is 8.
2336  // The extracted subvector will need to be expanded in such a way.
2337  unsigned Scale = VecWidth / ValWidth;
2338 
2339  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2340  // position 0.
2341  assert(ty(IdxV) == MVT::i32);
2342  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2343  DAG.getConstant(8*Scale, dl, MVT::i32));
2344  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2345  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2346  while (Scale > 1) {
2347  // The longest possible subvector is at most 32 bits, so it is always
2348  // contained in the low subregister.
2349  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2350  T1 = expandPredicate(T1, dl, DAG);
2351  Scale /= 2;
2352  }
2353 
2354  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2355  }
2356 
2357  assert(VecWidth == 32 || VecWidth == 64);
2358 
2359  // Cast everything to scalar integer types.
2360  MVT ScalarTy = tyScalar(VecTy);
2361  VecV = DAG.getBitcast(ScalarTy, VecV);
2362 
2363  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2364  SDValue ExtV;
2365 
2366  if (IdxN) {
2367  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2368  if (VecWidth == 64 && ValWidth == 32) {
2369  assert(Off == 0 || Off == 32);
2370  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2371  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2372  } else if (Off == 0 && (ValWidth % 8) == 0) {
2373  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2374  } else {
2375  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2376  // The return type of EXTRACTU must be the same as the type of the
2377  // input vector.
2378  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2379  {VecV, WidthV, OffV});
2380  }
2381  } else {
2382  if (ty(IdxV) != MVT::i32)
2383  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2384  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2385  DAG.getConstant(ElemWidth, dl, MVT::i32));
2386  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2387  {VecV, WidthV, OffV});
2388  }
2389 
2390  // Cast ExtV to the requested result type.
2391  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2392  ExtV = DAG.getBitcast(ResTy, ExtV);
2393  return ExtV;
2394 }
2395 
2396 SDValue
2397 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2398  const SDLoc &dl, MVT ValTy,
2399  SelectionDAG &DAG) const {
2400  MVT VecTy = ty(VecV);
2401  if (VecTy.getVectorElementType() == MVT::i1) {
2402  MVT ValTy = ty(ValV);
2403  assert(ValTy.getVectorElementType() == MVT::i1);
2404  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2405  unsigned VecLen = VecTy.getVectorNumElements();
2406  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2407  assert(Scale > 1);
2408 
2409  for (unsigned R = Scale; R > 1; R /= 2) {
2410  ValR = contractPredicate(ValR, dl, DAG);
2411  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2412  DAG.getUNDEF(MVT::i32), ValR);
2413  }
2414  // The longest possible subvector is at most 32 bits, so it is always
2415  // contained in the low subregister.
2416  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2417 
2418  unsigned ValBytes = 64 / Scale;
2419  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2420  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2421  DAG.getConstant(8, dl, MVT::i32));
2422  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2424  {VecR, ValR, Width, Idx});
2425  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2426  }
2427 
2428  unsigned VecWidth = VecTy.getSizeInBits();
2429  unsigned ValWidth = ValTy.getSizeInBits();
2430  assert(VecWidth == 32 || VecWidth == 64);
2431  assert((VecWidth % ValWidth) == 0);
2432 
2433  // Cast everything to scalar integer types.
2434  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2435  // The actual type of ValV may be different than ValTy (which is related
2436  // to the vector type).
2437  unsigned VW = ty(ValV).getSizeInBits();
2438  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2439  VecV = DAG.getBitcast(ScalarTy, VecV);
2440  if (VW != VecWidth)
2441  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2442 
2443  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2444  SDValue InsV;
2445 
2446  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2447  unsigned W = C->getZExtValue() * ValWidth;
2448  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2449  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2450  {VecV, ValV, WidthV, OffV});
2451  } else {
2452  if (ty(IdxV) != MVT::i32)
2453  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2454  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2455  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2456  {VecV, ValV, WidthV, OffV});
2457  }
2458 
2459  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2460 }
2461 
2462 SDValue
2463 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2464  SelectionDAG &DAG) const {
2465  assert(ty(Vec32).getSizeInBits() == 32);
2466  if (isUndef(Vec32))
2467  return DAG.getUNDEF(MVT::i64);
2468  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2469 }
2470 
2471 SDValue
2472 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2473  SelectionDAG &DAG) const {
2474  assert(ty(Vec64).getSizeInBits() == 64);
2475  if (isUndef(Vec64))
2476  return DAG.getUNDEF(MVT::i32);
2477  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2478 }
2479 
2480 SDValue
2481 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2482  const {
2483  if (Ty.isVector()) {
2484  assert(Ty.isInteger() && "Only integer vectors are supported here");
2485  unsigned W = Ty.getSizeInBits();
2486  if (W <= 64)
2487  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2488  return DAG.getNode(HexagonISD::VZERO, dl, Ty);
2489  }
2490 
2491  if (Ty.isInteger())
2492  return DAG.getConstant(0, dl, Ty);
2493  if (Ty.isFloatingPoint())
2494  return DAG.getConstantFP(0.0, dl, Ty);
2495  llvm_unreachable("Invalid type for zero");
2496 }
2497 
2498 SDValue
2500  MVT VecTy = ty(Op);
2501  unsigned BW = VecTy.getSizeInBits();
2502  const SDLoc &dl(Op);
2504  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2505  Ops.push_back(Op.getOperand(i));
2506 
2507  if (BW == 32)
2508  return buildVector32(Ops, dl, VecTy, DAG);
2509  if (BW == 64)
2510  return buildVector64(Ops, dl, VecTy, DAG);
2511 
2512  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2513  // For each i1 element in the resulting predicate register, put 1
2514  // shifted by the index of the element into a general-purpose register,
2515  // then or them together and transfer it back into a predicate register.
2516  SDValue Rs[8];
2517  SDValue Z = getZero(dl, MVT::i32, DAG);
2518  // Always produce 8 bits, repeat inputs if necessary.
2519  unsigned Rep = 8 / VecTy.getVectorNumElements();
2520  for (unsigned i = 0; i != 8; ++i) {
2521  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2522  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2523  }
2524  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2525  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2526  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2527  }
2528  // Move the value directly to a predicate register.
2529  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2530  }
2531 
2532  return SDValue();
2533 }
2534 
2535 SDValue
2537  SelectionDAG &DAG) const {
2538  MVT VecTy = ty(Op);
2539  const SDLoc &dl(Op);
2540  if (VecTy.getSizeInBits() == 64) {
2541  assert(Op.getNumOperands() == 2);
2542  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2543  Op.getOperand(0));
2544  }
2545 
2546  MVT ElemTy = VecTy.getVectorElementType();
2547  if (ElemTy == MVT::i1) {
2548  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2549  MVT OpTy = ty(Op.getOperand(0));
2550  // Scale is how many times the operands need to be contracted to match
2551  // the representation in the target register.
2552  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2553  assert(Scale == Op.getNumOperands() && Scale > 1);
2554 
2555  // First, convert all bool vectors to integers, then generate pairwise
2556  // inserts to form values of doubled length. Up until there are only
2557  // two values left to concatenate, all of these values will fit in a
2558  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2559  SmallVector<SDValue,4> Words[2];
2560  unsigned IdxW = 0;
2561 
2562  for (SDValue P : Op.getNode()->op_values()) {
2563  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2564  for (unsigned R = Scale; R > 1; R /= 2) {
2565  W = contractPredicate(W, dl, DAG);
2566  W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2567  DAG.getUNDEF(MVT::i32), W);
2568  }
2569  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2570  Words[IdxW].push_back(W);
2571  }
2572 
2573  while (Scale > 2) {
2574  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2575  Words[IdxW ^ 1].clear();
2576 
2577  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2578  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2579  // Insert W1 into W0 right next to the significant bits of W0.
2581  {W0, W1, WidthV, WidthV});
2582  Words[IdxW ^ 1].push_back(T);
2583  }
2584  IdxW ^= 1;
2585  Scale /= 2;
2586  }
2587 
2588  // Another sanity check. At this point there should only be two words
2589  // left, and Scale should be 2.
2590  assert(Scale == 2 && Words[IdxW].size() == 2);
2591 
2593  Words[IdxW][1], Words[IdxW][0]);
2594  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2595  }
2596 
2597  return SDValue();
2598 }
2599 
2600 SDValue
2602  SelectionDAG &DAG) const {
2603  SDValue Vec = Op.getOperand(0);
2604  MVT ElemTy = ty(Vec).getVectorElementType();
2605  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2606 }
2607 
2608 SDValue
2610  SelectionDAG &DAG) const {
2611  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2612  ty(Op), ty(Op), DAG);
2613 }
2614 
2615 SDValue
2617  SelectionDAG &DAG) const {
2618  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2619  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2620 }
2621 
2622 SDValue
2624  SelectionDAG &DAG) const {
2625  SDValue ValV = Op.getOperand(1);
2626  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2627  SDLoc(Op), ty(ValV), DAG);
2628 }
2629 
2630 bool
2632  // Assuming the caller does not have either a signext or zeroext modifier, and
2633  // only one value is accepted, any reasonable truncation is allowed.
2634  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2635  return false;
2636 
2637  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2638  // fragile at the moment: any support for multiple value returns would be
2639  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2640  return Ty1->getPrimitiveSizeInBits() <= 32;
2641 }
2642 
2643 SDValue
2645  const {
2646  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2647  unsigned HaveAlign = LN->getAlignment();
2648  MVT LoadTy = ty(Op);
2649  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2650  if (HaveAlign >= NeedAlign)
2651  return Op;
2652 
2653  const SDLoc &dl(Op);
2654  const DataLayout &DL = DAG.getDataLayout();
2655  LLVMContext &Ctx = *DAG.getContext();
2656  unsigned AS = LN->getAddressSpace();
2657 
2658  // If the load aligning is disabled or the load can be broken up into two
2659  // smaller legal loads, do the default (target-independent) expansion.
2660  bool DoDefault = false;
2661  // Handle it in the default way if this is an indexed load.
2662  if (!LN->isUnindexed())
2663  DoDefault = true;
2664 
2665  if (!AlignLoads) {
2666  if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), AS, HaveAlign))
2667  return Op;
2668  DoDefault = true;
2669  }
2670  if (!DoDefault && 2*HaveAlign == NeedAlign) {
2671  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2672  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8*HaveAlign)
2673  : MVT::getVectorVT(MVT::i8, HaveAlign);
2674  DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, AS, HaveAlign);
2675  }
2676  if (DoDefault) {
2677  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2678  return DAG.getMergeValues({P.first, P.second}, dl);
2679  }
2680 
2681  // The code below generates two loads, both aligned as NeedAlign, and
2682  // with the distance of NeedAlign between them. For that to cover the
2683  // bits that need to be loaded (and without overlapping), the size of
2684  // the loads should be equal to NeedAlign. This is true for all loadable
2685  // types, but add an assertion in case something changes in the future.
2686  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
2687 
2688  unsigned LoadLen = NeedAlign;
2689  SDValue Base = LN->getBasePtr();
2690  SDValue Chain = LN->getChain();
2691  auto BO = getBaseAndOffset(Base);
2692  unsigned BaseOpc = BO.first.getOpcode();
2693  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2694  return Op;
2695 
2696  if (BO.second % LoadLen != 0) {
2697  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2698  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2699  BO.second -= BO.second % LoadLen;
2700  }
2701  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2702  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2703  DAG.getConstant(NeedAlign, dl, MVT::i32))
2704  : BO.first;
2705  SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
2706  SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
2707 
2708  MachineMemOperand *WideMMO = nullptr;
2709  if (MachineMemOperand *MMO = LN->getMemOperand()) {
2710  MachineFunction &MF = DAG.getMachineFunction();
2711  WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
2712  2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
2713  MMO->getSyncScopeID(), MMO->getOrdering(),
2714  MMO->getFailureOrdering());
2715  }
2716 
2717  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2718  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2719 
2720  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2721  {Load1, Load0, BaseNoOff.getOperand(0)});
2722  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2723  Load0.getValue(1), Load1.getValue(1));
2724  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2725  return M;
2726 }
2727 
2728 SDValue
2730  const SDLoc &dl(Op);
2731  unsigned Opc = Op.getOpcode();
2732  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
2733 
2734  if (Opc == ISD::ADDCARRY)
2735  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
2736  { X, Y, C });
2737 
2738  EVT CarryTy = C.getValueType();
2739  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
2740  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
2741  SDValue Out[] = { SubC.getValue(0),
2742  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
2743  return DAG.getMergeValues(Out, dl);
2744 }
2745 
2746 SDValue
2748  SDValue Chain = Op.getOperand(0);
2749  SDValue Offset = Op.getOperand(1);
2750  SDValue Handler = Op.getOperand(2);
2751  SDLoc dl(Op);
2752  auto PtrVT = getPointerTy(DAG.getDataLayout());
2753 
2754  // Mark function as containing a call to EH_RETURN.
2755  HexagonMachineFunctionInfo *FuncInfo =
2757  FuncInfo->setHasEHReturn();
2758 
2759  unsigned OffsetReg = Hexagon::R28;
2760 
2761  SDValue StoreAddr =
2762  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2763  DAG.getIntPtrConstant(4, dl));
2764  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2765  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2766 
2767  // Not needed we already use it as explict input to EH_RETURN.
2768  // MF.getRegInfo().addLiveOut(OffsetReg);
2769 
2770  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2771 }
2772 
2773 SDValue
2775  unsigned Opc = Op.getOpcode();
2776 
2777  // Handle INLINEASM first.
2778  if (Opc == ISD::INLINEASM)
2779  return LowerINLINEASM(Op, DAG);
2780 
2781  if (isHvxOperation(Op)) {
2782  // If HVX lowering returns nothing, try the default lowering.
2783  if (SDValue V = LowerHvxOperation(Op, DAG))
2784  return V;
2785  }
2786 
2787  switch (Opc) {
2788  default:
2789 #ifndef NDEBUG
2790  Op.getNode()->dumpr(&DAG);
2791  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2792  errs() << "Error: check for a non-legal type in this operation\n";
2793 #endif
2794  llvm_unreachable("Should not custom lower this!");
2795  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2796  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
2797  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
2798  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
2799  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2800  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2801  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2802  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
2803  case ISD::LOAD: return LowerUnalignedLoad(Op, DAG);
2804  case ISD::ADDCARRY:
2805  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
2806  case ISD::SRA:
2807  case ISD::SHL:
2808  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2809  case ISD::ROTL: return LowerROTL(Op, DAG);
2810  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2811  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2812  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2813  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2814  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2815  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2816  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2817  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2818  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2819  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2820  case ISD::VASTART: return LowerVASTART(Op, DAG);
2821  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2822  case ISD::SETCC: return LowerSETCC(Op, DAG);
2823  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2824  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2825  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2826  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2827  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2828  break;
2829  }
2830 
2831  return SDValue();
2832 }
2833 
2834 void
2837  SelectionDAG &DAG) const {
2838  const SDLoc &dl(N);
2839  switch (N->getOpcode()) {
2840  case ISD::SRL:
2841  case ISD::SRA:
2842  case ISD::SHL:
2843  return;
2844  case ISD::BITCAST:
2845  // Handle a bitcast from v8i1 to i8.
2846  if (N->getValueType(0) == MVT::i8) {
2847  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
2848  N->getOperand(0), DAG);
2849  Results.push_back(P);
2850  }
2851  break;
2852  }
2853 }
2854 
2855 /// Returns relocation base for the given PIC jumptable.
2856 SDValue
2858  SelectionDAG &DAG) const {
2859  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2860  EVT VT = Table.getValueType();
2862  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2863 }
2864 
2865 //===----------------------------------------------------------------------===//
2866 // Inline Assembly Support
2867 //===----------------------------------------------------------------------===//
2868 
2871  if (Constraint.size() == 1) {
2872  switch (Constraint[0]) {
2873  case 'q':
2874  case 'v':
2875  if (Subtarget.useHVXOps())
2876  return C_RegisterClass;
2877  break;
2878  case 'a':
2879  return C_RegisterClass;
2880  default:
2881  break;
2882  }
2883  }
2884  return TargetLowering::getConstraintType(Constraint);
2885 }
2886 
2887 std::pair<unsigned, const TargetRegisterClass*>
2889  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2890 
2891  if (Constraint.size() == 1) {
2892  switch (Constraint[0]) {
2893  case 'r': // R0-R31
2894  switch (VT.SimpleTy) {
2895  default:
2896  return {0u, nullptr};
2897  case MVT::i1:
2898  case MVT::i8:
2899  case MVT::i16:
2900  case MVT::i32:
2901  case MVT::f32:
2902  return {0u, &Hexagon::IntRegsRegClass};
2903  case MVT::i64:
2904  case MVT::f64:
2905  return {0u, &Hexagon::DoubleRegsRegClass};
2906  }
2907  break;
2908  case 'a': // M0-M1
2909  if (VT != MVT::i32)
2910  return {0u, nullptr};
2911  return {0u, &Hexagon::ModRegsRegClass};
2912  case 'q': // q0-q3
2913  switch (VT.getSizeInBits()) {
2914  default:
2915  return {0u, nullptr};
2916  case 512:
2917  case 1024:
2918  return {0u, &Hexagon::HvxQRRegClass};
2919  }
2920  break;
2921  case 'v': // V0-V31
2922  switch (VT.getSizeInBits()) {
2923  default:
2924  return {0u, nullptr};
2925  case 512:
2926  return {0u, &Hexagon::HvxVRRegClass};
2927  case 1024:
2928  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
2929  return {0u, &Hexagon::HvxVRRegClass};
2930  return {0u, &Hexagon::HvxWRRegClass};
2931  case 2048:
2932  return {0u, &Hexagon::HvxWRRegClass};
2933  }
2934  break;
2935  default:
2936  return {0u, nullptr};
2937  }
2938  }
2939 
2940  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2941 }
2942 
2943 /// isFPImmLegal - Returns true if the target can instruction select the
2944 /// specified FP immediate natively. If false, the legalizer will
2945 /// materialize the FP immediate as a load from a constant pool.
2947  return Subtarget.hasV5Ops();
2948 }
2949 
2950 /// isLegalAddressingMode - Return true if the addressing mode represented by
2951 /// AM is legal for this target, for a load/store of the specified type.
2953  const AddrMode &AM, Type *Ty,
2954  unsigned AS, Instruction *I) const {
2955  if (Ty->isSized()) {
2956  // When LSR detects uses of the same base address to access different
2957  // types (e.g. unions), it will assume a conservative type for these
2958  // uses:
2959  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
2960  // The type Ty passed here would then be "void". Skip the alignment
2961  // checks, but do not return false right away, since that confuses
2962  // LSR into crashing.
2963  unsigned A = DL.getABITypeAlignment(Ty);
2964  // The base offset must be a multiple of the alignment.
2965  if ((AM.BaseOffs % A) != 0)
2966  return false;
2967  // The shifted offset must fit in 11 bits.
2968  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
2969  return false;
2970  }
2971 
2972  // No global is ever allowed as a base.
2973  if (AM.BaseGV)
2974  return false;
2975 
2976  int Scale = AM.Scale;
2977  if (Scale < 0)
2978  Scale = -Scale;
2979  switch (Scale) {
2980  case 0: // No scale reg, "r+i", "r", or just "i".
2981  break;
2982  default: // No scaled addressing mode.
2983  return false;
2984  }
2985  return true;
2986 }
2987 
2988 /// Return true if folding a constant offset with the given GlobalAddress is
2989 /// legal. It is frequently not legal in PIC relocation models.
2991  const {
2992  return HTM.getRelocationModel() == Reloc::Static;
2993 }
2994 
2995 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2996 /// icmp immediate, that is the target has icmp instructions which can compare
2997 /// a register against the immediate without having to materialize the
2998 /// immediate into a register.
3000  return Imm >= -512 && Imm <= 511;
3001 }
3002 
3003 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3004 /// for tail call optimization. Targets which want to do tail call
3005 /// optimization should implement this function.
3007  SDValue Callee,
3008  CallingConv::ID CalleeCC,
3009  bool IsVarArg,
3010  bool IsCalleeStructRet,
3011  bool IsCallerStructRet,
3012  const SmallVectorImpl<ISD::OutputArg> &Outs,
3013  const SmallVectorImpl<SDValue> &OutVals,
3015  SelectionDAG& DAG) const {
3016  const Function &CallerF = DAG.getMachineFunction().getFunction();
3017  CallingConv::ID CallerCC = CallerF.getCallingConv();
3018  bool CCMatch = CallerCC == CalleeCC;
3019 
3020  // ***************************************************************************
3021  // Look for obvious safe cases to perform tail call optimization that do not
3022  // require ABI changes.
3023  // ***************************************************************************
3024 
3025  // If this is a tail call via a function pointer, then don't do it!
3026  if (!isa<GlobalAddressSDNode>(Callee) &&
3027  !isa<ExternalSymbolSDNode>(Callee)) {
3028  return false;
3029  }
3030 
3031  // Do not optimize if the calling conventions do not match and the conventions
3032  // used are not C or Fast.
3033  if (!CCMatch) {
3034  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3035  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3036  // If R & E, then ok.
3037  if (!R || !E)
3038  return false;
3039  }
3040 
3041  // Do not tail call optimize vararg calls.
3042  if (IsVarArg)
3043  return false;
3044 
3045  // Also avoid tail call optimization if either caller or callee uses struct
3046  // return semantics.
3047  if (IsCalleeStructRet || IsCallerStructRet)
3048  return false;
3049 
3050  // In addition to the cases above, we also disable Tail Call Optimization if
3051  // the calling convention code that at least one outgoing argument needs to
3052  // go on the stack. We cannot check that here because at this point that
3053  // information is not available.
3054  return true;
3055 }
3056 
3057 /// Returns the target specific optimal type for load and store operations as
3058 /// a result of memset, memcpy, and memmove lowering.
3059 ///
3060 /// If DstAlign is zero that means it's safe to destination alignment can
3061 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3062 /// a need to check it against alignment requirement, probably because the
3063 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3064 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3065 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3066 /// does not need to be loaded. It returns EVT::Other if the type should be
3067 /// determined using generic target-independent logic.
3069  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3070  bool MemcpyStrSrc, MachineFunction &MF) const {
3071 
3072  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3073  return (GivenA % MinA) == 0;
3074  };
3075 
3076  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3077  return MVT::i64;
3078  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3079  return MVT::i32;
3080  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3081  return MVT::i16;
3082 
3083  return MVT::Other;
3084 }
3085 
3087  unsigned AS, unsigned Align, bool *Fast) const {
3088  if (Fast)
3089  *Fast = false;
3090  return Subtarget.isHVXVectorType(VT.getSimpleVT());
3091 }
3092 
3093 std::pair<const TargetRegisterClass*, uint8_t>
3094 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3095  MVT VT) const {
3096  if (Subtarget.isHVXVectorType(VT, true)) {
3097  unsigned BitWidth = VT.getSizeInBits();
3098  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3099 
3100  if (VT.getVectorElementType() == MVT::i1)
3101  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3102  if (BitWidth == VecWidth)
3103  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3104  assert(BitWidth == 2 * VecWidth);
3105  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3106  }
3107 
3109 }
3110 
3112  AtomicOrdering Ord) const {
3113  BasicBlock *BB = Builder.GetInsertBlock();
3114  Module *M = BB->getParent()->getParent();
3115  Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3116  unsigned SZ = Ty->getPrimitiveSizeInBits();
3117  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3118  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3119  : Intrinsic::hexagon_L4_loadd_locked;
3120  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3121  return Builder.CreateCall(Fn, Addr, "larx");
3122 }
3123 
3124 /// Perform a store-conditional operation to Addr. Return the status of the
3125 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3127  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3128  BasicBlock *BB = Builder.GetInsertBlock();
3129  Module *M = BB->getParent()->getParent();
3130  Type *Ty = Val->getType();
3131  unsigned SZ = Ty->getPrimitiveSizeInBits();
3132  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3133  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3134  : Intrinsic::hexagon_S4_stored_locked;
3135  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3136  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3137  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3138  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3139  return Ext;
3140 }
3141 
3144  // Do not expand loads and stores that don't exceed 64 bits.
3145  return LI->getType()->getPrimitiveSizeInBits() > 64
3148 }
3149 
3151  // Do not expand loads and stores that don't exceed 64 bits.
3152  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3153 }
3154 
3156  AtomicCmpXchgInst *AI) const {
3157  const DataLayout &DL = AI->getModule()->getDataLayout();
3158  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3159  return Size >= 4 && Size <= 8;
3160 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
bool isMachineConstantPoolEntry() const
Type * getVectorElementType() const
Definition: Type.h:371
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:539
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:506
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
Definition: Instructions.h:399
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:563
EVT getValueType() const
Return the ValueType of the referenced return value.
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isUndef() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1556
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:212
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:951
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:849
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:334
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:611
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:343
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:63
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:265
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:518
bool isVector() const
Return true if this is a vector value type.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const SDValue & getBasePtr() const
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:660
SDVTList getVTList() const
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:251
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
unsigned getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
const SDValue & getChain() const
Function Alias Analysis Results
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:714
unsigned getAlignment() const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Hexagon target-specific information for each MachineFunction.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:908
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
unsigned const TargetRegisterInfo * TRI
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
F(f)
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:964
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
An instruction for reading from memory.
Definition: Instructions.h:168
SDNode * getNode() const
get the SDNode which holds the desired result
#define R2(n)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:254
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:329
The address of the GOT.
Definition: ISDOpcodes.h:66
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:742
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:405
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:159
bool isMemLoc() const
unsigned getAddressSpace() const
Return the address space for the associated pointer.
SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL)
Returns sum of the base pointer and offset.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:565
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:210
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:426
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:836
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:361
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Shift and rotation operations.
Definition: ISDOpcodes.h:380
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:242
Base class for LoadSDNode and StoreSDNode.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:369
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:639
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:191
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:731
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:92
#define Hexagon_PointerSize
Definition: Hexagon.h:20
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:457
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:398
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
zlib-gnu style compression
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:628
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:656
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
int64_t getSExtValue() const
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static Value * getBrevLdObject(Value *V)
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1568
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:395
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:448
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
#define T
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:121
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:399
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:201
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:138
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:865
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
An instruction for storing to memory.
Definition: Instructions.h:310
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:911
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1556
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:708
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
amdgpu Simplify well known AMD library false Value * Callee
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1007
MVT getVectorElementType() const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Value * getOperand(unsigned i) const
Definition: User.h:170
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Class to represent pointers.
Definition: DerivedTypes.h:467
unsigned getByValSize() const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:492
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:303
Value * getOperand(unsigned i_nocapture) const
The memory access is volatile.
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:155
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:291
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:429
Machine Value Type.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
Definition: ISDOpcodes.h:260
static bool isBrevLdIntrinsic(const Value *Inst)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:689
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:308
#define H(x, y, z)
Definition: MD5.cpp:57
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:264
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:837
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:336
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
const APInt & getAPIntValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:325
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:115
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
static mvt_range vector_valuetypes()
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:1736
Class to represent integer types.
Definition: DerivedTypes.h:40
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:281
Constant Vector Declarations.
Definition: Constants.h:496
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:680
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:936
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:524
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:929
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
unsigned first
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:299
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:634
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:628
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void dump() const
Dump this node, for debugging.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:240
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
#define HEXAGON_LRFP_SIZE
Definition: Hexagon.h:27
unsigned getNumOperands() const
Definition: User.h:192
CCState - This class holds information needed while lowering arguments and return values...
static unsigned getIntrinsicID(const SDNode *N)
This is the shared class of boolean and integer constants.
Definition: Constants.h:84
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1032
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:315
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
#define HEXAGON_GOT_SYM_NAME
Definition: Hexagon.h:43
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:199
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:222
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:861
Module.h This file contains the declarations for the Module class.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
iterator end() const
Definition: ArrayRef.h:138
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:722
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:383
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:307
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
Represents one node in the SelectionDAG.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:674
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
static mvt_range integer_valuetypes()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:924
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:150
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:56
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:390
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:438
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:441
bool isTailCall() const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:288
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:599
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:685
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:668
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
unsigned getVectorLength() const
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:363
MO_GOT - Indicates a GOT-relative relocation.
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
unsigned getTypeAlignment(MVT Ty) const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:700
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:176
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:206
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:62
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:456
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:188
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:575
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:108
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:400
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:193
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:569
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:309
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:102
const GlobalObject * getBaseObject() const
Definition: Globals.cpp:256
bool isRegLoc() const
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:870
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:321
MachineConstantPoolValue * getMachineCPVal() const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void dumpr() const
Dump (recursively) this node and its use-def subgraph.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setReturnAddressIsTaken(bool s)
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memcpy"))
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
aarch64 promote const
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
LLVM Value Representation.
Definition: Value.h:73
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:278
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getRegister(unsigned Reg, EVT VT)