LLVM  9.0.0svn
HexagonISelLowering.cpp
Go to the documentation of this file.
1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
10 // into a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonISelLowering.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
46 #include "llvm/IR/Value.h"
47 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/CodeGen.h"
51 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <limits>
61 #include <utility>
62 
63 using namespace llvm;
64 
65 #define DEBUG_TYPE "hexagon-lowering"
66 
67 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
68  cl::init(true), cl::Hidden,
69  cl::desc("Control jump table emission on Hexagon target"));
70 
71 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
73  cl::desc("Enable Hexagon SDNode scheduling"));
74 
75 static cl::opt<bool> EnableFastMath("ffast-math",
77  cl::desc("Enable Fast Math processing"));
78 
79 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
81  cl::desc("Set minimum jump tables"));
82 
83 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
85  cl::desc("Max #stores to inline memcpy"));
86 
87 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
89  cl::desc("Max #stores to inline memcpy"));
90 
91 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
93  cl::desc("Max #stores to inline memmove"));
94 
95 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
97  cl::desc("Max #stores to inline memmove"));
98 
99 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
101  cl::desc("Max #stores to inline memset"));
102 
103 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
105  cl::desc("Max #stores to inline memset"));
106 
107 static cl::opt<bool> AlignLoads("hexagon-align-loads",
108  cl::Hidden, cl::init(false),
109  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
110 
111 
112 namespace {
113 
114  class HexagonCCState : public CCState {
115  unsigned NumNamedVarArgParams = 0;
116 
117  public:
118  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
120  unsigned NumNamedArgs)
121  : CCState(CC, IsVarArg, MF, locs, C),
122  NumNamedVarArgParams(NumNamedArgs) {}
123  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
124  };
125 
126 } // end anonymous namespace
127 
128 
129 // Implement calling convention for Hexagon.
130 
131 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
132  CCValAssign::LocInfo &LocInfo,
133  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
134  static const MCPhysReg ArgRegs[] = {
135  Hexagon::R0, Hexagon::R1, Hexagon::R2,
136  Hexagon::R3, Hexagon::R4, Hexagon::R5
137  };
138  const unsigned NumArgRegs = array_lengthof(ArgRegs);
139  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
140 
141  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
142  if (RegNum != NumArgRegs && RegNum % 2 == 1)
143  State.AllocateReg(ArgRegs[RegNum]);
144 
145  // Always return false here, as this function only makes sure that the first
146  // unallocated register has an even register number and does not actually
147  // allocate a register for the current argument.
148  return false;
149 }
150 
151 #include "HexagonGenCallingConv.inc"
152 
153 
154 SDValue
156  const {
157  return SDValue();
158 }
159 
160 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
161 /// by "Src" to address "Dst" of size "Size". Alignment information is
162 /// specified by the specific parameter attribute. The copy will be passed as
163 /// a byval function parameter. Sometimes what we are copying is the end of a
164 /// larger object, the part that does not fit in registers.
166  SDValue Chain, ISD::ArgFlagsTy Flags,
167  SelectionDAG &DAG, const SDLoc &dl) {
168  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
169  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
170  /*isVolatile=*/false, /*AlwaysInline=*/false,
171  /*isTailCall=*/false,
173 }
174 
175 bool
177  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
179  LLVMContext &Context) const {
181  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
182 
184  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
185  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
186 }
187 
188 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
189 // passed by value, the function prototype is modified to return void and
190 // the value is stored in memory pointed by a pointer passed by caller.
191 SDValue
193  bool IsVarArg,
195  const SmallVectorImpl<SDValue> &OutVals,
196  const SDLoc &dl, SelectionDAG &DAG) const {
197  // CCValAssign - represent the assignment of the return value to locations.
199 
200  // CCState - Info about the registers and stack slot.
201  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
202  *DAG.getContext());
203 
204  // Analyze return values of ISD::RET
205  if (Subtarget.useHVXOps())
206  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
207  else
208  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
209 
210  SDValue Flag;
211  SmallVector<SDValue, 4> RetOps(1, Chain);
212 
213  // Copy the result values into the output registers.
214  for (unsigned i = 0; i != RVLocs.size(); ++i) {
215  CCValAssign &VA = RVLocs[i];
216 
217  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
218 
219  // Guarantee that all emitted copies are stuck together with flags.
220  Flag = Chain.getValue(1);
221  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
222  }
223 
224  RetOps[0] = Chain; // Update chain.
225 
226  // Add the flag if we have it.
227  if (Flag.getNode())
228  RetOps.push_back(Flag);
229 
230  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
231 }
232 
234  // If either no tail call or told not to tail call at all, don't.
235  auto Attr =
236  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
237  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
238  return false;
239 
240  return true;
241 }
242 
243 unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
244  SelectionDAG &DAG) const {
245  // Just support r19, the linux kernel uses it.
246  unsigned Reg = StringSwitch<unsigned>(RegName)
247  .Case("r19", Hexagon::R19)
248  .Default(0);
249  if (Reg)
250  return Reg;
251 
252  report_fatal_error("Invalid register name global variable");
253 }
254 
255 /// LowerCallResult - Lower the result values of an ISD::CALL into the
256 /// appropriate copies out of appropriate physical registers. This assumes that
257 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
258 /// being lowered. Returns a SDNode with the same number of values as the
259 /// ISD::CALL.
261  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
262  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
264  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
265  // Assign locations to each value returned by this call.
267 
268  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
269  *DAG.getContext());
270 
271  if (Subtarget.useHVXOps())
272  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
273  else
274  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
275 
276  // Copy all of the result registers out of their specified physreg.
277  for (unsigned i = 0; i != RVLocs.size(); ++i) {
278  SDValue RetVal;
279  if (RVLocs[i].getValVT() == MVT::i1) {
280  // Return values of type MVT::i1 require special handling. The reason
281  // is that MVT::i1 is associated with the PredRegs register class, but
282  // values of that type are still returned in R0. Generate an explicit
283  // copy into a predicate register from R0, and treat the value of the
284  // predicate register as the call result.
285  auto &MRI = DAG.getMachineFunction().getRegInfo();
286  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
287  MVT::i32, Glue);
288  // FR0 = (Value, Chain, Glue)
289  unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
290  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
291  FR0.getValue(0), FR0.getValue(2));
292  // TPR = (Chain, Glue)
293  // Don't glue this CopyFromReg, because it copies from a virtual
294  // register. If it is glued to the call, InstrEmitter will add it
295  // as an implicit def to the call (EmitMachineNode).
296  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
297  Glue = TPR.getValue(1);
298  Chain = TPR.getValue(0);
299  } else {
300  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
301  RVLocs[i].getValVT(), Glue);
302  Glue = RetVal.getValue(2);
303  Chain = RetVal.getValue(1);
304  }
305  InVals.push_back(RetVal.getValue(0));
306  }
307 
308  return Chain;
309 }
310 
311 /// LowerCall - Functions arguments are copied from virtual regs to
312 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
313 SDValue
315  SmallVectorImpl<SDValue> &InVals) const {
316  SelectionDAG &DAG = CLI.DAG;
317  SDLoc &dl = CLI.DL;
319  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
321  SDValue Chain = CLI.Chain;
322  SDValue Callee = CLI.Callee;
323  CallingConv::ID CallConv = CLI.CallConv;
324  bool IsVarArg = CLI.IsVarArg;
325  bool DoesNotReturn = CLI.DoesNotReturn;
326 
327  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
329  MachineFrameInfo &MFI = MF.getFrameInfo();
330  auto PtrVT = getPointerTy(MF.getDataLayout());
331 
332  unsigned NumParams = CLI.CS.getInstruction()
333  ? CLI.CS.getFunctionType()->getNumParams()
334  : 0;
335  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
336  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
337 
338  // Analyze operands of the call, assigning locations to each operand.
340  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
341  NumParams);
342 
343  if (Subtarget.useHVXOps())
344  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
345  else
346  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
347 
348  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
349  if (Attr.getValueAsString() == "true")
350  CLI.IsTailCall = false;
351 
352  if (CLI.IsTailCall) {
353  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
354  CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
355  IsVarArg, IsStructRet, StructAttrFlag, Outs,
356  OutVals, Ins, DAG);
357  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
358  CCValAssign &VA = ArgLocs[i];
359  if (VA.isMemLoc()) {
360  CLI.IsTailCall = false;
361  break;
362  }
363  }
364  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
365  : "Argument must be passed on stack. "
366  "Not eligible for Tail Call\n"));
367  }
368  // Get a count of how many bytes are to be pushed on the stack.
369  unsigned NumBytes = CCInfo.getNextStackOffset();
371  SmallVector<SDValue, 8> MemOpChains;
372 
373  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
374  SDValue StackPtr =
375  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
376 
377  bool NeedsArgAlign = false;
378  unsigned LargestAlignSeen = 0;
379  // Walk the register/memloc assignments, inserting copies/loads.
380  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
381  CCValAssign &VA = ArgLocs[i];
382  SDValue Arg = OutVals[i];
383  ISD::ArgFlagsTy Flags = Outs[i].Flags;
384  // Record if we need > 8 byte alignment on an argument.
385  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
386  NeedsArgAlign |= ArgAlign;
387 
388  // Promote the value if needed.
389  switch (VA.getLocInfo()) {
390  default:
391  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
392  llvm_unreachable("Unknown loc info!");
393  case CCValAssign::Full:
394  break;
395  case CCValAssign::BCvt:
396  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
397  break;
398  case CCValAssign::SExt:
399  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
400  break;
401  case CCValAssign::ZExt:
402  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
403  break;
404  case CCValAssign::AExt:
405  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
406  break;
407  }
408 
409  if (VA.isMemLoc()) {
410  unsigned LocMemOffset = VA.getLocMemOffset();
411  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
412  StackPtr.getValueType());
413  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
414  if (ArgAlign)
415  LargestAlignSeen = std::max(LargestAlignSeen,
416  VA.getLocVT().getStoreSizeInBits() >> 3);
417  if (Flags.isByVal()) {
418  // The argument is a struct passed by value. According to LLVM, "Arg"
419  // is a pointer.
420  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
421  Flags, DAG, dl));
422  } else {
424  DAG.getMachineFunction(), LocMemOffset);
425  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
426  MemOpChains.push_back(S);
427  }
428  continue;
429  }
430 
431  // Arguments that can be passed on register must be kept at RegsToPass
432  // vector.
433  if (VA.isRegLoc())
434  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
435  }
436 
437  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
438  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
439  unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
440  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
441  MFI.ensureMaxAlignment(LargestAlignSeen);
442  }
443  // Transform all store nodes into one single node because all store
444  // nodes are independent of each other.
445  if (!MemOpChains.empty())
446  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
447 
448  SDValue Glue;
449  if (!CLI.IsTailCall) {
450  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
451  Glue = Chain.getValue(1);
452  }
453 
454  // Build a sequence of copy-to-reg nodes chained together with token
455  // chain and flag operands which copy the outgoing args into registers.
456  // The Glue is necessary since all emitted instructions must be
457  // stuck together.
458  if (!CLI.IsTailCall) {
459  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
460  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
461  RegsToPass[i].second, Glue);
462  Glue = Chain.getValue(1);
463  }
464  } else {
465  // For tail calls lower the arguments to the 'real' stack slot.
466  //
467  // Force all the incoming stack arguments to be loaded from the stack
468  // before any new outgoing arguments are stored to the stack, because the
469  // outgoing stack slots may alias the incoming argument stack slots, and
470  // the alias isn't otherwise explicit. This is slightly more conservative
471  // than necessary, because it means that each store effectively depends
472  // on every argument instead of just those arguments it would clobber.
473  //
474  // Do not flag preceding copytoreg stuff together with the following stuff.
475  Glue = SDValue();
476  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
477  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
478  RegsToPass[i].second, Glue);
479  Glue = Chain.getValue(1);
480  }
481  Glue = SDValue();
482  }
483 
484  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
485  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
486 
487  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
488  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
489  // node so that legalize doesn't hack it.
490  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
491  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
492  } else if (ExternalSymbolSDNode *S =
493  dyn_cast<ExternalSymbolSDNode>(Callee)) {
494  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
495  }
496 
497  // Returns a chain & a flag for retval copy to use.
498  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
500  Ops.push_back(Chain);
501  Ops.push_back(Callee);
502 
503  // Add argument registers to the end of the list so that they are
504  // known live into the call.
505  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
506  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
507  RegsToPass[i].second.getValueType()));
508  }
509 
510  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
511  assert(Mask && "Missing call preserved mask for calling convention");
512  Ops.push_back(DAG.getRegisterMask(Mask));
513 
514  if (Glue.getNode())
515  Ops.push_back(Glue);
516 
517  if (CLI.IsTailCall) {
518  MFI.setHasTailCall();
519  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
520  }
521 
522  // Set this here because we need to know this for "hasFP" in frame lowering.
523  // The target-independent code calls getFrameRegister before setting it, and
524  // getFrameRegister uses hasFP to determine whether the function has FP.
525  MFI.setHasCalls(true);
526 
527  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
528  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
529  Glue = Chain.getValue(1);
530 
531  // Create the CALLSEQ_END node.
532  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
533  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
534  Glue = Chain.getValue(1);
535 
536  // Handle result values, copying them out of physregs into vregs that we
537  // return.
538  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
539  InVals, OutVals, Callee);
540 }
541 
542 /// Returns true by value, base pointer and offset pointer and addressing
543 /// mode by reference if this node can be combined with a load / store to
544 /// form a post-indexed load / store.
547  SelectionDAG &DAG) const {
549  if (!LSN)
550  return false;
551  EVT VT = LSN->getMemoryVT();
552  if (!VT.isSimple())
553  return false;
554  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
555  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
556  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
557  VT == MVT::v4i16 || VT == MVT::v8i8 ||
558  Subtarget.isHVXVectorType(VT.getSimpleVT());
559  if (!IsLegalType)
560  return false;
561 
562  if (Op->getOpcode() != ISD::ADD)
563  return false;
564  Base = Op->getOperand(0);
565  Offset = Op->getOperand(1);
566  if (!isa<ConstantSDNode>(Offset.getNode()))
567  return false;
568  AM = ISD::POST_INC;
569 
570  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
571  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
572 }
573 
574 SDValue
577  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
578  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
579  unsigned LR = HRI.getRARegister();
580 
581  if (Op.getOpcode() != ISD::INLINEASM || HMFI.hasClobberLR())
582  return Op;
583 
584  unsigned NumOps = Op.getNumOperands();
585  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
586  --NumOps; // Ignore the flag operand.
587 
588  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
589  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
590  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
591  ++i; // Skip the ID value.
592 
593  switch (InlineAsm::getKind(Flags)) {
594  default:
595  llvm_unreachable("Bad flags!");
597  case InlineAsm::Kind_Imm:
598  case InlineAsm::Kind_Mem:
599  i += NumVals;
600  break;
604  for (; NumVals; --NumVals, ++i) {
605  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
606  if (Reg != LR)
607  continue;
608  HMFI.setHasClobberLR(true);
609  return Op;
610  }
611  break;
612  }
613  }
614  }
615 
616  return Op;
617 }
618 
619 // Need to transform ISD::PREFETCH into something that doesn't inherit
620 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
621 // SDNPMayStore.
623  SelectionDAG &DAG) const {
624  SDValue Chain = Op.getOperand(0);
625  SDValue Addr = Op.getOperand(1);
626  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
627  // if the "reg" is fed by an "add".
628  SDLoc DL(Op);
629  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
630  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
631 }
632 
633 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
634 // is marked as having side-effects, while the register read on Hexagon does
635 // not have any. TableGen refuses to accept the direct pattern from that node
636 // to the A4_tfrcpp.
638  SelectionDAG &DAG) const {
639  SDValue Chain = Op.getOperand(0);
640  SDLoc dl(Op);
642  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
643 }
644 
646  SelectionDAG &DAG) const {
647  SDValue Chain = Op.getOperand(0);
648  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
649  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
650  if (IntNo == Intrinsic::hexagon_prefetch) {
651  SDValue Addr = Op.getOperand(2);
652  SDLoc DL(Op);
653  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
654  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
655  }
656  return SDValue();
657 }
658 
659 SDValue
661  SelectionDAG &DAG) const {
662  SDValue Chain = Op.getOperand(0);
663  SDValue Size = Op.getOperand(1);
664  SDValue Align = Op.getOperand(2);
665  SDLoc dl(Op);
666 
668  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
669 
670  unsigned A = AlignConst->getSExtValue();
671  auto &HFI = *Subtarget.getFrameLowering();
672  // "Zero" means natural stack alignment.
673  if (A == 0)
674  A = HFI.getStackAlignment();
675 
676  LLVM_DEBUG({
677  dbgs () << __func__ << " Align: " << A << " Size: ";
678  Size.getNode()->dump(&DAG);
679  dbgs() << "\n";
680  });
681 
682  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
684  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
685 
686  DAG.ReplaceAllUsesOfValueWith(Op, AA);
687  return AA;
688 }
689 
691  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
692  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
693  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
695  MachineFrameInfo &MFI = MF.getFrameInfo();
697 
698  // Assign locations to all of the incoming arguments.
700  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
702 
703  if (Subtarget.useHVXOps())
704  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
705  else
706  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
707 
708  // For LLVM, in the case when returning a struct by value (>8byte),
709  // the first argument is a pointer that points to the location on caller's
710  // stack where the return value will be stored. For Hexagon, the location on
711  // caller's stack is passed only when the struct size is smaller than (and
712  // equal to) 8 bytes. If not, no address will be passed into callee and
713  // callee return the result direclty through R0/R1.
714 
715  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
716 
717  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
718  CCValAssign &VA = ArgLocs[i];
719  ISD::ArgFlagsTy Flags = Ins[i].Flags;
720  bool ByVal = Flags.isByVal();
721 
722  // Arguments passed in registers:
723  // 1. 32- and 64-bit values and HVX vectors are passed directly,
724  // 2. Large structs are passed via an address, and the address is
725  // passed in a register.
726  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
727  llvm_unreachable("ByValSize must be bigger than 8 bytes");
728 
729  bool InReg = VA.isRegLoc() &&
730  (!ByVal || (ByVal && Flags.getByValSize() > 8));
731 
732  if (InReg) {
733  MVT RegVT = VA.getLocVT();
734  if (VA.getLocInfo() == CCValAssign::BCvt)
735  RegVT = VA.getValVT();
736 
737  const TargetRegisterClass *RC = getRegClassFor(RegVT);
738  unsigned VReg = MRI.createVirtualRegister(RC);
739  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
740 
741  // Treat values of type MVT::i1 specially: they are passed in
742  // registers of type i32, but they need to remain as values of
743  // type i1 for consistency of the argument lowering.
744  if (VA.getValVT() == MVT::i1) {
745  assert(RegVT.getSizeInBits() <= 32);
746  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
747  Copy, DAG.getConstant(1, dl, RegVT));
748  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
749  ISD::SETNE);
750  } else {
751 #ifndef NDEBUG
752  unsigned RegSize = RegVT.getSizeInBits();
753  assert(RegSize == 32 || RegSize == 64 ||
754  Subtarget.isHVXVectorType(RegVT));
755 #endif
756  }
757  InVals.push_back(Copy);
758  MRI.addLiveIn(VA.getLocReg(), VReg);
759  } else {
760  assert(VA.isMemLoc() && "Argument should be passed in memory");
761 
762  // If it's a byval parameter, then we need to compute the
763  // "real" size, not the size of the pointer.
764  unsigned ObjSize = Flags.isByVal()
765  ? Flags.getByValSize()
766  : VA.getLocVT().getStoreSizeInBits() / 8;
767 
768  // Create the frame index object for this incoming parameter.
770  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
771  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
772 
773  if (Flags.isByVal()) {
774  // If it's a pass-by-value aggregate, then do not dereference the stack
775  // location. Instead, we should generate a reference to the stack
776  // location.
777  InVals.push_back(FIN);
778  } else {
779  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
781  InVals.push_back(L);
782  }
783  }
784  }
785 
786 
787  if (IsVarArg) {
788  // This will point to the next argument passed via stack.
789  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
790  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
791  HMFI.setVarArgsFrameIndex(FI);
792  }
793 
794  return Chain;
795 }
796 
797 SDValue
799  // VASTART stores the address of the VarArgsFrameIndex slot into the
800  // memory location argument.
804  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
805  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
806  MachinePointerInfo(SV));
807 }
808 
810  const SDLoc &dl(Op);
811  SDValue LHS = Op.getOperand(0);
812  SDValue RHS = Op.getOperand(1);
813  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
814  MVT ResTy = ty(Op);
815  MVT OpTy = ty(LHS);
816 
817  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
818  MVT ElemTy = OpTy.getVectorElementType();
819  assert(ElemTy.isScalarInteger());
821  OpTy.getVectorNumElements());
822  return DAG.getSetCC(dl, ResTy,
823  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
824  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
825  }
826 
827  // Treat all other vector types as legal.
828  if (ResTy.isVector())
829  return Op;
830 
831  // Comparisons of short integers should use sign-extend, not zero-extend,
832  // since we can represent small negative values in the compare instructions.
833  // The LLVM default is to use zero-extend arbitrarily in these cases.
834  auto isSExtFree = [this](SDValue N) {
835  switch (N.getOpcode()) {
836  case ISD::TRUNCATE: {
837  // A sign-extend of a truncate of a sign-extend is free.
838  SDValue Op = N.getOperand(0);
839  if (Op.getOpcode() != ISD::AssertSext)
840  return false;
841  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
842  unsigned ThisBW = ty(N).getSizeInBits();
843  unsigned OrigBW = OrigTy.getSizeInBits();
844  // The type that was sign-extended to get the AssertSext must be
845  // narrower than the type of N (so that N has still the same value
846  // as the original).
847  return ThisBW >= OrigBW;
848  }
849  case ISD::LOAD:
850  // We have sign-extended loads.
851  return true;
852  }
853  return false;
854  };
855 
856  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
858  bool IsNegative = C && C->getAPIntValue().isNegative();
859  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
860  return DAG.getSetCC(dl, ResTy,
861  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
862  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
863  }
864 
865  return SDValue();
866 }
867 
868 SDValue
870  SDValue PredOp = Op.getOperand(0);
871  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
872  EVT OpVT = Op1.getValueType();
873  SDLoc DL(Op);
874 
875  if (OpVT == MVT::v2i16) {
876  SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
877  SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
878  SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
879  SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
880  return TR;
881  }
882 
883  return SDValue();
884 }
885 
886 static Constant *convert_i1_to_i8(const Constant *ConstVal) {
888  const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
889  if (!CV)
890  return nullptr;
891 
892  LLVMContext &Ctx = ConstVal->getContext();
893  IRBuilder<> IRB(Ctx);
894  unsigned NumVectorElements = CV->getNumOperands();
895  assert(isPowerOf2_32(NumVectorElements) &&
896  "conversion only supported for pow2 VectorSize!");
897 
898  for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
899  uint8_t x = 0;
900  for (unsigned j = 0; j < 8; ++j) {
901  uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
902  x |= y << (7 - j);
903  }
904  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!");
905  NewConst.push_back(IRB.getInt8(x));
906  }
907  return ConstantVector::get(NewConst);
908 }
909 
910 SDValue
912  EVT ValTy = Op.getValueType();
913  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
914  Constant *CVal = nullptr;
915  bool isVTi1Type = false;
916  if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
917  Type *CValTy = ConstVal->getType();
918  if (CValTy->isVectorTy() &&
919  CValTy->getVectorElementType()->isIntegerTy(1)) {
920  CVal = convert_i1_to_i8(ConstVal);
921  isVTi1Type = (CVal != nullptr);
922  }
923  }
924  unsigned Align = CPN->getAlignment();
925  bool IsPositionIndependent = isPositionIndependent();
926  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
927 
928  unsigned Offset = 0;
929  SDValue T;
930  if (CPN->isMachineConstantPoolEntry())
931  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
932  TF);
933  else if (isVTi1Type)
934  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
935  else
936  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);
937 
938  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
939  "Inconsistent target flag encountered");
940 
941  if (IsPositionIndependent)
942  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
943  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
944 }
945 
946 SDValue
948  EVT VT = Op.getValueType();
949  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
950  if (isPositionIndependent()) {
952  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
953  }
954 
955  SDValue T = DAG.getTargetJumpTable(Idx, VT);
956  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
957 }
958 
959 SDValue
961  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
963  MachineFrameInfo &MFI = MF.getFrameInfo();
964  MFI.setReturnAddressIsTaken(true);
965 
966  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
967  return SDValue();
968 
969  EVT VT = Op.getValueType();
970  SDLoc dl(Op);
971  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
972  if (Depth) {
973  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
974  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
975  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
976  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
978  }
979 
980  // Return LR, which contains the return address. Mark it an implicit live-in.
981  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
982  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
983 }
984 
985 SDValue
987  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
989  MFI.setFrameAddressIsTaken(true);
990 
991  EVT VT = Op.getValueType();
992  SDLoc dl(Op);
993  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
994  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
995  HRI.getFrameRegister(), VT);
996  while (Depth--)
997  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
999  return FrameAddr;
1000 }
1001 
1002 SDValue
1004  SDLoc dl(Op);
1005  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1006 }
1007 
1008 SDValue
1010  SDLoc dl(Op);
1011  auto *GAN = cast<GlobalAddressSDNode>(Op);
1012  auto PtrVT = getPointerTy(DAG.getDataLayout());
1013  auto *GV = GAN->getGlobal();
1014  int64_t Offset = GAN->getOffset();
1015 
1016  auto &HLOF = *HTM.getObjFileLowering();
1017  Reloc::Model RM = HTM.getRelocationModel();
1018 
1019  if (RM == Reloc::Static) {
1020  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1021  const GlobalObject *GO = GV->getBaseObject();
1022  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1023  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1024  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1025  }
1026 
1027  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1028  if (UsePCRel) {
1029  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1031  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1032  }
1033 
1034  // Use GOT index.
1035  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1036  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1037  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1038  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1039 }
1040 
1041 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1042 SDValue
1044  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1045  SDLoc dl(Op);
1046  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1047 
1048  Reloc::Model RM = HTM.getRelocationModel();
1049  if (RM == Reloc::Static) {
1050  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1051  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1052  }
1053 
1054  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1055  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1056 }
1057 
1058 SDValue
1060  const {
1061  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1064  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1065 }
1066 
1067 SDValue
1069  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1070  unsigned char OperandFlags) const {
1071  MachineFunction &MF = DAG.getMachineFunction();
1072  MachineFrameInfo &MFI = MF.getFrameInfo();
1073  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1074  SDLoc dl(GA);
1075  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1076  GA->getValueType(0),
1077  GA->getOffset(),
1078  OperandFlags);
1079  // Create Operands for the call.The Operands should have the following:
1080  // 1. Chain SDValue
1081  // 2. Callee which in this case is the Global address value.
1082  // 3. Registers live into the call.In this case its R0, as we
1083  // have just one argument to be passed.
1084  // 4. Glue.
1085  // Note: The order is important.
1086 
1087  const auto &HRI = *Subtarget.getRegisterInfo();
1088  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1089  assert(Mask && "Missing call preserved mask for calling convention");
1090  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1091  DAG.getRegisterMask(Mask), Glue };
1092  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1093 
1094  // Inform MFI that function has calls.
1095  MFI.setAdjustsStack(true);
1096 
1097  Glue = Chain.getValue(1);
1098  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1099 }
1100 
1101 //
1102 // Lower using the intial executable model for TLS addresses
1103 //
1104 SDValue
1106  SelectionDAG &DAG) const {
1107  SDLoc dl(GA);
1108  int64_t Offset = GA->getOffset();
1109  auto PtrVT = getPointerTy(DAG.getDataLayout());
1110 
1111  // Get the thread pointer.
1112  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1113 
1114  bool IsPositionIndependent = isPositionIndependent();
1115  unsigned char TF =
1116  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1117 
1118  // First generate the TLS symbol address
1119  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1120  Offset, TF);
1121 
1122  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1123 
1124  if (IsPositionIndependent) {
1125  // Generate the GOT pointer in case of position independent code
1126  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1127 
1128  // Add the TLS Symbol address to GOT pointer.This gives
1129  // GOT relative relocation for the symbol.
1130  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1131  }
1132 
1133  // Load the offset value for TLS symbol.This offset is relative to
1134  // thread pointer.
1135  SDValue LoadOffset =
1136  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1137 
1138  // Address of the thread local variable is the add of thread
1139  // pointer and the offset of the variable.
1140  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1141 }
1142 
1143 //
1144 // Lower using the local executable model for TLS addresses
1145 //
1146 SDValue
1148  SelectionDAG &DAG) const {
1149  SDLoc dl(GA);
1150  int64_t Offset = GA->getOffset();
1151  auto PtrVT = getPointerTy(DAG.getDataLayout());
1152 
1153  // Get the thread pointer.
1154  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1155  // Generate the TLS symbol address
1156  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1158  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1159 
1160  // Address of the thread local variable is the add of thread
1161  // pointer and the offset of the variable.
1162  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1163 }
1164 
1165 //
1166 // Lower using the general dynamic model for TLS addresses
1167 //
1168 SDValue
1170  SelectionDAG &DAG) const {
1171  SDLoc dl(GA);
1172  int64_t Offset = GA->getOffset();
1173  auto PtrVT = getPointerTy(DAG.getDataLayout());
1174 
1175  // First generate the TLS symbol address
1176  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1178 
1179  // Then, generate the GOT pointer
1180  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1181 
1182  // Add the TLS symbol and the GOT pointer
1183  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1184  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1185 
1186  // Copy over the argument to R0
1187  SDValue InFlag;
1188  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1189  InFlag = Chain.getValue(1);
1190 
1191  unsigned Flags =
1192  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1195 
1196  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1197  Hexagon::R0, Flags);
1198 }
1199 
1200 //
1201 // Lower TLS addresses.
1202 //
1203 // For now for dynamic models, we only support the general dynamic model.
1204 //
1205 SDValue
1207  SelectionDAG &DAG) const {
1208  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1209 
1210  switch (HTM.getTLSModel(GA->getGlobal())) {
1213  return LowerToTLSGeneralDynamicModel(GA, DAG);
1214  case TLSModel::InitialExec:
1215  return LowerToTLSInitialExecModel(GA, DAG);
1216  case TLSModel::LocalExec:
1217  return LowerToTLSLocalExecModel(GA, DAG);
1218  }
1219  llvm_unreachable("Bogus TLS model");
1220 }
1221 
1222 //===----------------------------------------------------------------------===//
1223 // TargetLowering Implementation
1224 //===----------------------------------------------------------------------===//
1225 
1227  const HexagonSubtarget &ST)
1228  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1229  Subtarget(ST) {
1230  auto &HRI = *Subtarget.getRegisterInfo();
1231 
1235  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1238 
1241 
1244  else
1246 
1247  // Limits for inline expansion of memcpy/memmove
1254 
1255  //
1256  // Set up register classes.
1257  //
1258 
1259  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1260  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1261  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1262  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1263  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1264  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1265  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1266  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1267  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1268  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1269  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1270 
1271  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1272  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1273 
1274  //
1275  // Handling of scalar operations.
1276  //
1277  // All operations default to "legal", except:
1278  // - indexed loads and stores (pre-/post-incremented),
1279  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1280  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1281  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1282  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1283  // which default to "expand" for at least one type.
1284 
1285  // Misc operations.
1301 
1302  // Custom legalize GlobalAddress nodes into CONST32.
1306 
1307  // Hexagon needs to optimize cases with negative constants.
1312 
1313  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1318 
1322 
1323  if (EmitJumpTables)
1325  else
1328 
1331 
1332  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1333  // but they only operate on i64.
1334  for (MVT VT : MVT::integer_valuetypes()) {
1341  }
1344 
1349 
1350  // Popcount can count # of 1s in i64 but returns i32.
1355 
1360 
1365 
1366  for (unsigned IntExpOp :
1371  for (MVT VT : MVT::integer_valuetypes())
1372  setOperationAction(IntExpOp, VT, Expand);
1373  }
1374 
1375  for (unsigned FPExpOp :
1378  for (MVT VT : MVT::fp_valuetypes())
1379  setOperationAction(FPExpOp, VT, Expand);
1380  }
1381 
1382  // No extending loads from i32.
1383  for (MVT VT : MVT::integer_valuetypes()) {
1387  }
1388  // Turn FP truncstore into trunc + store.
1390  // Turn FP extload into load/fpextend.
1391  for (MVT VT : MVT::fp_valuetypes())
1393 
1394  // Expand BR_CC and SELECT_CC for all integer and fp types.
1395  for (MVT VT : MVT::integer_valuetypes()) {
1398  }
1399  for (MVT VT : MVT::fp_valuetypes()) {
1402  }
1404 
1405  //
1406  // Handling of vector operations.
1407  //
1408 
1409  // Set the action for vector operations to "expand", then override it with
1410  // either "custom" or "legal" for specific cases.
1411  static const unsigned VectExpOps[] = {
1412  // Integer arithmetic:
1416  // Logical/bit:
1419  // Floating point arithmetic/math functions:
1426  // Misc:
1428  // Vector:
1433  };
1434 
1435  for (MVT VT : MVT::vector_valuetypes()) {
1436  for (unsigned VectExpOp : VectExpOps)
1437  setOperationAction(VectExpOp, VT, Expand);
1438 
1439  // Expand all extending loads and truncating stores:
1440  for (MVT TargetVT : MVT::vector_valuetypes()) {
1441  if (TargetVT == VT)
1442  continue;
1443  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1444  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1445  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1446  setTruncStoreAction(VT, TargetVT, Expand);
1447  }
1448 
1449  // Normalize all inputs to SELECT to be vectors of i32.
1450  if (VT.getVectorElementType() != MVT::i32) {
1451  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1453  AddPromotedToType(ISD::SELECT, VT, VT32);
1454  }
1458  }
1459 
1460  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1461  // are legal.
1468 
1469  // Types natively supported:
1470  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1478 
1479  setOperationAction(ISD::ADD, NativeVT, Legal);
1480  setOperationAction(ISD::SUB, NativeVT, Legal);
1481  setOperationAction(ISD::MUL, NativeVT, Legal);
1482  setOperationAction(ISD::AND, NativeVT, Legal);
1483  setOperationAction(ISD::OR, NativeVT, Legal);
1484  setOperationAction(ISD::XOR, NativeVT, Legal);
1485  }
1486 
1487  // Custom lower unaligned loads.
1488  // Also, for both loads and stores, verify the alignment of the address
1489  // in case it is a compile-time constant. This is a usability feature to
1490  // provide a meaningful error message to users.
1495  }
1496 
1497  for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v2i32, MVT::v4i16, MVT::v2i32}) {
1502  }
1503 
1504  // Custom-lower bitcasts from i8 to v8i1.
1508  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1509  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1510  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1511 
1512  // V5+.
1517 
1520 
1533 
1534  // Handling of indexed loads/stores: default is "expand".
1535  //
1540  }
1541 
1542  // Subtarget-specific operation actions.
1543  //
1544  if (Subtarget.hasV60Ops()) {
1549  }
1550  if (Subtarget.hasV66Ops()) {
1553  }
1554 
1555  if (Subtarget.useHVXOps())
1556  initializeHVXLowering();
1557 
1559 
1560  //
1561  // Library calls for unsupported operations
1562  //
1563  bool FastMath = EnableFastMath;
1564 
1565  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1566  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1567  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1568  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1569  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1570  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1571  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1572  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1573 
1574  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1575  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1576  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1577  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1578  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1579  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1580 
1581  // This is the only fast library function for sqrtd.
1582  if (FastMath)
1583  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1584 
1585  // Prefix is: nothing for "slow-math",
1586  // "fast2_" for V5+ fast-math double-precision
1587  // (actually, keep fast-math and fast-math2 separate for now)
1588  if (FastMath) {
1589  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1590  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1591  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1592  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1593  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1594  } else {
1595  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1596  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1597  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1598  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1599  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1600  }
1601 
1602  if (FastMath)
1603  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1604  else
1605  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1606 
1607  // These cause problems when the shift amount is non-constant.
1608  setLibcallName(RTLIB::SHL_I128, nullptr);
1609  setLibcallName(RTLIB::SRL_I128, nullptr);
1610  setLibcallName(RTLIB::SRA_I128, nullptr);
1611 }
1612 
1613 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1614  switch ((HexagonISD::NodeType)Opcode) {
1615  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1616  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1617  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1618  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1619  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1620  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1621  case HexagonISD::CALL: return "HexagonISD::CALL";
1622  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1623  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1624  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1625  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1626  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1627  case HexagonISD::CP: return "HexagonISD::CP";
1628  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1629  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1630  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1631  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1632  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1633  case HexagonISD::JT: return "HexagonISD::JT";
1634  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1635  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1636  case HexagonISD::VASL: return "HexagonISD::VASL";
1637  case HexagonISD::VASR: return "HexagonISD::VASR";
1638  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1639  case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
1640  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1641  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1642  case HexagonISD::VROR: return "HexagonISD::VROR";
1643  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1644  case HexagonISD::VZERO: return "HexagonISD::VZERO";
1645  case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW";
1646  case HexagonISD::D2P: return "HexagonISD::D2P";
1647  case HexagonISD::P2D: return "HexagonISD::P2D";
1648  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1649  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1650  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1651  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1652  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1653  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1654  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1655  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1656  case HexagonISD::OP_END: break;
1657  }
1658  return nullptr;
1659 }
1660 
1661 void
1662 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
1663  unsigned NeedAlign) const {
1664  auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1665  if (!CA)
1666  return;
1667  unsigned Addr = CA->getZExtValue();
1668  unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
1669  if (HaveAlign < NeedAlign) {
1670  std::string ErrMsg;
1671  raw_string_ostream O(ErrMsg);
1672  O << "Misaligned constant address: " << format_hex(Addr, 10)
1673  << " has alignment " << HaveAlign
1674  << ", but the memory access requires " << NeedAlign;
1675  if (DebugLoc DL = dl.getDebugLoc())
1676  DL.print(O << ", at ");
1677  report_fatal_error(O.str());
1678  }
1679 }
1680 
1681 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1682 // intrinsic.
1683 static bool isBrevLdIntrinsic(const Value *Inst) {
1684  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1685  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1686  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1687  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1688  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1689  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1690  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1691 }
1692 
1693 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1694 // instruction. So far we only handle bitcast, extract value and bit reverse
1695 // load intrinsic instructions. Should we handle CGEP ?
1697  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1698  Operator::getOpcode(V) == Instruction::BitCast)
1699  V = cast<Operator>(V)->getOperand(0);
1700  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1701  V = cast<Instruction>(V)->getOperand(0);
1702  return V;
1703 }
1704 
1705 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1706 // a back edge. If the back edge comes from the intrinsic itself, the incoming
1707 // edge is returned.
1708 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1709  const BasicBlock *Parent = PN->getParent();
1710  int Idx = -1;
1711  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1712  BasicBlock *Blk = PN->getIncomingBlock(i);
1713  // Determine if the back edge is originated from intrinsic.
1714  if (Blk == Parent) {
1715  Value *BackEdgeVal = PN->getIncomingValue(i);
1716  Value *BaseVal;
1717  // Loop over till we return the same Value or we hit the IntrBaseVal.
1718  do {
1719  BaseVal = BackEdgeVal;
1720  BackEdgeVal = getBrevLdObject(BackEdgeVal);
1721  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1722  // If the getBrevLdObject returns IntrBaseVal, we should return the
1723  // incoming edge.
1724  if (IntrBaseVal == BackEdgeVal)
1725  continue;
1726  Idx = i;
1727  break;
1728  } else // Set the node to incoming edge.
1729  Idx = i;
1730  }
1731  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
1732  return PN->getIncomingValue(Idx);
1733 }
1734 
1735 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
1736 // pointer points to, for the bit-reverse load intrinsic. Setting this to
1737 // memoperand might help alias analysis to figure out the dependencies.
1739  Value *IntrBaseVal = V;
1740  Value *BaseVal;
1741  // Loop over till we return the same Value, implies we either figure out
1742  // the object or we hit a PHI
1743  do {
1744  BaseVal = V;
1745  V = getBrevLdObject(V);
1746  } while (BaseVal != V);
1747 
1748  // Identify the object from PHINode.
1749  if (const PHINode *PN = dyn_cast<PHINode>(V))
1750  return returnEdge(PN, IntrBaseVal);
1751  // For non PHI nodes, the object is the last value returned by getBrevLdObject
1752  else
1753  return V;
1754 }
1755 
1756 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1757 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1758 /// true and store the intrinsic information into the IntrinsicInfo that was
1759 /// passed to the function.
1761  const CallInst &I,
1762  MachineFunction &MF,
1763  unsigned Intrinsic) const {
1764  switch (Intrinsic) {
1765  case Intrinsic::hexagon_L2_loadrd_pbr:
1766  case Intrinsic::hexagon_L2_loadri_pbr:
1767  case Intrinsic::hexagon_L2_loadrh_pbr:
1768  case Intrinsic::hexagon_L2_loadruh_pbr:
1769  case Intrinsic::hexagon_L2_loadrb_pbr:
1770  case Intrinsic::hexagon_L2_loadrub_pbr: {
1771  Info.opc = ISD::INTRINSIC_W_CHAIN;
1772  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1773  auto &Cont = I.getCalledFunction()->getParent()->getContext();
1774  // The intrinsic function call is of the form { ElTy, i8* }
1775  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
1776  // should be derived from ElTy.
1778  Info.memVT = MVT::getVT(ElTy);
1779  llvm::Value *BasePtrVal = I.getOperand(0);
1780  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
1781  // The offset value comes through Modifier register. For now, assume the
1782  // offset is 0.
1783  Info.offset = 0;
1784  Info.align = DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont));
1786  return true;
1787  }
1788  case Intrinsic::hexagon_V6_vgathermw:
1789  case Intrinsic::hexagon_V6_vgathermw_128B:
1790  case Intrinsic::hexagon_V6_vgathermh:
1791  case Intrinsic::hexagon_V6_vgathermh_128B:
1792  case Intrinsic::hexagon_V6_vgathermhw:
1793  case Intrinsic::hexagon_V6_vgathermhw_128B:
1794  case Intrinsic::hexagon_V6_vgathermwq:
1795  case Intrinsic::hexagon_V6_vgathermwq_128B:
1796  case Intrinsic::hexagon_V6_vgathermhq:
1797  case Intrinsic::hexagon_V6_vgathermhq_128B:
1798  case Intrinsic::hexagon_V6_vgathermhwq:
1799  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
1800  const Module &M = *I.getParent()->getParent()->getParent();
1801  Info.opc = ISD::INTRINSIC_W_CHAIN;
1802  Type *VecTy = I.getArgOperand(1)->getType();
1803  Info.memVT = MVT::getVT(VecTy);
1804  Info.ptrVal = I.getArgOperand(0);
1805  Info.offset = 0;
1806  Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
1810  return true;
1811  }
1812  default:
1813  break;
1814  }
1815  return false;
1816 }
1817 
1819  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1820 }
1821 
1823  if (!VT1.isSimple() || !VT2.isSimple())
1824  return false;
1825  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1826 }
1827 
1829  return isOperationLegalOrCustom(ISD::FMA, VT);
1830 }
1831 
1832 // Should we expand the build vector with shuffles?
1834  unsigned DefinedValues) const {
1835  return false;
1836 }
1837 
1839  EVT VT) const {
1840  return true;
1841 }
1842 
1845  if (VT.getVectorNumElements() == 1)
1847 
1848  // Always widen vectors of i1.
1849  MVT ElemTy = VT.getVectorElementType();
1850  if (ElemTy == MVT::i1)
1852 
1853  if (Subtarget.useHVXOps()) {
1854  // If the size of VT is at least half of the vector length,
1855  // widen the vector. Note: the threshold was not selected in
1856  // any scientific way.
1857  ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
1858  if (llvm::find(Tys, ElemTy) != Tys.end()) {
1859  unsigned HwWidth = 8*Subtarget.getVectorLength();
1860  unsigned VecWidth = VT.getSizeInBits();
1861  if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
1863  }
1864  }
1866 }
1867 
1868 std::pair<SDValue, int>
1869 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
1870  if (Addr.getOpcode() == ISD::ADD) {
1871  SDValue Op1 = Addr.getOperand(1);
1872  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
1873  return { Addr.getOperand(0), CN->getSExtValue() };
1874  }
1875  return { Addr, 0 };
1876 }
1877 
1878 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
1879 // to select data from, V3 is the permutation.
1880 SDValue
1882  const {
1883  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
1884  ArrayRef<int> AM = SVN->getMask();
1885  assert(AM.size() <= 8 && "Unexpected shuffle mask");
1886  unsigned VecLen = AM.size();
1887 
1888  MVT VecTy = ty(Op);
1889  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
1890  "HVX shuffles should be legal");
1891  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
1892 
1893  SDValue Op0 = Op.getOperand(0);
1894  SDValue Op1 = Op.getOperand(1);
1895  const SDLoc &dl(Op);
1896 
1897  // If the inputs are not the same as the output, bail. This is not an
1898  // error situation, but complicates the handling and the default expansion
1899  // (into BUILD_VECTOR) should be adequate.
1900  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
1901  return SDValue();
1902 
1903  // Normalize the mask so that the first non-negative index comes from
1904  // the first operand.
1905  SmallVector<int,8> Mask(AM.begin(), AM.end());
1906  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
1907  if (F == AM.size())
1908  return DAG.getUNDEF(VecTy);
1909  if (AM[F] >= int(VecLen)) {
1911  std::swap(Op0, Op1);
1912  }
1913 
1914  // Express the shuffle mask in terms of bytes.
1915  SmallVector<int,8> ByteMask;
1916  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
1917  for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
1918  int M = Mask[i];
1919  if (M < 0) {
1920  for (unsigned j = 0; j != ElemBytes; ++j)
1921  ByteMask.push_back(-1);
1922  } else {
1923  for (unsigned j = 0; j != ElemBytes; ++j)
1924  ByteMask.push_back(M*ElemBytes + j);
1925  }
1926  }
1927  assert(ByteMask.size() <= 8);
1928 
1929  // All non-undef (non-negative) indexes are well within [0..127], so they
1930  // fit in a single byte. Build two 64-bit words:
1931  // - MaskIdx where each byte is the corresponding index (for non-negative
1932  // indexes), and 0xFF for negative indexes, and
1933  // - MaskUnd that has 0xFF for each negative index.
1934  uint64_t MaskIdx = 0;
1935  uint64_t MaskUnd = 0;
1936  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
1937  unsigned S = 8*i;
1938  uint64_t M = ByteMask[i] & 0xFF;
1939  if (M == 0xFF)
1940  MaskUnd |= M << S;
1941  MaskIdx |= M << S;
1942  }
1943 
1944  if (ByteMask.size() == 4) {
1945  // Identity.
1946  if (MaskIdx == (0x03020100 | MaskUnd))
1947  return Op0;
1948  // Byte swap.
1949  if (MaskIdx == (0x00010203 | MaskUnd)) {
1950  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
1951  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
1952  return DAG.getBitcast(VecTy, T1);
1953  }
1954 
1955  // Byte packs.
1956  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
1957  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
1958  if (MaskIdx == (0x06040200 | MaskUnd))
1959  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
1960  if (MaskIdx == (0x07050301 | MaskUnd))
1961  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
1962 
1963  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
1964  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
1965  if (MaskIdx == (0x02000604 | MaskUnd))
1966  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
1967  if (MaskIdx == (0x03010705 | MaskUnd))
1968  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
1969  }
1970 
1971  if (ByteMask.size() == 8) {
1972  // Identity.
1973  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
1974  return Op0;
1975  // Byte swap.
1976  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
1977  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
1978  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
1979  return DAG.getBitcast(VecTy, T1);
1980  }
1981 
1982  // Halfword picks.
1983  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
1984  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
1985  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
1986  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
1987  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
1988  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
1989  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
1990  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
1991  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
1992  VectorPair P = opSplit(Op0, dl, DAG);
1993  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
1994  }
1995 
1996  // Byte packs.
1997  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
1998  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
1999  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2000  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2001  }
2002 
2003  return SDValue();
2004 }
2005 
2006 // Create a Hexagon-specific node for shifting a vector by an integer.
2007 SDValue
2008 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2009  const {
2010  if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
2011  if (SDValue S = BVN->getSplatValue()) {
2012  unsigned NewOpc;
2013  switch (Op.getOpcode()) {
2014  case ISD::SHL:
2015  NewOpc = HexagonISD::VASL;
2016  break;
2017  case ISD::SRA:
2018  NewOpc = HexagonISD::VASR;
2019  break;
2020  case ISD::SRL:
2021  NewOpc = HexagonISD::VLSR;
2022  break;
2023  default:
2024  llvm_unreachable("Unexpected shift opcode");
2025  }
2026  return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
2027  }
2028  }
2029 
2030  return SDValue();
2031 }
2032 
2033 SDValue
2035  return getVectorShiftByInt(Op, DAG);
2036 }
2037 
2038 SDValue
2040  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2041  return Op;
2042  return SDValue();
2043 }
2044 
2045 SDValue
2047  MVT ResTy = ty(Op);
2048  SDValue InpV = Op.getOperand(0);
2049  MVT InpTy = ty(InpV);
2050  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2051  const SDLoc &dl(Op);
2052 
2053  // Handle conversion from i8 to v8i1.
2054  if (ResTy == MVT::v8i1) {
2055  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2056  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2057  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2058  }
2059 
2060  return SDValue();
2061 }
2062 
2063 bool
2064 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2065  MVT VecTy, SelectionDAG &DAG,
2066  MutableArrayRef<ConstantInt*> Consts) const {
2067  MVT ElemTy = VecTy.getVectorElementType();
2068  unsigned ElemWidth = ElemTy.getSizeInBits();
2069  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2070  bool AllConst = true;
2071 
2072  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2073  SDValue V = Values[i];
2074  if (V.isUndef()) {
2075  Consts[i] = ConstantInt::get(IntTy, 0);
2076  continue;
2077  }
2078  // Make sure to always cast to IntTy.
2079  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2080  const ConstantInt *CI = CN->getConstantIntValue();
2081  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2082  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2083  const ConstantFP *CF = CN->getConstantFPValue();
2084  APInt A = CF->getValueAPF().bitcastToAPInt();
2085  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2086  } else {
2087  AllConst = false;
2088  }
2089  }
2090  return AllConst;
2091 }
2092 
2093 SDValue
2094 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2095  MVT VecTy, SelectionDAG &DAG) const {
2096  MVT ElemTy = VecTy.getVectorElementType();
2097  assert(VecTy.getVectorNumElements() == Elem.size());
2098 
2099  SmallVector<ConstantInt*,4> Consts(Elem.size());
2100  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2101 
2102  unsigned First, Num = Elem.size();
2103  for (First = 0; First != Num; ++First)
2104  if (!isUndef(Elem[First]))
2105  break;
2106  if (First == Num)
2107  return DAG.getUNDEF(VecTy);
2108 
2109  if (AllConst &&
2110  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2111  return getZero(dl, VecTy, DAG);
2112 
2113  if (ElemTy == MVT::i16) {
2114  assert(Elem.size() == 2);
2115  if (AllConst) {
2116  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2117  Consts[1]->getZExtValue() << 16;
2118  return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2119  }
2120  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2121  {Elem[1], Elem[0]}, DAG);
2122  return DAG.getBitcast(MVT::v2i16, N);
2123  }
2124 
2125  if (ElemTy == MVT::i8) {
2126  // First try generating a constant.
2127  if (AllConst) {
2128  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2129  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2130  (Consts[1]->getZExtValue() & 0xFF) << 16 |
2131  Consts[2]->getZExtValue() << 24;
2132  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2133  }
2134 
2135  // Then try splat.
2136  bool IsSplat = true;
2137  for (unsigned i = 0; i != Num; ++i) {
2138  if (i == First)
2139  continue;
2140  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2141  continue;
2142  IsSplat = false;
2143  break;
2144  }
2145  if (IsSplat) {
2146  // Legalize the operand to VSPLAT.
2147  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2148  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2149  }
2150 
2151  // Generate
2152  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2153  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2154  assert(Elem.size() == 4);
2155  SDValue Vs[4];
2156  for (unsigned i = 0; i != 4; ++i) {
2157  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2158  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2159  }
2160  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2161  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2162  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2163  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2164  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2165 
2166  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2167  return DAG.getBitcast(MVT::v4i8, R);
2168  }
2169 
2170 #ifndef NDEBUG
2171  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2172 #endif
2173  llvm_unreachable("Unexpected vector element type");
2174 }
2175 
2176 SDValue
2177 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2178  MVT VecTy, SelectionDAG &DAG) const {
2179  MVT ElemTy = VecTy.getVectorElementType();
2180  assert(VecTy.getVectorNumElements() == Elem.size());
2181 
2182  SmallVector<ConstantInt*,8> Consts(Elem.size());
2183  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2184 
2185  unsigned First, Num = Elem.size();
2186  for (First = 0; First != Num; ++First)
2187  if (!isUndef(Elem[First]))
2188  break;
2189  if (First == Num)
2190  return DAG.getUNDEF(VecTy);
2191 
2192  if (AllConst &&
2193  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2194  return getZero(dl, VecTy, DAG);
2195 
2196  // First try splat if possible.
2197  if (ElemTy == MVT::i16) {
2198  bool IsSplat = true;
2199  for (unsigned i = 0; i != Num; ++i) {
2200  if (i == First)
2201  continue;
2202  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2203  continue;
2204  IsSplat = false;
2205  break;
2206  }
2207  if (IsSplat) {
2208  // Legalize the operand to VSPLAT.
2209  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2210  return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2211  }
2212  }
2213 
2214  // Then try constant.
2215  if (AllConst) {
2216  uint64_t Val = 0;
2217  unsigned W = ElemTy.getSizeInBits();
2218  uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2219  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2220  for (unsigned i = 0; i != Num; ++i)
2221  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2222  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2223  return DAG.getBitcast(VecTy, V0);
2224  }
2225 
2226  // Build two 32-bit vectors and concatenate.
2227  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2228  SDValue L = (ElemTy == MVT::i32)
2229  ? Elem[0]
2230  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2231  SDValue H = (ElemTy == MVT::i32)
2232  ? Elem[1]
2233  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2234  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2235 }
2236 
2237 SDValue
2238 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2239  const SDLoc &dl, MVT ValTy, MVT ResTy,
2240  SelectionDAG &DAG) const {
2241  MVT VecTy = ty(VecV);
2242  assert(!ValTy.isVector() ||
2243  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2244  unsigned VecWidth = VecTy.getSizeInBits();
2245  unsigned ValWidth = ValTy.getSizeInBits();
2246  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2247  assert((VecWidth % ElemWidth) == 0);
2248  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2249 
2250  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2251  // without any coprocessors).
2252  if (ElemWidth == 1) {
2253  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
2254  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2255  // Check if this is an extract of the lowest bit.
2256  if (IdxN) {
2257  // Extracting the lowest bit is a no-op, but it changes the type,
2258  // so it must be kept as an operation to avoid errors related to
2259  // type mismatches.
2260  if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2261  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2262  }
2263 
2264  // If the value extracted is a single bit, use tstbit.
2265  if (ValWidth == 1) {
2266  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2267  SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2268  SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2269  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2270  }
2271 
2272  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2273  // a predicate register. The elements of the vector are repeated
2274  // in the register (if necessary) so that the total number is 8.
2275  // The extracted subvector will need to be expanded in such a way.
2276  unsigned Scale = VecWidth / ValWidth;
2277 
2278  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2279  // position 0.
2280  assert(ty(IdxV) == MVT::i32);
2281  unsigned VecRep = 8 / VecWidth;
2282  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2283  DAG.getConstant(8*VecRep, dl, MVT::i32));
2284  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2285  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2286  while (Scale > 1) {
2287  // The longest possible subvector is at most 32 bits, so it is always
2288  // contained in the low subregister.
2289  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2290  T1 = expandPredicate(T1, dl, DAG);
2291  Scale /= 2;
2292  }
2293 
2294  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2295  }
2296 
2297  assert(VecWidth == 32 || VecWidth == 64);
2298 
2299  // Cast everything to scalar integer types.
2300  MVT ScalarTy = tyScalar(VecTy);
2301  VecV = DAG.getBitcast(ScalarTy, VecV);
2302 
2303  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2304  SDValue ExtV;
2305 
2306  if (IdxN) {
2307  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2308  if (VecWidth == 64 && ValWidth == 32) {
2309  assert(Off == 0 || Off == 32);
2310  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2311  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2312  } else if (Off == 0 && (ValWidth % 8) == 0) {
2313  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2314  } else {
2315  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2316  // The return type of EXTRACTU must be the same as the type of the
2317  // input vector.
2318  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2319  {VecV, WidthV, OffV});
2320  }
2321  } else {
2322  if (ty(IdxV) != MVT::i32)
2323  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2324  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2325  DAG.getConstant(ElemWidth, dl, MVT::i32));
2326  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2327  {VecV, WidthV, OffV});
2328  }
2329 
2330  // Cast ExtV to the requested result type.
2331  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2332  ExtV = DAG.getBitcast(ResTy, ExtV);
2333  return ExtV;
2334 }
2335 
2336 SDValue
2337 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2338  const SDLoc &dl, MVT ValTy,
2339  SelectionDAG &DAG) const {
2340  MVT VecTy = ty(VecV);
2341  if (VecTy.getVectorElementType() == MVT::i1) {
2342  MVT ValTy = ty(ValV);
2343  assert(ValTy.getVectorElementType() == MVT::i1);
2344  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2345  unsigned VecLen = VecTy.getVectorNumElements();
2346  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2347  assert(Scale > 1);
2348 
2349  for (unsigned R = Scale; R > 1; R /= 2) {
2350  ValR = contractPredicate(ValR, dl, DAG);
2351  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2352  DAG.getUNDEF(MVT::i32), ValR);
2353  }
2354  // The longest possible subvector is at most 32 bits, so it is always
2355  // contained in the low subregister.
2356  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2357 
2358  unsigned ValBytes = 64 / Scale;
2359  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2360  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2361  DAG.getConstant(8, dl, MVT::i32));
2362  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2364  {VecR, ValR, Width, Idx});
2365  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2366  }
2367 
2368  unsigned VecWidth = VecTy.getSizeInBits();
2369  unsigned ValWidth = ValTy.getSizeInBits();
2370  assert(VecWidth == 32 || VecWidth == 64);
2371  assert((VecWidth % ValWidth) == 0);
2372 
2373  // Cast everything to scalar integer types.
2374  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2375  // The actual type of ValV may be different than ValTy (which is related
2376  // to the vector type).
2377  unsigned VW = ty(ValV).getSizeInBits();
2378  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2379  VecV = DAG.getBitcast(ScalarTy, VecV);
2380  if (VW != VecWidth)
2381  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2382 
2383  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2384  SDValue InsV;
2385 
2386  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2387  unsigned W = C->getZExtValue() * ValWidth;
2388  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2389  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2390  {VecV, ValV, WidthV, OffV});
2391  } else {
2392  if (ty(IdxV) != MVT::i32)
2393  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2394  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2395  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2396  {VecV, ValV, WidthV, OffV});
2397  }
2398 
2399  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2400 }
2401 
2402 SDValue
2403 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2404  SelectionDAG &DAG) const {
2405  assert(ty(Vec32).getSizeInBits() == 32);
2406  if (isUndef(Vec32))
2407  return DAG.getUNDEF(MVT::i64);
2408  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2409 }
2410 
2411 SDValue
2412 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2413  SelectionDAG &DAG) const {
2414  assert(ty(Vec64).getSizeInBits() == 64);
2415  if (isUndef(Vec64))
2416  return DAG.getUNDEF(MVT::i32);
2417  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2418 }
2419 
2420 SDValue
2421 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2422  const {
2423  if (Ty.isVector()) {
2424  assert(Ty.isInteger() && "Only integer vectors are supported here");
2425  unsigned W = Ty.getSizeInBits();
2426  if (W <= 64)
2427  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2428  return DAG.getNode(HexagonISD::VZERO, dl, Ty);
2429  }
2430 
2431  if (Ty.isInteger())
2432  return DAG.getConstant(0, dl, Ty);
2433  if (Ty.isFloatingPoint())
2434  return DAG.getConstantFP(0.0, dl, Ty);
2435  llvm_unreachable("Invalid type for zero");
2436 }
2437 
2438 SDValue
2440  MVT VecTy = ty(Op);
2441  unsigned BW = VecTy.getSizeInBits();
2442  const SDLoc &dl(Op);
2444  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2445  Ops.push_back(Op.getOperand(i));
2446 
2447  if (BW == 32)
2448  return buildVector32(Ops, dl, VecTy, DAG);
2449  if (BW == 64)
2450  return buildVector64(Ops, dl, VecTy, DAG);
2451 
2452  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2453  // For each i1 element in the resulting predicate register, put 1
2454  // shifted by the index of the element into a general-purpose register,
2455  // then or them together and transfer it back into a predicate register.
2456  SDValue Rs[8];
2457  SDValue Z = getZero(dl, MVT::i32, DAG);
2458  // Always produce 8 bits, repeat inputs if necessary.
2459  unsigned Rep = 8 / VecTy.getVectorNumElements();
2460  for (unsigned i = 0; i != 8; ++i) {
2461  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2462  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2463  }
2464  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2465  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2466  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2467  }
2468  // Move the value directly to a predicate register.
2469  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2470  }
2471 
2472  return SDValue();
2473 }
2474 
2475 SDValue
2477  SelectionDAG &DAG) const {
2478  MVT VecTy = ty(Op);
2479  const SDLoc &dl(Op);
2480  if (VecTy.getSizeInBits() == 64) {
2481  assert(Op.getNumOperands() == 2);
2482  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2483  Op.getOperand(0));
2484  }
2485 
2486  MVT ElemTy = VecTy.getVectorElementType();
2487  if (ElemTy == MVT::i1) {
2488  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2489  MVT OpTy = ty(Op.getOperand(0));
2490  // Scale is how many times the operands need to be contracted to match
2491  // the representation in the target register.
2492  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2493  assert(Scale == Op.getNumOperands() && Scale > 1);
2494 
2495  // First, convert all bool vectors to integers, then generate pairwise
2496  // inserts to form values of doubled length. Up until there are only
2497  // two values left to concatenate, all of these values will fit in a
2498  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2499  SmallVector<SDValue,4> Words[2];
2500  unsigned IdxW = 0;
2501 
2502  for (SDValue P : Op.getNode()->op_values()) {
2503  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2504  for (unsigned R = Scale; R > 1; R /= 2) {
2505  W = contractPredicate(W, dl, DAG);
2506  W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2507  DAG.getUNDEF(MVT::i32), W);
2508  }
2509  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2510  Words[IdxW].push_back(W);
2511  }
2512 
2513  while (Scale > 2) {
2514  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2515  Words[IdxW ^ 1].clear();
2516 
2517  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2518  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2519  // Insert W1 into W0 right next to the significant bits of W0.
2521  {W0, W1, WidthV, WidthV});
2522  Words[IdxW ^ 1].push_back(T);
2523  }
2524  IdxW ^= 1;
2525  Scale /= 2;
2526  }
2527 
2528  // Another sanity check. At this point there should only be two words
2529  // left, and Scale should be 2.
2530  assert(Scale == 2 && Words[IdxW].size() == 2);
2531 
2533  Words[IdxW][1], Words[IdxW][0]);
2534  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2535  }
2536 
2537  return SDValue();
2538 }
2539 
2540 SDValue
2542  SelectionDAG &DAG) const {
2543  SDValue Vec = Op.getOperand(0);
2544  MVT ElemTy = ty(Vec).getVectorElementType();
2545  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2546 }
2547 
2548 SDValue
2550  SelectionDAG &DAG) const {
2551  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2552  ty(Op), ty(Op), DAG);
2553 }
2554 
2555 SDValue
2557  SelectionDAG &DAG) const {
2558  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2559  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2560 }
2561 
2562 SDValue
2564  SelectionDAG &DAG) const {
2565  SDValue ValV = Op.getOperand(1);
2566  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2567  SDLoc(Op), ty(ValV), DAG);
2568 }
2569 
2570 bool
2572  // Assuming the caller does not have either a signext or zeroext modifier, and
2573  // only one value is accepted, any reasonable truncation is allowed.
2574  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2575  return false;
2576 
2577  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2578  // fragile at the moment: any support for multiple value returns would be
2579  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2580  return Ty1->getPrimitiveSizeInBits() <= 32;
2581 }
2582 
2583 SDValue
2585  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2586  unsigned ClaimAlign = LN->getAlignment();
2587  validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
2588  // Call LowerUnalignedLoad for all loads, it recognizes loads that
2589  // don't need extra aligning.
2590  return LowerUnalignedLoad(Op, DAG);
2591 }
2592 
2593 SDValue
2595  StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2596  unsigned ClaimAlign = SN->getAlignment();
2597  SDValue Ptr = SN->getBasePtr();
2598  const SDLoc &dl(Op);
2599  validateConstPtrAlignment(Ptr, dl, ClaimAlign);
2600 
2601  MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2602  unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2603  if (ClaimAlign < NeedAlign)
2604  return expandUnalignedStore(SN, DAG);
2605  return Op;
2606 }
2607 
2608 SDValue
2610  const {
2611  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2612  MVT LoadTy = ty(Op);
2613  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2614  unsigned HaveAlign = LN->getAlignment();
2615  if (HaveAlign >= NeedAlign)
2616  return Op;
2617 
2618  const SDLoc &dl(Op);
2619  const DataLayout &DL = DAG.getDataLayout();
2620  LLVMContext &Ctx = *DAG.getContext();
2621  unsigned AS = LN->getAddressSpace();
2622 
2623  // If the load aligning is disabled or the load can be broken up into two
2624  // smaller legal loads, do the default (target-independent) expansion.
2625  bool DoDefault = false;
2626  // Handle it in the default way if this is an indexed load.
2627  if (!LN->isUnindexed())
2628  DoDefault = true;
2629 
2630  if (!AlignLoads) {
2631  if (allowsMemoryAccess(Ctx, DL, LN->getMemoryVT(), AS, HaveAlign))
2632  return Op;
2633  DoDefault = true;
2634  }
2635  if (!DoDefault && 2*HaveAlign == NeedAlign) {
2636  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2637  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8*HaveAlign)
2638  : MVT::getVectorVT(MVT::i8, HaveAlign);
2639  DoDefault = allowsMemoryAccess(Ctx, DL, PartTy, AS, HaveAlign);
2640  }
2641  if (DoDefault) {
2642  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2643  return DAG.getMergeValues({P.first, P.second}, dl);
2644  }
2645 
2646  // The code below generates two loads, both aligned as NeedAlign, and
2647  // with the distance of NeedAlign between them. For that to cover the
2648  // bits that need to be loaded (and without overlapping), the size of
2649  // the loads should be equal to NeedAlign. This is true for all loadable
2650  // types, but add an assertion in case something changes in the future.
2651  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
2652 
2653  unsigned LoadLen = NeedAlign;
2654  SDValue Base = LN->getBasePtr();
2655  SDValue Chain = LN->getChain();
2656  auto BO = getBaseAndOffset(Base);
2657  unsigned BaseOpc = BO.first.getOpcode();
2658  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2659  return Op;
2660 
2661  if (BO.second % LoadLen != 0) {
2662  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2663  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2664  BO.second -= BO.second % LoadLen;
2665  }
2666  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2667  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2668  DAG.getConstant(NeedAlign, dl, MVT::i32))
2669  : BO.first;
2670  SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
2671  SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
2672 
2673  MachineMemOperand *WideMMO = nullptr;
2674  if (MachineMemOperand *MMO = LN->getMemOperand()) {
2675  MachineFunction &MF = DAG.getMachineFunction();
2676  WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
2677  2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
2678  MMO->getSyncScopeID(), MMO->getOrdering(),
2679  MMO->getFailureOrdering());
2680  }
2681 
2682  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2683  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2684 
2685  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2686  {Load1, Load0, BaseNoOff.getOperand(0)});
2687  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2688  Load0.getValue(1), Load1.getValue(1));
2689  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2690  return M;
2691 }
2692 
2693 SDValue
2695  const SDLoc &dl(Op);
2696  unsigned Opc = Op.getOpcode();
2697  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
2698 
2699  if (Opc == ISD::ADDCARRY)
2700  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
2701  { X, Y, C });
2702 
2703  EVT CarryTy = C.getValueType();
2704  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
2705  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
2706  SDValue Out[] = { SubC.getValue(0),
2707  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
2708  return DAG.getMergeValues(Out, dl);
2709 }
2710 
2711 SDValue
2713  SDValue Chain = Op.getOperand(0);
2714  SDValue Offset = Op.getOperand(1);
2715  SDValue Handler = Op.getOperand(2);
2716  SDLoc dl(Op);
2717  auto PtrVT = getPointerTy(DAG.getDataLayout());
2718 
2719  // Mark function as containing a call to EH_RETURN.
2720  HexagonMachineFunctionInfo *FuncInfo =
2722  FuncInfo->setHasEHReturn();
2723 
2724  unsigned OffsetReg = Hexagon::R28;
2725 
2726  SDValue StoreAddr =
2727  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2728  DAG.getIntPtrConstant(4, dl));
2729  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2730  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2731 
2732  // Not needed we already use it as explict input to EH_RETURN.
2733  // MF.getRegInfo().addLiveOut(OffsetReg);
2734 
2735  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2736 }
2737 
2738 SDValue
2740  unsigned Opc = Op.getOpcode();
2741 
2742  // Handle INLINEASM first.
2743  if (Opc == ISD::INLINEASM)
2744  return LowerINLINEASM(Op, DAG);
2745 
2746  if (isHvxOperation(Op)) {
2747  // If HVX lowering returns nothing, try the default lowering.
2748  if (SDValue V = LowerHvxOperation(Op, DAG))
2749  return V;
2750  }
2751 
2752  switch (Opc) {
2753  default:
2754 #ifndef NDEBUG
2755  Op.getNode()->dumpr(&DAG);
2756  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2757  errs() << "Error: check for a non-legal type in this operation\n";
2758 #endif
2759  llvm_unreachable("Should not custom lower this!");
2760  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2761  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
2762  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
2763  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
2764  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2765  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2766  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2767  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
2768  case ISD::LOAD: return LowerLoad(Op, DAG);
2769  case ISD::STORE: return LowerStore(Op, DAG);
2770  case ISD::ADDCARRY:
2771  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
2772  case ISD::SRA:
2773  case ISD::SHL:
2774  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2775  case ISD::ROTL: return LowerROTL(Op, DAG);
2776  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2777  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2778  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2779  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2780  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2781  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2782  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2783  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2784  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2785  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2786  case ISD::VASTART: return LowerVASTART(Op, DAG);
2787  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2788  case ISD::SETCC: return LowerSETCC(Op, DAG);
2789  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2790  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2791  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2792  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2793  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2794  break;
2795  }
2796 
2797  return SDValue();
2798 }
2799 
2800 void
2803  SelectionDAG &DAG) const {
2804  // We are only custom-lowering stores to verify the alignment of the
2805  // address if it is a compile-time constant. Since a store can be modified
2806  // during type-legalization (the value being stored may need legalization),
2807  // return empty Results here to indicate that we don't really make any
2808  // changes in the custom lowering.
2809  if (N->getOpcode() != ISD::STORE)
2810  return TargetLowering::LowerOperationWrapper(N, Results, DAG);
2811 }
2812 
2813 void
2816  SelectionDAG &DAG) const {
2817  const SDLoc &dl(N);
2818  switch (N->getOpcode()) {
2819  case ISD::SRL:
2820  case ISD::SRA:
2821  case ISD::SHL:
2822  return;
2823  case ISD::BITCAST:
2824  // Handle a bitcast from v8i1 to i8.
2825  if (N->getValueType(0) == MVT::i8) {
2826  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
2827  N->getOperand(0), DAG);
2828  Results.push_back(P);
2829  }
2830  break;
2831  }
2832 }
2833 
2834 /// Returns relocation base for the given PIC jumptable.
2835 SDValue
2837  SelectionDAG &DAG) const {
2838  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2839  EVT VT = Table.getValueType();
2841  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2842 }
2843 
2844 //===----------------------------------------------------------------------===//
2845 // Inline Assembly Support
2846 //===----------------------------------------------------------------------===//
2847 
2850  if (Constraint.size() == 1) {
2851  switch (Constraint[0]) {
2852  case 'q':
2853  case 'v':
2854  if (Subtarget.useHVXOps())
2855  return C_RegisterClass;
2856  break;
2857  case 'a':
2858  return C_RegisterClass;
2859  default:
2860  break;
2861  }
2862  }
2863  return TargetLowering::getConstraintType(Constraint);
2864 }
2865 
2866 std::pair<unsigned, const TargetRegisterClass*>
2868  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2869 
2870  if (Constraint.size() == 1) {
2871  switch (Constraint[0]) {
2872  case 'r': // R0-R31
2873  switch (VT.SimpleTy) {
2874  default:
2875  return {0u, nullptr};
2876  case MVT::i1:
2877  case MVT::i8:
2878  case MVT::i16:
2879  case MVT::i32:
2880  case MVT::f32:
2881  return {0u, &Hexagon::IntRegsRegClass};
2882  case MVT::i64:
2883  case MVT::f64:
2884  return {0u, &Hexagon::DoubleRegsRegClass};
2885  }
2886  break;
2887  case 'a': // M0-M1
2888  if (VT != MVT::i32)
2889  return {0u, nullptr};
2890  return {0u, &Hexagon::ModRegsRegClass};
2891  case 'q': // q0-q3
2892  switch (VT.getSizeInBits()) {
2893  default:
2894  return {0u, nullptr};
2895  case 512:
2896  case 1024:
2897  return {0u, &Hexagon::HvxQRRegClass};
2898  }
2899  break;
2900  case 'v': // V0-V31
2901  switch (VT.getSizeInBits()) {
2902  default:
2903  return {0u, nullptr};
2904  case 512:
2905  return {0u, &Hexagon::HvxVRRegClass};
2906  case 1024:
2907  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
2908  return {0u, &Hexagon::HvxVRRegClass};
2909  return {0u, &Hexagon::HvxWRRegClass};
2910  case 2048:
2911  return {0u, &Hexagon::HvxWRRegClass};
2912  }
2913  break;
2914  default:
2915  return {0u, nullptr};
2916  }
2917  }
2918 
2919  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2920 }
2921 
2922 /// isFPImmLegal - Returns true if the target can instruction select the
2923 /// specified FP immediate natively. If false, the legalizer will
2924 /// materialize the FP immediate as a load from a constant pool.
2926  return true;
2927 }
2928 
2929 /// isLegalAddressingMode - Return true if the addressing mode represented by
2930 /// AM is legal for this target, for a load/store of the specified type.
2932  const AddrMode &AM, Type *Ty,
2933  unsigned AS, Instruction *I) const {
2934  if (Ty->isSized()) {
2935  // When LSR detects uses of the same base address to access different
2936  // types (e.g. unions), it will assume a conservative type for these
2937  // uses:
2938  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
2939  // The type Ty passed here would then be "void". Skip the alignment
2940  // checks, but do not return false right away, since that confuses
2941  // LSR into crashing.
2942  unsigned A = DL.getABITypeAlignment(Ty);
2943  // The base offset must be a multiple of the alignment.
2944  if ((AM.BaseOffs % A) != 0)
2945  return false;
2946  // The shifted offset must fit in 11 bits.
2947  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
2948  return false;
2949  }
2950 
2951  // No global is ever allowed as a base.
2952  if (AM.BaseGV)
2953  return false;
2954 
2955  int Scale = AM.Scale;
2956  if (Scale < 0)
2957  Scale = -Scale;
2958  switch (Scale) {
2959  case 0: // No scale reg, "r+i", "r", or just "i".
2960  break;
2961  default: // No scaled addressing mode.
2962  return false;
2963  }
2964  return true;
2965 }
2966 
2967 /// Return true if folding a constant offset with the given GlobalAddress is
2968 /// legal. It is frequently not legal in PIC relocation models.
2970  const {
2971  return HTM.getRelocationModel() == Reloc::Static;
2972 }
2973 
2974 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2975 /// icmp immediate, that is the target has icmp instructions which can compare
2976 /// a register against the immediate without having to materialize the
2977 /// immediate into a register.
2979  return Imm >= -512 && Imm <= 511;
2980 }
2981 
2982 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2983 /// for tail call optimization. Targets which want to do tail call
2984 /// optimization should implement this function.
2986  SDValue Callee,
2987  CallingConv::ID CalleeCC,
2988  bool IsVarArg,
2989  bool IsCalleeStructRet,
2990  bool IsCallerStructRet,
2991  const SmallVectorImpl<ISD::OutputArg> &Outs,
2992  const SmallVectorImpl<SDValue> &OutVals,
2994  SelectionDAG& DAG) const {
2995  const Function &CallerF = DAG.getMachineFunction().getFunction();
2996  CallingConv::ID CallerCC = CallerF.getCallingConv();
2997  bool CCMatch = CallerCC == CalleeCC;
2998 
2999  // ***************************************************************************
3000  // Look for obvious safe cases to perform tail call optimization that do not
3001  // require ABI changes.
3002  // ***************************************************************************
3003 
3004  // If this is a tail call via a function pointer, then don't do it!
3005  if (!isa<GlobalAddressSDNode>(Callee) &&
3006  !isa<ExternalSymbolSDNode>(Callee)) {
3007  return false;
3008  }
3009 
3010  // Do not optimize if the calling conventions do not match and the conventions
3011  // used are not C or Fast.
3012  if (!CCMatch) {
3013  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3014  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3015  // If R & E, then ok.
3016  if (!R || !E)
3017  return false;
3018  }
3019 
3020  // Do not tail call optimize vararg calls.
3021  if (IsVarArg)
3022  return false;
3023 
3024  // Also avoid tail call optimization if either caller or callee uses struct
3025  // return semantics.
3026  if (IsCalleeStructRet || IsCallerStructRet)
3027  return false;
3028 
3029  // In addition to the cases above, we also disable Tail Call Optimization if
3030  // the calling convention code that at least one outgoing argument needs to
3031  // go on the stack. We cannot check that here because at this point that
3032  // information is not available.
3033  return true;
3034 }
3035 
3036 /// Returns the target specific optimal type for load and store operations as
3037 /// a result of memset, memcpy, and memmove lowering.
3038 ///
3039 /// If DstAlign is zero that means it's safe to destination alignment can
3040 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3041 /// a need to check it against alignment requirement, probably because the
3042 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3043 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3044 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3045 /// does not need to be loaded. It returns EVT::Other if the type should be
3046 /// determined using generic target-independent logic.
3048  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3049  bool MemcpyStrSrc, MachineFunction &MF) const {
3050 
3051  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3052  return (GivenA % MinA) == 0;
3053  };
3054 
3055  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3056  return MVT::i64;
3057  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3058  return MVT::i32;
3059  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3060  return MVT::i16;
3061 
3062  return MVT::Other;
3063 }
3064 
3066  unsigned AS, unsigned Align, bool *Fast) const {
3067  if (Fast)
3068  *Fast = false;
3069  return Subtarget.isHVXVectorType(VT.getSimpleVT());
3070 }
3071 
3072 std::pair<const TargetRegisterClass*, uint8_t>
3073 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3074  MVT VT) const {
3075  if (Subtarget.isHVXVectorType(VT, true)) {
3076  unsigned BitWidth = VT.getSizeInBits();
3077  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3078 
3079  if (VT.getVectorElementType() == MVT::i1)
3080  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3081  if (BitWidth == VecWidth)
3082  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3083  assert(BitWidth == 2 * VecWidth);
3084  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3085  }
3086 
3088 }
3089 
3091  ISD::LoadExtType ExtTy, EVT NewVT) const {
3092  // TODO: This may be worth removing. Check regression tests for diffs.
3093  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3094  return false;
3095 
3096  auto *L = cast<LoadSDNode>(Load);
3097  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3098  // Small-data object, do not shrink.
3099  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3100  return false;
3101  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3102  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3103  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3104  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3105  }
3106  return true;
3107 }
3108 
3110  AtomicOrdering Ord) const {
3111  BasicBlock *BB = Builder.GetInsertBlock();
3112  Module *M = BB->getParent()->getParent();
3113  auto PT = cast<PointerType>(Addr->getType());
3114  Type *Ty = PT->getElementType();
3115  unsigned SZ = Ty->getPrimitiveSizeInBits();
3116  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3117  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3118  : Intrinsic::hexagon_L4_loadd_locked;
3119 
3120  PointerType *NewPtrTy
3121  = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
3122  Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3123 
3124  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3125  Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3126 
3127  return Builder.CreateBitCast(Call, Ty);
3128 }
3129 
3130 /// Perform a store-conditional operation to Addr. Return the status of the
3131 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3133  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3134  BasicBlock *BB = Builder.GetInsertBlock();
3135  Module *M = BB->getParent()->getParent();
3136  Type *Ty = Val->getType();
3137  unsigned SZ = Ty->getPrimitiveSizeInBits();
3138 
3139  Type *CastTy = Builder.getIntNTy(SZ);
3140  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3141  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3142  : Intrinsic::hexagon_S4_stored_locked;
3143  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3144 
3145  unsigned AS = Addr->getType()->getPointerAddressSpace();
3146  Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3147  Val = Builder.CreateBitCast(Val, CastTy);
3148 
3149  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3150  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3151  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3152  return Ext;
3153 }
3154 
3157  // Do not expand loads and stores that don't exceed 64 bits.
3158  return LI->getType()->getPrimitiveSizeInBits() > 64
3161 }
3162 
3164  // Do not expand loads and stores that don't exceed 64 bits.
3165  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3166 }
3167 
3170  AtomicCmpXchgInst *AI) const {
3171  const DataLayout &DL = AI->getModule()->getDataLayout();
3172  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3173  if (Size >= 4 && Size <= 8)
3176 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
bool isMachineConstantPoolEntry() const
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Type * getVectorElementType() const
Definition: Type.h:370
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
Definition: Instructions.h:409
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:593
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isUndef() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:211
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:936
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:835
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:357
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:649
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:366
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:64
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
HexagonTargetObjectFile * getObjFileLowering() const override
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:185
bool isVector() const
Return true if this is a vector value type.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const SDValue & getBasePtr() const
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:698
SDVTList getVTList() const
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
unsigned getVectorNumElements() const
ArrayRef< MVT > getHVXElementTypes() const
unsigned getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
const SDValue & getChain() const
Function Alias Analysis Results
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:704
unsigned getAlignment() const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Hexagon target-specific information for each MachineFunction.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
unsigned const TargetRegisterInfo * TRI
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
A debug info location.
Definition: DebugLoc.h:33
F(f)
Type * getStructElementType(unsigned N) const
Definition: DerivedTypes.h:332
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:949
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:502
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
An instruction for reading from memory.
Definition: Instructions.h:167
SDNode * getNode() const
get the SDNode which holds the desired result
#define R2(n)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:253
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:352
The address of the GOT.
Definition: ISDOpcodes.h:65
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:780
#define HEXAGON_LRFP_SIZE
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isMemLoc() const
unsigned getAddressSpace() const
Return the address space for the associated pointer.
SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL)
Returns sum of the base pointer and offset.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:578
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1134
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:455
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:370
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Shift and rotation operations.
Definition: ISDOpcodes.h:409
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:201
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:243
Base class for LoadSDNode and StoreSDNode.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:392
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
InstrTy * getInstruction() const
Definition: CallSite.h:91
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:459
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
zlib-gnu style compression
This file implements a class to represent arbitrary precision integral constant values and operations...
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:666
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:694
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
int64_t getSExtValue() const
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static Value * getBrevLdObject(Value *V)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1731
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:397
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
#define T
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:120
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:428
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:851
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
An instruction for storing to memory.
Definition: Instructions.h:320
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:960
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1658
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:746
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
amdgpu Simplify well known AMD library false Value * Callee
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1019
MVT getVectorElementType() const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Class to represent pointers.
Definition: DerivedTypes.h:466
unsigned getByValSize() const
This class is used to represent ISD::STORE nodes.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
The memory access is volatile.
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
#define P(N)
const SDValue & getBasePtr() const
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
static bool isBrevLdIntrinsic(const Value *Inst)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:727
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:935
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:331
#define H(x, y, z)
Definition: MD5.cpp:57
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:40
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:823
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
#define HEXAGON_GOT_SYM_NAME
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:766
const APInt & getAPIntValue() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
static mvt_range vector_valuetypes()
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:1838
Class to represent integer types.
Definition: DerivedTypes.h:39
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:280
Constant Vector Declarations.
Definition: Constants.h:499
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:718
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1213
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
Definition: IRBuilder.h:359
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1206
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
unsigned first
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:638
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:632
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
void dump() const
Dump this node, for debugging.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
Return true if it is profitable to reduce a load to a smaller type.
static unsigned getIntrinsicID(const SDNode *N)
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:338
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
Module.h This file contains the declarations for the Module class.
const DebugLoc & getDebugLoc() const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
iterator end() const
Definition: ArrayRef.h:137
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:729
const DataFlowGraph & G
Definition: RDFGraph.cpp:210
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:412
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:306
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:621
Represents one node in the SelectionDAG.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:678
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
void setPrefLoopAlignment(unsigned Align)
Set the target&#39;s preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
bool isTailCall() const
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:311
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:637
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:723
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:672
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
unsigned getVectorLength() const
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
MO_GOT - Indicates a GOT-relative relocation.
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
unsigned getTypeAlignment(MVT Ty) const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:704
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:485
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:187
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:613
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1180
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:402
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:192
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
uint32_t Size
Definition: Profile.cpp:46
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:1973
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:607
SDValue getValue(unsigned R) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:308
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents &#39;eh_return&#39; gcc dwarf builtin...
Definition: ISDOpcodes.h:101
const GlobalObject * getBaseObject() const
Definition: Globals.cpp:260
bool isRegLoc() const
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:856
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:344
MachineConstantPoolValue * getMachineCPVal() const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())