LLVM  6.0.0svn
MSP430ISelLowering.cpp
Go to the documentation of this file.
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430ISelLowering.h"
15 #include "MSP430.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/Support/Debug.h"
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "msp430-lower"
40 
42  const MSP430Subtarget &STI)
43  : TargetLowering(TM) {
44 
45  // Set up the register classes.
46  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
47  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
48 
49  // Compute derived properties from the register classes
51 
52  // Provide all sorts of operation actions
55  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
56 
57  // We have post-incremented loads / stores.
60 
61  for (MVT VT : MVT::integer_valuetypes()) {
67  }
68 
69  // We don't have any truncstores
71 
98 
105 
112 
114 
115  // FIXME: Implement efficiently multiplication by a constant
126 
139 
140  // varargs support
146 
147  // EABI Libcalls - EABI Section 6.2
148  const struct {
149  const RTLIB::Libcall Op;
150  const char * const Name;
151  const ISD::CondCode Cond;
152  } LibraryCalls[] = {
153  // Floating point conversions - EABI Table 6
154  { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
155  { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
156  // The following is NOT implemented in libgcc
157  //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
158  { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
159  { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
160  // The following is NOT implemented in libgcc
161  //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
162  { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
163  { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
164  // The following is NOT implemented in libgcc
165  //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
166  { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
167  { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
168  // The following is NOT implemented in libgcc
169  //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
170  { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
171  { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
172  // TODO The following IS implemented in libgcc
173  //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
174  { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
175  // TODO The following IS implemented in libgcc but is not in the EABI
176  { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
177  // TODO The following IS implemented in libgcc
178  //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
179  { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
180  // The following IS implemented in libgcc but is not in the EABI
181  { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
182  // TODO The following IS implemented in libgcc
183  //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
184  { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
185  // TODO The following IS implemented in libgcc but is not in the EABI
186  { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
187  // TODO The following IS implemented in libgcc
188  //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
189  { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
190  // The following IS implemented in libgcc but is not in the EABI
191  { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
192 
193  // Floating point comparisons - EABI Table 7
194  { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
195  { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
196  { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
197  { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
198  { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
199  { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
200  { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
201  { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
202  { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
203  { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
204  { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
205  { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
206 
207  // Floating point arithmetic - EABI Table 8
208  { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
209  { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
210  { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
211  { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
212  { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
213  { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
214  { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
215  { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
216  // The following are NOT implemented in libgcc
217  // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
218  // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
219 
220  // TODO: SLL/SRA/SRL are in libgcc, RLL isn't
221 
222  // Universal Integer Operations - EABI Table 9
223  { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
224  { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
225  { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
226  { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
227  { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
228  { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
229  { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
230  { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
231  { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
232  { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
233  { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
234  { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
235 
236  };
237 
238  for (const auto &LC : LibraryCalls) {
239  setLibcallName(LC.Op, LC.Name);
240  if (LC.Cond != ISD::SETCC_INVALID)
241  setCmpLibcallCC(LC.Op, LC.Cond);
242  }
243 
244  if (STI.hasHWMult16()) {
245  const struct {
246  const RTLIB::Libcall Op;
247  const char * const Name;
248  } LibraryCalls[] = {
249  // Integer Multiply - EABI Table 9
250  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
251  { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
252  { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
253  // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
254  // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
255  };
256  for (const auto &LC : LibraryCalls) {
257  setLibcallName(LC.Op, LC.Name);
258  }
259  } else if (STI.hasHWMult32()) {
260  const struct {
261  const RTLIB::Libcall Op;
262  const char * const Name;
263  } LibraryCalls[] = {
264  // Integer Multiply - EABI Table 9
265  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
266  { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
267  { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
268  // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
269  // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
270  };
271  for (const auto &LC : LibraryCalls) {
272  setLibcallName(LC.Op, LC.Name);
273  }
274  } else if (STI.hasHWMultF5()) {
275  const struct {
276  const RTLIB::Libcall Op;
277  const char * const Name;
278  } LibraryCalls[] = {
279  // Integer Multiply - EABI Table 9
280  { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
281  { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
282  { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
283  // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
284  // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
285  };
286  for (const auto &LC : LibraryCalls) {
287  setLibcallName(LC.Op, LC.Name);
288  }
289  } else { // NoHWMult
290  const struct {
291  const RTLIB::Libcall Op;
292  const char * const Name;
293  } LibraryCalls[] = {
294  // Integer Multiply - EABI Table 9
295  { RTLIB::MUL_I16, "__mspabi_mpyi" },
296  { RTLIB::MUL_I32, "__mspabi_mpyl" },
297  { RTLIB::MUL_I64, "__mspabi_mpyll" },
298  // The __mspabi_mpysl* functions are NOT implemented in libgcc
299  // The __mspabi_mpyul* functions are NOT implemented in libgcc
300  };
301  for (const auto &LC : LibraryCalls) {
302  setLibcallName(LC.Op, LC.Name);
303  }
305  }
306 
307  // Several of the runtime library functions use a special calling conv
322  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
323 
326 }
327 
329  SelectionDAG &DAG) const {
330  switch (Op.getOpcode()) {
331  case ISD::SHL: // FALLTHROUGH
332  case ISD::SRL:
333  case ISD::SRA: return LowerShifts(Op, DAG);
334  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
335  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
336  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
337  case ISD::SETCC: return LowerSETCC(Op, DAG);
338  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
339  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
340  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
341  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
342  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
343  case ISD::VASTART: return LowerVASTART(Op, DAG);
344  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
345  default:
346  llvm_unreachable("unimplemented operand");
347  }
348 }
349 
350 //===----------------------------------------------------------------------===//
351 // MSP430 Inline Assembly Support
352 //===----------------------------------------------------------------------===//
353 
354 /// getConstraintType - Given a constraint letter, return the type of
355 /// constraint it is for this target.
358  if (Constraint.size() == 1) {
359  switch (Constraint[0]) {
360  case 'r':
361  return C_RegisterClass;
362  default:
363  break;
364  }
365  }
366  return TargetLowering::getConstraintType(Constraint);
367 }
368 
369 std::pair<unsigned, const TargetRegisterClass *>
371  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
372  if (Constraint.size() == 1) {
373  // GCC Constraint Letters
374  switch (Constraint[0]) {
375  default: break;
376  case 'r': // GENERAL_REGS
377  if (VT == MVT::i8)
378  return std::make_pair(0U, &MSP430::GR8RegClass);
379 
380  return std::make_pair(0U, &MSP430::GR16RegClass);
381  }
382  }
383 
384  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
385 }
386 
387 //===----------------------------------------------------------------------===//
388 // Calling Convention Implementation
389 //===----------------------------------------------------------------------===//
390 
391 #include "MSP430GenCallingConv.inc"
392 
393 /// For each argument in a function store the number of pieces it is composed
394 /// of.
395 template<typename ArgT>
398  unsigned CurrentArgIndex;
399 
400  if (Args.empty())
401  return;
402 
403  CurrentArgIndex = Args[0].OrigArgIndex;
404  Out.push_back(0);
405 
406  for (auto &Arg : Args) {
407  if (CurrentArgIndex == Arg.OrigArgIndex) {
408  Out.back() += 1;
409  } else {
410  Out.push_back(1);
411  CurrentArgIndex = Arg.OrigArgIndex;
412  }
413  }
414 }
415 
416 static void AnalyzeVarArgs(CCState &State,
417  const SmallVectorImpl<ISD::OutputArg> &Outs) {
418  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
419 }
420 
421 static void AnalyzeVarArgs(CCState &State,
423  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
424 }
425 
426 /// Analyze incoming and outgoing function arguments. We need custom C++ code
427 /// to handle special constraints in the ABI like reversing the order of the
428 /// pieces of splitted arguments. In addition, all pieces of a certain argument
429 /// have to be passed either using registers or the stack but never mixing both.
430 template<typename ArgT>
431 static void AnalyzeArguments(CCState &State,
433  const SmallVectorImpl<ArgT> &Args) {
434  static const MCPhysReg CRegList[] = {
435  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
436  };
437  static const unsigned CNbRegs = array_lengthof(CRegList);
438  static const MCPhysReg BuiltinRegList[] = {
439  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
440  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
441  };
442  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
443 
444  ArrayRef<MCPhysReg> RegList;
445  unsigned NbRegs;
446 
447  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
448  if (Builtin) {
449  RegList = BuiltinRegList;
450  NbRegs = BuiltinNbRegs;
451  } else {
452  RegList = CRegList;
453  NbRegs = CNbRegs;
454  }
455 
456  if (State.isVarArg()) {
457  AnalyzeVarArgs(State, Args);
458  return;
459  }
460 
461  SmallVector<unsigned, 4> ArgsParts;
462  ParseFunctionArgs(Args, ArgsParts);
463 
464  if (Builtin) {
465  assert(ArgsParts.size() == 2 &&
466  "Builtin calling convention requires two arguments");
467  }
468 
469  unsigned RegsLeft = NbRegs;
470  bool UsedStack = false;
471  unsigned ValNo = 0;
472 
473  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
474  MVT ArgVT = Args[ValNo].VT;
475  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
476  MVT LocVT = ArgVT;
478 
479  // Promote i8 to i16
480  if (LocVT == MVT::i8) {
481  LocVT = MVT::i16;
482  if (ArgFlags.isSExt())
483  LocInfo = CCValAssign::SExt;
484  else if (ArgFlags.isZExt())
485  LocInfo = CCValAssign::ZExt;
486  else
487  LocInfo = CCValAssign::AExt;
488  }
489 
490  // Handle byval arguments
491  if (ArgFlags.isByVal()) {
492  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
493  continue;
494  }
495 
496  unsigned Parts = ArgsParts[i];
497 
498  if (Builtin) {
499  assert(Parts == 4 &&
500  "Builtin calling convention requires 64-bit arguments");
501  }
502 
503  if (!UsedStack && Parts == 2 && RegsLeft == 1) {
504  // Special case for 32-bit register split, see EABI section 3.3.3
505  unsigned Reg = State.AllocateReg(RegList);
506  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
507  RegsLeft -= 1;
508 
509  UsedStack = true;
510  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
511  } else if (Parts <= RegsLeft) {
512  for (unsigned j = 0; j < Parts; j++) {
513  unsigned Reg = State.AllocateReg(RegList);
514  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
515  RegsLeft--;
516  }
517  } else {
518  UsedStack = true;
519  for (unsigned j = 0; j < Parts; j++)
520  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
521  }
522  }
523 }
524 
525 static void AnalyzeRetResult(CCState &State,
527  State.AnalyzeCallResult(Ins, RetCC_MSP430);
528 }
529 
530 static void AnalyzeRetResult(CCState &State,
531  const SmallVectorImpl<ISD::OutputArg> &Outs) {
532  State.AnalyzeReturn(Outs, RetCC_MSP430);
533 }
534 
535 template<typename ArgT>
536 static void AnalyzeReturnValues(CCState &State,
538  const SmallVectorImpl<ArgT> &Args) {
539  AnalyzeRetResult(State, Args);
540 }
541 
542 SDValue MSP430TargetLowering::LowerFormalArguments(
543  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
544  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
545  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
546 
547  switch (CallConv) {
548  default:
549  report_fatal_error("Unsupported calling convention");
550  case CallingConv::C:
551  case CallingConv::Fast:
552  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
554  if (Ins.empty())
555  return Chain;
556  report_fatal_error("ISRs cannot have arguments");
557  }
558 }
559 
560 SDValue
561 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
562  SmallVectorImpl<SDValue> &InVals) const {
563  SelectionDAG &DAG = CLI.DAG;
564  SDLoc &dl = CLI.DL;
566  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
568  SDValue Chain = CLI.Chain;
569  SDValue Callee = CLI.Callee;
570  bool &isTailCall = CLI.IsTailCall;
571  CallingConv::ID CallConv = CLI.CallConv;
572  bool isVarArg = CLI.IsVarArg;
573 
574  // MSP430 target does not yet support tail call optimization.
575  isTailCall = false;
576 
577  switch (CallConv) {
578  default:
579  report_fatal_error("Unsupported calling convention");
581  case CallingConv::Fast:
582  case CallingConv::C:
583  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
584  Outs, OutVals, Ins, dl, DAG, InVals);
586  report_fatal_error("ISRs cannot be called directly");
587  }
588 }
589 
590 /// LowerCCCArguments - transform physical registers into virtual registers and
591 /// generate load operations for arguments places on the stack.
592 // FIXME: struct return stuff
593 SDValue MSP430TargetLowering::LowerCCCArguments(
594  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
595  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
596  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
598  MachineFrameInfo &MFI = MF.getFrameInfo();
599  MachineRegisterInfo &RegInfo = MF.getRegInfo();
601 
602  // Assign locations to all of the incoming arguments.
604  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
605  *DAG.getContext());
606  AnalyzeArguments(CCInfo, ArgLocs, Ins);
607 
608  // Create frame index for the start of the first vararg value
609  if (isVarArg) {
610  unsigned Offset = CCInfo.getNextStackOffset();
611  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
612  }
613 
614  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
615  CCValAssign &VA = ArgLocs[i];
616  if (VA.isRegLoc()) {
617  // Arguments passed in registers
618  EVT RegVT = VA.getLocVT();
619  switch (RegVT.getSimpleVT().SimpleTy) {
620  default:
621  {
622 #ifndef NDEBUG
623  errs() << "LowerFormalArguments Unhandled argument type: "
624  << RegVT.getEVTString() << "\n";
625 #endif
626  llvm_unreachable(nullptr);
627  }
628  case MVT::i16:
629  unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
630  RegInfo.addLiveIn(VA.getLocReg(), VReg);
631  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
632 
633  // If this is an 8-bit value, it is really passed promoted to 16
634  // bits. Insert an assert[sz]ext to capture this, then truncate to the
635  // right size.
636  if (VA.getLocInfo() == CCValAssign::SExt)
637  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
638  DAG.getValueType(VA.getValVT()));
639  else if (VA.getLocInfo() == CCValAssign::ZExt)
640  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
641  DAG.getValueType(VA.getValVT()));
642 
643  if (VA.getLocInfo() != CCValAssign::Full)
644  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
645 
646  InVals.push_back(ArgValue);
647  }
648  } else {
649  // Sanity check
650  assert(VA.isMemLoc());
651 
652  SDValue InVal;
653  ISD::ArgFlagsTy Flags = Ins[i].Flags;
654 
655  if (Flags.isByVal()) {
656  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
657  VA.getLocMemOffset(), true);
658  InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
659  } else {
660  // Load the argument to a virtual register
661  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
662  if (ObjSize > 2) {
663  errs() << "LowerFormalArguments Unhandled argument type: "
664  << EVT(VA.getLocVT()).getEVTString()
665  << "\n";
666  }
667  // Create the frame index object for this incoming parameter...
668  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
669 
670  // Create the SelectionDAG nodes corresponding to a load
671  //from this parameter
672  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
673  InVal = DAG.getLoad(
674  VA.getLocVT(), dl, Chain, FIN,
676  }
677 
678  InVals.push_back(InVal);
679  }
680  }
681 
682  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
683  if (Ins[i].Flags.isSRet()) {
684  unsigned Reg = FuncInfo->getSRetReturnReg();
685  if (!Reg) {
688  FuncInfo->setSRetReturnReg(Reg);
689  }
690  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
691  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
692  }
693  }
694 
695  return Chain;
696 }
697 
698 bool
699 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
700  MachineFunction &MF,
701  bool IsVarArg,
703  LLVMContext &Context) const {
705  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
706  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
707 }
708 
709 SDValue
710 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
711  bool isVarArg,
713  const SmallVectorImpl<SDValue> &OutVals,
714  const SDLoc &dl, SelectionDAG &DAG) const {
715 
717 
718  // CCValAssign - represent the assignment of the return value to a location
720 
721  // ISRs cannot return any value.
722  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
723  report_fatal_error("ISRs cannot return any value");
724 
725  // CCState - Info about the registers and stack slot.
726  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
727  *DAG.getContext());
728 
729  // Analize return values.
730  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
731 
732  SDValue Flag;
733  SmallVector<SDValue, 4> RetOps(1, Chain);
734 
735  // Copy the result values into the output registers.
736  for (unsigned i = 0; i != RVLocs.size(); ++i) {
737  CCValAssign &VA = RVLocs[i];
738  assert(VA.isRegLoc() && "Can only return in registers!");
739 
740  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
741  OutVals[i], Flag);
742 
743  // Guarantee that all emitted copies are stuck together,
744  // avoiding something bad.
745  Flag = Chain.getValue(1);
746  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
747  }
748 
749  if (MF.getFunction()->hasStructRetAttr()) {
751  unsigned Reg = FuncInfo->getSRetReturnReg();
752 
753  if (!Reg)
754  llvm_unreachable("sret virtual register not created in entry block");
755 
756  SDValue Val =
757  DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
758  unsigned R12 = MSP430::R12;
759 
760  Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
761  Flag = Chain.getValue(1);
762  RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
763  }
764 
765  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
767 
768  RetOps[0] = Chain; // Update chain.
769 
770  // Add the flag if we have it.
771  if (Flag.getNode())
772  RetOps.push_back(Flag);
773 
774  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
775 }
776 
777 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
778 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
779 SDValue MSP430TargetLowering::LowerCCCCallTo(
780  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
781  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
782  const SmallVectorImpl<SDValue> &OutVals,
783  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
784  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
785  // Analyze operands of the call, assigning locations to each operand.
787  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
788  *DAG.getContext());
789  AnalyzeArguments(CCInfo, ArgLocs, Outs);
790 
791  // Get a count of how many bytes are to be pushed on the stack.
792  unsigned NumBytes = CCInfo.getNextStackOffset();
793  auto PtrVT = getPointerTy(DAG.getDataLayout());
794 
795  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
796 
798  SmallVector<SDValue, 12> MemOpChains;
799  SDValue StackPtr;
800 
801  // Walk the register/memloc assignments, inserting copies/loads.
802  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
803  CCValAssign &VA = ArgLocs[i];
804 
805  SDValue Arg = OutVals[i];
806 
807  // Promote the value if needed.
808  switch (VA.getLocInfo()) {
809  default: llvm_unreachable("Unknown loc info!");
810  case CCValAssign::Full: break;
811  case CCValAssign::SExt:
812  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
813  break;
814  case CCValAssign::ZExt:
815  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
816  break;
817  case CCValAssign::AExt:
818  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
819  break;
820  }
821 
822  // Arguments that can be passed on register must be kept at RegsToPass
823  // vector
824  if (VA.isRegLoc()) {
825  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
826  } else {
827  assert(VA.isMemLoc());
828 
829  if (!StackPtr.getNode())
830  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
831 
832  SDValue PtrOff =
833  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
834  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
835 
836  SDValue MemOp;
837  ISD::ArgFlagsTy Flags = Outs[i].Flags;
838 
839  if (Flags.isByVal()) {
840  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
841  MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
842  Flags.getByValAlign(),
843  /*isVolatile*/false,
844  /*AlwaysInline=*/true,
845  /*isTailCall=*/false,
848  } else {
849  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
850  }
851 
852  MemOpChains.push_back(MemOp);
853  }
854  }
855 
856  // Transform all store nodes into one single node because all store nodes are
857  // independent of each other.
858  if (!MemOpChains.empty())
859  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
860 
861  // Build a sequence of copy-to-reg nodes chained together with token chain and
862  // flag operands which copy the outgoing args into registers. The InFlag in
863  // necessary since all emitted instructions must be stuck together.
864  SDValue InFlag;
865  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
866  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
867  RegsToPass[i].second, InFlag);
868  InFlag = Chain.getValue(1);
869  }
870 
871  // If the callee is a GlobalAddress node (quite common, every direct call is)
872  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
873  // Likewise ExternalSymbol -> TargetExternalSymbol.
874  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
875  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
876  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
877  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
878 
879  // Returns a chain & a flag for retval copy to use.
880  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
882  Ops.push_back(Chain);
883  Ops.push_back(Callee);
884 
885  // Add argument registers to the end of the list so that they are
886  // known live into the call.
887  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
888  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
889  RegsToPass[i].second.getValueType()));
890 
891  if (InFlag.getNode())
892  Ops.push_back(InFlag);
893 
894  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
895  InFlag = Chain.getValue(1);
896 
897  // Create the CALLSEQ_END node.
898  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
899  DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
900  InFlag = Chain.getValue(1);
901 
902  // Handle result values, copying them out of physregs into vregs that we
903  // return.
904  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
905  DAG, InVals);
906 }
907 
908 /// LowerCallResult - Lower the result values of a call into the
909 /// appropriate copies out of appropriate physical registers.
910 ///
911 SDValue MSP430TargetLowering::LowerCallResult(
912  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
913  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
914  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
915 
916  // Assign locations to each value returned by this call.
918  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
919  *DAG.getContext());
920 
921  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
922 
923  // Copy all of the result registers out of their specified physreg.
924  for (unsigned i = 0; i != RVLocs.size(); ++i) {
925  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
926  RVLocs[i].getValVT(), InFlag).getValue(1);
927  InFlag = Chain.getValue(2);
928  InVals.push_back(Chain.getValue(0));
929  }
930 
931  return Chain;
932 }
933 
935  SelectionDAG &DAG) const {
936  unsigned Opc = Op.getOpcode();
937  SDNode* N = Op.getNode();
938  EVT VT = Op.getValueType();
939  SDLoc dl(N);
940 
941  // Expand non-constant shifts to loops:
942  if (!isa<ConstantSDNode>(N->getOperand(1)))
943  switch (Opc) {
944  default: llvm_unreachable("Invalid shift opcode!");
945  case ISD::SHL:
946  return DAG.getNode(MSP430ISD::SHL, dl,
947  VT, N->getOperand(0), N->getOperand(1));
948  case ISD::SRA:
949  return DAG.getNode(MSP430ISD::SRA, dl,
950  VT, N->getOperand(0), N->getOperand(1));
951  case ISD::SRL:
952  return DAG.getNode(MSP430ISD::SRL, dl,
953  VT, N->getOperand(0), N->getOperand(1));
954  }
955 
956  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
957 
958  // Expand the stuff into sequence of shifts.
959  // FIXME: for some shift amounts this might be done better!
960  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
961  SDValue Victim = N->getOperand(0);
962 
963  if (Opc == ISD::SRL && ShiftAmount) {
964  // Emit a special goodness here:
965  // srl A, 1 => clrc; rrc A
966  Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
967  ShiftAmount -= 1;
968  }
969 
970  while (ShiftAmount--)
971  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
972  dl, VT, Victim);
973 
974  return Victim;
975 }
976 
978  SelectionDAG &DAG) const {
979  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
980  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
981  auto PtrVT = getPointerTy(DAG.getDataLayout());
982 
983  // Create the TargetGlobalAddress node, folding in the constant offset.
984  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
985  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
986 }
987 
989  SelectionDAG &DAG) const {
990  SDLoc dl(Op);
991  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
992  auto PtrVT = getPointerTy(DAG.getDataLayout());
993  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
994 
995  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
996 }
997 
999  SelectionDAG &DAG) const {
1000  SDLoc dl(Op);
1001  auto PtrVT = getPointerTy(DAG.getDataLayout());
1002  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1003  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1004 
1005  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1006 }
1007 
1008 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1009  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1010  // FIXME: Handle bittests someday
1011  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1012 
1013  // FIXME: Handle jump negative someday
1015  switch (CC) {
1016  default: llvm_unreachable("Invalid integer condition!");
1017  case ISD::SETEQ:
1018  TCC = MSP430CC::COND_E; // aka COND_Z
1019  // Minor optimization: if LHS is a constant, swap operands, then the
1020  // constant can be folded into comparison.
1021  if (LHS.getOpcode() == ISD::Constant)
1022  std::swap(LHS, RHS);
1023  break;
1024  case ISD::SETNE:
1025  TCC = MSP430CC::COND_NE; // aka COND_NZ
1026  // Minor optimization: if LHS is a constant, swap operands, then the
1027  // constant can be folded into comparison.
1028  if (LHS.getOpcode() == ISD::Constant)
1029  std::swap(LHS, RHS);
1030  break;
1031  case ISD::SETULE:
1032  std::swap(LHS, RHS);
1034  case ISD::SETUGE:
1035  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1036  // fold constant into instruction.
1037  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1038  LHS = RHS;
1039  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1040  TCC = MSP430CC::COND_LO;
1041  break;
1042  }
1043  TCC = MSP430CC::COND_HS; // aka COND_C
1044  break;
1045  case ISD::SETUGT:
1046  std::swap(LHS, RHS);
1048  case ISD::SETULT:
1049  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1050  // fold constant into instruction.
1051  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1052  LHS = RHS;
1053  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1054  TCC = MSP430CC::COND_HS;
1055  break;
1056  }
1057  TCC = MSP430CC::COND_LO; // aka COND_NC
1058  break;
1059  case ISD::SETLE:
1060  std::swap(LHS, RHS);
1062  case ISD::SETGE:
1063  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1064  // fold constant into instruction.
1065  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1066  LHS = RHS;
1067  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1068  TCC = MSP430CC::COND_L;
1069  break;
1070  }
1071  TCC = MSP430CC::COND_GE;
1072  break;
1073  case ISD::SETGT:
1074  std::swap(LHS, RHS);
1076  case ISD::SETLT:
1077  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1078  // fold constant into instruction.
1079  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1080  LHS = RHS;
1081  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1082  TCC = MSP430CC::COND_GE;
1083  break;
1084  }
1085  TCC = MSP430CC::COND_L;
1086  break;
1087  }
1088 
1089  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1090  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1091 }
1092 
1093 
1095  SDValue Chain = Op.getOperand(0);
1096  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1097  SDValue LHS = Op.getOperand(2);
1098  SDValue RHS = Op.getOperand(3);
1099  SDValue Dest = Op.getOperand(4);
1100  SDLoc dl (Op);
1101 
1102  SDValue TargetCC;
1103  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1104 
1105  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1106  Chain, Dest, TargetCC, Flag);
1107 }
1108 
1110  SDValue LHS = Op.getOperand(0);
1111  SDValue RHS = Op.getOperand(1);
1112  SDLoc dl (Op);
1113 
1114  // If we are doing an AND and testing against zero, then the CMP
1115  // will not be generated. The AND (or BIT) will generate the condition codes,
1116  // but they are different from CMP.
1117  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1118  // lowering & isel wouldn't diverge.
1119  bool andCC = false;
1120  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1121  if (RHSC->isNullValue() && LHS.hasOneUse() &&
1122  (LHS.getOpcode() == ISD::AND ||
1123  (LHS.getOpcode() == ISD::TRUNCATE &&
1124  LHS.getOperand(0).getOpcode() == ISD::AND))) {
1125  andCC = true;
1126  }
1127  }
1128  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1129  SDValue TargetCC;
1130  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1131 
1132  // Get the condition codes directly from the status register, if its easy.
1133  // Otherwise a branch will be generated. Note that the AND and BIT
1134  // instructions generate different flags than CMP, the carry bit can be used
1135  // for NE/EQ.
1136  bool Invert = false;
1137  bool Shift = false;
1138  bool Convert = true;
1139  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1140  default:
1141  Convert = false;
1142  break;
1143  case MSP430CC::COND_HS:
1144  // Res = SR & 1, no processing is required
1145  break;
1146  case MSP430CC::COND_LO:
1147  // Res = ~(SR & 1)
1148  Invert = true;
1149  break;
1150  case MSP430CC::COND_NE:
1151  if (andCC) {
1152  // C = ~Z, thus Res = SR & 1, no processing is required
1153  } else {
1154  // Res = ~((SR >> 1) & 1)
1155  Shift = true;
1156  Invert = true;
1157  }
1158  break;
1159  case MSP430CC::COND_E:
1160  Shift = true;
1161  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1162  // Res = (SR >> 1) & 1 is 1 word shorter.
1163  break;
1164  }
1165  EVT VT = Op.getValueType();
1166  SDValue One = DAG.getConstant(1, dl, VT);
1167  if (Convert) {
1168  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1169  MVT::i16, Flag);
1170  if (Shift)
1171  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1172  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1173  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1174  if (Invert)
1175  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1176  return SR;
1177  } else {
1178  SDValue Zero = DAG.getConstant(0, dl, VT);
1179  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1180  SDValue Ops[] = {One, Zero, TargetCC, Flag};
1181  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1182  }
1183 }
1184 
1186  SelectionDAG &DAG) const {
1187  SDValue LHS = Op.getOperand(0);
1188  SDValue RHS = Op.getOperand(1);
1189  SDValue TrueV = Op.getOperand(2);
1190  SDValue FalseV = Op.getOperand(3);
1191  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1192  SDLoc dl (Op);
1193 
1194  SDValue TargetCC;
1195  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1196 
1197  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1198  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1199 
1200  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1201 }
1202 
1204  SelectionDAG &DAG) const {
1205  SDValue Val = Op.getOperand(0);
1206  EVT VT = Op.getValueType();
1207  SDLoc dl(Op);
1208 
1209  assert(VT == MVT::i16 && "Only support i16 for now!");
1210 
1211  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1212  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1213  DAG.getValueType(Val.getValueType()));
1214 }
1215 
1216 SDValue
1218  MachineFunction &MF = DAG.getMachineFunction();
1220  int ReturnAddrIndex = FuncInfo->getRAIndex();
1221  auto PtrVT = getPointerTy(MF.getDataLayout());
1222 
1223  if (ReturnAddrIndex == 0) {
1224  // Set up a frame object for the return address.
1225  uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1226  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1227  true);
1228  FuncInfo->setRAIndex(ReturnAddrIndex);
1229  }
1230 
1231  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1232 }
1233 
1235  SelectionDAG &DAG) const {
1237  MFI.setReturnAddressIsTaken(true);
1238 
1240  return SDValue();
1241 
1242  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1243  SDLoc dl(Op);
1244  auto PtrVT = getPointerTy(DAG.getDataLayout());
1245 
1246  if (Depth > 0) {
1247  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1248  SDValue Offset =
1250  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1251  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1252  MachinePointerInfo());
1253  }
1254 
1255  // Just load the return address.
1256  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1257  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1258  MachinePointerInfo());
1259 }
1260 
1262  SelectionDAG &DAG) const {
1264  MFI.setFrameAddressIsTaken(true);
1265 
1266  EVT VT = Op.getValueType();
1267  SDLoc dl(Op); // FIXME probably not meaningful
1268  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1269  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1270  MSP430::FP, VT);
1271  while (Depth--)
1272  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1273  MachinePointerInfo());
1274  return FrameAddr;
1275 }
1276 
1278  SelectionDAG &DAG) const {
1279  MachineFunction &MF = DAG.getMachineFunction();
1281  auto PtrVT = getPointerTy(DAG.getDataLayout());
1282 
1283  // Frame index of first vararg argument
1285  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1286  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1287 
1288  // Create a store of the frame index to the location operand
1289  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1290  MachinePointerInfo(SV));
1291 }
1292 
1294  SelectionDAG &DAG) const {
1295  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1296  auto PtrVT = getPointerTy(DAG.getDataLayout());
1297  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1298  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1299 }
1300 
1301 /// getPostIndexedAddressParts - returns true by value, base pointer and
1302 /// offset pointer and addressing mode by reference if this node can be
1303 /// combined with a load / store to form a post-indexed load / store.
1304 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1305  SDValue &Base,
1306  SDValue &Offset,
1307  ISD::MemIndexedMode &AM,
1308  SelectionDAG &DAG) const {
1309 
1310  LoadSDNode *LD = cast<LoadSDNode>(N);
1311  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1312  return false;
1313 
1314  EVT VT = LD->getMemoryVT();
1315  if (VT != MVT::i8 && VT != MVT::i16)
1316  return false;
1317 
1318  if (Op->getOpcode() != ISD::ADD)
1319  return false;
1320 
1321  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1322  uint64_t RHSC = RHS->getZExtValue();
1323  if ((VT == MVT::i16 && RHSC != 2) ||
1324  (VT == MVT::i8 && RHSC != 1))
1325  return false;
1326 
1327  Base = Op->getOperand(0);
1328  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1329  AM = ISD::POST_INC;
1330  return true;
1331  }
1332 
1333  return false;
1334 }
1335 
1336 
1337 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1338  switch ((MSP430ISD::NodeType)Opcode) {
1339  case MSP430ISD::FIRST_NUMBER: break;
1340  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1341  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1342  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1343  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1344  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1345  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1346  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1347  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1348  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1349  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1350  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1351  case MSP430ISD::SHL: return "MSP430ISD::SHL";
1352  case MSP430ISD::SRA: return "MSP430ISD::SRA";
1353  case MSP430ISD::SRL: return "MSP430ISD::SRL";
1354  }
1355  return nullptr;
1356 }
1357 
1359  Type *Ty2) const {
1360  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1361  return false;
1362 
1363  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1364 }
1365 
1367  if (!VT1.isInteger() || !VT2.isInteger())
1368  return false;
1369 
1370  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1371 }
1372 
1374  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1375  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1376 }
1377 
1379  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1380  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1381 }
1382 
1384  return isZExtFree(Val.getValueType(), VT2);
1385 }
1386 
1387 //===----------------------------------------------------------------------===//
1388 // Other Lowering Code
1389 //===----------------------------------------------------------------------===//
1390 
1393  MachineBasicBlock *BB) const {
1394  MachineFunction *F = BB->getParent();
1395  MachineRegisterInfo &RI = F->getRegInfo();
1396  DebugLoc dl = MI.getDebugLoc();
1397  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1398 
1399  unsigned Opc;
1400  const TargetRegisterClass * RC;
1401  switch (MI.getOpcode()) {
1402  default: llvm_unreachable("Invalid shift opcode!");
1403  case MSP430::Shl8:
1404  Opc = MSP430::SHL8r1;
1405  RC = &MSP430::GR8RegClass;
1406  break;
1407  case MSP430::Shl16:
1408  Opc = MSP430::SHL16r1;
1409  RC = &MSP430::GR16RegClass;
1410  break;
1411  case MSP430::Sra8:
1412  Opc = MSP430::SAR8r1;
1413  RC = &MSP430::GR8RegClass;
1414  break;
1415  case MSP430::Sra16:
1416  Opc = MSP430::SAR16r1;
1417  RC = &MSP430::GR16RegClass;
1418  break;
1419  case MSP430::Srl8:
1420  Opc = MSP430::SAR8r1c;
1421  RC = &MSP430::GR8RegClass;
1422  break;
1423  case MSP430::Srl16:
1424  Opc = MSP430::SAR16r1c;
1425  RC = &MSP430::GR16RegClass;
1426  break;
1427  }
1428 
1429  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1431 
1432  // Create loop block
1433  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1434  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1435 
1436  F->insert(I, LoopBB);
1437  F->insert(I, RemBB);
1438 
1439  // Update machine-CFG edges by transferring all successors of the current
1440  // block to the block containing instructions after shift.
1441  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1442  BB->end());
1444 
1445  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1446  BB->addSuccessor(LoopBB);
1447  BB->addSuccessor(RemBB);
1448  LoopBB->addSuccessor(RemBB);
1449  LoopBB->addSuccessor(LoopBB);
1450 
1451  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1452  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1453  unsigned ShiftReg = RI.createVirtualRegister(RC);
1454  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1455  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1456  unsigned SrcReg = MI.getOperand(1).getReg();
1457  unsigned DstReg = MI.getOperand(0).getReg();
1458 
1459  // BB:
1460  // cmp 0, N
1461  // je RemBB
1462  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1463  .addReg(ShiftAmtSrcReg).addImm(0);
1464  BuildMI(BB, dl, TII.get(MSP430::JCC))
1465  .addMBB(RemBB)
1467 
1468  // LoopBB:
1469  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1470  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1471  // ShiftReg2 = shift ShiftReg
1472  // ShiftAmt2 = ShiftAmt - 1;
1473  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1474  .addReg(SrcReg).addMBB(BB)
1475  .addReg(ShiftReg2).addMBB(LoopBB);
1476  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1477  .addReg(ShiftAmtSrcReg).addMBB(BB)
1478  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1479  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1480  .addReg(ShiftReg);
1481  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1482  .addReg(ShiftAmtReg).addImm(1);
1483  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1484  .addMBB(LoopBB)
1486 
1487  // RemBB:
1488  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1489  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1490  .addReg(SrcReg).addMBB(BB)
1491  .addReg(ShiftReg2).addMBB(LoopBB);
1492 
1493  MI.eraseFromParent(); // The pseudo instruction is gone now.
1494  return RemBB;
1495 }
1496 
1499  MachineBasicBlock *BB) const {
1500  unsigned Opc = MI.getOpcode();
1501 
1502  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1503  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1504  Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1505  return EmitShiftInstr(MI, BB);
1506 
1507  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1508  DebugLoc dl = MI.getDebugLoc();
1509 
1510  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1511  "Unexpected instr type to insert");
1512 
1513  // To "insert" a SELECT instruction, we actually have to insert the diamond
1514  // control-flow pattern. The incoming instruction knows the destination vreg
1515  // to set, the condition code register to branch on, the true/false values to
1516  // select between, and a branch opcode to use.
1517  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1519 
1520  // thisMBB:
1521  // ...
1522  // TrueVal = ...
1523  // cmpTY ccX, r1, r2
1524  // jCC copy1MBB
1525  // fallthrough --> copy0MBB
1526  MachineBasicBlock *thisMBB = BB;
1527  MachineFunction *F = BB->getParent();
1528  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1529  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1530  F->insert(I, copy0MBB);
1531  F->insert(I, copy1MBB);
1532  // Update machine-CFG edges by transferring all successors of the current
1533  // block to the new block which will contain the Phi node for the select.
1534  copy1MBB->splice(copy1MBB->begin(), BB,
1535  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1536  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1537  // Next, add the true and fallthrough blocks as its successors.
1538  BB->addSuccessor(copy0MBB);
1539  BB->addSuccessor(copy1MBB);
1540 
1541  BuildMI(BB, dl, TII.get(MSP430::JCC))
1542  .addMBB(copy1MBB)
1543  .addImm(MI.getOperand(3).getImm());
1544 
1545  // copy0MBB:
1546  // %FalseValue = ...
1547  // # fallthrough to copy1MBB
1548  BB = copy0MBB;
1549 
1550  // Update machine-CFG edges
1551  BB->addSuccessor(copy1MBB);
1552 
1553  // copy1MBB:
1554  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1555  // ...
1556  BB = copy1MBB;
1557  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1558  .addReg(MI.getOperand(2).getReg())
1559  .addMBB(copy0MBB)
1560  .addReg(MI.getOperand(1).getReg())
1561  .addMBB(thisMBB);
1562 
1563  MI.eraseFromParent(); // The pseudo instruction is gone now.
1564  return BB;
1565 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
Definition: SmallVector.h:212
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:814
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:268
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool hasHWMult16() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
A debug info location.
Definition: DebugLoc.h:34
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:141
F(f)
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool hasHWMult32() const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:511
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:136
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:433
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:813
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:106
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:379
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:446
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
unsigned getSizeInBits() const
Same as RET_FLAG, but used for returning from ISRs.
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it&#39;s free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:249
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:59
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:695
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:605
const SDValue & getOperand(unsigned Num) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:802
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:120
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:82
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:686
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:611
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
bool isVarArg() const
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:720
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:611
const DataFlowGraph & G
Definition: RDFGraph.cpp:211
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
CallingConv::ID getCallingConv() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:657
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:923
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
unsigned getByValAlign() const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
bool hasHWMultF5() const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:605
Representation of each machine instruction.
Definition: MachineInstr.h:59
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:691
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:651
SmallVector< SDValue, 32 > OutVals
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:683
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:463
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
Definition: CallingConv.h:212
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
CondCodes
Definition: MSP430.h:23
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:115
LLVM Value Representation.
Definition: Value.h:73
SDValue getRegister(unsigned Reg, EVT VT)
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
Conversion operators.
Definition: ISDOpcodes.h:442
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
SHL, SRA, SRL - Non-constant shifts.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:295
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:600
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:355
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:590