LLVM  9.0.0svn
MSP430ISelLowering.cpp
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1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MSP430TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MSP430ISelLowering.h"
14 #include "MSP430.h"
16 #include "MSP430Subtarget.h"
17 #include "MSP430TargetMachine.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalAlias.h"
30 #include "llvm/IR/GlobalVariable.h"
31 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "msp430-lower"
39 
41  const MSP430Subtarget &STI)
42  : TargetLowering(TM) {
43 
44  // Set up the register classes.
45  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
46  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
47 
48  // Compute derived properties from the register classes
50 
51  // Provide all sorts of operation actions
54  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
55 
56  // We have post-incremented loads / stores.
59 
60  for (MVT VT : MVT::integer_valuetypes()) {
66  }
67 
68  // We don't have any truncstores
70 
99 
106 
113 
115 
116  // FIXME: Implement efficiently multiplication by a constant
127 
140 
141  // varargs support
147 
148  // EABI Libcalls - EABI Section 6.2
149  const struct {
150  const RTLIB::Libcall Op;
151  const char * const Name;
152  const ISD::CondCode Cond;
153  } LibraryCalls[] = {
154  // Floating point conversions - EABI Table 6
155  { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
156  { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
157  // The following is NOT implemented in libgcc
158  //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
159  { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
160  { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
161  // The following is NOT implemented in libgcc
162  //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
163  { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
164  { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
165  // The following is NOT implemented in libgcc
166  //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
167  { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
168  { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
169  // The following is NOT implemented in libgcc
170  //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
171  { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
172  { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
173  // TODO The following IS implemented in libgcc
174  //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
175  { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
176  // TODO The following IS implemented in libgcc but is not in the EABI
177  { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
178  // TODO The following IS implemented in libgcc
179  //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
180  { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
181  // The following IS implemented in libgcc but is not in the EABI
182  { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
183  // TODO The following IS implemented in libgcc
184  //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
185  { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
186  // TODO The following IS implemented in libgcc but is not in the EABI
187  { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
188  // TODO The following IS implemented in libgcc
189  //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
190  { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
191  // The following IS implemented in libgcc but is not in the EABI
192  { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
193 
194  // Floating point comparisons - EABI Table 7
195  { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
196  { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
197  { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
198  { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
199  { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
200  { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
201  { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
202  { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
203  { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
204  { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
205  { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
206  { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
207 
208  // Floating point arithmetic - EABI Table 8
209  { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
210  { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
211  { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
212  { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
213  { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
214  { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
215  { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
216  { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
217  // The following are NOT implemented in libgcc
218  // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
219  // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
220 
221  // Universal Integer Operations - EABI Table 9
222  { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
223  { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
224  { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
225  { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
226  { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
227  { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
228  { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
229  { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
230  { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
231  { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
232  { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
233  { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
234 
235  // Bitwise Operations - EABI Table 10
236  // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
237  { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
238  { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
239  { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
240  // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
241 
242  };
243 
244  for (const auto &LC : LibraryCalls) {
245  setLibcallName(LC.Op, LC.Name);
246  if (LC.Cond != ISD::SETCC_INVALID)
247  setCmpLibcallCC(LC.Op, LC.Cond);
248  }
249 
250  if (STI.hasHWMult16()) {
251  const struct {
252  const RTLIB::Libcall Op;
253  const char * const Name;
254  } LibraryCalls[] = {
255  // Integer Multiply - EABI Table 9
256  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
257  { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
258  { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
259  // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
260  // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
261  };
262  for (const auto &LC : LibraryCalls) {
263  setLibcallName(LC.Op, LC.Name);
264  }
265  } else if (STI.hasHWMult32()) {
266  const struct {
267  const RTLIB::Libcall Op;
268  const char * const Name;
269  } LibraryCalls[] = {
270  // Integer Multiply - EABI Table 9
271  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
272  { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
273  { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
274  // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
275  // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
276  };
277  for (const auto &LC : LibraryCalls) {
278  setLibcallName(LC.Op, LC.Name);
279  }
280  } else if (STI.hasHWMultF5()) {
281  const struct {
282  const RTLIB::Libcall Op;
283  const char * const Name;
284  } LibraryCalls[] = {
285  // Integer Multiply - EABI Table 9
286  { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
287  { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
288  { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
289  // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
290  // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
291  };
292  for (const auto &LC : LibraryCalls) {
293  setLibcallName(LC.Op, LC.Name);
294  }
295  } else { // NoHWMult
296  const struct {
297  const RTLIB::Libcall Op;
298  const char * const Name;
299  } LibraryCalls[] = {
300  // Integer Multiply - EABI Table 9
301  { RTLIB::MUL_I16, "__mspabi_mpyi" },
302  { RTLIB::MUL_I32, "__mspabi_mpyl" },
303  { RTLIB::MUL_I64, "__mspabi_mpyll" },
304  // The __mspabi_mpysl* functions are NOT implemented in libgcc
305  // The __mspabi_mpyul* functions are NOT implemented in libgcc
306  };
307  for (const auto &LC : LibraryCalls) {
308  setLibcallName(LC.Op, LC.Name);
309  }
311  }
312 
313  // Several of the runtime library functions use a special calling conv
328  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
329 
332 }
333 
335  SelectionDAG &DAG) const {
336  switch (Op.getOpcode()) {
337  case ISD::SHL: // FALLTHROUGH
338  case ISD::SRL:
339  case ISD::SRA: return LowerShifts(Op, DAG);
340  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
341  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
342  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
343  case ISD::SETCC: return LowerSETCC(Op, DAG);
344  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
345  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
346  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
347  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
348  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
349  case ISD::VASTART: return LowerVASTART(Op, DAG);
350  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
351  default:
352  llvm_unreachable("unimplemented operand");
353  }
354 }
355 
356 //===----------------------------------------------------------------------===//
357 // MSP430 Inline Assembly Support
358 //===----------------------------------------------------------------------===//
359 
360 /// getConstraintType - Given a constraint letter, return the type of
361 /// constraint it is for this target.
364  if (Constraint.size() == 1) {
365  switch (Constraint[0]) {
366  case 'r':
367  return C_RegisterClass;
368  default:
369  break;
370  }
371  }
372  return TargetLowering::getConstraintType(Constraint);
373 }
374 
375 std::pair<unsigned, const TargetRegisterClass *>
377  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
378  if (Constraint.size() == 1) {
379  // GCC Constraint Letters
380  switch (Constraint[0]) {
381  default: break;
382  case 'r': // GENERAL_REGS
383  if (VT == MVT::i8)
384  return std::make_pair(0U, &MSP430::GR8RegClass);
385 
386  return std::make_pair(0U, &MSP430::GR16RegClass);
387  }
388  }
389 
390  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
391 }
392 
393 //===----------------------------------------------------------------------===//
394 // Calling Convention Implementation
395 //===----------------------------------------------------------------------===//
396 
397 #include "MSP430GenCallingConv.inc"
398 
399 /// For each argument in a function store the number of pieces it is composed
400 /// of.
401 template<typename ArgT>
404  unsigned CurrentArgIndex;
405 
406  if (Args.empty())
407  return;
408 
409  CurrentArgIndex = Args[0].OrigArgIndex;
410  Out.push_back(0);
411 
412  for (auto &Arg : Args) {
413  if (CurrentArgIndex == Arg.OrigArgIndex) {
414  Out.back() += 1;
415  } else {
416  Out.push_back(1);
417  CurrentArgIndex = Arg.OrigArgIndex;
418  }
419  }
420 }
421 
422 static void AnalyzeVarArgs(CCState &State,
423  const SmallVectorImpl<ISD::OutputArg> &Outs) {
424  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
425 }
426 
427 static void AnalyzeVarArgs(CCState &State,
429  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
430 }
431 
432 /// Analyze incoming and outgoing function arguments. We need custom C++ code
433 /// to handle special constraints in the ABI like reversing the order of the
434 /// pieces of splitted arguments. In addition, all pieces of a certain argument
435 /// have to be passed either using registers or the stack but never mixing both.
436 template<typename ArgT>
437 static void AnalyzeArguments(CCState &State,
439  const SmallVectorImpl<ArgT> &Args) {
440  static const MCPhysReg CRegList[] = {
441  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
442  };
443  static const unsigned CNbRegs = array_lengthof(CRegList);
444  static const MCPhysReg BuiltinRegList[] = {
445  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
446  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
447  };
448  static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
449 
450  ArrayRef<MCPhysReg> RegList;
451  unsigned NbRegs;
452 
453  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
454  if (Builtin) {
455  RegList = BuiltinRegList;
456  NbRegs = BuiltinNbRegs;
457  } else {
458  RegList = CRegList;
459  NbRegs = CNbRegs;
460  }
461 
462  if (State.isVarArg()) {
463  AnalyzeVarArgs(State, Args);
464  return;
465  }
466 
467  SmallVector<unsigned, 4> ArgsParts;
468  ParseFunctionArgs(Args, ArgsParts);
469 
470  if (Builtin) {
471  assert(ArgsParts.size() == 2 &&
472  "Builtin calling convention requires two arguments");
473  }
474 
475  unsigned RegsLeft = NbRegs;
476  bool UsedStack = false;
477  unsigned ValNo = 0;
478 
479  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
480  MVT ArgVT = Args[ValNo].VT;
481  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
482  MVT LocVT = ArgVT;
484 
485  // Promote i8 to i16
486  if (LocVT == MVT::i8) {
487  LocVT = MVT::i16;
488  if (ArgFlags.isSExt())
489  LocInfo = CCValAssign::SExt;
490  else if (ArgFlags.isZExt())
491  LocInfo = CCValAssign::ZExt;
492  else
493  LocInfo = CCValAssign::AExt;
494  }
495 
496  // Handle byval arguments
497  if (ArgFlags.isByVal()) {
498  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
499  continue;
500  }
501 
502  unsigned Parts = ArgsParts[i];
503 
504  if (Builtin) {
505  assert(Parts == 4 &&
506  "Builtin calling convention requires 64-bit arguments");
507  }
508 
509  if (!UsedStack && Parts == 2 && RegsLeft == 1) {
510  // Special case for 32-bit register split, see EABI section 3.3.3
511  unsigned Reg = State.AllocateReg(RegList);
512  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
513  RegsLeft -= 1;
514 
515  UsedStack = true;
516  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
517  } else if (Parts <= RegsLeft) {
518  for (unsigned j = 0; j < Parts; j++) {
519  unsigned Reg = State.AllocateReg(RegList);
520  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
521  RegsLeft--;
522  }
523  } else {
524  UsedStack = true;
525  for (unsigned j = 0; j < Parts; j++)
526  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
527  }
528  }
529 }
530 
531 static void AnalyzeRetResult(CCState &State,
533  State.AnalyzeCallResult(Ins, RetCC_MSP430);
534 }
535 
536 static void AnalyzeRetResult(CCState &State,
537  const SmallVectorImpl<ISD::OutputArg> &Outs) {
538  State.AnalyzeReturn(Outs, RetCC_MSP430);
539 }
540 
541 template<typename ArgT>
542 static void AnalyzeReturnValues(CCState &State,
544  const SmallVectorImpl<ArgT> &Args) {
545  AnalyzeRetResult(State, Args);
546 }
547 
548 SDValue MSP430TargetLowering::LowerFormalArguments(
549  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
550  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
551  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
552 
553  switch (CallConv) {
554  default:
555  report_fatal_error("Unsupported calling convention");
556  case CallingConv::C:
557  case CallingConv::Fast:
558  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
560  if (Ins.empty())
561  return Chain;
562  report_fatal_error("ISRs cannot have arguments");
563  }
564 }
565 
566 SDValue
567 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
568  SmallVectorImpl<SDValue> &InVals) const {
569  SelectionDAG &DAG = CLI.DAG;
570  SDLoc &dl = CLI.DL;
572  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
574  SDValue Chain = CLI.Chain;
575  SDValue Callee = CLI.Callee;
576  bool &isTailCall = CLI.IsTailCall;
577  CallingConv::ID CallConv = CLI.CallConv;
578  bool isVarArg = CLI.IsVarArg;
579 
580  // MSP430 target does not yet support tail call optimization.
581  isTailCall = false;
582 
583  switch (CallConv) {
584  default:
585  report_fatal_error("Unsupported calling convention");
587  case CallingConv::Fast:
588  case CallingConv::C:
589  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
590  Outs, OutVals, Ins, dl, DAG, InVals);
592  report_fatal_error("ISRs cannot be called directly");
593  }
594 }
595 
596 /// LowerCCCArguments - transform physical registers into virtual registers and
597 /// generate load operations for arguments places on the stack.
598 // FIXME: struct return stuff
599 SDValue MSP430TargetLowering::LowerCCCArguments(
600  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
601  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
602  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
604  MachineFrameInfo &MFI = MF.getFrameInfo();
605  MachineRegisterInfo &RegInfo = MF.getRegInfo();
607 
608  // Assign locations to all of the incoming arguments.
610  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
611  *DAG.getContext());
612  AnalyzeArguments(CCInfo, ArgLocs, Ins);
613 
614  // Create frame index for the start of the first vararg value
615  if (isVarArg) {
616  unsigned Offset = CCInfo.getNextStackOffset();
617  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
618  }
619 
620  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
621  CCValAssign &VA = ArgLocs[i];
622  if (VA.isRegLoc()) {
623  // Arguments passed in registers
624  EVT RegVT = VA.getLocVT();
625  switch (RegVT.getSimpleVT().SimpleTy) {
626  default:
627  {
628 #ifndef NDEBUG
629  errs() << "LowerFormalArguments Unhandled argument type: "
630  << RegVT.getEVTString() << "\n";
631 #endif
632  llvm_unreachable(nullptr);
633  }
634  case MVT::i16:
635  unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
636  RegInfo.addLiveIn(VA.getLocReg(), VReg);
637  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
638 
639  // If this is an 8-bit value, it is really passed promoted to 16
640  // bits. Insert an assert[sz]ext to capture this, then truncate to the
641  // right size.
642  if (VA.getLocInfo() == CCValAssign::SExt)
643  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
644  DAG.getValueType(VA.getValVT()));
645  else if (VA.getLocInfo() == CCValAssign::ZExt)
646  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
647  DAG.getValueType(VA.getValVT()));
648 
649  if (VA.getLocInfo() != CCValAssign::Full)
650  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
651 
652  InVals.push_back(ArgValue);
653  }
654  } else {
655  // Sanity check
656  assert(VA.isMemLoc());
657 
658  SDValue InVal;
659  ISD::ArgFlagsTy Flags = Ins[i].Flags;
660 
661  if (Flags.isByVal()) {
662  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
663  VA.getLocMemOffset(), true);
664  InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
665  } else {
666  // Load the argument to a virtual register
667  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
668  if (ObjSize > 2) {
669  errs() << "LowerFormalArguments Unhandled argument type: "
670  << EVT(VA.getLocVT()).getEVTString()
671  << "\n";
672  }
673  // Create the frame index object for this incoming parameter...
674  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
675 
676  // Create the SelectionDAG nodes corresponding to a load
677  //from this parameter
678  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
679  InVal = DAG.getLoad(
680  VA.getLocVT(), dl, Chain, FIN,
682  }
683 
684  InVals.push_back(InVal);
685  }
686  }
687 
688  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
689  if (Ins[i].Flags.isSRet()) {
690  unsigned Reg = FuncInfo->getSRetReturnReg();
691  if (!Reg) {
694  FuncInfo->setSRetReturnReg(Reg);
695  }
696  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
697  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
698  }
699  }
700 
701  return Chain;
702 }
703 
704 bool
705 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
706  MachineFunction &MF,
707  bool IsVarArg,
709  LLVMContext &Context) const {
711  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
712  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
713 }
714 
715 SDValue
716 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
717  bool isVarArg,
719  const SmallVectorImpl<SDValue> &OutVals,
720  const SDLoc &dl, SelectionDAG &DAG) const {
721 
723 
724  // CCValAssign - represent the assignment of the return value to a location
726 
727  // ISRs cannot return any value.
728  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
729  report_fatal_error("ISRs cannot return any value");
730 
731  // CCState - Info about the registers and stack slot.
732  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
733  *DAG.getContext());
734 
735  // Analize return values.
736  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
737 
738  SDValue Flag;
739  SmallVector<SDValue, 4> RetOps(1, Chain);
740 
741  // Copy the result values into the output registers.
742  for (unsigned i = 0; i != RVLocs.size(); ++i) {
743  CCValAssign &VA = RVLocs[i];
744  assert(VA.isRegLoc() && "Can only return in registers!");
745 
746  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
747  OutVals[i], Flag);
748 
749  // Guarantee that all emitted copies are stuck together,
750  // avoiding something bad.
751  Flag = Chain.getValue(1);
752  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
753  }
754 
755  if (MF.getFunction().hasStructRetAttr()) {
757  unsigned Reg = FuncInfo->getSRetReturnReg();
758 
759  if (!Reg)
760  llvm_unreachable("sret virtual register not created in entry block");
761 
762  SDValue Val =
763  DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
764  unsigned R12 = MSP430::R12;
765 
766  Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
767  Flag = Chain.getValue(1);
768  RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
769  }
770 
771  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
773 
774  RetOps[0] = Chain; // Update chain.
775 
776  // Add the flag if we have it.
777  if (Flag.getNode())
778  RetOps.push_back(Flag);
779 
780  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
781 }
782 
783 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
784 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
785 SDValue MSP430TargetLowering::LowerCCCCallTo(
786  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
787  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
788  const SmallVectorImpl<SDValue> &OutVals,
789  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
790  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
791  // Analyze operands of the call, assigning locations to each operand.
793  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
794  *DAG.getContext());
795  AnalyzeArguments(CCInfo, ArgLocs, Outs);
796 
797  // Get a count of how many bytes are to be pushed on the stack.
798  unsigned NumBytes = CCInfo.getNextStackOffset();
799  auto PtrVT = getPointerTy(DAG.getDataLayout());
800 
801  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
802 
804  SmallVector<SDValue, 12> MemOpChains;
805  SDValue StackPtr;
806 
807  // Walk the register/memloc assignments, inserting copies/loads.
808  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
809  CCValAssign &VA = ArgLocs[i];
810 
811  SDValue Arg = OutVals[i];
812 
813  // Promote the value if needed.
814  switch (VA.getLocInfo()) {
815  default: llvm_unreachable("Unknown loc info!");
816  case CCValAssign::Full: break;
817  case CCValAssign::SExt:
818  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
819  break;
820  case CCValAssign::ZExt:
821  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
822  break;
823  case CCValAssign::AExt:
824  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
825  break;
826  }
827 
828  // Arguments that can be passed on register must be kept at RegsToPass
829  // vector
830  if (VA.isRegLoc()) {
831  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
832  } else {
833  assert(VA.isMemLoc());
834 
835  if (!StackPtr.getNode())
836  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
837 
838  SDValue PtrOff =
839  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
840  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
841 
842  SDValue MemOp;
843  ISD::ArgFlagsTy Flags = Outs[i].Flags;
844 
845  if (Flags.isByVal()) {
846  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
847  MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
848  Flags.getByValAlign(),
849  /*isVolatile*/false,
850  /*AlwaysInline=*/true,
851  /*isTailCall=*/false,
854  } else {
855  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
856  }
857 
858  MemOpChains.push_back(MemOp);
859  }
860  }
861 
862  // Transform all store nodes into one single node because all store nodes are
863  // independent of each other.
864  if (!MemOpChains.empty())
865  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
866 
867  // Build a sequence of copy-to-reg nodes chained together with token chain and
868  // flag operands which copy the outgoing args into registers. The InFlag in
869  // necessary since all emitted instructions must be stuck together.
870  SDValue InFlag;
871  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
872  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
873  RegsToPass[i].second, InFlag);
874  InFlag = Chain.getValue(1);
875  }
876 
877  // If the callee is a GlobalAddress node (quite common, every direct call is)
878  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
879  // Likewise ExternalSymbol -> TargetExternalSymbol.
880  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
881  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
882  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
883  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
884 
885  // Returns a chain & a flag for retval copy to use.
886  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
888  Ops.push_back(Chain);
889  Ops.push_back(Callee);
890 
891  // Add argument registers to the end of the list so that they are
892  // known live into the call.
893  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
894  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
895  RegsToPass[i].second.getValueType()));
896 
897  if (InFlag.getNode())
898  Ops.push_back(InFlag);
899 
900  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
901  InFlag = Chain.getValue(1);
902 
903  // Create the CALLSEQ_END node.
904  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
905  DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
906  InFlag = Chain.getValue(1);
907 
908  // Handle result values, copying them out of physregs into vregs that we
909  // return.
910  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
911  DAG, InVals);
912 }
913 
914 /// LowerCallResult - Lower the result values of a call into the
915 /// appropriate copies out of appropriate physical registers.
916 ///
917 SDValue MSP430TargetLowering::LowerCallResult(
918  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
919  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
920  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
921 
922  // Assign locations to each value returned by this call.
924  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
925  *DAG.getContext());
926 
927  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
928 
929  // Copy all of the result registers out of their specified physreg.
930  for (unsigned i = 0; i != RVLocs.size(); ++i) {
931  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
932  RVLocs[i].getValVT(), InFlag).getValue(1);
933  InFlag = Chain.getValue(2);
934  InVals.push_back(Chain.getValue(0));
935  }
936 
937  return Chain;
938 }
939 
941  SelectionDAG &DAG) const {
942  unsigned Opc = Op.getOpcode();
943  SDNode* N = Op.getNode();
944  EVT VT = Op.getValueType();
945  SDLoc dl(N);
946 
947  // Expand non-constant shifts to loops:
948  if (!isa<ConstantSDNode>(N->getOperand(1)))
949  return Op;
950 
951  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
952 
953  // Expand the stuff into sequence of shifts.
954  SDValue Victim = N->getOperand(0);
955 
956  if (ShiftAmount >= 8) {
957  assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
958  switch(Opc) {
959  default:
960  llvm_unreachable("Unknown shift");
961  case ISD::SHL:
962  // foo << (8 + N) => swpb(zext(foo)) << N
963  Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
964  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
965  break;
966  case ISD::SRA:
967  case ISD::SRL:
968  // foo >> (8 + N) => sxt(swpb(foo)) >> N
969  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
970  Victim = (Opc == ISD::SRA)
971  ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
972  DAG.getValueType(MVT::i8))
973  : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
974  break;
975  }
976  ShiftAmount -= 8;
977  }
978 
979  if (Opc == ISD::SRL && ShiftAmount) {
980  // Emit a special goodness here:
981  // srl A, 1 => clrc; rrc A
982  Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
983  ShiftAmount -= 1;
984  }
985 
986  while (ShiftAmount--)
987  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
988  dl, VT, Victim);
989 
990  return Victim;
991 }
992 
994  SelectionDAG &DAG) const {
995  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
996  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
997  auto PtrVT = getPointerTy(DAG.getDataLayout());
998 
999  // Create the TargetGlobalAddress node, folding in the constant offset.
1000  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1001  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1002 }
1003 
1005  SelectionDAG &DAG) const {
1006  SDLoc dl(Op);
1007  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1008  auto PtrVT = getPointerTy(DAG.getDataLayout());
1009  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1010 
1011  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1012 }
1013 
1015  SelectionDAG &DAG) const {
1016  SDLoc dl(Op);
1017  auto PtrVT = getPointerTy(DAG.getDataLayout());
1018  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1019  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1020 
1021  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1022 }
1023 
1024 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1025  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1026  // FIXME: Handle bittests someday
1027  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1028 
1029  // FIXME: Handle jump negative someday
1031  switch (CC) {
1032  default: llvm_unreachable("Invalid integer condition!");
1033  case ISD::SETEQ:
1034  TCC = MSP430CC::COND_E; // aka COND_Z
1035  // Minor optimization: if LHS is a constant, swap operands, then the
1036  // constant can be folded into comparison.
1037  if (LHS.getOpcode() == ISD::Constant)
1038  std::swap(LHS, RHS);
1039  break;
1040  case ISD::SETNE:
1041  TCC = MSP430CC::COND_NE; // aka COND_NZ
1042  // Minor optimization: if LHS is a constant, swap operands, then the
1043  // constant can be folded into comparison.
1044  if (LHS.getOpcode() == ISD::Constant)
1045  std::swap(LHS, RHS);
1046  break;
1047  case ISD::SETULE:
1048  std::swap(LHS, RHS);
1050  case ISD::SETUGE:
1051  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1052  // fold constant into instruction.
1053  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1054  LHS = RHS;
1055  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1056  TCC = MSP430CC::COND_LO;
1057  break;
1058  }
1059  TCC = MSP430CC::COND_HS; // aka COND_C
1060  break;
1061  case ISD::SETUGT:
1062  std::swap(LHS, RHS);
1064  case ISD::SETULT:
1065  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1066  // fold constant into instruction.
1067  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1068  LHS = RHS;
1069  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1070  TCC = MSP430CC::COND_HS;
1071  break;
1072  }
1073  TCC = MSP430CC::COND_LO; // aka COND_NC
1074  break;
1075  case ISD::SETLE:
1076  std::swap(LHS, RHS);
1078  case ISD::SETGE:
1079  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1080  // fold constant into instruction.
1081  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1082  LHS = RHS;
1083  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1084  TCC = MSP430CC::COND_L;
1085  break;
1086  }
1087  TCC = MSP430CC::COND_GE;
1088  break;
1089  case ISD::SETGT:
1090  std::swap(LHS, RHS);
1092  case ISD::SETLT:
1093  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1094  // fold constant into instruction.
1095  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1096  LHS = RHS;
1097  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1098  TCC = MSP430CC::COND_GE;
1099  break;
1100  }
1101  TCC = MSP430CC::COND_L;
1102  break;
1103  }
1104 
1105  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1106  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1107 }
1108 
1109 
1111  SDValue Chain = Op.getOperand(0);
1112  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1113  SDValue LHS = Op.getOperand(2);
1114  SDValue RHS = Op.getOperand(3);
1115  SDValue Dest = Op.getOperand(4);
1116  SDLoc dl (Op);
1117 
1118  SDValue TargetCC;
1119  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1120 
1121  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1122  Chain, Dest, TargetCC, Flag);
1123 }
1124 
1126  SDValue LHS = Op.getOperand(0);
1127  SDValue RHS = Op.getOperand(1);
1128  SDLoc dl (Op);
1129 
1130  // If we are doing an AND and testing against zero, then the CMP
1131  // will not be generated. The AND (or BIT) will generate the condition codes,
1132  // but they are different from CMP.
1133  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1134  // lowering & isel wouldn't diverge.
1135  bool andCC = false;
1136  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1137  if (RHSC->isNullValue() && LHS.hasOneUse() &&
1138  (LHS.getOpcode() == ISD::AND ||
1139  (LHS.getOpcode() == ISD::TRUNCATE &&
1140  LHS.getOperand(0).getOpcode() == ISD::AND))) {
1141  andCC = true;
1142  }
1143  }
1144  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1145  SDValue TargetCC;
1146  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1147 
1148  // Get the condition codes directly from the status register, if its easy.
1149  // Otherwise a branch will be generated. Note that the AND and BIT
1150  // instructions generate different flags than CMP, the carry bit can be used
1151  // for NE/EQ.
1152  bool Invert = false;
1153  bool Shift = false;
1154  bool Convert = true;
1155  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1156  default:
1157  Convert = false;
1158  break;
1159  case MSP430CC::COND_HS:
1160  // Res = SR & 1, no processing is required
1161  break;
1162  case MSP430CC::COND_LO:
1163  // Res = ~(SR & 1)
1164  Invert = true;
1165  break;
1166  case MSP430CC::COND_NE:
1167  if (andCC) {
1168  // C = ~Z, thus Res = SR & 1, no processing is required
1169  } else {
1170  // Res = ~((SR >> 1) & 1)
1171  Shift = true;
1172  Invert = true;
1173  }
1174  break;
1175  case MSP430CC::COND_E:
1176  Shift = true;
1177  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1178  // Res = (SR >> 1) & 1 is 1 word shorter.
1179  break;
1180  }
1181  EVT VT = Op.getValueType();
1182  SDValue One = DAG.getConstant(1, dl, VT);
1183  if (Convert) {
1184  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1185  MVT::i16, Flag);
1186  if (Shift)
1187  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1188  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1189  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1190  if (Invert)
1191  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1192  return SR;
1193  } else {
1194  SDValue Zero = DAG.getConstant(0, dl, VT);
1195  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1196  SDValue Ops[] = {One, Zero, TargetCC, Flag};
1197  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1198  }
1199 }
1200 
1202  SelectionDAG &DAG) const {
1203  SDValue LHS = Op.getOperand(0);
1204  SDValue RHS = Op.getOperand(1);
1205  SDValue TrueV = Op.getOperand(2);
1206  SDValue FalseV = Op.getOperand(3);
1207  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1208  SDLoc dl (Op);
1209 
1210  SDValue TargetCC;
1211  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1212 
1213  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1214  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1215 
1216  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1217 }
1218 
1220  SelectionDAG &DAG) const {
1221  SDValue Val = Op.getOperand(0);
1222  EVT VT = Op.getValueType();
1223  SDLoc dl(Op);
1224 
1225  assert(VT == MVT::i16 && "Only support i16 for now!");
1226 
1227  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1228  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1229  DAG.getValueType(Val.getValueType()));
1230 }
1231 
1232 SDValue
1234  MachineFunction &MF = DAG.getMachineFunction();
1236  int ReturnAddrIndex = FuncInfo->getRAIndex();
1237  auto PtrVT = getPointerTy(MF.getDataLayout());
1238 
1239  if (ReturnAddrIndex == 0) {
1240  // Set up a frame object for the return address.
1241  uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1242  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1243  true);
1244  FuncInfo->setRAIndex(ReturnAddrIndex);
1245  }
1246 
1247  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1248 }
1249 
1251  SelectionDAG &DAG) const {
1253  MFI.setReturnAddressIsTaken(true);
1254 
1256  return SDValue();
1257 
1258  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1259  SDLoc dl(Op);
1260  auto PtrVT = getPointerTy(DAG.getDataLayout());
1261 
1262  if (Depth > 0) {
1263  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1264  SDValue Offset =
1266  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1267  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1268  MachinePointerInfo());
1269  }
1270 
1271  // Just load the return address.
1272  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1273  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1274  MachinePointerInfo());
1275 }
1276 
1278  SelectionDAG &DAG) const {
1280  MFI.setFrameAddressIsTaken(true);
1281 
1282  EVT VT = Op.getValueType();
1283  SDLoc dl(Op); // FIXME probably not meaningful
1284  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1285  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1286  MSP430::FP, VT);
1287  while (Depth--)
1288  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1289  MachinePointerInfo());
1290  return FrameAddr;
1291 }
1292 
1294  SelectionDAG &DAG) const {
1295  MachineFunction &MF = DAG.getMachineFunction();
1297  auto PtrVT = getPointerTy(DAG.getDataLayout());
1298 
1299  // Frame index of first vararg argument
1301  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1302  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1303 
1304  // Create a store of the frame index to the location operand
1305  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1306  MachinePointerInfo(SV));
1307 }
1308 
1310  SelectionDAG &DAG) const {
1311  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1312  auto PtrVT = getPointerTy(DAG.getDataLayout());
1313  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1314  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1315 }
1316 
1317 /// getPostIndexedAddressParts - returns true by value, base pointer and
1318 /// offset pointer and addressing mode by reference if this node can be
1319 /// combined with a load / store to form a post-indexed load / store.
1320 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1321  SDValue &Base,
1322  SDValue &Offset,
1323  ISD::MemIndexedMode &AM,
1324  SelectionDAG &DAG) const {
1325 
1326  LoadSDNode *LD = cast<LoadSDNode>(N);
1327  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1328  return false;
1329 
1330  EVT VT = LD->getMemoryVT();
1331  if (VT != MVT::i8 && VT != MVT::i16)
1332  return false;
1333 
1334  if (Op->getOpcode() != ISD::ADD)
1335  return false;
1336 
1337  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1338  uint64_t RHSC = RHS->getZExtValue();
1339  if ((VT == MVT::i16 && RHSC != 2) ||
1340  (VT == MVT::i8 && RHSC != 1))
1341  return false;
1342 
1343  Base = Op->getOperand(0);
1344  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1345  AM = ISD::POST_INC;
1346  return true;
1347  }
1348 
1349  return false;
1350 }
1351 
1352 
1353 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1354  switch ((MSP430ISD::NodeType)Opcode) {
1355  case MSP430ISD::FIRST_NUMBER: break;
1356  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1357  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1358  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1359  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1360  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1361  case MSP430ISD::RRCL: return "MSP430ISD::RRCL";
1362  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1363  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1364  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1365  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1366  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1367  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1368  case MSP430ISD::DADD: return "MSP430ISD::DADD";
1369  }
1370  return nullptr;
1371 }
1372 
1374  Type *Ty2) const {
1375  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1376  return false;
1377 
1378  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1379 }
1380 
1382  if (!VT1.isInteger() || !VT2.isInteger())
1383  return false;
1384 
1385  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1386 }
1387 
1389  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1390  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1391 }
1392 
1394  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1395  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1396 }
1397 
1399  return isZExtFree(Val.getValueType(), VT2);
1400 }
1401 
1402 //===----------------------------------------------------------------------===//
1403 // Other Lowering Code
1404 //===----------------------------------------------------------------------===//
1405 
1408  MachineBasicBlock *BB) const {
1409  MachineFunction *F = BB->getParent();
1410  MachineRegisterInfo &RI = F->getRegInfo();
1411  DebugLoc dl = MI.getDebugLoc();
1412  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1413 
1414  unsigned Opc;
1415  bool ClearCarry = false;
1416  const TargetRegisterClass * RC;
1417  switch (MI.getOpcode()) {
1418  default: llvm_unreachable("Invalid shift opcode!");
1419  case MSP430::Shl8:
1420  Opc = MSP430::ADD8rr;
1421  RC = &MSP430::GR8RegClass;
1422  break;
1423  case MSP430::Shl16:
1424  Opc = MSP430::ADD16rr;
1425  RC = &MSP430::GR16RegClass;
1426  break;
1427  case MSP430::Sra8:
1428  Opc = MSP430::RRA8r;
1429  RC = &MSP430::GR8RegClass;
1430  break;
1431  case MSP430::Sra16:
1432  Opc = MSP430::RRA16r;
1433  RC = &MSP430::GR16RegClass;
1434  break;
1435  case MSP430::Srl8:
1436  ClearCarry = true;
1437  Opc = MSP430::RRC8r;
1438  RC = &MSP430::GR8RegClass;
1439  break;
1440  case MSP430::Srl16:
1441  ClearCarry = true;
1442  Opc = MSP430::RRC16r;
1443  RC = &MSP430::GR16RegClass;
1444  break;
1445  case MSP430::Rrcl8:
1446  case MSP430::Rrcl16: {
1447  BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1448  .addReg(MSP430::SR).addImm(1);
1449  unsigned SrcReg = MI.getOperand(1).getReg();
1450  unsigned DstReg = MI.getOperand(0).getReg();
1451  unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1452  ? MSP430::RRC16r : MSP430::RRC8r;
1453  BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1454  .addReg(SrcReg);
1455  MI.eraseFromParent(); // The pseudo instruction is gone now.
1456  return BB;
1457  }
1458  }
1459 
1460  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1462 
1463  // Create loop block
1464  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1465  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1466 
1467  F->insert(I, LoopBB);
1468  F->insert(I, RemBB);
1469 
1470  // Update machine-CFG edges by transferring all successors of the current
1471  // block to the block containing instructions after shift.
1472  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1473  BB->end());
1475 
1476  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1477  BB->addSuccessor(LoopBB);
1478  BB->addSuccessor(RemBB);
1479  LoopBB->addSuccessor(RemBB);
1480  LoopBB->addSuccessor(LoopBB);
1481 
1482  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1483  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1484  unsigned ShiftReg = RI.createVirtualRegister(RC);
1485  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1486  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1487  unsigned SrcReg = MI.getOperand(1).getReg();
1488  unsigned DstReg = MI.getOperand(0).getReg();
1489 
1490  // BB:
1491  // cmp 0, N
1492  // je RemBB
1493  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1494  .addReg(ShiftAmtSrcReg).addImm(0);
1495  BuildMI(BB, dl, TII.get(MSP430::JCC))
1496  .addMBB(RemBB)
1498 
1499  // LoopBB:
1500  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1501  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1502  // ShiftReg2 = shift ShiftReg
1503  // ShiftAmt2 = ShiftAmt - 1;
1504  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1505  .addReg(SrcReg).addMBB(BB)
1506  .addReg(ShiftReg2).addMBB(LoopBB);
1507  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1508  .addReg(ShiftAmtSrcReg).addMBB(BB)
1509  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1510  if (ClearCarry)
1511  BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1512  .addReg(MSP430::SR).addImm(1);
1513  if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1514  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1515  .addReg(ShiftReg)
1516  .addReg(ShiftReg);
1517  else
1518  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1519  .addReg(ShiftReg);
1520  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1521  .addReg(ShiftAmtReg).addImm(1);
1522  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1523  .addMBB(LoopBB)
1525 
1526  // RemBB:
1527  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1528  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1529  .addReg(SrcReg).addMBB(BB)
1530  .addReg(ShiftReg2).addMBB(LoopBB);
1531 
1532  MI.eraseFromParent(); // The pseudo instruction is gone now.
1533  return RemBB;
1534 }
1535 
1538  MachineBasicBlock *BB) const {
1539  unsigned Opc = MI.getOpcode();
1540 
1541  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1542  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1543  Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1544  Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1545  return EmitShiftInstr(MI, BB);
1546 
1547  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1548  DebugLoc dl = MI.getDebugLoc();
1549 
1550  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1551  "Unexpected instr type to insert");
1552 
1553  // To "insert" a SELECT instruction, we actually have to insert the diamond
1554  // control-flow pattern. The incoming instruction knows the destination vreg
1555  // to set, the condition code register to branch on, the true/false values to
1556  // select between, and a branch opcode to use.
1557  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1559 
1560  // thisMBB:
1561  // ...
1562  // TrueVal = ...
1563  // cmpTY ccX, r1, r2
1564  // jCC copy1MBB
1565  // fallthrough --> copy0MBB
1566  MachineBasicBlock *thisMBB = BB;
1567  MachineFunction *F = BB->getParent();
1568  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1569  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1570  F->insert(I, copy0MBB);
1571  F->insert(I, copy1MBB);
1572  // Update machine-CFG edges by transferring all successors of the current
1573  // block to the new block which will contain the Phi node for the select.
1574  copy1MBB->splice(copy1MBB->begin(), BB,
1575  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1576  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1577  // Next, add the true and fallthrough blocks as its successors.
1578  BB->addSuccessor(copy0MBB);
1579  BB->addSuccessor(copy1MBB);
1580 
1581  BuildMI(BB, dl, TII.get(MSP430::JCC))
1582  .addMBB(copy1MBB)
1583  .addImm(MI.getOperand(3).getImm());
1584 
1585  // copy0MBB:
1586  // %FalseValue = ...
1587  // # fallthrough to copy1MBB
1588  BB = copy0MBB;
1589 
1590  // Update machine-CFG edges
1591  BB->addSuccessor(copy1MBB);
1592 
1593  // copy1MBB:
1594  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1595  // ...
1596  BB = copy1MBB;
1597  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1598  .addReg(MI.getOperand(2).getReg())
1599  .addMBB(copy0MBB)
1600  .addReg(MI.getOperand(1).getReg())
1601  .addMBB(thisMBB);
1602 
1603  MI.eraseFromParent(); // The pseudo instruction is gone now.
1604  return BB;
1605 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:835
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:651
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:703
unsigned Reg
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool hasHWMult16() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
unsigned second
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
Definition: CallingConv.h:211
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool hasHWMult32() const
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool isMemLoc() const
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:578
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:455
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:839
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:409
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Rotate right via carry, carry gets cleared beforehand by clrc.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:459
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:699
unsigned getSizeInBits() const
Same as RET_FLAG, but used for returning from ISRs.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:397
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it&#39;s free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:336
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
TargetInstrInfo - Interface to description of machine instruction set.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:732
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:628
const SDValue & getOperand(unsigned Num) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:823
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:56
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:81
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:723
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:632
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
bool isVarArg() const
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:645
const DataFlowGraph & G
Definition: RDFGraph.cpp:210
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
CallingConv::ID getCallingConv() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:412
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:678
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
EVT getMemoryVT() const
Return the type of the in-memory value.
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
unsigned getByValAlign() const
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
bool hasHWMultF5() const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:639
Representation of each machine instruction.
Definition: MachineInstr.h:63
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:728
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:672
SmallVector< SDValue, 32 > OutVals
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:704
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:485
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
CondCodes
Definition: MSP430.h:22
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:114
LLVM Value Representation.
Definition: Value.h:72
SDValue getRegister(unsigned Reg, EVT VT)
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:442
Conversion operators.
Definition: ISDOpcodes.h:464
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:473
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
LLVMContext * getContext() const
Definition: SelectionDAG.h:406
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:105
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:621
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:920
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:379
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:624