LLVM  7.0.0svn
SystemZISelLowering.cpp
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1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
18 #include "SystemZTargetMachine.h"
23 #include "llvm/IR/Intrinsics.h"
24 #include "llvm/IR/IntrinsicInst.h"
26 #include "llvm/Support/KnownBits.h"
27 #include <cctype>
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "systemz-lower"
32 
33 namespace {
34 // Represents information about a comparison.
35 struct Comparison {
36  Comparison(SDValue Op0In, SDValue Op1In)
37  : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
38 
39  // The operands to the comparison.
40  SDValue Op0, Op1;
41 
42  // The opcode that should be used to compare Op0 and Op1.
43  unsigned Opcode;
44 
45  // A SystemZICMP value. Only used for integer comparisons.
46  unsigned ICmpType;
47 
48  // The mask of CC values that Opcode can produce.
49  unsigned CCValid;
50 
51  // The mask of CC values for which the original condition is true.
52  unsigned CCMask;
53 };
54 } // end anonymous namespace
55 
56 // Classify VT as either 32 or 64 bit.
57 static bool is32Bit(EVT VT) {
58  switch (VT.getSimpleVT().SimpleTy) {
59  case MVT::i32:
60  return true;
61  case MVT::i64:
62  return false;
63  default:
64  llvm_unreachable("Unsupported type");
65  }
66 }
67 
68 // Return a version of MachineOperand that can be safely used before the
69 // final use.
71  if (Op.isReg())
72  Op.setIsKill(false);
73  return Op;
74 }
75 
77  const SystemZSubtarget &STI)
78  : TargetLowering(TM), Subtarget(STI) {
79  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
80 
81  // Set up the register classes.
82  if (Subtarget.hasHighWord())
83  addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
84  else
85  addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
86  addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
87  if (Subtarget.hasVector()) {
88  addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
89  addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
90  } else {
91  addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
92  addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
93  }
94  if (Subtarget.hasVectorEnhancements1())
95  addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
96  else
97  addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
98 
99  if (Subtarget.hasVector()) {
100  addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
101  addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
102  addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
103  addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
104  addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
105  addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
106  }
107 
108  // Compute derived properties from the register classes
110 
111  // Set up special registers.
113 
114  // TODO: It may be better to default to latency-oriented scheduling, however
115  // LLVM's current latency-oriented scheduler can't handle physreg definitions
116  // such as SystemZ has with CC, so set this to the register-pressure
117  // scheduler, because it can.
119 
122 
123  // Instructions are strings of 2-byte aligned 2-byte values.
125 
126  // Handle operations that are handled in a similar way for all types.
127  for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
129  ++I) {
130  MVT VT = MVT::SimpleValueType(I);
131  if (isTypeLegal(VT)) {
132  // Lower SET_CC into an IPM-based sequence.
134 
135  // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
137 
138  // Lower SELECT_CC and BR_CC into separate comparisons and branches.
141  }
142  }
143 
144  // Expand jump table branches as address arithmetic followed by an
145  // indirect jump.
147 
148  // Expand BRCOND into a BR_CC (see above).
150 
151  // Handle integer types.
152  for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
154  ++I) {
155  MVT VT = MVT::SimpleValueType(I);
156  if (isTypeLegal(VT)) {
157  // Expand individual DIV and REMs into DIVREMs.
164 
165  // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
166  // stores, putting a serialization instruction after the stores.
169 
170  // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
171  // available, or if the operand is constant.
173 
174  // Use POPCNT on z196 and above.
175  if (Subtarget.hasPopulationCount())
177  else
179 
180  // No special instructions for these.
183 
184  // Use *MUL_LOHI where possible instead of MULH*.
189 
190  // Only z196 and above have native support for conversions to unsigned.
191  // On z10, promoting to i64 doesn't generate an inexact condition for
192  // values that are outside the i32 range but in the i64 range, so use
193  // the default expansion.
194  if (!Subtarget.hasFPExtension())
196  }
197  }
198 
199  // Type legalization will convert 8- and 16-bit atomic operations into
200  // forms that operate on i32s (but still keeping the original memory VT).
201  // Lower them into full i32 operations.
213 
214  // Even though i128 is not a legal type, we still need to custom lower
215  // the atomic operations in order to exploit SystemZ instructions.
218 
219  // We can use the CC result of compare-and-swap to implement
220  // the "success" result of ATOMIC_CMP_SWAP_WITH_SUCCESS.
224 
226 
227  // Traps are legal, as we will convert them to "j .+2".
229 
230  // z10 has instructions for signed but not unsigned FP conversion.
231  // Handle unsigned 32-bit types as signed 64-bit types.
232  if (!Subtarget.hasFPExtension()) {
235  }
236 
237  // We have native support for a 64-bit CTLZ, via FLOGR.
240 
241  // Give LowerOperation the chance to replace 64-bit ORs with subregs.
243 
244  // FIXME: Can we support these natively?
248 
249  // We have native instructions for i8, i16 and i32 extensions, but not i1.
251  for (MVT VT : MVT::integer_valuetypes()) {
255  }
256 
257  // Handle the various types of symbolic address.
263 
264  // We need to handle dynamic allocations specially because of the
265  // 160-byte area at the bottom of the stack.
268 
269  // Use custom expanders so that we can force the function to use
270  // a frame pointer.
273 
274  // Handle prefetches with PFD or PFDRL.
276 
277  for (MVT VT : MVT::vector_valuetypes()) {
278  // Assume by default that all vector operations need to be expanded.
279  for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
280  if (getOperationAction(Opcode, VT) == Legal)
281  setOperationAction(Opcode, VT, Expand);
282 
283  // Likewise all truncating stores and extending loads.
284  for (MVT InnerVT : MVT::vector_valuetypes()) {
285  setTruncStoreAction(VT, InnerVT, Expand);
286  setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
287  setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
288  setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
289  }
290 
291  if (isTypeLegal(VT)) {
292  // These operations are legal for anything that can be stored in a
293  // vector register, even if there is no native support for the format
294  // as such. In particular, we can do these for v4f32 even though there
295  // are no specific instructions for that format.
301 
302  // Likewise, except that we need to replace the nodes with something
303  // more specific.
306  }
307  }
308 
309  // Handle integer vector types.
310  for (MVT VT : MVT::integer_vector_valuetypes()) {
311  if (isTypeLegal(VT)) {
312  // These operations have direct equivalents.
317  if (VT != MVT::v2i64)
322  if (Subtarget.hasVectorEnhancements1())
324  else
328 
329  // Convert a GPR scalar to a vector by inserting it into element 0.
331 
332  // Use a series of unpacks for extensions.
335 
336  // Detect shifts by a scalar amount and convert them into
337  // V*_BY_SCALAR.
341 
342  // At present ROTL isn't matched by DAGCombiner. ROTR should be
343  // converted into ROTL.
346 
347  // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
348  // and inverting the result as necessary.
350  }
351  }
352 
353  if (Subtarget.hasVector()) {
354  // There should be no need to check for float types other than v2f64
355  // since <2 x f32> isn't a legal type.
364  }
365 
366  // Handle floating-point types.
367  for (unsigned I = MVT::FIRST_FP_VALUETYPE;
369  ++I) {
370  MVT VT = MVT::SimpleValueType(I);
371  if (isTypeLegal(VT)) {
372  // We can use FI for FRINT.
374 
375  // We can use the extended form of FI for other rounding operations.
376  if (Subtarget.hasFPExtension()) {
382  }
383 
384  // No special instructions for these.
390  }
391  }
392 
393  // Handle floating-point vector types.
394  if (Subtarget.hasVector()) {
395  // Scalar-to-vector conversion is just a subreg.
398 
399  // Some insertions and extractions can be done directly but others
400  // need to go via integers.
405 
406  // These operations have direct equivalents.
421  }
422 
423  // The vector enhancements facility 1 has instructions for these.
424  if (Subtarget.hasVectorEnhancements1()) {
439 
444 
449 
454 
459 
464  }
465 
466  // We have fused multiply-addition for f32 and f64 but not f128.
469  if (Subtarget.hasVectorEnhancements1())
471  else
473 
474  // We don't have a copysign instruction on vector registers.
475  if (Subtarget.hasVectorEnhancements1())
477 
478  // Needed so that we don't try to implement f128 constant loads using
479  // a load-and-extend of a f80 constant (in cases where the constant
480  // would fit in an f80).
481  for (MVT VT : MVT::fp_valuetypes())
483 
484  // We don't have extending load instruction on vector registers.
485  if (Subtarget.hasVectorEnhancements1()) {
488  }
489 
490  // Floating-point truncation and stores need to be done separately.
494 
495  // We have 64-bit FPR<->GPR moves, but need special handling for
496  // 32-bit forms.
497  if (!Subtarget.hasVector()) {
500  }
501 
502  // VASTART and VACOPY need to deal with the SystemZ-specific varargs
503  // structure, but VAEND is a no-op.
507 
508  // Codes for which we want to perform some z-specific combinations.
520 
521  // Handle intrinsics.
524 
525  // We want to use MVC in preference to even a single load/store pair.
526  MaxStoresPerMemcpy = 0;
528 
529  // The main memset sequence is a byte store followed by an MVC.
530  // Two STC or MV..I stores win over that, but the kind of fused stores
531  // generated by target-independent code don't when the byte value is
532  // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
533  // than "STC;MVC". Handle the choice in target-specific code instead.
534  MaxStoresPerMemset = 0;
536 }
537 
539  LLVMContext &, EVT VT) const {
540  if (!VT.isVector())
541  return MVT::i32;
543 }
544 
546  VT = VT.getScalarType();
547 
548  if (!VT.isSimple())
549  return false;
550 
551  switch (VT.getSimpleVT().SimpleTy) {
552  case MVT::f32:
553  case MVT::f64:
554  return true;
555  case MVT::f128:
556  return Subtarget.hasVectorEnhancements1();
557  default:
558  break;
559  }
560 
561  return false;
562 }
563 
564 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
565  // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
566  return Imm.isZero() || Imm.isNegZero();
567 }
568 
570  // We can use CGFI or CLGFI.
571  return isInt<32>(Imm) || isUInt<32>(Imm);
572 }
573 
575  // We can use ALGFI or SLGFI.
576  return isUInt<32>(Imm) || isUInt<32>(-Imm);
577 }
578 
580  unsigned,
581  unsigned,
582  bool *Fast) const {
583  // Unaligned accesses should never be slower than the expanded version.
584  // We check specifically for aligned accesses in the few cases where
585  // they are required.
586  if (Fast)
587  *Fast = true;
588  return true;
589 }
590 
591 // Information about the addressing mode for a memory access.
593  // True if a long displacement is supported.
595 
596  // True if use of index register is supported.
597  bool IndexReg;
598 
599  AddressingMode(bool LongDispl, bool IdxReg) :
600  LongDisplacement(LongDispl), IndexReg(IdxReg) {}
601 };
602 
603 // Return the desired addressing mode for a Load which has only one use (in
604 // the same block) which is a Store.
605 static AddressingMode getLoadStoreAddrMode(bool HasVector,
606  Type *Ty) {
607  // With vector support a Load->Store combination may be combined to either
608  // an MVC or vector operations and it seems to work best to allow the
609  // vector addressing mode.
610  if (HasVector)
611  return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
612 
613  // Otherwise only the MVC case is special.
614  bool MVC = Ty->isIntegerTy(8);
615  return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
616 }
617 
618 // Return the addressing mode which seems most desirable given an LLVM
619 // Instruction pointer.
620 static AddressingMode
622  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
623  switch (II->getIntrinsicID()) {
624  default: break;
625  case Intrinsic::memset:
626  case Intrinsic::memmove:
627  case Intrinsic::memcpy:
628  return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
629  }
630  }
631 
632  if (isa<LoadInst>(I) && I->hasOneUse()) {
633  auto *SingleUser = dyn_cast<Instruction>(*I->user_begin());
634  if (SingleUser->getParent() == I->getParent()) {
635  if (isa<ICmpInst>(SingleUser)) {
636  if (auto *C = dyn_cast<ConstantInt>(SingleUser->getOperand(1)))
637  if (C->getBitWidth() <= 64 &&
638  (isInt<16>(C->getSExtValue()) || isUInt<16>(C->getZExtValue())))
639  // Comparison of memory with 16 bit signed / unsigned immediate
640  return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
641  } else if (isa<StoreInst>(SingleUser))
642  // Load->Store
643  return getLoadStoreAddrMode(HasVector, I->getType());
644  }
645  } else if (auto *StoreI = dyn_cast<StoreInst>(I)) {
646  if (auto *LoadI = dyn_cast<LoadInst>(StoreI->getValueOperand()))
647  if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
648  // Load->Store
649  return getLoadStoreAddrMode(HasVector, LoadI->getType());
650  }
651 
652  if (HasVector && (isa<LoadInst>(I) || isa<StoreInst>(I))) {
653 
654  // * Use LDE instead of LE/LEY for z13 to avoid partial register
655  // dependencies (LDE only supports small offsets).
656  // * Utilize the vector registers to hold floating point
657  // values (vector load / store instructions only support small
658  // offsets).
659 
660  Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
661  I->getOperand(0)->getType());
662  bool IsFPAccess = MemAccessTy->isFloatingPointTy();
663  bool IsVectorAccess = MemAccessTy->isVectorTy();
664 
665  // A store of an extracted vector element will be combined into a VSTE type
666  // instruction.
667  if (!IsVectorAccess && isa<StoreInst>(I)) {
668  Value *DataOp = I->getOperand(0);
669  if (isa<ExtractElementInst>(DataOp))
670  IsVectorAccess = true;
671  }
672 
673  // A load which gets inserted into a vector element will be combined into a
674  // VLE type instruction.
675  if (!IsVectorAccess && isa<LoadInst>(I) && I->hasOneUse()) {
676  User *LoadUser = *I->user_begin();
677  if (isa<InsertElementInst>(LoadUser))
678  IsVectorAccess = true;
679  }
680 
681  if (IsFPAccess || IsVectorAccess)
682  return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
683  }
684 
685  return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
686 }
687 
689  const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
690  // Punt on globals for now, although they can be used in limited
691  // RELATIVE LONG cases.
692  if (AM.BaseGV)
693  return false;
694 
695  // Require a 20-bit signed offset.
696  if (!isInt<20>(AM.BaseOffs))
697  return false;
698 
699  AddressingMode SupportedAM(true, true);
700  if (I != nullptr)
701  SupportedAM = supportedAddressingMode(I, Subtarget.hasVector());
702 
703  if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))
704  return false;
705 
706  if (!SupportedAM.IndexReg)
707  // No indexing allowed.
708  return AM.Scale == 0;
709  else
710  // Indexing is OK but no scale factor can be applied.
711  return AM.Scale == 0 || AM.Scale == 1;
712 }
713 
715  if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
716  return false;
717  unsigned FromBits = FromType->getPrimitiveSizeInBits();
718  unsigned ToBits = ToType->getPrimitiveSizeInBits();
719  return FromBits > ToBits;
720 }
721 
723  if (!FromVT.isInteger() || !ToVT.isInteger())
724  return false;
725  unsigned FromBits = FromVT.getSizeInBits();
726  unsigned ToBits = ToVT.getSizeInBits();
727  return FromBits > ToBits;
728 }
729 
730 //===----------------------------------------------------------------------===//
731 // Inline asm support
732 //===----------------------------------------------------------------------===//
733 
736  if (Constraint.size() == 1) {
737  switch (Constraint[0]) {
738  case 'a': // Address register
739  case 'd': // Data register (equivalent to 'r')
740  case 'f': // Floating-point register
741  case 'h': // High-part register
742  case 'r': // General-purpose register
743  return C_RegisterClass;
744 
745  case 'Q': // Memory with base and unsigned 12-bit displacement
746  case 'R': // Likewise, plus an index
747  case 'S': // Memory with base and signed 20-bit displacement
748  case 'T': // Likewise, plus an index
749  case 'm': // Equivalent to 'T'.
750  return C_Memory;
751 
752  case 'I': // Unsigned 8-bit constant
753  case 'J': // Unsigned 12-bit constant
754  case 'K': // Signed 16-bit constant
755  case 'L': // Signed 20-bit displacement (on all targets we support)
756  case 'M': // 0x7fffffff
757  return C_Other;
758 
759  default:
760  break;
761  }
762  }
763  return TargetLowering::getConstraintType(Constraint);
764 }
765 
768  const char *constraint) const {
769  ConstraintWeight weight = CW_Invalid;
770  Value *CallOperandVal = info.CallOperandVal;
771  // If we don't have a value, we can't do a match,
772  // but allow it at the lowest weight.
773  if (!CallOperandVal)
774  return CW_Default;
775  Type *type = CallOperandVal->getType();
776  // Look at the constraint type.
777  switch (*constraint) {
778  default:
779  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
780  break;
781 
782  case 'a': // Address register
783  case 'd': // Data register (equivalent to 'r')
784  case 'h': // High-part register
785  case 'r': // General-purpose register
786  if (CallOperandVal->getType()->isIntegerTy())
787  weight = CW_Register;
788  break;
789 
790  case 'f': // Floating-point register
791  if (type->isFloatingPointTy())
792  weight = CW_Register;
793  break;
794 
795  case 'I': // Unsigned 8-bit constant
796  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
797  if (isUInt<8>(C->getZExtValue()))
798  weight = CW_Constant;
799  break;
800 
801  case 'J': // Unsigned 12-bit constant
802  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
803  if (isUInt<12>(C->getZExtValue()))
804  weight = CW_Constant;
805  break;
806 
807  case 'K': // Signed 16-bit constant
808  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
809  if (isInt<16>(C->getSExtValue()))
810  weight = CW_Constant;
811  break;
812 
813  case 'L': // Signed 20-bit displacement (on all targets we support)
814  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
815  if (isInt<20>(C->getSExtValue()))
816  weight = CW_Constant;
817  break;
818 
819  case 'M': // 0x7fffffff
820  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
821  if (C->getZExtValue() == 0x7fffffff)
822  weight = CW_Constant;
823  break;
824  }
825  return weight;
826 }
827 
828 // Parse a "{tNNN}" register constraint for which the register type "t"
829 // has already been verified. MC is the class associated with "t" and
830 // Map maps 0-based register numbers to LLVM register numbers.
831 static std::pair<unsigned, const TargetRegisterClass *>
833  const unsigned *Map) {
834  assert(*(Constraint.end()-1) == '}' && "Missing '}'");
835  if (isdigit(Constraint[2])) {
836  unsigned Index;
837  bool Failed =
838  Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
839  if (!Failed && Index < 16 && Map[Index])
840  return std::make_pair(Map[Index], RC);
841  }
842  return std::make_pair(0U, nullptr);
843 }
844 
845 std::pair<unsigned, const TargetRegisterClass *>
847  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
848  if (Constraint.size() == 1) {
849  // GCC Constraint Letters
850  switch (Constraint[0]) {
851  default: break;
852  case 'd': // Data register (equivalent to 'r')
853  case 'r': // General-purpose register
854  if (VT == MVT::i64)
855  return std::make_pair(0U, &SystemZ::GR64BitRegClass);
856  else if (VT == MVT::i128)
857  return std::make_pair(0U, &SystemZ::GR128BitRegClass);
858  return std::make_pair(0U, &SystemZ::GR32BitRegClass);
859 
860  case 'a': // Address register
861  if (VT == MVT::i64)
862  return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
863  else if (VT == MVT::i128)
864  return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
865  return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
866 
867  case 'h': // High-part register (an LLVM extension)
868  return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
869 
870  case 'f': // Floating-point register
871  if (VT == MVT::f64)
872  return std::make_pair(0U, &SystemZ::FP64BitRegClass);
873  else if (VT == MVT::f128)
874  return std::make_pair(0U, &SystemZ::FP128BitRegClass);
875  return std::make_pair(0U, &SystemZ::FP32BitRegClass);
876  }
877  }
878  if (Constraint.size() > 0 && Constraint[0] == '{') {
879  // We need to override the default register parsing for GPRs and FPRs
880  // because the interpretation depends on VT. The internal names of
881  // the registers are also different from the external names
882  // (F0D and F0S instead of F0, etc.).
883  if (Constraint[1] == 'r') {
884  if (VT == MVT::i32)
885  return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
887  if (VT == MVT::i128)
888  return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
890  return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
892  }
893  if (Constraint[1] == 'f') {
894  if (VT == MVT::f32)
895  return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
897  if (VT == MVT::f128)
898  return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
900  return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
902  }
903  }
904  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
905 }
906 
908 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
909  std::vector<SDValue> &Ops,
910  SelectionDAG &DAG) const {
911  // Only support length 1 constraints for now.
912  if (Constraint.length() == 1) {
913  switch (Constraint[0]) {
914  case 'I': // Unsigned 8-bit constant
915  if (auto *C = dyn_cast<ConstantSDNode>(Op))
916  if (isUInt<8>(C->getZExtValue()))
917  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
918  Op.getValueType()));
919  return;
920 
921  case 'J': // Unsigned 12-bit constant
922  if (auto *C = dyn_cast<ConstantSDNode>(Op))
923  if (isUInt<12>(C->getZExtValue()))
924  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
925  Op.getValueType()));
926  return;
927 
928  case 'K': // Signed 16-bit constant
929  if (auto *C = dyn_cast<ConstantSDNode>(Op))
930  if (isInt<16>(C->getSExtValue()))
931  Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
932  Op.getValueType()));
933  return;
934 
935  case 'L': // Signed 20-bit displacement (on all targets we support)
936  if (auto *C = dyn_cast<ConstantSDNode>(Op))
937  if (isInt<20>(C->getSExtValue()))
938  Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
939  Op.getValueType()));
940  return;
941 
942  case 'M': // 0x7fffffff
943  if (auto *C = dyn_cast<ConstantSDNode>(Op))
944  if (C->getZExtValue() == 0x7fffffff)
945  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
946  Op.getValueType()));
947  return;
948  }
949  }
950  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
951 }
952 
953 //===----------------------------------------------------------------------===//
954 // Calling conventions
955 //===----------------------------------------------------------------------===//
956 
957 #include "SystemZGenCallingConv.inc"
958 
960  Type *ToType) const {
961  return isTruncateFree(FromType, ToType);
962 }
963 
965  return CI->isTailCall();
966 }
967 
968 // We do not yet support 128-bit single-element vector types. If the user
969 // attempts to use such types as function argument or return type, prefer
970 // to error out instead of emitting code violating the ABI.
971 static void VerifyVectorType(MVT VT, EVT ArgVT) {
972  if (ArgVT.isVector() && !VT.isVector())
973  report_fatal_error("Unsupported vector argument or return type");
974 }
975 
977  for (unsigned i = 0; i < Ins.size(); ++i)
978  VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
979 }
980 
982  for (unsigned i = 0; i < Outs.size(); ++i)
983  VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
984 }
985 
986 // Value is a value that has been passed to us in the location described by VA
987 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
988 // any loads onto Chain.
990  CCValAssign &VA, SDValue Chain,
991  SDValue Value) {
992  // If the argument has been promoted from a smaller type, insert an
993  // assertion to capture this.
994  if (VA.getLocInfo() == CCValAssign::SExt)
995  Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
996  DAG.getValueType(VA.getValVT()));
997  else if (VA.getLocInfo() == CCValAssign::ZExt)
998  Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
999  DAG.getValueType(VA.getValVT()));
1000 
1001  if (VA.isExtInLoc())
1002  Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
1003  else if (VA.getLocInfo() == CCValAssign::BCvt) {
1004  // If this is a short vector argument loaded from the stack,
1005  // extend from i64 to full vector size and then bitcast.
1006  assert(VA.getLocVT() == MVT::i64);
1007  assert(VA.getValVT().isVector());
1008  Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
1009  Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
1010  } else
1011  assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
1012  return Value;
1013 }
1014 
1015 // Value is a value of type VA.getValVT() that we need to copy into
1016 // the location described by VA. Return a copy of Value converted to
1017 // VA.getValVT(). The caller is responsible for handling indirect values.
1019  CCValAssign &VA, SDValue Value) {
1020  switch (VA.getLocInfo()) {
1021  case CCValAssign::SExt:
1022  return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
1023  case CCValAssign::ZExt:
1024  return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
1025  case CCValAssign::AExt:
1026  return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
1027  case CCValAssign::BCvt:
1028  // If this is a short vector argument to be stored to the stack,
1029  // bitcast to v2i64 and then extract first element.
1030  assert(VA.getLocVT() == MVT::i64);
1031  assert(VA.getValVT().isVector());
1032  Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
1033  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
1034  DAG.getConstant(0, DL, MVT::i32));
1035  case CCValAssign::Full:
1036  return Value;
1037  default:
1038  llvm_unreachable("Unhandled getLocInfo()");
1039  }
1040 }
1041 
1043  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1044  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1045  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1046  MachineFunction &MF = DAG.getMachineFunction();
1047  MachineFrameInfo &MFI = MF.getFrameInfo();
1049  SystemZMachineFunctionInfo *FuncInfo =
1051  auto *TFL =
1052  static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
1053  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1054 
1055  // Detect unsupported vector argument types.
1056  if (Subtarget.hasVector())
1057  VerifyVectorTypes(Ins);
1058 
1059  // Assign locations to all of the incoming arguments.
1061  SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1062  CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
1063 
1064  unsigned NumFixedGPRs = 0;
1065  unsigned NumFixedFPRs = 0;
1066  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1067  SDValue ArgValue;
1068  CCValAssign &VA = ArgLocs[I];
1069  EVT LocVT = VA.getLocVT();
1070  if (VA.isRegLoc()) {
1071  // Arguments passed in registers
1072  const TargetRegisterClass *RC;
1073  switch (LocVT.getSimpleVT().SimpleTy) {
1074  default:
1075  // Integers smaller than i64 should be promoted to i64.
1076  llvm_unreachable("Unexpected argument type");
1077  case MVT::i32:
1078  NumFixedGPRs += 1;
1079  RC = &SystemZ::GR32BitRegClass;
1080  break;
1081  case MVT::i64:
1082  NumFixedGPRs += 1;
1083  RC = &SystemZ::GR64BitRegClass;
1084  break;
1085  case MVT::f32:
1086  NumFixedFPRs += 1;
1087  RC = &SystemZ::FP32BitRegClass;
1088  break;
1089  case MVT::f64:
1090  NumFixedFPRs += 1;
1091  RC = &SystemZ::FP64BitRegClass;
1092  break;
1093  case MVT::v16i8:
1094  case MVT::v8i16:
1095  case MVT::v4i32:
1096  case MVT::v2i64:
1097  case MVT::v4f32:
1098  case MVT::v2f64:
1099  RC = &SystemZ::VR128BitRegClass;
1100  break;
1101  }
1102 
1103  unsigned VReg = MRI.createVirtualRegister(RC);
1104  MRI.addLiveIn(VA.getLocReg(), VReg);
1105  ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1106  } else {
1107  assert(VA.isMemLoc() && "Argument not register or memory");
1108 
1109  // Create the frame index object for this incoming parameter.
1110  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1111  VA.getLocMemOffset(), true);
1112 
1113  // Create the SelectionDAG nodes corresponding to a load
1114  // from this parameter. Unpromoted ints and floats are
1115  // passed as right-justified 8-byte values.
1116  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1117  if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1118  FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
1119  DAG.getIntPtrConstant(4, DL));
1120  ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
1122  }
1123 
1124  // Convert the value of the argument register into the value that's
1125  // being passed.
1126  if (VA.getLocInfo() == CCValAssign::Indirect) {
1127  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1128  MachinePointerInfo()));
1129  // If the original argument was split (e.g. i128), we need
1130  // to load all parts of it here (using the same address).
1131  unsigned ArgIndex = Ins[I].OrigArgIndex;
1132  assert (Ins[I].PartOffset == 0);
1133  while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
1134  CCValAssign &PartVA = ArgLocs[I + 1];
1135  unsigned PartOffset = Ins[I + 1].PartOffset;
1136  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1137  DAG.getIntPtrConstant(PartOffset, DL));
1138  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1139  MachinePointerInfo()));
1140  ++I;
1141  }
1142  } else
1143  InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
1144  }
1145 
1146  if (IsVarArg) {
1147  // Save the number of non-varargs registers for later use by va_start, etc.
1148  FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
1149  FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
1150 
1151  // Likewise the address (in the form of a frame index) of where the
1152  // first stack vararg would be. The 1-byte size here is arbitrary.
1153  int64_t StackSize = CCInfo.getNextStackOffset();
1154  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1155 
1156  // ...and a similar frame index for the caller-allocated save area
1157  // that will be used to store the incoming registers.
1158  int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
1159  unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
1160  FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
1161 
1162  // Store the FPR varargs in the reserved frame slots. (We store the
1163  // GPRs as part of the prologue.)
1164  if (NumFixedFPRs < SystemZ::NumArgFPRs) {
1165  SDValue MemOps[SystemZ::NumArgFPRs];
1166  for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
1167  unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
1168  int FI = MFI.CreateFixedObject(8, RegSaveOffset + Offset, true);
1169  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1170  unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
1171  &SystemZ::FP64BitRegClass);
1172  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1173  MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1175  }
1176  // Join the stores, which are independent of one another.
1177  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1178  makeArrayRef(&MemOps[NumFixedFPRs],
1179  SystemZ::NumArgFPRs-NumFixedFPRs));
1180  }
1181  }
1182 
1183  return Chain;
1184 }
1185 
1186 static bool canUseSiblingCall(const CCState &ArgCCInfo,
1189  // Punt if there are any indirect or stack arguments, or if the call
1190  // needs the callee-saved argument register R6, or if the call uses
1191  // the callee-saved register arguments SwiftSelf and SwiftError.
1192  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1193  CCValAssign &VA = ArgLocs[I];
1194  if (VA.getLocInfo() == CCValAssign::Indirect)
1195  return false;
1196  if (!VA.isRegLoc())
1197  return false;
1198  unsigned Reg = VA.getLocReg();
1199  if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1200  return false;
1201  if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1202  return false;
1203  }
1204  return true;
1205 }
1206 
1207 SDValue
1209  SmallVectorImpl<SDValue> &InVals) const {
1210  SelectionDAG &DAG = CLI.DAG;
1211  SDLoc &DL = CLI.DL;
1213  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1215  SDValue Chain = CLI.Chain;
1216  SDValue Callee = CLI.Callee;
1217  bool &IsTailCall = CLI.IsTailCall;
1218  CallingConv::ID CallConv = CLI.CallConv;
1219  bool IsVarArg = CLI.IsVarArg;
1220  MachineFunction &MF = DAG.getMachineFunction();
1221  EVT PtrVT = getPointerTy(MF.getDataLayout());
1222 
1223  // Detect unsupported vector argument and return types.
1224  if (Subtarget.hasVector()) {
1225  VerifyVectorTypes(Outs);
1226  VerifyVectorTypes(Ins);
1227  }
1228 
1229  // Analyze the operands of the call, assigning locations to each operand.
1231  SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1232  ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1233 
1234  // We don't support GuaranteedTailCallOpt, only automatically-detected
1235  // sibling calls.
1236  if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
1237  IsTailCall = false;
1238 
1239  // Get a count of how many bytes are to be pushed on the stack.
1240  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1241 
1242  // Mark the start of the call.
1243  if (!IsTailCall)
1244  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1245 
1246  // Copy argument values to their designated locations.
1248  SmallVector<SDValue, 8> MemOpChains;
1249  SDValue StackPtr;
1250  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1251  CCValAssign &VA = ArgLocs[I];
1252  SDValue ArgValue = OutVals[I];
1253 
1254  if (VA.getLocInfo() == CCValAssign::Indirect) {
1255  // Store the argument in a stack slot and pass its address.
1256  SDValue SpillSlot = DAG.CreateStackTemporary(Outs[I].ArgVT);
1257  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1258  MemOpChains.push_back(
1259  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1261  // If the original argument was split (e.g. i128), we need
1262  // to store all parts of it here (and pass just one address).
1263  unsigned ArgIndex = Outs[I].OrigArgIndex;
1264  assert (Outs[I].PartOffset == 0);
1265  while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1266  SDValue PartValue = OutVals[I + 1];
1267  unsigned PartOffset = Outs[I + 1].PartOffset;
1268  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1269  DAG.getIntPtrConstant(PartOffset, DL));
1270  MemOpChains.push_back(
1271  DAG.getStore(Chain, DL, PartValue, Address,
1273  ++I;
1274  }
1275  ArgValue = SpillSlot;
1276  } else
1277  ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1278 
1279  if (VA.isRegLoc())
1280  // Queue up the argument copies and emit them at the end.
1281  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1282  else {
1283  assert(VA.isMemLoc() && "Argument not register or memory");
1284 
1285  // Work out the address of the stack slot. Unpromoted ints and
1286  // floats are passed as right-justified 8-byte values.
1287  if (!StackPtr.getNode())
1288  StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1290  if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1291  Offset += 4;
1292  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1293  DAG.getIntPtrConstant(Offset, DL));
1294 
1295  // Emit the store.
1296  MemOpChains.push_back(
1297  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1298  }
1299  }
1300 
1301  // Join the stores, which are independent of one another.
1302  if (!MemOpChains.empty())
1303  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1304 
1305  // Accept direct calls by converting symbolic call addresses to the
1306  // associated Target* opcodes. Force %r1 to be used for indirect
1307  // tail calls.
1308  SDValue Glue;
1309  if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1310  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1311  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1312  } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1313  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1314  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1315  } else if (IsTailCall) {
1316  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1317  Glue = Chain.getValue(1);
1318  Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1319  }
1320 
1321  // Build a sequence of copy-to-reg nodes, chained and glued together.
1322  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1323  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1324  RegsToPass[I].second, Glue);
1325  Glue = Chain.getValue(1);
1326  }
1327 
1328  // The first call operand is the chain and the second is the target address.
1330  Ops.push_back(Chain);
1331  Ops.push_back(Callee);
1332 
1333  // Add argument registers to the end of the list so that they are
1334  // known live into the call.
1335  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1336  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1337  RegsToPass[I].second.getValueType()));
1338 
1339  // Add a register mask operand representing the call-preserved registers.
1340  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1341  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1342  assert(Mask && "Missing call preserved mask for calling convention");
1343  Ops.push_back(DAG.getRegisterMask(Mask));
1344 
1345  // Glue the call to the argument copies, if any.
1346  if (Glue.getNode())
1347  Ops.push_back(Glue);
1348 
1349  // Emit the call.
1350  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1351  if (IsTailCall)
1352  return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1353  Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1354  Glue = Chain.getValue(1);
1355 
1356  // Mark the end of the call, which is glued to the call itself.
1357  Chain = DAG.getCALLSEQ_END(Chain,
1358  DAG.getConstant(NumBytes, DL, PtrVT, true),
1359  DAG.getConstant(0, DL, PtrVT, true),
1360  Glue, DL);
1361  Glue = Chain.getValue(1);
1362 
1363  // Assign locations to each value returned by this call.
1365  CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1366  RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1367 
1368  // Copy all of the result registers out of their specified physreg.
1369  for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1370  CCValAssign &VA = RetLocs[I];
1371 
1372  // Copy the value out, gluing the copy to the end of the call sequence.
1373  SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1374  VA.getLocVT(), Glue);
1375  Chain = RetValue.getValue(1);
1376  Glue = RetValue.getValue(2);
1377 
1378  // Convert the value of the return register into the value that's
1379  // being returned.
1380  InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1381  }
1382 
1383  return Chain;
1384 }
1385 
1388  MachineFunction &MF, bool isVarArg,
1389  const SmallVectorImpl<ISD::OutputArg> &Outs,
1390  LLVMContext &Context) const {
1391  // Detect unsupported vector return types.
1392  if (Subtarget.hasVector())
1393  VerifyVectorTypes(Outs);
1394 
1395  // Special case that we cannot easily detect in RetCC_SystemZ since
1396  // i128 is not a legal type.
1397  for (auto &Out : Outs)
1398  if (Out.ArgVT == MVT::i128)
1399  return false;
1400 
1402  CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1403  return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1404 }
1405 
1406 SDValue
1408  bool IsVarArg,
1409  const SmallVectorImpl<ISD::OutputArg> &Outs,
1410  const SmallVectorImpl<SDValue> &OutVals,
1411  const SDLoc &DL, SelectionDAG &DAG) const {
1412  MachineFunction &MF = DAG.getMachineFunction();
1413 
1414  // Detect unsupported vector return types.
1415  if (Subtarget.hasVector())
1416  VerifyVectorTypes(Outs);
1417 
1418  // Assign locations to each returned value.
1420  CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1421  RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1422 
1423  // Quick exit for void returns
1424  if (RetLocs.empty())
1425  return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1426 
1427  // Copy the result values into the output registers.
1428  SDValue Glue;
1429  SmallVector<SDValue, 4> RetOps;
1430  RetOps.push_back(Chain);
1431  for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1432  CCValAssign &VA = RetLocs[I];
1433  SDValue RetValue = OutVals[I];
1434 
1435  // Make the return register live on exit.
1436  assert(VA.isRegLoc() && "Can only return in registers!");
1437 
1438  // Promote the value as required.
1439  RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1440 
1441  // Chain and glue the copies together.
1442  unsigned Reg = VA.getLocReg();
1443  Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1444  Glue = Chain.getValue(1);
1445  RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1446  }
1447 
1448  // Update chain and glue.
1449  RetOps[0] = Chain;
1450  if (Glue.getNode())
1451  RetOps.push_back(Glue);
1452 
1453  return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1454 }
1455 
1456 // Return true if Op is an intrinsic node with chain that returns the CC value
1457 // as its only (other) argument. Provide the associated SystemZISD opcode and
1458 // the mask of valid CC values if so.
1459 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1460  unsigned &CCValid) {
1461  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1462  switch (Id) {
1463  case Intrinsic::s390_tbegin:
1464  Opcode = SystemZISD::TBEGIN;
1465  CCValid = SystemZ::CCMASK_TBEGIN;
1466  return true;
1467 
1468  case Intrinsic::s390_tbegin_nofloat:
1469  Opcode = SystemZISD::TBEGIN_NOFLOAT;
1470  CCValid = SystemZ::CCMASK_TBEGIN;
1471  return true;
1472 
1473  case Intrinsic::s390_tend:
1474  Opcode = SystemZISD::TEND;
1475  CCValid = SystemZ::CCMASK_TEND;
1476  return true;
1477 
1478  default:
1479  return false;
1480  }
1481 }
1482 
1483 // Return true if Op is an intrinsic node without chain that returns the
1484 // CC value as its final argument. Provide the associated SystemZISD
1485 // opcode and the mask of valid CC values if so.
1486 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1487  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1488  switch (Id) {
1489  case Intrinsic::s390_vpkshs:
1490  case Intrinsic::s390_vpksfs:
1491  case Intrinsic::s390_vpksgs:
1492  Opcode = SystemZISD::PACKS_CC;
1493  CCValid = SystemZ::CCMASK_VCMP;
1494  return true;
1495 
1496  case Intrinsic::s390_vpklshs:
1497  case Intrinsic::s390_vpklsfs:
1498  case Intrinsic::s390_vpklsgs:
1499  Opcode = SystemZISD::PACKLS_CC;
1500  CCValid = SystemZ::CCMASK_VCMP;
1501  return true;
1502 
1503  case Intrinsic::s390_vceqbs:
1504  case Intrinsic::s390_vceqhs:
1505  case Intrinsic::s390_vceqfs:
1506  case Intrinsic::s390_vceqgs:
1507  Opcode = SystemZISD::VICMPES;
1508  CCValid = SystemZ::CCMASK_VCMP;
1509  return true;
1510 
1511  case Intrinsic::s390_vchbs:
1512  case Intrinsic::s390_vchhs:
1513  case Intrinsic::s390_vchfs:
1514  case Intrinsic::s390_vchgs:
1515  Opcode = SystemZISD::VICMPHS;
1516  CCValid = SystemZ::CCMASK_VCMP;
1517  return true;
1518 
1519  case Intrinsic::s390_vchlbs:
1520  case Intrinsic::s390_vchlhs:
1521  case Intrinsic::s390_vchlfs:
1522  case Intrinsic::s390_vchlgs:
1523  Opcode = SystemZISD::VICMPHLS;
1524  CCValid = SystemZ::CCMASK_VCMP;
1525  return true;
1526 
1527  case Intrinsic::s390_vtm:
1528  Opcode = SystemZISD::VTM;
1529  CCValid = SystemZ::CCMASK_VCMP;
1530  return true;
1531 
1532  case Intrinsic::s390_vfaebs:
1533  case Intrinsic::s390_vfaehs:
1534  case Intrinsic::s390_vfaefs:
1535  Opcode = SystemZISD::VFAE_CC;
1536  CCValid = SystemZ::CCMASK_ANY;
1537  return true;
1538 
1539  case Intrinsic::s390_vfaezbs:
1540  case Intrinsic::s390_vfaezhs:
1541  case Intrinsic::s390_vfaezfs:
1542  Opcode = SystemZISD::VFAEZ_CC;
1543  CCValid = SystemZ::CCMASK_ANY;
1544  return true;
1545 
1546  case Intrinsic::s390_vfeebs:
1547  case Intrinsic::s390_vfeehs:
1548  case Intrinsic::s390_vfeefs:
1549  Opcode = SystemZISD::VFEE_CC;
1550  CCValid = SystemZ::CCMASK_ANY;
1551  return true;
1552 
1553  case Intrinsic::s390_vfeezbs:
1554  case Intrinsic::s390_vfeezhs:
1555  case Intrinsic::s390_vfeezfs:
1556  Opcode = SystemZISD::VFEEZ_CC;
1557  CCValid = SystemZ::CCMASK_ANY;
1558  return true;
1559 
1560  case Intrinsic::s390_vfenebs:
1561  case Intrinsic::s390_vfenehs:
1562  case Intrinsic::s390_vfenefs:
1563  Opcode = SystemZISD::VFENE_CC;
1564  CCValid = SystemZ::CCMASK_ANY;
1565  return true;
1566 
1567  case Intrinsic::s390_vfenezbs:
1568  case Intrinsic::s390_vfenezhs:
1569  case Intrinsic::s390_vfenezfs:
1570  Opcode = SystemZISD::VFENEZ_CC;
1571  CCValid = SystemZ::CCMASK_ANY;
1572  return true;
1573 
1574  case Intrinsic::s390_vistrbs:
1575  case Intrinsic::s390_vistrhs:
1576  case Intrinsic::s390_vistrfs:
1577  Opcode = SystemZISD::VISTR_CC;
1579  return true;
1580 
1581  case Intrinsic::s390_vstrcbs:
1582  case Intrinsic::s390_vstrchs:
1583  case Intrinsic::s390_vstrcfs:
1584  Opcode = SystemZISD::VSTRC_CC;
1585  CCValid = SystemZ::CCMASK_ANY;
1586  return true;
1587 
1588  case Intrinsic::s390_vstrczbs:
1589  case Intrinsic::s390_vstrczhs:
1590  case Intrinsic::s390_vstrczfs:
1591  Opcode = SystemZISD::VSTRCZ_CC;
1592  CCValid = SystemZ::CCMASK_ANY;
1593  return true;
1594 
1595  case Intrinsic::s390_vfcedbs:
1596  case Intrinsic::s390_vfcesbs:
1597  Opcode = SystemZISD::VFCMPES;
1598  CCValid = SystemZ::CCMASK_VCMP;
1599  return true;
1600 
1601  case Intrinsic::s390_vfchdbs:
1602  case Intrinsic::s390_vfchsbs:
1603  Opcode = SystemZISD::VFCMPHS;
1604  CCValid = SystemZ::CCMASK_VCMP;
1605  return true;
1606 
1607  case Intrinsic::s390_vfchedbs:
1608  case Intrinsic::s390_vfchesbs:
1609  Opcode = SystemZISD::VFCMPHES;
1610  CCValid = SystemZ::CCMASK_VCMP;
1611  return true;
1612 
1613  case Intrinsic::s390_vftcidb:
1614  case Intrinsic::s390_vftcisb:
1615  Opcode = SystemZISD::VFTCI;
1616  CCValid = SystemZ::CCMASK_VCMP;
1617  return true;
1618 
1619  case Intrinsic::s390_tdc:
1620  Opcode = SystemZISD::TDC;
1621  CCValid = SystemZ::CCMASK_TDC;
1622  return true;
1623 
1624  default:
1625  return false;
1626  }
1627 }
1628 
1629 // Emit an intrinsic with chain with a glued value instead of its CC result.
1631  unsigned Opcode) {
1632  // Copy all operands except the intrinsic ID.
1633  unsigned NumOps = Op.getNumOperands();
1635  Ops.reserve(NumOps - 1);
1636  Ops.push_back(Op.getOperand(0));
1637  for (unsigned I = 2; I < NumOps; ++I)
1638  Ops.push_back(Op.getOperand(I));
1639 
1640  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1641  SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1642  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1643  SDValue OldChain = SDValue(Op.getNode(), 1);
1644  SDValue NewChain = SDValue(Intr.getNode(), 0);
1645  DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1646  return Intr;
1647 }
1648 
1649 // Emit an intrinsic with a glued value instead of its CC result.
1651  unsigned Opcode) {
1652  // Copy all operands except the intrinsic ID.
1653  unsigned NumOps = Op.getNumOperands();
1655  Ops.reserve(NumOps - 1);
1656  for (unsigned I = 1; I < NumOps; ++I)
1657  Ops.push_back(Op.getOperand(I));
1658 
1659  if (Op->getNumValues() == 1)
1660  return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1661  assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1662  SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1663  return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1664 }
1665 
1666 // CC is a comparison that will be implemented using an integer or
1667 // floating-point comparison. Return the condition code mask for
1668 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1669 // unsigned comparisons and clear for signed ones. In the floating-point
1670 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1671 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1672 #define CONV(X) \
1673  case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1674  case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1675  case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1676 
1677  switch (CC) {
1678  default:
1679  llvm_unreachable("Invalid integer condition!");
1680 
1681  CONV(EQ);
1682  CONV(NE);
1683  CONV(GT);
1684  CONV(GE);
1685  CONV(LT);
1686  CONV(LE);
1687 
1688  case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1689  case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1690  }
1691 #undef CONV
1692 }
1693 
1694 // If C can be converted to a comparison against zero, adjust the operands
1695 // as necessary.
1696 static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
1697  if (C.ICmpType == SystemZICMP::UnsignedOnly)
1698  return;
1699 
1700  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1701  if (!ConstOp1)
1702  return;
1703 
1704  int64_t Value = ConstOp1->getSExtValue();
1705  if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1706  (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1707  (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1708  (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1709  C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1710  C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1711  }
1712 }
1713 
1714 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1715 // adjust the operands as necessary.
1716 static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
1717  Comparison &C) {
1718  // For us to make any changes, it must a comparison between a single-use
1719  // load and a constant.
1720  if (!C.Op0.hasOneUse() ||
1721  C.Op0.getOpcode() != ISD::LOAD ||
1722  C.Op1.getOpcode() != ISD::Constant)
1723  return;
1724 
1725  // We must have an 8- or 16-bit load.
1726  auto *Load = cast<LoadSDNode>(C.Op0);
1727  unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1728  if (NumBits != 8 && NumBits != 16)
1729  return;
1730 
1731  // The load must be an extending one and the constant must be within the
1732  // range of the unextended value.
1733  auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1734  uint64_t Value = ConstOp1->getZExtValue();
1735  uint64_t Mask = (1 << NumBits) - 1;
1736  if (Load->getExtensionType() == ISD::SEXTLOAD) {
1737  // Make sure that ConstOp1 is in range of C.Op0.
1738  int64_t SignedValue = ConstOp1->getSExtValue();
1739  if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1740  return;
1741  if (C.ICmpType != SystemZICMP::SignedOnly) {
1742  // Unsigned comparison between two sign-extended values is equivalent
1743  // to unsigned comparison between two zero-extended values.
1744  Value &= Mask;
1745  } else if (NumBits == 8) {
1746  // Try to treat the comparison as unsigned, so that we can use CLI.
1747  // Adjust CCMask and Value as necessary.
1748  if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1749  // Test whether the high bit of the byte is set.
1750  Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1751  else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1752  // Test whether the high bit of the byte is clear.
1753  Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1754  else
1755  // No instruction exists for this combination.
1756  return;
1757  C.ICmpType = SystemZICMP::UnsignedOnly;
1758  }
1759  } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1760  if (Value > Mask)
1761  return;
1762  // If the constant is in range, we can use any comparison.
1763  C.ICmpType = SystemZICMP::Any;
1764  } else
1765  return;
1766 
1767  // Make sure that the first operand is an i32 of the right extension type.
1768  ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1769  ISD::SEXTLOAD :
1770  ISD::ZEXTLOAD);
1771  if (C.Op0.getValueType() != MVT::i32 ||
1772  Load->getExtensionType() != ExtType) {
1773  C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
1774  Load->getBasePtr(), Load->getPointerInfo(),
1775  Load->getMemoryVT(), Load->getAlignment(),
1776  Load->getMemOperand()->getFlags());
1777  // Update the chain uses.
1778  DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0.getValue(1));
1779  }
1780 
1781  // Make sure that the second operand is an i32 with the right value.
1782  if (C.Op1.getValueType() != MVT::i32 ||
1783  Value != ConstOp1->getZExtValue())
1784  C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1785 }
1786 
1787 // Return true if Op is either an unextended load, or a load suitable
1788 // for integer register-memory comparisons of type ICmpType.
1789 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1790  auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1791  if (Load) {
1792  // There are no instructions to compare a register with a memory byte.
1793  if (Load->getMemoryVT() == MVT::i8)
1794  return false;
1795  // Otherwise decide on extension type.
1796  switch (Load->getExtensionType()) {
1797  case ISD::NON_EXTLOAD:
1798  return true;
1799  case ISD::SEXTLOAD:
1800  return ICmpType != SystemZICMP::UnsignedOnly;
1801  case ISD::ZEXTLOAD:
1802  return ICmpType != SystemZICMP::SignedOnly;
1803  default:
1804  break;
1805  }
1806  }
1807  return false;
1808 }
1809 
1810 // Return true if it is better to swap the operands of C.
1811 static bool shouldSwapCmpOperands(const Comparison &C) {
1812  // Leave f128 comparisons alone, since they have no memory forms.
1813  if (C.Op0.getValueType() == MVT::f128)
1814  return false;
1815 
1816  // Always keep a floating-point constant second, since comparisons with
1817  // zero can use LOAD TEST and comparisons with other constants make a
1818  // natural memory operand.
1819  if (isa<ConstantFPSDNode>(C.Op1))
1820  return false;
1821 
1822  // Never swap comparisons with zero since there are many ways to optimize
1823  // those later.
1824  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1825  if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1826  return false;
1827 
1828  // Also keep natural memory operands second if the loaded value is
1829  // only used here. Several comparisons have memory forms.
1830  if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1831  return false;
1832 
1833  // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1834  // In that case we generally prefer the memory to be second.
1835  if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1836  // The only exceptions are when the second operand is a constant and
1837  // we can use things like CHHSI.
1838  if (!ConstOp1)
1839  return true;
1840  // The unsigned memory-immediate instructions can handle 16-bit
1841  // unsigned integers.
1842  if (C.ICmpType != SystemZICMP::SignedOnly &&
1843  isUInt<16>(ConstOp1->getZExtValue()))
1844  return false;
1845  // The signed memory-immediate instructions can handle 16-bit
1846  // signed integers.
1847  if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1848  isInt<16>(ConstOp1->getSExtValue()))
1849  return false;
1850  return true;
1851  }
1852 
1853  // Try to promote the use of CGFR and CLGFR.
1854  unsigned Opcode0 = C.Op0.getOpcode();
1855  if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1856  return true;
1857  if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1858  return true;
1859  if (C.ICmpType != SystemZICMP::SignedOnly &&
1860  Opcode0 == ISD::AND &&
1861  C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1862  cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1863  return true;
1864 
1865  return false;
1866 }
1867 
1868 // Return a version of comparison CC mask CCMask in which the LT and GT
1869 // actions are swapped.
1870 static unsigned reverseCCMask(unsigned CCMask) {
1871  return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1873  (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1874  (CCMask & SystemZ::CCMASK_CMP_UO));
1875 }
1876 
1877 // Check whether C tests for equality between X and Y and whether X - Y
1878 // or Y - X is also computed. In that case it's better to compare the
1879 // result of the subtraction against zero.
1880 static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
1881  Comparison &C) {
1882  if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1883  C.CCMask == SystemZ::CCMASK_CMP_NE) {
1884  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1885  SDNode *N = *I;
1886  if (N->getOpcode() == ISD::SUB &&
1887  ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1888  (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1889  C.Op0 = SDValue(N, 0);
1890  C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1891  return;
1892  }
1893  }
1894  }
1895 }
1896 
1897 // Check whether C compares a floating-point value with zero and if that
1898 // floating-point value is also negated. In this case we can use the
1899 // negation to set CC, so avoiding separate LOAD AND TEST and
1900 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1901 static void adjustForFNeg(Comparison &C) {
1902  auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1903  if (C1 && C1->isZero()) {
1904  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1905  SDNode *N = *I;
1906  if (N->getOpcode() == ISD::FNEG) {
1907  C.Op0 = SDValue(N, 0);
1908  C.CCMask = reverseCCMask(C.CCMask);
1909  return;
1910  }
1911  }
1912  }
1913 }
1914 
1915 // Check whether C compares (shl X, 32) with 0 and whether X is
1916 // also sign-extended. In that case it is better to test the result
1917 // of the sign extension using LTGFR.
1918 //
1919 // This case is important because InstCombine transforms a comparison
1920 // with (sext (trunc X)) into a comparison with (shl X, 32).
1921 static void adjustForLTGFR(Comparison &C) {
1922  // Check for a comparison between (shl X, 32) and 0.
1923  if (C.Op0.getOpcode() == ISD::SHL &&
1924  C.Op0.getValueType() == MVT::i64 &&
1925  C.Op1.getOpcode() == ISD::Constant &&
1926  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1927  auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1928  if (C1 && C1->getZExtValue() == 32) {
1929  SDValue ShlOp0 = C.Op0.getOperand(0);
1930  // See whether X has any SIGN_EXTEND_INREG uses.
1931  for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1932  SDNode *N = *I;
1933  if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1934  cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1935  C.Op0 = SDValue(N, 0);
1936  return;
1937  }
1938  }
1939  }
1940  }
1941 }
1942 
1943 // If C compares the truncation of an extending load, try to compare
1944 // the untruncated value instead. This exposes more opportunities to
1945 // reuse CC.
1946 static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
1947  Comparison &C) {
1948  if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1949  C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1950  C.Op1.getOpcode() == ISD::Constant &&
1951  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1952  auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1953  if (L->getMemoryVT().getStoreSizeInBits() <= C.Op0.getValueSizeInBits()) {
1954  unsigned Type = L->getExtensionType();
1955  if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1956  (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1957  C.Op0 = C.Op0.getOperand(0);
1958  C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1959  }
1960  }
1961  }
1962 }
1963 
1964 // Return true if shift operation N has an in-range constant shift value.
1965 // Store it in ShiftVal if so.
1966 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1967  auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1968  if (!Shift)
1969  return false;
1970 
1971  uint64_t Amount = Shift->getZExtValue();
1972  if (Amount >= N.getValueSizeInBits())
1973  return false;
1974 
1975  ShiftVal = Amount;
1976  return true;
1977 }
1978 
1979 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1980 // instruction and whether the CC value is descriptive enough to handle
1981 // a comparison of type Opcode between the AND result and CmpVal.
1982 // CCMask says which comparison result is being tested and BitSize is
1983 // the number of bits in the operands. If TEST UNDER MASK can be used,
1984 // return the corresponding CC mask, otherwise return 0.
1985 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1986  uint64_t Mask, uint64_t CmpVal,
1987  unsigned ICmpType) {
1988  assert(Mask != 0 && "ANDs with zero should have been removed by now");
1989 
1990  // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1991  if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1992  !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1993  return 0;
1994 
1995  // Work out the masks for the lowest and highest bits.
1996  unsigned HighShift = 63 - countLeadingZeros(Mask);
1997  uint64_t High = uint64_t(1) << HighShift;
1998  uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1999 
2000  // Signed ordered comparisons are effectively unsigned if the sign
2001  // bit is dropped.
2002  bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
2003 
2004  // Check for equality comparisons with 0, or the equivalent.
2005  if (CmpVal == 0) {
2006  if (CCMask == SystemZ::CCMASK_CMP_EQ)
2007  return SystemZ::CCMASK_TM_ALL_0;
2008  if (CCMask == SystemZ::CCMASK_CMP_NE)
2010  }
2011  if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
2012  if (CCMask == SystemZ::CCMASK_CMP_LT)
2013  return SystemZ::CCMASK_TM_ALL_0;
2014  if (CCMask == SystemZ::CCMASK_CMP_GE)
2016  }
2017  if (EffectivelyUnsigned && CmpVal < Low) {
2018  if (CCMask == SystemZ::CCMASK_CMP_LE)
2019  return SystemZ::CCMASK_TM_ALL_0;
2020  if (CCMask == SystemZ::CCMASK_CMP_GT)
2022  }
2023 
2024  // Check for equality comparisons with the mask, or the equivalent.
2025  if (CmpVal == Mask) {
2026  if (CCMask == SystemZ::CCMASK_CMP_EQ)
2027  return SystemZ::CCMASK_TM_ALL_1;
2028  if (CCMask == SystemZ::CCMASK_CMP_NE)
2030  }
2031  if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
2032  if (CCMask == SystemZ::CCMASK_CMP_GT)
2033  return SystemZ::CCMASK_TM_ALL_1;
2034  if (CCMask == SystemZ::CCMASK_CMP_LE)
2036  }
2037  if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
2038  if (CCMask == SystemZ::CCMASK_CMP_GE)
2039  return SystemZ::CCMASK_TM_ALL_1;
2040  if (CCMask == SystemZ::CCMASK_CMP_LT)
2042  }
2043 
2044  // Check for ordered comparisons with the top bit.
2045  if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
2046  if (CCMask == SystemZ::CCMASK_CMP_LE)
2047  return SystemZ::CCMASK_TM_MSB_0;
2048  if (CCMask == SystemZ::CCMASK_CMP_GT)
2049  return SystemZ::CCMASK_TM_MSB_1;
2050  }
2051  if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
2052  if (CCMask == SystemZ::CCMASK_CMP_LT)
2053  return SystemZ::CCMASK_TM_MSB_0;
2054  if (CCMask == SystemZ::CCMASK_CMP_GE)
2055  return SystemZ::CCMASK_TM_MSB_1;
2056  }
2057 
2058  // If there are just two bits, we can do equality checks for Low and High
2059  // as well.
2060  if (Mask == Low + High) {
2061  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
2063  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
2065  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
2067  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
2069  }
2070 
2071  // Looks like we've exhausted our options.
2072  return 0;
2073 }
2074 
2075 // See whether C can be implemented as a TEST UNDER MASK instruction.
2076 // Update the arguments with the TM version if so.
2077 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
2078  Comparison &C) {
2079  // Check that we have a comparison with a constant.
2080  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
2081  if (!ConstOp1)
2082  return;
2083  uint64_t CmpVal = ConstOp1->getZExtValue();
2084 
2085  // Check whether the nonconstant input is an AND with a constant mask.
2086  Comparison NewC(C);
2087  uint64_t MaskVal;
2088  ConstantSDNode *Mask = nullptr;
2089  if (C.Op0.getOpcode() == ISD::AND) {
2090  NewC.Op0 = C.Op0.getOperand(0);
2091  NewC.Op1 = C.Op0.getOperand(1);
2092  Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2093  if (!Mask)
2094  return;
2095  MaskVal = Mask->getZExtValue();
2096  } else {
2097  // There is no instruction to compare with a 64-bit immediate
2098  // so use TMHH instead if possible. We need an unsigned ordered
2099  // comparison with an i64 immediate.
2100  if (NewC.Op0.getValueType() != MVT::i64 ||
2101  NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
2102  NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
2103  NewC.ICmpType == SystemZICMP::SignedOnly)
2104  return;
2105  // Convert LE and GT comparisons into LT and GE.
2106  if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
2107  NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
2108  if (CmpVal == uint64_t(-1))
2109  return;
2110  CmpVal += 1;
2111  NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2112  }
2113  // If the low N bits of Op1 are zero than the low N bits of Op0 can
2114  // be masked off without changing the result.
2115  MaskVal = -(CmpVal & -CmpVal);
2116  NewC.ICmpType = SystemZICMP::UnsignedOnly;
2117  }
2118  if (!MaskVal)
2119  return;
2120 
2121  // Check whether the combination of mask, comparison value and comparison
2122  // type are suitable.
2123  unsigned BitSize = NewC.Op0.getValueSizeInBits();
2124  unsigned NewCCMask, ShiftVal;
2125  if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2126  NewC.Op0.getOpcode() == ISD::SHL &&
2127  isSimpleShift(NewC.Op0, ShiftVal) &&
2128  (MaskVal >> ShiftVal != 0) &&
2129  ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
2130  (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2131  MaskVal >> ShiftVal,
2132  CmpVal >> ShiftVal,
2133  SystemZICMP::Any))) {
2134  NewC.Op0 = NewC.Op0.getOperand(0);
2135  MaskVal >>= ShiftVal;
2136  } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2137  NewC.Op0.getOpcode() == ISD::SRL &&
2138  isSimpleShift(NewC.Op0, ShiftVal) &&
2139  (MaskVal << ShiftVal != 0) &&
2140  ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
2141  (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2142  MaskVal << ShiftVal,
2143  CmpVal << ShiftVal,
2145  NewC.Op0 = NewC.Op0.getOperand(0);
2146  MaskVal <<= ShiftVal;
2147  } else {
2148  NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
2149  NewC.ICmpType);
2150  if (!NewCCMask)
2151  return;
2152  }
2153 
2154  // Go ahead and make the change.
2155  C.Opcode = SystemZISD::TM;
2156  C.Op0 = NewC.Op0;
2157  if (Mask && Mask->getZExtValue() == MaskVal)
2158  C.Op1 = SDValue(Mask, 0);
2159  else
2160  C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2161  C.CCValid = SystemZ::CCMASK_TM;
2162  C.CCMask = NewCCMask;
2163 }
2164 
2165 // See whether the comparison argument contains a redundant AND
2166 // and remove it if so. This sometimes happens due to the generic
2167 // BRCOND expansion.
2168 static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL,
2169  Comparison &C) {
2170  if (C.Op0.getOpcode() != ISD::AND)
2171  return;
2172  auto *Mask = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
2173  if (!Mask)
2174  return;
2175  KnownBits Known;
2176  DAG.computeKnownBits(C.Op0.getOperand(0), Known);
2177  if ((~Known.Zero).getZExtValue() & ~Mask->getZExtValue())
2178  return;
2179 
2180  C.Op0 = C.Op0.getOperand(0);
2181 }
2182 
2183 // Return a Comparison that tests the condition-code result of intrinsic
2184 // node Call against constant integer CC using comparison code Cond.
2185 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2186 // and CCValid is the set of possible condition-code results.
2187 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2188  SDValue Call, unsigned CCValid, uint64_t CC,
2189  ISD::CondCode Cond) {
2190  Comparison C(Call, SDValue());
2191  C.Opcode = Opcode;
2192  C.CCValid = CCValid;
2193  if (Cond == ISD::SETEQ)
2194  // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2195  C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2196  else if (Cond == ISD::SETNE)
2197  // ...and the inverse of that.
2198  C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2199  else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2200  // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2201  // always true for CC>3.
2202  C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2203  else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2204  // ...and the inverse of that.
2205  C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2206  else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2207  // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2208  // always true for CC>3.
2209  C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2210  else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2211  // ...and the inverse of that.
2212  C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2213  else
2214  llvm_unreachable("Unexpected integer comparison type");
2215  C.CCMask &= CCValid;
2216  return C;
2217 }
2218 
2219 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2220 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2221  ISD::CondCode Cond, const SDLoc &DL) {
2222  if (CmpOp1.getOpcode() == ISD::Constant) {
2223  uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2224  unsigned Opcode, CCValid;
2225  if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2226  CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2227  isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2228  return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2229  if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2230  CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2231  isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2232  return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2233  }
2234  Comparison C(CmpOp0, CmpOp1);
2235  C.CCMask = CCMaskForCondCode(Cond);
2236  if (C.Op0.getValueType().isFloatingPoint()) {
2237  C.CCValid = SystemZ::CCMASK_FCMP;
2238  C.Opcode = SystemZISD::FCMP;
2239  adjustForFNeg(C);
2240  } else {
2241  C.CCValid = SystemZ::CCMASK_ICMP;
2242  C.Opcode = SystemZISD::ICMP;
2243  // Choose the type of comparison. Equality and inequality tests can
2244  // use either signed or unsigned comparisons. The choice also doesn't
2245  // matter if both sign bits are known to be clear. In those cases we
2246  // want to give the main isel code the freedom to choose whichever
2247  // form fits best.
2248  if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2249  C.CCMask == SystemZ::CCMASK_CMP_NE ||
2250  (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2251  C.ICmpType = SystemZICMP::Any;
2252  else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2253  C.ICmpType = SystemZICMP::UnsignedOnly;
2254  else
2255  C.ICmpType = SystemZICMP::SignedOnly;
2256  C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2257  adjustForRedundantAnd(DAG, DL, C);
2258  adjustZeroCmp(DAG, DL, C);
2259  adjustSubwordCmp(DAG, DL, C);
2260  adjustForSubtraction(DAG, DL, C);
2261  adjustForLTGFR(C);
2262  adjustICmpTruncate(DAG, DL, C);
2263  }
2264 
2265  if (shouldSwapCmpOperands(C)) {
2266  std::swap(C.Op0, C.Op1);
2267  C.CCMask = reverseCCMask(C.CCMask);
2268  }
2269 
2270  adjustForTestUnderMask(DAG, DL, C);
2271  return C;
2272 }
2273 
2274 // Emit the comparison instruction described by C.
2275 static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2276  if (!C.Op1.getNode()) {
2277  SDValue Op;
2278  switch (C.Op0.getOpcode()) {
2280  Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2281  break;
2283  Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2284  break;
2285  default:
2286  llvm_unreachable("Invalid comparison operands");
2287  }
2288  return SDValue(Op.getNode(), Op->getNumValues() - 1);
2289  }
2290  if (C.Opcode == SystemZISD::ICMP)
2291  return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2292  DAG.getConstant(C.ICmpType, DL, MVT::i32));
2293  if (C.Opcode == SystemZISD::TM) {
2294  bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2295  bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2296  return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2297  DAG.getConstant(RegisterOnly, DL, MVT::i32));
2298  }
2299  return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2300 }
2301 
2302 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2303 // 64 bits. Extend is the extension type to use. Store the high part
2304 // in Hi and the low part in Lo.
2305 static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
2306  SDValue Op0, SDValue Op1, SDValue &Hi,
2307  SDValue &Lo) {
2308  Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2309  Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2310  SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2311  Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2312  DAG.getConstant(32, DL, MVT::i64));
2313  Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2314  Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2315 }
2316 
2317 // Lower a binary operation that produces two VT results, one in each
2318 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2319 // and Opcode performs the GR128 operation. Store the even register result
2320 // in Even and the odd register result in Odd.
2321 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2322  unsigned Opcode, SDValue Op0, SDValue Op1,
2323  SDValue &Even, SDValue &Odd) {
2324  SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
2325  bool Is32Bit = is32Bit(VT);
2326  Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2327  Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2328 }
2329 
2330 // Return an i32 value that is 1 if the CC value produced by Glue is
2331 // in the mask CCMask and 0 otherwise. CC is known to have a value
2332 // in CCValid, so other values can be ignored.
2333 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue Glue,
2334  unsigned CCValid, unsigned CCMask) {
2335  SDValue Ops[] = { DAG.getConstant(1, DL, MVT::i32),
2336  DAG.getConstant(0, DL, MVT::i32),
2337  DAG.getConstant(CCValid, DL, MVT::i32),
2338  DAG.getConstant(CCMask, DL, MVT::i32), Glue };
2339  return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, MVT::i32, Ops);
2340 }
2341 
2342 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2343 // be done directly. IsFP is true if CC is for a floating-point rather than
2344 // integer comparison.
2345 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2346  switch (CC) {
2347  case ISD::SETOEQ:
2348  case ISD::SETEQ:
2349  return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2350 
2351  case ISD::SETOGE:
2352  case ISD::SETGE:
2353  return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2354 
2355  case ISD::SETOGT:
2356  case ISD::SETGT:
2357  return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2358 
2359  case ISD::SETUGT:
2360  return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2361 
2362  default:
2363  return 0;
2364  }
2365 }
2366 
2367 // Return the SystemZISD vector comparison operation for CC or its inverse,
2368 // or 0 if neither can be done directly. Indicate in Invert whether the
2369 // result is for the inverse of CC. IsFP is true if CC is for a
2370 // floating-point rather than integer comparison.
2371 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2372  bool &Invert) {
2373  if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2374  Invert = false;
2375  return Opcode;
2376  }
2377 
2378  CC = ISD::getSetCCInverse(CC, !IsFP);
2379  if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2380  Invert = true;
2381  return Opcode;
2382  }
2383 
2384  return 0;
2385 }
2386 
2387 // Return a v2f64 that contains the extended form of elements Start and Start+1
2388 // of v4f32 value Op.
2389 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
2390  SDValue Op) {
2391  int Mask[] = { Start, -1, Start + 1, -1 };
2392  Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2393  return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2394 }
2395 
2396 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2397 // producing a result of type VT.
2398 SDValue SystemZTargetLowering::getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
2399  const SDLoc &DL, EVT VT,
2400  SDValue CmpOp0,
2401  SDValue CmpOp1) const {
2402  // There is no hardware support for v4f32 (unless we have the vector
2403  // enhancements facility 1), so extend the vector into two v2f64s
2404  // and compare those.
2405  if (CmpOp0.getValueType() == MVT::v4f32 &&
2406  !Subtarget.hasVectorEnhancements1()) {
2407  SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2408  SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2409  SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2410  SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2411  SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2412  SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2413  return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2414  }
2415  return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2416 }
2417 
2418 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2419 // an integer mask of type VT.
2420 SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
2421  const SDLoc &DL, EVT VT,
2422  ISD::CondCode CC,
2423  SDValue CmpOp0,
2424  SDValue CmpOp1) const {
2425  bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2426  bool Invert = false;
2427  SDValue Cmp;
2428  switch (CC) {
2429  // Handle tests for order using (or (ogt y x) (oge x y)).
2430  case ISD::SETUO:
2431  Invert = true;
2433  case ISD::SETO: {
2434  assert(IsFP && "Unexpected integer comparison");
2435  SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2436  SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2437  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2438  break;
2439  }
2440 
2441  // Handle <> tests using (or (ogt y x) (ogt x y)).
2442  case ISD::SETUEQ:
2443  Invert = true;
2445  case ISD::SETONE: {
2446  assert(IsFP && "Unexpected integer comparison");
2447  SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2448  SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2449  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2450  break;
2451  }
2452 
2453  // Otherwise a single comparison is enough. It doesn't really
2454  // matter whether we try the inversion or the swap first, since
2455  // there are no cases where both work.
2456  default:
2457  if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2458  Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2459  else {
2461  if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2462  Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2463  else
2464  llvm_unreachable("Unhandled comparison");
2465  }
2466  break;
2467  }
2468  if (Invert) {
2470  DAG.getConstant(65535, DL, MVT::i32));
2471  Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2472  Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2473  }
2474  return Cmp;
2475 }
2476 
2477 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2478  SelectionDAG &DAG) const {
2479  SDValue CmpOp0 = Op.getOperand(0);
2480  SDValue CmpOp1 = Op.getOperand(1);
2481  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2482  SDLoc DL(Op);
2483  EVT VT = Op.getValueType();
2484  if (VT.isVector())
2485  return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2486 
2487  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2488  SDValue Glue = emitCmp(DAG, DL, C);
2489  return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2490 }
2491 
2492 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2493  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2494  SDValue CmpOp0 = Op.getOperand(2);
2495  SDValue CmpOp1 = Op.getOperand(3);
2496  SDValue Dest = Op.getOperand(4);
2497  SDLoc DL(Op);
2498 
2499  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2500  SDValue Glue = emitCmp(DAG, DL, C);
2501  return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2502  Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2503  DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2504 }
2505 
2506 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2507 // allowing Pos and Neg to be wider than CmpOp.
2508 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2509  return (Neg.getOpcode() == ISD::SUB &&
2510  Neg.getOperand(0).getOpcode() == ISD::Constant &&
2511  cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2512  Neg.getOperand(1) == Pos &&
2513  (Pos == CmpOp ||
2514  (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2515  Pos.getOperand(0) == CmpOp)));
2516 }
2517 
2518 // Return the absolute or negative absolute of Op; IsNegative decides which.
2519 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2520  bool IsNegative) {
2521  Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2522  if (IsNegative)
2523  Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2524  DAG.getConstant(0, DL, Op.getValueType()), Op);
2525  return Op;
2526 }
2527 
2528 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2529  SelectionDAG &DAG) const {
2530  SDValue CmpOp0 = Op.getOperand(0);
2531  SDValue CmpOp1 = Op.getOperand(1);
2532  SDValue TrueOp = Op.getOperand(2);
2533  SDValue FalseOp = Op.getOperand(3);
2534  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2535  SDLoc DL(Op);
2536 
2537  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2538 
2539  // Check for absolute and negative-absolute selections, including those
2540  // where the comparison value is sign-extended (for LPGFR and LNGFR).
2541  // This check supplements the one in DAGCombiner.
2542  if (C.Opcode == SystemZISD::ICMP &&
2543  C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2544  C.CCMask != SystemZ::CCMASK_CMP_NE &&
2545  C.Op1.getOpcode() == ISD::Constant &&
2546  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2547  if (isAbsolute(C.Op0, TrueOp, FalseOp))
2548  return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2549  if (isAbsolute(C.Op0, FalseOp, TrueOp))
2550  return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2551  }
2552 
2553  SDValue Glue = emitCmp(DAG, DL, C);
2554  SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2555  DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2556 
2557  return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, Op.getValueType(), Ops);
2558 }
2559 
2560 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2561  SelectionDAG &DAG) const {
2562  SDLoc DL(Node);
2563  const GlobalValue *GV = Node->getGlobal();
2564  int64_t Offset = Node->getOffset();
2565  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2567 
2568  SDValue Result;
2569  if (Subtarget.isPC32DBLSymbol(GV, CM)) {
2570  // Assign anchors at 1<<12 byte boundaries.
2571  uint64_t Anchor = Offset & ~uint64_t(0xfff);
2572  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2573  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2574 
2575  // The offset can be folded into the address if it is aligned to a halfword.
2576  Offset -= Anchor;
2577  if (Offset != 0 && (Offset & 1) == 0) {
2578  SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2579  Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2580  Offset = 0;
2581  }
2582  } else {
2583  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2584  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2585  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2587  }
2588 
2589  // If there was a non-zero offset that we didn't fold, create an explicit
2590  // addition for it.
2591  if (Offset != 0)
2592  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2593  DAG.getConstant(Offset, DL, PtrVT));
2594 
2595  return Result;
2596 }
2597 
2598 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2599  SelectionDAG &DAG,
2600  unsigned Opcode,
2601  SDValue GOTOffset) const {
2602  SDLoc DL(Node);
2603  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2604  SDValue Chain = DAG.getEntryNode();
2605  SDValue Glue;
2606 
2607  // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2608  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2609  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2610  Glue = Chain.getValue(1);
2611  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2612  Glue = Chain.getValue(1);
2613 
2614  // The first call operand is the chain and the second is the TLS symbol.
2616  Ops.push_back(Chain);
2617  Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2618  Node->getValueType(0),
2619  0, 0));
2620 
2621  // Add argument registers to the end of the list so that they are
2622  // known live into the call.
2623  Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2624  Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2625 
2626  // Add a register mask operand representing the call-preserved registers.
2627  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2628  const uint32_t *Mask =
2630  assert(Mask && "Missing call preserved mask for calling convention");
2631  Ops.push_back(DAG.getRegisterMask(Mask));
2632 
2633  // Glue the call to the argument copies.
2634  Ops.push_back(Glue);
2635 
2636  // Emit the call.
2637  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2638  Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2639  Glue = Chain.getValue(1);
2640 
2641  // Copy the return value from %r2.
2642  return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2643 }
2644 
2645 SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
2646  SelectionDAG &DAG) const {
2647  SDValue Chain = DAG.getEntryNode();
2648  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2649 
2650  // The high part of the thread pointer is in access register 0.
2651  SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
2652  TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2653 
2654  // The low part of the thread pointer is in access register 1.
2655  SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
2656  TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2657 
2658  // Merge them into a single 64-bit address.
2659  SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2660  DAG.getConstant(32, DL, PtrVT));
2661  return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2662 }
2663 
2664 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2665  SelectionDAG &DAG) const {
2666  if (DAG.getTarget().Options.EmulatedTLS)
2667  return LowerToTLSEmulatedModel(Node, DAG);
2668  SDLoc DL(Node);
2669  const GlobalValue *GV = Node->getGlobal();
2670  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2671  TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2672 
2673  SDValue TP = lowerThreadPointer(DL, DAG);
2674 
2675  // Get the offset of GA from the thread pointer, based on the TLS model.
2676  SDValue Offset;
2677  switch (model) {
2678  case TLSModel::GeneralDynamic: {
2679  // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2682 
2683  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2684  Offset = DAG.getLoad(
2685  PtrVT, DL, DAG.getEntryNode(), Offset,
2687 
2688  // Call __tls_get_offset to retrieve the offset.
2689  Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2690  break;
2691  }
2692 
2693  case TLSModel::LocalDynamic: {
2694  // Load the GOT offset of the module ID.
2697 
2698  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2699  Offset = DAG.getLoad(
2700  PtrVT, DL, DAG.getEntryNode(), Offset,
2702 
2703  // Call __tls_get_offset to retrieve the module base offset.
2704  Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2705 
2706  // Note: The SystemZLDCleanupPass will remove redundant computations
2707  // of the module base offset. Count total number of local-dynamic
2708  // accesses to trigger execution of that pass.
2712 
2713  // Add the per-symbol offset.
2715 
2716  SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2717  DTPOffset = DAG.getLoad(
2718  PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2720 
2721  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2722  break;
2723  }
2724 
2725  case TLSModel::InitialExec: {
2726  // Load the offset from the GOT.
2727  Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2729  Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2730  Offset =
2731  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2733  break;
2734  }
2735 
2736  case TLSModel::LocalExec: {
2737  // Force the offset into the constant pool and load it from there.
2740 
2741  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2742  Offset = DAG.getLoad(
2743  PtrVT, DL, DAG.getEntryNode(), Offset,
2745  break;
2746  }
2747  }
2748 
2749  // Add the base and offset together.
2750  return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2751 }
2752 
2753 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2754  SelectionDAG &DAG) const {
2755  SDLoc DL(Node);
2756  const BlockAddress *BA = Node->getBlockAddress();
2757  int64_t Offset = Node->getOffset();
2758  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2759 
2760  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2761  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2762  return Result;
2763 }
2764 
2765 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2766  SelectionDAG &DAG) const {
2767  SDLoc DL(JT);
2768  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2769  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2770 
2771  // Use LARL to load the address of the table.
2772  return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2773 }
2774 
2775 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2776  SelectionDAG &DAG) const {
2777  SDLoc DL(CP);
2778  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2779 
2780  SDValue Result;
2781  if (CP->isMachineConstantPoolEntry())
2782  Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2783  CP->getAlignment());
2784  else
2785  Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2786  CP->getAlignment(), CP->getOffset());
2787 
2788  // Use LARL to load the address of the constant pool entry.
2789  return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2790 }
2791 
2792 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
2793  SelectionDAG &DAG) const {
2794  MachineFunction &MF = DAG.getMachineFunction();
2795  MachineFrameInfo &MFI = MF.getFrameInfo();
2796  MFI.setFrameAddressIsTaken(true);
2797 
2798  SDLoc DL(Op);
2799  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2800  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2801 
2802  // If the back chain frame index has not been allocated yet, do so.
2804  int BackChainIdx = FI->getFramePointerSaveIndex();
2805  if (!BackChainIdx) {
2806  // By definition, the frame address is the address of the back chain.
2807  BackChainIdx = MFI.CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
2808  FI->setFramePointerSaveIndex(BackChainIdx);
2809  }
2810  SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
2811 
2812  // FIXME The frontend should detect this case.
2813  if (Depth > 0) {
2814  report_fatal_error("Unsupported stack frame traversal count");
2815  }
2816 
2817  return BackChain;
2818 }
2819 
2820 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
2821  SelectionDAG &DAG) const {
2822  MachineFunction &MF = DAG.getMachineFunction();
2823  MachineFrameInfo &MFI = MF.getFrameInfo();
2824  MFI.setReturnAddressIsTaken(true);
2825 
2827  return SDValue();
2828 
2829  SDLoc DL(Op);
2830  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2831  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2832 
2833  // FIXME The frontend should detect this case.
2834  if (Depth > 0) {
2835  report_fatal_error("Unsupported stack frame traversal count");
2836  }
2837 
2838  // Return R14D, which has the return address. Mark it an implicit live-in.
2839  unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
2840  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
2841 }
2842 
2843 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2844  SelectionDAG &DAG) const {
2845  SDLoc DL(Op);
2846  SDValue In = Op.getOperand(0);
2847  EVT InVT = In.getValueType();
2848  EVT ResVT = Op.getValueType();
2849 
2850  // Convert loads directly. This is normally done by DAGCombiner,
2851  // but we need this case for bitcasts that are created during lowering
2852  // and which are then lowered themselves.
2853  if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2854  if (ISD::isNormalLoad(LoadN)) {
2855  SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(),
2856  LoadN->getBasePtr(), LoadN->getMemOperand());
2857  // Update the chain uses.
2858  DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1));
2859  return NewLoad;
2860  }
2861 
2862  if (InVT == MVT::i32 && ResVT == MVT::f32) {
2863  SDValue In64;
2864  if (Subtarget.hasHighWord()) {
2865  SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2866  MVT::i64);
2867  In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2868  MVT::i64, SDValue(U64, 0), In);
2869  } else {
2870  In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2871  In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2872  DAG.getConstant(32, DL, MVT::i64));
2873  }
2874  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2875  return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2876  DL, MVT::f32, Out64);
2877  }
2878  if (InVT == MVT::f32 && ResVT == MVT::i32) {
2879  SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2880  SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2881  MVT::f64, SDValue(U64, 0), In);
2882  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2883  if (Subtarget.hasHighWord())
2884  return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2885  MVT::i32, Out64);
2886  SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2887  DAG.getConstant(32, DL, MVT::i64));
2888  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2889  }
2890  llvm_unreachable("Unexpected bitcast combination");
2891 }
2892 
2893 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2894  SelectionDAG &DAG) const {
2895  MachineFunction &MF = DAG.getMachineFunction();
2896  SystemZMachineFunctionInfo *FuncInfo =
2898  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2899 
2900  SDValue Chain = Op.getOperand(0);
2901  SDValue Addr = Op.getOperand(1);
2902  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2903  SDLoc DL(Op);
2904 
2905  // The initial values of each field.
2906  const unsigned NumFields = 4;
2907  SDValue Fields[NumFields] = {
2908  DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2909  DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2910  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2911  DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2912  };
2913 
2914  // Store each field into its respective slot.
2915  SDValue MemOps[NumFields];
2916  unsigned Offset = 0;
2917  for (unsigned I = 0; I < NumFields; ++I) {
2918  SDValue FieldAddr = Addr;
2919  if (Offset != 0)
2920  FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2921  DAG.getIntPtrConstant(Offset, DL));
2922  MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2923  MachinePointerInfo(SV, Offset));
2924  Offset += 8;
2925  }
2926  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2927 }
2928 
2929 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2930  SelectionDAG &DAG) const {
2931  SDValue Chain = Op.getOperand(0);
2932  SDValue DstPtr = Op.getOperand(1);
2933  SDValue SrcPtr = Op.getOperand(2);
2934  const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2935  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2936  SDLoc DL(Op);
2937 
2938  return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2939  /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2940  /*isTailCall*/false,
2941  MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2942 }
2943 
2944 SDValue SystemZTargetLowering::
2945 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2946  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
2947  MachineFunction &MF = DAG.getMachineFunction();
2948  bool RealignOpt = !MF.getFunction().hasFnAttribute("no-realign-stack");
2949  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
2950 
2951  SDValue Chain = Op.getOperand(0);
2952  SDValue Size = Op.getOperand(1);
2953  SDValue Align = Op.getOperand(2);
2954  SDLoc DL(Op);
2955 
2956  // If user has set the no alignment function attribute, ignore
2957  // alloca alignments.
2958  uint64_t AlignVal = (RealignOpt ?
2959  dyn_cast<ConstantSDNode>(Align)->getZExtValue() : 0);
2960 
2961  uint64_t StackAlign = TFI->getStackAlignment();
2962  uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
2963  uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
2964 
2965  unsigned SPReg = getStackPointerRegisterToSaveRestore();
2966  SDValue NeededSpace = Size;
2967 
2968  // Get a reference to the stack pointer.
2969  SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2970 
2971  // If we need a backchain, save it now.
2972  SDValue Backchain;
2973  if (StoreBackchain)
2974  Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
2975 
2976  // Add extra space for alignment if needed.
2977  if (ExtraAlignSpace)
2978  NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
2979  DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2980 
2981  // Get the new stack pointer value.
2982  SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
2983 
2984  // Copy the new stack pointer back.
2985  Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2986 
2987  // The allocated data lives above the 160 bytes allocated for the standard
2988  // frame, plus any outgoing stack arguments. We don't know how much that
2989  // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2990  SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2991  SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2992 
2993  // Dynamically realign if needed.
2994  if (RequiredAlign > StackAlign) {
2995  Result =
2996  DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
2997  DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
2998  Result =
2999  DAG.getNode(ISD::AND, DL, MVT::i64, Result,
3000  DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
3001  }
3002 
3003  if (StoreBackchain)
3004  Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3005 
3006  SDValue Ops[2] = { Result, Chain };
3007  return DAG.getMergeValues(Ops, DL);
3008 }
3009 
3010 SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
3011  SDValue Op, SelectionDAG &DAG) const {
3012  SDLoc DL(Op);
3013 
3014  return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3015 }
3016 
3017 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
3018  SelectionDAG &DAG) const {
3019  EVT VT = Op.getValueType();
3020  SDLoc DL(Op);
3021  SDValue Ops[2];
3022  if (is32Bit(VT))
3023  // Just do a normal 64-bit multiplication and extract the results.
3024  // We define this so that it can be used for constant division.
3026  Op.getOperand(1), Ops[1], Ops[0]);
3027  else if (Subtarget.hasMiscellaneousExtensions2())
3028  // SystemZISD::SMUL_LOHI returns the low result in the odd register and
3029  // the high result in the even register. ISD::SMUL_LOHI is defined to
3030  // return the low half first, so the results are in reverse order.
3032  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3033  else {
3034  // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
3035  //
3036  // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
3037  //
3038  // but using the fact that the upper halves are either all zeros
3039  // or all ones:
3040  //
3041  // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
3042  //
3043  // and grouping the right terms together since they are quicker than the
3044  // multiplication:
3045  //
3046  // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
3047  SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
3048  SDValue LL = Op.getOperand(0);
3049  SDValue RL = Op.getOperand(1);
3050  SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
3051  SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
3052  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3053  // the high result in the even register. ISD::SMUL_LOHI is defined to
3054  // return the low half first, so the results are in reverse order.
3056  LL, RL, Ops[1], Ops[0]);
3057  SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
3058  SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
3059  SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
3060  Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
3061  }
3062  return DAG.getMergeValues(Ops, DL);
3063 }
3064 
3065 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
3066  SelectionDAG &DAG) const {
3067  EVT VT = Op.getValueType();
3068  SDLoc DL(Op);
3069  SDValue Ops[2];
3070  if (is32Bit(VT))
3071  // Just do a normal 64-bit multiplication and extract the results.
3072  // We define this so that it can be used for constant division.
3074  Op.getOperand(1), Ops[1], Ops[0]);
3075  else
3076  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3077  // the high result in the even register. ISD::UMUL_LOHI is defined to
3078  // return the low half first, so the results are in reverse order.
3080  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3081  return DAG.getMergeValues(Ops, DL);
3082 }
3083 
3084 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
3085  SelectionDAG &DAG) const {
3086  SDValue Op0 = Op.getOperand(0);
3087  SDValue Op1 = Op.getOperand(1);
3088  EVT VT = Op.getValueType();
3089  SDLoc DL(Op);
3090 
3091  // We use DSGF for 32-bit division. This means the first operand must
3092  // always be 64-bit, and the second operand should be 32-bit whenever
3093  // that is possible, to improve performance.
3094  if (is32Bit(VT))
3095  Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
3096  else if (DAG.ComputeNumSignBits(Op1) > 32)
3097  Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
3098 
3099  // DSG(F) returns the remainder in the even register and the
3100  // quotient in the odd register.
3101  SDValue Ops[2];
3102  lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
3103  return DAG.getMergeValues(Ops, DL);
3104 }
3105 
3106 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3107  SelectionDAG &DAG) const {
3108  EVT VT = Op.getValueType();
3109  SDLoc DL(Op);
3110 
3111  // DL(G) returns the remainder in the even register and the
3112  // quotient in the odd register.
3113  SDValue Ops[2];
3115  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3116  return DAG.getMergeValues(Ops, DL);
3117 }
3118 
3119 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3120  assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3121 
3122  // Get the known-zero masks for each operand.
3123  SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3124  KnownBits Known[2];
3125  DAG.computeKnownBits(Ops[0], Known[0]);
3126  DAG.computeKnownBits(Ops[1], Known[1]);
3127 
3128  // See if the upper 32 bits of one operand and the lower 32 bits of the
3129  // other are known zero. They are the low and high operands respectively.
3130  uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
3131  Known[1].Zero.getZExtValue() };
3132  unsigned High, Low;
3133  if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
3134  High = 1, Low = 0;
3135  else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
3136  High = 0, Low = 1;
3137  else
3138  return Op;
3139 
3140  SDValue LowOp = Ops[Low];
3141  SDValue HighOp = Ops[High];
3142 
3143  // If the high part is a constant, we're better off using IILH.
3144  if (HighOp.getOpcode() == ISD::Constant)
3145  return Op;
3146 
3147  // If the low part is a constant that is outside the range of LHI,
3148  // then we're better off using IILF.
3149  if (LowOp.getOpcode() == ISD::Constant) {
3150  int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
3151  if (!isInt<16>(Value))
3152  return Op;
3153  }
3154 
3155  // Check whether the high part is an AND that doesn't change the
3156  // high 32 bits and just masks out low bits. We can skip it if so.
3157  if (HighOp.getOpcode() == ISD::AND &&
3158  HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3159  SDValue HighOp0 = HighOp.getOperand(0);
3160  uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
3161  if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
3162  HighOp = HighOp0;
3163  }
3164 
3165  // Take advantage of the fact that all GR32 operations only change the
3166  // low 32 bits by truncating Low to an i32 and inserting it directly
3167  // using a subreg. The interesting cases are those where the truncation
3168  // can be folded.
3169  SDLoc DL(Op);
3170  SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
3171  return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
3172  MVT::i64, HighOp, Low32);
3173 }
3174 
3175 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3176  SelectionDAG &DAG) const {
3177  EVT VT = Op.getValueType();
3178  SDLoc DL(Op);
3179  Op = Op.getOperand(0);
3180 
3181  // Handle vector types via VPOPCT.
3182  if (VT.isVector()) {
3183  Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3184  Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3185  switch (VT.getScalarSizeInBits()) {
3186  case 8:
3187  break;
3188  case 16: {
3189  Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3190  SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
3191  SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3192  Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3193  Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3194  break;
3195  }
3196  case 32: {
3198  DAG.getConstant(0, DL, MVT::i32));
3199  Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3200  break;
3201  }
3202  case 64: {
3204  DAG.getConstant(0, DL, MVT::i32));
3205  Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3206  Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3207  break;
3208  }
3209  default:
3210  llvm_unreachable("Unexpected type");
3211  }
3212  return Op;
3213  }
3214 
3215  // Get the known-zero mask for the operand.
3216  KnownBits Known;
3217  DAG.computeKnownBits(Op, Known);
3218  unsigned NumSignificantBits = (~Known.Zero).getActiveBits();
3219  if (NumSignificantBits == 0)
3220  return DAG.getConstant(0, DL, VT);
3221 
3222  // Skip known-zero high parts of the operand.
3223  int64_t OrigBitSize = VT.getSizeInBits();
3224  int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3225  BitSize = std::min(BitSize, OrigBitSize);
3226 
3227  // The POPCNT instruction counts the number of bits in each byte.
3228  Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3229  Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3230  Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3231 
3232  // Add up per-byte counts in a binary tree. All bits of Op at
3233  // position larger than BitSize remain zero throughout.
3234  for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3235  SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3236  if (BitSize != OrigBitSize)
3237  Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3238  DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3239  Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3240  }
3241 
3242  // Extract overall result from high byte.
3243  if (BitSize > 8)
3244  Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3245  DAG.getConstant(BitSize - 8, DL, VT));
3246 
3247  return Op;
3248 }
3249 
3250 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3251  SelectionDAG &DAG) const {
3252  SDLoc DL(Op);
3253  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
3254  cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3255  SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
3256  cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3257 
3258  // The only fence that needs an instruction is a sequentially-consistent
3259  // cross-thread fence.
3260  if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
3261  FenceSSID == SyncScope::System) {
3262  return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
3263  Op.getOperand(0)),
3264  0);
3265  }
3266 
3267  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3268  return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3269 }
3270 
3271 // Op is an atomic load. Lower it into a normal volatile load.
3272 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3273  SelectionDAG &DAG) const {
3274  auto *Node = cast<AtomicSDNode>(Op.getNode());
3275  return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3276  Node->getChain(), Node->getBasePtr(),
3277  Node->getMemoryVT(), Node->getMemOperand());
3278 }
3279 
3280 // Op is an atomic store. Lower it into a normal volatile store.
3281 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3282  SelectionDAG &DAG) const {
3283  auto *Node = cast<AtomicSDNode>(Op.getNode());
3284  SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3285  Node->getBasePtr(), Node->getMemoryVT(),
3286  Node->getMemOperand());
3287  // We have to enforce sequential consistency by performing a
3288  // serialization operation after the store.
3289  if (Node->getOrdering() == AtomicOrdering::SequentiallyConsistent)
3290  Chain = SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op),
3291  MVT::Other, Chain), 0);
3292  return Chain;
3293 }
3294 
3295 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3296 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3297 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3298  SelectionDAG &DAG,
3299  unsigned Opcode) const {
3300  auto *Node = cast<AtomicSDNode>(Op.getNode());
3301 
3302  // 32-bit operations need no code outside the main loop.
3303  EVT NarrowVT = Node->getMemoryVT();
3304  EVT WideVT = MVT::i32;
3305  if (NarrowVT == WideVT)
3306  return Op;
3307 
3308  int64_t BitSize = NarrowVT.getSizeInBits();
3309  SDValue ChainIn = Node->getChain();
3310  SDValue Addr = Node->getBasePtr();
3311  SDValue Src2 = Node->getVal();
3312  MachineMemOperand *MMO = Node->getMemOperand();
3313  SDLoc DL(Node);
3314  EVT PtrVT = Addr.getValueType();
3315 
3316  // Convert atomic subtracts of constants into additions.
3317  if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3318  if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3320  Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3321  }
3322 
3323  // Get the address of the containing word.
3324  SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3325  DAG.getConstant(-4, DL, PtrVT));
3326 
3327  // Get the number of bits that the word must be rotated left in order
3328  // to bring the field to the top bits of a GR32.
3329  SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3330  DAG.getConstant(3, DL, PtrVT));
3331  BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3332 
3333  // Get the complementing shift amount, for rotating a field in the top
3334  // bits back to its proper position.
3335  SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3336  DAG.getConstant(0, DL, WideVT), BitShift);
3337 
3338  // Extend the source operand to 32 bits and prepare it for the inner loop.
3339  // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3340  // operations require the source to be shifted in advance. (This shift
3341  // can be folded if the source is constant.) For AND and NAND, the lower
3342  // bits must be set, while for other opcodes they should be left clear.
3343  if (Opcode != SystemZISD::ATOMIC_SWAPW)
3344  Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3345  DAG.getConstant(32 - BitSize, DL, WideVT));
3346  if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3348  Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3349  DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3350 
3351  // Construct the ATOMIC_LOADW_* node.
3352  SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3353  SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3354  DAG.getConstant(BitSize, DL, WideVT) };
3355  SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3356  NarrowVT, MMO);
3357 
3358  // Rotate the result of the final CS so that the field is in the lower
3359  // bits of a GR32, then truncate it.
3360  SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3361  DAG.getConstant(BitSize, DL, WideVT));
3362  SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3363 
3364  SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3365  return DAG.getMergeValues(RetOps, DL);
3366 }
3367 
3368 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3369 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3370 // operations into additions.
3371 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3372  SelectionDAG &DAG) const {
3373  auto *Node = cast<AtomicSDNode>(Op.getNode());
3374  EVT MemVT = Node->getMemoryVT();
3375  if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3376  // A full-width operation.
3377  assert(Op.getValueType() == MemVT && "Mismatched VTs");
3378  SDValue Src2 = Node->getVal();
3379  SDValue NegSrc2;
3380  SDLoc DL(Src2);
3381 
3382  if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3383  // Use an addition if the operand is constant and either LAA(G) is
3384  // available or the negative value is in the range of A(G)FHI.
3385  int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3386  if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3387  NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3388  } else if (Subtarget.hasInterlockedAccess1())
3389  // Use LAA(G) if available.
3390  NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3391  Src2);
3392 
3393  if (NegSrc2.getNode())
3394  return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3395  Node->getChain(), Node->getBasePtr(), NegSrc2,
3396  Node->getMemOperand());
3397 
3398  // Use the node as-is.
3399  return Op;
3400  }
3401 
3402  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3403 }
3404 
3405 // Lower 8/16/32/64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS node.
3406 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3407  SelectionDAG &DAG) const {
3408  auto *Node = cast<AtomicSDNode>(Op.getNode());
3409  SDValue ChainIn = Node->getOperand(0);
3410  SDValue Addr = Node->getOperand(1);
3411  SDValue CmpVal = Node->getOperand(2);
3412  SDValue SwapVal = Node->getOperand(3);
3413  MachineMemOperand *MMO = Node->getMemOperand();
3414  SDLoc DL(Node);
3415 
3416  // We have native support for 32-bit and 64-bit compare and swap, but we
3417  // still need to expand extracting the "success" result from the CC.
3418  EVT NarrowVT = Node->getMemoryVT();
3419  EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
3420  if (NarrowVT == WideVT) {
3421  SDVTList Tys = DAG.getVTList(WideVT, MVT::Other, MVT::Glue);
3422  SDValue Ops[] = { ChainIn, Addr, CmpVal, SwapVal };
3424  DL, Tys, Ops, NarrowVT, MMO);
3425  SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(2),
3427 
3428  DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
3430  DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(1));
3431  return SDValue();
3432  }
3433 
3434  // Convert 8-bit and 16-bit compare and swap to a loop, implemented
3435  // via a fullword ATOMIC_CMP_SWAPW operation.
3436  int64_t BitSize = NarrowVT.getSizeInBits();
3437  EVT PtrVT = Addr.getValueType();
3438 
3439  // Get the address of the containing word.
3440  SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3441  DAG.getConstant(-4, DL, PtrVT));
3442 
3443  // Get the number of bits that the word must be rotated left in order
3444  // to bring the field to the top bits of a GR32.
3445  SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3446  DAG.getConstant(3, DL, PtrVT));
3447  BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3448 
3449  // Get the complementing shift amount, for rotating a field in the top
3450  // bits back to its proper position.
3451  SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3452  DAG.getConstant(0, DL, WideVT), BitShift);
3453 
3454  // Construct the ATOMIC_CMP_SWAPW node.
3455  SDVTList VTList = DAG.getVTList(WideVT, MVT::Other, MVT::Glue);
3456  SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3457  NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3459  VTList, Ops, NarrowVT, MMO);
3460  SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(2),
3462 
3463  DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
3465  DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(1));
3466  return SDValue();
3467 }
3468 
3469 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3470  SelectionDAG &DAG) const {
3471  MachineFunction &MF = DAG.getMachineFunction();
3472  MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3473  return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3474  SystemZ::R15D, Op.getValueType());
3475 }
3476 
3477 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3478  SelectionDAG &DAG) const {
3479  MachineFunction &MF = DAG.getMachineFunction();
3480  MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3481  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
3482 
3483  SDValue Chain = Op.getOperand(0);
3484  SDValue NewSP = Op.getOperand(1);
3485  SDValue Backchain;
3486  SDLoc DL(Op);
3487 
3488  if (StoreBackchain) {
3489  SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
3490  Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
3491  }
3492 
3493  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
3494 
3495  if (StoreBackchain)
3496  Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3497 
3498  return Chain;
3499 }
3500 
3501 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3502  SelectionDAG &DAG) const {
3503  bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3504  if (!IsData)
3505  // Just preserve the chain.
3506  return Op.getOperand(0);
3507 
3508  SDLoc DL(Op);
3509  bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3510  unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3511  auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3512  SDValue Ops[] = {
3513  Op.getOperand(0),
3514  DAG.getConstant(Code, DL, MVT::i32),
3515  Op.getOperand(1)
3516  };
3518  Node->getVTList(), Ops,
3519  Node->getMemoryVT(), Node->getMemOperand());
3520 }
3521 
3522 // Return an i32 that contains the value of CC immediately after After,
3523 // whose final operand must be MVT::Glue.
3524 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3525  SDLoc DL(After);
3526  SDValue Glue = SDValue(After, After->getNumValues() - 1);
3527  SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3528  return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3530 }
3531 
3532 SDValue
3533 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3534  SelectionDAG &DAG) const {
3535  unsigned Opcode, CCValid;
3536  if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3537  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3538  SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3539  SDValue CC = getCCResult(DAG, Glued.getNode());
3540  DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3541  return SDValue();
3542  }
3543 
3544  return SDValue();
3545 }
3546 
3547 SDValue
3548 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3549  SelectionDAG &DAG) const {
3550  unsigned Opcode, CCValid;
3551  if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3552  SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3553  SDValue CC = getCCResult(DAG, Glued.getNode());
3554  if (Op->getNumValues() == 1)
3555  return CC;
3556  assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3557  return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3558  CC);
3559  }
3560 
3561  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3562  switch (Id) {
3563  case Intrinsic::thread_pointer:
3564  return lowerThreadPointer(SDLoc(Op), DAG);
3565 
3566  case Intrinsic::s390_vpdi:
3567  return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3568  Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3569 
3570  case Intrinsic::s390_vperm:
3571  return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3572  Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3573 
3574  case Intrinsic::s390_vuphb:
3575  case Intrinsic::s390_vuphh:
3576  case Intrinsic::s390_vuphf:
3577  return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3578  Op.getOperand(1));
3579 
3580  case Intrinsic::s390_vuplhb:
3581  case Intrinsic::s390_vuplhh:
3582  case Intrinsic::s390_vuplhf:
3583  return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3584  Op.getOperand(1));
3585 
3586  case Intrinsic::s390_vuplb:
3587  case Intrinsic::s390_vuplhw:
3588  case Intrinsic::s390_vuplf:
3589  return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3590  Op.getOperand(1));
3591 
3592  case Intrinsic::s390_vupllb:
3593  case Intrinsic::s390_vupllh:
3594  case Intrinsic::s390_vupllf:
3595  return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3596  Op.getOperand(1));
3597 
3598  case Intrinsic::s390_vsumb:
3599  case Intrinsic::s390_vsumh:
3600  case Intrinsic::s390_vsumgh:
3601  case Intrinsic::s390_vsumgf:
3602  case Intrinsic::s390_vsumqf:
3603  case Intrinsic::s390_vsumqg:
3604  return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3605  Op.getOperand(1), Op.getOperand(2));
3606  }
3607 
3608  return SDValue();
3609 }
3610 
3611 namespace {
3612 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3613 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3614 // Operand is the constant third operand, otherwise it is the number of
3615 // bytes in each element of the result.
3616 struct Permute {
3617  unsigned Opcode;
3618  unsigned Operand;
3619  unsigned char Bytes[SystemZ::VectorBytes];
3620 };
3621 }
3622 
3623 static const Permute PermuteForms[] = {
3624  // VMRHG
3626  { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3627  // VMRHF
3629  { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3630  // VMRHH
3632  { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3633  // VMRHB
3635  { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3636  // VMRLG
3637  { SystemZISD::MERGE_LOW, 8,
3638  { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3639  // VMRLF
3640  { SystemZISD::MERGE_LOW, 4,
3641  { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3642  // VMRLH
3643  { SystemZISD::MERGE_LOW, 2,
3644  { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3645  // VMRLB
3646  { SystemZISD::MERGE_LOW, 1,
3647  { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3648  // VPKG
3649  { SystemZISD::PACK, 4,
3650  { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3651  // VPKF
3652  { SystemZISD::PACK, 2,
3653  { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3654  // VPKH
3655  { SystemZISD::PACK, 1,
3656  { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3657  // VPDI V1, V2, 4 (low half of V1, high half of V2)
3659  { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3660  // VPDI V1, V2, 1 (high half of V1, low half of V2)
3662  { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3663 };
3664 
3665 // Called after matching a vector shuffle against a particular pattern.
3666 // Both the original shuffle and the pattern have two vector operands.
3667 // OpNos[0] is the operand of the original shuffle that should be used for
3668 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3669 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3670 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3671 // for operands 0 and 1 of the pattern.
3672 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3673  if (OpNos[0] < 0) {
3674  if (OpNos[1] < 0)
3675  return false;
3676  OpNo0 = OpNo1 = OpNos[1];
3677  } else if (OpNos[1] < 0) {
3678  OpNo0 = OpNo1 = OpNos[0];
3679  } else {
3680  OpNo0 = OpNos[0];
3681  OpNo1 = OpNos[1];
3682  }
3683  return true;
3684 }
3685 
3686 // Bytes is a VPERM-like permute vector, except that -1 is used for
3687 // undefined bytes. Return true if the VPERM can be implemented using P.
3688 // When returning true set OpNo0 to the VPERM operand that should be
3689 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3690 //
3691 // For example, if swapping the VPERM operands allows P to match, OpNo0
3692 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3693 // operand, but rewriting it to use two duplicated operands allows it to
3694 // match P, then OpNo0 and OpNo1 will be the same.
3695 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3696  unsigned &OpNo0, unsigned &OpNo1) {
3697  int OpNos[] = { -1, -1 };
3698  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3699  int Elt = Bytes[I];
3700  if (Elt >= 0) {
3701  // Make sure that the two permute vectors use the same suboperand
3702  // byte number. Only the operand numbers (the high bits) are
3703  // allowed to differ.
3704  if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3705  return false;
3706  int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3707  int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3708  // Make sure that the operand mappings are consistent with previous
3709  // elements.
3710  if (OpNos[ModelOpNo] == 1 - RealOpNo)
3711  return false;
3712  OpNos[ModelOpNo] = RealOpNo;
3713  }
3714  }
3715  return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3716 }
3717 
3718 // As above, but search for a matching permute.
3719 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3720  unsigned &OpNo0, unsigned &OpNo1) {
3721  for (auto &P : PermuteForms)
3722  if (matchPermute(Bytes, P, OpNo0, OpNo1))
3723  return &P;
3724  return nullptr;
3725 }
3726 
3727 // Bytes is a VPERM-like permute vector, except that -1 is used for
3728 // undefined bytes. This permute is an operand of an outer permute.
3729 // See whether redistributing the -1 bytes gives a shuffle that can be
3730 // implemented using P. If so, set Transform to a VPERM-like permute vector
3731 // that, when applied to the result of P, gives the original permute in Bytes.
3732 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3733  const Permute &P,
3734  SmallVectorImpl<int> &Transform) {
3735  unsigned To = 0;
3736  for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3737  int Elt = Bytes[From];
3738  if (Elt < 0)
3739  // Byte number From of the result is undefined.
3740  Transform[From] = -1;
3741  else {
3742  while (P.Bytes[To] != Elt) {
3743  To += 1;
3744  if (To == SystemZ::VectorBytes)
3745  return false;
3746  }
3747  Transform[From] = To;
3748  }
3749  }
3750  return true;
3751 }
3752 
3753 // As above, but search for a matching permute.
3754 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3755  SmallVectorImpl<int> &Transform) {
3756  for (auto &P : PermuteForms)
3757  if (matchDoublePermute(Bytes, P, Transform))
3758  return &P;
3759  return nullptr;
3760 }
3761 
3762 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3763 // as if it had type vNi8.
3765  SmallVectorImpl<int> &Bytes) {
3766  EVT VT = VSN->getValueType(0);
3767  unsigned NumElements = VT.getVectorNumElements();
3768  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3769  Bytes.resize(NumElements * BytesPerElement, -1);
3770  for (unsigned I = 0; I < NumElements; ++I) {
3771  int Index = VSN->getMaskElt(I);
3772  if (Index >= 0)
3773  for (unsigned J = 0; J < BytesPerElement; ++J)
3774  Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3775  }
3776 }
3777 
3778 // Bytes is a VPERM-like permute vector, except that -1 is used for
3779 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3780 // the result come from a contiguous sequence of bytes from one input.
3781 // Set Base to the selector for the first byte if so.
3782 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3783  unsigned BytesPerElement, int &Base) {
3784  Base = -1;
3785  for (unsigned I = 0; I < BytesPerElement; ++I) {
3786  if (Bytes[Start + I] >= 0) {
3787  unsigned Elem = Bytes[Start + I];
3788  if (Base < 0) {
3789  Base = Elem - I;
3790  // Make sure the bytes would come from one input operand.
3791  if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3792  return false;
3793  } else if (unsigned(Base) != Elem - I)
3794  return false;
3795  }
3796  }
3797  return true;
3798 }
3799 
3800 // Bytes is a VPERM-like permute vector, except that -1 is used for
3801 // undefined bytes. Return true if it can be performed using VSLDI.
3802 // When returning true, set StartIndex to the shift amount and OpNo0
3803 // and OpNo1 to the VPERM operands that should be used as the first
3804 // and second shift operand respectively.
3805 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3806  unsigned &StartIndex, unsigned &OpNo0,
3807  unsigned &OpNo1) {
3808  int OpNos[] = { -1, -1 };
3809  int Shift = -1;
3810  for (unsigned I = 0; I < 16; ++I) {
3811  int Index = Bytes[I];
3812  if (Index >= 0) {
3813  int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3814  int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3815  int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3816  if (Shift < 0)
3817  Shift = ExpectedShift;
3818  else if (Shift != ExpectedShift)
3819  return false;
3820  // Make sure that the operand mappings are consistent with previous
3821  // elements.
3822  if (OpNos[ModelOpNo] == 1 - RealOpNo)
3823  return false;
3824  OpNos[ModelOpNo] = RealOpNo;
3825  }
3826  }
3827  StartIndex = Shift;
3828  return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3829 }
3830 
3831 // Create a node that performs P on operands Op0 and Op1, casting the
3832 // operands to the appropriate type. The type of the result is determined by P.
3833 static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3834  const Permute &P, SDValue Op0, SDValue Op1) {
3835  // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3836  // elements of a PACK are twice as wide as the outputs.
3837  unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3838  P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3839  P.Operand);
3840  // Cast both operands to the appropriate type.
3841  MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3842  SystemZ::VectorBytes / InBytes);
3843  Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3844  Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3845  SDValue Op;
3846  if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3847  SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3848  Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3849  } else if (P.Opcode == SystemZISD::PACK) {
3850  MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3851  SystemZ::VectorBytes / P.Operand);
3852  Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3853  } else {
3854  Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3855  }
3856  return Op;
3857 }
3858 
3859 // Bytes is a VPERM-like permute vector, except that -1 is used for
3860 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3861 // VSLDI or VPERM.
3863  SDValue *Ops,
3864  const SmallVectorImpl<int> &Bytes) {
3865  for (unsigned I = 0; I < 2; ++I)
3866  Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3867 
3868  // First see whether VSLDI can be used.
3869  unsigned StartIndex, OpNo0, OpNo1;
3870  if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3871  return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3872  Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3873 
3874  // Fall back on VPERM. Construct an SDNode for the permute vector.
3875  SDValue IndexNodes[SystemZ::VectorBytes];
3876  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3877  if (Bytes[I] >= 0)
3878  IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3879  else
3880  IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3881  SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
3882  return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3883 }
3884 
3885 namespace {
3886 // Describes a general N-operand vector shuffle.
3887 struct GeneralShuffle {
3888  GeneralShuffle(EVT vt) : VT(vt) {}
3889  void addUndef();
3890  bool add(SDValue, unsigned);
3891  SDValue getNode(SelectionDAG &, const SDLoc &);
3892 
3893  // The operands of the shuffle.
3895 
3896  // Index I is -1 if byte I of the result is undefined. Otherwise the
3897  // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3898  // Bytes[I] / SystemZ::VectorBytes.
3900 
3901  // The type of the shuffle result.
3902  EVT VT;
3903 };
3904 }
3905 
3906 // Add an extra undefined element to the shuffle.
3907 void GeneralShuffle::addUndef() {
3908  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3909  for (unsigned I = 0; I < BytesPerElement; ++I)
3910  Bytes.push_back(-1);
3911 }
3912 
3913 // Add an extra element to the shuffle, taking it from element Elem of Op.
3914 // A null Op indicates a vector input whose value will be calculated later;
3915 // there is at most one such input per shuffle and it always has the same
3916 // type as the result. Aborts and returns false if the source vector elements
3917 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
3918 // LLVM they become implicitly extended, but this is rare and not optimized.
3919 bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
3920  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3921 
3922  // The source vector can have wider elements than the result,
3923  // either through an explicit TRUNCATE or because of type legalization.
3924  // We want the least significant part.
3925  EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3926  unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3927 
3928  // Return false if the source elements are smaller than their destination
3929  // elements.
3930  if (FromBytesPerElement < BytesPerElement)
3931  return false;
3932 
3933  unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3934  (FromBytesPerElement - BytesPerElement));
3935 
3936  // Look through things like shuffles and bitcasts.
3937  while (Op.getNode()) {
3938  if (Op.getOpcode() == ISD::BITCAST)
3939  Op = Op.getOperand(0);
3940  else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3941  // See whether the bytes we need come from a contiguous part of one
3942  // operand.
3944  getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3945  int NewByte;
3946  if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3947  break;
3948  if (NewByte < 0) {
3949  addUndef();
3950  return true;
3951  }
3952  Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3953  Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3954  } else if (Op.isUndef()) {
3955  addUndef();
3956  return true;
3957  } else
3958  break;
3959  }
3960 
3961  // Make sure that the source of the extraction is in Ops.
3962  unsigned OpNo = 0;
3963  for (; OpNo < Ops.size(); ++OpNo)
3964  if (Ops[OpNo] == Op)
3965  break;
3966  if (OpNo == Ops.size())
3967  Ops.push_back(Op);
3968 
3969  // Add the element to Bytes.
3970  unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3971  for (unsigned I = 0; I < BytesPerElement; ++I)
3972  Bytes.push_back(Base + I);
3973 
3974  return true;
3975 }
3976 
3977 // Return SDNodes for the completed shuffle.
3978 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
3979  assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3980 
3981  if (Ops.size() == 0)
3982  return DAG.getUNDEF(VT);
3983 
3984  // Make sure that there are at least two shuffle operands.
3985  if (Ops.size() == 1)
3986  Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3987 
3988  // Create a tree of shuffles, deferring root node until after the loop.
3989  // Try to redistribute the undefined elements of non-root nodes so that
3990  // the non-root shuffles match something like a pack or merge, then adjust
3991  // the parent node's permute vector to compensate for the new order.
3992  // Among other things, this copes with vectors like <2 x i16> that were
3993  // padded with undefined elements during type legalization.
3994  //
3995  // In the best case this redistribution will lead to the whole tree
3996  // using packs and merges. It should rarely be a loss in other cases.
3997  unsigned Stride = 1;
3998  for (; Stride * 2 < Ops.size(); Stride *= 2) {
3999  for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
4000  SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
4001 
4002  // Create a mask for just these two operands.
4004  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4005  unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
4006  unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
4007  if (OpNo == I)
4008  NewBytes[J] = Byte;
4009  else if (OpNo == I + Stride)
4010  NewBytes[J] = SystemZ::VectorBytes + Byte;
4011  else
4012  NewBytes[J] = -1;
4013  }
4014  // See if it would be better to reorganize NewMask to avoid using VPERM.
4015  SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
4016  if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
4017  Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
4018  // Applying NewBytesMap to Ops[I] gets back to NewBytes.
4019  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4020  if (NewBytes[J] >= 0) {
4021  assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
4022  "Invalid double permute");
4023  Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
4024  } else
4025  assert(NewBytesMap[J] < 0 && "Invalid double permute");
4026  }
4027  } else {
4028  // Just use NewBytes on the operands.
4029  Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
4030  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
4031  if (NewBytes[J] >= 0)
4032  Bytes[J] = I * SystemZ::VectorBytes + J;
4033  }
4034  }
4035  }
4036 
4037  // Now we just have 2 inputs. Put the second operand in Ops[1].
4038  if (Stride > 1) {
4039  Ops[1] = Ops[Stride];
4040  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4041  if (Bytes[I] >= int(SystemZ::VectorBytes))
4042  Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
4043  }
4044 
4045  // Look for an instruction that can do the permute without resorting
4046  // to VPERM.
4047  unsigned OpNo0, OpNo1;
4048  SDValue Op;
4049  if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
4050  Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
4051  else
4052  Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
4053  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4054 }
4055 
4056 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
4057 static bool isScalarToVector(SDValue Op) {
4058  for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
4059  if (!Op.getOperand(I).isUndef())
4060  return false;
4061  return true;
4062 }
4063 
4064 // Return a vector of type VT that contains Value in the first element.
4065 // The other elements don't matter.
4066 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4067  SDValue Value) {
4068  // If we have a constant, replicate it to all elements and let the
4069  // BUILD_VECTOR lowering take care of it.
4070  if (Value.getOpcode() == ISD::Constant ||
4071  Value.getOpcode() == ISD::ConstantFP) {
4073  return DAG.getBuildVector(VT, DL, Ops);
4074  }
4075  if (Value.isUndef())
4076  return DAG.getUNDEF(VT);
4077  return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4078 }
4079 
4080 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
4081 // element 1. Used for cases in which replication is cheap.
4082 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4083  SDValue Op0, SDValue Op1) {
4084  if (Op0.isUndef()) {
4085  if (Op1.isUndef())
4086  return DAG.getUNDEF(VT);
4087  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
4088  }
4089  if (Op1.isUndef())
4090  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
4091  return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
4092  buildScalarToVector(DAG, DL, VT, Op0),
4093  buildScalarToVector(DAG, DL, VT, Op1));
4094 }
4095 
4096 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4097 // vector for them.
4098 static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
4099  SDValue Op1) {
4100  if (Op0.isUndef() && Op1.isUndef())
4101  return DAG.getUNDEF(MVT::v2i64);
4102  // If one of the two inputs is undefined then replicate the other one,
4103  // in order to avoid using another register unnecessarily.
4104  if (Op0.isUndef())
4105  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4106  else if (Op1.isUndef())
4107  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4108  else {
4109  Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4110  Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4111  }
4112  return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4113 }
4114 
4115 // Try to represent constant BUILD_VECTOR node BVN using a
4116 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
4117 // on success.
4118 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
4119  EVT ElemVT = BVN->getValueType(0).getVectorElementType();
4120  unsigned BytesPerElement = ElemVT.getStoreSize();
4121  for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
4122  SDValue Op = BVN->getOperand(I);
4123  if (!Op.isUndef()) {
4124  uint64_t Value;
4125  if (Op.getOpcode() == ISD::Constant)
4126  Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
4127  else if (Op.getOpcode() == ISD::ConstantFP)
4128  Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
4129  .getZExtValue());
4130  else
4131  return false;
4132  for (unsigned J = 0; J < BytesPerElement; ++J) {
4133  uint64_t Byte = (Value >> (J * 8)) & 0xff;
4134  if (Byte == 0xff)
4135  Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
4136  else if (Byte != 0)
4137  return false;
4138  }
4139  }
4140  }
4141  return true;
4142 }
4143 
4144 // Try to load a vector constant in which BitsPerElement-bit value Value
4145 // is replicated to fill the vector. VT is the type of the resulting
4146 // constant, which may have elements of a different size from BitsPerElement.
4147 // Return the SDValue of the constant on success, otherwise return
4148 // an empty value.
4150  const SystemZInstrInfo *TII,
4151  const SDLoc &DL, EVT VT, uint64_t Value,
4152  unsigned BitsPerElement) {
4153  // Signed 16-bit values can be replicated using VREPI.
4154  int64_t SignedValue = SignExtend64(Value, BitsPerElement);
4155  if (isInt<16>(SignedValue)) {
4156  MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4157  SystemZ::VectorBits / BitsPerElement);
4158  SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
4159  DAG.getConstant(SignedValue, DL, MVT::i32));
4160  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4161  }
4162  // See whether rotating the constant left some N places gives a value that
4163  // is one less than a power of 2 (i.e. all zeros followed by all ones).
4164  // If so we can use VGM.
4165  unsigned Start, End;
4166  if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
4167  // isRxSBGMask returns the bit numbers for a full 64-bit value,
4168  // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
4169  // bit numbers for an BitsPerElement value, so that 0 denotes
4170  // 1 << (BitsPerElement-1).
4171  Start -= 64 - BitsPerElement;
4172  End -= 64 - BitsPerElement;
4173  MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4174  SystemZ::VectorBits / BitsPerElement);
4175  SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
4176  DAG.getConstant(Start, DL, MVT::i32),
4177  DAG.getConstant(End, DL, MVT::i32));
4178  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4179  }
4180  return SDValue();
4181 }
4182 
4183 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4184 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4185 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4186 // would benefit from this representation and return it if so.
4188  BuildVectorSDNode *BVN) {
4189  EVT VT = BVN->getValueType(0);
4190  unsigned NumElements = VT.getVectorNumElements();
4191 
4192  // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4193  // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4194  // need a BUILD_VECTOR, add an additional placeholder operand for that
4195  // BUILD_VECTOR and store its operands in ResidueOps.
4196  GeneralShuffle GS(VT);
4198  bool FoundOne = false;
4199  for (unsigned I = 0; I < NumElements; ++I) {
4200  SDValue Op = BVN->getOperand(I);
4201  if (Op.getOpcode() == ISD::TRUNCATE)
4202  Op = Op.getOperand(0);
4203  if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4204  Op.getOperand(1).getOpcode() == ISD::Constant) {
4205  unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4206  if (!GS.add(Op.getOperand(0), Elem))
4207  return SDValue();
4208  FoundOne = true;
4209  } else if (Op.isUndef()) {
4210  GS.addUndef();
4211  } else {
4212  if (!GS.add(SDValue(), ResidueOps.size()))
4213  return SDValue();
4214  ResidueOps.push_back(BVN->getOperand(I));
4215  }
4216  }
4217 
4218  // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
4219  if (!FoundOne)
4220  return SDValue();
4221 
4222  // Create the BUILD_VECTOR for the remaining elements, if any.
4223  if (!ResidueOps.empty()) {
4224  while (ResidueOps.size() < NumElements)
4225  ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
4226  for (auto &Op : GS.Ops) {
4227  if (!Op.getNode()) {
4228  Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4229  break;
4230  }
4231  }
4232  }
4233  return GS.getNode(DAG, SDLoc(BVN));
4234 }
4235 
4236 // Combine GPR scalar values Elems into a vector of type VT.
4237 static SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4238  SmallVectorImpl<SDValue> &Elems) {
4239  // See whether there is a single replicated value.
4240  SDValue Single;
4241  unsigned int NumElements = Elems.size();
4242  unsigned int Count = 0;
4243  for (auto Elem : Elems) {
4244  if (!Elem.isUndef()) {
4245  if (!Single.getNode())
4246  Single = Elem;
4247  else if (Elem != Single) {
4248  Single = SDValue();
4249  break;
4250  }
4251  Count += 1;
4252  }
4253  }
4254  // There are three cases here:
4255  //
4256  // - if the only defined element is a loaded one, the best sequence
4257  // is a replicating load.
4258  //
4259  // - otherwise, if the only defined element is an i64 value, we will
4260  // end up with the same VLVGP sequence regardless of whether we short-cut
4261  // for replication or fall through to the later code.
4262  //
4263  // - otherwise, if the only defined element is an i32 or smaller value,
4264  // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
4265  // This is only a win if the single defined element is used more than once.
4266  // In other cases we're better off using a single VLVGx.
4267  if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
4268  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
4269 
4270  // If all elements are loads, use VLREP/VLEs (below).
4271  bool AllLoads = true;
4272  for (auto Elem : Elems)
4273  if (Elem.getOpcode() != ISD::LOAD || cast<LoadSDNode>(Elem)->isIndexed()) {
4274  AllLoads = false;
4275  break;
4276  }
4277 
4278  // The best way of building a v2i64 from two i64s is to use VLVGP.
4279  if (VT == MVT::v2i64 && !AllLoads)
4280  return joinDwords(DAG, DL, Elems[0], Elems[1]);
4281 
4282  // Use a 64-bit merge high to combine two doubles.
4283  if (VT == MVT::v2f64 && !AllLoads)
4284  return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4285 
4286  // Build v4f32 values directly from the FPRs:
4287  //
4288  // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
4289  // V V VMRHF
4290  // <ABxx> <CDxx>
4291  // V VMRHG
4292  // <ABCD>
4293  if (VT == MVT::v4f32 && !AllLoads) {
4294  SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4295  SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
4296  // Avoid unnecessary undefs by reusing the other operand.
4297  if (Op01.isUndef())
4298  Op01 = Op23;
4299  else if (Op23.isUndef())
4300  Op23 = Op01;
4301  // Merging identical replications is a no-op.
4302  if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
4303  return Op01;
4304  Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
4305  Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
4307  DL, MVT::v2i64, Op01, Op23);
4308  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4309  }
4310 
4311  // Collect the constant terms.
4313  SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
4314 
4315  unsigned NumConstants = 0;
4316  for (unsigned I = 0; I < NumElements; ++I) {
4317  SDValue Elem = Elems[I];
4318  if (Elem.getOpcode() == ISD::Constant ||
4319  Elem.getOpcode() == ISD::ConstantFP) {
4320  NumConstants += 1;
4321  Constants[I] = Elem;
4322  Done[I] = true;
4323  }
4324  }
4325  // If there was at least one constant, fill in the other elements of
4326  // Constants with undefs to get a full vector constant and use that
4327  // as the starting point.
4328  SDValue Result;
4329  if (NumConstants > 0) {
4330  for (unsigned I = 0; I < NumElements; ++I)
4331  if (!Constants[I].getNode())
4332  Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
4333  Result = DAG.getBuildVector(VT, DL, Constants);
4334  } else {
4335  // Otherwise try to use VLREP or VLVGP to start the sequence in order to
4336  // avoid a false dependency on any previous contents of the vector
4337  // register.
4338 
4339  // Use a VLREP if at least one element is a load.
4340  unsigned LoadElIdx = UINT_MAX;
4341  for (unsigned I = 0; I < NumElements; ++I)
4342  if (Elems[I].getOpcode() == ISD::LOAD &&
4343  cast<LoadSDNode>(Elems[I])->isUnindexed()) {
4344  LoadElIdx = I;
4345  break;
4346  }
4347  if (LoadElIdx != UINT_MAX) {
4348  Result = DAG.getNode(SystemZISD::REPLICATE, DL, VT, Elems[LoadElIdx]);
4349  Done[LoadElIdx] = true;
4350  } else {
4351  // Try to use VLVGP.
4352  unsigned I1 = NumElements / 2 - 1;
4353  unsigned I2 = NumElements - 1;
4354  bool Def1 = !Elems[I1].isUndef();
4355  bool Def2 = !Elems[I2].isUndef();
4356  if (Def1 || Def2) {
4357  SDValue Elem1 = Elems[Def1 ? I1 : I2];
4358  SDValue Elem2 = Elems[Def2 ? I2 : I1];
4359  Result = DAG.getNode(ISD::BITCAST, DL, VT,
4360  joinDwords(DAG, DL, Elem1, Elem2));
4361  Done[I1] = true;
4362  Done[I2] = true;
4363  } else
4364  Result = DAG.getUNDEF(VT);
4365  }
4366  }
4367 
4368  // Use VLVGx to insert the other elements.
4369  for (unsigned I = 0; I < NumElements; ++I)
4370  if (!Done[I] && !Elems[I].isUndef())
4371  Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4372  DAG.getConstant(I, DL, MVT::i32));
4373  return Result;
4374 }
4375 
4376 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4377  SelectionDAG &DAG) const {
4378  const SystemZInstrInfo *TII =
4379  static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4380  auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4381  SDLoc DL(Op);
4382  EVT VT = Op.getValueType();
4383 
4384  if (BVN->isConstant()) {
4385  // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4386  // preferred way of creating all-zero and all-one vectors so give it
4387  // priority over other methods below.
4388  uint64_t Mask = 0;
4389  if (tryBuildVectorByteMask(BVN, Mask)) {
4391  DAG.getConstant(Mask, DL, MVT::i32));
4392  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4393  }
4394 
4395  // Try using some form of replication.
4396  APInt SplatBits, SplatUndef;
4397  unsigned SplatBitSize;
4398  bool HasAnyUndefs;
4399  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4400  8, true) &&
4401  SplatBitSize <= 64) {
4402  // First try assuming that any undefined bits above the highest set bit
4403  // and below the lowest set bit are 1s. This increases the likelihood of
4404  // being able to use a sign-extended element value in VECTOR REPLICATE
4405  // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4406  uint64_t SplatBitsZ = SplatBits.getZExtValue();
4407  uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4408  uint64_t Lower = (SplatUndefZ
4409  & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4410  uint64_t Upper = (SplatUndefZ
4411  & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4412  uint64_t Value = SplatBitsZ | Upper | Lower;
4413  SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4414  SplatBitSize);
4415  if (Op.getNode())
4416  return Op;
4417 
4418  // Now try assuming that any undefined bits between the first and
4419  // last defined set bits are set. This increases the chances of
4420  // using a non-wraparound mask.
4421  uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4422  Value = SplatBitsZ | Middle;
4423  Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4424  if (Op.getNode())
4425  return Op;
4426  }
4427 
4428  // Fall back to loading it from memory.
4429  return SDValue();
4430  }
4431 
4432  // See if we should use shuffles to construct the vector from other vectors.
4433  if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
4434  return Res;
4435 
4436  // Detect SCALAR_TO_VECTOR conversions.
4438  return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4439 
4440  // Otherwise use buildVector to build the vector up from GPRs.
4441  unsigned NumElements = Op.getNumOperands();
4443  for (unsigned I = 0; I < NumElements; ++I)
4444  Ops[I] = Op.getOperand(I);
4445  return buildVector(DAG, DL, VT, Ops);
4446 }
4447 
4448 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4449  SelectionDAG &DAG) const {
4450  auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4451  SDLoc DL(Op);
4452  EVT VT = Op.getValueType();
4453  unsigned NumElements = VT.getVectorNumElements();
4454 
4455  if (VSN->isSplat()) {
4456  SDValue Op0 = Op.getOperand(0);
4457  unsigned Index = VSN->getSplatIndex();
4458  assert(Index < VT.getVectorNumElements() &&
4459  "Splat index should be defined and in first operand");
4460  // See whether the value we're splatting is directly available as a scalar.
4461  if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4462  Op0.getOpcode() == ISD::BUILD_VECTOR)
4463  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4464  // Otherwise keep it as a vector-to-vector operation.
4465  return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4466  DAG.getConstant(Index, DL, MVT::i32));
4467  }
4468 
4469  GeneralShuffle GS(VT);
4470  for (unsigned I = 0; I < NumElements; ++I) {
4471  int Elt = VSN->getMaskElt(I);
4472  if (Elt < 0)
4473  GS.addUndef();
4474  else if (!GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4475  unsigned(Elt) % NumElements))
4476  return SDValue();
4477  }
4478  return GS.getNode(DAG, SDLoc(VSN));
4479 }
4480 
4481 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4482  SelectionDAG &DAG) const {
4483  SDLoc DL(Op);
4484  // Just insert the scalar into element 0 of an undefined vector.
4485  return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4486  Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4487  Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4488 }
4489 
4490 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4491  SelectionDAG &DAG) const {
4492  // Handle insertions of floating-point values.
4493  SDLoc DL(Op);
4494  SDValue Op0 = Op.getOperand(0);
4495  SDValue Op1 = Op.getOperand(1);
4496  SDValue Op2 = Op.getOperand(2);
4497  EVT VT = Op.getValueType();
4498 
4499  // Insertions into constant indices of a v2f64 can be done using VPDI.
4500  // However, if the inserted value is a bitcast or a constant then it's
4501  // better to use GPRs, as below.
4502  if (VT == MVT::v2f64 &&
4503  Op1.getOpcode() != ISD::BITCAST &&
4504  Op1.getOpcode() != ISD::ConstantFP &&
4505  Op2.getOpcode() == ISD::Constant) {
4506  uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4507  unsigned Mask = VT.getVectorNumElements() - 1;
4508  if (Index <= Mask)
4509  return Op;
4510  }
4511 
4512  // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4514  MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4515  SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4516  DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4517  DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4518  return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4519 }
4520 
4521 SDValue
4522 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4523  SelectionDAG &DAG) const {
4524  // Handle extractions of floating-point values.
4525  SDLoc DL(Op);
4526  SDValue Op0 = Op.getOperand(0);
4527  SDValue Op1 = Op.getOperand(1);
4528  EVT VT = Op.getValueType();
4529  EVT VecVT = Op0.getValueType();
4530 
4531  // Extractions of constant indices can be done directly.
4532  if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4533  uint64_t Index = CIndexN->getZExtValue();
4534  unsigned Mask = VecVT.getVectorNumElements() - 1;
4535  if (Index <= Mask)
4536  return Op;
4537  }
4538 
4539  // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4540  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4541  MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4542  SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4543  DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4544  return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4545 }
4546 
4547 SDValue
4548 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4549  unsigned UnpackHigh) const {
4550  SDValue PackedOp = Op.getOperand(0);
4551  EVT OutVT = Op.getValueType();
4552  EVT InVT = PackedOp.getValueType();
4553  unsigned ToBits = OutVT.getScalarSizeInBits();
4554  unsigned FromBits = InVT.getScalarSizeInBits();
4555  do {
4556  FromBits *= 2;
4557  EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4558  SystemZ::VectorBits / FromBits);
4559  PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4560  } while (FromBits != ToBits);
4561  return PackedOp;
4562 }
4563 
4564 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4565  unsigned ByScalar) const {
4566  // Look for cases where a vector shift can use the *_BY_SCALAR form.
4567  SDValue Op0 = Op.getOperand(0);
4568  SDValue Op1 = Op.getOperand(1);
4569  SDLoc DL(Op);
4570  EVT VT = Op.getValueType();
4571  unsigned ElemBitSize = VT.getScalarSizeInBits();
4572 
4573  // See whether the shift vector is a splat represented as BUILD_VECTOR.
4574  if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4575  APInt SplatBits, SplatUndef;
4576  unsigned SplatBitSize;
4577  bool HasAnyUndefs;
4578  // Check for constant splats. Use ElemBitSize as the minimum element
4579  // width and reject splats that need wider elements.
4580  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4581  ElemBitSize, true) &&
4582  SplatBitSize == ElemBitSize) {
4583  SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4584  DL, MVT::i32);
4585  return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4586  }
4587  // Check for variable splats.
4588  BitVector UndefElements;
4589  SDValue Splat = BVN->getSplatValue(&UndefElements);
4590  if (Splat) {
4591  // Since i32 is the smallest legal type, we either need a no-op
4592  // or a truncation.
4593  SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4594  return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4595  }
4596  }
4597 
4598  // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4599  // and the shift amount is directly available in a GPR.
4600  if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4601  if (VSN->isSplat()) {
4602  SDValue VSNOp0 = VSN->getOperand(0);
4603  unsigned Index = VSN->getSplatIndex();
4604  assert(Index < VT.getVectorNumElements() &&
4605  "Splat index should be defined and in first operand");
4606  if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4607  VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4608  // Since i32 is the smallest legal type, we either need a no-op
4609  // or a truncation.
4610  SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4611  VSNOp0.getOperand(Index));
4612  return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4613  }
4614  }
4615  }
4616