LLVM  7.0.0svn
SystemZISelLowering.cpp
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1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
18 #include "SystemZTargetMachine.h"
23 #include "llvm/IR/Intrinsics.h"
24 #include "llvm/IR/IntrinsicInst.h"
26 #include "llvm/Support/KnownBits.h"
27 #include <cctype>
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "systemz-lower"
32 
33 namespace {
34 // Represents information about a comparison.
35 struct Comparison {
36  Comparison(SDValue Op0In, SDValue Op1In)
37  : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
38 
39  // The operands to the comparison.
40  SDValue Op0, Op1;
41 
42  // The opcode that should be used to compare Op0 and Op1.
43  unsigned Opcode;
44 
45  // A SystemZICMP value. Only used for integer comparisons.
46  unsigned ICmpType;
47 
48  // The mask of CC values that Opcode can produce.
49  unsigned CCValid;
50 
51  // The mask of CC values for which the original condition is true.
52  unsigned CCMask;
53 };
54 } // end anonymous namespace
55 
56 // Classify VT as either 32 or 64 bit.
57 static bool is32Bit(EVT VT) {
58  switch (VT.getSimpleVT().SimpleTy) {
59  case MVT::i32:
60  return true;
61  case MVT::i64:
62  return false;
63  default:
64  llvm_unreachable("Unsupported type");
65  }
66 }
67 
68 // Return a version of MachineOperand that can be safely used before the
69 // final use.
71  if (Op.isReg())
72  Op.setIsKill(false);
73  return Op;
74 }
75 
77  const SystemZSubtarget &STI)
78  : TargetLowering(TM), Subtarget(STI) {
79  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
80 
81  // Set up the register classes.
82  if (Subtarget.hasHighWord())
83  addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
84  else
85  addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
86  addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
87  if (Subtarget.hasVector()) {
88  addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
89  addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
90  } else {
91  addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
92  addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
93  }
94  if (Subtarget.hasVectorEnhancements1())
95  addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass);
96  else
97  addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
98 
99  if (Subtarget.hasVector()) {
100  addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
101  addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
102  addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
103  addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
104  addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
105  addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
106  }
107 
108  // Compute derived properties from the register classes
110 
111  // Set up special registers.
113 
114  // TODO: It may be better to default to latency-oriented scheduling, however
115  // LLVM's current latency-oriented scheduler can't handle physreg definitions
116  // such as SystemZ has with CC, so set this to the register-pressure
117  // scheduler, because it can.
119 
122 
123  // Instructions are strings of 2-byte aligned 2-byte values.
125  // For performance reasons we prefer 16-byte alignment.
127 
128  // Handle operations that are handled in a similar way for all types.
129  for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
131  ++I) {
132  MVT VT = MVT::SimpleValueType(I);
133  if (isTypeLegal(VT)) {
134  // Lower SET_CC into an IPM-based sequence.
136 
137  // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
139 
140  // Lower SELECT_CC and BR_CC into separate comparisons and branches.
143  }
144  }
145 
146  // Expand jump table branches as address arithmetic followed by an
147  // indirect jump.
149 
150  // Expand BRCOND into a BR_CC (see above).
152 
153  // Handle integer types.
154  for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
156  ++I) {
157  MVT VT = MVT::SimpleValueType(I);
158  if (isTypeLegal(VT)) {
159  // Expand individual DIV and REMs into DIVREMs.
166 
167  // Support addition/subtraction with overflow.
170 
171  // Support addition/subtraction with carry.
174 
175  // Support carry in as value rather than glue.
178 
179  // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
180  // stores, putting a serialization instruction after the stores.
183 
184  // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
185  // available, or if the operand is constant.
187 
188  // Use POPCNT on z196 and above.
189  if (Subtarget.hasPopulationCount())
191  else
193 
194  // No special instructions for these.
197 
198  // Use *MUL_LOHI where possible instead of MULH*.
203 
204  // Only z196 and above have native support for conversions to unsigned.
205  // On z10, promoting to i64 doesn't generate an inexact condition for
206  // values that are outside the i32 range but in the i64 range, so use
207  // the default expansion.
208  if (!Subtarget.hasFPExtension())
210  }
211  }
212 
213  // Type legalization will convert 8- and 16-bit atomic operations into
214  // forms that operate on i32s (but still keeping the original memory VT).
215  // Lower them into full i32 operations.
227 
228  // Even though i128 is not a legal type, we still need to custom lower
229  // the atomic operations in order to exploit SystemZ instructions.
232 
233  // We can use the CC result of compare-and-swap to implement
234  // the "success" result of ATOMIC_CMP_SWAP_WITH_SUCCESS.
238 
240 
241  // Traps are legal, as we will convert them to "j .+2".
243 
244  // z10 has instructions for signed but not unsigned FP conversion.
245  // Handle unsigned 32-bit types as signed 64-bit types.
246  if (!Subtarget.hasFPExtension()) {
249  }
250 
251  // We have native support for a 64-bit CTLZ, via FLOGR.
254 
255  // Give LowerOperation the chance to replace 64-bit ORs with subregs.
257 
258  // FIXME: Can we support these natively?
262 
263  // We have native instructions for i8, i16 and i32 extensions, but not i1.
265  for (MVT VT : MVT::integer_valuetypes()) {
269  }
270 
271  // Handle the various types of symbolic address.
277 
278  // We need to handle dynamic allocations specially because of the
279  // 160-byte area at the bottom of the stack.
282 
283  // Use custom expanders so that we can force the function to use
284  // a frame pointer.
287 
288  // Handle prefetches with PFD or PFDRL.
290 
291  for (MVT VT : MVT::vector_valuetypes()) {
292  // Assume by default that all vector operations need to be expanded.
293  for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
294  if (getOperationAction(Opcode, VT) == Legal)
295  setOperationAction(Opcode, VT, Expand);
296 
297  // Likewise all truncating stores and extending loads.
298  for (MVT InnerVT : MVT::vector_valuetypes()) {
299  setTruncStoreAction(VT, InnerVT, Expand);
300  setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
301  setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
302  setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
303  }
304 
305  if (isTypeLegal(VT)) {
306  // These operations are legal for anything that can be stored in a
307  // vector register, even if there is no native support for the format
308  // as such. In particular, we can do these for v4f32 even though there
309  // are no specific instructions for that format.
315 
316  // Likewise, except that we need to replace the nodes with something
317  // more specific.
320  }
321  }
322 
323  // Handle integer vector types.
324  for (MVT VT : MVT::integer_vector_valuetypes()) {
325  if (isTypeLegal(VT)) {
326  // These operations have direct equivalents.
331  if (VT != MVT::v2i64)
336  if (Subtarget.hasVectorEnhancements1())
338  else
342 
343  // Convert a GPR scalar to a vector by inserting it into element 0.
345 
346  // Use a series of unpacks for extensions.
349 
350  // Detect shifts by a scalar amount and convert them into
351  // V*_BY_SCALAR.
355 
356  // At present ROTL isn't matched by DAGCombiner. ROTR should be
357  // converted into ROTL.
360 
361  // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
362  // and inverting the result as necessary.
364  }
365  }
366 
367  if (Subtarget.hasVector()) {
368  // There should be no need to check for float types other than v2f64
369  // since <2 x f32> isn't a legal type.
378  }
379 
380  // Handle floating-point types.
381  for (unsigned I = MVT::FIRST_FP_VALUETYPE;
383  ++I) {
384  MVT VT = MVT::SimpleValueType(I);
385  if (isTypeLegal(VT)) {
386  // We can use FI for FRINT.
388 
389  // We can use the extended form of FI for other rounding operations.
390  if (Subtarget.hasFPExtension()) {
396  }
397 
398  // No special instructions for these.
404  }
405  }
406 
407  // Handle floating-point vector types.
408  if (Subtarget.hasVector()) {
409  // Scalar-to-vector conversion is just a subreg.
412 
413  // Some insertions and extractions can be done directly but others
414  // need to go via integers.
419 
420  // These operations have direct equivalents.
435  }
436 
437  // The vector enhancements facility 1 has instructions for these.
438  if (Subtarget.hasVectorEnhancements1()) {
453 
458 
463 
468 
473 
478  }
479 
480  // We have fused multiply-addition for f32 and f64 but not f128.
483  if (Subtarget.hasVectorEnhancements1())
485  else
487 
488  // We don't have a copysign instruction on vector registers.
489  if (Subtarget.hasVectorEnhancements1())
491 
492  // Needed so that we don't try to implement f128 constant loads using
493  // a load-and-extend of a f80 constant (in cases where the constant
494  // would fit in an f80).
495  for (MVT VT : MVT::fp_valuetypes())
497 
498  // We don't have extending load instruction on vector registers.
499  if (Subtarget.hasVectorEnhancements1()) {
502  }
503 
504  // Floating-point truncation and stores need to be done separately.
508 
509  // We have 64-bit FPR<->GPR moves, but need special handling for
510  // 32-bit forms.
511  if (!Subtarget.hasVector()) {
514  }
515 
516  // VASTART and VACOPY need to deal with the SystemZ-specific varargs
517  // structure, but VAEND is a no-op.
521 
522  // Codes for which we want to perform some z-specific combinations.
534 
535  // Handle intrinsics.
538 
539  // We want to use MVC in preference to even a single load/store pair.
540  MaxStoresPerMemcpy = 0;
542 
543  // The main memset sequence is a byte store followed by an MVC.
544  // Two STC or MV..I stores win over that, but the kind of fused stores
545  // generated by target-independent code don't when the byte value is
546  // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
547  // than "STC;MVC". Handle the choice in target-specific code instead.
548  MaxStoresPerMemset = 0;
550 }
551 
553  LLVMContext &, EVT VT) const {
554  if (!VT.isVector())
555  return MVT::i32;
557 }
558 
560  VT = VT.getScalarType();
561 
562  if (!VT.isSimple())
563  return false;
564 
565  switch (VT.getSimpleVT().SimpleTy) {
566  case MVT::f32:
567  case MVT::f64:
568  return true;
569  case MVT::f128:
570  return Subtarget.hasVectorEnhancements1();
571  default:
572  break;
573  }
574 
575  return false;
576 }
577 
578 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
579  // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
580  return Imm.isZero() || Imm.isNegZero();
581 }
582 
584  // We can use CGFI or CLGFI.
585  return isInt<32>(Imm) || isUInt<32>(Imm);
586 }
587 
589  // We can use ALGFI or SLGFI.
590  return isUInt<32>(Imm) || isUInt<32>(-Imm);
591 }
592 
594  unsigned,
595  unsigned,
596  bool *Fast) const {
597  // Unaligned accesses should never be slower than the expanded version.
598  // We check specifically for aligned accesses in the few cases where
599  // they are required.
600  if (Fast)
601  *Fast = true;
602  return true;
603 }
604 
605 // Information about the addressing mode for a memory access.
607  // True if a long displacement is supported.
609 
610  // True if use of index register is supported.
611  bool IndexReg;
612 
613  AddressingMode(bool LongDispl, bool IdxReg) :
614  LongDisplacement(LongDispl), IndexReg(IdxReg) {}
615 };
616 
617 // Return the desired addressing mode for a Load which has only one use (in
618 // the same block) which is a Store.
619 static AddressingMode getLoadStoreAddrMode(bool HasVector,
620  Type *Ty) {
621  // With vector support a Load->Store combination may be combined to either
622  // an MVC or vector operations and it seems to work best to allow the
623  // vector addressing mode.
624  if (HasVector)
625  return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
626 
627  // Otherwise only the MVC case is special.
628  bool MVC = Ty->isIntegerTy(8);
629  return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
630 }
631 
632 // Return the addressing mode which seems most desirable given an LLVM
633 // Instruction pointer.
634 static AddressingMode
636  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
637  switch (II->getIntrinsicID()) {
638  default: break;
639  case Intrinsic::memset:
640  case Intrinsic::memmove:
641  case Intrinsic::memcpy:
642  return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
643  }
644  }
645 
646  if (isa<LoadInst>(I) && I->hasOneUse()) {
647  auto *SingleUser = dyn_cast<Instruction>(*I->user_begin());
648  if (SingleUser->getParent() == I->getParent()) {
649  if (isa<ICmpInst>(SingleUser)) {
650  if (auto *C = dyn_cast<ConstantInt>(SingleUser->getOperand(1)))
651  if (C->getBitWidth() <= 64 &&
652  (isInt<16>(C->getSExtValue()) || isUInt<16>(C->getZExtValue())))
653  // Comparison of memory with 16 bit signed / unsigned immediate
654  return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
655  } else if (isa<StoreInst>(SingleUser))
656  // Load->Store
657  return getLoadStoreAddrMode(HasVector, I->getType());
658  }
659  } else if (auto *StoreI = dyn_cast<StoreInst>(I)) {
660  if (auto *LoadI = dyn_cast<LoadInst>(StoreI->getValueOperand()))
661  if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
662  // Load->Store
663  return getLoadStoreAddrMode(HasVector, LoadI->getType());
664  }
665 
666  if (HasVector && (isa<LoadInst>(I) || isa<StoreInst>(I))) {
667 
668  // * Use LDE instead of LE/LEY for z13 to avoid partial register
669  // dependencies (LDE only supports small offsets).
670  // * Utilize the vector registers to hold floating point
671  // values (vector load / store instructions only support small
672  // offsets).
673 
674  Type *MemAccessTy = (isa<LoadInst>(I) ? I->getType() :
675  I->getOperand(0)->getType());
676  bool IsFPAccess = MemAccessTy->isFloatingPointTy();
677  bool IsVectorAccess = MemAccessTy->isVectorTy();
678 
679  // A store of an extracted vector element will be combined into a VSTE type
680  // instruction.
681  if (!IsVectorAccess && isa<StoreInst>(I)) {
682  Value *DataOp = I->getOperand(0);
683  if (isa<ExtractElementInst>(DataOp))
684  IsVectorAccess = true;
685  }
686 
687  // A load which gets inserted into a vector element will be combined into a
688  // VLE type instruction.
689  if (!IsVectorAccess && isa<LoadInst>(I) && I->hasOneUse()) {
690  User *LoadUser = *I->user_begin();
691  if (isa<InsertElementInst>(LoadUser))
692  IsVectorAccess = true;
693  }
694 
695  if (IsFPAccess || IsVectorAccess)
696  return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
697  }
698 
699  return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
700 }
701 
703  const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
704  // Punt on globals for now, although they can be used in limited
705  // RELATIVE LONG cases.
706  if (AM.BaseGV)
707  return false;
708 
709  // Require a 20-bit signed offset.
710  if (!isInt<20>(AM.BaseOffs))
711  return false;
712 
713  AddressingMode SupportedAM(true, true);
714  if (I != nullptr)
715  SupportedAM = supportedAddressingMode(I, Subtarget.hasVector());
716 
717  if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))
718  return false;
719 
720  if (!SupportedAM.IndexReg)
721  // No indexing allowed.
722  return AM.Scale == 0;
723  else
724  // Indexing is OK but no scale factor can be applied.
725  return AM.Scale == 0 || AM.Scale == 1;
726 }
727 
729  if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
730  return false;
731  unsigned FromBits = FromType->getPrimitiveSizeInBits();
732  unsigned ToBits = ToType->getPrimitiveSizeInBits();
733  return FromBits > ToBits;
734 }
735 
737  if (!FromVT.isInteger() || !ToVT.isInteger())
738  return false;
739  unsigned FromBits = FromVT.getSizeInBits();
740  unsigned ToBits = ToVT.getSizeInBits();
741  return FromBits > ToBits;
742 }
743 
744 //===----------------------------------------------------------------------===//
745 // Inline asm support
746 //===----------------------------------------------------------------------===//
747 
750  if (Constraint.size() == 1) {
751  switch (Constraint[0]) {
752  case 'a': // Address register
753  case 'd': // Data register (equivalent to 'r')
754  case 'f': // Floating-point register
755  case 'h': // High-part register
756  case 'r': // General-purpose register
757  case 'v': // Vector register
758  return C_RegisterClass;
759 
760  case 'Q': // Memory with base and unsigned 12-bit displacement
761  case 'R': // Likewise, plus an index
762  case 'S': // Memory with base and signed 20-bit displacement
763  case 'T': // Likewise, plus an index
764  case 'm': // Equivalent to 'T'.
765  return C_Memory;
766 
767  case 'I': // Unsigned 8-bit constant
768  case 'J': // Unsigned 12-bit constant
769  case 'K': // Signed 16-bit constant
770  case 'L': // Signed 20-bit displacement (on all targets we support)
771  case 'M': // 0x7fffffff
772  return C_Other;
773 
774  default:
775  break;
776  }
777  }
778  return TargetLowering::getConstraintType(Constraint);
779 }
780 
783  const char *constraint) const {
784  ConstraintWeight weight = CW_Invalid;
785  Value *CallOperandVal = info.CallOperandVal;
786  // If we don't have a value, we can't do a match,
787  // but allow it at the lowest weight.
788  if (!CallOperandVal)
789  return CW_Default;
790  Type *type = CallOperandVal->getType();
791  // Look at the constraint type.
792  switch (*constraint) {
793  default:
794  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
795  break;
796 
797  case 'a': // Address register
798  case 'd': // Data register (equivalent to 'r')
799  case 'h': // High-part register
800  case 'r': // General-purpose register
801  if (CallOperandVal->getType()->isIntegerTy())
802  weight = CW_Register;
803  break;
804 
805  case 'f': // Floating-point register
806  if (type->isFloatingPointTy())
807  weight = CW_Register;
808  break;
809 
810  case 'v': // Vector register
811  if ((type->isVectorTy() || type->isFloatingPointTy()) &&
812  Subtarget.hasVector())
813  weight = CW_Register;
814  break;
815 
816  case 'I': // Unsigned 8-bit constant
817  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
818  if (isUInt<8>(C->getZExtValue()))
819  weight = CW_Constant;
820  break;
821 
822  case 'J': // Unsigned 12-bit constant
823  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
824  if (isUInt<12>(C->getZExtValue()))
825  weight = CW_Constant;
826  break;
827 
828  case 'K': // Signed 16-bit constant
829  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
830  if (isInt<16>(C->getSExtValue()))
831  weight = CW_Constant;
832  break;
833 
834  case 'L': // Signed 20-bit displacement (on all targets we support)
835  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
836  if (isInt<20>(C->getSExtValue()))
837  weight = CW_Constant;
838  break;
839 
840  case 'M': // 0x7fffffff
841  if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
842  if (C->getZExtValue() == 0x7fffffff)
843  weight = CW_Constant;
844  break;
845  }
846  return weight;
847 }
848 
849 // Parse a "{tNNN}" register constraint for which the register type "t"
850 // has already been verified. MC is the class associated with "t" and
851 // Map maps 0-based register numbers to LLVM register numbers.
852 static std::pair<unsigned, const TargetRegisterClass *>
854  const unsigned *Map, unsigned Size) {
855  assert(*(Constraint.end()-1) == '}' && "Missing '}'");
856  if (isdigit(Constraint[2])) {
857  unsigned Index;
858  bool Failed =
859  Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
860  if (!Failed && Index < Size && Map[Index])
861  return std::make_pair(Map[Index], RC);
862  }
863  return std::make_pair(0U, nullptr);
864 }
865 
866 std::pair<unsigned, const TargetRegisterClass *>
868  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
869  if (Constraint.size() == 1) {
870  // GCC Constraint Letters
871  switch (Constraint[0]) {
872  default: break;
873  case 'd': // Data register (equivalent to 'r')
874  case 'r': // General-purpose register
875  if (VT == MVT::i64)
876  return std::make_pair(0U, &SystemZ::GR64BitRegClass);
877  else if (VT == MVT::i128)
878  return std::make_pair(0U, &SystemZ::GR128BitRegClass);
879  return std::make_pair(0U, &SystemZ::GR32BitRegClass);
880 
881  case 'a': // Address register
882  if (VT == MVT::i64)
883  return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
884  else if (VT == MVT::i128)
885  return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
886  return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
887 
888  case 'h': // High-part register (an LLVM extension)
889  return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
890 
891  case 'f': // Floating-point register
892  if (VT == MVT::f64)
893  return std::make_pair(0U, &SystemZ::FP64BitRegClass);
894  else if (VT == MVT::f128)
895  return std::make_pair(0U, &SystemZ::FP128BitRegClass);
896  return std::make_pair(0U, &SystemZ::FP32BitRegClass);
897 
898  case 'v': // Vector register
899  if (Subtarget.hasVector()) {
900  if (VT == MVT::f32)
901  return std::make_pair(0U, &SystemZ::VR32BitRegClass);
902  if (VT == MVT::f64)
903  return std::make_pair(0U, &SystemZ::VR64BitRegClass);
904  return std::make_pair(0U, &SystemZ::VR128BitRegClass);
905  }
906  break;
907  }
908  }
909  if (Constraint.size() > 0 && Constraint[0] == '{') {
910  // We need to override the default register parsing for GPRs and FPRs
911  // because the interpretation depends on VT. The internal names of
912  // the registers are also different from the external names
913  // (F0D and F0S instead of F0, etc.).
914  if (Constraint[1] == 'r') {
915  if (VT == MVT::i32)
916  return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
917  SystemZMC::GR32Regs, 16);
918  if (VT == MVT::i128)
919  return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
921  return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
922  SystemZMC::GR64Regs, 16);
923  }
924  if (Constraint[1] == 'f') {
925  if (VT == MVT::f32)
926  return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
927  SystemZMC::FP32Regs, 16);
928  if (VT == MVT::f128)
929  return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
931  return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
932  SystemZMC::FP64Regs, 16);
933  }
934  if (Constraint[1] == 'v') {
935  if (VT == MVT::f32)
936  return parseRegisterNumber(Constraint, &SystemZ::VR32BitRegClass,
937  SystemZMC::VR32Regs, 32);
938  if (VT == MVT::f64)
939  return parseRegisterNumber(Constraint, &SystemZ::VR64BitRegClass,
940  SystemZMC::VR64Regs, 32);
941  return parseRegisterNumber(Constraint, &SystemZ::VR128BitRegClass,
943  }
944  }
945  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
946 }
947 
949 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
950  std::vector<SDValue> &Ops,
951  SelectionDAG &DAG) const {
952  // Only support length 1 constraints for now.
953  if (Constraint.length() == 1) {
954  switch (Constraint[0]) {
955  case 'I': // Unsigned 8-bit constant
956  if (auto *C = dyn_cast<ConstantSDNode>(Op))
957  if (isUInt<8>(C->getZExtValue()))
958  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
959  Op.getValueType()));
960  return;
961 
962  case 'J': // Unsigned 12-bit constant
963  if (auto *C = dyn_cast<ConstantSDNode>(Op))
964  if (isUInt<12>(C->getZExtValue()))
965  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
966  Op.getValueType()));
967  return;
968 
969  case 'K': // Signed 16-bit constant
970  if (auto *C = dyn_cast<ConstantSDNode>(Op))
971  if (isInt<16>(C->getSExtValue()))
972  Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
973  Op.getValueType()));
974  return;
975 
976  case 'L': // Signed 20-bit displacement (on all targets we support)
977  if (auto *C = dyn_cast<ConstantSDNode>(Op))
978  if (isInt<20>(C->getSExtValue()))
979  Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
980  Op.getValueType()));
981  return;
982 
983  case 'M': // 0x7fffffff
984  if (auto *C = dyn_cast<ConstantSDNode>(Op))
985  if (C->getZExtValue() == 0x7fffffff)
986  Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
987  Op.getValueType()));
988  return;
989  }
990  }
991  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
992 }
993 
994 //===----------------------------------------------------------------------===//
995 // Calling conventions
996 //===----------------------------------------------------------------------===//
997 
998 #include "SystemZGenCallingConv.inc"
999 
1001  CallingConv::ID) const {
1002  static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
1003  SystemZ::R14D, 0 };
1004  return ScratchRegs;
1005 }
1006 
1008  Type *ToType) const {
1009  return isTruncateFree(FromType, ToType);
1010 }
1011 
1013  return CI->isTailCall();
1014 }
1015 
1016 // We do not yet support 128-bit single-element vector types. If the user
1017 // attempts to use such types as function argument or return type, prefer
1018 // to error out instead of emitting code violating the ABI.
1019 static void VerifyVectorType(MVT VT, EVT ArgVT) {
1020  if (ArgVT.isVector() && !VT.isVector())
1021  report_fatal_error("Unsupported vector argument or return type");
1022 }
1023 
1025  for (unsigned i = 0; i < Ins.size(); ++i)
1026  VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
1027 }
1028 
1030  for (unsigned i = 0; i < Outs.size(); ++i)
1031  VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
1032 }
1033 
1034 // Value is a value that has been passed to us in the location described by VA
1035 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
1036 // any loads onto Chain.
1038  CCValAssign &VA, SDValue Chain,
1039  SDValue Value) {
1040  // If the argument has been promoted from a smaller type, insert an
1041  // assertion to capture this.
1042  if (VA.getLocInfo() == CCValAssign::SExt)
1043  Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
1044  DAG.getValueType(VA.getValVT()));
1045  else if (VA.getLocInfo() == CCValAssign::ZExt)
1046  Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
1047  DAG.getValueType(VA.getValVT()));
1048 
1049  if (VA.isExtInLoc())
1050  Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
1051  else if (VA.getLocInfo() == CCValAssign::BCvt) {
1052  // If this is a short vector argument loaded from the stack,
1053  // extend from i64 to full vector size and then bitcast.
1054  assert(VA.getLocVT() == MVT::i64);
1055  assert(VA.getValVT().isVector());
1056  Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
1057  Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
1058  } else
1059  assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
1060  return Value;
1061 }
1062 
1063 // Value is a value of type VA.getValVT() that we need to copy into
1064 // the location described by VA. Return a copy of Value converted to
1065 // VA.getValVT(). The caller is responsible for handling indirect values.
1067  CCValAssign &VA, SDValue Value) {
1068  switch (VA.getLocInfo()) {
1069  case CCValAssign::SExt:
1070  return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
1071  case CCValAssign::ZExt:
1072  return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
1073  case CCValAssign::AExt:
1074  return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
1075  case CCValAssign::BCvt:
1076  // If this is a short vector argument to be stored to the stack,
1077  // bitcast to v2i64 and then extract first element.
1078  assert(VA.getLocVT() == MVT::i64);
1079  assert(VA.getValVT().isVector());
1080  Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
1081  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
1082  DAG.getConstant(0, DL, MVT::i32));
1083  case CCValAssign::Full:
1084  return Value;
1085  default:
1086  llvm_unreachable("Unhandled getLocInfo()");
1087  }
1088 }
1089 
1091  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1092  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1093  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1094  MachineFunction &MF = DAG.getMachineFunction();
1095  MachineFrameInfo &MFI = MF.getFrameInfo();
1097  SystemZMachineFunctionInfo *FuncInfo =
1099  auto *TFL =
1100  static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
1101  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1102 
1103  // Detect unsupported vector argument types.
1104  if (Subtarget.hasVector())
1105  VerifyVectorTypes(Ins);
1106 
1107  // Assign locations to all of the incoming arguments.
1109  SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1110  CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
1111 
1112  unsigned NumFixedGPRs = 0;
1113  unsigned NumFixedFPRs = 0;
1114  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1115  SDValue ArgValue;
1116  CCValAssign &VA = ArgLocs[I];
1117  EVT LocVT = VA.getLocVT();
1118  if (VA.isRegLoc()) {
1119  // Arguments passed in registers
1120  const TargetRegisterClass *RC;
1121  switch (LocVT.getSimpleVT().SimpleTy) {
1122  default:
1123  // Integers smaller than i64 should be promoted to i64.
1124  llvm_unreachable("Unexpected argument type");
1125  case MVT::i32:
1126  NumFixedGPRs += 1;
1127  RC = &SystemZ::GR32BitRegClass;
1128  break;
1129  case MVT::i64:
1130  NumFixedGPRs += 1;
1131  RC = &SystemZ::GR64BitRegClass;
1132  break;
1133  case MVT::f32:
1134  NumFixedFPRs += 1;
1135  RC = &SystemZ::FP32BitRegClass;
1136  break;
1137  case MVT::f64:
1138  NumFixedFPRs += 1;
1139  RC = &SystemZ::FP64BitRegClass;
1140  break;
1141  case MVT::v16i8:
1142  case MVT::v8i16:
1143  case MVT::v4i32:
1144  case MVT::v2i64:
1145  case MVT::v4f32:
1146  case MVT::v2f64:
1147  RC = &SystemZ::VR128BitRegClass;
1148  break;
1149  }
1150 
1151  unsigned VReg = MRI.createVirtualRegister(RC);
1152  MRI.addLiveIn(VA.getLocReg(), VReg);
1153  ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1154  } else {
1155  assert(VA.isMemLoc() && "Argument not register or memory");
1156 
1157  // Create the frame index object for this incoming parameter.
1158  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1159  VA.getLocMemOffset(), true);
1160 
1161  // Create the SelectionDAG nodes corresponding to a load
1162  // from this parameter. Unpromoted ints and floats are
1163  // passed as right-justified 8-byte values.
1164  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1165  if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1166  FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
1167  DAG.getIntPtrConstant(4, DL));
1168  ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
1170  }
1171 
1172  // Convert the value of the argument register into the value that's
1173  // being passed.
1174  if (VA.getLocInfo() == CCValAssign::Indirect) {
1175  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1176  MachinePointerInfo()));
1177  // If the original argument was split (e.g. i128), we need
1178  // to load all parts of it here (using the same address).
1179  unsigned ArgIndex = Ins[I].OrigArgIndex;
1180  assert (Ins[I].PartOffset == 0);
1181  while (I + 1 != E && Ins[I + 1].OrigArgIndex == ArgIndex) {
1182  CCValAssign &PartVA = ArgLocs[I + 1];
1183  unsigned PartOffset = Ins[I + 1].PartOffset;
1184  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1185  DAG.getIntPtrConstant(PartOffset, DL));
1186  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1187  MachinePointerInfo()));
1188  ++I;
1189  }
1190  } else
1191  InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
1192  }
1193 
1194  if (IsVarArg) {
1195  // Save the number of non-varargs registers for later use by va_start, etc.
1196  FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
1197  FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
1198 
1199  // Likewise the address (in the form of a frame index) of where the
1200  // first stack vararg would be. The 1-byte size here is arbitrary.
1201  int64_t StackSize = CCInfo.getNextStackOffset();
1202  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
1203 
1204  // ...and a similar frame index for the caller-allocated save area
1205  // that will be used to store the incoming registers.
1206  int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
1207  unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
1208  FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
1209 
1210  // Store the FPR varargs in the reserved frame slots. (We store the
1211  // GPRs as part of the prologue.)
1212  if (NumFixedFPRs < SystemZ::NumArgFPRs) {
1213  SDValue MemOps[SystemZ::NumArgFPRs];
1214  for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
1215  unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
1216  int FI = MFI.CreateFixedObject(8, RegSaveOffset + Offset, true);
1217  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1218  unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
1219  &SystemZ::FP64BitRegClass);
1220  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
1221  MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
1223  }
1224  // Join the stores, which are independent of one another.
1225  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1226  makeArrayRef(&MemOps[NumFixedFPRs],
1227  SystemZ::NumArgFPRs-NumFixedFPRs));
1228  }
1229  }
1230 
1231  return Chain;
1232 }
1233 
1234 static bool canUseSiblingCall(const CCState &ArgCCInfo,
1237  // Punt if there are any indirect or stack arguments, or if the call
1238  // needs the callee-saved argument register R6, or if the call uses
1239  // the callee-saved register arguments SwiftSelf and SwiftError.
1240  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1241  CCValAssign &VA = ArgLocs[I];
1242  if (VA.getLocInfo() == CCValAssign::Indirect)
1243  return false;
1244  if (!VA.isRegLoc())
1245  return false;
1246  unsigned Reg = VA.getLocReg();
1247  if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1248  return false;
1249  if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1250  return false;
1251  }
1252  return true;
1253 }
1254 
1255 SDValue
1257  SmallVectorImpl<SDValue> &InVals) const {
1258  SelectionDAG &DAG = CLI.DAG;
1259  SDLoc &DL = CLI.DL;
1261  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1263  SDValue Chain = CLI.Chain;
1264  SDValue Callee = CLI.Callee;
1265  bool &IsTailCall = CLI.IsTailCall;
1266  CallingConv::ID CallConv = CLI.CallConv;
1267  bool IsVarArg = CLI.IsVarArg;
1268  MachineFunction &MF = DAG.getMachineFunction();
1269  EVT PtrVT = getPointerTy(MF.getDataLayout());
1270 
1271  // Detect unsupported vector argument and return types.
1272  if (Subtarget.hasVector()) {
1273  VerifyVectorTypes(Outs);
1274  VerifyVectorTypes(Ins);
1275  }
1276 
1277  // Analyze the operands of the call, assigning locations to each operand.
1279  SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1280  ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1281 
1282  // We don't support GuaranteedTailCallOpt, only automatically-detected
1283  // sibling calls.
1284  if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
1285  IsTailCall = false;
1286 
1287  // Get a count of how many bytes are to be pushed on the stack.
1288  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1289 
1290  // Mark the start of the call.
1291  if (!IsTailCall)
1292  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1293 
1294  // Copy argument values to their designated locations.
1296  SmallVector<SDValue, 8> MemOpChains;
1297  SDValue StackPtr;
1298  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1299  CCValAssign &VA = ArgLocs[I];
1300  SDValue ArgValue = OutVals[I];
1301 
1302  if (VA.getLocInfo() == CCValAssign::Indirect) {
1303  // Store the argument in a stack slot and pass its address.
1304  SDValue SpillSlot = DAG.CreateStackTemporary(Outs[I].ArgVT);
1305  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1306  MemOpChains.push_back(
1307  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1309  // If the original argument was split (e.g. i128), we need
1310  // to store all parts of it here (and pass just one address).
1311  unsigned ArgIndex = Outs[I].OrigArgIndex;
1312  assert (Outs[I].PartOffset == 0);
1313  while (I + 1 != E && Outs[I + 1].OrigArgIndex == ArgIndex) {
1314  SDValue PartValue = OutVals[I + 1];
1315  unsigned PartOffset = Outs[I + 1].PartOffset;
1316  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1317  DAG.getIntPtrConstant(PartOffset, DL));
1318  MemOpChains.push_back(
1319  DAG.getStore(Chain, DL, PartValue, Address,
1321  ++I;
1322  }
1323  ArgValue = SpillSlot;
1324  } else
1325  ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1326 
1327  if (VA.isRegLoc())
1328  // Queue up the argument copies and emit them at the end.
1329  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1330  else {
1331  assert(VA.isMemLoc() && "Argument not register or memory");
1332 
1333  // Work out the address of the stack slot. Unpromoted ints and
1334  // floats are passed as right-justified 8-byte values.
1335  if (!StackPtr.getNode())
1336  StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1338  if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1339  Offset += 4;
1340  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1341  DAG.getIntPtrConstant(Offset, DL));
1342 
1343  // Emit the store.
1344  MemOpChains.push_back(
1345  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1346  }
1347  }
1348 
1349  // Join the stores, which are independent of one another.
1350  if (!MemOpChains.empty())
1351  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1352 
1353  // Accept direct calls by converting symbolic call addresses to the
1354  // associated Target* opcodes. Force %r1 to be used for indirect
1355  // tail calls.
1356  SDValue Glue;
1357  if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1358  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1359  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1360  } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1361  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1362  Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1363  } else if (IsTailCall) {
1364  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1365  Glue = Chain.getValue(1);
1366  Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1367  }
1368 
1369  // Build a sequence of copy-to-reg nodes, chained and glued together.
1370  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1371  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1372  RegsToPass[I].second, Glue);
1373  Glue = Chain.getValue(1);
1374  }
1375 
1376  // The first call operand is the chain and the second is the target address.
1378  Ops.push_back(Chain);
1379  Ops.push_back(Callee);
1380 
1381  // Add argument registers to the end of the list so that they are
1382  // known live into the call.
1383  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1384  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1385  RegsToPass[I].second.getValueType()));
1386 
1387  // Add a register mask operand representing the call-preserved registers.
1388  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1389  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1390  assert(Mask && "Missing call preserved mask for calling convention");
1391  Ops.push_back(DAG.getRegisterMask(Mask));
1392 
1393  // Glue the call to the argument copies, if any.
1394  if (Glue.getNode())
1395  Ops.push_back(Glue);
1396 
1397  // Emit the call.
1398  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1399  if (IsTailCall)
1400  return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1401  Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1402  Glue = Chain.getValue(1);
1403 
1404  // Mark the end of the call, which is glued to the call itself.
1405  Chain = DAG.getCALLSEQ_END(Chain,
1406  DAG.getConstant(NumBytes, DL, PtrVT, true),
1407  DAG.getConstant(0, DL, PtrVT, true),
1408  Glue, DL);
1409  Glue = Chain.getValue(1);
1410 
1411  // Assign locations to each value returned by this call.
1413  CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1414  RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1415 
1416  // Copy all of the result registers out of their specified physreg.
1417  for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1418  CCValAssign &VA = RetLocs[I];
1419 
1420  // Copy the value out, gluing the copy to the end of the call sequence.
1421  SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1422  VA.getLocVT(), Glue);
1423  Chain = RetValue.getValue(1);
1424  Glue = RetValue.getValue(2);
1425 
1426  // Convert the value of the return register into the value that's
1427  // being returned.
1428  InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1429  }
1430 
1431  return Chain;
1432 }
1433 
1436  MachineFunction &MF, bool isVarArg,
1437  const SmallVectorImpl<ISD::OutputArg> &Outs,
1438  LLVMContext &Context) const {
1439  // Detect unsupported vector return types.
1440  if (Subtarget.hasVector())
1441  VerifyVectorTypes(Outs);
1442 
1443  // Special case that we cannot easily detect in RetCC_SystemZ since
1444  // i128 is not a legal type.
1445  for (auto &Out : Outs)
1446  if (Out.ArgVT == MVT::i128)
1447  return false;
1448 
1450  CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1451  return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1452 }
1453 
1454 SDValue
1456  bool IsVarArg,
1457  const SmallVectorImpl<ISD::OutputArg> &Outs,
1458  const SmallVectorImpl<SDValue> &OutVals,
1459  const SDLoc &DL, SelectionDAG &DAG) const {
1460  MachineFunction &MF = DAG.getMachineFunction();
1461 
1462  // Detect unsupported vector return types.
1463  if (Subtarget.hasVector())
1464  VerifyVectorTypes(Outs);
1465 
1466  // Assign locations to each returned value.
1468  CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1469  RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1470 
1471  // Quick exit for void returns
1472  if (RetLocs.empty())
1473  return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1474 
1475  // Copy the result values into the output registers.
1476  SDValue Glue;
1477  SmallVector<SDValue, 4> RetOps;
1478  RetOps.push_back(Chain);
1479  for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1480  CCValAssign &VA = RetLocs[I];
1481  SDValue RetValue = OutVals[I];
1482 
1483  // Make the return register live on exit.
1484  assert(VA.isRegLoc() && "Can only return in registers!");
1485 
1486  // Promote the value as required.
1487  RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1488 
1489  // Chain and glue the copies together.
1490  unsigned Reg = VA.getLocReg();
1491  Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1492  Glue = Chain.getValue(1);
1493  RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1494  }
1495 
1496  // Update chain and glue.
1497  RetOps[0] = Chain;
1498  if (Glue.getNode())
1499  RetOps.push_back(Glue);
1500 
1501  return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1502 }
1503 
1504 // Return true if Op is an intrinsic node with chain that returns the CC value
1505 // as its only (other) argument. Provide the associated SystemZISD opcode and
1506 // the mask of valid CC values if so.
1507 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1508  unsigned &CCValid) {
1509  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1510  switch (Id) {
1511  case Intrinsic::s390_tbegin:
1512  Opcode = SystemZISD::TBEGIN;
1513  CCValid = SystemZ::CCMASK_TBEGIN;
1514  return true;
1515 
1516  case Intrinsic::s390_tbegin_nofloat:
1517  Opcode = SystemZISD::TBEGIN_NOFLOAT;
1518  CCValid = SystemZ::CCMASK_TBEGIN;
1519  return true;
1520 
1521  case Intrinsic::s390_tend:
1522  Opcode = SystemZISD::TEND;
1523  CCValid = SystemZ::CCMASK_TEND;
1524  return true;
1525 
1526  default:
1527  return false;
1528  }
1529 }
1530 
1531 // Return true if Op is an intrinsic node without chain that returns the
1532 // CC value as its final argument. Provide the associated SystemZISD
1533 // opcode and the mask of valid CC values if so.
1534 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1535  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1536  switch (Id) {
1537  case Intrinsic::s390_vpkshs:
1538  case Intrinsic::s390_vpksfs:
1539  case Intrinsic::s390_vpksgs:
1540  Opcode = SystemZISD::PACKS_CC;
1541  CCValid = SystemZ::CCMASK_VCMP;
1542  return true;
1543 
1544  case Intrinsic::s390_vpklshs:
1545  case Intrinsic::s390_vpklsfs:
1546  case Intrinsic::s390_vpklsgs:
1547  Opcode = SystemZISD::PACKLS_CC;
1548  CCValid = SystemZ::CCMASK_VCMP;
1549  return true;
1550 
1551  case Intrinsic::s390_vceqbs:
1552  case Intrinsic::s390_vceqhs:
1553  case Intrinsic::s390_vceqfs:
1554  case Intrinsic::s390_vceqgs:
1555  Opcode = SystemZISD::VICMPES;
1556  CCValid = SystemZ::CCMASK_VCMP;
1557  return true;
1558 
1559  case Intrinsic::s390_vchbs:
1560  case Intrinsic::s390_vchhs:
1561  case Intrinsic::s390_vchfs:
1562  case Intrinsic::s390_vchgs:
1563  Opcode = SystemZISD::VICMPHS;
1564  CCValid = SystemZ::CCMASK_VCMP;
1565  return true;
1566 
1567  case Intrinsic::s390_vchlbs:
1568  case Intrinsic::s390_vchlhs:
1569  case Intrinsic::s390_vchlfs:
1570  case Intrinsic::s390_vchlgs:
1571  Opcode = SystemZISD::VICMPHLS;
1572  CCValid = SystemZ::CCMASK_VCMP;
1573  return true;
1574 
1575  case Intrinsic::s390_vtm:
1576  Opcode = SystemZISD::VTM;
1577  CCValid = SystemZ::CCMASK_VCMP;
1578  return true;
1579 
1580  case Intrinsic::s390_vfaebs:
1581  case Intrinsic::s390_vfaehs:
1582  case Intrinsic::s390_vfaefs:
1583  Opcode = SystemZISD::VFAE_CC;
1584  CCValid = SystemZ::CCMASK_ANY;
1585  return true;
1586 
1587  case Intrinsic::s390_vfaezbs:
1588  case Intrinsic::s390_vfaezhs:
1589  case Intrinsic::s390_vfaezfs:
1590  Opcode = SystemZISD::VFAEZ_CC;
1591  CCValid = SystemZ::CCMASK_ANY;
1592  return true;
1593 
1594  case Intrinsic::s390_vfeebs:
1595  case Intrinsic::s390_vfeehs:
1596  case Intrinsic::s390_vfeefs:
1597  Opcode = SystemZISD::VFEE_CC;
1598  CCValid = SystemZ::CCMASK_ANY;
1599  return true;
1600 
1601  case Intrinsic::s390_vfeezbs:
1602  case Intrinsic::s390_vfeezhs:
1603  case Intrinsic::s390_vfeezfs:
1604  Opcode = SystemZISD::VFEEZ_CC;
1605  CCValid = SystemZ::CCMASK_ANY;
1606  return true;
1607 
1608  case Intrinsic::s390_vfenebs:
1609  case Intrinsic::s390_vfenehs:
1610  case Intrinsic::s390_vfenefs:
1611  Opcode = SystemZISD::VFENE_CC;
1612  CCValid = SystemZ::CCMASK_ANY;
1613  return true;
1614 
1615  case Intrinsic::s390_vfenezbs:
1616  case Intrinsic::s390_vfenezhs:
1617  case Intrinsic::s390_vfenezfs:
1618  Opcode = SystemZISD::VFENEZ_CC;
1619  CCValid = SystemZ::CCMASK_ANY;
1620  return true;
1621 
1622  case Intrinsic::s390_vistrbs:
1623  case Intrinsic::s390_vistrhs:
1624  case Intrinsic::s390_vistrfs:
1625  Opcode = SystemZISD::VISTR_CC;
1627  return true;
1628 
1629  case Intrinsic::s390_vstrcbs:
1630  case Intrinsic::s390_vstrchs:
1631  case Intrinsic::s390_vstrcfs:
1632  Opcode = SystemZISD::VSTRC_CC;
1633  CCValid = SystemZ::CCMASK_ANY;
1634  return true;
1635 
1636  case Intrinsic::s390_vstrczbs:
1637  case Intrinsic::s390_vstrczhs:
1638  case Intrinsic::s390_vstrczfs:
1639  Opcode = SystemZISD::VSTRCZ_CC;
1640  CCValid = SystemZ::CCMASK_ANY;
1641  return true;
1642 
1643  case Intrinsic::s390_vfcedbs:
1644  case Intrinsic::s390_vfcesbs:
1645  Opcode = SystemZISD::VFCMPES;
1646  CCValid = SystemZ::CCMASK_VCMP;
1647  return true;
1648 
1649  case Intrinsic::s390_vfchdbs:
1650  case Intrinsic::s390_vfchsbs:
1651  Opcode = SystemZISD::VFCMPHS;
1652  CCValid = SystemZ::CCMASK_VCMP;
1653  return true;
1654 
1655  case Intrinsic::s390_vfchedbs:
1656  case Intrinsic::s390_vfchesbs:
1657  Opcode = SystemZISD::VFCMPHES;
1658  CCValid = SystemZ::CCMASK_VCMP;
1659  return true;
1660 
1661  case Intrinsic::s390_vftcidb:
1662  case Intrinsic::s390_vftcisb:
1663  Opcode = SystemZISD::VFTCI;
1664  CCValid = SystemZ::CCMASK_VCMP;
1665  return true;
1666 
1667  case Intrinsic::s390_tdc:
1668  Opcode = SystemZISD::TDC;
1669  CCValid = SystemZ::CCMASK_TDC;
1670  return true;
1671 
1672  default:
1673  return false;
1674  }
1675 }
1676 
1677 // Emit an intrinsic with chain and an explicit CC register result.
1679  unsigned Opcode) {
1680  // Copy all operands except the intrinsic ID.
1681  unsigned NumOps = Op.getNumOperands();
1683  Ops.reserve(NumOps - 1);
1684  Ops.push_back(Op.getOperand(0));
1685  for (unsigned I = 2; I < NumOps; ++I)
1686  Ops.push_back(Op.getOperand(I));
1687 
1688  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1689  SDVTList RawVTs = DAG.getVTList(MVT::i32, MVT::Other);
1690  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1691  SDValue OldChain = SDValue(Op.getNode(), 1);
1692  SDValue NewChain = SDValue(Intr.getNode(), 1);
1693  DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1694  return Intr.getNode();
1695 }
1696 
1697 // Emit an intrinsic with an explicit CC register result.
1699  unsigned Opcode) {
1700  // Copy all operands except the intrinsic ID.
1701  unsigned NumOps = Op.getNumOperands();
1703  Ops.reserve(NumOps - 1);
1704  for (unsigned I = 1; I < NumOps; ++I)
1705  Ops.push_back(Op.getOperand(I));
1706 
1707  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), Op->getVTList(), Ops);
1708  return Intr.getNode();
1709 }
1710 
1711 // CC is a comparison that will be implemented using an integer or
1712 // floating-point comparison. Return the condition code mask for
1713 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1714 // unsigned comparisons and clear for signed ones. In the floating-point
1715 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1716 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1717 #define CONV(X) \
1718  case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1719  case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1720  case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1721 
1722  switch (CC) {
1723  default:
1724  llvm_unreachable("Invalid integer condition!");
1725 
1726  CONV(EQ);
1727  CONV(NE);
1728  CONV(GT);
1729  CONV(GE);
1730  CONV(LT);
1731  CONV(LE);
1732 
1733  case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1734  case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1735  }
1736 #undef CONV
1737 }
1738 
1739 // If C can be converted to a comparison against zero, adjust the operands
1740 // as necessary.
1741 static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
1742  if (C.ICmpType == SystemZICMP::UnsignedOnly)
1743  return;
1744 
1745  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1746  if (!ConstOp1)
1747  return;
1748 
1749  int64_t Value = ConstOp1->getSExtValue();
1750  if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1751  (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1752  (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1753  (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1754  C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1755  C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1756  }
1757 }
1758 
1759 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1760 // adjust the operands as necessary.
1761 static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
1762  Comparison &C) {
1763  // For us to make any changes, it must a comparison between a single-use
1764  // load and a constant.
1765  if (!C.Op0.hasOneUse() ||
1766  C.Op0.getOpcode() != ISD::LOAD ||
1767  C.Op1.getOpcode() != ISD::Constant)
1768  return;
1769 
1770  // We must have an 8- or 16-bit load.
1771  auto *Load = cast<LoadSDNode>(C.Op0);
1772  unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1773  if (NumBits != 8 && NumBits != 16)
1774  return;
1775 
1776  // The load must be an extending one and the constant must be within the
1777  // range of the unextended value.
1778  auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1779  uint64_t Value = ConstOp1->getZExtValue();
1780  uint64_t Mask = (1 << NumBits) - 1;
1781  if (Load->getExtensionType() == ISD::SEXTLOAD) {
1782  // Make sure that ConstOp1 is in range of C.Op0.
1783  int64_t SignedValue = ConstOp1->getSExtValue();
1784  if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1785  return;
1786  if (C.ICmpType != SystemZICMP::SignedOnly) {
1787  // Unsigned comparison between two sign-extended values is equivalent
1788  // to unsigned comparison between two zero-extended values.
1789  Value &= Mask;
1790  } else if (NumBits == 8) {
1791  // Try to treat the comparison as unsigned, so that we can use CLI.
1792  // Adjust CCMask and Value as necessary.
1793  if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1794  // Test whether the high bit of the byte is set.
1795  Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1796  else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1797  // Test whether the high bit of the byte is clear.
1798  Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1799  else
1800  // No instruction exists for this combination.
1801  return;
1802  C.ICmpType = SystemZICMP::UnsignedOnly;
1803  }
1804  } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1805  if (Value > Mask)
1806  return;
1807  // If the constant is in range, we can use any comparison.
1808  C.ICmpType = SystemZICMP::Any;
1809  } else
1810  return;
1811 
1812  // Make sure that the first operand is an i32 of the right extension type.
1813  ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1814  ISD::SEXTLOAD :
1815  ISD::ZEXTLOAD);
1816  if (C.Op0.getValueType() != MVT::i32 ||
1817  Load->getExtensionType() != ExtType) {
1818  C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(),
1819  Load->getBasePtr(), Load->getPointerInfo(),
1820  Load->getMemoryVT(), Load->getAlignment(),
1821  Load->getMemOperand()->getFlags());
1822  // Update the chain uses.
1823  DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0.getValue(1));
1824  }
1825 
1826  // Make sure that the second operand is an i32 with the right value.
1827  if (C.Op1.getValueType() != MVT::i32 ||
1828  Value != ConstOp1->getZExtValue())
1829  C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1830 }
1831 
1832 // Return true if Op is either an unextended load, or a load suitable
1833 // for integer register-memory comparisons of type ICmpType.
1834 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1835  auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1836  if (Load) {
1837  // There are no instructions to compare a register with a memory byte.
1838  if (Load->getMemoryVT() == MVT::i8)
1839  return false;
1840  // Otherwise decide on extension type.
1841  switch (Load->getExtensionType()) {
1842  case ISD::NON_EXTLOAD:
1843  return true;
1844  case ISD::SEXTLOAD:
1845  return ICmpType != SystemZICMP::UnsignedOnly;
1846  case ISD::ZEXTLOAD:
1847  return ICmpType != SystemZICMP::SignedOnly;
1848  default:
1849  break;
1850  }
1851  }
1852  return false;
1853 }
1854 
1855 // Return true if it is better to swap the operands of C.
1856 static bool shouldSwapCmpOperands(const Comparison &C) {
1857  // Leave f128 comparisons alone, since they have no memory forms.
1858  if (C.Op0.getValueType() == MVT::f128)
1859  return false;
1860 
1861  // Always keep a floating-point constant second, since comparisons with
1862  // zero can use LOAD TEST and comparisons with other constants make a
1863  // natural memory operand.
1864  if (isa<ConstantFPSDNode>(C.Op1))
1865  return false;
1866 
1867  // Never swap comparisons with zero since there are many ways to optimize
1868  // those later.
1869  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1870  if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1871  return false;
1872 
1873  // Also keep natural memory operands second if the loaded value is
1874  // only used here. Several comparisons have memory forms.
1875  if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1876  return false;
1877 
1878  // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1879  // In that case we generally prefer the memory to be second.
1880  if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1881  // The only exceptions are when the second operand is a constant and
1882  // we can use things like CHHSI.
1883  if (!ConstOp1)
1884  return true;
1885  // The unsigned memory-immediate instructions can handle 16-bit
1886  // unsigned integers.
1887  if (C.ICmpType != SystemZICMP::SignedOnly &&
1888  isUInt<16>(ConstOp1->getZExtValue()))
1889  return false;
1890  // The signed memory-immediate instructions can handle 16-bit
1891  // signed integers.
1892  if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1893  isInt<16>(ConstOp1->getSExtValue()))
1894  return false;
1895  return true;
1896  }
1897 
1898  // Try to promote the use of CGFR and CLGFR.
1899  unsigned Opcode0 = C.Op0.getOpcode();
1900  if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1901  return true;
1902  if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1903  return true;
1904  if (C.ICmpType != SystemZICMP::SignedOnly &&
1905  Opcode0 == ISD::AND &&
1906  C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1907  cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1908  return true;
1909 
1910  return false;
1911 }
1912 
1913 // Return a version of comparison CC mask CCMask in which the LT and GT
1914 // actions are swapped.
1915 static unsigned reverseCCMask(unsigned CCMask) {
1916  return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1918  (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1919  (CCMask & SystemZ::CCMASK_CMP_UO));
1920 }
1921 
1922 // Check whether C tests for equality between X and Y and whether X - Y
1923 // or Y - X is also computed. In that case it's better to compare the
1924 // result of the subtraction against zero.
1925 static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
1926  Comparison &C) {
1927  if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1928  C.CCMask == SystemZ::CCMASK_CMP_NE) {
1929  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1930  SDNode *N = *I;
1931  if (N->getOpcode() == ISD::SUB &&
1932  ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1933  (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1934  C.Op0 = SDValue(N, 0);
1935  C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1936  return;
1937  }
1938  }
1939  }
1940 }
1941 
1942 // Check whether C compares a floating-point value with zero and if that
1943 // floating-point value is also negated. In this case we can use the
1944 // negation to set CC, so avoiding separate LOAD AND TEST and
1945 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1946 static void adjustForFNeg(Comparison &C) {
1947  auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1948  if (C1 && C1->isZero()) {
1949  for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1950  SDNode *N = *I;
1951  if (N->getOpcode() == ISD::FNEG) {
1952  C.Op0 = SDValue(N, 0);
1953  C.CCMask = reverseCCMask(C.CCMask);
1954  return;
1955  }
1956  }
1957  }
1958 }
1959 
1960 // Check whether C compares (shl X, 32) with 0 and whether X is
1961 // also sign-extended. In that case it is better to test the result
1962 // of the sign extension using LTGFR.
1963 //
1964 // This case is important because InstCombine transforms a comparison
1965 // with (sext (trunc X)) into a comparison with (shl X, 32).
1966 static void adjustForLTGFR(Comparison &C) {
1967  // Check for a comparison between (shl X, 32) and 0.
1968  if (C.Op0.getOpcode() == ISD::SHL &&
1969  C.Op0.getValueType() == MVT::i64 &&
1970  C.Op1.getOpcode() == ISD::Constant &&
1971  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1972  auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1973  if (C1 && C1->getZExtValue() == 32) {
1974  SDValue ShlOp0 = C.Op0.getOperand(0);
1975  // See whether X has any SIGN_EXTEND_INREG uses.
1976  for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1977  SDNode *N = *I;
1978  if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1979  cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1980  C.Op0 = SDValue(N, 0);
1981  return;
1982  }
1983  }
1984  }
1985  }
1986 }
1987 
1988 // If C compares the truncation of an extending load, try to compare
1989 // the untruncated value instead. This exposes more opportunities to
1990 // reuse CC.
1991 static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
1992  Comparison &C) {
1993  if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1994  C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1995  C.Op1.getOpcode() == ISD::Constant &&
1996  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1997  auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1998  if (L->getMemoryVT().getStoreSizeInBits() <= C.Op0.getValueSizeInBits()) {
1999  unsigned Type = L->getExtensionType();
2000  if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
2001  (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
2002  C.Op0 = C.Op0.getOperand(0);
2003  C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
2004  }
2005  }
2006  }
2007 }
2008 
2009 // Return true if shift operation N has an in-range constant shift value.
2010 // Store it in ShiftVal if so.
2011 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
2012  auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
2013  if (!Shift)
2014  return false;
2015 
2016  uint64_t Amount = Shift->getZExtValue();
2017  if (Amount >= N.getValueSizeInBits())
2018  return false;
2019 
2020  ShiftVal = Amount;
2021  return true;
2022 }
2023 
2024 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
2025 // instruction and whether the CC value is descriptive enough to handle
2026 // a comparison of type Opcode between the AND result and CmpVal.
2027 // CCMask says which comparison result is being tested and BitSize is
2028 // the number of bits in the operands. If TEST UNDER MASK can be used,
2029 // return the corresponding CC mask, otherwise return 0.
2030 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
2031  uint64_t Mask, uint64_t CmpVal,
2032  unsigned ICmpType) {
2033  assert(Mask != 0 && "ANDs with zero should have been removed by now");
2034 
2035  // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
2036  if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
2037  !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
2038  return 0;
2039 
2040  // Work out the masks for the lowest and highest bits.
2041  unsigned HighShift = 63 - countLeadingZeros(Mask);
2042  uint64_t High = uint64_t(1) << HighShift;
2043  uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
2044 
2045  // Signed ordered comparisons are effectively unsigned if the sign
2046  // bit is dropped.
2047  bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
2048 
2049  // Check for equality comparisons with 0, or the equivalent.
2050  if (CmpVal == 0) {
2051  if (CCMask == SystemZ::CCMASK_CMP_EQ)
2052  return SystemZ::CCMASK_TM_ALL_0;
2053  if (CCMask == SystemZ::CCMASK_CMP_NE)
2055  }
2056  if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
2057  if (CCMask == SystemZ::CCMASK_CMP_LT)
2058  return SystemZ::CCMASK_TM_ALL_0;
2059  if (CCMask == SystemZ::CCMASK_CMP_GE)
2061  }
2062  if (EffectivelyUnsigned && CmpVal < Low) {
2063  if (CCMask == SystemZ::CCMASK_CMP_LE)
2064  return SystemZ::CCMASK_TM_ALL_0;
2065  if (CCMask == SystemZ::CCMASK_CMP_GT)
2067  }
2068 
2069  // Check for equality comparisons with the mask, or the equivalent.
2070  if (CmpVal == Mask) {
2071  if (CCMask == SystemZ::CCMASK_CMP_EQ)
2072  return SystemZ::CCMASK_TM_ALL_1;
2073  if (CCMask == SystemZ::CCMASK_CMP_NE)
2075  }
2076  if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
2077  if (CCMask == SystemZ::CCMASK_CMP_GT)
2078  return SystemZ::CCMASK_TM_ALL_1;
2079  if (CCMask == SystemZ::CCMASK_CMP_LE)
2081  }
2082  if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
2083  if (CCMask == SystemZ::CCMASK_CMP_GE)
2084  return SystemZ::CCMASK_TM_ALL_1;
2085  if (CCMask == SystemZ::CCMASK_CMP_LT)
2087  }
2088 
2089  // Check for ordered comparisons with the top bit.
2090  if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
2091  if (CCMask == SystemZ::CCMASK_CMP_LE)
2092  return SystemZ::CCMASK_TM_MSB_0;
2093  if (CCMask == SystemZ::CCMASK_CMP_GT)
2094  return SystemZ::CCMASK_TM_MSB_1;
2095  }
2096  if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
2097  if (CCMask == SystemZ::CCMASK_CMP_LT)
2098  return SystemZ::CCMASK_TM_MSB_0;
2099  if (CCMask == SystemZ::CCMASK_CMP_GE)
2100  return SystemZ::CCMASK_TM_MSB_1;
2101  }
2102 
2103  // If there are just two bits, we can do equality checks for Low and High
2104  // as well.
2105  if (Mask == Low + High) {
2106  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
2108  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
2110  if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
2112  if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
2114  }
2115 
2116  // Looks like we've exhausted our options.
2117  return 0;
2118 }
2119 
2120 // See whether C can be implemented as a TEST UNDER MASK instruction.
2121 // Update the arguments with the TM version if so.
2122 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
2123  Comparison &C) {
2124  // Check that we have a comparison with a constant.
2125  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
2126  if (!ConstOp1)
2127  return;
2128  uint64_t CmpVal = ConstOp1->getZExtValue();
2129 
2130  // Check whether the nonconstant input is an AND with a constant mask.
2131  Comparison NewC(C);
2132  uint64_t MaskVal;
2133  ConstantSDNode *Mask = nullptr;
2134  if (C.Op0.getOpcode() == ISD::AND) {
2135  NewC.Op0 = C.Op0.getOperand(0);
2136  NewC.Op1 = C.Op0.getOperand(1);
2137  Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2138  if (!Mask)
2139  return;
2140  MaskVal = Mask->getZExtValue();
2141  } else {
2142  // There is no instruction to compare with a 64-bit immediate
2143  // so use TMHH instead if possible. We need an unsigned ordered
2144  // comparison with an i64 immediate.
2145  if (NewC.Op0.getValueType() != MVT::i64 ||
2146  NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
2147  NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
2148  NewC.ICmpType == SystemZICMP::SignedOnly)
2149  return;
2150  // Convert LE and GT comparisons into LT and GE.
2151  if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
2152  NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
2153  if (CmpVal == uint64_t(-1))
2154  return;
2155  CmpVal += 1;
2156  NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2157  }
2158  // If the low N bits of Op1 are zero than the low N bits of Op0 can
2159  // be masked off without changing the result.
2160  MaskVal = -(CmpVal & -CmpVal);
2161  NewC.ICmpType = SystemZICMP::UnsignedOnly;
2162  }
2163  if (!MaskVal)
2164  return;
2165 
2166  // Check whether the combination of mask, comparison value and comparison
2167  // type are suitable.
2168  unsigned BitSize = NewC.Op0.getValueSizeInBits();
2169  unsigned NewCCMask, ShiftVal;
2170  if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2171  NewC.Op0.getOpcode() == ISD::SHL &&
2172  isSimpleShift(NewC.Op0, ShiftVal) &&
2173  (MaskVal >> ShiftVal != 0) &&
2174  ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
2175  (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2176  MaskVal >> ShiftVal,
2177  CmpVal >> ShiftVal,
2178  SystemZICMP::Any))) {
2179  NewC.Op0 = NewC.Op0.getOperand(0);
2180  MaskVal >>= ShiftVal;
2181  } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
2182  NewC.Op0.getOpcode() == ISD::SRL &&
2183  isSimpleShift(NewC.Op0, ShiftVal) &&
2184  (MaskVal << ShiftVal != 0) &&
2185  ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
2186  (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
2187  MaskVal << ShiftVal,
2188  CmpVal << ShiftVal,
2190  NewC.Op0 = NewC.Op0.getOperand(0);
2191  MaskVal <<= ShiftVal;
2192  } else {
2193  NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
2194  NewC.ICmpType);
2195  if (!NewCCMask)
2196  return;
2197  }
2198 
2199  // Go ahead and make the change.
2200  C.Opcode = SystemZISD::TM;
2201  C.Op0 = NewC.Op0;
2202  if (Mask && Mask->getZExtValue() == MaskVal)
2203  C.Op1 = SDValue(Mask, 0);
2204  else
2205  C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2206  C.CCValid = SystemZ::CCMASK_TM;
2207  C.CCMask = NewCCMask;
2208 }
2209 
2210 // See whether the comparison argument contains a redundant AND
2211 // and remove it if so. This sometimes happens due to the generic
2212 // BRCOND expansion.
2213 static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL,
2214  Comparison &C) {
2215  if (C.Op0.getOpcode() != ISD::AND)
2216  return;
2217  auto *Mask = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
2218  if (!Mask)
2219  return;
2220  KnownBits Known;
2221  DAG.computeKnownBits(C.Op0.getOperand(0), Known);
2222  if ((~Known.Zero).getZExtValue() & ~Mask->getZExtValue())
2223  return;
2224 
2225  C.Op0 = C.Op0.getOperand(0);
2226 }
2227 
2228 // Return a Comparison that tests the condition-code result of intrinsic
2229 // node Call against constant integer CC using comparison code Cond.
2230 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2231 // and CCValid is the set of possible condition-code results.
2232 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2233  SDValue Call, unsigned CCValid, uint64_t CC,
2234  ISD::CondCode Cond) {
2235  Comparison C(Call, SDValue());
2236  C.Opcode = Opcode;
2237  C.CCValid = CCValid;
2238  if (Cond == ISD::SETEQ)
2239  // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2240  C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2241  else if (Cond == ISD::SETNE)
2242  // ...and the inverse of that.
2243  C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2244  else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2245  // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2246  // always true for CC>3.
2247  C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2248  else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2249  // ...and the inverse of that.
2250  C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2251  else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2252  // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2253  // always true for CC>3.
2254  C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2255  else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2256  // ...and the inverse of that.
2257  C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2258  else
2259  llvm_unreachable("Unexpected integer comparison type");
2260  C.CCMask &= CCValid;
2261  return C;
2262 }
2263 
2264 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2265 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2266  ISD::CondCode Cond, const SDLoc &DL) {
2267  if (CmpOp1.getOpcode() == ISD::Constant) {
2268  uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2269  unsigned Opcode, CCValid;
2270  if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2271  CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2272  isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2273  return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2274  if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2275  CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2276  isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2277  return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2278  }
2279  Comparison C(CmpOp0, CmpOp1);
2280  C.CCMask = CCMaskForCondCode(Cond);
2281  if (C.Op0.getValueType().isFloatingPoint()) {
2282  C.CCValid = SystemZ::CCMASK_FCMP;
2283  C.Opcode = SystemZISD::FCMP;
2284  adjustForFNeg(C);
2285  } else {
2286  C.CCValid = SystemZ::CCMASK_ICMP;
2287  C.Opcode = SystemZISD::ICMP;
2288  // Choose the type of comparison. Equality and inequality tests can
2289  // use either signed or unsigned comparisons. The choice also doesn't
2290  // matter if both sign bits are known to be clear. In those cases we
2291  // want to give the main isel code the freedom to choose whichever
2292  // form fits best.
2293  if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2294  C.CCMask == SystemZ::CCMASK_CMP_NE ||
2295  (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2296  C.ICmpType = SystemZICMP::Any;
2297  else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2298  C.ICmpType = SystemZICMP::UnsignedOnly;
2299  else
2300  C.ICmpType = SystemZICMP::SignedOnly;
2301  C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2302  adjustForRedundantAnd(DAG, DL, C);
2303  adjustZeroCmp(DAG, DL, C);
2304  adjustSubwordCmp(DAG, DL, C);
2305  adjustForSubtraction(DAG, DL, C);
2306  adjustForLTGFR(C);
2307  adjustICmpTruncate(DAG, DL, C);
2308  }
2309 
2310  if (shouldSwapCmpOperands(C)) {
2311  std::swap(C.Op0, C.Op1);
2312  C.CCMask = reverseCCMask(C.CCMask);
2313  }
2314 
2315  adjustForTestUnderMask(DAG, DL, C);
2316  return C;
2317 }
2318 
2319 // Emit the comparison instruction described by C.
2320 static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2321  if (!C.Op1.getNode()) {
2322  SDNode *Node;
2323  switch (C.Op0.getOpcode()) {
2325  Node = emitIntrinsicWithCCAndChain(DAG, C.Op0, C.Opcode);
2326  return SDValue(Node, 0);
2328  Node = emitIntrinsicWithCC(DAG, C.Op0, C.Opcode);
2329  return SDValue(Node, Node->getNumValues() - 1);
2330  default:
2331  llvm_unreachable("Invalid comparison operands");
2332  }
2333  }
2334  if (C.Opcode == SystemZISD::ICMP)
2335  return DAG.getNode(SystemZISD::ICMP, DL, MVT::i32, C.Op0, C.Op1,
2336  DAG.getConstant(C.ICmpType, DL, MVT::i32));
2337  if (C.Opcode == SystemZISD::TM) {
2338  bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2339  bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2340  return DAG.getNode(SystemZISD::TM, DL, MVT::i32, C.Op0, C.Op1,
2341  DAG.getConstant(RegisterOnly, DL, MVT::i32));
2342  }
2343  return DAG.getNode(C.Opcode, DL, MVT::i32, C.Op0, C.Op1);
2344 }
2345 
2346 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2347 // 64 bits. Extend is the extension type to use. Store the high part
2348 // in Hi and the low part in Lo.
2349 static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
2350  SDValue Op0, SDValue Op1, SDValue &Hi,
2351  SDValue &Lo) {
2352  Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2353  Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2354  SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2355  Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2356  DAG.getConstant(32, DL, MVT::i64));
2357  Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2358  Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2359 }
2360 
2361 // Lower a binary operation that produces two VT results, one in each
2362 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2363 // and Opcode performs the GR128 operation. Store the even register result
2364 // in Even and the odd register result in Odd.
2365 static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
2366  unsigned Opcode, SDValue Op0, SDValue Op1,
2367  SDValue &Even, SDValue &Odd) {
2368  SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
2369  bool Is32Bit = is32Bit(VT);
2370  Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2371  Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2372 }
2373 
2374 // Return an i32 value that is 1 if the CC value produced by CCReg is
2375 // in the mask CCMask and 0 otherwise. CC is known to have a value
2376 // in CCValid, so other values can be ignored.
2377 static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg,
2378  unsigned CCValid, unsigned CCMask) {
2379  SDValue Ops[] = { DAG.getConstant(1, DL, MVT::i32),
2380  DAG.getConstant(0, DL, MVT::i32),
2381  DAG.getConstant(CCValid, DL, MVT::i32),
2382  DAG.getConstant(CCMask, DL, MVT::i32), CCReg };
2383  return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, MVT::i32, Ops);
2384 }
2385 
2386 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2387 // be done directly. IsFP is true if CC is for a floating-point rather than
2388 // integer comparison.
2389 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2390  switch (CC) {
2391  case ISD::SETOEQ:
2392  case ISD::SETEQ:
2393  return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2394 
2395  case ISD::SETOGE:
2396  case ISD::SETGE:
2397  return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2398 
2399  case ISD::SETOGT:
2400  case ISD::SETGT:
2401  return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2402 
2403  case ISD::SETUGT:
2404  return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2405 
2406  default:
2407  return 0;
2408  }
2409 }
2410 
2411 // Return the SystemZISD vector comparison operation for CC or its inverse,
2412 // or 0 if neither can be done directly. Indicate in Invert whether the
2413 // result is for the inverse of CC. IsFP is true if CC is for a
2414 // floating-point rather than integer comparison.
2415 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2416  bool &Invert) {
2417  if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2418  Invert = false;
2419  return Opcode;
2420  }
2421 
2422  CC = ISD::getSetCCInverse(CC, !IsFP);
2423  if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2424  Invert = true;
2425  return Opcode;
2426  }
2427 
2428  return 0;
2429 }
2430 
2431 // Return a v2f64 that contains the extended form of elements Start and Start+1
2432 // of v4f32 value Op.
2433 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
2434  SDValue Op) {
2435  int Mask[] = { Start, -1, Start + 1, -1 };
2436  Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2437  return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2438 }
2439 
2440 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2441 // producing a result of type VT.
2442 SDValue SystemZTargetLowering::getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
2443  const SDLoc &DL, EVT VT,
2444  SDValue CmpOp0,
2445  SDValue CmpOp1) const {
2446  // There is no hardware support for v4f32 (unless we have the vector
2447  // enhancements facility 1), so extend the vector into two v2f64s
2448  // and compare those.
2449  if (CmpOp0.getValueType() == MVT::v4f32 &&
2450  !Subtarget.hasVectorEnhancements1()) {
2451  SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2452  SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2453  SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2454  SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2455  SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2456  SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2457  return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2458  }
2459  return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2460 }
2461 
2462 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2463 // an integer mask of type VT.
2464 SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
2465  const SDLoc &DL, EVT VT,
2466  ISD::CondCode CC,
2467  SDValue CmpOp0,
2468  SDValue CmpOp1) const {
2469  bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2470  bool Invert = false;
2471  SDValue Cmp;
2472  switch (CC) {
2473  // Handle tests for order using (or (ogt y x) (oge x y)).
2474  case ISD::SETUO:
2475  Invert = true;
2477  case ISD::SETO: {
2478  assert(IsFP && "Unexpected integer comparison");
2479  SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2480  SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2481  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2482  break;
2483  }
2484 
2485  // Handle <> tests using (or (ogt y x) (ogt x y)).
2486  case ISD::SETUEQ:
2487  Invert = true;
2489  case ISD::SETONE: {
2490  assert(IsFP && "Unexpected integer comparison");
2491  SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2492  SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2493  Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2494  break;
2495  }
2496 
2497  // Otherwise a single comparison is enough. It doesn't really
2498  // matter whether we try the inversion or the swap first, since
2499  // there are no cases where both work.
2500  default:
2501  if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2502  Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2503  else {
2505  if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2506  Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2507  else
2508  llvm_unreachable("Unhandled comparison");
2509  }
2510  break;
2511  }
2512  if (Invert) {
2514  DAG.getConstant(65535, DL, MVT::i32));
2515  Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2516  Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2517  }
2518  return Cmp;
2519 }
2520 
2521 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2522  SelectionDAG &DAG) const {
2523  SDValue CmpOp0 = Op.getOperand(0);
2524  SDValue CmpOp1 = Op.getOperand(1);
2525  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2526  SDLoc DL(Op);
2527  EVT VT = Op.getValueType();
2528  if (VT.isVector())
2529  return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2530 
2531  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2532  SDValue CCReg = emitCmp(DAG, DL, C);
2533  return emitSETCC(DAG, DL, CCReg, C.CCValid, C.CCMask);
2534 }
2535 
2536 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2537  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2538  SDValue CmpOp0 = Op.getOperand(2);
2539  SDValue CmpOp1 = Op.getOperand(3);
2540  SDValue Dest = Op.getOperand(4);
2541  SDLoc DL(Op);
2542 
2543  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2544  SDValue CCReg = emitCmp(DAG, DL, C);
2545  return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2546  Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2547  DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, CCReg);
2548 }
2549 
2550 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2551 // allowing Pos and Neg to be wider than CmpOp.
2552 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2553  return (Neg.getOpcode() == ISD::SUB &&
2554  Neg.getOperand(0).getOpcode() == ISD::Constant &&
2555  cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2556  Neg.getOperand(1) == Pos &&
2557  (Pos == CmpOp ||
2558  (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2559  Pos.getOperand(0) == CmpOp)));
2560 }
2561 
2562 // Return the absolute or negative absolute of Op; IsNegative decides which.
2563 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2564  bool IsNegative) {
2565  Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2566  if (IsNegative)
2567  Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2568  DAG.getConstant(0, DL, Op.getValueType()), Op);
2569  return Op;
2570 }
2571 
2572 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2573  SelectionDAG &DAG) const {
2574  SDValue CmpOp0 = Op.getOperand(0);
2575  SDValue CmpOp1 = Op.getOperand(1);
2576  SDValue TrueOp = Op.getOperand(2);
2577  SDValue FalseOp = Op.getOperand(3);
2578  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2579  SDLoc DL(Op);
2580 
2581  Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2582 
2583  // Check for absolute and negative-absolute selections, including those
2584  // where the comparison value is sign-extended (for LPGFR and LNGFR).
2585  // This check supplements the one in DAGCombiner.
2586  if (C.Opcode == SystemZISD::ICMP &&
2587  C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2588  C.CCMask != SystemZ::CCMASK_CMP_NE &&
2589  C.Op1.getOpcode() == ISD::Constant &&
2590  cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2591  if (isAbsolute(C.Op0, TrueOp, FalseOp))
2592  return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2593  if (isAbsolute(C.Op0, FalseOp, TrueOp))
2594  return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2595  }
2596 
2597  SDValue CCReg = emitCmp(DAG, DL, C);
2598  SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2599  DAG.getConstant(C.CCMask, DL, MVT::i32), CCReg};
2600 
2601  return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, Op.getValueType(), Ops);
2602 }
2603 
2604 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2605  SelectionDAG &DAG) const {
2606  SDLoc DL(Node);
2607  const GlobalValue *GV = Node->getGlobal();
2608  int64_t Offset = Node->getOffset();
2609  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2611 
2612  SDValue Result;
2613  if (Subtarget.isPC32DBLSymbol(GV, CM)) {
2614  // Assign anchors at 1<<12 byte boundaries.
2615  uint64_t Anchor = Offset & ~uint64_t(0xfff);
2616  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2617  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2618 
2619  // The offset can be folded into the address if it is aligned to a halfword.
2620  Offset -= Anchor;
2621  if (Offset != 0 && (Offset & 1) == 0) {
2622  SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2623  Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2624  Offset = 0;
2625  }
2626  } else {
2627  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2628  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2629  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2631  }
2632 
2633  // If there was a non-zero offset that we didn't fold, create an explicit
2634  // addition for it.
2635  if (Offset != 0)
2636  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2637  DAG.getConstant(Offset, DL, PtrVT));
2638 
2639  return Result;
2640 }
2641 
2642 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2643  SelectionDAG &DAG,
2644  unsigned Opcode,
2645  SDValue GOTOffset) const {
2646  SDLoc DL(Node);
2647  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2648  SDValue Chain = DAG.getEntryNode();
2649  SDValue Glue;
2650 
2651  // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2652  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2653  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2654  Glue = Chain.getValue(1);
2655  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2656  Glue = Chain.getValue(1);
2657 
2658  // The first call operand is the chain and the second is the TLS symbol.
2660  Ops.push_back(Chain);
2661  Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2662  Node->getValueType(0),
2663  0, 0));
2664 
2665  // Add argument registers to the end of the list so that they are
2666  // known live into the call.
2667  Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2668  Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2669 
2670  // Add a register mask operand representing the call-preserved registers.
2671  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2672  const uint32_t *Mask =
2674  assert(Mask && "Missing call preserved mask for calling convention");
2675  Ops.push_back(DAG.getRegisterMask(Mask));
2676 
2677  // Glue the call to the argument copies.
2678  Ops.push_back(Glue);
2679 
2680  // Emit the call.
2681  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2682  Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2683  Glue = Chain.getValue(1);
2684 
2685  // Copy the return value from %r2.
2686  return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2687 }
2688 
2689 SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
2690  SelectionDAG &DAG) const {
2691  SDValue Chain = DAG.getEntryNode();
2692  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2693 
2694  // The high part of the thread pointer is in access register 0.
2695  SDValue TPHi = DAG.getCopyFromReg(Chain, DL, SystemZ::A0, MVT::i32);
2696  TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2697 
2698  // The low part of the thread pointer is in access register 1.
2699  SDValue TPLo = DAG.getCopyFromReg(Chain, DL, SystemZ::A1, MVT::i32);
2700  TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2701 
2702  // Merge them into a single 64-bit address.
2703  SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2704  DAG.getConstant(32, DL, PtrVT));
2705  return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2706 }
2707 
2708 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2709  SelectionDAG &DAG) const {
2710  if (DAG.getTarget().useEmulatedTLS())
2711  return LowerToTLSEmulatedModel(Node, DAG);
2712  SDLoc DL(Node);
2713  const GlobalValue *GV = Node->getGlobal();
2714  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2715  TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2716 
2717  SDValue TP = lowerThreadPointer(DL, DAG);
2718 
2719  // Get the offset of GA from the thread pointer, based on the TLS model.
2720  SDValue Offset;
2721  switch (model) {
2722  case TLSModel::GeneralDynamic: {
2723  // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2726 
2727  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2728  Offset = DAG.getLoad(
2729  PtrVT, DL, DAG.getEntryNode(), Offset,
2731 
2732  // Call __tls_get_offset to retrieve the offset.
2733  Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2734  break;
2735  }
2736 
2737  case TLSModel::LocalDynamic: {
2738  // Load the GOT offset of the module ID.
2741 
2742  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2743  Offset = DAG.getLoad(
2744  PtrVT, DL, DAG.getEntryNode(), Offset,
2746 
2747  // Call __tls_get_offset to retrieve the module base offset.
2748  Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2749 
2750  // Note: The SystemZLDCleanupPass will remove redundant computations
2751  // of the module base offset. Count total number of local-dynamic
2752  // accesses to trigger execution of that pass.
2756 
2757  // Add the per-symbol offset.
2759 
2760  SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2761  DTPOffset = DAG.getLoad(
2762  PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2764 
2765  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2766  break;
2767  }
2768 
2769  case TLSModel::InitialExec: {
2770  // Load the offset from the GOT.
2771  Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2773  Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2774  Offset =
2775  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2777  break;
2778  }
2779 
2780  case TLSModel::LocalExec: {
2781  // Force the offset into the constant pool and load it from there.
2784 
2785  Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2786  Offset = DAG.getLoad(
2787  PtrVT, DL, DAG.getEntryNode(), Offset,
2789  break;
2790  }
2791  }
2792 
2793  // Add the base and offset together.
2794  return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2795 }
2796 
2797 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2798  SelectionDAG &DAG) const {
2799  SDLoc DL(Node);
2800  const BlockAddress *BA = Node->getBlockAddress();
2801  int64_t Offset = Node->getOffset();
2802  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2803 
2804  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2805  Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2806  return Result;
2807 }
2808 
2809 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2810  SelectionDAG &DAG) const {
2811  SDLoc DL(JT);
2812  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2813  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2814 
2815  // Use LARL to load the address of the table.
2816  return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2817 }
2818 
2819 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2820  SelectionDAG &DAG) const {
2821  SDLoc DL(CP);
2822  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2823 
2824  SDValue Result;
2825  if (CP->isMachineConstantPoolEntry())
2826  Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2827  CP->getAlignment());
2828  else
2829  Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2830  CP->getAlignment(), CP->getOffset());
2831 
2832  // Use LARL to load the address of the constant pool entry.
2833  return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2834 }
2835 
2836 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
2837  SelectionDAG &DAG) const {
2838  MachineFunction &MF = DAG.getMachineFunction();
2839  MachineFrameInfo &MFI = MF.getFrameInfo();
2840  MFI.setFrameAddressIsTaken(true);
2841 
2842  SDLoc DL(Op);
2843  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2844  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2845 
2846  // If the back chain frame index has not been allocated yet, do so.
2848  int BackChainIdx = FI->getFramePointerSaveIndex();
2849  if (!BackChainIdx) {
2850  // By definition, the frame address is the address of the back chain.
2851  BackChainIdx = MFI.CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
2852  FI->setFramePointerSaveIndex(BackChainIdx);
2853  }
2854  SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
2855 
2856  // FIXME The frontend should detect this case.
2857  if (Depth > 0) {
2858  report_fatal_error("Unsupported stack frame traversal count");
2859  }
2860 
2861  return BackChain;
2862 }
2863 
2864 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
2865  SelectionDAG &DAG) const {
2866  MachineFunction &MF = DAG.getMachineFunction();
2867  MachineFrameInfo &MFI = MF.getFrameInfo();
2868  MFI.setReturnAddressIsTaken(true);
2869 
2871  return SDValue();
2872 
2873  SDLoc DL(Op);
2874  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2875  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2876 
2877  // FIXME The frontend should detect this case.
2878  if (Depth > 0) {
2879  report_fatal_error("Unsupported stack frame traversal count");
2880  }
2881 
2882  // Return R14D, which has the return address. Mark it an implicit live-in.
2883  unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
2884  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
2885 }
2886 
2887 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2888  SelectionDAG &DAG) const {
2889  SDLoc DL(Op);
2890  SDValue In = Op.getOperand(0);
2891  EVT InVT = In.getValueType();
2892  EVT ResVT = Op.getValueType();
2893 
2894  // Convert loads directly. This is normally done by DAGCombiner,
2895  // but we need this case for bitcasts that are created during lowering
2896  // and which are then lowered themselves.
2897  if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2898  if (ISD::isNormalLoad(LoadN)) {
2899  SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(),
2900  LoadN->getBasePtr(), LoadN->getMemOperand());
2901  // Update the chain uses.
2902  DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1));
2903  return NewLoad;
2904  }
2905 
2906  if (InVT == MVT::i32 && ResVT == MVT::f32) {
2907  SDValue In64;
2908  if (Subtarget.hasHighWord()) {
2909  SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2910  MVT::i64);
2911  In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2912  MVT::i64, SDValue(U64, 0), In);
2913  } else {
2914  In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2915  In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2916  DAG.getConstant(32, DL, MVT::i64));
2917  }
2918  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2919  return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2920  DL, MVT::f32, Out64);
2921  }
2922  if (InVT == MVT::f32 && ResVT == MVT::i32) {
2923  SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2924  SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2925  MVT::f64, SDValue(U64, 0), In);
2926  SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2927  if (Subtarget.hasHighWord())
2928  return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2929  MVT::i32, Out64);
2930  SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2931  DAG.getConstant(32, DL, MVT::i64));
2932  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2933  }
2934  llvm_unreachable("Unexpected bitcast combination");
2935 }
2936 
2937 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2938  SelectionDAG &DAG) const {
2939  MachineFunction &MF = DAG.getMachineFunction();
2940  SystemZMachineFunctionInfo *FuncInfo =
2942  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2943 
2944  SDValue Chain = Op.getOperand(0);
2945  SDValue Addr = Op.getOperand(1);
2946  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2947  SDLoc DL(Op);
2948 
2949  // The initial values of each field.
2950  const unsigned NumFields = 4;
2951  SDValue Fields[NumFields] = {
2952  DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2953  DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2954  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2955  DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2956  };
2957 
2958  // Store each field into its respective slot.
2959  SDValue MemOps[NumFields];
2960  unsigned Offset = 0;
2961  for (unsigned I = 0; I < NumFields; ++I) {
2962  SDValue FieldAddr = Addr;
2963  if (Offset != 0)
2964  FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2965  DAG.getIntPtrConstant(Offset, DL));
2966  MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2967  MachinePointerInfo(SV, Offset));
2968  Offset += 8;
2969  }
2970  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2971 }
2972 
2973 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2974  SelectionDAG &DAG) const {
2975  SDValue Chain = Op.getOperand(0);
2976  SDValue DstPtr = Op.getOperand(1);
2977  SDValue SrcPtr = Op.getOperand(2);
2978  const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2979  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2980  SDLoc DL(Op);
2981 
2982  return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2983  /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2984  /*isTailCall*/false,
2985  MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2986 }
2987 
2988 SDValue SystemZTargetLowering::
2989 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2990  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
2991  MachineFunction &MF = DAG.getMachineFunction();
2992  bool RealignOpt = !MF.getFunction().hasFnAttribute("no-realign-stack");
2993  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
2994 
2995  SDValue Chain = Op.getOperand(0);
2996  SDValue Size = Op.getOperand(1);
2997  SDValue Align = Op.getOperand(2);
2998  SDLoc DL(Op);
2999 
3000  // If user has set the no alignment function attribute, ignore
3001  // alloca alignments.
3002  uint64_t AlignVal = (RealignOpt ?
3003  dyn_cast<ConstantSDNode>(Align)->getZExtValue() : 0);
3004 
3005  uint64_t StackAlign = TFI->getStackAlignment();
3006  uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
3007  uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
3008 
3009  unsigned SPReg = getStackPointerRegisterToSaveRestore();
3010  SDValue NeededSpace = Size;
3011 
3012  // Get a reference to the stack pointer.
3013  SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
3014 
3015  // If we need a backchain, save it now.
3016  SDValue Backchain;
3017  if (StoreBackchain)
3018  Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
3019 
3020  // Add extra space for alignment if needed.
3021  if (ExtraAlignSpace)
3022  NeededSpace = DAG.getNode(ISD::ADD, DL, MVT::i64, NeededSpace,
3023  DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
3024 
3025  // Get the new stack pointer value.
3026  SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
3027 
3028  // Copy the new stack pointer back.
3029  Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
3030 
3031  // The allocated data lives above the 160 bytes allocated for the standard
3032  // frame, plus any outgoing stack arguments. We don't know how much that
3033  // amounts to yet, so emit a special ADJDYNALLOC placeholder.
3034  SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3035  SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
3036 
3037  // Dynamically realign if needed.
3038  if (RequiredAlign > StackAlign) {
3039  Result =
3040  DAG.getNode(ISD::ADD, DL, MVT::i64, Result,
3041  DAG.getConstant(ExtraAlignSpace, DL, MVT::i64));
3042  Result =
3043  DAG.getNode(ISD::AND, DL, MVT::i64, Result,
3044  DAG.getConstant(~(RequiredAlign - 1), DL, MVT::i64));
3045  }
3046 
3047  if (StoreBackchain)
3048  Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3049 
3050  SDValue Ops[2] = { Result, Chain };
3051  return DAG.getMergeValues(Ops, DL);
3052 }
3053 
3054 SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
3055  SDValue Op, SelectionDAG &DAG) const {
3056  SDLoc DL(Op);
3057 
3058  return DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
3059 }
3060 
3061 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
3062  SelectionDAG &DAG) const {
3063  EVT VT = Op.getValueType();
3064  SDLoc DL(Op);
3065  SDValue Ops[2];
3066  if (is32Bit(VT))
3067  // Just do a normal 64-bit multiplication and extract the results.
3068  // We define this so that it can be used for constant division.
3070  Op.getOperand(1), Ops[1], Ops[0]);
3071  else if (Subtarget.hasMiscellaneousExtensions2())
3072  // SystemZISD::SMUL_LOHI returns the low result in the odd register and
3073  // the high result in the even register. ISD::SMUL_LOHI is defined to
3074  // return the low half first, so the results are in reverse order.
3076  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3077  else {
3078  // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
3079  //
3080  // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
3081  //
3082  // but using the fact that the upper halves are either all zeros
3083  // or all ones:
3084  //
3085  // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
3086  //
3087  // and grouping the right terms together since they are quicker than the
3088  // multiplication:
3089  //
3090  // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
3091  SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
3092  SDValue LL = Op.getOperand(0);
3093  SDValue RL = Op.getOperand(1);
3094  SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
3095  SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
3096  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3097  // the high result in the even register. ISD::SMUL_LOHI is defined to
3098  // return the low half first, so the results are in reverse order.
3100  LL, RL, Ops[1], Ops[0]);
3101  SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
3102  SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
3103  SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
3104  Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
3105  }
3106  return DAG.getMergeValues(Ops, DL);
3107 }
3108 
3109 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
3110  SelectionDAG &DAG) const {
3111  EVT VT = Op.getValueType();
3112  SDLoc DL(Op);
3113  SDValue Ops[2];
3114  if (is32Bit(VT))
3115  // Just do a normal 64-bit multiplication and extract the results.
3116  // We define this so that it can be used for constant division.
3118  Op.getOperand(1), Ops[1], Ops[0]);
3119  else
3120  // SystemZISD::UMUL_LOHI returns the low result in the odd register and
3121  // the high result in the even register. ISD::UMUL_LOHI is defined to
3122  // return the low half first, so the results are in reverse order.
3124  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3125  return DAG.getMergeValues(Ops, DL);
3126 }
3127 
3128 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
3129  SelectionDAG &DAG) const {
3130  SDValue Op0 = Op.getOperand(0);
3131  SDValue Op1 = Op.getOperand(1);
3132  EVT VT = Op.getValueType();
3133  SDLoc DL(Op);
3134 
3135  // We use DSGF for 32-bit division. This means the first operand must
3136  // always be 64-bit, and the second operand should be 32-bit whenever
3137  // that is possible, to improve performance.
3138  if (is32Bit(VT))
3139  Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
3140  else if (DAG.ComputeNumSignBits(Op1) > 32)
3141  Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
3142 
3143  // DSG(F) returns the remainder in the even register and the
3144  // quotient in the odd register.
3145  SDValue Ops[2];
3146  lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
3147  return DAG.getMergeValues(Ops, DL);
3148 }
3149 
3150 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3151  SelectionDAG &DAG) const {
3152  EVT VT = Op.getValueType();
3153  SDLoc DL(Op);
3154 
3155  // DL(G) returns the remainder in the even register and the
3156  // quotient in the odd register.
3157  SDValue Ops[2];
3159  Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3160  return DAG.getMergeValues(Ops, DL);
3161 }
3162 
3163 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3164  assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3165 
3166  // Get the known-zero masks for each operand.
3167  SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3168  KnownBits Known[2];
3169  DAG.computeKnownBits(Ops[0], Known[0]);
3170  DAG.computeKnownBits(Ops[1], Known[1]);
3171 
3172  // See if the upper 32 bits of one operand and the lower 32 bits of the
3173  // other are known zero. They are the low and high operands respectively.
3174  uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
3175  Known[1].Zero.getZExtValue() };
3176  unsigned High, Low;
3177  if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
3178  High = 1, Low = 0;
3179  else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
3180  High = 0, Low = 1;
3181  else
3182  return Op;
3183 
3184  SDValue LowOp = Ops[Low];
3185  SDValue HighOp = Ops[High];
3186 
3187  // If the high part is a constant, we're better off using IILH.
3188  if (HighOp.getOpcode() == ISD::Constant)
3189  return Op;
3190 
3191  // If the low part is a constant that is outside the range of LHI,
3192  // then we're better off using IILF.
3193  if (LowOp.getOpcode() == ISD::Constant) {
3194  int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
3195  if (!isInt<16>(Value))
3196  return Op;
3197  }
3198 
3199  // Check whether the high part is an AND that doesn't change the
3200  // high 32 bits and just masks out low bits. We can skip it if so.
3201  if (HighOp.getOpcode() == ISD::AND &&
3202  HighOp.getOperand(1).getOpcode() == ISD::Constant) {
3203  SDValue HighOp0 = HighOp.getOperand(0);
3204  uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
3205  if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
3206  HighOp = HighOp0;
3207  }
3208 
3209  // Take advantage of the fact that all GR32 operations only change the
3210  // low 32 bits by truncating Low to an i32 and inserting it directly
3211  // using a subreg. The interesting cases are those where the truncation
3212  // can be folded.
3213  SDLoc DL(Op);
3214  SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
3215  return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
3216  MVT::i64, HighOp, Low32);
3217 }
3218 
3219 // Lower SADDO/SSUBO/UADDO/USUBO nodes.
3220 SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
3221  SelectionDAG &DAG) const {
3222  SDNode *N = Op.getNode();
3223  SDValue LHS = N->getOperand(0);
3224  SDValue RHS = N->getOperand(1);
3225  SDLoc DL(N);
3226  unsigned BaseOp = 0;
3227  unsigned CCValid = 0;
3228  unsigned CCMask = 0;
3229 
3230  switch (Op.getOpcode()) {
3231  default: llvm_unreachable("Unknown instruction!");
3232  case ISD::SADDO:
3233  BaseOp = SystemZISD::SADDO;
3234  CCValid = SystemZ::CCMASK_ARITH;
3236  break;
3237  case ISD::SSUBO:
3238  BaseOp = SystemZISD::SSUBO;
3239  CCValid = SystemZ::CCMASK_ARITH;
3241  break;
3242  case ISD::UADDO:
3243  BaseOp = SystemZISD::UADDO;
3244  CCValid = SystemZ::CCMASK_LOGICAL;
3246  break;
3247  case ISD::USUBO:
3248  BaseOp = SystemZISD::USUBO;
3249  CCValid = SystemZ::CCMASK_LOGICAL;
3251  break;
3252  }
3253 
3254  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
3255  SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
3256 
3257  SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3258  if (N->getValueType(1) == MVT::i1)
3259  SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3260 
3261  return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3262 }
3263 
3264 // Lower ADDCARRY/SUBCARRY nodes.
3265 SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
3266  SelectionDAG &DAG) const {
3267 
3268  SDNode *N = Op.getNode();
3269  MVT VT = N->getSimpleValueType(0);
3270 
3271  // Let legalize expand this if it isn't a legal type yet.
3272  if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3273  return SDValue();
3274 
3275  SDValue LHS = N->getOperand(0);
3276  SDValue RHS = N->getOperand(1);
3277  SDValue Carry = Op.getOperand(2);
3278  SDLoc DL(N);
3279  unsigned BaseOp = 0;
3280  unsigned CCValid = 0;
3281  unsigned CCMask = 0;
3282 
3283  switch (Op.getOpcode()) {
3284  default: llvm_unreachable("Unknown instruction!");
3285  case ISD::ADDCARRY:
3286  BaseOp = SystemZISD::ADDCARRY;
3287  CCValid = SystemZ::CCMASK_LOGICAL;
3289  break;
3290  case ISD::SUBCARRY:
3291  BaseOp = SystemZISD::SUBCARRY;
3292  CCValid = SystemZ::CCMASK_LOGICAL;
3294  break;
3295  }
3296 
3297  // Set the condition code from the carry flag.
3298  Carry = DAG.getNode(SystemZISD::GET_CCMASK, DL, MVT::i32, Carry,
3299  DAG.getConstant(CCValid, DL, MVT::i32),
3300  DAG.getConstant(CCMask, DL, MVT::i32));
3301 
3302  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3303  SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry);
3304 
3305  SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3306  if (N->getValueType(1) == MVT::i1)
3307  SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3308 
3309  return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3310 }
3311 
3312 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3313  SelectionDAG &DAG) const {
3314  EVT VT = Op.getValueType();
3315  SDLoc DL(Op);
3316  Op = Op.getOperand(0);
3317 
3318  // Handle vector types via VPOPCT.
3319  if (VT.isVector()) {
3320  Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3321  Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3322  switch (VT.getScalarSizeInBits()) {
3323  case 8:
3324  break;
3325  case 16: {
3326  Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3327  SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
3328  SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3329  Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3330  Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3331  break;
3332  }
3333  case 32: {
3335  DAG.getConstant(0, DL, MVT::i32));
3336  Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3337  break;
3338  }
3339  case 64: {
3341  DAG.getConstant(0, DL, MVT::i32));
3342  Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3343  Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3344  break;
3345  }
3346  default:
3347  llvm_unreachable("Unexpected type");
3348  }
3349  return Op;
3350  }
3351 
3352  // Get the known-zero mask for the operand.
3353  KnownBits Known;
3354  DAG.computeKnownBits(Op, Known);
3355  unsigned NumSignificantBits = (~Known.Zero).getActiveBits();
3356  if (NumSignificantBits == 0)
3357  return DAG.getConstant(0, DL, VT);
3358 
3359  // Skip known-zero high parts of the operand.
3360  int64_t OrigBitSize = VT.getSizeInBits();
3361  int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
3362  BitSize = std::min(BitSize, OrigBitSize);
3363 
3364  // The POPCNT instruction counts the number of bits in each byte.
3365  Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3366  Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3367  Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3368 
3369  // Add up per-byte counts in a binary tree. All bits of Op at
3370  // position larger than BitSize remain zero throughout.
3371  for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
3372  SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3373  if (BitSize != OrigBitSize)
3374  Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3375  DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3376  Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3377  }
3378 
3379  // Extract overall result from high byte.
3380  if (BitSize > 8)
3381  Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3382  DAG.getConstant(BitSize - 8, DL, VT));
3383 
3384  return Op;
3385 }
3386 
3387 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3388  SelectionDAG &DAG) const {
3389  SDLoc DL(Op);
3390  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
3391  cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3392  SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
3393  cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3394 
3395  // The only fence that needs an instruction is a sequentially-consistent
3396  // cross-thread fence.
3397  if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
3398  FenceSSID == SyncScope::System) {
3399  return SDValue(DAG.getMachineNode(SystemZ::Serialize, DL, MVT::Other,
3400  Op.getOperand(0)),
3401  0);
3402  }
3403 
3404  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3405  return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3406 }
3407 
3408 // Op is an atomic load. Lower it into a normal volatile load.
3409 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3410  SelectionDAG &DAG) const {
3411  auto *Node = cast<AtomicSDNode>(Op.getNode());
3412  return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3413  Node->getChain(), Node->getBasePtr(),
3414  Node->getMemoryVT(), Node->getMemOperand());
3415 }
3416 
3417 // Op is an atomic store. Lower it into a normal volatile store.
3418 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3419  SelectionDAG &DAG) const {
3420  auto *Node = cast<AtomicSDNode>(Op.getNode());
3421  SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3422  Node->getBasePtr(), Node->getMemoryVT(),
3423  Node->getMemOperand());
3424  // We have to enforce sequential consistency by performing a
3425  // serialization operation after the store.
3426  if (Node->getOrdering() == AtomicOrdering::SequentiallyConsistent)
3427  Chain = SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op),
3428  MVT::Other, Chain), 0);
3429  return Chain;
3430 }
3431 
3432 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3433 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3434 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3435  SelectionDAG &DAG,
3436  unsigned Opcode) const {
3437  auto *Node = cast<AtomicSDNode>(Op.getNode());
3438 
3439  // 32-bit operations need no code outside the main loop.
3440  EVT NarrowVT = Node->getMemoryVT();
3441  EVT WideVT = MVT::i32;
3442  if (NarrowVT == WideVT)
3443  return Op;
3444 
3445  int64_t BitSize = NarrowVT.getSizeInBits();
3446  SDValue ChainIn = Node->getChain();
3447  SDValue Addr = Node->getBasePtr();
3448  SDValue Src2 = Node->getVal();
3449  MachineMemOperand *MMO = Node->getMemOperand();
3450  SDLoc DL(Node);
3451  EVT PtrVT = Addr.getValueType();
3452 
3453  // Convert atomic subtracts of constants into additions.
3454  if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3455  if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3457  Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3458  }
3459 
3460  // Get the address of the containing word.
3461  SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3462  DAG.getConstant(-4, DL, PtrVT));
3463 
3464  // Get the number of bits that the word must be rotated left in order
3465  // to bring the field to the top bits of a GR32.
3466  SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3467  DAG.getConstant(3, DL, PtrVT));
3468  BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3469 
3470  // Get the complementing shift amount, for rotating a field in the top
3471  // bits back to its proper position.
3472  SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3473  DAG.getConstant(0, DL, WideVT), BitShift);
3474 
3475  // Extend the source operand to 32 bits and prepare it for the inner loop.
3476  // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3477  // operations require the source to be shifted in advance. (This shift
3478  // can be folded if the source is constant.) For AND and NAND, the lower
3479  // bits must be set, while for other opcodes they should be left clear.
3480  if (Opcode != SystemZISD::ATOMIC_SWAPW)
3481  Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3482  DAG.getConstant(32 - BitSize, DL, WideVT));
3483  if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3485  Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3486  DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3487 
3488  // Construct the ATOMIC_LOADW_* node.
3489  SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3490  SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3491  DAG.getConstant(BitSize, DL, WideVT) };
3492  SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3493  NarrowVT, MMO);
3494 
3495  // Rotate the result of the final CS so that the field is in the lower
3496  // bits of a GR32, then truncate it.
3497  SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3498  DAG.getConstant(BitSize, DL, WideVT));
3499  SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3500 
3501  SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3502  return DAG.getMergeValues(RetOps, DL);
3503 }
3504 
3505 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3506 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3507 // operations into additions.
3508 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3509  SelectionDAG &DAG) const {
3510  auto *Node = cast<AtomicSDNode>(Op.getNode());
3511  EVT MemVT = Node->getMemoryVT();
3512  if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3513  // A full-width operation.
3514  assert(Op.getValueType() == MemVT && "Mismatched VTs");
3515  SDValue Src2 = Node->getVal();
3516  SDValue NegSrc2;
3517  SDLoc DL(Src2);
3518 
3519  if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3520  // Use an addition if the operand is constant and either LAA(G) is
3521  // available or the negative value is in the range of A(G)FHI.
3522  int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3523  if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3524  NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3525  } else if (Subtarget.hasInterlockedAccess1())
3526  // Use LAA(G) if available.
3527  NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3528  Src2);
3529 
3530  if (NegSrc2.getNode())
3531  return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3532  Node->getChain(), Node->getBasePtr(), NegSrc2,
3533  Node->getMemOperand());
3534 
3535  // Use the node as-is.
3536  return Op;
3537  }
3538 
3539  return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3540 }
3541 
3542 // Lower 8/16/32/64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS node.
3543 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3544  SelectionDAG &DAG) const {
3545  auto *Node = cast<AtomicSDNode>(Op.getNode());
3546  SDValue ChainIn = Node->getOperand(0);
3547  SDValue Addr = Node->getOperand(1);
3548  SDValue CmpVal = Node->getOperand(2);
3549  SDValue SwapVal = Node->getOperand(3);
3550  MachineMemOperand *MMO = Node->getMemOperand();
3551  SDLoc DL(Node);
3552 
3553  // We have native support for 32-bit and 64-bit compare and swap, but we
3554  // still need to expand extracting the "success" result from the CC.
3555  EVT NarrowVT = Node->getMemoryVT();
3556  EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
3557  if (NarrowVT == WideVT) {
3558  SDVTList Tys = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
3559  SDValue Ops[] = { ChainIn, Addr, CmpVal, SwapVal };
3561  DL, Tys, Ops, NarrowVT, MMO);
3562  SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
3564 
3565  DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
3567  DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
3568  return SDValue();
3569  }
3570 
3571  // Convert 8-bit and 16-bit compare and swap to a loop, implemented
3572  // via a fullword ATOMIC_CMP_SWAPW operation.
3573  int64_t BitSize = NarrowVT.getSizeInBits();
3574  EVT PtrVT = Addr.getValueType();
3575 
3576  // Get the address of the containing word.
3577  SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3578  DAG.getConstant(-4, DL, PtrVT));
3579 
3580  // Get the number of bits that the word must be rotated left in order
3581  // to bring the field to the top bits of a GR32.
3582  SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3583  DAG.getConstant(3, DL, PtrVT));
3584  BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3585 
3586  // Get the complementing shift amount, for rotating a field in the top
3587  // bits back to its proper position.
3588  SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3589  DAG.getConstant(0, DL, WideVT), BitShift);
3590 
3591  // Construct the ATOMIC_CMP_SWAPW node.
3592  SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other);
3593  SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3594  NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3596  VTList, Ops, NarrowVT, MMO);
3597  SDValue Success = emitSETCC(DAG, DL, AtomicOp.getValue(1),
3599 
3600  DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), AtomicOp.getValue(0));
3602  DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), AtomicOp.getValue(2));
3603  return SDValue();
3604 }
3605 
3606 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3607  SelectionDAG &DAG) const {
3608  MachineFunction &MF = DAG.getMachineFunction();
3609  MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3610  return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3611  SystemZ::R15D, Op.getValueType());
3612 }
3613 
3614 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3615  SelectionDAG &DAG) const {
3616  MachineFunction &MF = DAG.getMachineFunction();
3617  MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3618  bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
3619 
3620  SDValue Chain = Op.getOperand(0);
3621  SDValue NewSP = Op.getOperand(1);
3622  SDValue Backchain;
3623  SDLoc DL(Op);
3624 
3625  if (StoreBackchain) {
3626  SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
3627  Backchain = DAG.getLoad(MVT::i64, DL, Chain, OldSP, MachinePointerInfo());
3628  }
3629 
3630  Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
3631 
3632  if (StoreBackchain)
3633  Chain = DAG.getStore(Chain, DL, Backchain, NewSP, MachinePointerInfo());
3634 
3635  return Chain;
3636 }
3637 
3638 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3639  SelectionDAG &DAG) const {
3640  bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3641  if (!IsData)
3642  // Just preserve the chain.
3643  return Op.getOperand(0);
3644 
3645  SDLoc DL(Op);
3646  bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3647  unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3648  auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3649  SDValue Ops[] = {
3650  Op.getOperand(0),
3651  DAG.getConstant(Code, DL, MVT::i32),
3652  Op.getOperand(1)
3653  };
3655  Node->getVTList(), Ops,
3656  Node->getMemoryVT(), Node->getMemOperand());
3657 }
3658 
3659 // Convert condition code in CCReg to an i32 value.
3661  SDLoc DL(CCReg);
3662  SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg);
3663  return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3665 }
3666 
3667 SDValue
3668 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3669  SelectionDAG &DAG) const {
3670  unsigned Opcode, CCValid;
3671  if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3672  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3673  SDNode *Node = emitIntrinsicWithCCAndChain(DAG, Op, Opcode);
3674  SDValue CC = getCCResult(DAG, SDValue(Node, 0));
3675  DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3676  return SDValue();
3677  }
3678 
3679  return SDValue();
3680 }
3681 
3682 SDValue
3683 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3684  SelectionDAG &DAG) const {
3685  unsigned Opcode, CCValid;
3686  if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3687  SDNode *Node = emitIntrinsicWithCC(DAG, Op, Opcode);
3688  if (Op->getNumValues() == 1)
3689  return getCCResult(DAG, SDValue(Node, 0));
3690  assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3691  return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
3692  SDValue(Node, 0), getCCResult(DAG, SDValue(Node, 1)));
3693  }
3694 
3695  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3696  switch (Id) {
3697  case Intrinsic::thread_pointer:
3698  return lowerThreadPointer(SDLoc(Op), DAG);
3699 
3700  case Intrinsic::s390_vpdi:
3701  return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3702  Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3703 
3704  case Intrinsic::s390_vperm:
3705  return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3706  Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3707 
3708  case Intrinsic::s390_vuphb:
3709  case Intrinsic::s390_vuphh:
3710  case Intrinsic::s390_vuphf:
3711  return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3712  Op.getOperand(1));
3713 
3714  case Intrinsic::s390_vuplhb:
3715  case Intrinsic::s390_vuplhh:
3716  case Intrinsic::s390_vuplhf:
3717  return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3718  Op.getOperand(1));
3719 
3720  case Intrinsic::s390_vuplb:
3721  case Intrinsic::s390_vuplhw:
3722  case Intrinsic::s390_vuplf:
3723  return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3724  Op.getOperand(1));
3725 
3726  case Intrinsic::s390_vupllb:
3727  case Intrinsic::s390_vupllh:
3728  case Intrinsic::s390_vupllf:
3729  return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3730  Op.getOperand(1));
3731 
3732  case Intrinsic::s390_vsumb:
3733  case Intrinsic::s390_vsumh:
3734  case Intrinsic::s390_vsumgh:
3735  case Intrinsic::s390_vsumgf:
3736  case Intrinsic::s390_vsumqf:
3737  case Intrinsic::s390_vsumqg:
3738  return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3739  Op.getOperand(1), Op.getOperand(2));
3740  }
3741 
3742  return SDValue();
3743 }
3744 
3745 namespace {
3746 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3747 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3748 // Operand is the constant third operand, otherwise it is the number of
3749 // bytes in each element of the result.
3750 struct Permute {
3751  unsigned Opcode;
3752  unsigned Operand;
3753  unsigned char Bytes[SystemZ::VectorBytes];
3754 };
3755 }
3756 
3757 static const Permute PermuteForms[] = {
3758  // VMRHG
3760  { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3761  // VMRHF
3763  { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3764  // VMRHH
3766  { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3767  // VMRHB
3769  { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3770  // VMRLG
3771  { SystemZISD::MERGE_LOW, 8,
3772  { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3773  // VMRLF
3774  { SystemZISD::MERGE_LOW, 4,
3775  { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3776  // VMRLH
3777  { SystemZISD::MERGE_LOW, 2,
3778  { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3779  // VMRLB
3780  { SystemZISD::MERGE_LOW, 1,
3781  { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3782  // VPKG
3783  { SystemZISD::PACK, 4,
3784  { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3785  // VPKF
3786  { SystemZISD::PACK, 2,
3787  { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3788  // VPKH
3789  { SystemZISD::PACK, 1,
3790  { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3791  // VPDI V1, V2, 4 (low half of V1, high half of V2)
3793  { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3794  // VPDI V1, V2, 1 (high half of V1, low half of V2)
3796  { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3797 };
3798 
3799 // Called after matching a vector shuffle against a particular pattern.
3800 // Both the original shuffle and the pattern have two vector operands.
3801 // OpNos[0] is the operand of the original shuffle that should be used for
3802 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3803 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3804 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3805 // for operands 0 and 1 of the pattern.
3806 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3807  if (OpNos[0] < 0) {
3808  if (OpNos[1] < 0)
3809  return false;
3810  OpNo0 = OpNo1 = OpNos[1];
3811  } else if (OpNos[1] < 0) {
3812  OpNo0 = OpNo1 = OpNos[0];
3813  } else {
3814  OpNo0 = OpNos[0];
3815  OpNo1 = OpNos[1];
3816  }
3817  return true;
3818 }
3819 
3820 // Bytes is a VPERM-like permute vector, except that -1 is used for
3821 // undefined bytes. Return true if the VPERM can be implemented using P.
3822 // When returning true set OpNo0 to the VPERM operand that should be
3823 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3824 //
3825 // For example, if swapping the VPERM operands allows P to match, OpNo0
3826 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3827 // operand, but rewriting it to use two duplicated operands allows it to
3828 // match P, then OpNo0 and OpNo1 will be the same.
3829 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3830  unsigned &OpNo0, unsigned &OpNo1) {
3831  int OpNos[] = { -1, -1 };
3832  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3833  int Elt = Bytes[I];
3834  if (Elt >= 0) {
3835  // Make sure that the two permute vectors use the same suboperand
3836  // byte number. Only the operand numbers (the high bits) are
3837  // allowed to differ.
3838  if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3839  return false;
3840  int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3841  int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3842  // Make sure that the operand mappings are consistent with previous
3843  // elements.
3844  if (OpNos[ModelOpNo] == 1 - RealOpNo)
3845  return false;
3846  OpNos[ModelOpNo] = RealOpNo;
3847  }
3848  }
3849  return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3850 }
3851 
3852 // As above, but search for a matching permute.
3853 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3854  unsigned &OpNo0, unsigned &OpNo1) {
3855  for (auto &P : PermuteForms)
3856  if (matchPermute(Bytes, P, OpNo0, OpNo1))
3857  return &P;
3858  return nullptr;
3859 }
3860 
3861 // Bytes is a VPERM-like permute vector, except that -1 is used for
3862 // undefined bytes. This permute is an operand of an outer permute.
3863 // See whether redistributing the -1 bytes gives a shuffle that can be
3864 // implemented using P. If so, set Transform to a VPERM-like permute vector
3865 // that, when applied to the result of P, gives the original permute in Bytes.
3866 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3867  const Permute &P,
3868  SmallVectorImpl<int> &Transform) {
3869  unsigned To = 0;
3870  for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3871  int Elt = Bytes[From];
3872  if (Elt < 0)
3873  // Byte number From of the result is undefined.
3874  Transform[From] = -1;
3875  else {
3876  while (P.Bytes[To] != Elt) {
3877  To += 1;
3878  if (To == SystemZ::VectorBytes)
3879  return false;
3880  }
3881  Transform[From] = To;
3882  }
3883  }
3884  return true;
3885 }
3886 
3887 // As above, but search for a matching permute.
3888 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3889  SmallVectorImpl<int> &Transform) {
3890  for (auto &P : PermuteForms)
3891  if (matchDoublePermute(Bytes, P, Transform))
3892  return &P;
3893  return nullptr;
3894 }
3895 
3896 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3897 // as if it had type vNi8.
3899  SmallVectorImpl<int> &Bytes) {
3900  EVT VT = VSN->getValueType(0);
3901  unsigned NumElements = VT.getVectorNumElements();
3902  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3903  Bytes.resize(NumElements * BytesPerElement, -1);
3904  for (unsigned I = 0; I < NumElements; ++I) {
3905  int Index = VSN->getMaskElt(I);
3906  if (Index >= 0)
3907  for (unsigned J = 0; J < BytesPerElement; ++J)
3908  Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3909  }
3910 }
3911 
3912 // Bytes is a VPERM-like permute vector, except that -1 is used for
3913 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3914 // the result come from a contiguous sequence of bytes from one input.
3915 // Set Base to the selector for the first byte if so.
3916 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3917  unsigned BytesPerElement, int &Base) {
3918  Base = -1;
3919  for (unsigned I = 0; I < BytesPerElement; ++I) {
3920  if (Bytes[Start + I] >= 0) {
3921  unsigned Elem = Bytes[Start + I];
3922  if (Base < 0) {
3923  Base = Elem - I;
3924  // Make sure the bytes would come from one input operand.
3925  if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3926  return false;
3927  } else if (unsigned(Base) != Elem - I)
3928  return false;
3929  }
3930  }
3931  return true;
3932 }
3933 
3934 // Bytes is a VPERM-like permute vector, except that -1 is used for
3935 // undefined bytes. Return true if it can be performed using VSLDI.
3936 // When returning true, set StartIndex to the shift amount and OpNo0
3937 // and OpNo1 to the VPERM operands that should be used as the first
3938 // and second shift operand respectively.
3939 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3940  unsigned &StartIndex, unsigned &OpNo0,
3941  unsigned &OpNo1) {
3942  int OpNos[] = { -1, -1 };
3943  int Shift = -1;
3944  for (unsigned I = 0; I < 16; ++I) {
3945  int Index = Bytes[I];
3946  if (Index >= 0) {
3947  int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3948  int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3949  int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3950  if (Shift < 0)
3951  Shift = ExpectedShift;
3952  else if (Shift != ExpectedShift)
3953  return false;
3954  // Make sure that the operand mappings are consistent with previous
3955  // elements.
3956  if (OpNos[ModelOpNo] == 1 - RealOpNo)
3957  return false;
3958  OpNos[ModelOpNo] = RealOpNo;
3959  }
3960  }
3961  StartIndex = Shift;
3962  return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3963 }
3964 
3965 // Create a node that performs P on operands Op0 and Op1, casting the
3966 // operands to the appropriate type. The type of the result is determined by P.
3967 static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
3968  const Permute &P, SDValue Op0, SDValue Op1) {
3969  // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3970  // elements of a PACK are twice as wide as the outputs.
3971  unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3972  P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3973  P.Operand);
3974  // Cast both operands to the appropriate type.
3975  MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3976  SystemZ::VectorBytes / InBytes);
3977  Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3978  Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3979  SDValue Op;
3980  if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3981  SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3982  Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3983  } else if (P.Opcode == SystemZISD::PACK) {
3984  MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3985  SystemZ::VectorBytes / P.Operand);
3986  Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3987  } else {
3988  Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3989  }
3990  return Op;
3991 }
3992 
3993 // Bytes is a VPERM-like permute vector, except that -1 is used for
3994 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3995 // VSLDI or VPERM.
3997  SDValue *Ops,
3998  const SmallVectorImpl<int> &Bytes) {
3999  for (unsigned I = 0; I < 2; ++I)
4000  Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
4001 
4002  // First see whether VSLDI can be used.
4003  unsigned StartIndex, OpNo0, OpNo1;
4004  if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
4005  return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
4006  Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
4007 
4008  // Fall back on VPERM. Construct an SDNode for the permute vector.
4009  SDValue IndexNodes[SystemZ::VectorBytes];
4010  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4011  if (Bytes[I] >= 0)
4012  IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
4013  else
4014  IndexNodes[I] = DAG.getUNDEF(MVT::i32);
4015  SDValue Op2 = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
4016  return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
4017 }
4018 
4019 namespace {
4020 // Describes a general N-operand vector shuffle.
4021 struct GeneralShuffle {
4022  GeneralShuffle(EVT vt) : VT(vt) {}
4023  void addUndef();
4024  bool add(SDValue, unsigned);
4025  SDValue getNode(SelectionDAG &, const SDLoc &);
4026 
4027  // The operands of the shuffle.
4029 
4030  // Index I is -1 if byte I of the result is undefined. Otherwise the
4031  // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
4032  // Bytes[I] / SystemZ::VectorBytes.
4034 
4035  // The type of the shuffle result.
4036  EVT VT;
4037 };
4038 }
4039 
4040 // Add an extra undefined element to the shuffle.
4041 void GeneralShuffle::addUndef() {
4042  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
4043  for (unsigned I = 0; I < BytesPerElement; ++I)
4044  Bytes.push_back(-1);
4045 }
4046 
4047 // Add an extra element to the shuffle, taking it from element Elem of Op.
4048 // A null Op indicates a vector input whose value will be calculated later;
4049 // there is at most one such input per shuffle and it always has the same
4050 // type as the result. Aborts and returns false if the source vector elements
4051 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
4052 // LLVM they become implicitly extended, but this is rare and not optimized.
4053 bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
4054  unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
4055 
4056  // The source vector can have wider elements than the result,
4057  // either through an explicit TRUNCATE or because of type legalization.
4058  // We want the least significant part.
4059  EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
4060  unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
4061 
4062  // Return false if the source elements are smaller than their destination
4063  // elements.
4064  if (FromBytesPerElement < BytesPerElement)
4065  return false;
4066 
4067  unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
4068  (FromBytesPerElement - BytesPerElement));
4069 
4070  // Look through things like shuffles and bitcasts.
4071  while (Op.getNode()) {
4072  if (Op.getOpcode() == ISD::BITCAST)
4073  Op = Op.getOperand(0);
4074  else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
4075  // See whether the bytes we need come from a contiguous part of one
4076  // operand.
4078  getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
4079  int NewByte;
4080  if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
4081  break;
4082  if (NewByte < 0) {
4083  addUndef();
4084  return true;
4085  }
4086  Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
4087  Byte = unsigned(NewByte) % SystemZ::VectorBytes;
4088  } else if (Op.isUndef()) {
4089  addUndef();
4090  return true;
4091  } else
4092  break;
4093  }
4094 
4095  // Make sure that the source of the extraction is in Ops.
4096  unsigned OpNo = 0;
4097  for (; OpNo < Ops.size(); ++OpNo)
4098  if (Ops[OpNo] == Op)
4099  break;
4100  if (OpNo == Ops.size())
4101  Ops.push_back(Op);
4102 
4103  // Add the element to Bytes.
4104  unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
4105  for (unsigned I = 0; I < BytesPerElement; ++I)
4106  Bytes.push_back(Base + I);
4107 
4108  return true;
4109 }
4110 
4111 // Return SDNodes for the completed shuffle.
4112 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
4113  assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
4114 
4115  if (Ops.size() == 0)
4116  return DAG.getUNDEF(VT);
4117 
4118  // Make sure that there are at least two shuffle operands.
4119  if (Ops.size() == 1)
4120  Ops.push_back(DAG.getUNDEF(MVT::v16i8));
4121 
4122  // Create a tree of shuffles, deferring root node until after the loop.
4123  // Try to redistribute the undefined elements of non-root nodes so that
4124  // the non-root shuffles match something like a pack or merge, then adjust
4125  // the parent node's permute vector to compensate for the new order.
4126  // Among other things, this copes with vectors like <2 x i16> that were
4127  // padded with undefined elements during type legalization.
4128  //
4129  // In the best case this redistribution will lead to the whole tree
4130  // using packs and merges. It should rarely be a loss in other cases.
4131  unsigned Stride = 1;
4132  for (; Stride * 2 < Ops.size(); Stride *= 2) {
4133  for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
4134  SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
4135 
4136  // Create a mask for just these two operands.
4138  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4139  unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
4140  unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
4141  if (OpNo == I)
4142  NewBytes[J] = Byte;
4143  else if (OpNo == I + Stride)
4144  NewBytes[J] = SystemZ::VectorBytes + Byte;
4145  else
4146  NewBytes[J] = -1;
4147  }
4148  // See if it would be better to reorganize NewMask to avoid using VPERM.
4149  SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
4150  if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
4151  Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
4152  // Applying NewBytesMap to Ops[I] gets back to NewBytes.
4153  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
4154  if (NewBytes[J] >= 0) {
4155  assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
4156  "Invalid double permute");
4157  Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
4158  } else
4159  assert(NewBytesMap[J] < 0 && "Invalid double permute");
4160  }
4161  } else {
4162  // Just use NewBytes on the operands.
4163  Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
4164  for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
4165  if (NewBytes[J] >= 0)
4166  Bytes[J] = I * SystemZ::VectorBytes + J;
4167  }
4168  }
4169  }
4170 
4171  // Now we just have 2 inputs. Put the second operand in Ops[1].
4172  if (Stride > 1) {
4173  Ops[1] = Ops[Stride];
4174  for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
4175  if (Bytes[I] >= int(SystemZ::VectorBytes))
4176  Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
4177  }
4178 
4179  // Look for an instruction that can do the permute without resorting
4180  // to VPERM.
4181  unsigned OpNo0, OpNo1;
4182  SDValue Op;
4183  if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
4184  Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
4185  else
4186  Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
4187  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4188 }
4189 
4190 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
4191 static bool isScalarToVector(SDValue Op) {
4192  for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
4193  if (!Op.getOperand(I).isUndef())
4194  return false;
4195  return true;
4196 }
4197 
4198 // Return a vector of type VT that contains Value in the first element.
4199 // The other elements don't matter.
4200 static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4201  SDValue Value) {
4202  // If we have a constant, replicate it to all elements and let the
4203  // BUILD_VECTOR lowering take care of it.
4204  if (Value.getOpcode() == ISD::Constant ||
4205  Value.getOpcode() == ISD::ConstantFP) {
4207  return DAG.getBuildVector(VT, DL, Ops);
4208  }
4209  if (Value.isUndef())
4210  return DAG.getUNDEF(VT);
4211  return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4212 }
4213 
4214 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
4215 // element 1. Used for cases in which replication is cheap.
4216 static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4217  SDValue Op0, SDValue Op1) {
4218  if (Op0.isUndef()) {
4219  if (Op1.isUndef())
4220  return DAG.getUNDEF(VT);
4221  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
4222  }
4223  if (Op1.isUndef())
4224  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
4225  return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
4226  buildScalarToVector(DAG, DL, VT, Op0),
4227  buildScalarToVector(DAG, DL, VT, Op1));
4228 }
4229 
4230 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4231 // vector for them.
4232 static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
4233  SDValue Op1) {
4234  if (Op0.isUndef() && Op1.isUndef())
4235  return DAG.getUNDEF(MVT::v2i64);
4236  // If one of the two inputs is undefined then replicate the other one,
4237  // in order to avoid using another register unnecessarily.
4238  if (Op0.isUndef())
4239  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4240  else if (Op1.isUndef())
4241  Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4242  else {
4243  Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
4244  Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
4245  }
4246  return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
4247 }
4248 
4249 // Try to represent constant BUILD_VECTOR node BVN using a
4250 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
4251 // on success.
4252 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
4253  EVT ElemVT = BVN->getValueType(0).getVectorElementType();
4254  unsigned BytesPerElement = ElemVT.getStoreSize();
4255  for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
4256  SDValue Op = BVN->getOperand(I);
4257  if (!Op.isUndef()) {
4258  uint64_t Value;
4259  if (Op.getOpcode() == ISD::Constant)
4260  Value = cast<ConstantSDNode>(Op)->getZExtValue();
4261  else if (Op.getOpcode() == ISD::ConstantFP)
4262  Value = (cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
4263  .getZExtValue());
4264  else
4265  return false;
4266  for (unsigned J = 0; J < BytesPerElement; ++J) {
4267  uint64_t Byte = (Value >> (J * 8)) & 0xff;
4268  if (Byte == 0xff)
4269  Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
4270  else if (Byte != 0)
4271  return false;
4272  }
4273  }
4274  }
4275  return true;
4276 }
4277 
4278 // Try to load a vector constant in which BitsPerElement-bit value Value
4279 // is replicated to fill the vector. VT is the type of the resulting
4280 // constant, which may have elements of a different size from BitsPerElement.
4281 // Return the SDValue of the constant on success, otherwise return
4282 // an empty value.
4284  const SystemZInstrInfo *TII,
4285  const SDLoc &DL, EVT VT, uint64_t Value,
4286  unsigned BitsPerElement) {
4287  // Signed 16-bit values can be replicated using VREPI.
4288  // Mark the constants as opaque or DAGCombiner will convert back to
4289  // BUILD_VECTOR.
4290  int64_t SignedValue = SignExtend64(Value, BitsPerElement);
4291  if (isInt<16>(SignedValue)) {
4292  MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4293  SystemZ::VectorBits / BitsPerElement);
4294  SDValue Op = DAG.getNode(
4295  SystemZISD::REPLICATE, DL, VecVT,
4296  DAG.getConstant(SignedValue, DL, MVT::i32, false, true /*isOpaque*/));
4297  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4298  }
4299  // See whether rotating the constant left some N places gives a value that
4300  // is one less than a power of 2 (i.e. all zeros followed by all ones).
4301  // If so we can use VGM.
4302  unsigned Start, End;
4303  if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
4304  // isRxSBGMask returns the bit numbers for a full 64-bit value,
4305  // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
4306  // bit numbers for an BitsPerElement value, so that 0 denotes
4307  // 1 << (BitsPerElement-1).
4308  Start -= 64 - BitsPerElement;
4309  End -= 64 - BitsPerElement;
4310  MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
4311  SystemZ::VectorBits / BitsPerElement);
4312  SDValue Op = DAG.getNode(
4313  SystemZISD::ROTATE_MASK, DL, VecVT,
4314  DAG.getConstant(Start, DL, MVT::i32, false, true /*isOpaque*/),
4315  DAG.getConstant(End, DL, MVT::i32, false, true /*isOpaque*/));
4316  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4317  }
4318  return SDValue();
4319 }
4320 
4321 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
4322 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
4323 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4324 // would benefit from this representation and return it if so.
4326  BuildVectorSDNode *BVN) {
4327  EVT VT = BVN->getValueType(0);
4328  unsigned NumElements = VT.getVectorNumElements();
4329 
4330  // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
4331  // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4332  // need a BUILD_VECTOR, add an additional placeholder operand for that
4333  // BUILD_VECTOR and store its operands in ResidueOps.
4334  GeneralShuffle GS(VT);
4336  bool FoundOne = false;
4337  for (unsigned I = 0; I < NumElements; ++I) {
4338  SDValue Op = BVN->getOperand(I);
4339  if (Op.getOpcode() == ISD::TRUNCATE)
4340  Op = Op.getOperand(0);
4341  if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4342  Op.getOperand(1).getOpcode() == ISD::Constant) {
4343  unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4344  if (!GS.add(Op.getOperand(0), Elem))
4345  return SDValue();
4346  FoundOne = true;
4347  } else if (Op.isUndef()) {
4348  GS.addUndef();
4349  } else {
4350  if (!GS.add(SDValue(), ResidueOps.size()))
4351  return SDValue();
4352  ResidueOps.push_back(BVN->getOperand(I));
4353  }
4354  }
4355 
4356  // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
4357  if (!FoundOne)
4358  return SDValue();
4359 
4360  // Create the BUILD_VECTOR for the remaining elements, if any.
4361  if (!ResidueOps.empty()) {
4362  while (ResidueOps.size() < NumElements)
4363  ResidueOps.push_back(DAG.getUNDEF(ResidueOps[0].getValueType()));
4364  for (auto &Op : GS.Ops) {
4365  if (!Op.getNode()) {
4366  Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4367  break;
4368  }
4369  }
4370  }
4371  return GS.getNode(DAG, SDLoc(BVN));
4372 }
4373 
4374 // Combine GPR scalar values Elems into a vector of type VT.
4375 static SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
4376  SmallVectorImpl<SDValue> &Elems) {
4377  // See whether there is a single replicated value.
4378  SDValue Single;
4379  unsigned int NumElements = Elems.size();
4380  unsigned int Count = 0;
4381  for (auto Elem : Elems) {
4382  if (!Elem.isUndef()) {
4383  if (!Single.getNode())
4384  Single = Elem;
4385  else if (Elem != Single) {
4386  Single = SDValue();
4387  break;
4388  }
4389  Count += 1;
4390  }
4391  }
4392  // There are three cases here:
4393  //
4394  // - if the only defined element is a loaded one, the best sequence
4395  // is a replicating load.
4396  //
4397  // - otherwise, if the only defined element is an i64 value, we will
4398  // end up with the same VLVGP sequence regardless of whether we short-cut
4399  // for replication or fall through to the later code.
4400  //
4401  // - otherwise, if the only defined element is an i32 or smaller value,
4402  // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
4403  // This is only a win if the single defined element is used more than once.
4404  // In other cases we're better off using a single VLVGx.
4405  if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
4406  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
4407 
4408  // If all elements are loads, use VLREP/VLEs (below).
4409  bool AllLoads = true;
4410  for (auto Elem : Elems)
4411  if (Elem.getOpcode() != ISD::LOAD || cast<LoadSDNode>(Elem)->isIndexed()) {
4412  AllLoads = false;
4413  break;
4414  }
4415 
4416  // The best way of building a v2i64 from two i64s is to use VLVGP.
4417  if (VT == MVT::v2i64 && !AllLoads)
4418  return joinDwords(DAG, DL, Elems[0], Elems[1]);
4419 
4420  // Use a 64-bit merge high to combine two doubles.
4421  if (VT == MVT::v2f64 && !AllLoads)
4422  return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4423 
4424  // Build v4f32 values directly from the FPRs:
4425  //
4426  // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
4427  // V V VMRHF
4428  // <ABxx> <CDxx>
4429  // V VMRHG
4430  // <ABCD>
4431  if (VT == MVT::v4f32 && !AllLoads) {
4432  SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
4433  SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
4434  // Avoid unnecessary undefs by reusing the other operand.
4435  if (Op01.isUndef())
4436  Op01 = Op23;
4437  else if (Op23.isUndef())
4438  Op23 = Op01;
4439  // Merging identical replications is a no-op.
4440  if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
4441  return Op01;
4442  Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
4443  Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
4445  DL, MVT::v2i64, Op01, Op23);
4446  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4447  }
4448 
4449  // Collect the constant terms.
4451  SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
4452 
4453  unsigned NumConstants = 0;
4454  for (unsigned I = 0; I < NumElements; ++I) {
4455  SDValue Elem = Elems[I];
4456  if (Elem.getOpcode() == ISD::Constant ||
4457  Elem.getOpcode() == ISD::ConstantFP) {
4458  NumConstants += 1;
4459  Constants[I] = Elem;
4460  Done[I] = true;
4461  }
4462  }
4463  // If there was at least one constant, fill in the other elements of
4464  // Constants with undefs to get a full vector constant and use that
4465  // as the starting point.
4466  SDValue Result;
4467  if (NumConstants > 0) {
4468  for (unsigned I = 0; I < NumElements; ++I)
4469  if (!Constants[I].getNode())
4470  Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
4471  Result = DAG.getBuildVector(VT, DL, Constants);
4472  } else {
4473  // Otherwise try to use VLREP or VLVGP to start the sequence in order to
4474  // avoid a false dependency on any previous contents of the vector
4475  // register.
4476 
4477  // Use a VLREP if at least one element is a load.
4478  unsigned LoadElIdx = UINT_MAX;
4479  for (unsigned I = 0; I < NumElements; ++I)
4480  if (Elems[I].getOpcode() == ISD::LOAD &&
4481  cast<LoadSDNode>(Elems[I])->isUnindexed()) {
4482  LoadElIdx = I;
4483  break;
4484  }
4485  if (LoadElIdx != UINT_MAX) {
4486  Result = DAG.getNode(SystemZISD::REPLICATE, DL, VT, Elems[LoadElIdx]);
4487  Done[LoadElIdx] = true;
4488  } else {
4489  // Try to use VLVGP.
4490  unsigned I1 = NumElements / 2 - 1;
4491  unsigned I2 = NumElements - 1;
4492  bool Def1 = !Elems[I1].isUndef();
4493  bool Def2 = !Elems[I2].isUndef();
4494  if (Def1 || Def2) {
4495  SDValue Elem1 = Elems[Def1 ? I1 : I2];
4496  SDValue Elem2 = Elems[Def2 ? I2 : I1];
4497  Result = DAG.getNode(ISD::BITCAST, DL, VT,
4498  joinDwords(DAG, DL, Elem1, Elem2));
4499  Done[I1] = true;
4500  Done[I2] = true;
4501  } else
4502  Result = DAG.getUNDEF(VT);
4503  }
4504  }
4505 
4506  // Use VLVGx to insert the other elements.
4507  for (unsigned I = 0; I < NumElements; ++I)
4508  if (!Done[I] && !Elems[I].isUndef())
4509  Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4510  DAG.getConstant(I, DL, MVT::i32));
4511  return Result;
4512 }
4513 
4514 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4515  SelectionDAG &DAG) const {
4516  const SystemZInstrInfo *TII =
4517  static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4518  auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4519  SDLoc DL(Op);
4520  EVT VT = Op.getValueType();
4521 
4522  if (BVN->isConstant()) {
4523  // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4524  // preferred way of creating all-zero and all-one vectors so give it
4525  // priority over other methods below.
4526  uint64_t Mask = 0;
4527  if (tryBuildVectorByteMask(BVN, Mask)) {
4528  SDValue Op = DAG.getNode(
4530  DAG.getConstant(Mask, DL, MVT::i32, false, true /*isOpaque*/));
4531  return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4532  }
4533 
4534  // Try using some form of replication.
4535  APInt SplatBits, SplatUndef;
4536  unsigned SplatBitSize;
4537  bool HasAnyUndefs;
4538  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4539  8, true) &&
4540  SplatBitSize <= 64) {
4541  // First try assuming that any undefined bits above the highest set bit
4542  // and below the lowest set bit are 1s. This increases the likelihood of
4543  // being able to use a sign-extended element value in VECTOR REPLICATE
4544  // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4545  uint64_t SplatBitsZ = SplatBits.getZExtValue();
4546  uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4547  uint64_t Lower = (SplatUndefZ
4548  & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4549  uint64_t Upper = (SplatUndefZ
4550  & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4551  uint64_t Value = SplatBitsZ | Upper | Lower;
4552  SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4553  SplatBitSize);
4554  if (Op.getNode())
4555  return Op;
4556 
4557  // Now try assuming that any undefined bits between the first and
4558  // last defined set bits are set. This increases the chances of
4559  // using a non-wraparound mask.
4560  uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4561  Value = SplatBitsZ | Middle;
4562  Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4563  if (Op.getNode())
4564  return Op;
4565  }
4566 
4567  // Fall back to loading it from memory.
4568  return SDValue();
4569  }
4570 
4571  // See if we should use shuffles to construct the vector from other vectors.
4572  if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
4573  return Res;
4574 
4575  // Detect SCALAR_TO_VECTOR conversions.
4577  return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4578 
4579  // Otherwise use buildVector to build the vector up from GPRs.
4580  unsigned NumElements = Op.getNumOperands();
4582  for (unsigned I = 0; I < NumElements; ++I)
4583  Ops[I] = Op.getOperand(I);
4584  return buildVector(DAG, DL, VT, Ops);
4585 }
4586 
4587 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4588  SelectionDAG &DAG) const {
4589  auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4590  SDLoc DL(Op);
4591  EVT VT = Op.getValueType();
4592  unsigned NumElements = VT.getVectorNumElements();
4593 
4594  if (VSN->isSplat()) {
4595  SDValue Op0 = Op.getOperand(0);
4596  unsigned Index = VSN->getSplatIndex();
4597  assert(Index < VT.getVectorNumElements() &&
4598  "Splat index should be defined and in first operand");
4599  // See whether the value we're splatting is directly available as a scalar.
4600  if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4601  Op0.getOpcode() == ISD::BUILD_VECTOR)
4602  return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4603  // Otherwise keep it as a vector-to-vector operation.
4604  return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4605  DAG.getConstant(Index, DL, MVT::i32));
4606  }
4607 
4608  GeneralShuffle GS(VT);
4609  for (unsigned I = 0; I < NumElements; ++I) {
4610  int Elt = VSN->getMaskElt(I);
4611  if (Elt < 0)
4612  GS.addUndef();
4613  else if (!GS.add(Op.getOperand</