LLVM  8.0.0svn
SystemZMCTargetDesc.h
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1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
12 
13 #include "llvm/Support/DataTypes.h"
14 
15 #include <memory>
16 
17 namespace llvm {
18 
19 class MCAsmBackend;
20 class MCCodeEmitter;
21 class MCContext;
22 class MCInstrInfo;
23 class MCObjectTargetWriter;
24 class MCRegisterInfo;
25 class MCSubtargetInfo;
26 class MCTargetOptions;
27 class StringRef;
28 class Target;
29 class Triple;
30 class raw_pwrite_stream;
31 class raw_ostream;
32 
33 Target &getTheSystemZTarget();
34 
35 namespace SystemZMC {
36 // How many bytes are in the ABI-defined, caller-allocated part of
37 // a stack frame.
38 const int64_t CallFrameSize = 160;
39 
40 // The offset of the DWARF CFA from the incoming stack pointer.
42 
43 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
44 // an invalid register. In principle we could use 32-bit and 64-bit register
45 // classes directly, provided that we relegated the GPR allocation order
46 // in SystemZRegisterInfo.td to an AltOrder and left the default order
47 // as %r0-%r15. It seems better to provide the same interface for
48 // all classes though.
49 extern const unsigned GR32Regs[16];
50 extern const unsigned GRH32Regs[16];
51 extern const unsigned GR64Regs[16];
52 extern const unsigned GR128Regs[16];
53 extern const unsigned FP32Regs[16];
54 extern const unsigned FP64Regs[16];
55 extern const unsigned FP128Regs[16];
56 extern const unsigned VR32Regs[32];
57 extern const unsigned VR64Regs[32];
58 extern const unsigned VR128Regs[32];
59 extern const unsigned AR32Regs[16];
60 extern const unsigned CR64Regs[16];
61 
62 // Return the 0-based number of the first architectural register that
63 // contains the given LLVM register. E.g. R1D -> 1.
64 unsigned getFirstReg(unsigned Reg);
65 
66 // Return the given register as a GR64.
67 inline unsigned getRegAsGR64(unsigned Reg) {
68  return GR64Regs[getFirstReg(Reg)];
69 }
70 
71 // Return the given register as a low GR32.
72 inline unsigned getRegAsGR32(unsigned Reg) {
73  return GR32Regs[getFirstReg(Reg)];
74 }
75 
76 // Return the given register as a high GR32.
77 inline unsigned getRegAsGRH32(unsigned Reg) {
78  return GRH32Regs[getFirstReg(Reg)];
79 }
80 
81 // Return the given register as a VR128.
82 inline unsigned getRegAsVR128(unsigned Reg) {
83  return VR128Regs[getFirstReg(Reg)];
84 }
85 } // end namespace SystemZMC
86 
88  const MCRegisterInfo &MRI,
89  MCContext &Ctx);
90 
92  const MCSubtargetInfo &STI,
93  const MCRegisterInfo &MRI,
94  const MCTargetOptions &Options);
95 
96 std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI);
97 } // end namespace llvm
98 
99 // Defines symbolic names for SystemZ registers.
100 // This defines a mapping from register name to register number.
101 #define GET_REGINFO_ENUM
102 #include "SystemZGenRegisterInfo.inc"
103 
104 // Defines symbolic names for the SystemZ instructions.
105 #define GET_INSTRINFO_ENUM
106 #include "SystemZGenInstrInfo.inc"
107 
108 #define GET_SUBTARGETINFO_ENUM
109 #include "SystemZGenSubtargetInfo.inc"
110 
111 #endif
const unsigned GR32Regs[16]
const int64_t CallFrameSize
unsigned getFirstReg(unsigned Reg)
This class represents lattice values for constants.
Definition: AllocatorList.h:24
const unsigned FP128Regs[16]
unsigned Reg
const unsigned FP32Regs[16]
const unsigned VR64Regs[32]
unsigned getRegAsGRH32(unsigned Reg)
const unsigned AR32Regs[16]
unsigned getRegAsGR32(unsigned Reg)
std::unique_ptr< MCObjectTargetWriter > createSystemZObjectWriter(uint8_t OSABI)
const unsigned GRH32Regs[16]
Context object for machine code objects.
Definition: MCContext.h:63
const unsigned CR64Regs[16]
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
const int64_t CFAOffsetFromInitialSP
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
const unsigned FP64Regs[16]
const unsigned GR128Regs[16]
unsigned getRegAsGR64(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
const unsigned GR64Regs[16]
Target - Wrapper for Target specific information.
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheSystemZTarget()
Generic base class for all target subtargets.
const unsigned VR32Regs[32]
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
const unsigned VR128Regs[32]