LLVM  9.0.0svn
SystemZMCTargetDesc.h
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1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
10 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11 
12 #include "llvm/Support/DataTypes.h"
13 
14 #include <memory>
15 
16 namespace llvm {
17 
18 class MCAsmBackend;
19 class MCCodeEmitter;
20 class MCContext;
21 class MCInstrInfo;
22 class MCObjectTargetWriter;
23 class MCRegisterInfo;
24 class MCSubtargetInfo;
25 class MCTargetOptions;
26 class StringRef;
27 class Target;
28 class Triple;
29 class raw_pwrite_stream;
30 class raw_ostream;
31 
32 Target &getTheSystemZTarget();
33 
34 namespace SystemZMC {
35 // How many bytes are in the ABI-defined, caller-allocated part of
36 // a stack frame.
37 const int64_t CallFrameSize = 160;
38 
39 // The offset of the DWARF CFA from the incoming stack pointer.
41 
42 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
43 // an invalid register. In principle we could use 32-bit and 64-bit register
44 // classes directly, provided that we relegated the GPR allocation order
45 // in SystemZRegisterInfo.td to an AltOrder and left the default order
46 // as %r0-%r15. It seems better to provide the same interface for
47 // all classes though.
48 extern const unsigned GR32Regs[16];
49 extern const unsigned GRH32Regs[16];
50 extern const unsigned GR64Regs[16];
51 extern const unsigned GR128Regs[16];
52 extern const unsigned FP32Regs[16];
53 extern const unsigned FP64Regs[16];
54 extern const unsigned FP128Regs[16];
55 extern const unsigned VR32Regs[32];
56 extern const unsigned VR64Regs[32];
57 extern const unsigned VR128Regs[32];
58 extern const unsigned AR32Regs[16];
59 extern const unsigned CR64Regs[16];
60 
61 // Return the 0-based number of the first architectural register that
62 // contains the given LLVM register. E.g. R1D -> 1.
63 unsigned getFirstReg(unsigned Reg);
64 
65 // Return the given register as a GR64.
66 inline unsigned getRegAsGR64(unsigned Reg) {
67  return GR64Regs[getFirstReg(Reg)];
68 }
69 
70 // Return the given register as a low GR32.
71 inline unsigned getRegAsGR32(unsigned Reg) {
72  return GR32Regs[getFirstReg(Reg)];
73 }
74 
75 // Return the given register as a high GR32.
76 inline unsigned getRegAsGRH32(unsigned Reg) {
77  return GRH32Regs[getFirstReg(Reg)];
78 }
79 
80 // Return the given register as a VR128.
81 inline unsigned getRegAsVR128(unsigned Reg) {
82  return VR128Regs[getFirstReg(Reg)];
83 }
84 } // end namespace SystemZMC
85 
87  const MCRegisterInfo &MRI,
88  MCContext &Ctx);
89 
91  const MCSubtargetInfo &STI,
92  const MCRegisterInfo &MRI,
93  const MCTargetOptions &Options);
94 
95 std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI);
96 } // end namespace llvm
97 
98 // Defines symbolic names for SystemZ registers.
99 // This defines a mapping from register name to register number.
100 #define GET_REGINFO_ENUM
101 #include "SystemZGenRegisterInfo.inc"
102 
103 // Defines symbolic names for the SystemZ instructions.
104 #define GET_INSTRINFO_ENUM
105 #include "SystemZGenInstrInfo.inc"
106 
107 #define GET_SUBTARGETINFO_ENUM
108 #include "SystemZGenSubtargetInfo.inc"
109 
110 #endif
const unsigned GR32Regs[16]
const int64_t CallFrameSize
unsigned getFirstReg(unsigned Reg)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const unsigned FP128Regs[16]
unsigned Reg
const unsigned FP32Regs[16]
const unsigned VR64Regs[32]
unsigned getRegAsGRH32(unsigned Reg)
const unsigned AR32Regs[16]
unsigned getRegAsGR32(unsigned Reg)
std::unique_ptr< MCObjectTargetWriter > createSystemZObjectWriter(uint8_t OSABI)
const unsigned GRH32Regs[16]
Context object for machine code objects.
Definition: MCContext.h:62
const unsigned CR64Regs[16]
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
const int64_t CFAOffsetFromInitialSP
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const unsigned FP64Regs[16]
const unsigned GR128Regs[16]
unsigned getRegAsGR64(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
const unsigned GR64Regs[16]
Target - Wrapper for Target specific information.
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheSystemZTarget()
Generic base class for all target subtargets.
const unsigned VR32Regs[32]
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
const unsigned VR128Regs[32]