LLVM  9.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::Legalize method.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Metadata.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <cassert>
49 #include <cstdint>
50 #include <tuple>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "legalizedag"
56 
57 namespace {
58 
59 /// Keeps track of state when getting the sign of a floating-point value as an
60 /// integer.
61 struct FloatSignAsInt {
62  EVT FloatVT;
63  SDValue Chain;
64  SDValue FloatPtr;
65  SDValue IntPtr;
66  MachinePointerInfo IntPointerInfo;
67  MachinePointerInfo FloatPointerInfo;
68  SDValue IntValue;
69  APInt SignMask;
70  uint8_t SignBit;
71 };
72 
73 //===----------------------------------------------------------------------===//
74 /// This takes an arbitrary SelectionDAG as input and
75 /// hacks on it until the target machine can handle it. This involves
76 /// eliminating value sizes the machine cannot handle (promoting small sizes to
77 /// large sizes or splitting up large values into small values) as well as
78 /// eliminating operations the machine cannot handle.
79 ///
80 /// This code also does a small amount of optimization and recognition of idioms
81 /// as part of its processing. For example, if a target does not support a
82 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
83 /// will attempt merge setcc and brc instructions into brcc's.
84 class SelectionDAGLegalize {
85  const TargetMachine &TM;
86  const TargetLowering &TLI;
87  SelectionDAG &DAG;
88 
89  /// The set of nodes which have already been legalized. We hold a
90  /// reference to it in order to update as necessary on node deletion.
91  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
92 
93  /// A set of all the nodes updated during legalization.
94  SmallSetVector<SDNode *, 16> *UpdatedNodes;
95 
96  EVT getSetCCResultType(EVT VT) const {
97  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
98  }
99 
100  // Libcall insertion helpers.
101 
102 public:
103  SelectionDAGLegalize(SelectionDAG &DAG,
104  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
105  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
106  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
107  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
108 
109  /// Legalizes the given operation.
110  void LegalizeOp(SDNode *Node);
111 
112 private:
113  SDValue OptimizeFloatStore(StoreSDNode *ST);
114 
115  void LegalizeLoadOps(SDNode *Node);
116  void LegalizeStoreOps(SDNode *Node);
117 
118  /// Some targets cannot handle a variable
119  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
120  /// is necessary to spill the vector being inserted into to memory, perform
121  /// the insert there, and then read the result back.
122  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
123  const SDLoc &dl);
124  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
125  const SDLoc &dl);
126 
127  /// Return a vector shuffle operation which
128  /// performs the same shuffe in terms of order or result bytes, but on a type
129  /// whose vector element type is narrower than the original shuffle type.
130  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
131  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
132  SDValue N1, SDValue N2,
133  ArrayRef<int> Mask) const;
134 
135  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
136  bool &NeedInvert, const SDLoc &dl);
137 
138  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
139 
140  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
141  SDNode *Node, bool isSigned);
142  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
143  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
144  RTLIB::Libcall Call_F128,
145  RTLIB::Libcall Call_PPCF128);
146  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
147  RTLIB::Libcall Call_I8,
148  RTLIB::Libcall Call_I16,
149  RTLIB::Libcall Call_I32,
150  RTLIB::Libcall Call_I64,
151  RTLIB::Libcall Call_I128);
152  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
153  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
154 
155  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
156  const SDLoc &dl);
157  SDValue ExpandBUILD_VECTOR(SDNode *Node);
158  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
159  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
160  SmallVectorImpl<SDValue> &Results);
161  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
162  SDValue Value) const;
163  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
164  SDValue NewIntValue) const;
165  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
166  SDValue ExpandFABS(SDNode *Node) const;
167  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
168  const SDLoc &dl);
169  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
170  const SDLoc &dl);
171  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
172  const SDLoc &dl);
173 
174  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
175  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
176 
177  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
178  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
179  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
180 
181  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
182  SDValue ExpandConstant(ConstantSDNode *CP);
183 
184  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
185  bool ExpandNode(SDNode *Node);
186  void ConvertNodeToLibcall(SDNode *Node);
187  void PromoteNode(SDNode *Node);
188 
189 public:
190  // Node replacement helpers
191 
192  void ReplacedNode(SDNode *N) {
193  LegalizedNodes.erase(N);
194  if (UpdatedNodes)
195  UpdatedNodes->insert(N);
196  }
197 
198  void ReplaceNode(SDNode *Old, SDNode *New) {
199  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
200  dbgs() << " with: "; New->dump(&DAG));
201 
202  assert(Old->getNumValues() == New->getNumValues() &&
203  "Replacing one node with another that produces a different number "
204  "of values!");
205  DAG.ReplaceAllUsesWith(Old, New);
206  if (UpdatedNodes)
207  UpdatedNodes->insert(New);
208  ReplacedNode(Old);
209  }
210 
211  void ReplaceNode(SDValue Old, SDValue New) {
212  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
213  dbgs() << " with: "; New->dump(&DAG));
214 
215  DAG.ReplaceAllUsesWith(Old, New);
216  if (UpdatedNodes)
217  UpdatedNodes->insert(New.getNode());
218  ReplacedNode(Old.getNode());
219  }
220 
221  void ReplaceNode(SDNode *Old, const SDValue *New) {
222  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
223 
224  DAG.ReplaceAllUsesWith(Old, New);
225  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
226  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
227  New[i]->dump(&DAG));
228  if (UpdatedNodes)
229  UpdatedNodes->insert(New[i].getNode());
230  }
231  ReplacedNode(Old);
232  }
233 };
234 
235 } // end anonymous namespace
236 
237 /// Return a vector shuffle operation which
238 /// performs the same shuffle in terms of order or result bytes, but on a type
239 /// whose vector element type is narrower than the original shuffle type.
240 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
241 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
242  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
243  ArrayRef<int> Mask) const {
244  unsigned NumMaskElts = VT.getVectorNumElements();
245  unsigned NumDestElts = NVT.getVectorNumElements();
246  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
247 
248  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 
250  if (NumEltsGrowth == 1)
251  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
252 
253  SmallVector<int, 8> NewMask;
254  for (unsigned i = 0; i != NumMaskElts; ++i) {
255  int Idx = Mask[i];
256  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
257  if (Idx < 0)
258  NewMask.push_back(-1);
259  else
260  NewMask.push_back(Idx * NumEltsGrowth + j);
261  }
262  }
263  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
264  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
265  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
266 }
267 
268 /// Expands the ConstantFP node to an integer constant or
269 /// a load from the constant pool.
270 SDValue
271 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
272  bool Extend = false;
273  SDLoc dl(CFP);
274 
275  // If a FP immediate is precise when represented as a float and if the
276  // target can do an extending load from float to double, we put it into
277  // the constant pool as a float, even if it's is statically typed as a
278  // double. This shrinks FP constants and canonicalizes them for targets where
279  // an FP extending load is the same cost as a normal load (such as on the x87
280  // fp stack or PPC FP unit).
281  EVT VT = CFP->getValueType(0);
282  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
283  if (!UseCP) {
284  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
285  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
286  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
287  }
288 
289  APFloat APF = CFP->getValueAPF();
290  EVT OrigVT = VT;
291  EVT SVT = VT;
292 
293  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
294  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
295  if (!APF.isSignaling()) {
296  while (SVT != MVT::f32 && SVT != MVT::f16) {
297  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
299  // Only do this if the target has a native EXTLOAD instruction from
300  // smaller type.
301  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
302  TLI.ShouldShrinkFPConstant(OrigVT)) {
303  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
304  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
305  VT = SVT;
306  Extend = true;
307  }
308  }
309  }
310 
311  SDValue CPIdx =
312  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
313  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
314  if (Extend) {
315  SDValue Result = DAG.getExtLoad(
316  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
317  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
318  Alignment);
319  return Result;
320  }
321  SDValue Result = DAG.getLoad(
322  OrigVT, dl, DAG.getEntryNode(), CPIdx,
323  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
324  return Result;
325 }
326 
327 /// Expands the Constant node to a load from the constant pool.
328 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
329  SDLoc dl(CP);
330  EVT VT = CP->getValueType(0);
331  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
332  TLI.getPointerTy(DAG.getDataLayout()));
333  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
334  SDValue Result = DAG.getLoad(
335  VT, dl, DAG.getEntryNode(), CPIdx,
336  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
337  return Result;
338 }
339 
340 /// Some target cannot handle a variable insertion index for the
341 /// INSERT_VECTOR_ELT instruction. In this case, it
342 /// is necessary to spill the vector being inserted into to memory, perform
343 /// the insert there, and then read the result back.
344 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
345  SDValue Val,
346  SDValue Idx,
347  const SDLoc &dl) {
348  SDValue Tmp1 = Vec;
349  SDValue Tmp2 = Val;
350  SDValue Tmp3 = Idx;
351 
352  // If the target doesn't support this, we have to spill the input vector
353  // to a temporary stack slot, update the element, then reload it. This is
354  // badness. We could also load the value into a vector register (either
355  // with a "move to register" or "extload into register" instruction, then
356  // permute it into place, if the idx is a constant and if the idx is
357  // supported by the target.
358  EVT VT = Tmp1.getValueType();
359  EVT EltVT = VT.getVectorElementType();
360  SDValue StackPtr = DAG.CreateStackTemporary(VT);
361 
362  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
363 
364  // Store the vector.
365  SDValue Ch = DAG.getStore(
366  DAG.getEntryNode(), dl, Tmp1, StackPtr,
367  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
368 
369  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
370 
371  // Store the scalar value.
372  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
373  // Load the updated vector.
374  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
375  DAG.getMachineFunction(), SPFI));
376 }
377 
378 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
379  SDValue Idx,
380  const SDLoc &dl) {
381  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
382  // SCALAR_TO_VECTOR requires that the type of the value being inserted
383  // match the element type of the vector being created, except for
384  // integers in which case the inserted value can be over width.
385  EVT EltVT = Vec.getValueType().getVectorElementType();
386  if (Val.getValueType() == EltVT ||
387  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
388  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
389  Vec.getValueType(), Val);
390 
391  unsigned NumElts = Vec.getValueType().getVectorNumElements();
392  // We generate a shuffle of InVec and ScVec, so the shuffle mask
393  // should be 0,1,2,3,4,5... with the appropriate element replaced with
394  // elt 0 of the RHS.
395  SmallVector<int, 8> ShufOps;
396  for (unsigned i = 0; i != NumElts; ++i)
397  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
398 
399  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
400  }
401  }
402  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
403 }
404 
405 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
406  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
407  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
408  // FIXME: We shouldn't do this for TargetConstantFP's.
409  // FIXME: move this to the DAG Combiner! Note that we can't regress due
410  // to phase ordering between legalized code and the dag combiner. This
411  // probably means that we need to integrate dag combiner and legalizer
412  // together.
413  // We generally can't do this one for long doubles.
414  SDValue Chain = ST->getChain();
415  SDValue Ptr = ST->getBasePtr();
416  unsigned Alignment = ST->getAlignment();
417  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
418  AAMDNodes AAInfo = ST->getAAInfo();
419  SDLoc dl(ST);
420  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
421  if (CFP->getValueType(0) == MVT::f32 &&
422  TLI.isTypeLegal(MVT::i32)) {
423  SDValue Con = DAG.getConstant(CFP->getValueAPF().
424  bitcastToAPInt().zextOrTrunc(32),
425  SDLoc(CFP), MVT::i32);
426  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
427  MMOFlags, AAInfo);
428  }
429 
430  if (CFP->getValueType(0) == MVT::f64) {
431  // If this target supports 64-bit registers, do a single 64-bit store.
432  if (TLI.isTypeLegal(MVT::i64)) {
433  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
434  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
435  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
436  Alignment, MMOFlags, AAInfo);
437  }
438 
439  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
440  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
441  // stores. If the target supports neither 32- nor 64-bits, this
442  // xform is certainly not worth it.
443  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
444  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
445  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
446  if (DAG.getDataLayout().isBigEndian())
447  std::swap(Lo, Hi);
448 
449  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
450  MMOFlags, AAInfo);
451  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
452  DAG.getConstant(4, dl, Ptr.getValueType()));
453  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
454  ST->getPointerInfo().getWithOffset(4),
455  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
456 
457  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
458  }
459  }
460  }
461  return SDValue(nullptr, 0);
462 }
463 
464 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
465  StoreSDNode *ST = cast<StoreSDNode>(Node);
466  SDValue Chain = ST->getChain();
467  SDValue Ptr = ST->getBasePtr();
468  SDLoc dl(Node);
469 
470  unsigned Alignment = ST->getAlignment();
471  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
472  AAMDNodes AAInfo = ST->getAAInfo();
473 
474  if (!ST->isTruncatingStore()) {
475  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
476  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
477  ReplaceNode(ST, OptStore);
478  return;
479  }
480 
481  SDValue Value = ST->getValue();
482  MVT VT = Value.getSimpleValueType();
483  switch (TLI.getOperationAction(ISD::STORE, VT)) {
484  default: llvm_unreachable("This action is not supported yet!");
485  case TargetLowering::Legal: {
486  // If this is an unaligned store and the target doesn't support it,
487  // expand it.
488  EVT MemVT = ST->getMemoryVT();
489  unsigned AS = ST->getAddressSpace();
490  unsigned Align = ST->getAlignment();
491  const DataLayout &DL = DAG.getDataLayout();
492  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
493  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
494  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
495  ReplaceNode(SDValue(ST, 0), Result);
496  } else
497  LLVM_DEBUG(dbgs() << "Legal store\n");
498  break;
499  }
500  case TargetLowering::Custom: {
501  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
502  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
503  if (Res && Res != SDValue(Node, 0))
504  ReplaceNode(SDValue(Node, 0), Res);
505  return;
506  }
508  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
509  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
510  "Can only promote stores to same size type");
511  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
512  SDValue Result =
513  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
514  Alignment, MMOFlags, AAInfo);
515  ReplaceNode(SDValue(Node, 0), Result);
516  break;
517  }
518  }
519  return;
520  }
521 
522  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
523  SDValue Value = ST->getValue();
524  EVT StVT = ST->getMemoryVT();
525  unsigned StWidth = StVT.getSizeInBits();
526  auto &DL = DAG.getDataLayout();
527 
528  if (StWidth != StVT.getStoreSizeInBits()) {
529  // Promote to a byte-sized store with upper bits zero if not
530  // storing an integral number of bytes. For example, promote
531  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
532  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
533  StVT.getStoreSizeInBits());
534  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
535  SDValue Result =
536  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
537  Alignment, MMOFlags, AAInfo);
538  ReplaceNode(SDValue(Node, 0), Result);
539  } else if (StWidth & (StWidth - 1)) {
540  // If not storing a power-of-2 number of bits, expand as two stores.
541  assert(!StVT.isVector() && "Unsupported truncstore!");
542  unsigned RoundWidth = 1 << Log2_32(StWidth);
543  assert(RoundWidth < StWidth);
544  unsigned ExtraWidth = StWidth - RoundWidth;
545  assert(ExtraWidth < RoundWidth);
546  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
547  "Store size not an integral number of bytes!");
548  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
549  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
550  SDValue Lo, Hi;
551  unsigned IncrementSize;
552 
553  if (DL.isLittleEndian()) {
554  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
555  // Store the bottom RoundWidth bits.
556  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
557  RoundVT, Alignment, MMOFlags, AAInfo);
558 
559  // Store the remaining ExtraWidth bits.
560  IncrementSize = RoundWidth / 8;
561  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
562  DAG.getConstant(IncrementSize, dl,
563  Ptr.getValueType()));
564  Hi = DAG.getNode(
565  ISD::SRL, dl, Value.getValueType(), Value,
566  DAG.getConstant(RoundWidth, dl,
567  TLI.getShiftAmountTy(Value.getValueType(), DL)));
568  Hi = DAG.getTruncStore(
569  Chain, dl, Hi, Ptr,
570  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
571  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
572  } else {
573  // Big endian - avoid unaligned stores.
574  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
575  // Store the top RoundWidth bits.
576  Hi = DAG.getNode(
577  ISD::SRL, dl, Value.getValueType(), Value,
578  DAG.getConstant(ExtraWidth, dl,
579  TLI.getShiftAmountTy(Value.getValueType(), DL)));
580  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
581  RoundVT, Alignment, MMOFlags, AAInfo);
582 
583  // Store the remaining ExtraWidth bits.
584  IncrementSize = RoundWidth / 8;
585  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
586  DAG.getConstant(IncrementSize, dl,
587  Ptr.getValueType()));
588  Lo = DAG.getTruncStore(
589  Chain, dl, Value, Ptr,
590  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
591  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
592  }
593 
594  // The order of the stores doesn't matter.
595  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
596  ReplaceNode(SDValue(Node, 0), Result);
597  } else {
598  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
599  default: llvm_unreachable("This action is not supported yet!");
600  case TargetLowering::Legal: {
601  EVT MemVT = ST->getMemoryVT();
602  unsigned AS = ST->getAddressSpace();
603  unsigned Align = ST->getAlignment();
604  // If this is an unaligned store and the target doesn't support it,
605  // expand it.
606  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
607  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
608  ReplaceNode(SDValue(ST, 0), Result);
609  }
610  break;
611  }
612  case TargetLowering::Custom: {
613  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
614  if (Res && Res != SDValue(Node, 0))
615  ReplaceNode(SDValue(Node, 0), Res);
616  return;
617  }
619  assert(!StVT.isVector() &&
620  "Vector Stores are handled in LegalizeVectorOps");
621 
622  SDValue Result;
623 
624  // TRUNCSTORE:i16 i32 -> STORE i16
625  if (TLI.isTypeLegal(StVT)) {
626  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
627  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
628  Alignment, MMOFlags, AAInfo);
629  } else {
630  // The in-memory type isn't legal. Truncate to the type it would promote
631  // to, and then do a truncstore.
632  Value = DAG.getNode(ISD::TRUNCATE, dl,
633  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
634  Value);
635  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
636  StVT, Alignment, MMOFlags, AAInfo);
637  }
638 
639  ReplaceNode(SDValue(Node, 0), Result);
640  break;
641  }
642  }
643 }
644 
645 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
646  LoadSDNode *LD = cast<LoadSDNode>(Node);
647  SDValue Chain = LD->getChain(); // The chain.
648  SDValue Ptr = LD->getBasePtr(); // The base pointer.
649  SDValue Value; // The value returned by the load op.
650  SDLoc dl(Node);
651 
653  if (ExtType == ISD::NON_EXTLOAD) {
654  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
655  MVT VT = Node->getSimpleValueType(0);
656  SDValue RVal = SDValue(Node, 0);
657  SDValue RChain = SDValue(Node, 1);
658 
659  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
660  default: llvm_unreachable("This action is not supported yet!");
661  case TargetLowering::Legal: {
662  EVT MemVT = LD->getMemoryVT();
663  unsigned AS = LD->getAddressSpace();
664  unsigned Align = LD->getAlignment();
665  const DataLayout &DL = DAG.getDataLayout();
666  // If this is an unaligned load and the target doesn't support it,
667  // expand it.
668  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
669  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
670  }
671  break;
672  }
674  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
675  RVal = Res;
676  RChain = Res.getValue(1);
677  }
678  break;
679 
681  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
682  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
683  "Can only promote loads to same size type");
684 
685  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
686  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
687  RChain = Res.getValue(1);
688  break;
689  }
690  }
691  if (RChain.getNode() != Node) {
692  assert(RVal.getNode() != Node && "Load must be completely replaced");
693  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
694  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
695  if (UpdatedNodes) {
696  UpdatedNodes->insert(RVal.getNode());
697  UpdatedNodes->insert(RChain.getNode());
698  }
699  ReplacedNode(Node);
700  }
701  return;
702  }
703 
704  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
705  EVT SrcVT = LD->getMemoryVT();
706  unsigned SrcWidth = SrcVT.getSizeInBits();
707  unsigned Alignment = LD->getAlignment();
708  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
709  AAMDNodes AAInfo = LD->getAAInfo();
710 
711  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
712  // Some targets pretend to have an i1 loading operation, and actually
713  // load an i8. This trick is correct for ZEXTLOAD because the top 7
714  // bits are guaranteed to be zero; it helps the optimizers understand
715  // that these bits are zero. It is also useful for EXTLOAD, since it
716  // tells the optimizers that those bits are undefined. It would be
717  // nice to have an effective generic way of getting these benefits...
718  // Until such a way is found, don't insist on promoting i1 here.
719  (SrcVT != MVT::i1 ||
720  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
722  // Promote to a byte-sized load if not loading an integral number of
723  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
724  unsigned NewWidth = SrcVT.getStoreSizeInBits();
725  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
726  SDValue Ch;
727 
728  // The extra bits are guaranteed to be zero, since we stored them that
729  // way. A zext load from NVT thus automatically gives zext from SrcVT.
730 
731  ISD::LoadExtType NewExtType =
733 
734  SDValue Result =
735  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
736  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
737 
738  Ch = Result.getValue(1); // The chain.
739 
740  if (ExtType == ISD::SEXTLOAD)
741  // Having the top bits zero doesn't help when sign extending.
742  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
743  Result.getValueType(),
744  Result, DAG.getValueType(SrcVT));
745  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
746  // All the top bits are guaranteed to be zero - inform the optimizers.
747  Result = DAG.getNode(ISD::AssertZext, dl,
748  Result.getValueType(), Result,
749  DAG.getValueType(SrcVT));
750 
751  Value = Result;
752  Chain = Ch;
753  } else if (SrcWidth & (SrcWidth - 1)) {
754  // If not loading a power-of-2 number of bits, expand as two loads.
755  assert(!SrcVT.isVector() && "Unsupported extload!");
756  unsigned RoundWidth = 1 << Log2_32(SrcWidth);
757  assert(RoundWidth < SrcWidth);
758  unsigned ExtraWidth = SrcWidth - RoundWidth;
759  assert(ExtraWidth < RoundWidth);
760  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
761  "Load size not an integral number of bytes!");
762  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
763  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
764  SDValue Lo, Hi, Ch;
765  unsigned IncrementSize;
766  auto &DL = DAG.getDataLayout();
767 
768  if (DL.isLittleEndian()) {
769  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
770  // Load the bottom RoundWidth bits.
771  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
772  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
773  AAInfo);
774 
775  // Load the remaining ExtraWidth bits.
776  IncrementSize = RoundWidth / 8;
777  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
778  DAG.getConstant(IncrementSize, dl,
779  Ptr.getValueType()));
780  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
781  LD->getPointerInfo().getWithOffset(IncrementSize),
782  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
783  AAInfo);
784 
785  // Build a factor node to remember that this load is independent of
786  // the other one.
787  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
788  Hi.getValue(1));
789 
790  // Move the top bits to the right place.
791  Hi = DAG.getNode(
792  ISD::SHL, dl, Hi.getValueType(), Hi,
793  DAG.getConstant(RoundWidth, dl,
794  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
795 
796  // Join the hi and lo parts.
797  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
798  } else {
799  // Big endian - avoid unaligned loads.
800  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
801  // Load the top RoundWidth bits.
802  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
803  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
804  AAInfo);
805 
806  // Load the remaining ExtraWidth bits.
807  IncrementSize = RoundWidth / 8;
808  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809  DAG.getConstant(IncrementSize, dl,
810  Ptr.getValueType()));
811  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
812  LD->getPointerInfo().getWithOffset(IncrementSize),
813  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
814  AAInfo);
815 
816  // Build a factor node to remember that this load is independent of
817  // the other one.
818  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
819  Hi.getValue(1));
820 
821  // Move the top bits to the right place.
822  Hi = DAG.getNode(
823  ISD::SHL, dl, Hi.getValueType(), Hi,
824  DAG.getConstant(ExtraWidth, dl,
825  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
826 
827  // Join the hi and lo parts.
828  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
829  }
830 
831  Chain = Ch;
832  } else {
833  bool isCustom = false;
834  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
835  SrcVT.getSimpleVT())) {
836  default: llvm_unreachable("This action is not supported yet!");
838  isCustom = true;
841  Value = SDValue(Node, 0);
842  Chain = SDValue(Node, 1);
843 
844  if (isCustom) {
845  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
846  Value = Res;
847  Chain = Res.getValue(1);
848  }
849  } else {
850  // If this is an unaligned load and the target doesn't support it,
851  // expand it.
852  EVT MemVT = LD->getMemoryVT();
853  unsigned AS = LD->getAddressSpace();
854  unsigned Align = LD->getAlignment();
855  const DataLayout &DL = DAG.getDataLayout();
856  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
857  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
858  }
859  }
860  break;
861 
862  case TargetLowering::Expand: {
863  EVT DestVT = Node->getValueType(0);
864  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
865  // If the source type is not legal, see if there is a legal extload to
866  // an intermediate type that we can then extend further.
867  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
868  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
869  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
870  // If we are loading a legal type, this is a non-extload followed by a
871  // full extend.
872  ISD::LoadExtType MidExtType =
873  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
874 
875  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
876  SrcVT, LD->getMemOperand());
877  unsigned ExtendOp =
879  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
880  Chain = Load.getValue(1);
881  break;
882  }
883 
884  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
885  // normal undefined upper bits behavior to allow using an in-reg extend
886  // with the illegal FP type, so load as an integer and do the
887  // from-integer conversion.
888  if (SrcVT.getScalarType() == MVT::f16) {
889  EVT ISrcVT = SrcVT.changeTypeToInteger();
890  EVT IDestVT = DestVT.changeTypeToInteger();
891  EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
892 
893  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
894  Chain, Ptr, ISrcVT,
895  LD->getMemOperand());
896  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
897  Chain = Result.getValue(1);
898  break;
899  }
900  }
901 
902  assert(!SrcVT.isVector() &&
903  "Vector Loads are handled in LegalizeVectorOps");
904 
905  // FIXME: This does not work for vectors on most targets. Sign-
906  // and zero-extend operations are currently folded into extending
907  // loads, whether they are legal or not, and then we end up here
908  // without any support for legalizing them.
909  assert(ExtType != ISD::EXTLOAD &&
910  "EXTLOAD should always be supported!");
911  // Turn the unsupported load into an EXTLOAD followed by an
912  // explicit zero/sign extend inreg.
913  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
914  Node->getValueType(0),
915  Chain, Ptr, SrcVT,
916  LD->getMemOperand());
917  SDValue ValRes;
918  if (ExtType == ISD::SEXTLOAD)
919  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
920  Result.getValueType(),
921  Result, DAG.getValueType(SrcVT));
922  else
923  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
924  Value = ValRes;
925  Chain = Result.getValue(1);
926  break;
927  }
928  }
929  }
930 
931  // Since loads produce two values, make sure to remember that we legalized
932  // both of them.
933  if (Chain.getNode() != Node) {
934  assert(Value.getNode() != Node && "Load must be completely replaced");
935  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
936  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
937  if (UpdatedNodes) {
938  UpdatedNodes->insert(Value.getNode());
939  UpdatedNodes->insert(Chain.getNode());
940  }
941  ReplacedNode(Node);
942  }
943 }
944 
945 /// Return a legal replacement for the given operation, with all legal operands.
946 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
947  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
948 
949  // Allow illegal target nodes and illegal registers.
950  if (Node->getOpcode() == ISD::TargetConstant ||
951  Node->getOpcode() == ISD::Register)
952  return;
953 
954 #ifndef NDEBUG
955  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
956  assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
958  TLI.isTypeLegal(Node->getValueType(i))) &&
959  "Unexpected illegal type!");
960 
961  for (const SDValue &Op : Node->op_values())
962  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
964  TLI.isTypeLegal(Op.getValueType()) ||
965  Op.getOpcode() == ISD::TargetConstant ||
966  Op.getOpcode() == ISD::Register) &&
967  "Unexpected illegal type!");
968 #endif
969 
970  // Figure out the correct action; the way to query this varies by opcode
972  bool SimpleFinishLegalizing = true;
973  switch (Node->getOpcode()) {
976  case ISD::INTRINSIC_VOID:
977  case ISD::STACKSAVE:
978  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
979  break;
981  Action = TLI.getOperationAction(Node->getOpcode(),
982  Node->getValueType(0));
983  break;
984  case ISD::VAARG:
985  Action = TLI.getOperationAction(Node->getOpcode(),
986  Node->getValueType(0));
987  if (Action != TargetLowering::Promote)
988  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
989  break;
990  case ISD::FP_TO_FP16:
991  case ISD::SINT_TO_FP:
992  case ISD::UINT_TO_FP:
994  Action = TLI.getOperationAction(Node->getOpcode(),
995  Node->getOperand(0).getValueType());
996  break;
997  case ISD::FP_ROUND_INREG:
998  case ISD::SIGN_EXTEND_INREG: {
999  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1000  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1001  break;
1002  }
1003  case ISD::ATOMIC_STORE:
1004  Action = TLI.getOperationAction(Node->getOpcode(),
1005  Node->getOperand(2).getValueType());
1006  break;
1007  case ISD::SELECT_CC:
1008  case ISD::SETCC:
1009  case ISD::BR_CC: {
1010  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1011  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1012  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1013  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1014  ISD::CondCode CCCode =
1015  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1016  Action = TLI.getCondCodeAction(CCCode, OpVT);
1017  if (Action == TargetLowering::Legal) {
1018  if (Node->getOpcode() == ISD::SELECT_CC)
1019  Action = TLI.getOperationAction(Node->getOpcode(),
1020  Node->getValueType(0));
1021  else
1022  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1023  }
1024  break;
1025  }
1026  case ISD::LOAD:
1027  case ISD::STORE:
1028  // FIXME: Model these properly. LOAD and STORE are complicated, and
1029  // STORE expects the unlegalized operand in some cases.
1030  SimpleFinishLegalizing = false;
1031  break;
1032  case ISD::CALLSEQ_START:
1033  case ISD::CALLSEQ_END:
1034  // FIXME: This shouldn't be necessary. These nodes have special properties
1035  // dealing with the recursive nature of legalization. Removing this
1036  // special case should be done as part of making LegalizeDAG non-recursive.
1037  SimpleFinishLegalizing = false;
1038  break;
1039  case ISD::EXTRACT_ELEMENT:
1040  case ISD::FLT_ROUNDS_:
1041  case ISD::MERGE_VALUES:
1042  case ISD::EH_RETURN:
1044  case ISD::EH_DWARF_CFA:
1045  case ISD::EH_SJLJ_SETJMP:
1046  case ISD::EH_SJLJ_LONGJMP:
1048  // These operations lie about being legal: when they claim to be legal,
1049  // they should actually be expanded.
1050  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1051  if (Action == TargetLowering::Legal)
1052  Action = TargetLowering::Expand;
1053  break;
1054  case ISD::INIT_TRAMPOLINE:
1056  case ISD::FRAMEADDR:
1057  case ISD::RETURNADDR:
1058  case ISD::ADDROFRETURNADDR:
1059  case ISD::SPONENTRY:
1060  // These operations lie about being legal: when they claim to be legal,
1061  // they should actually be custom-lowered.
1062  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1063  if (Action == TargetLowering::Legal)
1064  Action = TargetLowering::Custom;
1065  break;
1066  case ISD::READCYCLECOUNTER:
1067  // READCYCLECOUNTER returns an i64, even if type legalization might have
1068  // expanded that to several smaller types.
1069  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1070  break;
1071  case ISD::READ_REGISTER:
1072  case ISD::WRITE_REGISTER:
1073  // Named register is legal in the DAG, but blocked by register name
1074  // selection if not implemented by target (to chose the correct register)
1075  // They'll be converted to Copy(To/From)Reg.
1076  Action = TargetLowering::Legal;
1077  break;
1078  case ISD::DEBUGTRAP:
1079  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1080  if (Action == TargetLowering::Expand) {
1081  // replace ISD::DEBUGTRAP with ISD::TRAP
1082  SDValue NewVal;
1083  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1084  Node->getOperand(0));
1085  ReplaceNode(Node, NewVal.getNode());
1086  LegalizeOp(NewVal.getNode());
1087  return;
1088  }
1089  break;
1090  case ISD::STRICT_FADD:
1091  case ISD::STRICT_FSUB:
1092  case ISD::STRICT_FMUL:
1093  case ISD::STRICT_FDIV:
1094  case ISD::STRICT_FREM:
1095  case ISD::STRICT_FSQRT:
1096  case ISD::STRICT_FMA:
1097  case ISD::STRICT_FPOW:
1098  case ISD::STRICT_FPOWI:
1099  case ISD::STRICT_FSIN:
1100  case ISD::STRICT_FCOS:
1101  case ISD::STRICT_FEXP:
1102  case ISD::STRICT_FEXP2:
1103  case ISD::STRICT_FLOG:
1104  case ISD::STRICT_FLOG10:
1105  case ISD::STRICT_FLOG2:
1106  case ISD::STRICT_FRINT:
1108  case ISD::STRICT_FMAXNUM:
1109  case ISD::STRICT_FMINNUM:
1110  case ISD::STRICT_FCEIL:
1111  case ISD::STRICT_FFLOOR:
1112  case ISD::STRICT_FROUND:
1113  case ISD::STRICT_FTRUNC:
1114  // These pseudo-ops get legalized as if they were their non-strict
1115  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
1116  // is also legal, but if ISD::FSQRT requires expansion then so does
1117  // ISD::STRICT_FSQRT.
1118  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1119  Node->getValueType(0));
1120  break;
1121  case ISD::SADDSAT:
1122  case ISD::UADDSAT:
1123  case ISD::SSUBSAT:
1124  case ISD::USUBSAT: {
1125  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1126  break;
1127  }
1128  case ISD::SMULFIX:
1129  case ISD::UMULFIX: {
1130  unsigned Scale = Node->getConstantOperandVal(2);
1131  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1132  Node->getValueType(0), Scale);
1133  break;
1134  }
1135  case ISD::MSCATTER:
1136  Action = TLI.getOperationAction(Node->getOpcode(),
1137  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1138  break;
1139  case ISD::MSTORE:
1140  Action = TLI.getOperationAction(Node->getOpcode(),
1141  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1142  break;
1143  default:
1144  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1145  Action = TargetLowering::Legal;
1146  } else {
1147  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1148  }
1149  break;
1150  }
1151 
1152  if (SimpleFinishLegalizing) {
1153  SDNode *NewNode = Node;
1154  switch (Node->getOpcode()) {
1155  default: break;
1156  case ISD::SHL:
1157  case ISD::SRL:
1158  case ISD::SRA:
1159  case ISD::ROTL:
1160  case ISD::ROTR: {
1161  // Legalizing shifts/rotates requires adjusting the shift amount
1162  // to the appropriate width.
1163  SDValue Op0 = Node->getOperand(0);
1164  SDValue Op1 = Node->getOperand(1);
1165  if (!Op1.getValueType().isVector()) {
1166  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1167  // The getShiftAmountOperand() may create a new operand node or
1168  // return the existing one. If new operand is created we need
1169  // to update the parent node.
1170  // Do not try to legalize SAO here! It will be automatically legalized
1171  // in the next round.
1172  if (SAO != Op1)
1173  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1174  }
1175  }
1176  break;
1177  case ISD::FSHL:
1178  case ISD::FSHR:
1179  case ISD::SRL_PARTS:
1180  case ISD::SRA_PARTS:
1181  case ISD::SHL_PARTS: {
1182  // Legalizing shifts/rotates requires adjusting the shift amount
1183  // to the appropriate width.
1184  SDValue Op0 = Node->getOperand(0);
1185  SDValue Op1 = Node->getOperand(1);
1186  SDValue Op2 = Node->getOperand(2);
1187  if (!Op2.getValueType().isVector()) {
1188  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1189  // The getShiftAmountOperand() may create a new operand node or
1190  // return the existing one. If new operand is created we need
1191  // to update the parent node.
1192  if (SAO != Op2)
1193  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1194  }
1195  break;
1196  }
1197  }
1198 
1199  if (NewNode != Node) {
1200  ReplaceNode(Node, NewNode);
1201  Node = NewNode;
1202  }
1203  switch (Action) {
1204  case TargetLowering::Legal:
1205  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1206  return;
1208  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1209  // FIXME: The handling for custom lowering with multiple results is
1210  // a complete mess.
1211  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1212  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1213  return;
1214 
1215  if (Node->getNumValues() == 1) {
1216  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1217  // We can just directly replace this node with the lowered value.
1218  ReplaceNode(SDValue(Node, 0), Res);
1219  return;
1220  }
1221 
1222  SmallVector<SDValue, 8> ResultVals;
1223  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1224  ResultVals.push_back(Res.getValue(i));
1225  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1226  ReplaceNode(Node, ResultVals.data());
1227  return;
1228  }
1229  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1232  if (ExpandNode(Node))
1233  return;
1236  ConvertNodeToLibcall(Node);
1237  return;
1239  PromoteNode(Node);
1240  return;
1241  }
1242  }
1243 
1244  switch (Node->getOpcode()) {
1245  default:
1246 #ifndef NDEBUG
1247  dbgs() << "NODE: ";
1248  Node->dump( &DAG);
1249  dbgs() << "\n";
1250 #endif
1251  llvm_unreachable("Do not know how to legalize this operator!");
1252 
1253  case ISD::CALLSEQ_START:
1254  case ISD::CALLSEQ_END:
1255  break;
1256  case ISD::LOAD:
1257  return LegalizeLoadOps(Node);
1258  case ISD::STORE:
1259  return LegalizeStoreOps(Node);
1260  }
1261 }
1262 
1263 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1264  SDValue Vec = Op.getOperand(0);
1265  SDValue Idx = Op.getOperand(1);
1266  SDLoc dl(Op);
1267 
1268  // Before we generate a new store to a temporary stack slot, see if there is
1269  // already one that we can use. There often is because when we scalarize
1270  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1271  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1272  // the vector. If all are expanded here, we don't want one store per vector
1273  // element.
1274 
1275  // Caches for hasPredecessorHelper
1278  Visited.insert(Op.getNode());
1279  Worklist.push_back(Idx.getNode());
1280  SDValue StackPtr, Ch;
1281  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1282  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1283  SDNode *User = *UI;
1284  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1285  if (ST->isIndexed() || ST->isTruncatingStore() ||
1286  ST->getValue() != Vec)
1287  continue;
1288 
1289  // Make sure that nothing else could have stored into the destination of
1290  // this store.
1291  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1292  continue;
1293 
1294  // If the index is dependent on the store we will introduce a cycle when
1295  // creating the load (the load uses the index, and by replacing the chain
1296  // we will make the index dependent on the load). Also, the store might be
1297  // dependent on the extractelement and introduce a cycle when creating
1298  // the load.
1299  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1300  ST->hasPredecessor(Op.getNode()))
1301  continue;
1302 
1303  StackPtr = ST->getBasePtr();
1304  Ch = SDValue(ST, 0);
1305  break;
1306  }
1307  }
1308 
1309  EVT VecVT = Vec.getValueType();
1310 
1311  if (!Ch.getNode()) {
1312  // Store the value to a temporary stack slot, then LOAD the returned part.
1313  StackPtr = DAG.CreateStackTemporary(VecVT);
1314  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1315  MachinePointerInfo());
1316  }
1317 
1318  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1319 
1320  SDValue NewLoad;
1321 
1322  if (Op.getValueType().isVector())
1323  NewLoad =
1324  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1325  else
1326  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1328  VecVT.getVectorElementType());
1329 
1330  // Replace the chain going out of the store, by the one out of the load.
1331  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1332 
1333  // We introduced a cycle though, so update the loads operands, making sure
1334  // to use the original store's chain as an incoming chain.
1335  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1336  NewLoad->op_end());
1337  NewLoadOperands[0] = Ch;
1338  NewLoad =
1339  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1340  return NewLoad;
1341 }
1342 
1343 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1344  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1345 
1346  SDValue Vec = Op.getOperand(0);
1347  SDValue Part = Op.getOperand(1);
1348  SDValue Idx = Op.getOperand(2);
1349  SDLoc dl(Op);
1350 
1351  // Store the value to a temporary stack slot, then LOAD the returned part.
1352  EVT VecVT = Vec.getValueType();
1353  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1354  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1355  MachinePointerInfo PtrInfo =
1356  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1357 
1358  // First store the whole vector.
1359  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1360 
1361  // Then store the inserted part.
1362  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1363 
1364  // Store the subvector.
1365  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1366 
1367  // Finally, load the updated vector.
1368  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1369 }
1370 
1371 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1372  // We can't handle this case efficiently. Allocate a sufficiently
1373  // aligned object on the stack, store each element into it, then load
1374  // the result as a vector.
1375  // Create the stack frame object.
1376  EVT VT = Node->getValueType(0);
1377  EVT EltVT = VT.getVectorElementType();
1378  SDLoc dl(Node);
1379  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1380  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1381  MachinePointerInfo PtrInfo =
1382  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1383 
1384  // Emit a store of each element to the stack slot.
1385  SmallVector<SDValue, 8> Stores;
1386  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1387  // Store (in the right endianness) the elements to memory.
1388  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1389  // Ignore undef elements.
1390  if (Node->getOperand(i).isUndef()) continue;
1391 
1392  unsigned Offset = TypeByteSize*i;
1393 
1394  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1395  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1396 
1397  // If the destination vector element type is narrower than the source
1398  // element type, only store the bits necessary.
1399  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1400  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1401  Node->getOperand(i), Idx,
1402  PtrInfo.getWithOffset(Offset), EltVT));
1403  } else
1404  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1405  Idx, PtrInfo.getWithOffset(Offset)));
1406  }
1407 
1408  SDValue StoreChain;
1409  if (!Stores.empty()) // Not all undef elements?
1410  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1411  else
1412  StoreChain = DAG.getEntryNode();
1413 
1414  // Result is a load from the stack slot.
1415  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1416 }
1417 
1418 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1419 /// containing the sign bit if the target has no integer value capable of
1420 /// holding all bits of the floating-point value.
1421 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1422  const SDLoc &DL,
1423  SDValue Value) const {
1424  EVT FloatVT = Value.getValueType();
1425  unsigned NumBits = FloatVT.getSizeInBits();
1426  State.FloatVT = FloatVT;
1427  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1428  // Convert to an integer of the same size.
1429  if (TLI.isTypeLegal(IVT)) {
1430  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1431  State.SignMask = APInt::getSignMask(NumBits);
1432  State.SignBit = NumBits - 1;
1433  return;
1434  }
1435 
1436  auto &DataLayout = DAG.getDataLayout();
1437  // Store the float to memory, then load the sign part out as an integer.
1438  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1439  // First create a temporary that is aligned for both the load and store.
1440  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1441  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1442  // Then store the float to it.
1443  State.FloatPtr = StackPtr;
1444  MachineFunction &MF = DAG.getMachineFunction();
1445  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1446  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1447  State.FloatPointerInfo);
1448 
1449  SDValue IntPtr;
1450  if (DataLayout.isBigEndian()) {
1451  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1452  // Load out a legal integer with the same sign bit as the float.
1453  IntPtr = StackPtr;
1454  State.IntPointerInfo = State.FloatPointerInfo;
1455  } else {
1456  // Advance the pointer so that the loaded byte will contain the sign bit.
1457  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1458  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1459  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1460  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1461  ByteOffset);
1462  }
1463 
1464  State.IntPtr = IntPtr;
1465  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1466  State.IntPointerInfo, MVT::i8);
1467  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1468  State.SignBit = 7;
1469 }
1470 
1471 /// Replace the integer value produced by getSignAsIntValue() with a new value
1472 /// and cast the result back to a floating-point type.
1473 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1474  const SDLoc &DL,
1475  SDValue NewIntValue) const {
1476  if (!State.Chain)
1477  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1478 
1479  // Override the part containing the sign bit in the value stored on the stack.
1480  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1481  State.IntPointerInfo, MVT::i8);
1482  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1483  State.FloatPointerInfo);
1484 }
1485 
1486 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1487  SDLoc DL(Node);
1488  SDValue Mag = Node->getOperand(0);
1489  SDValue Sign = Node->getOperand(1);
1490 
1491  // Get sign bit into an integer value.
1492  FloatSignAsInt SignAsInt;
1493  getSignAsIntValue(SignAsInt, DL, Sign);
1494 
1495  EVT IntVT = SignAsInt.IntValue.getValueType();
1496  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1497  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1498  SignMask);
1499 
1500  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1501  EVT FloatVT = Mag.getValueType();
1502  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1503  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1504  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1505  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1506  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1507  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1508  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1509  }
1510 
1511  // Transform Mag value to integer, and clear the sign bit.
1512  FloatSignAsInt MagAsInt;
1513  getSignAsIntValue(MagAsInt, DL, Mag);
1514  EVT MagVT = MagAsInt.IntValue.getValueType();
1515  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1516  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1517  ClearSignMask);
1518 
1519  // Get the signbit at the right position for MagAsInt.
1520  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1521  EVT ShiftVT = IntVT;
1522  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1523  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1524  ShiftVT = MagVT;
1525  }
1526  if (ShiftAmount > 0) {
1527  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1528  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1529  } else if (ShiftAmount < 0) {
1530  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1531  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1532  }
1533  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1534  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1535  }
1536 
1537  // Store the part with the modified sign and convert back to float.
1538  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1539  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1540 }
1541 
1542 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1543  SDLoc DL(Node);
1544  SDValue Value = Node->getOperand(0);
1545 
1546  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1547  EVT FloatVT = Value.getValueType();
1548  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1549  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1550  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1551  }
1552 
1553  // Transform value to integer, clear the sign bit and transform back.
1554  FloatSignAsInt ValueAsInt;
1555  getSignAsIntValue(ValueAsInt, DL, Value);
1556  EVT IntVT = ValueAsInt.IntValue.getValueType();
1557  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1558  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1559  ClearSignMask);
1560  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1561 }
1562 
1563 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1565  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1566  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1567  " not tell us which reg is the stack pointer!");
1568  SDLoc dl(Node);
1569  EVT VT = Node->getValueType(0);
1570  SDValue Tmp1 = SDValue(Node, 0);
1571  SDValue Tmp2 = SDValue(Node, 1);
1572  SDValue Tmp3 = Node->getOperand(2);
1573  SDValue Chain = Tmp1.getOperand(0);
1574 
1575  // Chain the dynamic stack allocation so that it doesn't modify the stack
1576  // pointer when other instructions are using the stack.
1577  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1578 
1579  SDValue Size = Tmp2.getOperand(1);
1580  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1581  Chain = SP.getValue(1);
1582  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1583  unsigned StackAlign =
1584  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1585  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1586  if (Align > StackAlign)
1587  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1588  DAG.getConstant(-(uint64_t)Align, dl, VT));
1589  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1590 
1591  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1592  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1593 
1594  Results.push_back(Tmp1);
1595  Results.push_back(Tmp2);
1596 }
1597 
1598 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1599 /// target.
1600 ///
1601 /// If the SETCC has been legalized using AND / OR, then the legalized node
1602 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1603 /// will be set to false.
1604 ///
1605 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1606 /// then the values of LHS and RHS will be swapped, CC will be set to the
1607 /// new condition, and NeedInvert will be set to false.
1608 ///
1609 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1610 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1611 /// will be set to true. The caller must invert the result of the SETCC with
1612 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1613 /// of a true/false result.
1614 ///
1615 /// \returns true if the SetCC has been legalized, false if it hasn't.
1616 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1617  SDValue &RHS, SDValue &CC,
1618  bool &NeedInvert,
1619  const SDLoc &dl) {
1620  MVT OpVT = LHS.getSimpleValueType();
1621  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1622  NeedInvert = false;
1623  bool NeedSwap = false;
1624  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1625  default: llvm_unreachable("Unknown condition code action!");
1626  case TargetLowering::Legal:
1627  // Nothing to do.
1628  break;
1629  case TargetLowering::Expand: {
1631  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1632  std::swap(LHS, RHS);
1633  CC = DAG.getCondCode(InvCC);
1634  return true;
1635  }
1636  // Swapping operands didn't work. Try inverting the condition.
1637  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1638  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1639  // If inverting the condition is not enough, try swapping operands
1640  // on top of it.
1641  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1642  NeedSwap = true;
1643  }
1644  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1645  CC = DAG.getCondCode(InvCC);
1646  NeedInvert = true;
1647  if (NeedSwap)
1648  std::swap(LHS, RHS);
1649  return true;
1650  }
1651 
1653  unsigned Opc = 0;
1654  switch (CCCode) {
1655  default: llvm_unreachable("Don't know how to expand this condition!");
1656  case ISD::SETO:
1657  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1658  && "If SETO is expanded, SETOEQ must be legal!");
1659  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1660  case ISD::SETUO:
1661  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1662  && "If SETUO is expanded, SETUNE must be legal!");
1663  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1664  case ISD::SETOEQ:
1665  case ISD::SETOGT:
1666  case ISD::SETOGE:
1667  case ISD::SETOLT:
1668  case ISD::SETOLE:
1669  case ISD::SETONE:
1670  case ISD::SETUEQ:
1671  case ISD::SETUNE:
1672  case ISD::SETUGT:
1673  case ISD::SETUGE:
1674  case ISD::SETULT:
1675  case ISD::SETULE:
1676  // If we are floating point, assign and break, otherwise fall through.
1677  if (!OpVT.isInteger()) {
1678  // We can use the 4th bit to tell if we are the unordered
1679  // or ordered version of the opcode.
1680  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1681  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1682  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1683  break;
1684  }
1685  // Fallthrough if we are unsigned integer.
1687  case ISD::SETLE:
1688  case ISD::SETGT:
1689  case ISD::SETGE:
1690  case ISD::SETLT:
1691  case ISD::SETNE:
1692  case ISD::SETEQ:
1693  // If all combinations of inverting the condition and swapping operands
1694  // didn't work then we have no means to expand the condition.
1695  llvm_unreachable("Don't know how to expand this condition!");
1696  }
1697 
1698  SDValue SetCC1, SetCC2;
1699  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1700  // If we aren't the ordered or unorder operation,
1701  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1702  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1703  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1704  } else {
1705  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1706  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1707  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1708  }
1709  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1710  RHS = SDValue();
1711  CC = SDValue();
1712  return true;
1713  }
1714  }
1715  return false;
1716 }
1717 
1718 /// Emit a store/load combination to the stack. This stores
1719 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1720 /// a load from the stack slot to DestVT, extending it if needed.
1721 /// The resultant code need not be legal.
1722 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1723  EVT DestVT, const SDLoc &dl) {
1724  // Create the stack frame object.
1725  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1726  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1727  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1728 
1729  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1730  int SPFI = StackPtrFI->getIndex();
1731  MachinePointerInfo PtrInfo =
1732  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1733 
1734  unsigned SrcSize = SrcOp.getValueSizeInBits();
1735  unsigned SlotSize = SlotVT.getSizeInBits();
1736  unsigned DestSize = DestVT.getSizeInBits();
1737  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1738  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1739 
1740  // Emit a store to the stack slot. Use a truncstore if the input value is
1741  // later than DestVT.
1742  SDValue Store;
1743 
1744  if (SrcSize > SlotSize)
1745  Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo,
1746  SlotVT, SrcAlign);
1747  else {
1748  assert(SrcSize == SlotSize && "Invalid store");
1749  Store =
1750  DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1751  }
1752 
1753  // Result is a load from the stack slot.
1754  if (SlotSize == DestSize)
1755  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1756 
1757  assert(SlotSize < DestSize && "Unknown extension!");
1758  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1759  DestAlign);
1760 }
1761 
1762 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1763  SDLoc dl(Node);
1764  // Create a vector sized/aligned stack slot, store the value to element #0,
1765  // then load the whole vector back out.
1766  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1767 
1768  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1769  int SPFI = StackPtrFI->getIndex();
1770 
1771  SDValue Ch = DAG.getTruncStore(
1772  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1773  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1774  Node->getValueType(0).getVectorElementType());
1775  return DAG.getLoad(
1776  Node->getValueType(0), dl, Ch, StackPtr,
1777  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1778 }
1779 
1780 static bool
1782  const TargetLowering &TLI, SDValue &Res) {
1783  unsigned NumElems = Node->getNumOperands();
1784  SDLoc dl(Node);
1785  EVT VT = Node->getValueType(0);
1786 
1787  // Try to group the scalars into pairs, shuffle the pairs together, then
1788  // shuffle the pairs of pairs together, etc. until the vector has
1789  // been built. This will work only if all of the necessary shuffle masks
1790  // are legal.
1791 
1792  // We do this in two phases; first to check the legality of the shuffles,
1793  // and next, assuming that all shuffles are legal, to create the new nodes.
1794  for (int Phase = 0; Phase < 2; ++Phase) {
1796  NewIntermedVals;
1797  for (unsigned i = 0; i < NumElems; ++i) {
1798  SDValue V = Node->getOperand(i);
1799  if (V.isUndef())
1800  continue;
1801 
1802  SDValue Vec;
1803  if (Phase)
1804  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1805  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1806  }
1807 
1808  while (IntermedVals.size() > 2) {
1809  NewIntermedVals.clear();
1810  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1811  // This vector and the next vector are shuffled together (simply to
1812  // append the one to the other).
1813  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1814 
1815  SmallVector<int, 16> FinalIndices;
1816  FinalIndices.reserve(IntermedVals[i].second.size() +
1817  IntermedVals[i+1].second.size());
1818 
1819  int k = 0;
1820  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1821  ++j, ++k) {
1822  ShuffleVec[k] = j;
1823  FinalIndices.push_back(IntermedVals[i].second[j]);
1824  }
1825  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1826  ++j, ++k) {
1827  ShuffleVec[k] = NumElems + j;
1828  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1829  }
1830 
1831  SDValue Shuffle;
1832  if (Phase)
1833  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1834  IntermedVals[i+1].first,
1835  ShuffleVec);
1836  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1837  return false;
1838  NewIntermedVals.push_back(
1839  std::make_pair(Shuffle, std::move(FinalIndices)));
1840  }
1841 
1842  // If we had an odd number of defined values, then append the last
1843  // element to the array of new vectors.
1844  if ((IntermedVals.size() & 1) != 0)
1845  NewIntermedVals.push_back(IntermedVals.back());
1846 
1847  IntermedVals.swap(NewIntermedVals);
1848  }
1849 
1850  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1851  "Invalid number of intermediate vectors");
1852  SDValue Vec1 = IntermedVals[0].first;
1853  SDValue Vec2;
1854  if (IntermedVals.size() > 1)
1855  Vec2 = IntermedVals[1].first;
1856  else if (Phase)
1857  Vec2 = DAG.getUNDEF(VT);
1858 
1859  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1860  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1861  ShuffleVec[IntermedVals[0].second[i]] = i;
1862  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1863  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1864 
1865  if (Phase)
1866  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1867  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1868  return false;
1869  }
1870 
1871  return true;
1872 }
1873 
1874 /// Expand a BUILD_VECTOR node on targets that don't
1875 /// support the operation, but do support the resultant vector type.
1876 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1877  unsigned NumElems = Node->getNumOperands();
1878  SDValue Value1, Value2;
1879  SDLoc dl(Node);
1880  EVT VT = Node->getValueType(0);
1881  EVT OpVT = Node->getOperand(0).getValueType();
1882  EVT EltVT = VT.getVectorElementType();
1883 
1884  // If the only non-undef value is the low element, turn this into a
1885  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1886  bool isOnlyLowElement = true;
1887  bool MoreThanTwoValues = false;
1888  bool isConstant = true;
1889  for (unsigned i = 0; i < NumElems; ++i) {
1890  SDValue V = Node->getOperand(i);
1891  if (V.isUndef())
1892  continue;
1893  if (i > 0)
1894  isOnlyLowElement = false;
1895  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1896  isConstant = false;
1897 
1898  if (!Value1.getNode()) {
1899  Value1 = V;
1900  } else if (!Value2.getNode()) {
1901  if (V != Value1)
1902  Value2 = V;
1903  } else if (V != Value1 && V != Value2) {
1904  MoreThanTwoValues = true;
1905  }
1906  }
1907 
1908  if (!Value1.getNode())
1909  return DAG.getUNDEF(VT);
1910 
1911  if (isOnlyLowElement)
1912  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1913 
1914  // If all elements are constants, create a load from the constant pool.
1915  if (isConstant) {
1917  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1918  if (ConstantFPSDNode *V =
1919  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1920  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1921  } else if (ConstantSDNode *V =
1922  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1923  if (OpVT==EltVT)
1924  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1925  else {
1926  // If OpVT and EltVT don't match, EltVT is not legal and the
1927  // element values have been promoted/truncated earlier. Undo this;
1928  // we don't want a v16i8 to become a v16i32 for example.
1929  const ConstantInt *CI = V->getConstantIntValue();
1930  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1931  CI->getZExtValue()));
1932  }
1933  } else {
1934  assert(Node->getOperand(i).isUndef());
1935  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1936  CV.push_back(UndefValue::get(OpNTy));
1937  }
1938  }
1939  Constant *CP = ConstantVector::get(CV);
1940  SDValue CPIdx =
1941  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1942  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1943  return DAG.getLoad(
1944  VT, dl, DAG.getEntryNode(), CPIdx,
1945  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1946  Alignment);
1947  }
1948 
1949  SmallSet<SDValue, 16> DefinedValues;
1950  for (unsigned i = 0; i < NumElems; ++i) {
1951  if (Node->getOperand(i).isUndef())
1952  continue;
1953  DefinedValues.insert(Node->getOperand(i));
1954  }
1955 
1956  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1957  if (!MoreThanTwoValues) {
1958  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1959  for (unsigned i = 0; i < NumElems; ++i) {
1960  SDValue V = Node->getOperand(i);
1961  if (V.isUndef())
1962  continue;
1963  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1964  }
1965  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1966  // Get the splatted value into the low element of a vector register.
1967  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1968  SDValue Vec2;
1969  if (Value2.getNode())
1970  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1971  else
1972  Vec2 = DAG.getUNDEF(VT);
1973 
1974  // Return shuffle(LowValVec, undef, <0,0,0,0>)
1975  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1976  }
1977  } else {
1978  SDValue Res;
1979  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
1980  return Res;
1981  }
1982  }
1983 
1984  // Otherwise, we can't handle this case efficiently.
1985  return ExpandVectorBuildThroughStack(Node);
1986 }
1987 
1988 // Expand a node into a call to a libcall. If the result value
1989 // does not fit into a register, return the lo part and set the hi part to the
1990 // by-reg argument. If it does fit into a single register, return the result
1991 // and leave the Hi part unset.
1992 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1993  bool isSigned) {
1995  TargetLowering::ArgListEntry Entry;
1996  for (const SDValue &Op : Node->op_values()) {
1997  EVT ArgVT = Op.getValueType();
1998  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1999  Entry.Node = Op;
2000  Entry.Ty = ArgTy;
2001  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2002  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2003  Args.push_back(Entry);
2004  }
2005  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2006  TLI.getPointerTy(DAG.getDataLayout()));
2007 
2008  EVT RetVT = Node->getValueType(0);
2009  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2010 
2011  // By default, the input chain to this libcall is the entry node of the
2012  // function. If the libcall is going to be emitted as a tail call then
2013  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2014  // node which is being folded has a non-entry input chain.
2015  SDValue InChain = DAG.getEntryNode();
2016 
2017  // isTailCall may be true since the callee does not reference caller stack
2018  // frame. Check if it's in the right position and that the return types match.
2019  SDValue TCChain = InChain;
2020  const Function &F = DAG.getMachineFunction().getFunction();
2021  bool isTailCall =
2022  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2023  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2024  if (isTailCall)
2025  InChain = TCChain;
2026 
2028  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2029  CLI.setDebugLoc(SDLoc(Node))
2030  .setChain(InChain)
2031  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2032  std::move(Args))
2033  .setTailCall(isTailCall)
2034  .setSExtResult(signExtend)
2035  .setZExtResult(!signExtend)
2037 
2038  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2039 
2040  if (!CallInfo.second.getNode()) {
2041  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump());
2042  // It's a tailcall, return the chain (which is the DAG root).
2043  return DAG.getRoot();
2044  }
2045 
2046  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump());
2047  return CallInfo.first;
2048 }
2049 
2050 // Expand a node into a call to a libcall. Similar to
2051 // ExpandLibCall except that the first operand is the in-chain.
2052 std::pair<SDValue, SDValue>
2053 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2054  SDNode *Node,
2055  bool isSigned) {
2056  SDValue InChain = Node->getOperand(0);
2057 
2059  TargetLowering::ArgListEntry Entry;
2060  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2061  EVT ArgVT = Node->getOperand(i).getValueType();
2062  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2063  Entry.Node = Node->getOperand(i);
2064  Entry.Ty = ArgTy;
2065  Entry.IsSExt = isSigned;
2066  Entry.IsZExt = !isSigned;
2067  Args.push_back(Entry);
2068  }
2069  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2070  TLI.getPointerTy(DAG.getDataLayout()));
2071 
2072  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2073 
2075  CLI.setDebugLoc(SDLoc(Node))
2076  .setChain(InChain)
2077  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2078  std::move(Args))
2079  .setSExtResult(isSigned)
2080  .setZExtResult(!isSigned);
2081 
2082  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2083 
2084  return CallInfo;
2085 }
2086 
2087 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2088  RTLIB::Libcall Call_F32,
2089  RTLIB::Libcall Call_F64,
2090  RTLIB::Libcall Call_F80,
2091  RTLIB::Libcall Call_F128,
2092  RTLIB::Libcall Call_PPCF128) {
2093  if (Node->isStrictFPOpcode())
2094  Node = DAG.mutateStrictFPToFP(Node);
2095 
2096  RTLIB::Libcall LC;
2097  switch (Node->getSimpleValueType(0).SimpleTy) {
2098  default: llvm_unreachable("Unexpected request for libcall!");
2099  case MVT::f32: LC = Call_F32; break;
2100  case MVT::f64: LC = Call_F64; break;
2101  case MVT::f80: LC = Call_F80; break;
2102  case MVT::f128: LC = Call_F128; break;
2103  case MVT::ppcf128: LC = Call_PPCF128; break;
2104  }
2105  return ExpandLibCall(LC, Node, false);
2106 }
2107 
2108 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2109  RTLIB::Libcall Call_I8,
2110  RTLIB::Libcall Call_I16,
2111  RTLIB::Libcall Call_I32,
2112  RTLIB::Libcall Call_I64,
2113  RTLIB::Libcall Call_I128) {
2114  RTLIB::Libcall LC;
2115  switch (Node->getSimpleValueType(0).SimpleTy) {
2116  default: llvm_unreachable("Unexpected request for libcall!");
2117  case MVT::i8: LC = Call_I8; break;
2118  case MVT::i16: LC = Call_I16; break;
2119  case MVT::i32: LC = Call_I32; break;
2120  case MVT::i64: LC = Call_I64; break;
2121  case MVT::i128: LC = Call_I128; break;
2122  }
2123  return ExpandLibCall(LC, Node, isSigned);
2124 }
2125 
2126 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2127 void
2128 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2129  SmallVectorImpl<SDValue> &Results) {
2130  unsigned Opcode = Node->getOpcode();
2131  bool isSigned = Opcode == ISD::SDIVREM;
2132 
2133  RTLIB::Libcall LC;
2134  switch (Node->getSimpleValueType(0).SimpleTy) {
2135  default: llvm_unreachable("Unexpected request for libcall!");
2136  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2137  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2138  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2139  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2140  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2141  }
2142 
2143  // The input chain to this libcall is the entry node of the function.
2144  // Legalizing the call will automatically add the previous call to the
2145  // dependence.
2146  SDValue InChain = DAG.getEntryNode();
2147 
2148  EVT RetVT = Node->getValueType(0);
2149  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2150 
2152  TargetLowering::ArgListEntry Entry;
2153  for (const SDValue &Op : Node->op_values()) {
2154  EVT ArgVT = Op.getValueType();
2155  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2156  Entry.Node = Op;
2157  Entry.Ty = ArgTy;
2158  Entry.IsSExt = isSigned;
2159  Entry.IsZExt = !isSigned;
2160  Args.push_back(Entry);
2161  }
2162 
2163  // Also pass the return address of the remainder.
2164  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2165  Entry.Node = FIPtr;
2166  Entry.Ty = RetTy->getPointerTo();
2167  Entry.IsSExt = isSigned;
2168  Entry.IsZExt = !isSigned;
2169  Args.push_back(Entry);
2170 
2171  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2172  TLI.getPointerTy(DAG.getDataLayout()));
2173 
2174  SDLoc dl(Node);
2176  CLI.setDebugLoc(dl)
2177  .setChain(InChain)
2178  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2179  std::move(Args))
2180  .setSExtResult(isSigned)
2181  .setZExtResult(!isSigned);
2182 
2183  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2184 
2185  // Remainder is loaded back from the stack frame.
2186  SDValue Rem =
2187  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2188  Results.push_back(CallInfo.first);
2189  Results.push_back(Rem);
2190 }
2191 
2192 /// Return true if sincos libcall is available.
2193 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2194  RTLIB::Libcall LC;
2195  switch (Node->getSimpleValueType(0).SimpleTy) {
2196  default: llvm_unreachable("Unexpected request for libcall!");
2197  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2198  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2199  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2200  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2201  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2202  }
2203  return TLI.getLibcallName(LC) != nullptr;
2204 }
2205 
2206 /// Only issue sincos libcall if both sin and cos are needed.
2207 static bool useSinCos(SDNode *Node) {
2208  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2209  ? ISD::FCOS : ISD::FSIN;
2210 
2211  SDValue Op0 = Node->getOperand(0);
2212  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2213  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2214  SDNode *User = *UI;
2215  if (User == Node)
2216  continue;
2217  // The other user might have been turned into sincos already.
2218  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2219  return true;
2220  }
2221  return false;
2222 }
2223 
2224 /// Issue libcalls to sincos to compute sin / cos pairs.
2225 void
2226 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2227  SmallVectorImpl<SDValue> &Results) {
2228  RTLIB::Libcall LC;
2229  switch (Node->getSimpleValueType(0).SimpleTy) {
2230  default: llvm_unreachable("Unexpected request for libcall!");
2231  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2232  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2233  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2234  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2235  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2236  }
2237 
2238  // The input chain to this libcall is the entry node of the function.
2239  // Legalizing the call will automatically add the previous call to the
2240  // dependence.
2241  SDValue InChain = DAG.getEntryNode();
2242 
2243  EVT RetVT = Node->getValueType(0);
2244  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2245 
2247  TargetLowering::ArgListEntry Entry;
2248 
2249  // Pass the argument.
2250  Entry.Node = Node->getOperand(0);
2251  Entry.Ty = RetTy;
2252  Entry.IsSExt = false;
2253  Entry.IsZExt = false;
2254  Args.push_back(Entry);
2255 
2256  // Pass the return address of sin.
2257  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2258  Entry.Node = SinPtr;
2259  Entry.Ty = RetTy->getPointerTo();
2260  Entry.IsSExt = false;
2261  Entry.IsZExt = false;
2262  Args.push_back(Entry);
2263 
2264  // Also pass the return address of the cos.
2265  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2266  Entry.Node = CosPtr;
2267  Entry.Ty = RetTy->getPointerTo();
2268  Entry.IsSExt = false;
2269  Entry.IsZExt = false;
2270  Args.push_back(Entry);
2271 
2272  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2273  TLI.getPointerTy(DAG.getDataLayout()));
2274 
2275  SDLoc dl(Node);
2277  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2278  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2279  std::move(Args));
2280 
2281  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2282 
2283  Results.push_back(
2284  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2285  Results.push_back(
2286  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2287 }
2288 
2289 /// This function is responsible for legalizing a
2290 /// INT_TO_FP operation of the specified operand when the target requests that
2291 /// we expand it. At this point, we know that the result and operand types are
2292 /// legal for the target.
2293 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2294  EVT DestVT,
2295  const SDLoc &dl) {
2296  EVT SrcVT = Op0.getValueType();
2297 
2298  // TODO: Should any fast-math-flags be set for the created nodes?
2299  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2300  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2301  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2302  "expansion\n");
2303 
2304  // Get the stack frame index of a 8 byte buffer.
2305  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2306 
2307  // word offset constant for Hi/Lo address computation
2308  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2309  StackSlot.getValueType());
2310  // set up Hi and Lo (into buffer) address based on endian
2311  SDValue Hi = StackSlot;
2312  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2313  StackSlot, WordOff);
2314  if (DAG.getDataLayout().isLittleEndian())
2315  std::swap(Hi, Lo);
2316 
2317  // if signed map to unsigned space
2318  SDValue Op0Mapped;
2319  if (isSigned) {
2320  // constant used to invert sign bit (signed to unsigned mapping)
2321  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2322  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2323  } else {
2324  Op0Mapped = Op0;
2325  }
2326  // store the lo of the constructed double - based on integer input
2327  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2328  MachinePointerInfo());
2329  // initial hi portion of constructed double
2330  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2331  // store the hi of the constructed double - biased exponent
2332  SDValue Store2 =
2333  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2334  // load the constructed double
2335  SDValue Load =
2336  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2337  // FP constant to bias correct the final result
2338  SDValue Bias = DAG.getConstantFP(isSigned ?
2339  BitsToDouble(0x4330000080000000ULL) :
2340  BitsToDouble(0x4330000000000000ULL),
2341  dl, MVT::f64);
2342  // subtract the bias
2343  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2344  // final result
2345  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2346  return Result;
2347  }
2348  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2349  // Code below here assumes !isSigned without checking again.
2350 
2351  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2352 
2353  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2354  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2355  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2356  Four = DAG.getIntPtrConstant(4, dl);
2357  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2358  SignSet, Four, Zero);
2359 
2360  // If the sign bit of the integer is set, the large number will be treated
2361  // as a negative number. To counteract this, the dynamic code adds an
2362  // offset depending on the data type.
2363  uint64_t FF;
2364  switch (SrcVT.getSimpleVT().SimpleTy) {
2365  default: llvm_unreachable("Unsupported integer type!");
2366  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2367  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2368  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2369  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2370  }
2371  if (DAG.getDataLayout().isLittleEndian())
2372  FF <<= 32;
2373  Constant *FudgeFactor = ConstantInt::get(
2374  Type::getInt64Ty(*DAG.getContext()), FF);
2375 
2376  SDValue CPIdx =
2377  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2378  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2379  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2380  Alignment = std::min(Alignment, 4u);
2381  SDValue FudgeInReg;
2382  if (DestVT == MVT::f32)
2383  FudgeInReg = DAG.getLoad(
2384  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2385  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2386  Alignment);
2387  else {
2388  SDValue Load = DAG.getExtLoad(
2389  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2390  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2391  Alignment);
2392  HandleSDNode Handle(Load);
2393  LegalizeOp(Load.getNode());
2394  FudgeInReg = Handle.getValue();
2395  }
2396 
2397  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2398 }
2399 
2400 /// This function is responsible for legalizing a
2401 /// *INT_TO_FP operation of the specified operand when the target requests that
2402 /// we promote it. At this point, we know that the result and operand types are
2403 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2404 /// operation that takes a larger input.
2405 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2406  bool isSigned,
2407  const SDLoc &dl) {
2408  // First step, figure out the appropriate *INT_TO_FP operation to use.
2409  EVT NewInTy = LegalOp.getValueType();
2410 
2411  unsigned OpToUse = 0;
2412 
2413  // Scan for the appropriate larger type to use.
2414  while (true) {
2415  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2416  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2417 
2418  // If the target supports SINT_TO_FP of this type, use it.
2419  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2420  OpToUse = ISD::SINT_TO_FP;
2421  break;
2422  }
2423  if (isSigned) continue;
2424 
2425  // If the target supports UINT_TO_FP of this type, use it.
2426  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2427  OpToUse = ISD::UINT_TO_FP;
2428  break;
2429  }
2430 
2431  // Otherwise, try a larger type.
2432  }
2433 
2434  // Okay, we found the operation and type to use. Zero extend our input to the
2435  // desired type then run the operation on it.
2436  return DAG.getNode(OpToUse, dl, DestVT,
2437  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2438  dl, NewInTy, LegalOp));
2439 }
2440 
2441 /// This function is responsible for legalizing a
2442 /// FP_TO_*INT operation of the specified operand when the target requests that
2443 /// we promote it. At this point, we know that the result and operand types are
2444 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2445 /// operation that returns a larger result.
2446 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2447  bool isSigned,
2448  const SDLoc &dl) {
2449  // First step, figure out the appropriate FP_TO*INT operation to use.
2450  EVT NewOutTy = DestVT;
2451 
2452  unsigned OpToUse = 0;
2453 
2454  // Scan for the appropriate larger type to use.
2455  while (true) {
2456  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2457  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2458 
2459  // A larger signed type can hold all unsigned values of the requested type,
2460  // so using FP_TO_SINT is valid
2461  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2462  OpToUse = ISD::FP_TO_SINT;
2463  break;
2464  }
2465 
2466  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2467  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2468  OpToUse = ISD::FP_TO_UINT;
2469  break;
2470  }
2471 
2472  // Otherwise, try a larger type.
2473  }
2474 
2475  // Okay, we found the operation and type to use.
2476  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2477 
2478  // Truncate the result of the extended FP_TO_*INT operation to the desired
2479  // size.
2480  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2481 }
2482 
2483 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2484 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2485  EVT VT = Op.getValueType();
2486  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2487  unsigned Sz = VT.getScalarSizeInBits();
2488 
2489  SDValue Tmp, Tmp2, Tmp3;
2490 
2491  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2492  // and finally the i1 pairs.
2493  // TODO: We can easily support i4/i2 legal types if any target ever does.
2494  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2495  // Create the masks - repeating the pattern every byte.
2496  APInt MaskHi4(Sz, 0), MaskHi2(Sz, 0), MaskHi1(Sz, 0);
2497  APInt MaskLo4(Sz, 0), MaskLo2(Sz, 0), MaskLo1(Sz, 0);
2498  for (unsigned J = 0; J != Sz; J += 8) {
2499  MaskHi4 = MaskHi4 | (0xF0ull << J);
2500  MaskLo4 = MaskLo4 | (0x0Full << J);
2501  MaskHi2 = MaskHi2 | (0xCCull << J);
2502  MaskLo2 = MaskLo2 | (0x33ull << J);
2503  MaskHi1 = MaskHi1 | (0xAAull << J);
2504  MaskLo1 = MaskLo1 | (0x55ull << J);
2505  }
2506 
2507  // BSWAP if the type is wider than a single byte.
2508  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2509 
2510  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2511  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2512  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2513  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2514  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2515  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2516 
2517  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2518  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2519  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2520  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2521  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2522  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2523 
2524  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2525  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2526  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2527  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2528  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2529  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2530  return Tmp;
2531  }
2532 
2533  Tmp = DAG.getConstant(0, dl, VT);
2534  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2535  if (I < J)
2536  Tmp2 =
2537  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2538  else
2539  Tmp2 =
2540  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2541 
2542  APInt Shift(Sz, 1);
2543  Shift <<= J;
2544  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2545  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2546  }
2547 
2548  return Tmp;
2549 }
2550 
2551 /// Open code the operations for BSWAP of the specified operation.
2552 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2553  EVT VT = Op.getValueType();
2554  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2555  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2556  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2557  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2558  case MVT::i16:
2559  Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2560  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2561  return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2562  case MVT::i32:
2563  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2564  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2565  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2566  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2567  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2568  DAG.getConstant(0xFF0000, dl, VT));
2569  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2570  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2571  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2572  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2573  case MVT::i64:
2574  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2575  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2576  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2577  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2578  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2579  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2580  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2581  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2582  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2583  DAG.getConstant(255ULL<<48, dl, VT));
2584  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2585  DAG.getConstant(255ULL<<40, dl, VT));
2586  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2587  DAG.getConstant(255ULL<<32, dl, VT));
2588  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2589  DAG.getConstant(255ULL<<24, dl, VT));
2590  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2591  DAG.getConstant(255ULL<<16, dl, VT));
2592  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2593  DAG.getConstant(255ULL<<8 , dl, VT));
2594  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2595  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2596  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2597  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2598  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2599  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2600  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2601  }
2602 }
2603 
2604 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2605  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2607  SDLoc dl(Node);
2608  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2609  bool NeedInvert;
2610  switch (Node->getOpcode()) {
2611  case ISD::ABS:
2612  if (TLI.expandABS(Node, Tmp1, DAG))
2613  Results.push_back(Tmp1);
2614  break;
2615  case ISD::CTPOP:
2616  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2617  Results.push_back(Tmp1);
2618  break;
2619  case ISD::CTLZ:
2620  case ISD::CTLZ_ZERO_UNDEF:
2621  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2622  Results.push_back(Tmp1);
2623  break;
2624  case ISD::CTTZ:
2625  case ISD::CTTZ_ZERO_UNDEF:
2626  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2627  Results.push_back(Tmp1);
2628  break;
2629  case ISD::BITREVERSE:
2630  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2631  break;
2632  case ISD::BSWAP:
2633  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2634  break;
2635  case ISD::FRAMEADDR:
2636  case ISD::RETURNADDR:
2638  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2639  break;
2640  case ISD::EH_DWARF_CFA: {
2641  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2642  TLI.getPointerTy(DAG.getDataLayout()));
2643  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2644  CfaArg.getValueType(),
2645  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2646  CfaArg.getValueType()),
2647  CfaArg);
2648  SDValue FA = DAG.getNode(
2649  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2650  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2651  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2652  FA, Offset));
2653  break;
2654  }
2655  case ISD::FLT_ROUNDS_:
2656  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2657  break;
2658  case ISD::EH_RETURN:
2659  case ISD::EH_LABEL:
2660  case ISD::PREFETCH:
2661  case ISD::VAEND:
2662  case ISD::EH_SJLJ_LONGJMP:
2663  // If the target didn't expand these, there's nothing to do, so just
2664  // preserve the chain and be done.
2665  Results.push_back(Node->getOperand(0));
2666  break;
2667  case ISD::READCYCLECOUNTER:
2668  // If the target didn't expand this, just return 'zero' and preserve the
2669  // chain.
2670  Results.append(Node->getNumValues() - 1,
2671  DAG.getConstant(0, dl, Node->getValueType(0)));
2672  Results.push_back(Node->getOperand(0));
2673  break;
2674  case ISD::EH_SJLJ_SETJMP:
2675  // If the target didn't expand this, just return 'zero' and preserve the
2676  // chain.
2677  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2678  Results.push_back(Node->getOperand(0));
2679  break;
2680  case ISD::ATOMIC_LOAD: {
2681  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2682  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2683  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2684  SDValue Swap = DAG.getAtomicCmpSwap(
2685  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2686  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2687  cast<AtomicSDNode>(Node)->getMemOperand());
2688  Results.push_back(Swap.getValue(0));
2689  Results.push_back(Swap.getValue(1));
2690  break;
2691  }
2692  case ISD::ATOMIC_STORE: {
2693  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2694  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2695  cast<AtomicSDNode>(Node)->getMemoryVT(),
2696  Node->getOperand(0),
2697  Node->getOperand(1), Node->getOperand(2),
2698  cast<AtomicSDNode>(Node)->getMemOperand());
2699  Results.push_back(Swap.getValue(1));
2700  break;
2701  }
2703  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2704  // splits out the success value as a comparison. Expanding the resulting
2705  // ATOMIC_CMP_SWAP will produce a libcall.
2706  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2707  SDValue Res = DAG.getAtomicCmpSwap(
2708  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2709  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2710  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2711 
2712  SDValue ExtRes = Res;
2713  SDValue LHS = Res;
2714  SDValue RHS = Node->getOperand(1);
2715 
2716  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2717  EVT OuterType = Node->getValueType(0);
2718  switch (TLI.getExtendForAtomicOps()) {
2719  case ISD::SIGN_EXTEND:
2720  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2721  DAG.getValueType(AtomicType));
2722  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2723  Node->getOperand(2), DAG.getValueType(AtomicType));
2724  ExtRes = LHS;
2725  break;
2726  case ISD::ZERO_EXTEND:
2727  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2728  DAG.getValueType(AtomicType));
2729  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2730  ExtRes = LHS;
2731  break;
2732  case ISD::ANY_EXTEND:
2733  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2734  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2735  break;
2736  default:
2737  llvm_unreachable("Invalid atomic op extension");
2738  }
2739 
2740  SDValue Success =
2741  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2742 
2743  Results.push_back(ExtRes.getValue(0));
2744  Results.push_back(Success);
2745  Results.push_back(Res.getValue(1));
2746  break;
2747  }
2749  ExpandDYNAMIC_STACKALLOC(Node, Results);
2750  break;
2751  case ISD::MERGE_VALUES:
2752  for (unsigned i = 0; i < Node->getNumValues(); i++)
2753  Results.push_back(Node->getOperand(i));
2754  break;
2755  case ISD::UNDEF: {
2756  EVT VT = Node->getValueType(0);
2757  if (VT.isInteger())
2758  Results.push_back(DAG.getConstant(0, dl, VT));
2759  else {
2760  assert(VT.isFloatingPoint() && "Unknown value type!");
2761  Results.push_back(DAG.getConstantFP(0, dl, VT));
2762  }
2763  break;
2764  }
2765  case ISD::FP_ROUND:
2766  case ISD::BITCAST:
2767  Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2768  Node->getValueType(0), dl);
2769  Results.push_back(Tmp1);
2770  break;
2771  case ISD::FP_EXTEND:
2772  Tmp1 = EmitStackConvert(Node->getOperand(0),
2773  Node->getOperand(0).getValueType(),
2774  Node->getValueType(0), dl);
2775  Results.push_back(Tmp1);
2776  break;
2777  case ISD::SIGN_EXTEND_INREG: {
2778  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2779  EVT VT = Node->getValueType(0);
2780 
2781  // An in-register sign-extend of a boolean is a negation:
2782  // 'true' (1) sign-extended is -1.
2783  // 'false' (0) sign-extended is 0.
2784  // However, we must mask the high bits of the source operand because the
2785  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2786 
2787  // TODO: Do this for vectors too?
2788  if (ExtraVT.getSizeInBits() == 1) {
2789  SDValue One = DAG.getConstant(1, dl, VT);
2790  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2791  SDValue Zero = DAG.getConstant(0, dl, VT);
2792  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2793  Results.push_back(Neg);
2794  break;
2795  }
2796 
2797  // NOTE: we could fall back on load/store here too for targets without
2798  // SRA. However, it is doubtful that any exist.
2799  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2800  unsigned BitsDiff = VT.getScalarSizeInBits() -
2801  ExtraVT.getScalarSizeInBits();
2802  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2803  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2804  Node->getOperand(0), ShiftCst);
2805  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2806  Results.push_back(Tmp1);
2807  break;
2808  }
2809  case ISD::FP_ROUND_INREG: {
2810  // The only way we can lower this is to turn it into a TRUNCSTORE,
2811  // EXTLOAD pair, targeting a temporary location (a stack slot).
2812 
2813  // NOTE: there is a choice here between constantly creating new stack
2814  // slots and always reusing the same one. We currently always create
2815  // new ones, as reuse may inhibit scheduling.
2816  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2817  Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2818  Node->getValueType(0), dl);
2819  Results.push_back(Tmp1);
2820  break;
2821  }
2822  case ISD::UINT_TO_FP:
2823  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2824  Results.push_back(Tmp1);
2825  break;
2826  }
2828  case ISD::SINT_TO_FP:
2829  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2830  Node->getOperand(0), Node->getValueType(0), dl);
2831  Results.push_back(Tmp1);
2832  break;
2833  case ISD::FP_TO_SINT:
2834  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2835  Results.push_back(Tmp1);
2836  break;
2837  case ISD::FP_TO_UINT:
2838  if (TLI.expandFP_TO_UINT(Node, Tmp1, DAG))
2839  Results.push_back(Tmp1);
2840  break;
2841  case ISD::VAARG:
2842  Results.push_back(DAG.expandVAArg(Node));
2843  Results.push_back(Results[0].getValue(1));
2844  break;
2845  case ISD::VACOPY:
2846  Results.push_back(DAG.expandVACopy(Node));
2847  break;
2849  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2850  // This must be an access of the only element. Return it.
2851  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2852  Node->getOperand(0));
2853  else
2854  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2855  Results.push_back(Tmp1);
2856  break;
2858  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2859  break;
2860  case ISD::INSERT_SUBVECTOR:
2861  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2862  break;
2863  case ISD::CONCAT_VECTORS:
2864  Results.push_back(ExpandVectorBuildThroughStack(Node));
2865  break;
2866  case ISD::SCALAR_TO_VECTOR:
2867  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2868  break;
2870  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2871  Node->getOperand(1),
2872  Node->getOperand(2), dl));
2873  break;
2874  case ISD::VECTOR_SHUFFLE: {
2875  SmallVector<int, 32> NewMask;
2876  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2877 
2878  EVT VT = Node->getValueType(0);
2879  EVT EltVT = VT.getVectorElementType();
2880  SDValue Op0 = Node->getOperand(0);
2881  SDValue Op1 = Node->getOperand(1);
2882  if (!TLI.isTypeLegal(EltVT)) {
2883  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2884 
2885  // BUILD_VECTOR operands are allowed to be wider than the element type.
2886  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2887  // it.
2888  if (NewEltVT.bitsLT(EltVT)) {
2889  // Convert shuffle node.
2890  // If original node was v4i64 and the new EltVT is i32,
2891  // cast operands to v8i32 and re-build the mask.
2892 
2893  // Calculate new VT, the size of the new VT should be equal to original.
2894  EVT NewVT =
2895  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2896  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2897  assert(NewVT.bitsEq(VT));
2898 
2899  // cast operands to new VT
2900  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2901  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2902 
2903  // Convert the shuffle mask
2904  unsigned int factor =
2906 
2907  // EltVT gets smaller
2908  assert(factor > 0);
2909 
2910  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2911  if (Mask[i] < 0) {
2912  for (unsigned fi = 0; fi < factor; ++fi)
2913  NewMask.push_back(Mask[i]);
2914  }
2915  else {
2916  for (unsigned fi = 0; fi < factor; ++fi)
2917  NewMask.push_back(Mask[i]*factor+fi);
2918  }
2919  }
2920  Mask = NewMask;
2921  VT = NewVT;
2922  }
2923  EltVT = NewEltVT;
2924  }
2925  unsigned NumElems = VT.getVectorNumElements();
2927  for (unsigned i = 0; i != NumElems; ++i) {
2928  if (Mask[i] < 0) {
2929  Ops.push_back(DAG.getUNDEF(EltVT));
2930  continue;
2931  }
2932  unsigned Idx = Mask[i];
2933  if (Idx < NumElems)
2934  Ops.push_back(DAG.getNode(
2935  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
2936  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2937  else
2938  Ops.push_back(DAG.getNode(
2939  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
2940  DAG.getConstant(Idx - NumElems, dl,
2941  TLI.getVectorIdxTy(DAG.getDataLayout()))));
2942  }
2943 
2944  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
2945  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2946  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2947  Results.push_back(Tmp1);
2948  break;
2949  }
2950  case ISD::EXTRACT_ELEMENT: {
2951  EVT OpTy = Node->getOperand(0).getValueType();
2952  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2953  // 1 -> Hi
2954  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2955  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
2956  TLI.getShiftAmountTy(
2957  Node->getOperand(0).getValueType(),
2958  DAG.getDataLayout())));
2959  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2960  } else {
2961  // 0 -> Lo
2962  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2963  Node->getOperand(0));
2964  }
2965  Results.push_back(Tmp1);
2966  break;
2967  }
2968  case ISD::STACKSAVE:
2969  // Expand to CopyFromReg if the target set
2970  // StackPointerRegisterToSaveRestore.
2971  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2972  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2973  Node->getValueType(0)));
2974  Results.push_back(Results[0].getValue(1));
2975  } else {
2976  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2977  Results.push_back(Node->getOperand(0));
2978  }
2979  break;
2980  case ISD::STACKRESTORE:
2981  // Expand to CopyToReg if the target set
2982  // StackPointerRegisterToSaveRestore.
2983  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2984  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2985  Node->getOperand(1)));
2986  } else {
2987  Results.push_back(Node->getOperand(0));
2988  }
2989  break;
2991  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2992  Results.push_back(Results[0].getValue(0));
2993  break;
2994  case ISD::FCOPYSIGN:
2995  Results.push_back(ExpandFCOPYSIGN(Node));
2996  break;
2997  case ISD::FNEG:
2998  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2999  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3000  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3001  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3002  Node->getOperand(0));
3003  Results.push_back(Tmp1);
3004  break;
3005  case ISD::FABS:
3006  Results.push_back(ExpandFABS(Node));
3007  break;
3008  case ISD::SMIN:
3009  case ISD::SMAX:
3010  case ISD::UMIN:
3011  case ISD::UMAX: {
3012  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3013  ISD::CondCode Pred;
3014  switch (Node->getOpcode()) {
3015  default: llvm_unreachable("How did we get here?");
3016  case ISD::SMAX: Pred = ISD::SETGT; break;
3017  case ISD::SMIN: Pred = ISD::SETLT; break;
3018  case ISD::UMAX: Pred = ISD::SETUGT; break;
3019  case ISD::UMIN: Pred = ISD::SETULT; break;
3020  }
3021  Tmp1 = Node->getOperand(0);
3022  Tmp2 = Node->getOperand(1);
3023  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3024  Results.push_back(Tmp1);
3025  break;
3026  }
3027  case ISD::FMINNUM:
3028  case ISD::FMAXNUM: {
3029  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3030  Results.push_back(Expanded);
3031  break;
3032  }
3033  case ISD::FSIN:
3034  case ISD::FCOS: {
3035  EVT VT = Node->getValueType(0);
3036  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3037  // fcos which share the same operand and both are used.
3038  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3039  isSinCosLibcallAvailable(Node, TLI))
3040  && useSinCos(Node)) {
3041  SDVTList VTs = DAG.getVTList(VT, VT);
3042  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3043  if (Node->getOpcode() == ISD::FCOS)
3044  Tmp1 = Tmp1.getValue(1);
3045  Results.push_back(Tmp1);
3046  }
3047  break;
3048  }
3049  case ISD::FMAD:
3050  llvm_unreachable("Illegal fmad should never be formed");
3051 
3052  case ISD::FP16_TO_FP:
3053  if (Node->getValueType(0) != MVT::f32) {
3054  // We can extend to types bigger than f32 in two steps without changing
3055  // the result. Since "f16 -> f32" is much more commonly available, give
3056  // CodeGen the option of emitting that before resorting to a libcall.
3057  SDValue Res =
3058  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3059  Results.push_back(
3060  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3061  }
3062  break;
3063  case ISD::FP_TO_FP16:
3064  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3065  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3066  SDValue Op = Node->getOperand(0);
3067  MVT SVT = Op.getSimpleValueType();
3068  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3069  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3070  // Under fastmath, we can expand this node into a fround followed by
3071  // a float-half conversion.
3072  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3073  DAG.getIntPtrConstant(0, dl));
3074  Results.push_back(
3075  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3076  }
3077  }
3078  break;
3079  case ISD::ConstantFP: {
3080  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3081  // Check to see if this FP immediate is already legal.
3082  // If this is a legal constant, turn it into a TargetConstantFP node.
3083  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3084  Results.push_back(ExpandConstantFP(CFP, true));
3085  break;
3086  }
3087  case ISD::Constant: {
3088  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3089  Results.push_back(ExpandConstant(CP));
3090  break;
3091  }
3092  case ISD::FSUB: {
3093  EVT VT = Node->getValueType(0);
3094  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3095  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3096  const SDNodeFlags Flags = Node->getFlags();
3097  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3098  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3099  Results.push_back(Tmp1);
3100  }
3101  break;
3102  }
3103  case ISD::SUB: {
3104  EVT VT = Node->getValueType(0);
3105  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3106  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3107  "Don't know how to expand this subtraction!");
3108  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3109  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3110  VT));
3111  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3112  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3113  break;
3114  }
3115  case ISD::UREM:
3116  case ISD::SREM: {
3117  EVT VT = Node->getValueType(0);
3118  bool isSigned = Node->getOpcode() == ISD::SREM;
3119  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3120  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3121  Tmp2 = Node->getOperand(0);
3122  Tmp3 = Node->getOperand(1);
3123  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3124  SDVTList VTs = DAG.getVTList(VT, VT);
3125  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3126  Results.push_back(Tmp1);
3127  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3128  // X % Y -> X-X/Y*Y
3129  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3130  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3131  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3132  Results.push_back(Tmp1);
3133  }
3134  break;
3135  }
3136  case ISD::UDIV:
3137  case ISD::SDIV: {
3138  bool isSigned = Node->getOpcode() == ISD::SDIV;
3139  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3140  EVT VT = Node->getValueType(0);
3141  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3142  SDVTList VTs = DAG.getVTList(VT, VT);
3143  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3144  Node->getOperand(1));
3145  Results.push_back(Tmp1);
3146  }
3147  break;
3148  }
3149  case ISD::MULHU:
3150  case ISD::MULHS: {
3151  unsigned ExpandOpcode =
3153  EVT VT = Node->getValueType(0);
3154  SDVTList VTs = DAG.getVTList(VT, VT);
3155 
3156  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3157  Node->getOperand(1));
3158  Results.push_back(Tmp1.getValue(1));
3159  break;
3160  }
3161  case ISD::UMUL_LOHI:
3162  case ISD::SMUL_LOHI: {
3163  SDValue LHS = Node->getOperand(0);
3164  SDValue RHS = Node->getOperand(1);
3165  MVT VT = LHS.getSimpleValueType();
3166  unsigned MULHOpcode =
3168 
3169  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3170  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3171  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3172  break;
3173  }
3174 
3175  SmallVector<SDValue, 4> Halves;
3176  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3177  assert(TLI.isTypeLegal(HalfType));
3178  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3179  HalfType, DAG,
3181  for (unsigned i = 0; i < 2; ++i) {
3182  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3183  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3184  SDValue Shift = DAG.getConstant(
3185  HalfType.getScalarSizeInBits(), dl,
3186  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3187  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3188  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3189  }
3190  break;
3191  }
3192  break;
3193  }
3194  case ISD::MUL: {
3195  EVT VT = Node->getValueType(0);
3196  SDVTList VTs = DAG.getVTList(VT, VT);
3197  // See if multiply or divide can be lowered using two-result operations.
3198  // We just need the low half of the multiply; try both the signed
3199  // and unsigned forms. If the target supports both SMUL_LOHI and
3200  // UMUL_LOHI, form a preference by checking which forms of plain
3201  // MULH it supports.
3202  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3203  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3204  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3205  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3206  unsigned OpToUse = 0;
3207  if (HasSMUL_LOHI && !HasMULHS) {
3208  OpToUse = ISD::SMUL_LOHI;
3209  } else if (HasUMUL_LOHI && !HasMULHU) {
3210  OpToUse = ISD::UMUL_LOHI;
3211  } else if (HasSMUL_LOHI) {
3212  OpToUse = ISD::SMUL_LOHI;
3213  } else if (HasUMUL_LOHI) {
3214  OpToUse = ISD::UMUL_LOHI;
3215  }
3216  if (OpToUse) {
3217  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3218  Node->getOperand(1)));
3219  break;
3220  }
3221 
3222  SDValue Lo, Hi;
3223  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3224  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3225  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3226  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3227  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3228  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3230  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3231  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3232  SDValue Shift =
3233  DAG.getConstant(HalfType.getSizeInBits(), dl,
3234  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3235  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3236  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3237  }
3238  break;
3239  }
3240  case ISD::FSHL:
3241  case ISD::FSHR:
3242  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3243  Results.push_back(Tmp1);
3244  break;
3245  case ISD::ROTL:
3246  case ISD::ROTR:
3247  if (TLI.expandROT(Node, Tmp1, DAG))
3248  Results.push_back(Tmp1);
3249  break;
3250  case ISD::SADDSAT:
3251  case ISD::UADDSAT:
3252  case ISD::SSUBSAT:
3253  case ISD::USUBSAT:
3254  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3255  break;
3256  case ISD::SMULFIX:
3257  case ISD::UMULFIX:
3258  Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3259  break;
3260  case ISD::SADDO:
3261  case ISD::SSUBO: {
3262  SDValue LHS = Node->getOperand(0);
3263  SDValue RHS = Node->getOperand(1);
3264  SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3265  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3266  LHS, RHS);
3267  Results.push_back(Sum);
3268  EVT ResultType = Node->getValueType(1);
3269  EVT OType = getSetCCResultType(Node->getValueType(0));
3270 
3271  SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3272 
3273  // LHSSign -> LHS >= 0
3274  // RHSSign -> RHS >= 0
3275  // SumSign -> Sum >= 0
3276  //
3277  // Add:
3278  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3279  // Sub:
3280  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3281  SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3282  SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3283  SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3284  Node->getOpcode() == ISD::SADDO ?
3286 
3287  SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3288  SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3289 
3290  SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3291  Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3292  break;
3293  }
3294  case ISD::UADDO:
3295  case ISD::USUBO: {
3296  SDValue LHS = Node->getOperand(0);
3297  SDValue RHS = Node->getOperand(1);
3298  bool IsAdd = Node->getOpcode() == ISD::UADDO;
3299  // If ADD/SUBCARRY is legal, use that instead.
3300  unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
3301  if (TLI.isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {
3302  SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1));
3303  SDValue NodeCarry = DAG.getNode(OpcCarry, dl, Node->getVTList(),
3304  { LHS, RHS, CarryIn });
3305  Results.push_back(SDValue(NodeCarry.getNode(), 0));
3306  Results.push_back(SDValue(NodeCarry.getNode(), 1));
3307  break;
3308  }
3309 
3310  SDValue Sum = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
3311  LHS.getValueType(), LHS, RHS);
3312  Results.push_back(Sum);
3313 
3314  EVT ResultType = Node->getValueType(1);
3315  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3316  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3317  SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3318 
3319  Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3320  break;
3321  }
3322  case ISD::UMULO:
3323  case ISD::SMULO: {
3324  SDValue Result, Overflow;
3325  if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3326  Results.push_back(Result);
3327  Results.push_back(Overflow);
3328  }
3329  break;
3330  }
3331  case ISD::BUILD_PAIR: {
3332  EVT PairTy = Node->getValueType(0);
3333  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3334  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3335  Tmp2 = DAG.getNode(
3336  ISD::SHL, dl, PairTy, Tmp2,
3337  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3338  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3339  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3340  break;
3341  }
3342  case ISD::SELECT:
3343  Tmp1 = Node->getOperand(0);
3344  Tmp2 = Node->getOperand(1);
3345  Tmp3 = Node->getOperand(2);
3346  if (Tmp1.getOpcode() == ISD::SETCC) {
3347  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3348  Tmp2, Tmp3,
3349  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3350  } else {
3351  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3352  DAG.getConstant(0, dl, Tmp1.getValueType()),
3353  Tmp2, Tmp3, ISD::SETNE);
3354  }
3355  Results.push_back(Tmp1);
3356  break;
3357  case ISD::BR_JT: {
3358  SDValue Chain = Node->getOperand(0);
3359  SDValue Table = Node->getOperand(1);
3360  SDValue Index = Node->getOperand(2);
3361 
3362  const DataLayout &TD = DAG.getDataLayout();
3363  EVT PTy = TLI.getPointerTy(TD);
3364 
3365  unsigned EntrySize =
3366  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3367 
3368  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3369  // This transformation needs to be done here since otherwise the MIPS
3370  // backend will end up emitting a three instruction multiply sequence
3371  // instead of a single shift and MSP430 will call a runtime function.
3372  if (llvm::isPowerOf2_32(EntrySize))
3373  Index = DAG.getNode(
3374  ISD::SHL, dl, Index.getValueType(), Index,
3375  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3376  else
3377  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3378  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3379  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3380  Index, Table);
3381 
3382  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3383  SDValue LD = DAG.getExtLoad(
3384  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3385  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3386  Addr = LD;
3387  if (TLI.isJumpTableRelative()) {
3388  // For PIC, the sequence is:
3389  // BRIND(load(Jumptable + index) + RelocBase)
3390  // RelocBase can be JumpTable, GOT or some sort of global base.
3391  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3392  TLI.getPICJumpTableRelocBase(Table, DAG));
3393  }
3394 
3395  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3396  Results.push_back(Tmp1);
3397  break;
3398  }
3399  case ISD::BRCOND:
3400  // Expand brcond's setcc into its constituent parts and create a BR_CC
3401  // Node.
3402  Tmp1 = Node->getOperand(0);
3403  Tmp2 = Node->getOperand(1);
3404  if (Tmp2.getOpcode() == ISD::SETCC) {
3405  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3406  Tmp1, Tmp2.getOperand(2),
3407  Tmp2.getOperand(0), Tmp2.getOperand(1),
3408  Node->getOperand(2));
3409  } else {
3410  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3411  if (Tmp2.isUndef() ||
3412  (Tmp2.getOpcode() == ISD::AND &&
3413  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3414  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3415  Tmp3 = Tmp2;
3416  else
3417  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3418  DAG.getConstant(1, dl, Tmp2.getValueType()));
3419  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3420  DAG.getCondCode(ISD::SETNE), Tmp3,
3421  DAG.getConstant(0, dl, Tmp3.getValueType()),
3422  Node->getOperand(2));
3423  }
3424  Results.push_back(Tmp1);
3425  break;
3426  case ISD::SETCC: {
3427  Tmp1 = Node->getOperand(0);
3428  Tmp2 = Node->getOperand(1);
3429  Tmp3 = Node->getOperand(2);
3430  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3431  Tmp3, NeedInvert, dl);
3432 
3433  if (Legalized) {
3434  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3435  // condition code, create a new SETCC node.
3436  if (Tmp3.getNode())
3437  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3438  Tmp1, Tmp2, Tmp3);
3439 
3440  // If we expanded the SETCC by inverting the condition code, then wrap
3441  // the existing SETCC in a NOT to restore the intended condition.
3442  if (NeedInvert)
3443  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3444 
3445  Results.push_back(Tmp1);
3446  break;
3447  }
3448 
3449  // Otherwise, SETCC for the given comparison type must be completely
3450  // illegal; expand it into a SELECT_CC.
3451  EVT VT = Node->getValueType(0);
3452  int TrueValue;
3453  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3456  TrueValue = 1;
3457  break;
3459  TrueValue = -1;
3460  break;
3461  }
3462  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3463  DAG.getConstant(TrueValue, dl, VT),
3464  DAG.getConstant(0, dl, VT),
3465  Tmp3);
3466  Results.push_back(Tmp1);
3467  break;
3468  }
3469  case ISD::SELECT_CC: {
3470  Tmp1 = Node->getOperand(0); // LHS
3471  Tmp2 = Node->getOperand(1); // RHS
3472  Tmp3 = Node->getOperand(2); // True
3473  Tmp4 = Node->getOperand(3); // False
3474  EVT VT = Node->getValueType(0);
3475  SDValue CC = Node->getOperand(4);
3476  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3477 
3478  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3479  // If the condition code is legal, then we need to expand this
3480  // node using SETCC and SELECT.
3481  EVT CmpVT = Tmp1.getValueType();
3482  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3483  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3484  "expanded.");
3485  EVT CCVT =
3486  TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3487  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3488  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3489  break;
3490  }
3491 
3492  // SELECT_CC is legal, so the condition code must not be.
3493  bool Legalized = false;
3494  // Try to legalize by inverting the condition. This is for targets that
3495  // might support an ordered version of a condition, but not the unordered
3496  // version (or vice versa).
3497  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3498  Tmp1.getValueType().isInteger());
3499  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3500  // Use the new condition code and swap true and false
3501  Legalized = true;
3502  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3503  } else {
3504  // If The inverse is not legal, then try to swap the arguments using
3505  // the inverse condition code.
3506  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3507  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3508  // The swapped inverse condition is legal, so swap true and false,
3509  // lhs and rhs.
3510  Legalized = true;
3511  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3512  }
3513  }
3514 
3515  if (!Legalized) {
3516  Legalized = LegalizeSetCCCondCode(
3517  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3518  dl);
3519 
3520  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3521 
3522  // If we expanded the SETCC by inverting the condition code, then swap
3523  // the True/False operands to match.
3524  if (NeedInvert)
3525  std::swap(Tmp3, Tmp4);
3526 
3527  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3528  // condition code, create a new SELECT_CC node.
3529  if (CC.getNode()) {
3530  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3531  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3532  } else {
3533  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3534  CC = DAG.getCondCode(ISD::SETNE);
3535  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3536  Tmp2, Tmp3, Tmp4, CC);
3537  }
3538  }
3539  Results.push_back(Tmp1);
3540  break;
3541  }
3542  case ISD::BR_CC: {
3543  Tmp1 = Node->getOperand(0); // Chain
3544  Tmp2 = Node->getOperand(2); // LHS
3545  Tmp3 = Node->getOperand(3); // RHS
3546  Tmp4 = Node->getOperand(1); // CC
3547 
3548  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3549  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3550  (void)Legalized;
3551  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3552 
3553  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3554 
3555  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3556  // node.
3557  if (Tmp4.getNode()) {
3558  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3559  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3560  } else {
3561  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3562  Tmp4 = DAG.getCondCode(ISD::SETNE);
3563  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3564  Tmp2, Tmp3, Node->getOperand(4));
3565  }
3566  Results.push_back(Tmp1);
3567  break;
3568  }
3569  case ISD::BUILD_VECTOR:
3570  Results.push_back(ExpandBUILD_VECTOR(Node));
3571  break;
3572  case ISD::SRA:
3573  case ISD::SRL:
3574  case ISD::SHL: {
3575  // Scalarize vector SRA/SRL/SHL.
3576  EVT VT = Node->getValueType(0);
3577  assert(VT.isVector() && "Unable to legalize non-vector shift");
3578  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3579  unsigned NumElem = VT.getVectorNumElements();
3580 
3581  SmallVector<SDValue, 8> Scalars;
3582  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3583  SDValue Ex = DAG.getNode(
3584  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3585  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3586  SDValue Sh = DAG.getNode(
3587  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3588  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3589  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3590  VT.getScalarType(), Ex, Sh));
3591  }
3592 
3593  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3594  ReplaceNode(SDValue(Node, 0), Result);
3595  break;
3596  }
3598  case ISD::GlobalAddress:
3599  case ISD::GlobalTLSAddress:
3600  case ISD::ExternalSymbol:
3601  case ISD::ConstantPool:
3602  case ISD::JumpTable:
3605  case ISD::INTRINSIC_VOID:
3606  // FIXME: Custom lowering for these operations shouldn't return null!
3607  break;
3608  }
3609 
3610  // Replace the original node with the legalized result.
3611  if (Results.empty()) {
3612  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3613  return false;
3614  }
3615 
3616  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3617  ReplaceNode(Node, Results.data());
3618  return true;
3619 }
3620 
3621 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3622  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3624  SDLoc dl(Node);
3625  // FIXME: Check flags on the node to see if we can use a finite call.
3626  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3627  unsigned Opc = Node->getOpcode();
3628  switch (Opc) {
3629  case ISD::ATOMIC_FENCE: {
3630  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3631  // FIXME: handle "fence singlethread" more efficiently.
3633 
3635  CLI.setDebugLoc(dl)
3636  .setChain(Node->getOperand(0))
3637  .setLibCallee(
3638  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3639  DAG.getExternalSymbol("__sync_synchronize",
3640  TLI.getPointerTy(DAG.getDataLayout())),
3641  std::move(Args));
3642 
3643  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3644 
3645  Results.push_back(CallResult.second);
3646  break;
3647  }
3648  // By default, atomic intrinsics are marked Legal and lowered. Targets
3649  // which don't support them directly, however, may want libcalls, in which
3650  // case they mark them Expand, and we get here.
3651  case ISD::ATOMIC_SWAP:
3652  case ISD::ATOMIC_LOAD_ADD:
3653  case ISD::ATOMIC_LOAD_SUB:
3654  case ISD::ATOMIC_LOAD_AND:
3655  case ISD::ATOMIC_LOAD_CLR:
3656  case ISD::ATOMIC_LOAD_OR:
3657  case ISD::ATOMIC_LOAD_XOR:
3658  case ISD::ATOMIC_LOAD_NAND:
3659  case ISD::ATOMIC_LOAD_MIN:
3660  case ISD::ATOMIC_LOAD_MAX:
3661  case ISD::ATOMIC_LOAD_UMIN:
3662  case ISD::ATOMIC_LOAD_UMAX:
3663  case ISD::ATOMIC_CMP_SWAP: {
3664  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3665  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3666  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3667 
3668  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3669  Results.push_back(Tmp.first);
3670  Results.push_back(Tmp.second);
3671  break;
3672  }
3673  case ISD::TRAP: {
3674  // If this operation is not supported, lower it to 'abort()' call
3677  CLI.setDebugLoc(dl)
3678  .setChain(Node->getOperand(0))
3679  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3680  DAG.getExternalSymbol(
3681  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3682  std::move(Args));
3683  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3684 
3685  Results.push_back(CallResult.second);
3686  break;
3687  }
3688  case ISD::FMINNUM:
3689  case ISD::STRICT_FMINNUM:
3690  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3691  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3692  RTLIB::FMIN_PPCF128));
3693  break;
3694  case ISD::FMAXNUM:
3695  case ISD::STRICT_FMAXNUM:
3696  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3697  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3698  RTLIB::FMAX_PPCF128));
3699  break;
3700  case ISD::FSQRT:
3701  case ISD::STRICT_FSQRT:
3702  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3703  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3704  RTLIB::SQRT_PPCF128));
3705  break;
3706  case ISD::FCBRT:
3707  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3708  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3709  RTLIB::CBRT_PPCF128));
3710  break;
3711  case ISD::FSIN:
3712  case ISD::STRICT_FSIN:
3713  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3714  RTLIB::SIN_F80, RTLIB::SIN_F128,
3715  RTLIB::SIN_PPCF128));
3716  break;
3717  case ISD::FCOS:
3718  case ISD::STRICT_FCOS:
3719  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3720  RTLIB::COS_F80, RTLIB::COS_F128,
3721  RTLIB::COS_PPCF128));
3722  break;
3723  case ISD::FSINCOS:
3724  // Expand into sincos libcall.
3725  ExpandSinCosLibCall(Node, Results);
3726  break;
3727  case ISD::FLOG:
3728  case ISD::STRICT_FLOG:
3729  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3730  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3731  RTLIB::LOG_FINITE_F64,
3732  RTLIB::LOG_FINITE_F80,
3733  RTLIB::LOG_FINITE_F128,
3734  RTLIB::LOG_FINITE_PPCF128));
3735  else
3736  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3737  RTLIB::LOG_F80, RTLIB::LOG_F128,
3738  RTLIB::LOG_PPCF128));
3739  break;
3740  case ISD::FLOG2:
3741  case ISD::STRICT_FLOG2:
3742  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3743  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3744  RTLIB::LOG2_FINITE_F64,
3745  RTLIB::LOG2_FINITE_F80,
3746  RTLIB::LOG2_FINITE_F128,
3747  RTLIB::LOG2_FINITE_PPCF128));
3748  else
3749  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3750  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3751  RTLIB::LOG2_PPCF128));
3752  break;
3753  case ISD::FLOG10:
3754  case ISD::STRICT_FLOG10:
3755  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3756  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3757  RTLIB::LOG10_FINITE_F64,
3758  RTLIB::LOG10_FINITE_F80,
3759  RTLIB::LOG10_FINITE_F128,
3760  RTLIB::LOG10_FINITE_PPCF128));
3761  else
3762  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3763  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3764  RTLIB::LOG10_PPCF128));
3765  break;
3766  case ISD::FEXP:
3767  case ISD::STRICT_FEXP:
3768  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3769  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3770  RTLIB::EXP_FINITE_F64,
3771  RTLIB::EXP_FINITE_F80,
3772  RTLIB::EXP_FINITE_F128,
3773  RTLIB::EXP_FINITE_PPCF128));
3774  else
3775  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3776  RTLIB::EXP_F80, RTLIB::EXP_F128,
3777  RTLIB::EXP_PPCF128));
3778  break;
3779  case ISD::FEXP2:
3780  case ISD::STRICT_FEXP2:
3781  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3782  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3783  RTLIB::EXP2_FINITE_F64,
3784  RTLIB::EXP2_FINITE_F80,
3785  RTLIB::EXP2_FINITE_F128,
3786  RTLIB::EXP2_FINITE_PPCF128));
3787  else
3788  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3789  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3790  RTLIB::EXP2_PPCF128));
3791  break;
3792  case ISD::FTRUNC:
3793  case ISD::STRICT_FTRUNC:
3794  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3795  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3796  RTLIB::TRUNC_PPCF128));
3797  break;
3798  case ISD::FFLOOR:
3799  case ISD::STRICT_FFLOOR:
3800  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3801  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3802  RTLIB::FLOOR_PPCF128));
3803  break;
3804  case ISD::FCEIL:
3805  case ISD::STRICT_FCEIL:
3806  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3807  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3808  RTLIB::CEIL_PPCF128));
3809  break;
3810  case ISD::FRINT:
3811  case ISD::STRICT_FRINT:
3812  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3813  RTLIB::RINT_F80, RTLIB::RINT_F128,
3814  RTLIB::RINT_PPCF128));
3815  break;
3816  case ISD::FNEARBYINT:
3818  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3819  RTLIB::NEARBYINT_F64,
3820  RTLIB::NEARBYINT_F80,
3821  RTLIB::NEARBYINT_F128,
3822  RTLIB::NEARBYINT_PPCF128));
3823  break;
3824  case ISD::FROUND:
3825  case ISD::STRICT_FROUND:
3826  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3827  RTLIB::ROUND_F64,
3828  RTLIB::ROUND_F80,
3829  RTLIB::ROUND_F128,
3830  RTLIB::ROUND_PPCF128));
3831  break;
3832  case ISD::FPOWI:
3833  case ISD::STRICT_FPOWI:
3834  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3835  RTLIB::POWI_F80, RTLIB::POWI_F128,
3836  RTLIB::POWI_PPCF128));
3837  break;
3838  case ISD::FPOW:
3839  case ISD::STRICT_FPOW:
3840  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3841  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3842  RTLIB::POW_FINITE_F64,
3843  RTLIB::POW_FINITE_F80,
3844  RTLIB::POW_FINITE_F128,
3845  RTLIB::POW_FINITE_PPCF128));
3846  else
3847  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3848  RTLIB::POW_F80, RTLIB::POW_F128,
3849  RTLIB::POW_PPCF128));
3850  break;
3851  case ISD::FDIV:
3852  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3853  RTLIB::DIV_F80, RTLIB::DIV_F128,
3854  RTLIB::DIV_PPCF128));
3855  break;
3856  case ISD::FREM:
3857  case ISD::STRICT_FREM:
3858  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3859  RTLIB::REM_F80, RTLIB::REM_F128,
3860  RTLIB::REM_PPCF128));
3861  break;
3862  case ISD::FMA:
3863  case ISD::STRICT_FMA:
3864  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3865  RTLIB::FMA_F80, RTLIB::FMA_F128,
3866  RTLIB::FMA_PPCF128));
3867  break;
3868  case ISD::FADD:
3869  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3870  RTLIB::ADD_F80, RTLIB::ADD_F128,
3871  RTLIB::ADD_PPCF128));
3872  break;
3873  case ISD::FMUL:
3874  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3875  RTLIB::MUL_F80, RTLIB::MUL_F128,
3876  RTLIB::MUL_PPCF128));
3877  break;
3878  case ISD::FP16_TO_FP:
3879  if (Node->getValueType(0) == MVT::f32) {
3880  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3881  }
3882  break;
3883  case ISD::FP_TO_FP16: {
3884  RTLIB::Libcall LC =
3886  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3887  Results.push_back(ExpandLibCall(LC, Node, false));
3888  break;
3889  }
3890  case ISD::FSUB:
3891  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3892  RTLIB::SUB_F80, RTLIB::SUB_F128,
3893  RTLIB::SUB_PPCF128));
3894  break;
3895  case ISD::SREM:
3896  Results.push_back(ExpandIntLibCall(Node, true,
3897  RTLIB::SREM_I8,
3898  RTLIB::SREM_I16, RTLIB::SREM_I32,
3899  RTLIB::SREM_I64, RTLIB::SREM_I128));
3900  break;
3901  case ISD::UREM:
3902  Results.push_back(ExpandIntLibCall(Node, false,
3903  RTLIB::UREM_I8,
3904  RTLIB::UREM_I16, RTLIB::UREM_I32,
3905  RTLIB::UREM_I64, RTLIB::UREM_I128));
3906  break;
3907  case ISD::SDIV:
3908  Results.push_back(ExpandIntLibCall(Node, true,
3909  RTLIB::SDIV_I8,
3910  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3911  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
3912  break;
3913  case ISD::UDIV:
3914  Results.push_back(ExpandIntLibCall(Node, false,
3915  RTLIB::UDIV_I8,
3916  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3917  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
3918  break;
3919  case ISD::SDIVREM:
3920  case ISD::UDIVREM:
3921  // Expand into divrem libcall
3922  ExpandDivRemLibCall(Node, Results);
3923  break;
3924  case ISD::MUL:
3925  Results.push_back(ExpandIntLibCall(Node, false,
3926  RTLIB::MUL_I8,
3927  RTLIB::MUL_I16, RTLIB::MUL_I32,
3928  RTLIB::MUL_I64, RTLIB::MUL_I128));
3929  break;
3930  case ISD::CTLZ_ZERO_UNDEF:
3931  switch (Node->getSimpleValueType(0).SimpleTy) {
3932  default:
3933  llvm_unreachable("LibCall explicitly requested, but not available");
3934  case MVT::i32:
3935  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
3936  break;
3937  case MVT::i64:
3938  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
3939  break;
3940  case MVT::i128:
3941  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
3942  break;
3943  }
3944  break;
3945  }
3946 
3947  // Replace the original node with the legalized result.
3948  if (!Results.empty()) {
3949  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
3950  ReplaceNode(Node, Results.data());
3951  } else
3952  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
3953 }
3954 
3955 // Determine the vector type to use in place of an original scalar element when
3956 // promoting equally sized vectors.
3958  MVT EltVT, MVT NewEltVT) {
3959  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
3960  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
3961  assert(TLI.isTypeLegal(MidVT) && "unexpected");
3962  return MidVT;
3963 }
3964 
3965 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3966  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
3968  MVT OVT = Node->getSimpleValueType(0);
3969  if (Node->getOpcode() == ISD::UINT_TO_FP ||
3970  Node->getOpcode() == ISD::SINT_TO_FP ||
3971  Node->getOpcode() == ISD::SETCC ||
3972  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
3973  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
3974  OVT = Node->getOperand(0).getSimpleValueType();
3975  }
3976  if (Node->getOpcode() == ISD::BR_CC)
3977  OVT = Node->getOperand(2).getSimpleValueType();
3978  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3979  SDLoc dl(Node);
3980  SDValue Tmp1, Tmp2, Tmp3;
3981  switch (Node->getOpcode()) {
3982  case ISD::CTTZ:
3983  case ISD::CTTZ_ZERO_UNDEF:
3984  case ISD::CTLZ:
3985  case ISD::CTLZ_ZERO_UNDEF:
3986  case ISD::CTPOP:
3987  // Zero extend the argument.
3988  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3989  if (Node->getOpcode() == ISD::CTTZ) {
3990  // The count is the same in the promoted type except if the original
3991  // value was zero. This can be handled by setting the bit just off
3992  // the top of the original type.
3993  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
3994  OVT.getSizeInBits());
3995  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
3996  DAG.getConstant(TopBit, dl, NVT));
3997  }
3998  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3999  // already the correct result.
4000  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4001  if (Node->getOpcode() == ISD::CTLZ ||
4002  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4003  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4004  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4005  DAG.getConstant(NVT.getSizeInBits() -
4006  OVT.getSizeInBits(), dl, NVT));
4007  }
4008  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4009  break;
4010  case ISD::BITREVERSE:
4011  case ISD::BSWAP: {
4012  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4013  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4014  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4015  Tmp1 = DAG.getNode(
4016  ISD::SRL, dl, NVT, Tmp1,
4017  DAG.getConstant(DiffBits, dl,
4018  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4019 
4020  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4021  break;
4022  }
4023  case ISD::FP_TO_UINT:
4024  case ISD::FP_TO_SINT:
4025  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4026  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4027  Results.push_back(Tmp1);
4028  break;
4029  case ISD::UINT_TO_FP:
4030  case ISD::SINT_TO_FP:
4031  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4032  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4033  Results.push_back(Tmp1);
4034  break;
4035  case ISD::VAARG: {
4036  SDValue Chain = Node->getOperand(0); // Get the chain.
4037  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4038 
4039  unsigned TruncOp;
4040  if (OVT.isVector()) {
4041  TruncOp = ISD::BITCAST;
4042  } else {
4043  assert(OVT.isInteger()
4044  && "VAARG promotion is supported only for vectors or integer types");
4045  TruncOp = ISD::TRUNCATE;
4046  }
4047 
4048  // Perform the larger operation, then convert back
4049  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4050  Node->getConstantOperandVal(3));
4051  Chain = Tmp1.getValue(1);
4052 
4053  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4054 
4055  // Modified the chain result - switch anything that used the old chain to
4056  // use the new one.
4057  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4058  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4059  if (UpdatedNodes) {
4060  UpdatedNodes->insert(Tmp2.getNode());
4061  UpdatedNodes->insert(Chain.getNode());
4062  }
4063  ReplacedNode(Node);
4064  break;
4065  }
4066  case ISD::MUL:
4067  case ISD::SDIV:
4068  case ISD::SREM:
4069  case ISD::UDIV:
4070  case ISD::UREM:
4071  case ISD::AND:
4072  case ISD::OR:
4073  case ISD::XOR: {
4074  unsigned ExtOp, TruncOp;
4075  if (OVT.isVector()) {
4076  ExtOp = ISD::BITCAST;
4077  TruncOp = ISD::BITCAST;
4078  } else {
4079  assert(OVT.isInteger() && "Cannot promote logic operation");
4080 
4081  switch (Node->getOpcode()) {
4082  default:
4083  ExtOp = ISD::ANY_EXTEND;
4084  break;
4085  case ISD::SDIV:
4086  case ISD::SREM:
4087  ExtOp = ISD::SIGN_EXTEND;
4088  break;
4089  case ISD::UDIV:
4090  case ISD::UREM:
4091  ExtOp = ISD::ZERO_EXTEND;
4092  break;
4093  }
4094  TruncOp = ISD::TRUNCATE;
4095  }
4096  // Promote each of the values to the new type.
4097  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4098  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4099  // Perform the larger operation, then convert back
4100  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4101  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4102  break;
4103  }
4104  case ISD::UMUL_LOHI:
4105  case ISD::SMUL_LOHI: {
4106  // Promote to a multiply in a wider integer type.
4107  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4108  : ISD::SIGN_EXTEND;
4109  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4110  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4111  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4112 
4113  auto &DL = DAG.getDataLayout();
4114  unsigned OriginalSize = OVT.getScalarSizeInBits();
4115  Tmp2 = DAG.getNode(
4116  ISD::SRL, dl, NVT, Tmp1,
4117  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4118  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4119  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4120  break;
4121  }
4122  case ISD::SELECT: {
4123  unsigned ExtOp, TruncOp;
4124  if (Node->getValueType(0).isVector() ||
4125  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4126  ExtOp = ISD::BITCAST;
4127  TruncOp = ISD::BITCAST;
4128  } else if (Node->getValueType(0).isInteger()) {
4129  ExtOp = ISD::ANY_EXTEND;
4130  TruncOp = ISD::TRUNCATE;
4131  } else {
4132  ExtOp = ISD::FP_EXTEND;
4133  TruncOp = ISD::FP_ROUND;
4134  }
4135  Tmp1 = Node->getOperand(0);
4136  // Promote each of the values to the new type.
4137  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4138  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4139  // Perform the larger operation, then round down.
4140  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4141  if (TruncOp != ISD::FP_ROUND)
4142  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4143  else
4144  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4145  DAG.getIntPtrConstant(0, dl));
4146  Results.push_back(Tmp1);
4147  break;
4148  }
4149  case ISD::VECTOR_SHUFFLE: {
4150  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4151 
4152  // Cast the two input vectors.
4153  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4154  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4155 
4156  // Convert the shuffle mask to the right # elements.
4157  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4158  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4159  Results.push_back(Tmp1);
4160  break;
4161  }
4162  case ISD::SETCC: {
4163  unsigned ExtOp = ISD::FP_EXTEND;
4164  if (NVT.isInteger()) {
4165  ISD::CondCode CCCode =
4166  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4168  }
4169  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4170  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4171  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4172  Tmp1, Tmp2, Node->getOperand(2)));
4173  break;
4174  }
4175  case ISD::BR_CC: {
4176  unsigned ExtOp = ISD::FP_EXTEND;
4177  if (NVT.isInteger()) {
4178  ISD::CondCode CCCode =
4179  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4181  }
4182  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4183  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4184  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4185  Node->getOperand(0), Node->getOperand(1),
4186  Tmp1, Tmp2, Node->getOperand(4)));
4187  break;
4188  }
4189  case ISD::FADD:
4190  case ISD::FSUB:
4191  case ISD::FMUL:
4192  case ISD::FDIV:
4193  case ISD::FREM:
4194  case ISD::FMINNUM:
4195  case ISD::FMAXNUM:
4196  case ISD::FPOW:
4197  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4198  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4199  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4200  Node->getFlags());
4201  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4202  Tmp3, DAG.getIntPtrConstant(0, dl)));
4203  break;
4204  case ISD::FMA:
4205  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4206  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4207  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4208  Results.push_back(
4209  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4210  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4211  DAG.getIntPtrConstant(0, dl)));
4212  break;
4213  case ISD::FCOPYSIGN:
4214  case ISD::FPOWI: {
4215  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4216  Tmp2 = Node->getOperand(1);
4217  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4218 
4219  // fcopysign doesn't change anything but the sign bit, so
4220  // (fp_round (fcopysign (fpext a), b))
4221  // is as precise as
4222  // (fp_round (fpext a))
4223  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4224  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4225  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4226  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4227  break;
4228  }
4229  case ISD::FFLOOR:
4230  case ISD::FCEIL:
4231  case ISD::FRINT:
4232  case ISD::FNEARBYINT:
4233  case ISD::FROUND:
4234  case ISD::FTRUNC:
4235  case ISD::FNEG:
4236  case ISD::FSQRT:
4237  case ISD::FSIN:
4238  case ISD::FCOS:
4239  case ISD::FLOG:
4240  case ISD::FLOG2:
4241  case ISD::FLOG10:
4242  case ISD::FABS:
4243  case ISD::FEXP:
4244  case ISD::FEXP2:
4245  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4246  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4247  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4248  Tmp2, DAG.getIntPtrConstant(0, dl)));
4249  break;
4250  case ISD::BUILD_VECTOR: {
4251  MVT EltVT = OVT.getVectorElementType();
4252  MVT NewEltVT = NVT.getVectorElementType();
4253 
4254  // Handle bitcasts to a different vector type with the same total bit size
4255  //
4256  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4257  // =>
4258  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4259 
4260  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4261  "Invalid promote type for build_vector");
4262  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4263 
4264  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4265 
4266  SmallVector<SDValue, 8> NewOps;
4267  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4268  SDValue Op = Node->getOperand(I);
4269  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4270  }
4271 
4272  SDLoc SL(Node);
4273  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4274  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4275  Results.push_back(CvtVec);
4276  break;
4277  }
4278  case ISD::EXTRACT_VECTOR_ELT: {
4279  MVT EltVT = OVT.getVectorElementType();
4280  MVT NewEltVT = NVT.getVectorElementType();
4281 
4282  // Handle bitcasts to a different vector type with the same total bit size.
4283  //
4284  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4285  // =>
4286  // v4i32:castx = bitcast x:v2i64
4287  //
4288  // i64 = bitcast
4289  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4290  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4291  //
4292 
4293  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4294  "Invalid promote type for extract_vector_elt");
4295  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4296 
4297  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4298  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4299 
4300  SDValue Idx = Node->getOperand(1);
4301  EVT IdxVT = Idx.getValueType();
4302  SDLoc SL(Node);
4303  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4304  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4305 
4306  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4307 
4308  SmallVector<SDValue, 8> NewOps;
4309  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4310  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4311  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4312 
4313  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4314  CastVec, TmpIdx);
4315  NewOps.push_back(Elt);
4316  }
4317 
4318  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4319  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4320  break;
4321  }
4322  case ISD::INSERT_VECTOR_ELT: {
4323  MVT EltVT = OVT.getVectorElementType();
4324  MVT NewEltVT = NVT.getVectorElementType();
4325 
4326  // Handle bitcasts to a different vector type with the same total bit size
4327  //
4328  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4329  // =>
4330  // v4i32:castx = bitcast x:v2i64
4331  // v2i32:casty = bitcast y:i64
4332  //
4333  // v2i64 = bitcast
4334  // (v4i32 insert_vector_elt
4335  // (v4i32 insert_vector_elt v4i32:castx,
4336  // (extract_vector_elt casty, 0), 2 * z),
4337  // (extract_vector_elt casty, 1), (2 * z + 1))
4338 
4339  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4340  "Invalid promote type for insert_vector_elt");
4341  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4342 
4343  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4344  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4345 
4346  SDValue Val = Node->getOperand(1);
4347  SDValue Idx = Node->getOperand(2);
4348  EVT IdxVT = Idx.getValueType();
4349  SDLoc SL(Node);
4350 
4351  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4352  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4353 
4354  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4355  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4356 
4357  SDValue NewVec = CastVec;
4358  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4359  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4360  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4361 
4362  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4363  CastVal, IdxOffset);
4364 
4365  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4366  NewVec, Elt, InEltIdx);
4367  }
4368 
4369  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4370  break;
4371  }
4372  case ISD::SCALAR_TO_VECTOR: {
4373  MVT EltVT = OVT.getVectorElementType();
4374  MVT NewEltVT = NVT.getVectorElementType();
4375 
4376  // Handle bitcasts to different vector type with the same total bit size.
4377  //
4378  // e.g. v2i64 = scalar_to_vector x:i64
4379  // =>
4380  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4381  //
4382 
4383  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4384  SDValue Val = Node->getOperand(0);
4385  SDLoc SL(Node);
4386 
4387  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4388  SDValue Undef = DAG.getUNDEF(MidVT);
4389 
4390  SmallVector<SDValue, 8> NewElts;
4391  NewElts.push_back(CastVal);
4392  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4393  NewElts.push_back(Undef);
4394 
4395  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4396  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4397  Results.push_back(CvtVec);
4398  break;
4399  }
4400  case ISD::ATOMIC_SWAP: {
4401  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4402  SDLoc SL(Node);
4403  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4404  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4405  "unexpected promotion type");
4406  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4407  "unexpected atomic_swap with illegal type");
4408 
4409  SDValue NewAtomic
4410  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4411  DAG.getVTList(NVT, MVT::Other),
4412  { AM->getChain(), AM->getBasePtr(), CastVal },
4413  AM->getMemOperand());
4414  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4415  Results.push_back(NewAtomic.getValue(1));
4416  break;
4417  }
4418  }
4419 
4420  // Replace the original node with the legalized result.
4421  if (!Results.empty()) {
4422  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4423  ReplaceNode(Node, Results.data());
4424  } else
4425  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4426 }
4427 
4428 /// This is the entry point for the file.
4430  AssignTopologicalOrder();
4431 
4432  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4433  // Use a delete listener to remove nodes which were deleted during
4434  // legalization from LegalizeNodes. This is needed to handle the situation
4435  // where a new node is allocated by the object pool to the same address of a
4436  // previously deleted node.
4437  DAGNodeDeletedListener DeleteListener(
4438  *this,
4439  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4440 
4441  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4442 
4443  // Visit all the nodes. We start in topological order, so that we see
4444  // nodes with their original operands intact. Legalization can produce
4445  // new nodes which may themselves need to be legalized. Iterate until all
4446  // nodes have been legalized.
4447  while (true) {
4448  bool AnyLegalized = false;
4449  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4450  --NI;
4451 
4452  SDNode *N = &*NI;
4453  if (N->use_empty() && N != getRoot().getNode()) {
4454  ++NI;
4455  DeleteNode(N);
4456  continue;
4457  }
4458 
4459  if (LegalizedNodes.insert(N).second) {
4460  AnyLegalized = true;
4461  Legalizer.LegalizeOp(N);
4462 
4463  if (N->use_empty() && N != getRoot().getNode()) {
4464  ++NI;
4465  DeleteNode(N);
4466  }
4467  }
4468  }
4469  if (!AnyLegalized)
4470  break;
4471 
4472  }
4473 
4474  // Remove dead nodes now.
4475  RemoveDeadNodes();
4476 }
4477 
4479  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4480  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4481  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4482 
4483  // Directly insert the node in question, and legalize it. This will recurse
4484  // as needed through operands.
4485  LegalizedNodes.insert(N);
4486  Legalizer.LegalizeOp(N);
4487 
4488  return LegalizedNodes.count(N);
4489 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:768
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1678
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:537
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:883
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:295
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:357
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:651
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:366
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
const SDValue & getVal() const
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:703
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:806
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:288
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:176
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:383
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:253
void reserve(size_type N)
Definition: SmallVector.h:368
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:352
The address of the GOT.
Definition: ISDOpcodes.h:65
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:785
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:113
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:455
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:409
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:201
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:392
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:545
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:717
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:95
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:814
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:400
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:699
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:90
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:117
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:401
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
CallLoweringInfo & setZExtResult(bool Value=true)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:851
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:965
op_iterator op_begin() const
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:751
static bool useSinCos(SDNode *Node)
Only issue sincos libcall if both sin and cos are needed.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:998
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MVT getVectorElementType() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getBasePtr() const
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:234
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:84
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
void Legalize()
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction s...
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void swap(SmallVectorImpl &RHS)
Definition: SmallVector.h:670
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
PowerPC Reduce CR logical Operation
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:732
iterator_range< value_op_iterator > op_values() const
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:940
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:331
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:370
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
Definition: APInt.h:587
size_type size() const
Definition: SmallSet.h:159
This file declares a class to represent arbitrary precision floating point values and provide a varie...
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:160
This class provides iterator support for SDUse operands that use a specific SDNode.
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:762
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using &#39;From&#39; to use &#39;To&#39; instead.